From 65fb38bbcf3c6dcbeea04be76ad47e11e595da77 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 18 Mar 2013 21:10:08 +0000 Subject: [PATCH] Add support for ram vectors to the ARMv7-M architecture git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5756 42af7a65-404d-4744-a932-0658087f49c3 --- arch/Kconfig | 12 ++ arch/arm/Kconfig | 2 + arch/arm/src/armv7-m/ram_vectors.h | 123 +++++++++++++++++++ arch/arm/src/armv7-m/up_ramvec_attach.c | 125 ++++++++++++++++++++ arch/arm/src/armv7-m/up_ramvec_initialize.c | 124 +++++++++++++++++++ arch/arm/src/kinetis/Make.defs | 4 + arch/arm/src/kinetis/kinetis_irq.c | 9 ++ arch/arm/src/lm/Make.defs | 4 + arch/arm/src/lm/lm_irq.c | 9 ++ arch/arm/src/lpc17xx/Make.defs | 4 + arch/arm/src/lpc17xx/lpc17_irq.c | 9 ++ arch/arm/src/lpc43xx/Make.defs | 6 +- arch/arm/src/lpc43xx/lpc43_irq.c | 8 ++ arch/arm/src/sam3u/Make.defs | 4 + arch/arm/src/sam3u/sam3u_irq.c | 11 +- arch/arm/src/stm32/Make.defs | 4 + arch/arm/src/stm32/stm32_irq.c | 8 +- 17 files changed, 462 insertions(+), 4 deletions(-) create mode 100644 arch/arm/src/armv7-m/ram_vectors.h create mode 100644 arch/arm/src/armv7-m/up_ramvec_attach.c create mode 100644 arch/arm/src/armv7-m/up_ramvec_initialize.c diff --git a/arch/Kconfig b/arch/Kconfig index 44c030fe0c..55f81aa698 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -300,6 +300,18 @@ config ARCH_RAMFUNCS so that FLASH can be reconfigured while the MCU executes out of SRAM. +config ARCH_HAVE_RAMVECTORS + bool + default n + +config ARCH_RAMVECTORS + bool "Support RAM interrupt vectors" + default n + depends on ARCH_HAVE_RAMVECTORS + ---help--- + If ARCH_RAMVECTORS is defined, then the architecture will support + modifiable vectors in a RAM-based vector table. + comment "Board Settings" config BOARD_LOOPSPERMSEC diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a5e24e29a9..63151fdc71 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -143,10 +143,12 @@ config ARCH_CORTEXM0 config ARCH_CORTEXM3 bool select ARCH_IRQPRIO + select ARCH_HAVE_RAMVECTORS config ARCH_CORTEXM4 bool select ARCH_IRQPRIO + select ARCH_HAVE_RAMVECTORS config ARCH_FAMILY string diff --git a/arch/arm/src/armv7-m/ram_vectors.h b/arch/arm/src/armv7-m/ram_vectors.h new file mode 100644 index 0000000000..4cbe42d8c4 --- /dev/null +++ b/arch/arm/src/armv7-m/ram_vectors.h @@ -0,0 +1,123 @@ +/************************************************************************************ + * arch/arm/src/armv7-m/ram_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_RAM_VECTORS_H +#define __ARCH_ARM_SRC_COMMON_ARMV7_M_RAM_VECTORS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* If CONFIG_ARMV7M_CMNVECTOR is defined then the number of peripheral interrupts + * is provided in chip.h. + */ + +#include "chip.h" +#include "up_internal.h" + +#ifdef CONFIG_ARCH_RAMVECTORS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* This logic currently only works if CONFIG_ARMV7M_CMNVECTOR is defined. That is + * because CONFIG_ARMV7M_CMNVECTOR is needed to induce chip.h into giving us the + * number of peripheral interrupts. "Oh want a tangled web we weave..." + */ + +#ifndef CONFIG_ARMV7M_CMNVECTOR +# error "This logic requires CONFIG_ARMV7M_CMNVECTOR" +#endif + +/* This, then is the size of the vector table (in 4-byte entries). This size + * includes the IDLE stack pointer which lies at the beginning of + * the table. + */ + +#define ARMV7M_VECTAB_SIZE (ARMV7M_PERIPHERAL_INTERRUPTS) + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide + * ARM-specific implementations of irq_initialize(), irq_attach(), and + * irq_dispatch. In this case, it is also assumed that the ARM vector + * table resides in RAM, has the the name up_ram_vectors, and has been + * properly positioned and aligned in memory by the linker script. + */ + +extern up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE] + __attribute__((section(".ram_vectors"))); + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/**************************************************************************** + * Name: up_ramvec_initialize + * + * Description: + * Copy vectors to RAM an configure the NVIC to use the RAM vectors. + * + ****************************************************************************/ + +void up_ramvec_initialize(void); + +/**************************************************************************** + * Name: exception_common + * + * Description: + * This is the default, common vector handling entrypoint. + * + ****************************************************************************/ + +void exception_common(void); + +/**************************************************************************** + * Name: up_ramvec_attach + * + * Description: + * Configure the ram vector table so that IRQ number 'irq' will be + * dipatched by hardware to 'vector' + * + ****************************************************************************/ + +int up_ramvec_attach(int irq, up_vector_t vector); + +#endif /* CONFIG_ARCH_RAMVECTORS */ +#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_RAM_VECTORS_H */ diff --git a/arch/arm/src/armv7-m/up_ramvec_attach.c b/arch/arm/src/armv7-m/up_ramvec_attach.c new file mode 100644 index 0000000000..605886352f --- /dev/null +++ b/arch/arm/src/armv7-m/up_ramvec_attach.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/irq/up_ramvec_attach.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "ram_vectors.h" + +#ifdef CONFIG_ARCH_RAMVECTORS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Type Declarations + ****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Common exception entrypoint */ + +void exception_common(void); + +/**************************************************************************** + * Name: up_ramvec_attach + * + * Description: + * Configure the ram vector table so that IRQ number 'irq' will be + * dipatched by hardware to 'vector' + * + ****************************************************************************/ + +int up_ramvec_attach(int irq, up_vector_t vector) +{ + int ret = ERROR; + + if ((unsigned)irq < ARMV7M_PERIPHERAL_INTERRUPTS) + { + irqstate_t flags; + + /* If the new vector is NULL, then the vector is being detached. In + * this case, disable the itnerrupt and direct any interrupts to the + * common exception handler. + */ + + flags = irqsave(); + if (vector == NULL) + { + /* Disable the interrupt if we can before detaching it. We might + * not be able to do this for all interrupts. + */ + + up_disable_irq(irq); + + /* Detaching the vector really means re-attaching it to the + * common exception handler. + */ + + vector = exception_common; + } + + /* Save the new vector in the vector table. */ + + g_ram_vectors[irq] = vector; + irqrestore(flags); + ret = OK; + } + + return ret; +} + +#endif /* !CONFIG_ARCH_RAMVECTORS */ diff --git a/arch/arm/src/armv7-m/up_ramvec_initialize.c b/arch/arm/src/armv7-m/up_ramvec_initialize.c new file mode 100644 index 0000000000..8ad4920c9e --- /dev/null +++ b/arch/arm/src/armv7-m/up_ramvec_initialize.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * arm/arm/src/armv7-m/up_ramvec_initialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "up_arch.h" +#include "up_internal.h" + +#ifdef CONFIG_ARCH_RAMVECTORS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Type Declarations + ****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide + * ARM-specific implementations of up_ramvec_initialize(), irq_attach(), and + * irq_dispatch. In this case, it is also assumed that the ARM vector + * table resides in RAM, has the the name up_ram_vectors, and has been + * properly positioned and aligned in memory by the linker script. + */ + +up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE] + __attribute__((section(".ram_vectors"))); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_ramvec_initialize + * + * Description: + * Copy vectors to RAM an configure the NVIC to use the RAM vectors. + * + ****************************************************************************/ + +void up_ramvec_initialize(void) +{ + const up_vector_t *src; + up_vector_t *dest; + int i; + + /* The vector table must be aligned */ + + DEBUGASSERT(((uintptr)g_ram_vectors & 0x3f) == 0); + + /* Copy the ROM vector table at address zero to RAM vector table. + * + * This must be done BEFORE the MPU is enable if the MPU is being used to + * protect against NULL pointer references. + */ + + src = (const CODE up_vector_t *)0; + dest = g_ram_vectors; + + for (i = 0; i < ARMV7M_VECTAB_SIZE; i++) + { + *dest++ = *src++; + } + + /* Now configure the NVIC to use the new vector table. Bit 29 indicates + * that the vector table is in RAM. + */ + + putreg32((uint32_t)g_ram_vectors | (1 << 29), NVIC_VECTAB); +} + +#endif /* !CONFIG_ARCH_RAMVECTORS */ diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index e417465478..1bfb8803e4 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -50,6 +50,10 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c \ up_vfork.c +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S endif diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index b0aea55d15..f651c9e5d6 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -48,6 +48,7 @@ #include #include "nvic.h" +#include "ram_vectors.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" @@ -322,6 +323,14 @@ void up_irqinitialize(void) putreg32(0, NVIC_IRQ64_95_ENABLE); putreg32(0, NVIC_IRQ96_127_ENABLE); + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + +#ifdef CONFIG_ARCH_RAMVECTORS + up_ramvec_initialize(); +#endif + /* Set all interrrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); diff --git a/arch/arm/src/lm/Make.defs b/arch/arm/src/lm/Make.defs index e760f7e014..cb367e8795 100644 --- a/arch/arm/src/lm/Make.defs +++ b/arch/arm/src/lm/Make.defs @@ -46,6 +46,10 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ up_vfork.c +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S endif diff --git a/arch/arm/src/lm/lm_irq.c b/arch/arm/src/lm/lm_irq.c index d8c0852ed6..11ea6fbb61 100644 --- a/arch/arm/src/lm/lm_irq.c +++ b/arch/arm/src/lm/lm_irq.c @@ -48,6 +48,7 @@ #include #include "nvic.h" +#include "ram_vectors.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" @@ -292,6 +293,14 @@ void up_irqinitialize(void) putreg32(0, NVIC_IRQ0_31_ENABLE); putreg32(0, NVIC_IRQ32_63_ENABLE); + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + +#ifdef CONFIG_ARCH_RAMVECTORS + up_ramvec_initialize(); +#endif + /* Set all interrrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs index 2bedbf5b33..4691653872 100644 --- a/arch/arm/src/lpc17xx/Make.defs +++ b/arch/arm/src/lpc17xx/Make.defs @@ -59,6 +59,10 @@ CMN_ASRCS += up_exception.S CMN_CSRCS += up_vectors.c endif +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S endif diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index 6d96ff386c..80de4596c5 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -48,6 +48,7 @@ #include #include "nvic.h" +#include "ram_vectors.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" @@ -290,6 +291,14 @@ void up_irqinitialize(void) putreg32(0, NVIC_IRQ0_31_ENABLE); + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + +#ifdef CONFIG_ARCH_RAMVECTORS + up_ramvec_initialize(); +#endif + /* Set all interrrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index 9674196c5b..0354b698bc 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -51,8 +51,12 @@ CMN_ASRCS += up_exception.S CMN_CSRCS += up_vectors.c endif +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + ifeq ($(CONFIG_ARCH_MEMCPY),y) -CMN_ASRCS += up_memcpy.S +CMN_ASRCS += up_memcpy.S endif ifeq ($(CONFIG_DEBUG_STACK),y) diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index 6f49b3e38f..042b3360b8 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -49,6 +49,7 @@ #include "chip.h" #include "nvic.h" +#include "ram_vectors.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" @@ -309,9 +310,16 @@ void up_irqinitialize(void) * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. + * + * If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. */ +#ifdef CONFIG_ARCH_RAMVECTORS + up_ramvec_initialize(); +#else putreg32((uint32_t)_vectors, NVIC_VECTAB); +#endif /* Set all interrupts (and exceptions) to the default priority */ diff --git a/arch/arm/src/sam3u/Make.defs b/arch/arm/src/sam3u/Make.defs index 14cc68d493..16ca22401a 100644 --- a/arch/arm/src/sam3u/Make.defs +++ b/arch/arm/src/sam3u/Make.defs @@ -51,6 +51,10 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vfork.c # Configuration-dependent common files +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S endif diff --git a/arch/arm/src/sam3u/sam3u_irq.c b/arch/arm/src/sam3u/sam3u_irq.c index ed424f91d3..9c1e9bb3e4 100644 --- a/arch/arm/src/sam3u/sam3u_irq.c +++ b/arch/arm/src/sam3u/sam3u_irq.c @@ -48,6 +48,7 @@ #include #include "nvic.h" +#include "ram_vectors.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" @@ -280,9 +281,15 @@ void up_irqinitialize(void) putreg32(0, NVIC_IRQ0_31_ENABLE); - /* Set up the vector table address */ + /* Set up the vector table address. + * + * If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ -#ifdef CONFIG_SAM3U_DFU +#if defined(CONFIG_ARCH_RAMVECTORS) + up_ramvec_initialize(); +#elif defined(CONFIG_STM32_DFU) putreg32((uint32_t)sam3u_vectors, NVIC_VECTAB); #endif diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index aea8719b1f..d51c360fe1 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -56,6 +56,10 @@ CMN_ASRCS += up_exception.S CMN_CSRCS += up_vectors.c endif +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S endif diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index 79b8120e93..96b239c36b 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -48,6 +48,7 @@ #include #include "nvic.h" +#include "ram_vectors.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" @@ -302,9 +303,14 @@ void up_irqinitialize(void) * at address 0x0800:0000. If we are using the STMicro DFU bootloader, then * the vector table will be offset to a different location in FLASH and we * will need to set the NVIC vector location to this alternative location. + * + * If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. */ -#ifdef CONFIG_STM32_DFU +#if defined(CONFIG_ARCH_RAMVECTORS) + up_ramvec_initialize(); +#elif defined(CONFIG_STM32_DFU) putreg32((uint32_t)stm32_vectors, NVIC_VECTAB); #endif