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arch/risc-v: inline up_cpu_index if RISCV_PERCPU_SCRATCH is not enabled

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Inline the short function to provide better performance.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2024-12-30 11:22:03 +08:00 committed by Alan C. Assis
parent cd92e2d6e7
commit 6eb2f33278
2 changed files with 19 additions and 0 deletions
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17
arch/risc-v/include/irq.h
View file

@ -697,10 +697,27 @@ irqstate_t up_irq_enable(void);
* Description:
* Return the real core number regardless CONFIG_SMP setting
*
* When CONFIG_RISCV_PERCPU_SCRATCH is enabled, this uses the percpu
* scratch area to store the hart ID. This is needed when the CSR_MHARTID
* register may not contain the actual hart ID.
*
* When CONFIG_RISCV_PERCPU_SCRATCH is not enabled, this directly reads
* the CSR_MHARTID register. Use this version when you can guarantee
* CSR_MHARTID contains the actual hart ID. This is the default behavior
* that can be achieved by single instruction to provide better
* performance.
*
****************************************************************************/
#ifdef CONFIG_ARCH_HAVE_MULTICPU
#ifdef CONFIG_RISCV_PERCPU_SCRATCH
int up_cpu_index(void) noinstrument_function;
#else
noinstrument_function static inline int up_cpu_index(void)
{
return READ_CSR(CSR_MHARTID);
}
#endif
#endif /* CONFIG_ARCH_HAVE_MULTICPU */
/****************************************************************************

2
arch/risc-v/src/common/riscv_cpuindex.c
View file

@ -45,10 +45,12 @@
*
****************************************************************************/
#ifdef CONFIG_RISCV_PERCPU_SCRATCH
int up_cpu_index(void)
{
return (int)riscv_mhartid();
}
#endif
/****************************************************************************
* Name: up_this_cpu