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arch: arm: nxstyle fixes

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Fixes for nxstyle warnigs

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-04-08 18:38:34 +02:00 committed by Xiang Xiao
parent d2e7ea05c6
commit 8dcd16d5a6
10 changed files with 121 additions and 75 deletions
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4
arch/arm/src/common/arm_vfork.h
View file

@ -63,8 +63,8 @@ struct vfork_s
uint32_t r10; /* Volatile register r10 */
uint32_t fp; /* Frame pointer */
uint32_t sp; /* Stack pointer*/
uint32_t lr; /* Return address*/
uint32_t sp; /* Stack pointer */
uint32_t lr; /* Return address */
/* Floating point registers (not yet) */
};

10
arch/arm/src/moxart/moxart_16550.c
View file

@ -103,6 +103,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
*/
/* HARD: coded value for UART1 */
bitm_off = 1;
switch (cmd)
@ -125,9 +126,11 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Update mode register with requested mode */
vmode = getreg32(CONFIG_UART_MOXA_MODE_REG);
putreg32(vmode & ~(OP_MODE_MASK << 2 * bitm_off), CONFIG_UART_MOXA_MODE_REG);
putreg32(vmode & ~(OP_MODE_MASK << 2 * bitm_off),
CONFIG_UART_MOXA_MODE_REG);
vmode = opmode << 2 * bitm_off;
putreg32(getreg32(CONFIG_UART_MOXA_MODE_REG) | vmode, CONFIG_UART_MOXA_MODE_REG);
putreg32(getreg32(CONFIG_UART_MOXA_MODE_REG) | vmode,
CONFIG_UART_MOXA_MODE_REG);
leave_critical_section(flags);
ret = OK;
@ -141,7 +144,8 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Read from mode register */
opmode = (getreg32(CONFIG_UART_MOXA_MODE_REG) >> 2 * bitm_off) & OP_MODE_MASK;
opmode = (getreg32(CONFIG_UART_MOXA_MODE_REG) >> 2 * bitm_off) &
OP_MODE_MASK;
leave_critical_section(flags);
*(unsigned long *)arg = opmode;

11
arch/arm/src/moxart/moxart_timer.c
View file

@ -34,6 +34,10 @@
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <nuttx/irq.h>
@ -44,7 +48,7 @@
#include "arm_arch.h"
/****************************************************************************
* {re-processor Definitions
* Pre-processor Definitions
****************************************************************************/
#define TM1_ADDR 0x98400000
@ -59,7 +63,7 @@ enum timer_reg
CNTL_TIMER = 0x30,
LOAD_TIMER = 0x04,
MATCH1_TIMER = 0x08,
MATCH2_TIMER = 0x0C,
MATCH2_TIMER = 0x0c,
INTR_STATE_TIMER = 0x34,
INTR_MASK_TIMER = 0x38,
};
@ -135,7 +139,8 @@ void up_timer_initialize(void)
{
uint32_t tmp;
// up_disable_irq(IRQ_SYSTIMER);
/* up_disable_irq(IRQ_SYSTIMER); */
putreg32(0, TM1_ADDR + CNTL_TIMER);
putreg32(0, TM1_ADDR + INTR_STATE_TIMER);
putreg32(0x1ff, TM1_ADDR + INTR_MASK_TIMER);

33
arch/arm/src/nrf52/nrf52_flash.c
View file

@ -12,30 +12,31 @@
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/

37
arch/arm/src/nrf52/nrf52_nvmc.c
View file

@ -11,30 +11,31 @@
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
@ -407,9 +408,9 @@ void nrf_nvmc_page_erase(uint32_t address)
void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
{
uint32_t byte_shift = address & (uint32_t)0x03;
uint32_t address32 = address & ~byte_shift; /* Address to the word this byte is in.*/
uint32_t address32 = address & ~byte_shift; /* Address to the word this byte is in. */
uint32_t value32 = (*(uint32_t *)address32 &
~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
~((uint32_t)0xff << (byte_shift << (uint32_t)3)));
value32 = value32 + ((uint32_t)value << (byte_shift << 3));
/* Enable write */

24
arch/arm/src/rp2040/boot2/pico/config.h
View file

@ -1 +1,25 @@
/****************************************************************************
* arch/arm/src/rp2040/boot2/pico/config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "boards/pico.h"

4
arch/arm/src/tms570/tms570_esm.c
View file

@ -147,8 +147,8 @@ int tms570_esm_initialize(void)
int tms570_esm_interrupt(int irq, void *context, FAR void *arg)
{
/* Save the saved processor context in CURRENT_REGS where it can be accessed
* for register dumps and possibly context switching.
/* Save the saved processor context in CURRENT_REGS where it can be
* accessed for register dumps and possibly context switching.
*/
CURRENT_REGS = (uint32_t *)context;

15
arch/arm/src/tms570/tms570_selftest.c
View file

@ -274,21 +274,22 @@ void tms570_memtest_start(uint32_t rinfol)
int tms570_memtest_complete(void)
{
bool pass;
/* Wait for the test to complete */
while (!pbist_test_complete());
while (!pbist_test_complete());
/* Get the test result */
/* Get the test result */
pass = pbist_test_passed();
pass = pbist_test_passed();
/* Disable PBIST clocks and disable memory self-test mode */
/* Disable PBIST clocks and disable memory self-test mode */
pbist_stop();
pbist_stop();
/* Then return the test result */
/* Then return the test result */
return pass ? OK : ERROR;
return pass ? OK : ERROR;
}
/****************************************************************************

31
arch/arm/src/xmc4/xmc4_clockutils.c
View file

@ -37,15 +37,15 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS,
* IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR
* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
****************************************************************************/
@ -109,9 +109,12 @@ uint32_t xmc4_get_coreclock(void)
/* PLL normal mode */
regval = getreg32(XMC4_SCU_PLLCON1);
pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1;
ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1;
kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1;
pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >>
SCU_PLLCON1_PDIV_SHIFT) + 1;
ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >>
SCU_PLLCON1_NDIV_SHIFT) + 1;
kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >>
SCU_PLLCON1_K2DIV_SHIFT) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
@ -120,7 +123,8 @@ uint32_t xmc4_get_coreclock(void)
/* PLL prescalar mode */
regval = getreg32(XMC4_SCU_PLLCON1);
kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1;
kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >>
SCU_PLLCON1_K1DIV_SHIFT) + 1;
temp = (temp / kdiv);
}
@ -135,7 +139,8 @@ uint32_t xmc4_get_coreclock(void)
/* Divide by SYSDIV to get fSYS */
regval = getreg32(XMC4_SCU_SYSCLKCR);
sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1;
sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >>
SCU_SYSCLKCR_SYSDIV_SHIFT) + 1;
temp = temp / sysdiv;
/* Check if the fSYS clock is divided by two to produce fCPU clock. */

27
arch/arm/src/xmc4/xmc4_usic.c
View file

@ -33,17 +33,17 @@
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS,
* IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR
* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
****************************************************************************/
@ -203,6 +203,7 @@ int xmc4_disable_usic(enum usic_e usic)
switch (usic)
{
case USIC0:
/* Set bit in PRSET0 to assert USIC0 peripheral reset */
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0);
@ -216,6 +217,7 @@ int xmc4_disable_usic(enum usic_e usic)
#if XMC4_NUSIC > 1
case USIC1:
/* Set bit in PRSET1 to assert USIC1 peripheral reset */
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1);
@ -229,6 +231,7 @@ int xmc4_disable_usic(enum usic_e usic)
#if XMC4_NUSIC > 2
case USIC2:
/* Set bit in PRSET1 to assert USIC2 peripheral reset */
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1);
@ -454,8 +457,10 @@ int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
/* Setup and enable the baud rate generator */
regval = getreg32(base + XMC4_USIC_BRG_OFFSET);
regval &= ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK | USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN);
regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1));
regval &= ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK |
USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN);
regval |= (USIC_BRG_DCTQ(oversampling - 1) |
USIC_BRG_PDIV(pdiv_int_min - 1));
putreg32(regval, base + XMC4_USIC_BRG_OFFSET);
ret = OK;