nuttx/nuttx-mirror
1
2
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2025-01-13 09:49:21 +08:00
Code Issues Projects Releases Packages Wiki Activity Actions

xtensa/esp32s3: SPI support quad I/O mode

Browse source
This commit is contained in:
Dong Heng 2023-05-06 15:20:48 +08:00 committed by Alan Carvalho de Assis
parent fa5db655cd
commit 8f25329260
6 changed files with 2132 additions and 192 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

80
arch/xtensa/src/esp32s3/Kconfig
View file

@ -594,9 +594,22 @@ config ESP32S3_RTCIO_IRQ
menu "SPI configuration"
depends on ESP32S3_SPI
choice
prompt "SPI I/O Mode"
default ESP32S3_SPI_IO_SPI
config ESP32S3_SPI_IO_SPI
bool "SPI (4-line)"
config ESP32S3_SPI_IO_QIO
bool "QIO (6-line)"
endchoice # SPI I/O Mode
config ESP32S3_SPI_SWCS
bool "SPI software CS"
default n
depends on ESP32S3_SPI_IO_SPI
---help---
Use SPI software CS.
@ -607,36 +620,34 @@ config ESP32S3_SPI_UDCS
---help---
Use user-defined CS.
config ESP32S3_SPI_SLAVE_BUFSIZE
int "SPI slave buffer size"
default 2048
depends on SPI_SLAVE
if ESP32S3_SPI2
config ESP32S3_SPI2_DMA
bool "SPI2 use GDMA"
config ESP32S3_SPI_DMA
bool "SPI use GDMA"
default n
depends on ESP32S3_DMA
select ESP32S3_DMA
---help---
Enable support for transfers using the GDMA engine.
config ESP32S3_SPI2_DMADESC_NUM
int "SPI2 Master GDMA maximum number of descriptors"
default 2
depends on ESP32S3_SPI2_DMA
config ESP32S3_SPI_DMA_BUFSIZE
int "SPI Master GDMA buffer size"
default 2048
depends on ESP32S3_SPI_DMA
---help---
Configure the maximum number of out-link/in-link descriptors to
be chained for a GDMA transfer.
This is used to calculate and allocate DMA description buffer,
not really allocate TX/RX buffer.
config ESP32S3_SPI2_DMATHRESHOLD
int "SPI2 Master GDMA threshold"
config ESP32S3_SPI_DMATHRESHOLD
int "SPI Master GDMA threshold"
default 64
depends on ESP32S3_SPI2_DMA
depends on ESP32S3_SPI_DMA && ESP32S3_SPI_IO_SPI
---help---
When SPI GDMA is enabled, GDMA transfers whose size are below the
defined threshold will be performed by polling logic.
config ESP32S3_SPI_SLAVE_BUFSIZE
int "SPI Slave buffer size"
default 2048
depends on SPI_SLAVE
config ESP32S3_SPI2_CSPIN
int "SPI2 CS Pin"
default 10
@ -657,16 +668,17 @@ config ESP32S3_SPI2_MISOPIN
default 13
range 0 48
endif # ESP32S3_SPI2
config ESP32S3_SPI2_IO2PIN
int "SPI2 IO2 Pin"
default 14
range 0 48
depends on ESP32S3_SPI_IO_QIO
if ESP32S3_SPI3
config ESP32S3_SPI3_DMA
bool "SPI3 use GDMA"
default n
depends on ESP32S3_DMA
---help---
Enable support for transfers using the GDMA engine.
config ESP32S3_SPI2_IO3PIN
int "SPI2 IO3 Pin"
default 9
range 0 48
depends on ESP32S3_SPI_IO_QIO
config ESP32S3_SPI3_CSPIN
int "SPI3 CS Pin"
@ -688,7 +700,17 @@ config ESP32S3_SPI3_MISOPIN
default 2
range 0 48
endif # ESP32S3_SPI3
config ESP32S3_SPI3_IO2PIN
int "SPI3 IO2 Pin"
default 3
range 0 48
depends on ESP32S3_SPI_IO_QIO
config ESP32S3_SPI3_IO3PIN
int "SPI3 IO3 Pin"
default 4
range 0 48
depends on ESP32S3_SPI_IO_QIO
endmenu # SPI configuration

13
arch/xtensa/src/esp32s3/Make.defs
View file

@ -106,10 +106,15 @@ CHIP_CSRCS += esp32s3_i2c.c
endif
ifeq ($(CONFIG_ESP32S3_SPI),y)
CHIP_CSRCS += esp32s3_spi.c
ifeq ($(CONFIG_SPI_SLAVE),y)
CHIP_CSRCS += esp32s3_spi_slave.c
endif
ifeq ($(CONFIG_ESP32S3_SPI_IO_SPI),y)
CHIP_CSRCS += esp32s3_spi.c
else
CHIP_CSRCS += esp32s3_qspi.c
endif
ifeq ($(CONFIG_SPI_SLAVE),y)
CHIP_CSRCS += esp32s3_spi_slave.c
endif
endif
ifeq ($(CONFIG_ESP32S3_SPIFLASH),y)

1610
arch/xtensa/src/esp32s3/esp32s3_qspi.c Normal file
View file

File diff suppressed because it is too large Load diff

126
arch/xtensa/src/esp32s3/esp32s3_qspi.h Normal file
View file

@ -0,0 +1,126 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_qspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi/qspi.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_ESP32S3_SPI
#ifdef CONFIG_ESP32S3_SPI2
# define ESP32S3_SPI2 2
#endif
#ifdef CONFIG_ESP32S3_SPI3
# define ESP32S3_SPI3 3
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: esp32s3_qspibus_set_attr
*
* Description:
* Set attribution of QSPI bus transfer.
*
* Input Parameters:
* dev - Device-specific state data
* dummies - Number of dummy cycles, this only works in command
* transfer, not works in memory transfer
* addr_lines - Number of address transmiting I/O pins
* data_lines - Number of data transmiting I/O pins
*
* Returned Value:
* Zero (OK) is returned on success. Otherwise -1 (ERROR).
*
****************************************************************************/
int esp32s3_qspibus_set_attr(struct qspi_dev_s *dev,
uint8_t dummies,
uint8_t addr_lines,
uint8_t data_lines);
/****************************************************************************
* Name: esp32s3_qspibus_initialize
*
* Description:
* Initialize the selected QSPI bus.
*
* Input Parameters:
* port - Port number (for hardware that has multiple QSPI interfaces)
*
* Returned Value:
* Valid QSPI device structure reference on success; NULL on failure
*
****************************************************************************/
struct qspi_dev_s *esp32s3_qspibus_initialize(int port);
/****************************************************************************
* Name: esp32s3_qspibus_uninitialize
*
* Description:
* Uninitialize an QSPI bus.
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* Zero (OK) is returned on success. Otherwise -1 (ERROR).
*
****************************************************************************/
int esp32s3_qspibus_uninitialize(struct qspi_dev_s *dev);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_ESP32S3_SPI */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H */

105
arch/xtensa/src/esp32s3/esp32s3_spi.c
View file

@ -48,7 +48,7 @@
#include "esp32s3_irq.h"
#include "esp32s3_gpio.h"
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
#include "esp32s3_dma.h"
#endif
@ -71,11 +71,15 @@
# define SPI_HAVE_SWCS 0
#endif
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
/* SPI DMA RX/TX number of descriptors */
/* QSPI DMA RX/TX number of descriptors */
#define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI2_DMADESC_NUM)
# if (CONFIG_ESP32S3_SPI_DMA_BUFSIZE % ESP32S3_DMA_BUFLEN_MAX) > 0
# define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI_DMA_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX + 1)
# else
# define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI_DMA_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX)
# endif
/* SPI DMA reset before exchange */
@ -123,13 +127,13 @@ struct esp32s3_spi_config_s
uint8_t mosi_pin; /* GPIO configuration for MOSI */
uint8_t miso_pin; /* GPIO configuration for MISO */
uint8_t clk_pin; /* GPIO configuration for CLK */
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
uint8_t periph; /* Peripheral ID */
uint8_t irq; /* Interrupt ID */
#endif
uint32_t clk_bit; /* Clock enable bit */
uint32_t rst_bit; /* SPI reset bit */
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
uint32_t dma_clk_bit; /* DMA clock enable bit */
uint32_t dma_rst_bit; /* DMA reset bit */
#endif
@ -154,11 +158,16 @@ struct esp32s3_spi_priv_s
const struct esp32s3_spi_config_s *config;
int refs; /* Reference count */
mutex_t lock; /* Held while chip is selected for mutual exclusion */
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
sem_t sem_isr; /* Interrupt wait semaphore */
int cpu; /* CPU ID */
int cpuint; /* SPI interrupt ID */
int32_t dma_channel; /* Channel assigned by the GDMA driver */
/* DMA RX/TX description */
struct esp32s3_dmadesc_s *dma_rxdesc;
struct esp32s3_dmadesc_s *dma_txdesc;
#endif
uint32_t frequency; /* Requested clock frequency */
uint32_t actual; /* Actual clock frequency */
@ -188,7 +197,7 @@ static uint32_t esp32s3_spi_send(struct spi_dev_s *dev, uint32_t wd);
static void esp32s3_spi_exchange(struct spi_dev_s *dev,
const void *txbuffer,
void *rxbuffer, size_t nwords);
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static int esp32s3_spi_interrupt(int irq, void *context, void *arg);
static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv);
static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
@ -212,7 +221,7 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev,
#ifdef CONFIG_SPI_TRIGGER
static int esp32s3_spi_trigger(struct spi_dev_s *dev);
#endif
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static void esp32s3_spi_dma_init(struct spi_dev_s *dev);
#endif
static void esp32s3_spi_init(struct spi_dev_s *dev);
@ -233,13 +242,13 @@ static const struct esp32s3_spi_config_s esp32s3_spi2_config =
.mosi_pin = CONFIG_ESP32S3_SPI2_MOSIPIN,
.miso_pin = CONFIG_ESP32S3_SPI2_MISOPIN,
.clk_pin = CONFIG_ESP32S3_SPI2_CLKPIN,
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
.periph = ESP32S3_PERIPH_SPI2,
.irq = ESP32S3_IRQ_SPI2,
#endif
.clk_bit = SYSTEM_SPI2_CLK_EN,
.rst_bit = SYSTEM_SPI2_RST,
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
.dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN,
.dma_rst_bit = SYSTEM_SPI2_DMA_RST,
#endif
@ -284,6 +293,15 @@ static const struct spi_ops_s esp32s3_spi2_ops =
.registercallback = NULL,
};
#ifdef CONFIG_ESP32S3_SPI_DMA
/* SPI DMA RX/TX description */
static struct esp32s3_dmadesc_s esp32s3_spi2_dma_txdesc[SPI_DMA_DESC_NUM];
static struct esp32s3_dmadesc_s esp32s3_spi2_dma_rxdesc[SPI_DMA_DESC_NUM];
#endif
static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
{
.spi_dev =
@ -293,10 +311,12 @@ static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
.config = &esp32s3_spi2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
.sem_isr = SEM_INITIALIZER(0),
.cpuint = -ENOMEM,
.dma_channel = -1,
.dma_rxdesc = esp32s3_spi2_dma_rxdesc,
.dma_txdesc = esp32s3_spi2_dma_txdesc,
#endif
.frequency = 0,
.actual = 0,
@ -316,8 +336,16 @@ static const struct esp32s3_spi_config_s esp32s3_spi3_config =
.mosi_pin = CONFIG_ESP32S3_SPI3_MOSIPIN,
.miso_pin = CONFIG_ESP32S3_SPI3_MISOPIN,
.clk_pin = CONFIG_ESP32S3_SPI3_CLKPIN,
#ifdef CONFIG_ESP32S3_SPI_DMA
.periph = ESP32S3_PERIPH_SPI3,
.irq = ESP32S3_IRQ_SPI3,
#endif
.clk_bit = SYSTEM_SPI3_CLK_EN,
.rst_bit = SYSTEM_SPI3_RST,
#ifdef CONFIG_ESP32S3_SPI_DMA
.dma_clk_bit = SYSTEM_SPI3_DMA_CLK_EN,
.dma_rst_bit = SYSTEM_SPI3_DMA_RST,
#endif
.cs_insig = FSPICS0_IN_IDX,
.cs_outsig = FSPICS0_OUT_IDX,
.mosi_insig = FSPID_IN_IDX,
@ -359,6 +387,15 @@ static const struct spi_ops_s esp32s3_spi3_ops =
.registercallback = NULL,
};
#ifdef CONFIG_ESP32S3_SPI_DMA
/* SPI DMA RX/TX description */
static struct esp32s3_dmadesc_s esp32s3_spi3_dma_txdesc[SPI_DMA_DESC_NUM];
static struct esp32s3_dmadesc_s esp32s3_spi3_dma_rxdesc[SPI_DMA_DESC_NUM];
#endif
static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
{
.spi_dev =
@ -368,6 +405,13 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
.config = &esp32s3_spi3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_ESP32S3_SPI_DMA
.sem_isr = SEM_INITIALIZER(0),
.cpuint = -ENOMEM,
.dma_channel = -1,
.dma_rxdesc = esp32s3_spi3_dma_rxdesc,
.dma_txdesc = esp32s3_spi3_dma_txdesc,
#endif
.frequency = 0,
.actual = 0,
.mode = 0,
@ -375,15 +419,6 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
};
#endif /* CONFIG_ESP32S3_SPI3 */
#ifdef CONFIG_ESP32S3_SPI2_DMA
/* SPI DMA RX/TX description */
static struct esp32s3_dmadesc_s dma_rxdesc[SPI_DMA_DESC_NUM];
static struct esp32s3_dmadesc_s dma_txdesc[SPI_DMA_DESC_NUM];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -515,7 +550,7 @@ static int esp32s3_spi_lock(struct spi_dev_s *dev, bool lock)
*
****************************************************************************/
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv)
{
return nxsem_tickwait_uninterruptible(&priv->sem_isr, SEC2TICK(10));
@ -824,7 +859,7 @@ static int esp32s3_spi_hwfeatures(struct spi_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
const void *txbuffer,
void *rxbuffer,
@ -869,8 +904,8 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id),
SPI_DMA_TX_ENA_M);
n = esp32s3_dma_setup(channel, true, dma_txdesc, SPI_DMA_DESC_NUM,
tp, bytes);
n = esp32s3_dma_setup(channel, true, priv->dma_txdesc,
SPI_DMA_DESC_NUM, tp, bytes);
esp32s3_dma_enable(channel, true);
putreg32((n * 8 - 1), SPI_MS_DLEN_REG(priv->config->id));
@ -886,8 +921,8 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id),
SPI_DMA_RX_ENA_M);
esp32s3_dma_setup(channel, false, dma_rxdesc, SPI_DMA_DESC_NUM,
rp, bytes);
esp32s3_dma_setup(channel, false, priv->dma_rxdesc,
SPI_DMA_DESC_NUM, rp, bytes);
esp32s3_dma_enable(channel, false);
esp32s3_spi_set_regbits(SPI_USER_REG(priv->config->id),
@ -1158,8 +1193,8 @@ static void esp32s3_spi_exchange(struct spi_dev_s *dev,
{
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
#ifdef CONFIG_ESP32S3_SPI2_DMA
size_t thld = CONFIG_ESP32S3_SPI2_DMATHRESHOLD;
#ifdef CONFIG_ESP32S3_SPI_DMA
size_t thld = CONFIG_ESP32S3_SPI_DMATHRESHOLD;
if (nwords > thld)
{
@ -1270,7 +1305,7 @@ static int esp32s3_spi_trigger(struct spi_dev_s *dev)
*
****************************************************************************/
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
void esp32s3_spi_dma_init(struct spi_dev_s *dev)
{
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
@ -1389,7 +1424,7 @@ static void esp32s3_spi_init(struct spi_dev_s *dev)
putreg32(VALUE_MASK(0, SPI_CS_HOLD_TIME),
SPI_USER1_REG(priv->config->id));
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
esp32s3_spi_dma_init(dev);
#endif
@ -1416,7 +1451,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
{
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0);
#endif
@ -1445,7 +1480,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
*
****************************************************************************/
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static int esp32s3_spi_interrupt(int irq, void *context, void *arg)
{
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)arg;
@ -1505,7 +1540,7 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port)
return spi_dev;
}
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
/* If a CPU Interrupt was previously allocated, then deallocate it */
if (priv->cpuint != -ENOMEM)
@ -1591,7 +1626,7 @@ int esp32s3_spibus_uninitialize(struct spi_dev_s *dev)
return OK;
}
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
up_disable_irq(priv->config->irq);
esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
irq_detach(priv->config->irq);

390
arch/xtensa/src/esp32s3/esp32s3_spi_slave.c
View file

@ -48,7 +48,7 @@
#include "esp32s3_irq.h"
#include "esp32s3_gpio.h"
#if defined(CONFIG_ESP32S3_SPI2_DMA) || defined(CONFIG_ESP32S3_SPI3_DMA)
#ifdef CONFIG_ESP32S3_SPI_DMA
#include "esp32s3_dma.h"
#endif
@ -65,20 +65,27 @@
#define SPI_SLAVE_BUFSIZE (CONFIG_ESP32S3_SPI_SLAVE_BUFSIZE)
#if defined(CONFIG_ESP32S3_SPI2_DMA) || defined(CONFIG_ESP32S3_SPI3_DMA)
# define ESP32S3_SPI_DMA
#endif
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
/* SPI DMA RX/TX number of descriptors */
#if (SPI_SLAVE_BUFSIZE % ESP32S3_DMA_BUFLEN_MAX) > 0
# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX + 1)
#else
# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX)
#endif
# if (SPI_SLAVE_BUFSIZE % ESP32S3_DMA_BUFLEN_MAX) > 0
# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX + 1)
# else
# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX)
# endif
#endif /* ESP32S3_SPI_DMA */
# define SPI_SLV_INT_EN (SPI_SLV_WR_DMA_DONE_INT_ENA_M | SPI_SLV_RD_DMA_DONE_INT_ENA_M)
# define SPI_SLV_INT_RX SPI_SLV_WR_DMA_DONE_INT_ST_M
# define SPI_SLV_INT_CLR_RX SPI_SLV_WR_DMA_DONE_INT_CLR_M
# define SPI_SLV_INT_TX SPI_SLV_RD_DMA_DONE_INT_ST_M
# define SPI_SLV_INT_CLR_TX SPI_SLV_RD_DMA_DONE_INT_CLR_M
#else
# define SPI_SLV_INT_EN (SPI_SLV_WR_BUF_DONE_INT_ENA_M | SPI_SLV_RD_BUF_DONE_INT_ENA_M)
# define SPI_SLV_INT_RX SPI_SLV_WR_BUF_DONE_INT_ST_M
# define SPI_SLV_INT_CLR_RX SPI_SLV_WR_BUF_DONE_INT_CLR_M
# define SPI_SLV_INT_TX SPI_SLV_RD_BUF_DONE_INT_ST_M
# define SPI_SLV_INT_CLR_TX SPI_SLV_RD_BUF_DONE_INT_CLR_M
#endif /* CONFIG_ESP32S3_SPI_DMA */
/* Verify whether SPI has been assigned IOMUX pins.
* Otherwise, SPI signals will be routed via GPIO Matrix.
@ -90,10 +97,29 @@
# define SPI_IS_MOSI_IOMUX (CONFIG_ESP32S3_SPI2_MOSIPIN == SPI2_IOMUX_MOSIPIN)
# define SPI_IS_MISO_IOMUX (CONFIG_ESP32S3_SPI2_MISOPIN == SPI2_IOMUX_MISOPIN)
# define SPI_VIA_IOMUX ((SPI_IS_CS_IOMUX) && \
(SPI_IS_CLK_IOMUX) && \
(SPI_IS_MOSI_IOMUX) && \
(SPI_IS_MISO_IOMUX))
/* In quad SPI mode, flash's IO map is:
* MOSI -> IO0
* MISO -> IO1
* WP -> IO2
* Hold -> IO3
*/
# ifdef CONFIG_ESP32S3_SPI_IO_QIO
# define SPI_IS_IO2_IOMUX (CONFIG_ESP32S3_SPI2_IO2PIN == SPI2_IOMUX_WPPIN)
# define SPI_IS_IO3_IOMUX (CONFIG_ESP32S3_SPI2_IO3PIN == SPI2_IOMUX_HDPIN)
# define SPI_VIA_IOMUX ((SPI_IS_CS_IOMUX) && \
(SPI_IS_CLK_IOMUX) && \
(SPI_IS_MOSI_IOMUX) && \
(SPI_IS_MISO_IOMUX) && \
(SPI_IS_IO2_IOMUX) && \
(SPI_IS_IO3_IOMUX))
# else
# define SPI_VIA_IOMUX ((SPI_IS_CS_IOMUX) && \
(SPI_IS_CLK_IOMUX) && \
(SPI_IS_MOSI_IOMUX) && \
(SPI_IS_MISO_IOMUX))
# endif
#else
# define SPI_VIA_IOMUX 0
#endif
@ -136,12 +162,15 @@ struct spislave_config_s
uint8_t mosi_pin; /* GPIO configuration for MOSI */
uint8_t miso_pin; /* GPIO configuration for MISO */
uint8_t clk_pin; /* GPIO configuration for CLK */
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
uint8_t io2_pin; /* GPIO configuration for IO2 */
uint8_t io3_pin; /* GPIO configuration for IO3 */
#endif
uint8_t periph; /* Peripheral ID */
uint8_t irq; /* Interrupt ID */
uint32_t clk_bit; /* Clock enable bit */
uint32_t rst_bit; /* SPI reset bit */
#ifdef ESP32S3_SPI_DMA
bool dma_used; /* Enable DMA channel */
#ifdef CONFIG_ESP32S3_SPI_DMA
uint32_t dma_clk_bit; /* DMA clock enable bit */
uint32_t dma_rst_bit; /* DMA reset bit */
uint8_t dma_periph; /* DMA peripheral */
@ -154,6 +183,12 @@ struct spislave_config_s
uint32_t miso_outsig; /* SPI MISO output signal index */
uint32_t clk_insig; /* SPI CLK input signal index */
uint32_t clk_outsig; /* SPI CLK output signal index */
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
uint32_t io2_insig;
uint32_t io2_outsig;
uint32_t io3_insig;
uint32_t io3_outsig;
#endif
};
struct spislave_priv_s
@ -172,7 +207,7 @@ struct spislave_priv_s
int refs; /* Reference count */
int cpu; /* CPU ID */
int cpuint; /* SPI interrupt ID */
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
int32_t dma_channel; /* Channel assigned by the GDMA driver */
/* DMA RX/TX description */
@ -224,7 +259,7 @@ static void spislave_store_result(struct spislave_priv_s *priv,
uint32_t recv_bytes);
static void spislave_evict_sent_data(struct spislave_priv_s *priv,
uint32_t sent_bytes);
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static void spislave_setup_rx_dma(struct spislave_priv_s *priv);
static void spislave_setup_tx_dma(struct spislave_priv_s *priv);
static void spislave_prepare_next_rx(struct spislave_priv_s *priv);
@ -265,12 +300,15 @@ static const struct spislave_config_s esp32s3_spi2slave_config =
.mosi_pin = CONFIG_ESP32S3_SPI2_MOSIPIN,
.miso_pin = CONFIG_ESP32S3_SPI2_MISOPIN,
.clk_pin = CONFIG_ESP32S3_SPI2_CLKPIN,
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
.io2_pin = CONFIG_ESP32S3_SPI2_IO2PIN,
.io3_pin = CONFIG_ESP32S3_SPI2_IO3PIN,
#endif
.periph = ESP32S3_PERIPH_SPI2,
.irq = ESP32S3_IRQ_SPI2,
.clk_bit = SYSTEM_SPI2_CLK_EN,
.rst_bit = SYSTEM_SPI2_RST,
#ifdef CONFIG_ESP32S3_SPI2_DMA
.dma_used = true,
#ifdef CONFIG_ESP32S3_SPI_DMA
.dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN,
.dma_rst_bit = SYSTEM_SPI2_DMA_RST,
.dma_periph = ESP32S3_DMA_PERIPH_SPI2,
@ -282,7 +320,13 @@ static const struct spislave_config_s esp32s3_spi2slave_config =
.miso_insig = FSPIQ_IN_IDX,
.miso_outsig = FSPIQ_OUT_IDX,
.clk_insig = FSPICLK_IN_IDX,
.clk_outsig = FSPICLK_OUT_IDX
.clk_outsig = FSPICLK_OUT_IDX,
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
.io2_insig = FSPIWP_IN_IDX,
.io2_outsig = FSPIWP_OUT_IDX,
.io3_insig = FSPIHD_IN_IDX,
.io3_outsig = FSPIHD_OUT_IDX,
#endif
};
static const struct spi_slave_ctrlrops_s esp32s3_spi2slave_ops =
@ -295,7 +339,7 @@ static const struct spi_slave_ctrlrops_s esp32s3_spi2slave_ops =
.qpoll = spislave_qpoll
};
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
/* SPI DMA RX/TX description buffer */
@ -314,7 +358,7 @@ static struct spislave_priv_s esp32s3_spi2slave_priv =
.refs = 0,
.cpu = -1,
.cpuint = -ENOMEM,
#ifdef CONFIG_ESP32S3_SPI2_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
.dma_channel = -ENOMEM,
.dma_rxdesc = esp32s3_spi2_dma_rxdesc,
.dma_txdesc = esp32s3_spi2_dma_txdesc,
@ -347,12 +391,15 @@ static const struct spislave_config_s esp32s3_spi3slave_config =
.mosi_pin = CONFIG_ESP32S3_SPI3_MOSIPIN,
.miso_pin = CONFIG_ESP32S3_SPI3_MISOPIN,
.clk_pin = CONFIG_ESP32S3_SPI3_CLKPIN,
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
.io2_pin = CONFIG_ESP32S3_SPI3_IO2PIN,
.io3_pin = CONFIG_ESP32S3_SPI3_IO3PIN,
#endif
.periph = ESP32S3_PERIPH_SPI3,
.irq = ESP32S3_IRQ_SPI3,
.clk_bit = SYSTEM_SPI3_CLK_EN,
.rst_bit = SYSTEM_SPI3_RST,
#ifdef CONFIG_ESP32S3_SPI3_DMA
.dma_used = true,
#ifdef CONFIG_ESP32S3_SPI_DMA
.dma_clk_bit = SYSTEM_SPI3_DMA_CLK_EN,
.dma_rst_bit = SYSTEM_SPI3_DMA_RST,
.dma_periph = ESP32S3_DMA_PERIPH_SPI3,
@ -364,7 +411,13 @@ static const struct spislave_config_s esp32s3_spi3slave_config =
.miso_insig = SPI3_Q_IN_IDX,
.miso_outsig = SPI3_Q_OUT_IDX,
.clk_insig = SPI3_CLK_IN_IDX,
.clk_outsig = SPI3_CLK_OUT_IDX
.clk_outsig = SPI3_CLK_OUT_IDX,
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
.io2_insig = SPI3_WP_IN_IDX,
.io2_outsig = SPI3_WP_OUT_IDX,
.io3_insig = SPI3_HD_IN_IDX,
.io3_outsig = SPI3_HD_OUT_IDX,
#endif
};
static const struct spi_slave_ctrlrops_s esp32s3_spi3slave_ops =
@ -377,7 +430,7 @@ static const struct spi_slave_ctrlrops_s esp32s3_spi3slave_ops =
.qpoll = spislave_qpoll
};
#ifdef CONFIG_ESP32S3_SPI3_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
/* SPI DMA RX/TX description buffer */
@ -396,7 +449,7 @@ static struct spislave_priv_s esp32s3_spi3slave_priv =
.refs = 0,
.cpu = -1,
.cpuint = -ENOMEM,
#ifdef CONFIG_ESP32S3_SPI3_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
.dma_channel = -ENOMEM,
.dma_rxdesc = esp32s3_spi3_dma_rxdesc,
.dma_txdesc = esp32s3_spi3_dma_txdesc,
@ -479,7 +532,7 @@ static inline void spislave_cpu_tx_fifo_reset(struct spislave_priv_s *priv)
*
****************************************************************************/
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static inline void spislave_dma_tx_fifo_reset(struct spislave_priv_s *priv)
{
setbits(SPI_DMA_AFIFO_RST_M, SPI_DMA_CONF_REG(priv->config->id));
@ -502,7 +555,7 @@ static inline void spislave_dma_tx_fifo_reset(struct spislave_priv_s *priv)
*
****************************************************************************/
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static inline void spislave_dma_rx_fifo_reset(struct spislave_priv_s *priv)
{
setbits(SPI_RX_AFIFO_RST_M, SPI_DMA_CONF_REG(priv->config->id));
@ -678,7 +731,7 @@ static void spislave_store_result(struct spislave_priv_s *priv,
bytes_to_copy = remaining_space;
}
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
if (bytes_to_copy)
{
if ((priv->rx_dma_offset != priv->rx_length))
@ -739,7 +792,7 @@ static void spislave_store_result(struct spislave_priv_s *priv,
*
****************************************************************************/
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static void spislave_prepare_next_rx(struct spislave_priv_s *priv)
{
if (priv->rx_length < SPI_SLAVE_BUFSIZE)
@ -797,7 +850,7 @@ static void spislave_evict_sent_data(struct spislave_priv_s *priv,
*
****************************************************************************/
#ifndef ESP32S3_SPI_DMA
#ifndef CONFIG_ESP32S3_SPI_DMA
static void spislave_write_tx_buffer(struct spislave_priv_s *priv)
{
/* Initialize data_buf_reg with the address of the first data buffer
@ -842,7 +895,7 @@ static void spislave_write_tx_buffer(struct spislave_priv_s *priv)
*
****************************************************************************/
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static void spislave_setup_rx_dma(struct spislave_priv_s *priv)
{
uint32_t length = SPI_SLAVE_BUFSIZE - priv->rx_length;
@ -888,7 +941,7 @@ static void spislave_setup_rx_dma(struct spislave_priv_s *priv)
*
****************************************************************************/
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
static void spislave_setup_tx_dma(struct spislave_priv_s *priv)
{
esp32s3_dma_setup(priv->dma_channel,
@ -934,11 +987,8 @@ static void spislave_prepare_next_tx(struct spislave_priv_s *priv)
{
if (priv->tx_length != 0)
{
#ifdef ESP32S3_SPI_DMA
if (priv->config->dma_used)
{
spislave_setup_tx_dma(priv);
}
#ifdef CONFIG_ESP32S3_SPI_DMA
spislave_setup_tx_dma(priv);
#else
spislave_peripheral_reset(priv);
@ -953,14 +1003,7 @@ static void spislave_prepare_next_tx(struct spislave_priv_s *priv)
{
spiwarn("TX buffer empty! Disabling TX for next transaction\n");
#ifdef ESP32S3_SPI_DMA
if (!priv->config->dma_used)
{
spislave_cpu_tx_fifo_reset(priv);
}
#else
spislave_cpu_tx_fifo_reset(priv);
#endif
priv->is_tx_enabled = false;
}
@ -986,10 +1029,16 @@ static void spislave_prepare_next_tx(struct spislave_priv_s *priv)
static int spislave_periph_interrupt(int irq, void *context, void *arg)
{
struct spislave_priv_s *priv = (struct spislave_priv_s *)arg;
uint32_t regval = getreg32(SPI_SLAVE1_REG(priv->config->id));
uint32_t transfer_size = REG_MASK(regval, SPI_SLV_DATA_BITLEN) / 8;
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
uint32_t int_clear = 0;
uint32_t int_status = getreg32(SPI_DMA_INT_ST_REG(priv->config->id));
#else
uint32_t int_clear = SPI_TRANS_DONE_INT_CLR_M;
#endif
if (!priv->is_processing)
{
SPIS_DEV_SELECT(priv->dev, true);
@ -998,26 +1047,41 @@ static int spislave_periph_interrupt(int irq, void *context, void *arg)
/* RX process */
if (transfer_size > 0)
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
if (int_status & SPI_SLV_INT_RX)
{
spislave_store_result(priv, transfer_size);
}
#endif
if (transfer_size > 0)
{
spislave_store_result(priv, transfer_size);
}
#ifdef ESP32S3_SPI_DMA
if (priv->config->dma_used)
{
#ifdef CONFIG_ESP32S3_SPI_DMA
spislave_prepare_next_rx(priv);
#endif
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
int_clear |= SPI_SLV_INT_CLR_RX;
}
#endif
/* TX process */
if (priv->is_tx_enabled && transfer_size > 0)
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
if (int_status & SPI_SLV_INT_TX)
{
spislave_evict_sent_data(priv, transfer_size);
}
#endif
if (priv->is_tx_enabled && transfer_size > 0)
{
spislave_evict_sent_data(priv, transfer_size);
}
spislave_prepare_next_tx(priv);
spislave_prepare_next_tx(priv);
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
int_clear |= SPI_SLV_INT_CLR_TX;
}
#endif
if (priv->is_processing && esp32s3_gpioread(priv->config->cs_pin))
{
@ -1027,11 +1091,13 @@ static int spislave_periph_interrupt(int irq, void *context, void *arg)
/* Clear the trans_done interrupt flag */
setbits(SPI_TRANS_DONE_INT_CLR_M, SPI_DMA_INT_CLR_REG(priv->config->id));
setbits(int_clear, SPI_DMA_INT_CLR_REG(priv->config->id));
/* Trigger the start of user-defined transaction */
#ifndef CONFIG_ESP32S3_SPI_IO_QIO
setbits(SPI_USR_M, SPI_CMD_REG(priv->config->id));
#endif
return 0;
}
@ -1050,7 +1116,7 @@ static int spislave_periph_interrupt(int irq, void *context, void *arg)
*
****************************************************************************/
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
void spislave_dma_init(struct spislave_priv_s *priv)
{
/* Enable GDMA clock for the SPI peripheral */
@ -1086,6 +1152,105 @@ void spislave_dma_init(struct spislave_priv_s *priv)
}
#endif
/****************************************************************************
* Name: spislave_initializ_iomux
*
* Description:
* Initialize ESP32-S3 SPI Slave GPIO by IO MUX.
*
* Input Parameters:
* priv - Private SPI Slave controller structure
*
* Returned Value:
* None.
*
****************************************************************************/
#if SPI_VIA_IOMUX != 0
static void spislave_initializ_iomux(struct spislave_priv_s *priv)
{
uint32_t attr = INPUT_FUNCTION_5 | DRIVE_0;
const struct spislave_config_s *config = priv->config;
esp32s3_configgpio(config->cs_pin, attr);
esp32s3_configgpio(config->clk_pin, attr);
esp32s3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0);
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
attr |= OUTPUT;
esp32s3_configgpio(config->mosi_pin, attr);
esp32s3_configgpio(config->miso_pin, attr);
esp32s3_configgpio(config->io2_pin, attr);
esp32s3_configgpio(config->io3_pin, attr);
esp32s3_gpio_matrix_out(config->io2_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_gpio_matrix_out(config->io3_pin, SIG_GPIO_OUT_IDX, 0, 0);
#else
esp32s3_configgpio(config->mosi_pin, attr);
esp32s3_configgpio(config->miso_pin, OUTPUT_FUNCTION_5);
#endif
}
#endif
/****************************************************************************
* Name: spislave_initializ_iomatrix
*
* Description:
* Initialize ESP32-S3 SPI Slave GPIO by IO matrix.
*
* Input Parameters:
* priv - Private SPI Slave controller structure
*
* Returned Value:
* None.
*
****************************************************************************/
#if SPI_VIA_IOMUX == 0 || defined(CONFIG_ESP32S3_SPI3)
static void spislave_initializ_iomatrix(struct spislave_priv_s *priv)
{
uint32_t attr = INPUT | DRIVE_0;
const struct spislave_config_s *config = priv->config;
esp32s3_configgpio(config->cs_pin, attr);
esp32s3_gpio_matrix_in(config->cs_pin, config->cs_insig, 0);
esp32s3_configgpio(config->clk_pin, attr);
esp32s3_gpio_matrix_in(config->clk_pin, config->clk_insig, 0);
# ifdef CONFIG_ESP32S3_SPI_IO_QIO
attr |= OUTPUT;
esp32s3_configgpio(config->mosi_pin, attr);
esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0);
esp32s3_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0);
esp32s3_configgpio(config->miso_pin, attr);
esp32s3_gpio_matrix_in(config->miso_pin, config->miso_insig, 0);
esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0);
esp32s3_configgpio(config->io2_pin, attr);
esp32s3_gpio_matrix_in(config->io2_pin, config->io2_insig, 0);
esp32s3_gpio_matrix_out(config->io2_pin, config->io2_outsig, 0, 0);
esp32s3_configgpio(config->io3_pin, attr);
esp32s3_gpio_matrix_in(config->io3_pin, config->io3_insig, 0);
esp32s3_gpio_matrix_out(config->io3_pin, config->io3_outsig, 0, 0);
# else
esp32s3_configgpio(config->mosi_pin, attr);
esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0);
esp32s3_configgpio(config->miso_pin, OUTPUT);
esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0);
# endif
}
#endif
/****************************************************************************
* Name: spislave_gpio_initialize
*
@ -1102,54 +1267,19 @@ void spislave_dma_init(struct spislave_priv_s *priv)
static void spislave_gpio_initialize(struct spislave_priv_s *priv)
{
const struct spislave_config_s *config = priv->config;
esp32s3_gpiowrite(config->cs_pin, 1);
esp32s3_gpiowrite(config->mosi_pin, 1);
esp32s3_gpiowrite(config->miso_pin, 1);
esp32s3_gpiowrite(config->clk_pin, 1);
#if SPI_VIA_IOMUX != 0
if (priv->config->id == 0)
if (priv->config->id == 2)
{
esp32s3_configgpio(config->cs_pin, INPUT_FUNCTION_5 | PULLUP);
esp32s3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_configgpio(config->mosi_pin, INPUT_FUNCTION_5 | PULLUP);
esp32s3_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_configgpio(config->miso_pin, OUTPUT_FUNCTION_5 | PULLUP);
esp32s3_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32s3_configgpio(config->clk_pin, INPUT_FUNCTION_5 | PULLUP);
esp32s3_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0);
spislave_initializ_iomux(priv);
}
# ifdef CONFIG_ESP32S3_SPI3
else
{
esp32s3_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_in(config->cs_pin, config->cs_insig, 0);
esp32s3_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0);
esp32s3_configgpio(config->miso_pin, OUTPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0);
esp32s3_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_in(config->clk_pin, config->clk_insig, 0);
spislave_initializ_iomatrix(priv);
}
# endif
#else
esp32s3_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_in(config->cs_pin, config->cs_insig, 0);
esp32s3_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0);
esp32s3_configgpio(config->miso_pin, OUTPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0);
esp32s3_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP);
esp32s3_gpio_matrix_in(config->clk_pin, config->clk_insig, 0);
spislave_initializ_iomatrix(priv);
#endif
}
@ -1169,6 +1299,7 @@ static void spislave_gpio_initialize(struct spislave_priv_s *priv)
static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr)
{
uint32_t regval;
struct spislave_priv_s *priv = (struct spislave_priv_s *)ctrlr;
const struct spislave_config_s *config = priv->config;
@ -1183,11 +1314,23 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr)
putreg32(0, SPI_CLOCK_REG(priv->config->id));
putreg32(SPI_DOUTDIN_M, SPI_USER_REG(priv->config->id));
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
regval = 0;
#else
regval = SPI_DOUTDIN_M;
#endif
putreg32(regval, SPI_USER_REG(priv->config->id));
putreg32(0, SPI_CTRL_REG(priv->config->id));
putreg32(SPI_SLAVE_MODE_M, SPI_SLAVE_REG(priv->config->id));
regval = SPI_SLAVE_MODE_M;
#ifdef CONFIG_ESP32S3_SPI_DMA
regval |= SPI_SLV_WRDMA_BITLEN_EN_M | SPI_SLV_RDDMA_BITLEN_EN_M;
#else
regval |= SPI_SLV_WRBUF_BITLEN_EN_M | SPI_SLV_RDBUF_BITLEN_EN_M;
#endif
putreg32(regval, SPI_SLAVE_REG(priv->config->id));
spislave_peripheral_reset(priv);
@ -1200,11 +1343,8 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr)
resetbits(SPI_INT_MASK, SPI_DMA_INT_ENA_REG(priv->config->id));
#ifdef ESP32S3_SPI_DMA
if (priv->config->dma_used)
{
spislave_dma_init(priv);
}
#ifdef CONFIG_ESP32S3_SPI_DMA
spislave_dma_init(priv);
#endif
esp32s3_gpioirqenable(ESP32S3_PIN2IRQ(config->cs_pin), GPIO_INTR_POSEDGE);
@ -1216,8 +1356,13 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr)
* queued.
*/
setbits(SPI_TRANS_DONE_INT_RAW_M, SPI_DMA_INT_RAW_REG(priv->config->id));
setbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG(priv->config->id));
#ifdef CONFIG_ESP32S3_SPI_IO_QIO
regval = SPI_SLV_INT_EN;
#else
regval = SPI_TRANS_DONE_INT_ENA_M;
#endif
setbits(regval, SPI_DMA_INT_RAW_REG(priv->config->id));
setbits(regval, SPI_DMA_INT_ENA_REG(priv->config->id));
}
/****************************************************************************
@ -1244,12 +1389,8 @@ static void spislave_deinitialize(struct spi_slave_ctrlr_s *ctrlr)
resetbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG(priv->config->id));
#ifdef ESP32S3_SPI_DMA
if (priv->config->dma_used)
{
resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG);
}
#ifdef CONFIG_ESP32S3_SPI_DMA
resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG);
priv->rx_dma_offset = 0;
#endif
@ -1315,7 +1456,7 @@ static void spislave_bind(struct spi_slave_ctrlr_s *ctrlr,
SPIS_DEV_CMDDATA(dev, false);
#ifdef ESP32S3_SPI_DMA
#ifdef CONFIG_ESP32S3_SPI_DMA
priv->rx_dma_offset = 0;
#endif
@ -1337,6 +1478,10 @@ static void spislave_bind(struct spi_slave_ctrlr_s *ctrlr,
priv->tx_length += num_bytes;
}
#ifdef CONFIG_ESP32S3_SPI_DMA
spislave_prepare_next_rx(priv);
#endif
/* Enable the CPU interrupt that is linked to the SPI Slave controller */
up_enable_irq(priv->config->irq);
@ -1380,11 +1525,8 @@ static void spislave_unbind(struct spi_slave_ctrlr_s *ctrlr)
resetbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG(priv->config->id));
#ifdef ESP32S3_SPI_DMA
if (priv->config->dma_used)
{
resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG);
}
#ifdef CONFIG_ESP32S3_SPI_DMA
resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG);
#endif
resetbits(priv->config->clk_bit, SYSTEM_PERIP_CLK_EN0_REG);