mirror of
https://github.com/apache/nuttx.git
synced 2025-01-13 02:48:37 +08:00
Merge ede365faad into aa0aecbd80
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Neo Xu
GitHub
commit
8f64fc8844
5 changed files with 1628 additions and 0 deletions
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@ -254,6 +254,7 @@ config ARCH_CORTEX_A53
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM64_HAVE_NEON
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select ARCH_HAVE_DEBUG
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config ARCH_CORTEX_A55
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bool
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@ -278,6 +279,7 @@ config ARCH_CORTEX_A57
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM64_HAVE_NEON
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select ARCH_HAVE_DEBUG
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config ARCH_CORTEX_A72
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bool
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@ -290,6 +292,7 @@ config ARCH_CORTEX_A72
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM64_HAVE_NEON
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select ARCH_HAVE_DEBUG
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config ARCH_CORTEX_R82
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bool
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@ -314,6 +317,7 @@ config ARCH_CPU_UNKNOWN
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM64_HAVE_NEON
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select ARCH_HAVE_DEBUG
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config ARCH_FAMILY
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string
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@ -126,3 +126,7 @@ endif
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ifeq ($(CONFIG_ARM64_SEMIHOSTING_HOSTFS),y)
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CMN_CSRCS += arm64_hostfs.c
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endif
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ifeq ($(CONFIG_ARCH_HAVE_DEBUG),y)
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CMN_CSRCS += arm64_hwdebug.c
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endif
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1274
arch/arm64/src/common/arm64_hwdebug.c
Normal file
1274
arch/arm64/src/common/arm64_hwdebug.c
Normal file
File diff suppressed because it is too large
Load diff
337
arch/arm64/src/common/arm64_hwdebug.h
Normal file
337
arch/arm64/src/common/arm64_hwdebug.h
Normal file
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@ -0,0 +1,337 @@
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/****************************************************************************
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* arch/arm64/src/common/arm64_hwdebug.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_HWDEBUG_H
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#define __ARCH_ARM64_SRC_COMMON_ARM64_HWDEBUG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/list.h>
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#include <nuttx/mutex.h>
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#include <nuttx/sched.h>
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#include <sched/sched.h>
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#include "arm64_arch.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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enum
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{
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BREAKPOINT_LEN_1 = 1,
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BREAKPOINT_LEN_2 = 2,
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BREAKPOINT_LEN_3 = 3,
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BREAKPOINT_LEN_4 = 4,
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BREAKPOINT_LEN_5 = 5,
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BREAKPOINT_LEN_6 = 6,
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BREAKPOINT_LEN_7 = 7,
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BREAKPOINT_LEN_8 = 8,
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};
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#define DBG_HOOK_HANDLED 0
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#define DBG_HOOK_ERROR 1
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/* BRK instruction trap from AArch64 state */
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#define ESR_ELX_BRK64_ISS_COMMENT_MASK 0xffff
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/* ISS field definitions for System instruction traps */
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#define ESR_ELX_SYS64_ISS_RES0_SHIFT 22
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#define ESR_ELX_SYS64_ISS_RES0_MASK \
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(UL(0x7) << ESR_ELX_SYS64_ISS_RES0_SHIFT)
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#define ESR_ELX_SYS64_ISS_DIR_MASK 0x1
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#define ESR_ELX_SYS64_ISS_DIR_READ 0x1
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#define ESR_ELX_SYS64_ISS_DIR_WRITE 0x0
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#define ESR_ELX_SYS64_ISS_RT_SHIFT 5
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#define ESR_ELX_SYS64_ISS_RT_MASK \
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(UL(0x1f) << ESR_ELX_SYS64_ISS_RT_SHIFT)
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#define ESR_ELX_SYS64_ISS_CRM_SHIFT 1
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#define ESR_ELX_SYS64_ISS_CRM_MASK \
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(UL(0xf) << ESR_ELX_SYS64_ISS_CRM_SHIFT)
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#define ESR_ELX_SYS64_ISS_CRN_SHIFT 10
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#define ESR_ELX_SYS64_ISS_CRN_MASK \
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(UL(0xf) << ESR_ELX_SYS64_ISS_CRN_SHIFT)
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#define ESR_ELX_SYS64_ISS_OP1_SHIFT 14
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#define ESR_ELX_SYS64_ISS_OP1_MASK \
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(UL(0x7) << ESR_ELX_SYS64_ISS_OP1_SHIFT)
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#define ESR_ELX_SYS64_ISS_OP2_SHIFT 17
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#define ESR_ELX_SYS64_ISS_OP2_MASK \
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(UL(0x7) << ESR_ELX_SYS64_ISS_OP2_SHIFT)
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#define ESR_ELX_SYS64_ISS_OP0_SHIFT 20
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#define ESR_ELX_SYS64_ISS_OP0_MASK \
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(UL(0x3) << ESR_ELX_SYS64_ISS_OP0_SHIFT)
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#define ESR_ELX_SYS64_ISS_SYS_MASK (ESR_ELX_SYS64_ISS_OP0_MASK | \
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ESR_ELX_SYS64_ISS_OP1_MASK | \
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ESR_ELX_SYS64_ISS_OP2_MASK | \
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ESR_ELX_SYS64_ISS_CRN_MASK | \
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ESR_ELX_SYS64_ISS_CRM_MASK)
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#define ESR_ELX_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
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(((op0) << ESR_ELX_SYS64_ISS_OP0_SHIFT) | \
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((op1) << ESR_ELX_SYS64_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELX_SYS64_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELX_SYS64_ISS_CRN_SHIFT) | \
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((crm) << ESR_ELX_SYS64_ISS_CRM_SHIFT))
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#define ESR_ELX_SYS64_ISS_SYS_OP_MASK (ESR_ELX_SYS64_ISS_SYS_MASK | \
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ESR_ELX_SYS64_ISS_DIR_MASK)
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#define ESR_ELX_SYS64_ISS_RT(esr) (((esr) & ESR_ELX_SYS64_ISS_RT_MASK) \
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>> ESR_ELX_SYS64_ISS_RT_SHIFT)
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/* Low-level stepping controls. */
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#define DBG_MDSCR_SS (1 << 0)
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#define DBG_SPSR_SS (1 << 21)
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/* MDSCR_EL1 enabling bits */
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#define DBG_MDSCR_KDE (1 << 13)
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#define DBG_MDSCR_MDE (1 << 15)
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#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
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/* Privilege Levels */
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#define AARCH64_BREAKPOINT_EL1 1
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#define AARCH64_BREAKPOINT_EL0 2
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/* Breakpoint */
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#define ARM_BREAKPOINT_EXECUTE 0
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/* Watchpoints */
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#define ARM_BREAKPOINT_LOAD 1
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#define ARM_BREAKPOINT_STORE 2
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#define AARCH64_ESR_ACCESS_MASK (1 << 6)
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/* Lengths */
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#define ARM_BREAKPOINT_LEN_1 0x1
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#define ARM_BREAKPOINT_LEN_2 0x3
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#define ARM_BREAKPOINT_LEN_3 0x7
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#define ARM_BREAKPOINT_LEN_4 0xf
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#define ARM_BREAKPOINT_LEN_5 0x1f
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#define ARM_BREAKPOINT_LEN_6 0x3f
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#define ARM_BREAKPOINT_LEN_7 0x7f
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#define ARM_BREAKPOINT_LEN_8 0xff
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/* Kernel stepping */
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#define ARM_KERNEL_STEP_NONE 0
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#define ARM_KERNEL_STEP_ACTIVE 1
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#define ARM_KERNEL_STEP_SUSPEND 2
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/* MDSCR_EL1
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* Monitor Debug System Control Register. It's the
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* main control register for the debug implementation.
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*
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* Initial value for MSDCR_EL1 when starting userspace,
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* which disables all debug exceptions.
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*
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* Instruction Breakpoint Exceptions (software breakpoints)
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* cannot be disabled and MDSCR does not affect
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* single-step behaviour.
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*/
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#define MSDCR_EL1_INITIAL_VALUE 0
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#define ARM64_MDSCR_EL1_SS (1u << 0)
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#define ARM64_MDSCR_EL1_SS_SHIFT 0
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#define ARM64_MDSCR_EL1_ERR (1u << 6)
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#define ARM64_MDSCR_EL1_ERR_SHIFT 6
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#define ARM64_MDSCR_EL1_TDCC (1u << 12)
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#define ARM64_MDSCR_EL1_TDCC_SHIFT 12
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#define ARM64_MDSCR_EL1_KDE (1u << 13)
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#define ARM64_MDSCR_EL1_KDE_SHIFT 13
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#define ARM64_MDSCR_EL1_HDE (1u << 14)
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#define ARM64_MDSCR_EL1_HDE_SHIFT 14
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#define ARM64_MDSCR_EL1_MDE (1u << 15)
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#define ARM64_MDSCR_EL1_MDE_SHIFT 15
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#define ARM64_MDSCR_EL1_RAZ_WI 0x000e0000lu
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#define ARM64_MDSCR_EL1_RAZ_WI_SHIFT 16
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#define ARM64_MDSCR_EL1_TDA (1u << 21)
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#define ARM64_MDSCR_EL1_TDA_SHIFT 21
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#define ARM64_MDSCR_EL1_INTDIS 0x000c0000u
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#define ARM64_MDSCR_EL1_INTDIS_SHIFT 22
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#define ARM64_MDSCR_EL1_TXU (1u << 26)
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#define ARM64_MDSCR_EL1_TXU_SHIFT 26
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#define ARM64_MDSCR_EL1_RXO (1u << 27)
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#define ARM64_MDSCR_EL1_RXO_SHIFT 27
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#define ARM64_MDSCR_EL1_TXfull (1u << 29)
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#define ARM64_MDSCR_EL1_TXfull_SHIFT 29
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#define ARM64_MDSCR_EL1_RXfull (1u << 30)
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#define ARM64_MDSCR_EL1_RXfull_SHIFT 30
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/* ID_AA64DFR0
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* Debug Feature Register 0. This register is used to query the system
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* for the debug capabilities present within the chip.
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*/
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#define ARM64_ID_AADFR0_EL1_DEBUG_VER 0x0000000000000Flu
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#define ARM64_ID_AADFR0_EL1_TRACE_VER 0x000000000000F0lu
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#define ARM64_ID_AADFR0_EL1_PMU_VER 0x00000000000F00lu
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/* Defines the amount of HW breakpoints. */
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#define ARM64_ID_AADFR0_EL1_BRPS 0x0000000000F000lu
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#define ARM64_ID_AADFR0_EL1_BRPS_SHIFT 12lu
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/* Defines the amount of HW data watchpoints. */
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#define ARM64_ID_AADFR0_EL1_WRPS 0x00000000F00000lu
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#define ARM64_ID_AADFR0_EL1_WRPS_SHIFT 20lu
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#define ARM64_ID_AADFR0_EL1_CTX_CMP 0x000000F0000000lu
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#define ARM64_ID_AADFR0_EL1_PMS_VER 0x00000F00000000lu
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/* Limits */
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#define ARM64_MAX_BRP 16
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#define ARM64_MAX_WRP 16
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#define ARM64_MAX_HBP_SLOTS (ARM64_MAX_BRP + ARM64_MAX_WRP)
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/* Virtual debug register bases. */
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#define AARCH64_DBG_REG_BVR 0
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#define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM64_MAX_BRP)
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#define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM64_MAX_BRP)
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#define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM64_MAX_WRP)
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/* Debug register names. */
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#define AARCH64_DBG_REG_NAME_BVR bvr
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#define AARCH64_DBG_REG_NAME_BCR bcr
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#define AARCH64_DBG_REG_NAME_WVR wvr
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#define AARCH64_DBG_REG_NAME_WCR wcr
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/* Accessor macros for the debug registers. */
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#define AARCH64_DBG_READ(N, REG, VAL) \
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do \
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{ \
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VAL = read_sysreg(dbg ## REG ## N ## _el1);\
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} while (0)
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#define AARCH64_DBG_WRITE(N, REG, VAL) \
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do \
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{ \
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write_sysreg(VAL, dbg ## REG ## N ## _el1); \
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} while (0)
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/****************************************************************************
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* Type Declarations
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****************************************************************************/
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struct arch_hw_breakpoint_ctrl
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{
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uint32_t __reserved : 19;
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uint32_t len : 8;
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uint32_t type : 2;
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uint32_t privilege : 2;
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uint32_t enabled : 1;
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};
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struct arch_hw_breakpoint
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{
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uint64_t address;
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uint64_t trigger;
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struct arch_hw_breakpoint_ctrl ctrl;
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int in_used;
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/* callback handler */
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debug_callback_t handle_fn;
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void *arg;
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int type;
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size_t size;
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};
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struct arm64_breakpoint_context
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{
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/* Breakpoint currently in use for each BRP. */
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struct arch_hw_breakpoint on_reg[ARM64_MAX_BRP];
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/* Number of BRP registers on this CPU. */
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int core_num;
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int disabled;
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};
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struct arm64_debugpoint
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{
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void *addr;
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int type;
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size_t size;
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int hbp_slot;
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int in_used;
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};
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struct arm64_debugpoint_slot
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{
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struct arm64_debugpoint slot[ARM64_MAX_HBP_SLOTS];
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};
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typedef int (*break_func_t)(struct regs_context *regs, uint64_t esr);
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struct break_inst_hook
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{
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break_func_t func;
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uint16_t imm;
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uint16_t mask;
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struct list_node entry;
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};
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static inline uint32_t encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
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{
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uint32_t val =
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(ctrl.len << 5) | (ctrl.type << 3) |
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(ctrl.privilege << 1) | ctrl.enabled;
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return val;
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}
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static inline void decode_ctrl_reg(uint32_t reg,
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struct arch_hw_breakpoint_ctrl *ctrl)
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{
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ctrl->enabled = reg & 0x1;
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reg >>= 1;
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ctrl->privilege = reg & 0x3;
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reg >>= 2;
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ctrl->type = reg & 0x3;
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reg >>= 2;
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ctrl->len = reg & 0xff;
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}
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/****************************************************************************
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* Public Function Prototypes
|
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****************************************************************************/
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void arm64_hwdebug_init(void);
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void arm64_hwdebug_secondary_init(void);
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#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_HWDEBUG_H */
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@ -45,6 +45,11 @@
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#ifdef CONFIG_ARCH_FPU
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#include "arm64_fpu.h"
|
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#endif
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|
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#ifdef CONFIG_ARCH_HAVE_DEBUG
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#include "arm64_hwdebug.h"
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#endif
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#include "arm64_internal.h"
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#include "chip.h"
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@ -218,4 +223,8 @@ void up_initialize(void)
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#endif
|
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#endif
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|
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#ifdef CONFIG_ARCH_HAVE_DEBUG
|
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arm64_hwdebug_init();
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#endif
|
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}
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||||
|
|
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|||
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