mirror of
https://github.com/apache/nuttx.git
synced 2025-01-13 09:49:21 +08:00
Merged in raiden00/nuttx_lora (pull request #876)
Initial support for STM32G0 configs: initial support for nucleo-g071rb Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
Gregory Nutt
parent
a82e8db811
commit
9c676a9e67
61 changed files with 9803 additions and 3789 deletions
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@ -317,6 +317,13 @@ config ARCH_CHIP_STM32L0
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---help---
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STMicro STM32L0 architectures (ARM Cortex-M0).
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config ARCH_CHIP_STM32G0
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bool "STMicro STM32 G0"
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select ARCH_CORTEXM0
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depends on EXPERIMENTAL
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---help---
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STMicro STM32G0 architectures (ARM Cortex-M0).
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config ARCH_CHIP_STM32F7
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bool "STMicro STM32 F7"
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select ARCH_CORTEXM7
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@ -677,7 +684,7 @@ config ARCH_CHIP
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default "sam34" if ARCH_CHIP_SAM34
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default "samv7" if ARCH_CHIP_SAMV7
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default "stm32" if ARCH_CHIP_STM32
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default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
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default "stm32f0l0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
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default "stm32f7" if ARCH_CHIP_STM32F7
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default "stm32h7" if ARCH_CHIP_STM32H7
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default "stm32l4" if ARCH_CHIP_STM32L4
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@ -909,7 +916,7 @@ endif
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if ARCH_CHIP_STM32
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source arch/arm/src/stm32/Kconfig
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endif
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if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
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if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
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source arch/arm/src/stm32f0l0/Kconfig
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endif
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if ARCH_CHIP_STM32F7
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@ -213,6 +213,39 @@
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# endif
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
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defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \
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defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \
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defined(CONFIG_ARCH_CHIP_STM32G071RB)
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* Two LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 12-channels */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 0 /* No CRC module */
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# define STM32_NRNG 0 /* No Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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/* STM32L EnergyLite Line ***********************************************************/
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/* STM32L073XX - With LCD
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@ -82,6 +82,8 @@
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# include <arch/stm32f0l0/stm32f0_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_STM32L0)
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# include <arch/stm32f0l0/stm32l0_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_STM32G0)
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# include <arch/stm32f0l0/stm32g0_irq.h>
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#else
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# error Unrecognized STM32 Cortex M0 family
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#endif
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142
arch/arm/include/stm32f0l0/stm32g0_irq.h
Normal file
142
arch/arm/include/stm32f0l0/stm32g0_irq.h
Normal file
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@ -0,0 +1,142 @@
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/****************************************************************************************************
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* arch/arm/include/stm32f0l0/stm32g0_irq.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <arch/stm32f0l0/chip.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32f0l0/irq.h
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */
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#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash */
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#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */
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#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */
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#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */
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#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */
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#define STM32_IRQ_UCPD12 (STM32_IRQ_EXTINT + 8) /* 8: UCPD1_2 */
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#define STM32_IRQ_EXTI32_33 (STM32_IRQ_EXTINT + 8) /* 8: EXTI_32_33 */
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#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */
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#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */
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#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */
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#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */
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#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */
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#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
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#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
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#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */
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#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
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#define STM32_IRQ_EXTI17_18 (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */
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#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
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#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
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#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
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#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
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#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
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#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
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#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */
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#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */
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#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */
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#define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */
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#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */
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#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */
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#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */
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#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */
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#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */
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#define STM32_IRQ_EXTI23 (STM32_IRQ_EXTINT + 23) /* 23: EXTI_23 */
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#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */
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#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */
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#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */
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#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */
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#define STM32_IRQ_EXTI25 (STM32_IRQ_EXTINT + 27) /* 27: EXTI_25 */
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#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */
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#define STM32_IRQ_EXTI26 (STM32_IRQ_EXTINT + 28) /* 28: EXTI_26 */
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#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
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#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
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#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 */
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#define STM32_IRQ_EXTI28 (STM32_IRQ_EXTINT + 29) /* 29: EXTI_28 */
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#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */
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#define STM32_IRQ_EXTI27 (STM32_IRQ_EXTINT + 30) /* 30: EXTI_27 */
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#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 31) /* 31: AES */
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#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */
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#define STM32_IRQ_NEXTINT (32)
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32G0_IRQ_H */
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@ -1,5 +1,5 @@
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/****************************************************************************************************
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* arch/arm/include/stm32f0l0/stm32_irq.h
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* arch/arm/include/stm32f0l0/stm32l0_irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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@ -3,13 +3,14 @@
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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comment "STM32F0/L0 Configuration Options"
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comment "STM32F0/L0/G0 Configuration Options"
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choice
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prompt "ST STM32F0/L0 Chip Selection"
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prompt "ST STM32F0/L0/G0 Chip Selection"
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default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0
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default ARCH_CHIP_STM32L073RZ if !ARCH_CHIP_STM32F0 && ARCH_CHIP_STM32L0
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depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
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default ARCH_CHIP_STM32L073RZ if ARCH_CHIP_STM32L0
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default ARCH_CHIP_STM32G071RB if ARCH_CHIP_STM32G0
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depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32F030C6
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bool "STM32F030C6"
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@ -449,6 +450,71 @@ config ARCH_CHIP_STM32F098VC
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select STM32F0L0_LOWVOLTLINE
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depends on ARCH_CHIP_STM32F0
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config ARCH_CHIP_STM32G071EB
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bool "STM32G071EB"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071G8
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bool "STM32G071G8"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071GB
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bool "STM32G071GB"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071G8XN
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bool "STM32G071G8XN"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071GBXN
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bool "STM32G071GBXN"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071K8
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bool "STM32G071K8"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071KB
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bool "STM32G071KB"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071K8XN
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bool "STM32G071K8XN"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071KBXN
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bool "STM32G071KBXN"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071C8
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bool "STM32G071C8"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071CB
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bool "STM32G071CB"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071R8
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bool "STM32G071R8"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071RB
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bool "STM32G071RB"
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select STM32F0L0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32L071K8
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bool "STM32L071K8"
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select ARCH_CHIP_STM32L071XX
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@ -624,9 +690,6 @@ config ARCH_CHIP_STM32L073RZ
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endchoice # ST STM32F0/L0 Chip Selection
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config ARCH_FAMILY_STM32F0XX
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bool
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choice
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prompt "Override Flash Size Designator"
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default STM32F0L0_FLASH_CONFIG_DEFAULT
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@ -709,6 +772,15 @@ config STM32F0L0_STM32F0
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select STM32F0L0_HAVE_TIM16
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select STM32F0L0_HAVE_TIM17
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select STM32F0L0_HAVE_ADC1_DMA
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select STM32F0L0_HAVE_IP_USART_V1
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select STM32F0L0_HAVE_IP_EXTI_V1
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config STM32F0L0_STM32G0
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bool
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default n
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select STM32F0L0_HAVE_DMAMUX
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select STM32F0L0_HAVE_IP_USART_V2
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select STM32F0L0_HAVE_IP_EXTI_V2
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config STM32F0L0_STM32L0
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bool
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@ -716,6 +788,8 @@ config STM32F0L0_STM32L0
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select STM32F0L0_ENERGYLITE
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select STM32F0L0_HAVE_VREFINT
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select STM32F0L0_HAVE_ADC1_DMA
|
||||
select STM32F0L0_HAVE_IP_USART_V1
|
||||
select STM32F0L0_HAVE_IP_EXTI_V1
|
||||
|
||||
config STM32F0L0_STM32F03X
|
||||
bool
|
||||
|
|
@ -950,6 +1024,10 @@ config STM32F0L0_HAVE_DAC1
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0_HAVE_DMAMUX
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0_HAVE_DMA2
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1014,6 +1092,24 @@ config STM32F0L0_HAVE_OPAMP4
|
|||
bool
|
||||
default n
|
||||
|
||||
# These are STM32 peripherals IP blocks
|
||||
|
||||
config STM32F0L0_HAVE_IP_USART_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0_HAVE_IP_USART_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0_HAVE_IP_EXTI_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0_HAVE_IP_EXTI_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
# These are the peripheral selections proper
|
||||
|
||||
config STM32F0L0_ADC1
|
||||
|
|
@ -1077,12 +1173,14 @@ config STM32F0L0_DMA1
|
|||
bool "DMA1"
|
||||
default n
|
||||
select ARCH_DMA
|
||||
select STM32F0L0_DMA
|
||||
|
||||
config STM32F0L0_DMA2
|
||||
bool "DMA2"
|
||||
default n
|
||||
depends on STM32F0L0_HAVE_DMA2
|
||||
select ARCH_DMA
|
||||
select STM32F0L0_DMA
|
||||
|
||||
config STM32F0L0_DAC1
|
||||
bool "DAC1"
|
||||
|
|
@ -1308,6 +1406,9 @@ config STM32F0L0_ADC
|
|||
config STM32F0L0_DAC
|
||||
bool
|
||||
|
||||
config STM32F0L0_DMA
|
||||
bool
|
||||
|
||||
config STM32F0L0_SPI
|
||||
bool
|
||||
|
||||
|
|
@ -1350,6 +1451,25 @@ endchoice # USART1 Driver Configuration
|
|||
|
||||
if STM32F0L0_USART1_SERIALDRIVER
|
||||
|
||||
config USART1_RXFIFO_THRES
|
||||
int "USART1 Rx FIFO Threshold"
|
||||
default 3
|
||||
range 0 5
|
||||
depends on STM32F0L0_HAVE_IP_USART_V2
|
||||
---help---
|
||||
Select the Rx FIFO threshold:
|
||||
|
||||
0 -> 1/8 full
|
||||
1 -> 1/4 full
|
||||
2 -> 1/2 full
|
||||
3 -> 3/4 full
|
||||
4 -> 7/8 full
|
||||
5 -> Full
|
||||
|
||||
Higher values mean lower interrupt rates and better CPU performance.
|
||||
Lower values may be needed at high BAUD rates to prevent Rx data
|
||||
overrun errors.
|
||||
|
||||
config USART1_RS485
|
||||
bool "RS-485 on USART1"
|
||||
default n
|
||||
|
|
@ -1387,6 +1507,25 @@ endchoice # USART2 Driver Configuration
|
|||
|
||||
if STM32F0L0_USART2_SERIALDRIVER
|
||||
|
||||
config USART2_RXFIFO_THRES
|
||||
int "USART2 Rx FIFO Threshold"
|
||||
default 3
|
||||
range 0 5
|
||||
depends on STM32F0L0_HAVE_IP_USART_V2
|
||||
---help---
|
||||
Select the Rx FIFO threshold:
|
||||
|
||||
0 -> 1/8 full
|
||||
1 -> 1/4 full
|
||||
2 -> 1/2 full
|
||||
3 -> 3/4 full
|
||||
4 -> 7/8 full
|
||||
5 -> Full
|
||||
|
||||
Higher values mean lower interrupt rates and better CPU performance.
|
||||
Lower values may be needed at high BAUD rates to prevent Rx data
|
||||
overrun errors.
|
||||
|
||||
config USART2_RS485
|
||||
bool "RS-485 on USART2"
|
||||
default n
|
||||
|
|
|
|||
|
|
@ -63,9 +63,13 @@ CMN_CSRCS += up_dumpnvic.c
|
|||
endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c stm32_dma_v1.c
|
||||
CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
|
||||
CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_rcc.c
|
||||
|
||||
ifeq ($(CONFIG_STM32F0L0_DMA),y)
|
||||
CHIP_CSRCS += stm32_dma_v1.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32F0L0_PWR),y)
|
||||
CHIP_CSRCS += stm32_pwr.c
|
||||
endif
|
||||
|
|
|
|||
162
arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h
Normal file
162
arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMAMUX_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define DMAMUX1 0
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */
|
||||
#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4)
|
||||
#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5)
|
||||
#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6)
|
||||
/* 0x01C-0x07C: Reserved */
|
||||
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */
|
||||
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */
|
||||
/* 0x088-0x0FC: Reserved */
|
||||
#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */
|
||||
#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */
|
||||
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */
|
||||
/* 0x148-0x3FC: Reserved */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET)
|
||||
#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* DMAMUX12 request line multiplexer channel x configuration register */
|
||||
|
||||
#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */
|
||||
#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT)
|
||||
#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
|
||||
#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */
|
||||
#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */
|
||||
#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
|
||||
#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT)
|
||||
#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */
|
||||
#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT)
|
||||
#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */
|
||||
#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT)
|
||||
|
||||
/* DMAMUX12 request line multiplexer interrupt channel status register */
|
||||
|
||||
#define DMAMUX1_CSR_SOF(x) (1 << x) /* Synchronization overrun event flag */
|
||||
|
||||
/* DMAMUX12 request line multiplexer interrupt clear flag register */
|
||||
|
||||
#define DMAMUX1_CFR_SOF(x) (1 << x) /* Clear synchronization overrun event flag */
|
||||
|
||||
/* DMAMUX12 request generator channel x configuration register */
|
||||
|
||||
#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
|
||||
/* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
|
||||
#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT)
|
||||
#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
|
||||
#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
|
||||
#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
|
||||
#define DMAMUX_RGCR_GPOL_MASK (7 << DMAMUX_RGCR_GPOL_SHIFT)
|
||||
#define DMAMUX_RGCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */
|
||||
#define DMAMUX_RGCR_GNBREQL_MASK (7 << DMAMUX_RGCR_GNBREQ_SHIFT)
|
||||
|
||||
/* DMAMUX12 request generator interrupt status register */
|
||||
|
||||
#define DMAMUX1_RGSR_SOF(x) (1 << x) /* Trigger overrun event flag */
|
||||
|
||||
/* DMAMUX12 request generator interrupt clear flag register */
|
||||
|
||||
#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */
|
||||
|
||||
/* DMA channel mapping
|
||||
*
|
||||
* XXXXX.DDD.CCCCCCCC
|
||||
* C - DMAMUX request
|
||||
* D - DMA controller
|
||||
* X - free bits
|
||||
*/
|
||||
|
||||
#define DMAMAP_MAP(d,c) ((d) << 8 | c)
|
||||
#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07)
|
||||
#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff)
|
||||
|
||||
/* Import DMAMUX map */
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_STM32G0)
|
||||
# include "chip/stm32g0_dmamux.h"
|
||||
#else
|
||||
# error "Unsupported STM32 M0 sub family"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMAMUX_H */
|
||||
|
|
@ -48,8 +48,10 @@
|
|||
# include "hardware/stm32f0_exti.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_exti.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_exti.h"
|
||||
#else
|
||||
# error "Unrecognized STM32F0/L0 EXTI"
|
||||
# error "Unrecognized STM32 M0 EXTI"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H */
|
||||
|
|
|
|||
|
|
@ -47,8 +47,10 @@
|
|||
# include "hardware/stm32f0_flash.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_flash.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_flash.h"
|
||||
#else
|
||||
# error "Unsupported STM32 FLASH"
|
||||
# error "Unsupported STM32 M0 FLASH"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H */
|
||||
|
|
|
|||
|
|
@ -37,20 +37,322 @@
|
|||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/* Include the appropriate GPIO definitions for this MCU GPIO version */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_gpio.h"
|
||||
# undef STM32_GPIO_VERY_LOW_SPEED /* No very low speed operation */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_gpio.h"
|
||||
# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation (400KHz) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */
|
||||
#else
|
||||
# error "Unrecognized STM32F0/L0 GPIO"
|
||||
# error "Unsupported STM32 M0 family"
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 6
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 7
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#if defined(STM32_GPIO_VERY_LOW_SPEED)
|
||||
# define GPIO_OSPEED_VERYLOW (0) /* Very low speed */
|
||||
# define GPIO_OSPEED_LOW (1) /* Low speed */
|
||||
# define GPIO_OSPEED_MEDIUM (2) /* Medium speed */
|
||||
# define GPIO_OSPEED_HIGH (3) /* High speed */
|
||||
#else
|
||||
# define GPIO_OSPEED_LOW (0) /* Low speed */
|
||||
# define GPIO_OSPEED_MEDIUM (1) /* Medium speed */
|
||||
# define GPIO_OSPEED_HIGH (3) /* High speed */
|
||||
#endif
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H */
|
||||
|
|
|
|||
|
|
@ -49,8 +49,10 @@
|
|||
# include "hardware/stm32f05xf07xf09x_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_memorymap.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 memory map"
|
||||
# error "Unsupported STM32 M0 memory map"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H */
|
||||
|
|
|
|||
|
|
@ -51,8 +51,10 @@
|
|||
# include "hardware/stm32f09x_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 pin map"
|
||||
# error "Unsupported STM32 M0 pin map"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */
|
||||
|
|
|
|||
|
|
@ -48,8 +48,10 @@
|
|||
# include "hardware/stm32f0_pwr.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_pwr.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_pwr.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 PWR"
|
||||
# error "Unsupported STM32 M0 PWR"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */
|
||||
|
|
|
|||
|
|
@ -48,8 +48,10 @@
|
|||
# include "hardware/stm32f0_rcc.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_rcc.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32 RCC"
|
||||
# error "Unsupported STM32 M0 RCC"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H */
|
||||
|
|
|
|||
|
|
@ -48,8 +48,10 @@
|
|||
# include "hardware/stm32f0_syscfg.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_syscfg.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "hardware/stm32g0_syscfg.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 SYSCFG"
|
||||
# error "Unsupported STM32 M0 SYSCFG"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H */
|
||||
|
|
|
|||
|
|
@ -44,12 +44,12 @@
|
|||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_uart.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_uart.h"
|
||||
#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1)
|
||||
# include "hardware/stm32_uart_v1.h"
|
||||
#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2)
|
||||
# include "hardware/stm32_uart_v2.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 UART"
|
||||
# error "Unsupported STM32 M0 USART"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
|
@ -34,8 +34,8 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V1_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V1_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -313,4 +313,4 @@
|
|||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_V1_H */
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -33,21 +33,21 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H
|
||||
#define __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V2_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V2_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
|
|
@ -61,75 +61,80 @@
|
|||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */
|
||||
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
/* No UART 3 in L0 */
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART4_CR1 (STM32_USART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART4_CR2 (STM32_USART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART4_CR3 (STM32_USART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART4_BRR (STM32_USART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART4_GTPR (STM32_USART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART4_RTOR (STM32_USART4_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART4_RQR (STM32_USART4_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART4_GTPR (STM32_USART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART4_ISR (STM32_USART4_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART4_ICR (STM32_USART4_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART4_RDR (STM32_USART4_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART4_TDR (STM32_USART4_BASE+STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_USART5_CR1 (STM32_USART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART5_CR2 (STM32_USART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART5_CR3 (STM32_USART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART5_BRR (STM32_USART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART5_GTPR (STM32_USART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART5_RTOR (STM32_USART5_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART5_RQR (STM32_USART5_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART5_GTPR (STM32_USART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART5_ISR (STM32_USART5_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART5_ICR (STM32_USART5_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART5_RDR (STM32_USART5_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART5_TDR (STM32_USART5_BASE+STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART4_PRESC (STM32_USART4_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in low-power mode */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
|
|
@ -140,33 +145,37 @@
|
|||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: Word length */
|
||||
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */
|
||||
#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT)
|
||||
# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT)
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */
|
||||
#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT)
|
||||
# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT)
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */
|
||||
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length, bit 1 */
|
||||
#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO mode enable */
|
||||
#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */
|
||||
#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */
|
||||
|
||||
#define USART_CR1_ALLINTS \
|
||||
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\
|
||||
USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE)
|
||||
|
||||
/* F0 Compatibility definitions */
|
||||
|
||||
#define USART_CR1_M0 USART_CR1_M
|
||||
#define USART_CR1_M1 0
|
||||
USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\
|
||||
USART_CR1_TXFEIE | USART_CR1_RXFFIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */
|
||||
#define USART_CR2_DISNSS (1 << 3) /* Bit 3: Ignore NSS pin input */
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-/4-bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
|
|
@ -175,6 +184,7 @@
|
|||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
|
|
@ -187,17 +197,15 @@
|
|||
# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */
|
||||
# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */
|
||||
#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT)
|
||||
#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */
|
||||
#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT)
|
||||
# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT)
|
||||
#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */
|
||||
#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT)
|
||||
#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT)
|
||||
# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT)
|
||||
#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */
|
||||
#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT)
|
||||
|
||||
/* F0 Compatibility definitions */
|
||||
|
||||
#define USART_CR2_SWAP 0
|
||||
#define USART_CR2_ADD_MASK USART_CR2_ADD8_MASK
|
||||
# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT)
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
|
|
@ -219,35 +227,50 @@
|
|||
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */
|
||||
#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */
|
||||
#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT)
|
||||
#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */
|
||||
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
|
||||
# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */
|
||||
# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */
|
||||
# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */
|
||||
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
|
||||
# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT)
|
||||
#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */
|
||||
#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT)
|
||||
# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT)
|
||||
# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */
|
||||
# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */
|
||||
# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */
|
||||
# define USART_CR3_RXFTCFG_75PCT (3 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 3/4 full */
|
||||
# define USART_CR3_RXFTCFG_88PCT (4 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 7/8 full */
|
||||
# define USART_CR3_RXFTCFG_FULL (5 << USART_CR3_RXFTCFG_SHIFT) /* RXIFO full */
|
||||
#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */
|
||||
#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */
|
||||
#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT)
|
||||
# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT)
|
||||
# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */
|
||||
# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */
|
||||
# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */
|
||||
# define USART_CR3_TXFTCFG_75PCT (3 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 3/4 full */
|
||||
# define USART_CR3_TXFTCFG_88PCT (4 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 7/8 full */
|
||||
# define USART_CR3_TXFTCFG_EMPY (5 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO empty */
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/
|
||||
#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT)
|
||||
#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */
|
||||
#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT)
|
||||
#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/
|
||||
#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT)
|
||||
# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT)
|
||||
|
||||
/* Request register */
|
||||
|
||||
|
|
@ -261,7 +284,7 @@
|
|||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */
|
||||
#define USART_ISR_NE (1 << 2) /* Bit 2: Noise detected flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */
|
||||
|
|
@ -272,17 +295,23 @@
|
|||
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */
|
||||
#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */
|
||||
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */
|
||||
#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */
|
||||
#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from low-power mode flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */
|
||||
#define USART_ISR_TXFE (1 << 23) /* Bit 23: TXFIFO Empty */
|
||||
#define USART_ISR_RXFF (1 << 24) /* Bit 24: RXFIFO Full */
|
||||
#define USART_ISR_TCBGT (1 << 25) /* Bit 25: Transmission complete before guard time flag */
|
||||
#define USART_ISR_RXFT (1 << 26) /* Bit 26: RXFIFO threshold flag */
|
||||
#define USART_ISR_TXFT (1 << 27) /* Bit 27: TXFIFO threshold flag */
|
||||
|
||||
#define USART_ISR_ALLBITS (0x007fdfff)
|
||||
#define USART_ISR_ALLBITS (0x0fffffff)
|
||||
|
||||
/* Interrupt flag clear register */
|
||||
|
||||
|
|
@ -291,42 +320,44 @@
|
|||
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
|
||||
#define USART_ICR_TXFECF (1 << 5) /* Bit 5: TXFIFO empty clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */
|
||||
#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7: Transmission complete before Guard time clear flag */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
|
||||
#define USART_ICR_UDRCF (1 << 13) /* Bit 13:SPI slave underrun clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from low-power mode clear flag */
|
||||
|
||||
#define USART_ICR_ALLBITS (0x00121b5f)
|
||||
#define USART_ICR_ALLBITS (0x00123b7f)
|
||||
|
||||
/* Receive data register */
|
||||
|
||||
#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */
|
||||
#define USART_RDR_SHIFT (0) /* Bits 0-8: Receive data value */
|
||||
#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
|
||||
|
||||
/* Transmit data register */
|
||||
|
||||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */
|
||||
#define USART_TDR_SHIFT (0) /* Bits 0-8: Transmit data value */
|
||||
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
|
||||
|
||||
/* Compatibility definitions ********************************************************/
|
||||
/* F1/F2/F4 Status register */
|
||||
/* Prescaler register */
|
||||
|
||||
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
|
||||
#define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */
|
||||
#define USART_PRESC_MASK (15 << USART_PRESC_SHIFT)
|
||||
# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */
|
||||
# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */
|
||||
# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */
|
||||
# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */
|
||||
# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */
|
||||
# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */
|
||||
# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */
|
||||
# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */
|
||||
# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */
|
||||
# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */
|
||||
# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
|
||||
# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
|
||||
|
||||
#define USART_SR_PE USART_ISR_PE /* Parity Error */
|
||||
#define USART_SR_FE USART_ISR_FE /* Framing error */
|
||||
#define USART_SR_NE USART_ISR_NF /* Noise detected flag */
|
||||
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
|
||||
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
|
||||
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
|
||||
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
|
||||
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
|
||||
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
|
||||
#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS USART_ISR_ALLBITS
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H */
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_V2_H */
|
||||
|
|
@ -1,336 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#undef STM32_GPIO_VERY_LOW_SPEED /* No very low speed operation */
|
||||
#define STM32_HAVE_PORTF 1 /* If STM32_NPORTS > 5, then have GPIOF */
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_2MHz (0) /* x0: 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_10MHz (1) /* 01: 10 MHz Medium speed */
|
||||
#define GPIO_OSPEED_50MHz (3) /* 11: 50 MHz High speed */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H */
|
||||
74
arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h
Normal file
74
arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32g0_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* DMAMUX1 mapping ****************************************************/
|
||||
|
||||
/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7 */
|
||||
|
||||
#define DMAMUX1_REQ_GEN0 (1)
|
||||
#define DMAMUX1_REQ_GEN1 (2)
|
||||
#define DMAMUX1_REQ_GEN2 (3)
|
||||
#define DMAMUX1_REQ_GEN3 (4)
|
||||
#define DMAMUX1_ADC1 (5)
|
||||
#define DMAMUX1_AES_IN (6)
|
||||
#define DMAMUX1_AES_OUT (7)
|
||||
|
||||
/* TODO: ... */
|
||||
|
||||
/* DMAP for DMA1 */
|
||||
|
||||
#define DMAMAP_DMA1_REGGEN0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0)
|
||||
#define DMAMAP_DMA1_REGGEN1 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1)
|
||||
#define DMAMAP_DMA1_REGGEN2 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2)
|
||||
#define DMAMAP_DMA1_REGGEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3)
|
||||
#define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1)
|
||||
|
||||
/* TODO: ... */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_DMAMUX_H */
|
||||
103
arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h
Normal file
103
arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32G0_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32G0_EXTI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_NEXTI 18
|
||||
#define STM32_EXTI_MASK 0xffffffff
|
||||
|
||||
#define STM32_EXTI_BIT(n) (1 << (n))
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger selection register 1 */
|
||||
#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger selection register 1 */
|
||||
#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */
|
||||
#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising edge pending register 1 */
|
||||
#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling edge pending register 1 */
|
||||
|
||||
#define STM32_EXTI_EXTICR_OFFSET(p) (0x0060 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External interrupt selection register 1 */
|
||||
#define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* External interrupt selection register 2 */
|
||||
#define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* External interrupt selection register 3 */
|
||||
#define STM32_EXTI_EXTICR4_OFFSET 0x006c /* External interrupt selection register 4 */
|
||||
#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU wakeup with interrupt mask register 1 */
|
||||
#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU wakeup with event mask register 1 */
|
||||
#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU wakeup with interrupt mask register 2 */
|
||||
#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU wakeup with event mask register 2 */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET)
|
||||
#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET)
|
||||
#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET)
|
||||
#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET)
|
||||
#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET)
|
||||
#define STM32_EXTI_EXTICR(p) (STM32_EXTI_BASE + STM32_EXTI_EXTICR_OFFSET(p))
|
||||
#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET)
|
||||
#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET)
|
||||
#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET)
|
||||
#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* EXTI external interrupt configuration register 1-4 */
|
||||
|
||||
#define EXTI_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define EXTI_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define EXTI_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define EXTI_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
/* 0100: Reserved */
|
||||
#define EXTI_EXTICR_PORTF (5) /* 0100: PF[x] pin */
|
||||
|
||||
#define EXTI_EXTICR_PORT_MASK (0xff)
|
||||
#define EXTI_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 3)
|
||||
#define EXTI_EXTICR_EXTI_MASK(g) (EXTI_EXTICR_PORT_MASK << (EXTI_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
/* TODO */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32G0_EXTI_H */
|
||||
107
arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h
Normal file
107
arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32g0_flash.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32_FLASH_PCROP1ASE_OFFSET 0x0024
|
||||
#define STM32_FLASH_PCROP1AER_OFFSET 0x0028
|
||||
#define STM32_FLASH_WPR1AR_OFFSET 0x002c
|
||||
#define STM32_FLASH_WPR1BR_OFFSET 0x0030
|
||||
#define STM32_FLASH_WPR1BSR_OFFSET 0x0034
|
||||
#define STM32_FLASH_PCROP1BER_OFFSET 0x0038
|
||||
#define STM32_FLASH_SECR_OFFSET 0x0080
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
|
||||
#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1ASE (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASE_OFFSET)
|
||||
#define STM32_FLASH_PCROP1AER (STM32_FLASHIF_BAER+STM32_FLASH_PCROP1AER_OFFSET)
|
||||
#define STM32_FLASH_WPR1AR (STM32_FLASHIF_BASE+STM32_FLASH_WPR1AR_OFFSET)
|
||||
#define STM32_FLASH_WPR1BR (STM32_FLASHIF_BASE+STM32_FLASH_WPR1BR_OFFSET)
|
||||
#define STM32_FLASH_WPR1BSR (STM32_FLASHIF_BASE+STM32_FLASH_WPR1BSR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1BER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET)
|
||||
#define STM32_FLASH_SECR (STM32_FLASHIF_BASE+STM32_FLASH_SECR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-2: Flash memory access latency*/
|
||||
#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
|
||||
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
|
||||
#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
|
||||
/* Bit 10:Reserved */
|
||||
#define FLASH_ACR_ICRST (1 << 11) /* Bit 11:Instruction cache reset */
|
||||
/* Bits 12-15: Reserved */
|
||||
#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Main Flash memory area empty */
|
||||
/* Bit 17: Reserved */
|
||||
#define FLASH_ACR_DBGSWEN (1 << 18) /* Bit 18: Debug access software enable */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* TODO */
|
||||
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_FLASH_H */
|
||||
140
arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h
Normal file
140
arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32g0_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* ST32F05XF07X Address Blocks ******************************************************/
|
||||
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
/* 0x60000000-0xdfffffff: Reserved */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M0 block */
|
||||
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
|
||||
/* Code Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0001ffff: Aliased boot memory */
|
||||
/* 0x00020000-0x07ffffff: Reserved */
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0801ffff: FLASH memory */
|
||||
/* 0x08020000-0x1fffd7ff: Reserved */
|
||||
#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff77ff: System memory */
|
||||
#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff7fff: Option bytes */
|
||||
|
||||
/* Peripheral Base Addresses ********************************************************/
|
||||
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000b3ff: APB1 */
|
||||
/* 0x4000b400-0x4000ffff: Reserved */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40015800: APB2 */
|
||||
/* 0x40015c00-0x4001ffff: Reserved */
|
||||
#define STM32_AHB_BASE 0x40020000 /* 0x40020000-0x400263ff: AHB */
|
||||
/* 0x40026400-0x4fffffff: Reserved */
|
||||
#define STM32_IOPORT_BASE 0x50000000 /* 0x50000000-0x50001fff: IOPORT */
|
||||
|
||||
/* APB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
|
||||
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
|
||||
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
|
||||
#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
|
||||
#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
|
||||
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 */
|
||||
#define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */
|
||||
#define STM32_LPTIM1_BASE 0x40007C00 /* 0x40007c00-0x40007fff LPTIM1 */
|
||||
#define STM32_LPUART1_BASE 0x40008000 /* 0x40008000-0x400083ff LPUART1 */
|
||||
#define STM32_LPTIM2_BASE 0x40009400 /* 0x40009400-0x400097ff LPTIM2 */
|
||||
#define STM32_UCPD1_BASE 0x4000a000 /* 0x4000a000-0x4000a3ff UCPD1 */
|
||||
#define STM32_UCPD2_BASE 0x4000a400 /* 0x4000a400-0x4000a7ff UCPD2 */
|
||||
#define STM32_TAMP_BASE 0x4000b000 /* 0x4000b000-0x4000b3ff TAMP */
|
||||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG */
|
||||
/* EXTI ??? */
|
||||
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 1 */
|
||||
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
|
||||
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
|
||||
#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */
|
||||
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
|
||||
#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
|
||||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
|
||||
#define STM32_DMAMUX_BASE 0x40020800 /* 0x40020800-0x40020bff: DMAMUX */
|
||||
#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */
|
||||
#define STM32_EXTI_BASE 0x40021800 /* 0x40021800-0x40021bff: EXTI */
|
||||
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */
|
||||
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
|
||||
#define STM32_RNG_BASE 0x40025000 /* 0x40025000-0x400253ff: RNG */
|
||||
#define STM32_AES_BASE 0x40026000 /* 0x40026000-0x400263ff: AES */
|
||||
|
||||
/* AHB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
|
||||
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
|
||||
#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
|
||||
#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */
|
||||
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
|
||||
|
||||
/* Cortex-M4 Base Addresses *********************************************************/
|
||||
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
|
||||
* address range
|
||||
*/
|
||||
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32G0_MEMORYMAP_H */
|
||||
122
arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h
Normal file
122
arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32g0_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions.
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* CAN1_RX connects vis PA11 on some board, then the following definitions should
|
||||
* appear in the board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
*
|
||||
* The driver will then automatically configre PB6 as the I2C1 SCL pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
* Additional effort is required to select specific GPIO options such as frequency,
|
||||
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
|
||||
* pins in this file.
|
||||
*/
|
||||
|
||||
/* TODO: ADC */
|
||||
|
||||
/* TODO: DAC */
|
||||
|
||||
/* TODO: I2C */
|
||||
|
||||
/* TODO: Clocking */
|
||||
|
||||
/* TODO: RTC */
|
||||
|
||||
/* TODO: SPI */
|
||||
|
||||
/* TODO: Timers */
|
||||
|
||||
/* TODO: USART */
|
||||
|
||||
#define GPIO_USART1_CTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)
|
||||
#define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_USART1_RTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_USART1_RTS_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_USART1_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN5)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_USART1_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN4)
|
||||
|
||||
#define GPIO_USART2_CTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_USART2_CTS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN3)
|
||||
#define GPIO_USART2_RTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_USART2_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN14)
|
||||
#define GPIO_USART2_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
|
||||
|
||||
/* TODO: USART3 */
|
||||
|
||||
/* TODO: USART4 */
|
||||
|
||||
/* TODO: LPTIM */
|
||||
|
||||
/* TODO: LPUART */
|
||||
|
||||
/* TODO: COMP */
|
||||
|
||||
/* TODO: UCPD */
|
||||
|
||||
/* TODO: CEC */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PINMAP_H */
|
||||
186
arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h
Normal file
186
arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32g0_pwr.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
|
||||
#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
|
||||
#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */
|
||||
#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */
|
||||
#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */
|
||||
#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */
|
||||
#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */
|
||||
#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET)
|
||||
#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET)
|
||||
#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET)
|
||||
#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET)
|
||||
#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET)
|
||||
#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET)
|
||||
#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET)
|
||||
#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET)
|
||||
#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET)
|
||||
#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET)
|
||||
#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET)
|
||||
#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET)
|
||||
#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET)
|
||||
#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET)
|
||||
#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET)
|
||||
#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET)
|
||||
#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET)
|
||||
#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET)
|
||||
#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET)
|
||||
#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET)
|
||||
#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET)
|
||||
#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET)
|
||||
#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Power control register 1 */
|
||||
|
||||
#define PWR_CR1_LPMS_SHIFT (0) /* Bits 0-2: Low-power mode selection */
|
||||
#define PWR_CR1_LPMS_MASK (7 << PWR_CR1_LPMS_SHIFT)
|
||||
# define PWR_CR1_LPMS_STOP1MR (0 << PWR_CR1_LPMS_SHIFT) /* Stop 1 mode with main regulator (MR) */
|
||||
# define PWR_CR1_LPMS_STOP1LPR (1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 mode with low-power regulator (LPR) */
|
||||
# define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
|
||||
# define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
|
||||
# define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
|
||||
#define PWR_CR1_FPDSTOP (1 << 3) /* Bit 3: Flash memory powered down during Stop mode */
|
||||
#define PWR_CR1_FPDLPRUN (1 << 4) /* Bit 4: Flash memory powered down during Low-power run mode */
|
||||
#define PWR_CR1_FPDLPSLP (1 << 5) /* Bit 5: Flash memory powered down during Low-power sleep mode */
|
||||
#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */
|
||||
#define PWR_CR1_VOS_SHIFT (9) /* Bits 9-10: Voltage scaling range selection */
|
||||
#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT)
|
||||
# define PWR_CR1_VOS_RANGE1 (1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 */
|
||||
# define PWR_CR1_VOS_RANGE2 (2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 */
|
||||
#define PWR_CR1_LPR (1 << 14) /* Bit 14: Low-power run */
|
||||
|
||||
/* Power control register 2 */
|
||||
|
||||
#define PWR_CR2_PVDE (1 << 0) /* Bit 0: Power voltage detector enable */
|
||||
#define PWR_CR2_PVDFT_SHIFT (1) /* Bits 1-3: Power voltage detector falling threshold selection */
|
||||
#define PWR_CR2_PVDFT_MASK (7 << PWR_CR2_PLS_SHIFT)
|
||||
#define PWR_CR2_PVDRT_SHIFT (4) /* Bits 4-6: Power voltage detector rising threshold selection */
|
||||
#define PWR_CR2_PVDRT_MASK (7 << PWR_CR2_PLS_SHIFT)
|
||||
|
||||
/* Power control register 3 */
|
||||
|
||||
#define PWR_CR3_EWUP1 (1 << 0) /* Bit 0: Enable Wakeup pin WKUP1 */
|
||||
#define PWR_CR3_EWUP2 (1 << 1) /* Bit 1: Enable Wakeup pin WKUP2 */
|
||||
#define PWR_CR3_EWUP3 (1 << 2) /* Bit 2: Enable Wakeup pin WKUP3 */
|
||||
#define PWR_CR3_EWUP4 (1 << 3) /* Bit 3: Enable Wakeup pin WKUP4 */
|
||||
#define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */
|
||||
#define PWR_CR3_EWUP6 (1 << 5) /* Bit 5: Enable Wakeup pin WKUP6 */
|
||||
#define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */
|
||||
#define PWR_CR3_ULPEN (1 << 9) /* Bit 9: Ultra-low-power enable */
|
||||
#define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
|
||||
#define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */
|
||||
|
||||
/* Power control register 4 */
|
||||
|
||||
#define PWR_CR4_WP1 (1 << 0) /* Bit 0: Wakeup pin WKUP1 polarity */
|
||||
#define PWR_CR4_WP2 (1 << 1) /* Bit 1: Wakeup pin WKUP2 polarity */
|
||||
#define PWR_CR4_WP3 (1 << 2) /* Bit 2: Wakeup pin WKUP3 polarity */
|
||||
#define PWR_CR4_WP4 (1 << 3) /* Bit 3: Wakeup pin WKUP4 polarity */
|
||||
#define PWR_CR4_WP5 (1 << 4) /* Bit 4: Wakeup pin WKUP5 polarity */
|
||||
#define PWR_CR4_VBE (1 << 8) /* Bit 8: Vbat battery charging enable */
|
||||
#define PWR_CR4_VBRS (1 << 9) /* Bit 9: Vbat battery charging resistor selection */
|
||||
# define PWR_CR4_VBRS_5k 0 /* 0: 5k resistor */
|
||||
# define PWR_CR4_VBRS_1k5 PWR_CR4_VBRS /* 1: 1k5 resistor */
|
||||
|
||||
/* Power status register 1 */
|
||||
|
||||
#define PWR_SR1_WUF1 (1 << 0) /* Bit 0: Wakeup flag 1 */
|
||||
#define PWR_SR1_WUF2 (1 << 1) /* Bit 1: Wakeup flag 2 */
|
||||
#define PWR_SR1_WUF3 (1 << 2) /* Bit 2: Wakeup flag 3 */
|
||||
#define PWR_SR1_WUF4 (1 << 3) /* Bit 3: Wakeup flag 4 */
|
||||
#define PWR_SR1_WUF5 (1 << 4) /* Bit 4: Wakeup flag 5 */
|
||||
#define PWR_SR1_WUF6 (1 << 5) /* Bit 5: Wakeup flag 6 */
|
||||
#define PWR_SR1_SBF (1 << 8) /* Bit 8: Standby flag */
|
||||
#define PWR_SR1_WUFI (1 << 15) /* Bit 15: Wakeup internal flag */
|
||||
|
||||
/* Power status register 2 */
|
||||
|
||||
#define PWR_SR2_FLASHRDY (1 << 7) /* Bit 7: Flash ready flag */
|
||||
#define PWR_SR2_REGLPS (1 << 8) /* Bit 8: Low power regulator started */
|
||||
#define PWR_SR2_REGLPF (1 << 9) /* Bit 9: Low power regulator flag */
|
||||
#define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */
|
||||
#define PWR_SR2_PVDO (1 << 11) /* Bit 11: Power voltage detector output */
|
||||
|
||||
/* Power status clear register */
|
||||
|
||||
#define PWR_SCR_CWUF1 (1 << 0) /* Bit 0: Clear wakeup flag 1 */
|
||||
#define PWR_SCR_CWUF2 (1 << 1) /* Bit 1: Clear wakeup flag 2 */
|
||||
#define PWR_SCR_CWUF3 (1 << 2) /* Bit 2: Clear wakeup flag 3 */
|
||||
#define PWR_SCR_CWUF4 (1 << 3) /* Bit 3: Clear wakeup flag 4 */
|
||||
#define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */
|
||||
#define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_PWR_H */
|
||||
362
arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h
Normal file
362
arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32g0_rcc.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000C /* PLL clock configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock Source Interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock Source Interrupt Flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock Source Interrupt Clear register */
|
||||
#define STM32_RCC_IOPRSTR_OFFSET 0x0024 /* GPIO reset register */
|
||||
#define STM32_RCC_AHBRSTR_OFFSET 0x0028 /* AHB peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR_OFFSET 0x002C /* APB1 Peripheral reset register */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0030 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_IOPENR_OFFSET 0x0034 /* GPIO clock enable register */
|
||||
#define STM32_RCC_AHBENR_OFFSET 0x0038 /* AHB Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x003C /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0040 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_IOPSMEN_OFFSET 0x0044 /* GPIO clock enable in Sleep mode register */
|
||||
#define STM32_RCC_AHBSMENR_OFFSET 0x0048 /* AHB peripheral clock enable in Sleep mode register */
|
||||
#define STM32_RCC_APB1SMENR_OFFSET 0x004C /* APB1 peripheral clock enable in Sleep mode register */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0050 /* APB2 peripheral clock enable in Sleep mode register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0054 /* Clock configuration register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x005c /* RTC domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0060 /* Control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_IOPRSTR (STM32_RCC_BASE+STM32_RCC_IOPRSTR_OFFSET)
|
||||
#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_IOPENR (STM32_RCC_BASE+STM32_RCC_IOPENR_OFFSET)
|
||||
#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_IOPSMEN (STM32_RCC_BASE+STM32_RCC_IOPSMEN_OFFSET)
|
||||
#define STM32_RCC_AHBSMENR (STM32_RCC_BASE+STM32_RCC_AHBSMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR (STM32_RCC_BASE+STM32_RCC_APB1SMENR_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
/* Bits 0-7: Reserved */
|
||||
#define RCC_CR_HSION (1 << 8) /* Bit 8: Internal high speed clock enable */
|
||||
#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: Internal high speed clock enable for some IP kernels */
|
||||
#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: Internal high speed clock ready flag */
|
||||
#define RCC_CR_HSIDIV_SHIFT (11) /* Bit 11: Internal high speed clock divider */
|
||||
#define RCC_CR_HSIDIV_MASK (7 << RCC_CR_HSIDIV_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External high speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External high speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External high speed clock bypass */
|
||||
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock security system enable */
|
||||
/* Bits 20-23: Reserved */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
/* Bits 26-27: Reserved */
|
||||
|
||||
/* Internal clock sources calibration register */
|
||||
|
||||
#define RCC_ICSCR_HSICAL_SHIFT (0) /* Bits 0-7: Internal high speed clock calibration */
|
||||
#define RCC_ICSCR_HSICAL_MASK (0xff << RCC_ICSCR_HSICAL_SHIFT)
|
||||
#define RCC_ICSCR_HSITRIM_SHIFT (8) /* Bits 8-14: High speed internal clock trimming */
|
||||
#define RCC_ICSCR_HSITRIM_MASK (0x7f << RCC_ICSCR_HSITRIM_SHIFT)
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 001: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 010: PLL selected as system clock */
|
||||
# define RCC_CFGR_SW_LSI (3 << RCC_CFGR_SW_SHIFT) /* 011: LSI selected as system clock */
|
||||
# define RCC_CFGR_SW_LSE (4 << RCC_CFGR_SW_SHIFT) /* 100: LSE selected as system clock */
|
||||
#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 001: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 010: PLL oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_LSI (3 << RCC_CFGR_SWS_SHIFT) /* 011: LSI used as system clock */
|
||||
# define RCC_CFGR_SWS_LSE (4 << RCC_CFGR_SWS_SHIFT) /* 100: LSE used as system clock */
|
||||
#define RCC_CFGR_HPRE_SHIFT (8) /* Bits 8-11: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
#define RCC_CFGR_PPRE1_SHIFT (12) /* Bits 12-14: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
/* Bits 15-23: Reserved */
|
||||
#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-26: Microcontroller clock output selection */
|
||||
#define RCC_CFGR_MCOSEL_MASK (7 << RCC_CFGR_MCOSEL_SHIFT)
|
||||
/* Bit 27: Reserved */
|
||||
#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */
|
||||
#define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
|
||||
/* PLL clock configuration register */
|
||||
|
||||
#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bits 0-1: PLL entry clock source */
|
||||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NOCLK (0 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Division factor M of the PLL input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (7 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
#define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT)
|
||||
/* Bit 7: Reserved */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: PLL frequency multiplication factor N */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
#define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT)
|
||||
/* Bit 15: Reserved */
|
||||
#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: PLLPCLK clock output enable */
|
||||
#define RCC_PLLCFG_PLLP_SHIFT (17) /* Bits 17-21: PLL VCO division factor P for PLLPCLK clock output */
|
||||
#define RCC_PLLCFG_PLLP_MASK (0x1f << RCC_PLLCFG_PLLP_SHIFT)
|
||||
#define RCC_PLLCFG_PLLP(n) ((n+1) << RCC_PLLCFG_PLLP_SHIFT) /* n=2,...,32 */
|
||||
/* Bits 22-23: Reserved */
|
||||
#define RCC_PLLCFG_PLLQEN (1 << 24) /* Bit 24: PLLQCLK clock output enable */
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (25) /* Bits 25-27: Division factor Q of the PLL input clock divider */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (7 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
#define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
#define RCC_PLLCFG_PLLREN (1 << 28) /* Bit 28: PLLRCLK clock output enable */
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (29) /* Bits 29-31: Division factor R of the PLL input clock divider */
|
||||
#define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
#define RCC_PLLCFG_PLLR(n) ((n) << RCC_PLLCFG_PLLR_SHIFT)
|
||||
|
||||
/* TODO: Clock Source Interrupt enable register */
|
||||
|
||||
/* TODO: Clock Source Interrupt Flag register */
|
||||
|
||||
/* TODO: Clock Source Interrupt Clear register */
|
||||
|
||||
/* GPIO reset register */
|
||||
|
||||
#define RCC_IOPRSTR_IOPARST (1 << 0) /* Bit 0: IO port A reset */
|
||||
#define RCC_IOPRSTR_IOPBRST (1 << 1) /* Bit 1: IO port B reset */
|
||||
#define RCC_IOPRSTR_IOPCRST (1 << 2) /* Bit 2: IO port C reset */
|
||||
#define RCC_IOPRSTR_IOPDRST (1 << 3) /* Bit 3: IO port D reset */
|
||||
/* Bits 4: Reserved */
|
||||
#define RCC_IOPRSTR_IOPFRST (1 << 5) /* Bit 5: IO port F reset */
|
||||
|
||||
/* AHB peripheral reset register */
|
||||
|
||||
#define RCC_AHBRSTR_DMA1RST (1 << 0) /* Bit 0: DMA 1 reset */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define RCC_AHBRSTR_MIFRST (1 << 8) /* Bit 8: Memory interface reset */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBRSTR_CRCRST (1 << 12) /* Bit 12: Memory interface reset */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBRSTR_AESRST (1 << 16) /* Bit 16: Touch sensing reset */
|
||||
/* Bit 17: Reserved */
|
||||
#define RCC_AHBRSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */
|
||||
/* Bits 6-13: Reserved */
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
|
||||
/* Bits 15-16: Reserved */
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
|
||||
#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */
|
||||
#define RCC_APB1RSTR_LPUSART1RST (1 << 20) /* Bit 20: Low-power USART 1 reset */
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
|
||||
/* Bit 23: Reserved */
|
||||
#define RCC_APB1RSTR_CECRST (1 << 24) /* Bit 24: HDMI CEC reset */
|
||||
#define RCC_APB1RSTR_UCPD1RST (1 << 25) /* Bit 25: UCPD1 reset */
|
||||
#define RCC_APB1RSTR_UCPD2RST (1 << 26) /* Bit 26: UCPD2 reset */
|
||||
#define RCC_APB1RSTR_DBGRST (1 << 27) /* Bit 27: DBG reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: PWR reset */
|
||||
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 reset */
|
||||
#define RCC_APB1RSTR_LPTIM2RST (1 << 30) /* Bit 30: LPTIM2 reset */
|
||||
#define RCC_APB1RSTR_LPTIM1RST (1 << 31) /* Bit 31: LPTIM1 reset */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: System configuration controller reset */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 timer reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
|
||||
/* Bit 13: Reserved */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
|
||||
#define RCC_APB2RSTR_TIM14RST (1 << 15) /* Bit 15: TIM14 timer reset */
|
||||
#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 timer reset */
|
||||
#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 timer reset */
|
||||
#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 timer reset */
|
||||
/* Bit 19: Reserved */
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 20) /* Bit 20: ADC1 timer reset */
|
||||
|
||||
/* GPIO clock enable register */
|
||||
|
||||
#define RCC_IOPENR_IOPAEN (1 << 0) /* Bit 0: IO port A enable */
|
||||
#define RCC_IOPENR_IOPBEN (1 << 1) /* Bit 1: IO port B enable */
|
||||
#define RCC_IOPENR_IOPCEN (1 << 2) /* Bit 2: IO port C enable */
|
||||
#define RCC_IOPENR_IOPDEN (1 << 3) /* Bit 3: IO port D enable */
|
||||
/* Bits 4: Reserved */
|
||||
#define RCC_IOPENR_IOPFEN (1 << 5) /* Bit 5: IO port F enable */
|
||||
|
||||
/* AHB Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA 1 enable */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define RCC_AHBENR_MIFEN (1 << 8) /* Bit 8: Memory interface enable */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBENR_CRCEN (1 << 12) /* Bit 12: Memory interface enable */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBENR_AESEN (1 << 16) /* Bit 16: Touch sensing enable */
|
||||
/* Bit 17: Reserved */
|
||||
#define RCC_AHBENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 enable */
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 enable */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 enable */
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 enable */
|
||||
/* Bits 6-13: Reserved */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 enable */
|
||||
/* Bits 15-16: Reserved */
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 enable */
|
||||
#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 enable */
|
||||
#define RCC_APB1ENR_LPUSART1EN (1 << 20) /* Bit 20: Low-power USART 1 enable */
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 enable */
|
||||
/* Bit 23: Reserved */
|
||||
#define RCC_APB1ENR_CECEN (1 << 24) /* Bit 24: HDMI CEC enable */
|
||||
#define RCC_APB1ENR_UCPD1EN (1 << 25) /* Bit 25: UCPD1 enable */
|
||||
#define RCC_APB1ENR_UCPD2EN (1 << 26) /* Bit 26: UCPD2 enable */
|
||||
#define RCC_APB1ENR_DBGEN (1 << 27) /* Bit 27: DBG enable */
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: PWR enable */
|
||||
#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 enable */
|
||||
#define RCC_APB1ENR_LPTIM2EN (1 << 30) /* Bit 30: LPTIM2 enable */
|
||||
#define RCC_APB1ENR_LPTIM1EN (1 << 31) /* Bit 31: LPTIM1 enable */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 timer enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 enable */
|
||||
/* Bit 13: Reserved */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 enable */
|
||||
#define RCC_APB2ENR_TIM14EN (1 << 15) /* Bit 15: TIM14 timer enable */
|
||||
#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 timer enable */
|
||||
#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 timer enable */
|
||||
#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 timer enable */
|
||||
/* Bit 19: Reserved */
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 20) /* Bit 20: ADC1 timer enable */
|
||||
|
||||
/* GPIO clock enable in Sleep mode register */
|
||||
|
||||
/* AHB peripheral clock enable in Sleep mode register */
|
||||
|
||||
#define RCC_AHBSMENR_DMA1SMEN (1 << 0) /* Bit 0: DMA 1 enable in Sleep mode */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define RCC_AHBSMENR_MIFSMEN (1 << 8) /* Bit 8: Memory interface enable in Sleep mode */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBSMENR_CRCSMEN (1 << 12) /* Bit 12: Memory interface enable in Sleep mode */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBSMENR_AESSMEN (1 << 16) /* Bit 16: Touch sensing enable in Sleep mode */
|
||||
/* Bit 17: Reserved */
|
||||
#define RCC_AHBSMENR_RNGSMEN (1 << 18) /* Bit 18: Random number generator module enable in Sleep mode */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* TODO: APB1 peripheral clock enable in Sleep mode register */
|
||||
|
||||
/* TODO: APB2 peripheral clock enable in Sleep mode register */
|
||||
|
||||
/* TODO: Clock configuration register */
|
||||
|
||||
/* TODO: RTC domain control register */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: LSI enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: ready */
|
||||
/* Bits 2-22: Reserved */
|
||||
#define RCC_CSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */
|
||||
/* Bit 24: Reserved */
|
||||
#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Options bytes loading reset flag */
|
||||
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: software reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: IWDG reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_RCC_H */
|
||||
316
arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h
Normal file
316
arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h
Normal file
|
|
@ -0,0 +1,316 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32g0_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register */
|
||||
#define STM32_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register */
|
||||
#define STM32_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register */
|
||||
#define STM32_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register */
|
||||
#define STM32_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register */
|
||||
#define STM32_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register */
|
||||
#define STM32_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register */
|
||||
#define STM32_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register */
|
||||
#define STM32_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register */
|
||||
#define STM32_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register */
|
||||
#define STM32_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register */
|
||||
#define STM32_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register */
|
||||
#define STM32_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register */
|
||||
#define STM32_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register */
|
||||
#define STM32_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register */
|
||||
#define STM32_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register */
|
||||
#define STM32_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register */
|
||||
#define STM32_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register */
|
||||
#define STM32_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register */
|
||||
#define STM32_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register */
|
||||
#define STM32_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register */
|
||||
#define STM32_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register */
|
||||
#define STM32_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register */
|
||||
#define STM32_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register */
|
||||
#define STM32_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register */
|
||||
#define STM32_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register */
|
||||
#define STM32_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register */
|
||||
#define STM32_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register */
|
||||
#define STM32_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register */
|
||||
#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register */
|
||||
#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register */
|
||||
#define STM32_SYSCFG_ITLINE31_OFFSET 0x00fc /* SYSCFG interrupt line 31 status register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_ITLINE0 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE0_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE1 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE1_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE2 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE2_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE3 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE3_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE4 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE4_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE5 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE5_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE6 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE6_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE7 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE7_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE8 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE8_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE9 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE9_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE10 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE10_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE11 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE11_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE12 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE12_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE13 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE13_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE14 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE14_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE15 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE15_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE16 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE16_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE17 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE17_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE18 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE18_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE19 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE19_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE20 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE20_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE21 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE21_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE22 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE22_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE23 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE23_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE24 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE24_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE25 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE25_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE26 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE26_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE27 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE27_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE28 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE28_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE31 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE31_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
|
||||
# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
|
||||
# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
|
||||
# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
|
||||
/* Bit 2: Reserved */
|
||||
#define SYSCFG_CFGR1_PA11_RMP (1 << 3) /* Bit 3: PA11 remapping bit */
|
||||
#define SYSCFG_CFGR1_PA12_RMP (1 << 4) /* Bit 4: PA12 remapping bit */
|
||||
#define SYSCFG_CFGR1_IRPOL (1 << 5) /* Bit 5: IR output polarity selection */
|
||||
#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */
|
||||
#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
|
||||
# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
|
||||
# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
|
||||
# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
|
||||
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: IO analog switch voltage booster enable */
|
||||
#define SYSCFG_CFGR1_UCPD1STROBE (1 << 9) /* Bit 9: UCPD1 pull-down configuration strobe */
|
||||
#define SYSCFG_CFGR1_UCPD2STROBE (1 << 10) /* Bit 10: UCPD2 pull-down configuration strobe */
|
||||
/* Bits 11-15: Reserved */
|
||||
#define SYSCFG_CFGR1_I2CPB6FMP (1 << 16) /* Bit 16: */
|
||||
#define SYSCFG_CFGR1_I2CPB7FMP (1 << 17) /* Bit 17: */
|
||||
#define SYSCFG_CFGR1_I2CPB8FMP (1 << 18) /* Bit 18: */
|
||||
#define SYSCFG_CFGR1_I2CPB9FMP (1 << 19) /* Bit 19: */
|
||||
#define SYSCFG_CFGR1_I2C1FMP (1 << 20) /* Bit 20: */
|
||||
#define SYSCFG_CFGR1_I2C2FMP (1 << 21) /* Bit 21: */
|
||||
#define SYSCFG_CFGR1_I2CPA9FMP (1 << 22) /* Bit 22: */
|
||||
#define SYSCFG_CFGR1_I2CPA10FMP (1 << 23) /* Bit 23: */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* SYSCFG interrupt line 0 status register */
|
||||
|
||||
#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */
|
||||
|
||||
/* SYSCFG interrupt line 1 status register */
|
||||
|
||||
#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */
|
||||
|
||||
/* SYSCFG interrupt line 2 status register */
|
||||
|
||||
#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */
|
||||
#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */
|
||||
|
||||
/* SYSCFG interrupt line 3 status register */
|
||||
|
||||
#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */
|
||||
#define SYSCFG_ITLINE3_FLASH_ECC (1 << 1) /* Bit 1: Flash interface ECC interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 4 status register */
|
||||
|
||||
#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 5 status register */
|
||||
|
||||
#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */
|
||||
#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 6 status register */
|
||||
|
||||
#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */
|
||||
#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 7 status register */
|
||||
|
||||
#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 8 status register */
|
||||
|
||||
#define SYSCFG_ITLINE8_UCPD1 (1 << 0) /* Bit 0: UCPD1 interrupt request pending */
|
||||
#define SYSCFG_ITLINE8_UCPD2 (1 << 1) /* Bit 1: UCPD2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 9 status register */
|
||||
|
||||
#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 10 status register */
|
||||
|
||||
#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 11 status register */
|
||||
|
||||
#define SYSCFG_ITLINE11_DMAMUX (1 << 0) /* Bit 0: DMAMUX interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 1) /* Bit 1: DMA1 channel 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 2) /* Bit 2: DMA1 channel 5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 3) /* Bit 3: DMA1 channel 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 4) /* Bit 4: DMA1 channel 7 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 12 status register */
|
||||
|
||||
#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */
|
||||
#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */
|
||||
#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 13 status register */
|
||||
|
||||
#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 14 status register */
|
||||
|
||||
#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 15 status register */
|
||||
|
||||
#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 16 status register */
|
||||
|
||||
#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 17 status register */
|
||||
|
||||
#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */
|
||||
#define SYSCFG_ITLINE17_LPTIM1 (1 << 2) /* Bit 2: Low-power timer 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 18 status register */
|
||||
|
||||
#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE18_LPTIM2 (1 << 1) /* Bit 1: Low-power timer 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 19 status register */
|
||||
|
||||
#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 20 status register */
|
||||
|
||||
#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 21 status register */
|
||||
|
||||
#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 22 status register */
|
||||
|
||||
#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 23 status register */
|
||||
|
||||
#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */
|
||||
|
||||
/* SYSCFG interrupt line 24 status register */
|
||||
|
||||
#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 25 status register */
|
||||
|
||||
#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 26 status register */
|
||||
|
||||
#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 27 status register */
|
||||
|
||||
#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 28 status register */
|
||||
|
||||
#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 29 status register */
|
||||
|
||||
#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_LPUART1 (1 << 2) /* Bit 2: LPUART1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 30 status register */
|
||||
|
||||
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
|
||||
|
||||
/* SYSCFG interrupt line 31 status register */
|
||||
|
||||
#define SYSCFG_ITLINE30_RNG (1 << 0) /* Bit 0: RNG interrupt request pending */
|
||||
#define SYSCFG_ITLINE30_AES (1 << 1) /* Bit 1: AES interrupt request pending */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_SYSCFG_H */
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_NEXTI 31 /* REVISIT: Taken from the F0, probably incorrect */
|
||||
#define STM32_NEXTI 29
|
||||
#define STM32_EXTI_MASK 0xffffffff
|
||||
|
||||
#define STM32_EXTI_BIT(n) (1 << (n))
|
||||
|
|
|
|||
|
|
@ -1,345 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation (400KHz) */
|
||||
#undef STM32_HAVE_PORTF /* If STM32_NPORTS > 5, then have GPIOH */
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 6
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 7
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_400KHz (0) /* 400 kHz Very low speed */
|
||||
#define GPIO_OSPEED_2MHz (1) /* 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_10MHz (2) /* 10 MHz Medium speed */
|
||||
#define GPIO_OSPEED_40MHz (3) /* 40 MHz High speed */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H */
|
||||
|
|
@ -294,7 +294,6 @@
|
|||
#define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_USART1_RTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_USART1_RTS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
|
||||
|
|
@ -340,6 +339,4 @@
|
|||
|
||||
/* TODO: LPUART */
|
||||
|
||||
/* TODO: LCD */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H */
|
||||
|
|
|
|||
|
|
@ -263,12 +263,12 @@
|
|||
/* GPIO reset register */
|
||||
|
||||
#define RCC_IOPRSTR_IOPARST (1 << 0) /* Bit 0: IO port A reset */
|
||||
#define RCC_IOPRSTR_IOPBRST (1 << 1) /* Bit 0: IO port B reset */
|
||||
#define RCC_IOPRSTR_IOPCRST (1 << 2) /* Bit 0: IO port C reset */
|
||||
#define RCC_IOPRSTR_IOPDRST (1 << 3) /* Bit 0: IO port D reset */
|
||||
#define RCC_IOPRSTR_IOPERST (1 << 4) /* Bit 0: IO port E reset */
|
||||
#define RCC_IOPRSTR_IOPBRST (1 << 1) /* Bit 1: IO port B reset */
|
||||
#define RCC_IOPRSTR_IOPCRST (1 << 2) /* Bit 3: IO port C reset */
|
||||
#define RCC_IOPRSTR_IOPDRST (1 << 3) /* Bit 4: IO port D reset */
|
||||
#define RCC_IOPRSTR_IOPERST (1 << 4) /* Bit 4: IO port E reset */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define RCC_IOPRSTR_IOPHRST (1 << 7) /* Bit 0: IO port H reset */
|
||||
#define RCC_IOPRSTR_IOPHRST (1 << 7) /* Bit 5: IO port H reset */
|
||||
|
||||
/* AHB peripheral reset register */
|
||||
|
||||
|
|
@ -278,7 +278,7 @@
|
|||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBRSTR_CRCRST (1 << 12) /* Bit 12: Memory interface reset */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBRSTR_TSCRST (1 << 12) /* Bit 12: Touch sensing reset */
|
||||
#define RCC_AHBRSTR_TSCRST (1 << 16) /* Bit 16: Touch sensing reset */
|
||||
/* Bits 17-19: Reserved */
|
||||
#define RCC_AHBRSTR_RNGRST (1 << 20) /* Bit 20: Random number generator module reset */
|
||||
/* Bits 21-23: Reserved */
|
||||
|
|
@ -333,12 +333,12 @@
|
|||
/* GPIO clock enable register */
|
||||
|
||||
#define RCC_IOPENR_IOPAEN (1 << 0) /* Bit 0: IO port A clock enable */
|
||||
#define RCC_IOPENR_IOPBEN (1 << 1) /* Bit 0: IO port B clock enable */
|
||||
#define RCC_IOPENR_IOPCEN (1 << 2) /* Bit 0: IO port C clock enable */
|
||||
#define RCC_IOPENR_IOPDEN (1 << 3) /* Bit 0: IO port D clock enable */
|
||||
#define RCC_IOPENR_IOPEEN (1 << 4) /* Bit 0: IO port E clock enable */
|
||||
#define RCC_IOPENR_IOPBEN (1 << 1) /* Bit 1: IO port B clock enable */
|
||||
#define RCC_IOPENR_IOPCEN (1 << 2) /* Bit 2: IO port C clock enable */
|
||||
#define RCC_IOPENR_IOPDEN (1 << 3) /* Bit 3: IO port D clock enable */
|
||||
#define RCC_IOPENR_IOPEEN (1 << 4) /* Bit 4: IO port E clock enable */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define RCC_IOPENR_IOPHEN (1 << 7) /* Bit 0: IO port H clock enable */
|
||||
#define RCC_IOPENR_IOPHEN (1 << 7) /* Bit 5: IO port H clock enable */
|
||||
|
||||
/* AHB Peripheral Clock enable register */
|
||||
|
||||
|
|
@ -403,12 +403,12 @@
|
|||
/* GPIO clock enable in Sleep mode register */
|
||||
|
||||
#define RCC_IOPSMENR_IOPASMEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPBSMEN (1 << 1) /* Bit 0: IO port B clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPCSMEN (1 << 2) /* Bit 0: IO port C clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPDSMEN (1 << 3) /* Bit 0: IO port D clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPESMEN (1 << 4) /* Bit 0: IO port E clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPBSMEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPCSMEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPDSMEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPESMEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define RCC_IOPSMENR_IOPHSMEN (1 << 7) /* Bit 0: IO port H clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPHSMEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
|
||||
|
||||
/* AHB peripheral clock enable in Sleep mode register */
|
||||
|
||||
|
|
@ -484,7 +484,7 @@
|
|||
# define RCC_CCIPR_USART2SEL_SYSCLK (1 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_HSI16 (2 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_LSE (3 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
/* Bits 4-9: Reserved */
|
||||
/* Bits 4-9: Reserved */
|
||||
#define RCC_CCIPR_LPUART1SEL_SHIFT (10) /* Bits 10-11: LPUART1 clock source selection */
|
||||
#define RCC_CCIPR_LPUART1SEL_MASK (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_APB (0 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
|
|
@ -519,7 +519,7 @@
|
|||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: LSI enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: ready */
|
||||
/* Bits 3-7: Reserved */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define RCC_CSR_LSEON (1 << 8) /* Bit 8: LSE enable */
|
||||
#define RCC_CSR_LSERDY (1 << 9) /* Bit 9: LSE ready */
|
||||
#define RCC_CSR_LSEBPY (1 << 10) /* Bit 10: LSE bypass */
|
||||
|
|
|
|||
|
|
@ -64,6 +64,10 @@
|
|||
* the DMA requests for each channel.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_HAVE_DMAMUX
|
||||
# error DMAMUX not supported yet
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -55,6 +55,17 @@
|
|||
#include "stm32_gpio.h"
|
||||
#include "stm32_exti.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
|
||||
# define STM32_EXTI_FTSR STM32_EXTI_FTSR1
|
||||
# define STM32_EXTI_RTSR STM32_EXTI_RTSR1
|
||||
# define STM32_EXTI_IMR STM32_EXTI_IMR1
|
||||
# define STM32_EXTI_EMR STM32_EXTI_EMR1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
|
@ -81,6 +92,7 @@ static struct gpio_callback_s g_gpio_callbacks[16];
|
|||
* Interrupt Service Routines - Dispatchers
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1)
|
||||
static int stm32_exti_multiisr(int irq, void *context, void *arg,
|
||||
int first, int last)
|
||||
{
|
||||
|
|
@ -124,6 +136,56 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg,
|
|||
|
||||
return ret;
|
||||
}
|
||||
#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
|
||||
static int stm32_exti_multiisr(int irq, void *context, void *arg,
|
||||
int first, int last)
|
||||
{
|
||||
uint32_t rpr;
|
||||
uint32_t fpr;
|
||||
int pin;
|
||||
int ret = OK;
|
||||
|
||||
/* Examine the state of each pin in the group.
|
||||
* NOTE: We don't distinguish rising/falling edge!
|
||||
*/
|
||||
|
||||
rpr = getreg32(STM32_EXTI_RPR1);
|
||||
fpr = getreg32(STM32_EXTI_FPR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
for (pin = first; pin <= last; pin++)
|
||||
{
|
||||
/* Is an interrupt pending on this pin? */
|
||||
|
||||
uint32_t mask = (1 << pin);
|
||||
if (((rpr & mask) != 0) || ((fpr & mask) != 0))
|
||||
{
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(mask, STM32_EXTI_RPR1);
|
||||
putreg32(mask, STM32_EXTI_FPR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
if (g_gpio_callbacks[pin].callback != NULL)
|
||||
{
|
||||
xcpt_t callback = g_gpio_callbacks[pin].callback;
|
||||
void *cbarg = g_gpio_callbacks[pin].arg;
|
||||
int tmp;
|
||||
|
||||
tmp = callback(irq, context, cbarg);
|
||||
if (tmp < 0)
|
||||
{
|
||||
ret = tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int stm32_exti01_isr(int irq, void *context, void *arg)
|
||||
{
|
||||
|
|
@ -241,6 +303,7 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
|
||||
stm32_configgpio(pinset);
|
||||
|
||||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32_EXTI_RTSR,
|
||||
|
|
|
|||
|
|
@ -54,7 +54,11 @@
|
|||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#include "hardware/stm32_syscfg.h"
|
||||
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1)
|
||||
# include "hardware/stm32_syscfg.h"
|
||||
#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
|
||||
# include "hardware/stm32_exti.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
|
@ -70,18 +74,19 @@ const uint32_t g_gpiobase[STM32_NPORTS] =
|
|||
STM32_GPIOB_BASE, /* Two GPIO ports, GPIOA-B */
|
||||
#endif
|
||||
#if STM32_NPORTS > 2
|
||||
STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-D*/
|
||||
STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C*/
|
||||
#endif
|
||||
#if STM32_NPORTS > 3
|
||||
STM32_GPIOD_BASE, /* Four GPIO ports, GPIOA-D */
|
||||
#endif
|
||||
#if STM32_NPORTS > 4
|
||||
STM32_GPIOE_BASE, /* Five GPIO ports, GPIOA-E */
|
||||
#if defined(STM32_GPIOE_BASE)
|
||||
STM32_GPIOE_BASE, /* GPIOE */
|
||||
#endif
|
||||
#if STM32_NPORTS > 5 && defined(STM32_HAVE_PORTF)
|
||||
STM32_GPIOF_BASE, /* Six GPIO ports, GPIOA-F */
|
||||
#elif STM32_NPORTS > 5 && !defined(STM32_HAVE_PORTF)
|
||||
STM32_GPIOH_BASE, /* Six GPIO ports, GPIOA-E, H */
|
||||
#if defined(STM32_GPIOF_BASE)
|
||||
STM32_GPIOF_BASE, /* GPIOF */
|
||||
#endif
|
||||
#if defined(STM32_GPIOH_BASE)
|
||||
STM32_GPIOH_BASE, /* GPIOH */
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -252,32 +257,32 @@ int stm32_configgpio(uint32_t cfgset)
|
|||
{
|
||||
default:
|
||||
#if defined(STM32_GPIO_VERY_LOW_SPEED)
|
||||
case GPIO_SPPED_VERYLOW: /* 400KHz Very Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
case GPIO_SPPED_VERYLOW: /* Very Low speed output */
|
||||
setting = GPIO_OSPEED_VERYLOW;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_LOW: /* 2 MHz Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
case GPIO_SPEED_LOW: /* Low speed output */
|
||||
setting = GPIO_OSPEED_LOW;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_MEDIUM: /* 10 MHz Medium speed output */
|
||||
setting = GPIO_OSPEED_10MHz;
|
||||
case GPIO_SPEED_MEDIUM: /* Medium speed output */
|
||||
setting = GPIO_OSPEED_MEDIUM;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_HIGH: /* 40 MHz High speed output */
|
||||
setting = GPIO_OSPEED_40MHz;
|
||||
case GPIO_SPEED_HIGH: /* High speed output */
|
||||
setting = GPIO_OSPEED_HIGH;
|
||||
break;
|
||||
#else
|
||||
case GPIO_SPEED_LOW: /* 2 MHz Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
case GPIO_SPEED_LOW: /* Low speed output */
|
||||
setting = GPIO_OSPEED_LOW;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_MEDIUM: /* 10 MHz Medium speed output */
|
||||
setting = GPIO_OSPEED_10MHz;
|
||||
case GPIO_SPEED_MEDIUM: /* Medium speed output */
|
||||
setting = GPIO_OSPEED_MEDIUM;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_HIGH: /* 50 MHz High speed output */
|
||||
setting = GPIO_OSPEED_50MHz;
|
||||
case GPIO_SPEED_HIGH: /* High speed output */
|
||||
setting = GPIO_OSPEED_HIGH;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -313,19 +318,10 @@ int stm32_configgpio(uint32_t cfgset)
|
|||
|
||||
if ((cfgset & GPIO_EXTI) != 0)
|
||||
{
|
||||
/* "In STM32 F1 the selection of the EXTI line source is performed through
|
||||
* the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
|
||||
* selection is done through the EXTIx bits in the SYSCFG_EXTICRx registers.
|
||||
*
|
||||
* "Only the mapping of the EXTICRx registers has been changed, without any
|
||||
* changes to the meaning of the EXTIx bits. However, the range of EXTI
|
||||
* bits values has been extended to 0b1000 to support the two ports added
|
||||
* in F2, port H and I (in F1 series the maximum value is 0b0110)."
|
||||
*/
|
||||
|
||||
uint32_t regaddr;
|
||||
int shift;
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V1)
|
||||
/* Set the bits in the SYSCFG EXTICR register */
|
||||
|
||||
regaddr = STM32_SYSCFG_EXTICR(pin);
|
||||
|
|
@ -335,6 +331,19 @@ int stm32_configgpio(uint32_t cfgset)
|
|||
regval |= (((uint32_t)port) << shift);
|
||||
|
||||
putreg32(regval, regaddr);
|
||||
#elif defined(CONFIG_STM32F0L0_HAVE_IP_EXTI_V2)
|
||||
/* Set the bits in the EXTI EXTICR register */
|
||||
|
||||
regaddr = STM32_EXTI_EXTICR(pin);
|
||||
regval = getreg32(regaddr);
|
||||
shift = EXTI_EXTICR_EXTI_SHIFT(pin);
|
||||
regval &= ~(EXTI_EXTICR_PORT_MASK << shift);
|
||||
regval |= (((uint32_t)port) << shift);
|
||||
|
||||
putreg32(regval, regaddr);
|
||||
#else
|
||||
# error unknown EXTI IP core
|
||||
#endif
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
|
|
|||
|
|
@ -1,9 +1,8 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0/stm32_lowputc.c
|
||||
*
|
||||
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -39,368 +38,16 @@
|
|||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select USART parameters for the selected console */
|
||||
|
||||
#ifdef HAVE_CONSOLE
|
||||
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# ifdef CONFIG_USART1_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART2_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# ifdef CONFIG_USART2_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART3_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
|
||||
# ifdef CONFIG_USART3_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
|
||||
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART4_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART4_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART4_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP
|
||||
# ifdef CONFIG_USART4_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
|
||||
# if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART5_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART5_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART5_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART5_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART5_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART5_2STOP
|
||||
# ifdef CONFIG_USART5_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR
|
||||
# if (CONFIG_USART5_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* CR1 settings */
|
||||
|
||||
# if STM32_CONSOLE_BITS == 9
|
||||
# define USART_CR1_M0_VALUE USART_CR1_M0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# elif STM32_CONSOLE_BITS == 7
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE USART_CR1_M1
|
||||
# else /* 8 bits */
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# endif
|
||||
|
||||
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
|
||||
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
|
||||
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
|
||||
# else /* no parity */
|
||||
# define USART_CR1_PARITY_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR1_CLRBITS \
|
||||
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
|
||||
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
|
||||
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
|
||||
USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
|
||||
|
||||
# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
|
||||
|
||||
/* CR2 settings */
|
||||
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
|
||||
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
|
||||
USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
|
||||
USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
|
||||
USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
|
||||
|
||||
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
|
||||
|
||||
/* CR3 settings */
|
||||
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
|
||||
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
|
||||
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
|
||||
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
|
||||
USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
|
||||
|
||||
# define USART_CR3_SETBITS 0
|
||||
|
||||
# undef USE_OVER8
|
||||
|
||||
/* Calculate USART BAUD rate divider */
|
||||
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / UARTDIV
|
||||
* UARTDIV = fCK / baud
|
||||
*
|
||||
* In case of oversampling by 8, the equation is:
|
||||
*
|
||||
* baud = 2 * fCK / UARTDIV
|
||||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if STM32_USARTDIV8 > 100
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_lowputc(char ch)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#if defined(CONFIG_STM32F0L0_HAVE_IP_USART_V1)
|
||||
# include "stm32_lowputc_v1.c"
|
||||
#elif defined(CONFIG_STM32F0L0_HAVE_IP_USART_V2)
|
||||
# include "stm32_lowputc_v2.c"
|
||||
#else
|
||||
# error "Unsupported STM32 M0 serial"
|
||||
#endif
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the USART used for the serial
|
||||
* console. Its purpose is to get the console output availabe as soon
|
||||
* as possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_USART)
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
uint32_t cr;
|
||||
#endif
|
||||
|
||||
/* Setup clocking and GPIO pins for all configured USARTs */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART1
|
||||
/* Enable USART APB2 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART1_TX);
|
||||
stm32_configgpio(GPIO_USART1_RX);
|
||||
|
||||
#ifdef CONFIG_USART1_RS485
|
||||
stm32_configgpio(GPIO_USART1_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART2
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART2_TX);
|
||||
stm32_configgpio(GPIO_USART2_RX);
|
||||
|
||||
#ifdef CONFIG_USART2_RS485
|
||||
stm32_configgpio(GPIO_USART2_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART3
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART3_TX);
|
||||
stm32_configgpio(GPIO_USART3_RX);
|
||||
|
||||
#ifdef CONFIG_USART3_RS485
|
||||
stm32_configgpio(GPIO_USART3_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART4
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART4_TX);
|
||||
stm32_configgpio(GPIO_USART4_RX);
|
||||
|
||||
#ifdef CONFIG_USART4_RS485
|
||||
stm32_configgpio(GPIO_USART4_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART5
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART5_TX);
|
||||
stm32_configgpio(GPIO_USART5_RX);
|
||||
|
||||
#ifdef CONFIG_USART5_RS485
|
||||
stm32_configgpio(GPIO_USART5_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Configure CR2 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
cr &= ~USART_CR2_CLRBITS;
|
||||
cr |= USART_CR2_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr &= ~USART_CR1_CLRBITS;
|
||||
cr |= USART_CR1_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_CLRBITS;
|
||||
cr |= USART_CR3_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Configure the USART Baud Rate */
|
||||
|
||||
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#ifdef USE_OVER8
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_USART */
|
||||
}
|
||||
|
|
|
|||
406
arch/arm/src/stm32f0l0/stm32_lowputc_v1.c
Normal file
406
arch/arm/src/stm32f0l0/stm32_lowputc_v1.c
Normal file
|
|
@ -0,0 +1,406 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0/stm32_lowputc_v1.c
|
||||
*
|
||||
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select USART parameters for the selected console */
|
||||
|
||||
#ifdef HAVE_CONSOLE
|
||||
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# ifdef CONFIG_USART1_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART2_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# ifdef CONFIG_USART2_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART3_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
|
||||
# ifdef CONFIG_USART3_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
|
||||
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART4_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART4_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART4_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP
|
||||
# ifdef CONFIG_USART4_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
|
||||
# if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART5_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART5_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART5_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART5_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART5_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART5_2STOP
|
||||
# ifdef CONFIG_USART5_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR
|
||||
# if (CONFIG_USART5_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* CR1 settings */
|
||||
|
||||
# if STM32_CONSOLE_BITS == 9
|
||||
# define USART_CR1_M0_VALUE USART_CR1_M0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# elif STM32_CONSOLE_BITS == 7
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE USART_CR1_M1
|
||||
# else /* 8 bits */
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# endif
|
||||
|
||||
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
|
||||
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
|
||||
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
|
||||
# else /* no parity */
|
||||
# define USART_CR1_PARITY_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR1_CLRBITS \
|
||||
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
|
||||
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
|
||||
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
|
||||
USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
|
||||
|
||||
# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
|
||||
|
||||
/* CR2 settings */
|
||||
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
|
||||
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
|
||||
USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
|
||||
USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
|
||||
USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
|
||||
|
||||
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
|
||||
|
||||
/* CR3 settings */
|
||||
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
|
||||
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
|
||||
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
|
||||
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
|
||||
USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
|
||||
|
||||
# define USART_CR3_SETBITS 0
|
||||
|
||||
# undef USE_OVER8
|
||||
|
||||
/* Calculate USART BAUD rate divider */
|
||||
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / UARTDIV
|
||||
* UARTDIV = fCK / baud
|
||||
*
|
||||
* In case of oversampling by 8, the equation is:
|
||||
*
|
||||
* baud = 2 * fCK / UARTDIV
|
||||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if STM32_USARTDIV8 > 100
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_lowputc(char ch)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the USART used for the serial
|
||||
* console. Its purpose is to get the console output availabe as soon
|
||||
* as possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_USART)
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
uint32_t cr;
|
||||
#endif
|
||||
|
||||
/* Setup clocking and GPIO pins for all configured USARTs */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART1
|
||||
/* Enable USART APB2 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART1_TX);
|
||||
stm32_configgpio(GPIO_USART1_RX);
|
||||
|
||||
#ifdef CONFIG_USART1_RS485
|
||||
stm32_configgpio(GPIO_USART1_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART2
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART2_TX);
|
||||
stm32_configgpio(GPIO_USART2_RX);
|
||||
|
||||
#ifdef CONFIG_USART2_RS485
|
||||
stm32_configgpio(GPIO_USART2_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART3
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART3_TX);
|
||||
stm32_configgpio(GPIO_USART3_RX);
|
||||
|
||||
#ifdef CONFIG_USART3_RS485
|
||||
stm32_configgpio(GPIO_USART3_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART4
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART4_TX);
|
||||
stm32_configgpio(GPIO_USART4_RX);
|
||||
|
||||
#ifdef CONFIG_USART4_RS485
|
||||
stm32_configgpio(GPIO_USART4_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART5
|
||||
/* Enable USART APB1 clock */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);
|
||||
|
||||
/* Configure RX/TX pins */
|
||||
|
||||
stm32_configgpio(GPIO_USART5_TX);
|
||||
stm32_configgpio(GPIO_USART5_RX);
|
||||
|
||||
#ifdef CONFIG_USART5_RS485
|
||||
stm32_configgpio(GPIO_USART5_RS485_DIR);
|
||||
stm32_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Configure CR2 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
cr &= ~USART_CR2_CLRBITS;
|
||||
cr |= USART_CR2_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr &= ~USART_CR1_CLRBITS;
|
||||
cr |= USART_CR1_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_CLRBITS;
|
||||
cr |= USART_CR3_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Configure the USART Baud Rate */
|
||||
|
||||
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#ifdef USE_OVER8
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_USART */
|
||||
}
|
||||
364
arch/arm/src/stm32f0l0/stm32_lowputc_v2.c
Normal file
364
arch/arm/src/stm32f0l0/stm32_lowputc_v2.c
Normal file
|
|
@ -0,0 +1,364 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0/stm32_lowputc_v2.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "hardware/stm32_pinmap.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_uart.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select USART parameters for the selected console */
|
||||
|
||||
#ifdef HAVE_CONSOLE
|
||||
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART1_RX
|
||||
# ifdef CONFIG_USART1_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART2_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART2_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART2_RX
|
||||
# ifdef CONFIG_USART2_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART3_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART3_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART3_RX
|
||||
# ifdef CONFIG_USART3_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
|
||||
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART4_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART4_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART4EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART4_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART4_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART4_RX
|
||||
# ifdef CONFIG_USART4_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
|
||||
# if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* CR1 settings */
|
||||
|
||||
# if STM32_CONSOLE_BITS == 7
|
||||
# define USART_CR_M01_VALUE USART_CR1_M1
|
||||
# elif STM32_CONSOLE_BITS == 9
|
||||
# define USART_CR_M01_VALUE USART_CR1_M0
|
||||
# else /* STM32_CONSOLE_BITS == 8 */
|
||||
# define USART_CR_M01_VALUE 0
|
||||
# endif
|
||||
|
||||
# if STM32_CONSOLE_PARITY == 1
|
||||
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
|
||||
# elif STM32_CONSOLE_PARITY == 2
|
||||
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
|
||||
# else
|
||||
# define USART_CR1_PARITY_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR1_CLRBITS \
|
||||
(USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | USART_CR1_PCE | \
|
||||
USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_MME | USART_CR1_OVER8 | \
|
||||
USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
|
||||
|
||||
# define USART_CR1_SETBITS (USART_CR_M01_VALUE | USART_CR1_PARITY_VALUE)
|
||||
|
||||
/* CR2 settings */
|
||||
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
|
||||
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
|
||||
USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
|
||||
USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \
|
||||
USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
|
||||
|
||||
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
|
||||
|
||||
/* CR3 settings */
|
||||
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
|
||||
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
|
||||
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT | \
|
||||
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
|
||||
USART_CR3_SCARCNT_MASK)
|
||||
|
||||
# define USART_CR3_SETBITS 0
|
||||
|
||||
/* Only the STM32 F3 supports oversampling by 8 */
|
||||
|
||||
# undef USE_OVER8
|
||||
|
||||
/* Calculate USART BAUD rate divider */
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / UARTDIV
|
||||
* UARTDIV = fCK / baud
|
||||
*
|
||||
* In case of oversampling by 8, the equation is:
|
||||
*
|
||||
* baud = 2 * fCK / UARTDIV
|
||||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversampling by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if STM32_USARTDIV8 > 100
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_lowputc(char ch)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the USART used for the serial
|
||||
* console. Its purpose is to get the console output availabe as soon
|
||||
* as possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART)
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
uint32_t cr;
|
||||
#endif
|
||||
|
||||
#if defined(HAVE_CONSOLE)
|
||||
/* Enable USART APB1/2 clock */
|
||||
|
||||
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
|
||||
#endif
|
||||
|
||||
/* Enable the console USART and configure GPIO pins needed for rx/tx.
|
||||
*
|
||||
* NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c
|
||||
*/
|
||||
|
||||
#ifdef STM32_CONSOLE_TX
|
||||
stm32_configgpio(STM32_CONSOLE_TX);
|
||||
#endif
|
||||
#ifdef STM32_CONSOLE_RX
|
||||
stm32_configgpio(STM32_CONSOLE_RX);
|
||||
#endif
|
||||
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Configure CR2 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
cr &= ~USART_CR2_CLRBITS;
|
||||
cr |= USART_CR2_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr &= ~USART_CR1_CLRBITS;
|
||||
cr |= USART_CR1_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_CLRBITS;
|
||||
cr |= USART_CR3_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Configure the USART Baud Rate */
|
||||
|
||||
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#ifdef USE_OVER8
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx and the USART */
|
||||
|
||||
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
|
@ -86,6 +86,8 @@
|
|||
# include "stm32f0_rcc.c"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "stm32l0_rcc.c"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# include "stm32g0_rcc.c"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 RCC"
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
2591
arch/arm/src/stm32f0l0/stm32_serial_v1.c
Normal file
2591
arch/arm/src/stm32f0l0/stm32_serial_v1.c
Normal file
File diff suppressed because it is too large
Load diff
1959
arch/arm/src/stm32f0l0/stm32_serial_v2.c
Normal file
1959
arch/arm/src/stm32f0l0/stm32_serial_v2.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -525,7 +525,7 @@ static inline void rcc_enableperipherals(void)
|
|||
rcc_enableapb1();
|
||||
|
||||
#ifdef STM32_USE_HSI48
|
||||
/* Enable HSI48 clocking to to support USB transfers or RNG */
|
||||
/* Enable HSI48 clocking to support USB transfers or RNG */
|
||||
|
||||
stm32_enable_hsi48(STM32_HSI48_SYNCSRC);
|
||||
#endif
|
||||
|
|
|
|||
622
arch/arm/src/stm32f0l0/stm32g0_rcc.c
Normal file
622
arch/arm/src/stm32f0l0/stm32g0_rcc.c
Normal file
|
|
@ -0,0 +1,622 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0/stm32g0_rcc.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Allow up to 100 milliseconds for the high speed clock to become ready.
|
||||
* that is a very long delay, but if the clock does not become ready we are
|
||||
* hosed anyway. Normally this is very fast, but I have seen at least one
|
||||
* board that required this long, long timeout for the HSE to be ready.
|
||||
*/
|
||||
|
||||
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
/* HSE divisor to yield ~1MHz RTC clock (valid for HSE = 8MHz) */
|
||||
|
||||
#define HSE_DIVISOR RCC_CR_RTCPRE_HSEd8
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_reset
|
||||
*
|
||||
* Description:
|
||||
* Put all RCC registers in reset state
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_reset(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
|
||||
#if 1
|
||||
/* DBG clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DBGEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableio
|
||||
*
|
||||
* Description:
|
||||
* Enable selected GPIO
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableio(void)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
/* REVISIT: */
|
||||
|
||||
regval |= (RCC_IOPENR_IOPAEN | RCC_IOPENR_IOPBEN | RCC_IOPENR_IOPCEN | \
|
||||
RCC_IOPENR_IOPDEN | RCC_IOPENR_IOPFEN);
|
||||
|
||||
putreg32(regval, STM32_RCC_IOPENR); /* Enable GPIO */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb(void)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
/* Set the appropriate bits in the AHBENR register to enabled the
|
||||
* selected AHBENR peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHBENR);
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_DMA1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_MIF
|
||||
/* Memory interface clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_MIFEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_CRC
|
||||
/* CRC clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_CRCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_RNG
|
||||
/* Random number generator clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_RNGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_AES
|
||||
/* AES modules clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_AESEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB1ENR register to enabled the
|
||||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM2
|
||||
/* Timer 2 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM2EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM3
|
||||
/* Timer 3 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM3EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM6
|
||||
/* Timer 6 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM6EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM7
|
||||
/* Timer 7 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM7EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SPI2
|
||||
/* SPI 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART2
|
||||
/* USART 2 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_USART2EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART3
|
||||
/* USART 3 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_USART3EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART4
|
||||
/* USART 4 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_USART4EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_LPUSART1
|
||||
/* USART 5 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_LPUSART1EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_I2C1
|
||||
/* I2C 1 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_I2C1EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_I2C2
|
||||
/* I2C 2 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_I2C2EN;
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_STM32F0L0_PWR
|
||||
/* Power interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_DAC1
|
||||
/* DAC 1 interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DAC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_LPTIM1
|
||||
/* LPTIM1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_LPTIM1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_LPTIM2
|
||||
/* LPTIM2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_LPTIM2EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SYSCFG
|
||||
/* SYSCFG clock */
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM1
|
||||
/* TIM1 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM1EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SPI1
|
||||
/* SPI 1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART1
|
||||
/* USART1 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_USART1EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM14
|
||||
/* TIM14 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM14EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM15
|
||||
/* TIM5 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM15EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM16
|
||||
/* TIM16 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM16EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM17
|
||||
/* TIM17 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM17EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_ADC1
|
||||
/* ADC 1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC1EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablehse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External High-Speed (HSE) Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
|
||||
static inline bool stm32_rcc_enablehse(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */
|
||||
regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */
|
||||
#else
|
||||
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
|
||||
#endif
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSERDY flag is set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then return TRUE */
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
/* In the case of a timeout starting the HSE, we really don't have a
|
||||
* strategy. This is almost always a hardware failure or misconfiguration.
|
||||
*/
|
||||
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h.
|
||||
*
|
||||
* NOTE: This logic would need to be extended if you need to select low-
|
||||
* power clocking modes or any clocking other than PLL driven by the HSE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
|
||||
static void stm32_stdclockconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
|
||||
uint16_t pwrcr;
|
||||
#endif
|
||||
uint32_t pwr_vos;
|
||||
bool flash_1ws;
|
||||
|
||||
/* Enable PWR clock from APB1 to give access to PWR_CR register */
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
#warning TODO: configure VOS range
|
||||
UNUSED(pwr_vos);
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
|
||||
/* If RTC / LCD selects HSE as clock source, the RTC prescaler
|
||||
* needs to be set before HSEON bit is set.
|
||||
*/
|
||||
|
||||
/* The RTC domain has write access denied after reset,
|
||||
* you have to enable write access using DBP bit in the PWR CR
|
||||
* register before to selecting the clock source ( and the PWR
|
||||
* peripheral must be enabled)
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
pwrcr = getreg16(STM32_PWR_CR);
|
||||
putreg16(pwrcr | PWR_CR_DBP, STM32_PWR_CR);
|
||||
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CSR);
|
||||
regval &= ~RCC_CSR_RTCSEL_MASK;
|
||||
regval |= RCC_CSR_RTCSEL_HSE;
|
||||
putreg32(regval, STM32_RCC_CSR);
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_RTCPRE_MASK;
|
||||
regval |= HSE_DIVISOR;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Restore the previous state of the DBP bit */
|
||||
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
#endif
|
||||
|
||||
/* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
|
||||
|
||||
#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
|
||||
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE))
|
||||
|
||||
/* The PLL is using the HSE, or the HSE is the system clock. In either
|
||||
* case, we need to enable HSE clocking.
|
||||
*/
|
||||
|
||||
if (!stm32_rcc_enablehse())
|
||||
{
|
||||
/* In the case of a timeout starting the HSE, we really don't have a
|
||||
* strategy. This is almost always a hardware failure or
|
||||
* misconfiguration (for example, if no crystal is fitted on the board.
|
||||
*/
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
|
||||
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
|
||||
|
||||
/* The PLL is using the HSI, or the HSI is the system clock. In either
|
||||
* case, we need to enable HSI clocking.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_CR); /* Enable the HSI */
|
||||
regval |= RCC_CR_HSION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI clock is ready. Since this is an internal clock, no
|
||||
* timeout is expected
|
||||
*/
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0);
|
||||
|
||||
#endif
|
||||
|
||||
#warning TODO: cofnigure flash latency
|
||||
UNUSED(flash_1ws);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* If we are using the PLL, configure and start it */
|
||||
|
||||
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
|
||||
|
||||
/* Configure PLLs */
|
||||
|
||||
regval = STM32_PLLCFG_PLLSRC | STM32_PLLCFG_PLLCFG;
|
||||
|
||||
/* Configure PLL clock input */
|
||||
|
||||
regval |= STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN;
|
||||
|
||||
/* Configure PLL clock outputs division */
|
||||
|
||||
regval |= STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR;
|
||||
|
||||
/* Write PLLCFG register */
|
||||
|
||||
putreg32(regval, STM32_RCC_PLLCFG);
|
||||
#endif
|
||||
|
||||
/* Select the system clock source (probably the PLL) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= STM32_SYSCLK_SW;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the selected source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_IWDG) || \
|
||||
defined(CONFIG_STM32F0L0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
|
||||
/* Low speed internal clock source LSI
|
||||
*
|
||||
* TODO: There is another case where the LSI needs to
|
||||
* be enabled: if the MCO pin selects LSI as source.
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if the MCO pin selects LSE as source.
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if TIM9-10 Channel 1 selects LSE as input.
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if TIM10-11 selects LSE as ETR Input.
|
||||
*
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelse();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableperiphals
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableperipherals(void)
|
||||
{
|
||||
rcc_enableio();
|
||||
rcc_enableahb();
|
||||
rcc_enableapb2();
|
||||
rcc_enableapb1();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -799,7 +799,7 @@ static inline void rcc_enableperipherals(void)
|
|||
#endif
|
||||
|
||||
#ifdef STM32_USE_HSI48
|
||||
/* Enable HSI48 clocking to to support USB transfers or RNG */
|
||||
/* Enable HSI48 clocking to support USB transfers or RNG */
|
||||
|
||||
stm32_enable_hsi48(STM32_HSI48_SYNCSRC);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@
|
|||
************************************************************************************/
|
||||
|
||||
#define DMAMUX1 0
|
||||
#define DMAMUX2 0
|
||||
#define DMAMUX2 1
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@
|
|||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
|
||||
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */
|
||||
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */
|
||||
|
|
|
|||
|
|
@ -1034,6 +1034,16 @@ config ARCH_BOARD_NUCLEO_F446RE
|
|||
This is a minimal configuration that supports low-level test of the
|
||||
Nucleo F446RE in the NuttX source tree.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_G071RB
|
||||
bool "STM32G071 Nucleo G071RB"
|
||||
depends on ARCH_CHIP_STM32G071RB
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
---help---
|
||||
This is a minimal configuration that supports low-level test of the
|
||||
Nucleo G071RB in the NuttX source tree.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_H743ZI
|
||||
bool "STM32H743 Nucleo H743ZI"
|
||||
depends on ARCH_CHIP_STM32H743ZI
|
||||
|
|
@ -1873,6 +1883,7 @@ config ARCH_BOARD
|
|||
default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE
|
||||
default "nucleo-f446re" if ARCH_BOARD_NUCLEO_F446RE
|
||||
default "nucleo-f410rb" if ARCH_BOARD_NUCLEO_F410RB
|
||||
default "nucleo-g071rb" if ARCH_BOARD_NUCLEO_G071RB
|
||||
default "nucleo-h743zi" if ARCH_BOARD_NUCLEO_H743ZI
|
||||
default "nucleo-l073rz" if ARCH_BOARD_NUCLEO_L073RZ
|
||||
default "nucleo-l152re" if ARCH_BOARD_NUCLEO_L152RE
|
||||
|
|
@ -2228,6 +2239,9 @@ endif
|
|||
if ARCH_BOARD_NUCLEO_F410RB
|
||||
source "configs/nucleo-f410rb/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_NUCLEO_G071RB
|
||||
source "configs/nucleo-g071rb/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_NUCLEO_H743ZI
|
||||
source "configs/nucleo-h743zi/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
8
configs/nucleo-g071rb/Kconfig
Normal file
8
configs/nucleo-g071rb/Kconfig
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_NUCLEO_G071RB
|
||||
|
||||
endif
|
||||
32
configs/nucleo-g071rb/README.txt
Normal file
32
configs/nucleo-g071rb/README.txt
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
Nucleo-64 Boards
|
||||
================
|
||||
|
||||
The Nucleo-G071RB is a member of the Nucleo-64 board family. The Nucleo-64
|
||||
is a standard board for use with several STM32 parts in the LQFP64 package.
|
||||
Variants include
|
||||
|
||||
Order code Targeted STM32
|
||||
------------- --------------
|
||||
NUCLEO-F030R8 STM32F030R8T6
|
||||
NUCLEO-F070RB STM32F070RBT6
|
||||
NUCLEO-F072RB STM32F072RBT6
|
||||
NUCLEO-F091RC STM32F091RCT6
|
||||
NUCLEO-F103RB STM32F103RBT6
|
||||
NUCLEO-F302R8 STM32F302R8T6
|
||||
NUCLEO-F303RE STM32F303RET6
|
||||
NUCLEO-F334R8 STM32F334R8T6
|
||||
NUCLEO-F401RE STM32F401RET6
|
||||
NUCLEO-F410RB STM32F410RBT6
|
||||
NUCLEO-F411RE STM32F411RET6
|
||||
NUCLEO-F446RE STM32F446RET6
|
||||
NUCLEO-L053R8 STM32L053R8T6
|
||||
NUCLEO-L073RZ STM32L073RZT6
|
||||
NUCLEO-L152RE STM32L152RET6
|
||||
NUCLEO-L452RE STM32L452RET6
|
||||
NUCLEO-L476RG STM32L476RGT6
|
||||
|
||||
STATUS
|
||||
======
|
||||
|
||||
2019-05-27: Brings in initial WIP support for the STM32 G0.
|
||||
Not tested on hardware.
|
||||
221
configs/nucleo-g071rb/include/board.h
Normal file
221
configs/nucleo-g071rb/include/board.h
Normal file
|
|
@ -0,0 +1,221 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/include/board.h
|
||||
* include/arch/board/board.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIG_NUCLEO_G071RB_INCLUDE_BOARD_H
|
||||
#define __CONFIG_NUCLEO_G071RB_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include <stdbool.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
/* HSI - Internal 8 MHz RC Oscillator
|
||||
* LSI - 32 KHz RC
|
||||
* HSE - 8 MHz from MCO output of ST-LINK
|
||||
* LSE - 32.768 kHz
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
#define STM32_HSI_FREQUENCY 8000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
|
||||
|
||||
/* Main PLL Configuration.
|
||||
*
|
||||
* PLL source is HSE = 8,000,000
|
||||
*
|
||||
* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
|
||||
* Subject to:
|
||||
*
|
||||
* 1 <= PLLM <= 8
|
||||
* 8 <= PLLN <= 86
|
||||
* 4 MHz <= PLL_IN <= 16MHz
|
||||
* 64 MHz <= PLL_VCO <= 344MHz
|
||||
* SYSCLK = PLLRCLK = PLL_VCO / PLLR
|
||||
*
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_USEHSE
|
||||
#define STM32_HSEBYP_ENABLE
|
||||
|
||||
/* PLL source is HSE, PLLN=50, PLLM=2
|
||||
* PLLP enable, PLLQ enable, PLLR enable
|
||||
*
|
||||
* PLLR <= 64MHz
|
||||
* PLLQ <= 128MHz
|
||||
* PLLP <= 128MHz
|
||||
*
|
||||
* PLL_VCO = (8,000,000 / 2) * 50 = 200 MHz
|
||||
*
|
||||
* PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
|
||||
* PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
|
||||
* PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSE
|
||||
#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \
|
||||
RCC_PLLCFG_PLLQEN | \
|
||||
RCC_PLLCFG_PLLREN)
|
||||
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4)
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLQ(8)
|
||||
|
||||
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50)
|
||||
#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4)
|
||||
#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4)
|
||||
#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4)
|
||||
|
||||
/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */
|
||||
|
||||
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
|
||||
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY)
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (40MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
|
||||
/* TODO: timers */
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2-1.
|
||||
* LD3 PWR: red LED indicates that the board is powered.
|
||||
*
|
||||
* And one can be controlled by software:
|
||||
*
|
||||
* User LD2: green LED is a user LED connected to the I/O PA5 of the
|
||||
* STM32LO73RZ.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
|
||||
* any way. The following definition is used to access the LED.
|
||||
*/
|
||||
|
||||
/* LED index values for use with board_userled() */
|
||||
|
||||
#define BOARD_LED1 0 /* User LD2 */
|
||||
#define BOARD_NLEDS 1
|
||||
|
||||
/* LED bits for use with board_userled_all() */
|
||||
|
||||
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
||||
|
||||
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
|
||||
* the Nucleo LO73RZ. The following definitions describe how NuttX controls
|
||||
* the LED:
|
||||
*
|
||||
* SYMBOL Meaning LED1 state
|
||||
* ------------------ ----------------------- ----------
|
||||
* LED_STARTED NuttX has been started OFF
|
||||
* LED_HEAPALLOCATE Heap has been allocated OFF
|
||||
* LED_IRQSENABLED Interrupts enabled OFF
|
||||
* LED_STACKCREATED Idle stack created ON
|
||||
* LED_INIRQ In an interrupt No change
|
||||
* LED_SIGNAL In a signal handler No change
|
||||
* LED_ASSERTION An assertion failed No change
|
||||
* LED_PANIC The system has crashed Blinking
|
||||
* LED_IDLE STM32 is is sleep mode Not used
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0
|
||||
#define LED_HEAPALLOCATE 0
|
||||
#define LED_IRQSENABLED 0
|
||||
#define LED_STACKCREATED 1
|
||||
#define LED_INIRQ 2
|
||||
#define LED_SIGNAL 2
|
||||
#define LED_ASSERTION 2
|
||||
#define LED_PANIC 1
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
/* The Nucleo LO73RZ supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ.
|
||||
* B2 RESET: push button connected to NRST is used to RESET the
|
||||
* STM32LO73RZ.
|
||||
*/
|
||||
|
||||
#define BUTTON_USER 0
|
||||
#define NUM_BUTTONS 1
|
||||
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
/* Alternate function pin selections ****************************************/
|
||||
|
||||
/* USART */
|
||||
|
||||
/* By default the USART2 is connected to STLINK Virtual COM Port:
|
||||
* USART2_RX - PA3
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
|
||||
|
||||
/* DMA channels *************************************************************/
|
||||
/* ADC */
|
||||
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */
|
||||
|
||||
#endif /* __CONFIG_NUCLEO_LO73RZ_INCLUDE_BOARD_H */
|
||||
58
configs/nucleo-g071rb/nsh/defconfig
Normal file
58
configs/nucleo-g071rb/nsh/defconfig
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_LIBC_LONG_LONG is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-g071rb"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_G071RB=y
|
||||
CONFIG_ARCH_CHIP_STM32G071RB=y
|
||||
CONFIG_ARCH_CHIP_STM32G0=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=2796
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DISABLE_ENVIRON=y
|
||||
CONFIG_DISABLE_MOUNTPOINT=y
|
||||
CONFIG_DISABLE_MQUEUE=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_DISABLE_POSIX_TIMERS=y
|
||||
CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
|
||||
CONFIG_EXAMPLES_HELLO=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MAX_TASKS=8
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_NFILE_DESCRIPTORS=6
|
||||
CONFIG_NFILE_STREAMS=6
|
||||
CONFIG_NPTHREAD_KEYS=0
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=64
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_NUNGET_CHARS=0
|
||||
CONFIG_PREALLOC_TIMERS=0
|
||||
CONFIG_PREALLOC_WDOGS=4
|
||||
CONFIG_PTHREAD_MUTEX_UNSAFE=y
|
||||
CONFIG_PTHREAD_STACK_DEFAULT=1536
|
||||
CONFIG_RAM_SIZE=20480
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=19
|
||||
CONFIG_START_MONTH=5
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_STDIO_DISABLE_BUFFERING=y
|
||||
CONFIG_STM32F0L0_USART2=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
|
||||
CONFIG_USART2_SERIAL_CONSOLE=y
|
||||
CONFIG_USERMAIN_STACKSIZE=1536
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=0
|
||||
114
configs/nucleo-g071rb/scripts/Make.defs
Normal file
114
configs/nucleo-g071rb/scripts/Make.defs
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
############################################################################
|
||||
# configs/nucleo-g071rb/scripts/Make.defs
|
||||
#
|
||||
# Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
STRIP = $(CROSSDEV)strip --strip-unneeded
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ASMEXT = .S
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
|
||||
124
configs/nucleo-g071rb/scripts/ld.script
Normal file
124
configs/nucleo-g071rb/scripts/ld.script
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/scripts/ld.script
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The STM32GO71RB has 128Kb of FLASH beginning at address 0x0800:0000.
|
||||
* 32Kb/36Kb of SRAM
|
||||
*
|
||||
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
|
||||
* where the code expects to begin execution by jumping to the entry point in
|
||||
* the 0x0800:0000 address range.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 36K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
EXTERN(_vectors)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
*(.init_array .init_array.*)
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
/* The RAM vector table (if present) should lie at the beginning of SRAM */
|
||||
|
||||
.ram_vectors : {
|
||||
*(.ram_vectors)
|
||||
} > sram
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
55
configs/nucleo-g071rb/src/Makefile
Normal file
55
configs/nucleo-g071rb/src/Makefile
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
############################################################################
|
||||
# configs/nucleo-g071rb/src/Makefile
|
||||
#
|
||||
# Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
# Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
-include $(TOPDIR)/Make.defs
|
||||
|
||||
ASRCS =
|
||||
CSRCS = stm32_boot.c stm32_bringup.c
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += stm32_autoleds.c
|
||||
else
|
||||
CSRCS += stm32_userleds.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += stm32_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinit.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
114
configs/nucleo-g071rb/src/nucleo-g071rb.h
Normal file
114
configs/nucleo-g071rb/src/nucleo-g071rb.h
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/src/nucleo-g071rb.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_NUCLEO_G071RB_SRC_NUCLEO_G071RB_H
|
||||
#define __CONFIGS_NUCLEO_G071RB_SRC_NUCLEO_G071RB_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
/* The Nucleo G071RB board has three LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2-1.
|
||||
* LD3 PWR: red LED indicates that the board is powered.
|
||||
*
|
||||
* And one can be controlled by software:
|
||||
*
|
||||
* User LD2: green LED is a user LED connected to the I/O PA5 of the
|
||||
* STM32G071RBT6.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
|
||||
* any way. The following definition is used to access the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
|
||||
|
||||
#define LED_DRIVER_PATH "/dev/userleds"
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
/* The Nucleo G071RB supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user button connected to the I/O PC13 of the STM32G071RBT6.
|
||||
* B2 RESET: push button connected to NRST is used to RESET the
|
||||
* STM32G071RBT6.
|
||||
*
|
||||
* NOTE that EXTI interrupts are configured.
|
||||
*/
|
||||
|
||||
#define MIN_IRQBUTTON BUTTON_USER
|
||||
#define MAX_IRQBUTTON BUTTON_USER
|
||||
#define NUM_IRQBUTTONS 1
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | \
|
||||
GPIO_PIN13)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_bringup
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture-specific initialization
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=y :
|
||||
* Called from board_late_initialize().
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
|
||||
* Called from the NSH library
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_bringup(void);
|
||||
|
||||
#endif /* __CONFIGS_NUCLEO_G071RB_SRC_NUCLEO_G071RB_H */
|
||||
90
configs/nucleo-g071rb/src/stm32_appinit.c
Normal file
90
configs/nucleo-g071rb/src/stm32_appinit.c
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/src/stm32_appinitialize.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/leds/userled.h>
|
||||
|
||||
#include "nucleo-g071rb.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_app_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform application specific initialization. This function is never
|
||||
* called directly from application code, but only indirectly via the
|
||||
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
|
||||
*
|
||||
* Input Parameters:
|
||||
* arg - The boardctl() argument is passed to the board_app_initialize()
|
||||
* implementation without modification. The argument has no
|
||||
* meaning to NuttX; the meaning of the argument is a contract
|
||||
* between the board-specific initalization logic and the
|
||||
* matching application logic. The value cold be such things as a
|
||||
* mode enumeration value, a set of DIP switch switch settings, a
|
||||
* pointer to configuration data read from a file or serial FLASH,
|
||||
* or whatever you would like to do with it. Every implementation
|
||||
* should accept zero/NULL as a default configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
#ifdef CONFIG_BOARD_LATE_INITIALIZE
|
||||
/* Board initialization already performed by board_late_initialize() */
|
||||
|
||||
return OK;
|
||||
#else
|
||||
/* Perform board-specific initialization */
|
||||
|
||||
return stm32_bringup();
|
||||
#endif
|
||||
}
|
||||
94
configs/nucleo-g071rb/src/stm32_autoleds.c
Normal file
94
configs/nucleo-g071rb/src/stm32_autoleds.c
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/src/stm32_autoleds.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
#include "nucleo-g071rb.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_initialize
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_initialize(void)
|
||||
{
|
||||
/* Configure LED1 GPIO for output */
|
||||
|
||||
stm32_configgpio(GPIO_LED1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_on
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_on(int led)
|
||||
{
|
||||
if (led == BOARD_LED1)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_LED1, true);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_off
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_off(int led)
|
||||
{
|
||||
if (led == BOARD_LED1)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_LED1, false);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
99
configs/nucleo-g071rb/src/stm32_boot.c
Normal file
99
configs/nucleo-g071rb/src/stm32_boot.c
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/src/stm32_boot.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nucleo-g071rb.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following entry point. This
|
||||
* entry point is called early in the intitialization -- after all memory
|
||||
* has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_boardinitialize(void)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SPI
|
||||
/* Configure SPI chip selects */
|
||||
|
||||
stm32_spidev_initialize();
|
||||
#endif
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_late_initialize
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call
|
||||
* will be performed in the boot-up sequence to a function called
|
||||
* board_late_initialize(). board_late_initialize() will be called immediately after
|
||||
* up_initialize() is called and just before the initial application is started.
|
||||
* This additional initialization phase may be used, for example, to initialize
|
||||
* board-specific device drivers.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INITIALIZE
|
||||
void board_late_initialize(void)
|
||||
{
|
||||
#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
|
||||
/* Perform board bring-up here instead of from the board_app_initialize(). */
|
||||
|
||||
(void)stm32_bringup();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
164
configs/nucleo-g071rb/src/stm32_bringup.c
Normal file
164
configs/nucleo-g071rb/src/stm32_bringup.c
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/src/stm32_bringup.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/leds/userled.h>
|
||||
|
||||
#include "nucleo-g071rb.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#undef HAVE_LEDS
|
||||
#undef HAVE_DAC
|
||||
|
||||
#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
|
||||
# define HAVE_LEDS 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DAC)
|
||||
# define HAVE_DAC1 1
|
||||
# define HAVE_DAC2 1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
/****************************************************************************
|
||||
* Name: stm32_bringup
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture-specific initialization
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=y :
|
||||
* Called from board_late_initialize().
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT:
|
||||
* Called from the NSH library
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bringup(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef HAVE_LEDS
|
||||
/* Register the LED driver */
|
||||
|
||||
ret = userled_lower_initialize(LED_DRIVER_PATH);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC driver. */
|
||||
|
||||
ret = stm32_adc_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DAC
|
||||
/* Initialize DAC and register the DAC driver. */
|
||||
|
||||
ret = stm32_dac_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_COMP
|
||||
/* Initialize COMP and register the COMP driver. */
|
||||
|
||||
ret = stm32_comp_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OPAMP
|
||||
/* Initialize OPAMP and register the OPAMP driver. */
|
||||
|
||||
ret = stm32_opamp_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WL_NRF24L01
|
||||
ret = stm32_wlinitialize();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_WL_NRF24L01 */
|
||||
|
||||
#ifdef CONFIG_LPWAN_SX127X
|
||||
ret = stm32_lpwaninitialize();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_LPWAN_SX127X */
|
||||
|
||||
#ifdef CONFIG_CL_MFRC522
|
||||
ret = stm32_mfrc522initialize("/dev/rfid0");
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_CL_MFRC522 */
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
129
configs/nucleo-g071rb/src/stm32_buttons.c
Normal file
129
configs/nucleo-g071rb/src/stm32_buttons.c
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
/****************************************************************************
|
||||
* configs/nucleo-g071rb/src/stm32_buttons.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
#include "nucleo-g071rb.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_BUTTONS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_button_initialize
|
||||
*
|
||||
* Description:
|
||||
* board_button_initialize() must be called to initialize button resources.
|
||||
* After that, board_buttons() may be called to collect the current state
|
||||
* of all buttons or board_button_irq() may be called to register button
|
||||
* interrupt handlers.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void board_button_initialize(void)
|
||||
{
|
||||
/* Configure the single button as an input. NOTE that EXTI interrupts are
|
||||
* also configured for the pin.
|
||||
*/
|
||||
|
||||
stm32_configgpio(GPIO_BTN_USER);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_buttons
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
/* Check that state of each USER button. A LOW value means that the key is
|
||||
* pressed.
|
||||
*/
|
||||
|
||||
bool released = stm32_gpioread(GPIO_BTN_USER);
|
||||
return !released;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Button support.
|
||||
*
|
||||
* Description:
|
||||
* board_button_initialize() must be called to initialize button resources. After
|
||||
* that, board_buttons() may be called to collect the current state of all
|
||||
* buttons or board_button_irq() may be called to register button interrupt
|
||||
* handlers.
|
||||
*
|
||||
* After board_button_initialize() has been called, board_buttons() may be called to
|
||||
* collect the state of all buttons. board_buttons() returns an 32-bit bit set
|
||||
* with each bit associated with a button. See the BUTTON_*_BIT
|
||||
* definitions in board.h for the meaning of each bit.
|
||||
*
|
||||
* board_button_irq() may be called to register an interrupt handler that will
|
||||
* be called when a button is depressed or released. The ID value is a
|
||||
* button enumeration value that uniquely identifies a button resource. See the
|
||||
* BUTTON_* definitions in board.h for the meaning of enumeration
|
||||
* value.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQBUTTONS
|
||||
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (id == BUTTON_USER)
|
||||
{
|
||||
ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_ARCH_BUTTONS */
|
||||
Loading…
Reference in a new issue