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use small lock in following files:

Browse source 
arch/arm/src/rp2040/rp2040_usbdev.c
arch/arm/src/rp23xx/rp23xx_uart.c
arch/arm/src/s32k1xx/s32k1xx_enet.c
arch/arm/src/sam34/sam_lowputc.c
arch/arm/src/sama5/sam_lowputc.c
arch/arm/src/samd2l2/sam_serial.c
arch/arm/src/samd5e5/sam_serial.c
arch/arm/src/samv7/sam_lowputc.c
arch/arm/src/stm32/stm32_hciuart.c
arch/arm/src/stm32/stm32_qencoder.c
arch/arm/src/stm32/stm32_serial.c
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5 2024-12-23 15:20:07 +08:00 committed by Xiang Xiao
parent c96b8cdfdd
commit b66c1b94ce
12 changed files with 161 additions and 133 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
arch/arm/src/rp2040/rp2040_usbdev.c
View file

@ -267,6 +267,7 @@ struct rp2040_usbdev_s
uint16_t next_offset; /* Unused DPSRAM buffer offset */
uint8_t dev_addr; /* USB device address */
spinlock_t lock; /* USB device address */
enum rp2040_zlp_e zlp_stat; /* Pending EP0 ZLP status */
uint16_t used; /* used epphy */
bool stalled;
@ -496,6 +497,7 @@ static void rp2040_update_buffer_control(struct rp2040_ep_s *privep,
static int rp2040_epwrite(struct rp2040_ep_s *privep, uint8_t *buf,
uint16_t nbytes)
{
struct rp2040_usbdev_s *priv = privep->dev;
uint32_t val;
irqstate_t flags;
@ -513,9 +515,9 @@ static int rp2040_epwrite(struct rp2040_ep_s *privep, uint8_t *buf,
/* Start the transfer */
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
rp2040_update_buffer_control(privep, 0, val);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
return nbytes;
}
@ -530,6 +532,7 @@ static int rp2040_epwrite(struct rp2040_ep_s *privep, uint8_t *buf,
static int rp2040_epread(struct rp2040_ep_s *privep, uint16_t nbytes)
{
struct rp2040_usbdev_s *priv = privep->dev;
uint32_t val;
irqstate_t flags;
@ -542,9 +545,9 @@ static int rp2040_epread(struct rp2040_ep_s *privep, uint16_t nbytes)
/* Start the transfer */
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
rp2040_update_buffer_control(privep, 0, val);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
return OK;
}
@ -1708,15 +1711,12 @@ static int rp2040_epcancel(struct usbdev_ep_s *ep,
*
****************************************************************************/
static int rp2040_epstall_exec(struct usbdev_ep_s *ep)
static int rp2040_epstall_exec_nolock(struct usbdev_ep_s *ep)
{
struct rp2040_ep_s *privep = (struct rp2040_ep_s *)ep;
irqstate_t flags;
usbtrace(TRACE_EPSTALL, privep->epphy);
flags = spin_lock_irqsave(NULL);
if (privep->epphy == 0)
{
setbits_reg32(privep->in ?
@ -1731,10 +1731,22 @@ static int rp2040_epstall_exec(struct usbdev_ep_s *ep)
privep->pending_stall = false;
spin_unlock_irqrestore(NULL, flags);
return OK;
}
static int rp2040_epstall_exec(struct usbdev_ep_s *ep)
{
struct rp2040_ep_s *privep = (struct rp2040_ep_s *)ep;
struct rp2040_usbdev_s *priv = privep->dev;
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->lock);
ret = rp2040_epstall_exec_nolock(ep);
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
/****************************************************************************
* Name: rp2040_epstall
*
@ -1749,7 +1761,7 @@ static int rp2040_epstall(struct usbdev_ep_s *ep, bool resume)
struct rp2040_usbdev_s *priv = privep->dev;
irqstate_t flags;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
if (resume)
{
@ -1784,13 +1796,13 @@ static int rp2040_epstall(struct usbdev_ep_s *ep, bool resume)
{
/* Stall immediately */
rp2040_epstall_exec(ep);
rp2040_epstall_exec_nolock(ep);
}
priv->zlp_stat = RP2040_ZLP_NONE;
}
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
return OK;
}
@ -2027,6 +2039,7 @@ void arm_usbinitialize(void)
g_usbdev.eplist[i].ep.eplog = 0;
}
spin_lock_init(&g_usbdev.lock);
if (irq_attach(RP2040_USBCTRL_IRQ, rp2040_usbinterrupt, &g_usbdev) != 0)
{
usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_IRQREGISTRATION),
@ -2139,7 +2152,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
/* Unbind the class driver */
@ -2157,7 +2170,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
priv->driver = NULL;
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
return OK;
}

6
arch/arm/src/rp23xx/rp23xx_uart.c
View file

@ -116,6 +116,8 @@
* Private Data
****************************************************************************/
static spinlock_t g_rp23xx_uart_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -189,7 +191,7 @@ void rp23xx_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
uint32_t div;
uint32_t lcr_h;
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_rp23xx_uart_lock);
div = basefreq / (16 * baud / 100);
ibrd = div / 100;
@ -214,5 +216,5 @@ void rp23xx_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
putreg32(lcr_h, uartbase + RP23XX_UART_UARTLCR_H_OFFSET);
finish:
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_rp23xx_uart_lock, flags);
}

7
arch/arm/src/s32k1xx/s32k1xx_enet.c
View file

@ -260,6 +260,7 @@ struct s32k1xx_driver_s
struct work_s pollwork; /* For deferring poll work to the work queue */
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */
spinlock_t lock; /* Spinlock */
/* This holds the information visible to the NuttX network */
@ -541,7 +542,7 @@ static int s32k1xx_transmit(struct s32k1xx_driver_s *priv)
/* Make the following operations atomic */
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
/* Enable TX interrupts */
@ -558,7 +559,7 @@ static int s32k1xx_transmit(struct s32k1xx_driver_s *priv)
putreg32(ENET_TDAR, S32K1XX_ENET_TDAR);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
return OK;
}
@ -2443,6 +2444,8 @@ int s32k1xx_netinitialize(int intf)
#endif
priv->dev.d_private = g_enet; /* Used to recover private state from dev */
spin_lock_init(&priv->lock);
#ifdef CONFIG_NET_ETHERNET
/* Determine a semi-unique MAC address from MCU UID
* We use UID Low and Mid Low registers to get 64 bits, from which we keep

29
arch/arm/src/sam34/sam_lowputc.c
View file

@ -249,6 +249,10 @@
* Private Data
****************************************************************************/
#ifdef HAVE_CONSOLE
static spinlock_t g_sam_lowputc_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -270,30 +274,19 @@ void arm_lowputc(char ch)
#ifdef HAVE_CONSOLE
irqstate_t flags;
for (; ; )
{
flags = spin_lock_irqsave(&g_sam_lowputc_lock);
/* Wait for the transmitter to be available */
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) == 0);
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) == 0);
/* Disable interrupts so that the test and the transmission are
* atomic.
*/
/* Send the character */
flags = spin_lock_irqsave(NULL);
if ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) != 0)
{
/* Send the character */
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
spin_unlock_irqrestore(NULL, flags);
return;
}
spin_unlock_irqrestore(&g_sam_lowputc_lock, flags);
spin_unlock_irqrestore(NULL, flags);
}
#endif
}

36
arch/arm/src/sama5/sam_lowputc.c
View file

@ -211,6 +211,14 @@
UART_MR_CHMODE_NORMAL)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE)
static spinlock_t g_sam_lowputc_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -228,30 +236,16 @@ void arm_lowputc(char ch)
#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE)
irqstate_t flags;
for (; ; )
{
/* Wait for the transmitter to be available */
/* Wait for the transmitter to be available */
while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) == 0);
flags = spin_lock_irqsave(&g_sam_lowputc_lock);
while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) == 0);
/* Disable interrupts so that the test and the transmission are
* atomic.
*/
/* Send the character */
flags = spin_lock_irqsave(NULL);
if ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) != 0)
{
/* Send the character */
putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET);
spin_unlock_irqrestore(NULL, flags);
return;
}
spin_unlock_irqrestore(NULL, flags);
}
putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET);
spin_unlock_irqrestore(&g_sam_lowputc_lock, flags);
#elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE)
irqstate_t flags;

8
arch/arm/src/samd2l2/sam_serial.c
View file

@ -260,6 +260,10 @@ static bool sam_txempty(struct uart_dev_s *dev);
* Private Data
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
static spinlock_t g_sam_serial_lock = SP_UNLOCKED;
#endif
static const struct uart_ops_s g_uart_ops =
{
.setup = sam_setup,
@ -1048,9 +1052,9 @@ void up_putc(int ch)
* interrupts from firing in the serial driver code.
*/
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&g_sam_serial_lock);
sam_lowputc(ch);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_sam_serial_lock, flags);
#endif
}

8
arch/arm/src/samd5e5/sam_serial.c
View file

@ -327,6 +327,10 @@ static bool sam_txempty(struct uart_dev_s *dev);
* Private Data
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
static spinlock_t g_sam_serial_lock = SP_UNLOCKED;
#endif
static const struct uart_ops_s g_uart_ops =
{
.setup = sam_setup,
@ -1107,9 +1111,9 @@ void up_putc(int ch)
* interrupts from firing in the serial driver code.
*/
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&g_sam_serial_lock);
sam_lowputc(ch);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_sam_serial_lock, flags);
#endif
}

35
arch/arm/src/samv7/sam_lowputc.c
View file

@ -159,6 +159,14 @@
#endif /* HAVE_SERIAL_CONSOLE */
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
static spinlock_t g_sam_lowputc_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -176,30 +184,17 @@ void arm_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
irqstate_t flags;
for (; ; )
{
/* Wait for the transmitter to be available */
/* Wait for the transmitter to be available */
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) == 0);
flags = spin_lock_irqsave(&g_sam_lowputc_lock);
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) == 0);
/* Disable interrupts so that the test and the transmission are
* atomic.
*/
/* Send the character */
flags = spin_lock_irqsave(NULL);
if ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) &
UART_INT_TXEMPTY) != 0)
{
/* Send the character */
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
spin_unlock_irqrestore(NULL, flags);
return;
}
spin_unlock_irqrestore(NULL, flags);
}
spin_unlock_irqrestore(&g_sam_lowputc_lock, flags);
#endif
}

85
arch/arm/src/stm32/stm32_hciuart.c
View file

@ -283,6 +283,7 @@ struct hciuart_config_s
uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */
uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
spinlock_t lock; /* Spinlock */
};
/****************************************************************************
@ -408,6 +409,7 @@ static const struct hciuart_config_s g_hciusart1_config =
.rx_gpio = GPIO_USART1_RX,
.cts_gpio = GPIO_USART1_CTS,
.rts_gpio = GPIO_USART1_RTS,
.lock = SP_UNLOCKED
};
#endif
@ -468,6 +470,7 @@ static const struct hciuart_config_s g_hciusart2_config =
.rx_gpio = GPIO_USART2_RX,
.cts_gpio = GPIO_USART2_CTS,
.rts_gpio = GPIO_USART2_RTS,
.lock = SP_UNLOCKED
};
#endif
@ -528,6 +531,7 @@ static const struct hciuart_config_s g_hciusart3_config =
.rx_gpio = GPIO_USART3_RX,
.cts_gpio = GPIO_USART3_CTS,
.rts_gpio = GPIO_USART3_RTS,
.lock = SP_UNLOCKED
};
#endif
@ -588,6 +592,7 @@ static const struct hciuart_config_s g_hciusart6_config =
.rx_gpio = GPIO_USART6_RX,
.cts_gpio = GPIO_USART6_CTS,
.rts_gpio = GPIO_USART6_RTS,
.lock = SP_UNLOCKED
};
#endif
@ -648,6 +653,7 @@ static const struct hciuart_config_s g_hciuart7_config =
.rx_gpio = GPIO_UART7_RX,
.cts_gpio = GPIO_UART7_CTS,
.rts_gpio = GPIO_UART7_RTS,
.lock = SP_UNLOCKED
};
#endif
@ -708,6 +714,7 @@ static const struct hciuart_config_s g_hciuart8_config =
.rx_gpio = GPIO_UART8_RX,
.cts_gpio = GPIO_UART8_CTS,
.rts_gpio = GPIO_UART8_RTS,
.lock = SP_UNLOCKED
};
#endif
@ -1915,7 +1922,7 @@ static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower,
/* If the callback is NULL, then we are detaching */
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&config->lock);
if (callback == NULL)
{
uint32_t intset;
@ -1938,7 +1945,7 @@ static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower,
state->callback = callback;
}
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&config->lock, flags);
}
/****************************************************************************
@ -2003,7 +2010,7 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower,
* " " USART_SR_ORE Overrun Error Detected
*/
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&config->lock);
if (enable)
{
/* Receive an interrupt when their is anything in the Rx data
@ -2019,7 +2026,7 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower,
hciuart_disableints(config, intset);
}
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&config->lock, flags);
}
#endif
}
@ -2218,9 +2225,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower,
* USART_CR3_CTSIE USART_SR_CTS CTS flag (not used)
*/
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&config->lock);
hciuart_disableints(config, USART_CR1_TXEIE);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&config->lock, flags);
/* Loop until all of the user data have been moved to the Tx buffer */
@ -2313,9 +2320,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower,
if (state->txhead != state->txtail)
{
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&config->lock);
hciuart_enableints(config, USART_CR1_TXEIE);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&config->lock, flags);
}
return ntotal;
@ -2394,8 +2401,19 @@ static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status,
const struct hciuart_config_s *config =
(const struct hciuart_config_s *)arg;
struct hciuart_state_s *state;
irqstate_t flags;
ssize_t nbytes;
flags = spin_lock_irqsave(&config->lock);
sched_lock();
if (config.state->rxdmastream == NULL)
{
spin_unlock_irqrestore(&config->lock, flags);
sched_unlock();
return;
}
wlinfo("status %u config %p\n", status, config);
DEBUGASSERT(config != NULL && config->state != NULL);
@ -2417,6 +2435,9 @@ static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status,
state->callback(config->lower, state->arg);
handled = true;
}
spin_unlock_irqrestore(&config->lock, flags);
sched_unlock();
}
#endif
@ -2639,59 +2660,35 @@ void hciuart_initialize(void)
#ifdef CONFIG_STM32_HCIUART_RXDMA
void stm32_serial_dma_poll(void)
{
irqstate_t flags;
flags = spin_lock_irqsave(NULL);
#ifdef CONFIG_STM32_HCIUART1_RXDMA
if (g_hciusart1_config.state->rxdmastream != NULL)
{
hciuart_dma_rxcallback(g_hciusart1_config.state->rxdmastream, 0,
&g_hciusart1_config);
}
hciuart_dma_rxcallback(g_hciusart1_config.state->rxdmastream, 0,
&g_hciusart1_config);
#endif
#ifdef CONFIG_STM32_HCIUART2_RXDMA
if (g_hciusart2_config.state->rxdmastream != NULL)
{
hciuart_dma_rxcallback(g_hciusart2_config.state->rxdmastream, 0,
hciuart_dma_rxcallback(g_hciusart2_config.state->rxdmastream, 0,
&g_hciusart2_config);
}
#endif
#ifdef CONFIG_STM32_HCIUART3_RXDMA
if (g_hciusart3_config.state->rxdmastream != NULL)
{
hciuart_dma_rxcallback(g_hciusart3_config.state->rxdmastream, 0,
&g_hciusart3_config);
}
hciuart_dma_rxcallback(g_hciusart3_config.state->rxdmastream, 0,
&g_hciusart3_config);
#endif
#ifdef CONFIG_STM32_HCIUART6_RXDMA
if (g_hciusart6_config.state->rxdmastream != NULL)
{
hciuart_dma_rxcallback(g_hciusart6_config.state->rxdmastream, 0,
&g_hciusart6_config);
}
hciuart_dma_rxcallback(g_hciusart6_config.state->rxdmastream, 0,
&g_hciusart6_config);
#endif
#ifdef CONFIG_STM32_HCIUART7_RXDMA
if (g_hciuart7_config.state->rxdmastream != NULL)
{
hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream,
0,
&g_hciuart7_config);
}
hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream,
0,
&g_hciuart7_config);
#endif
#ifdef CONFIG_STM32_HCIUART8_RXDMA
if (g_hciuart8_config.state->rxdmastream != NULL)
{
hciuart_dma_rxcallback(g_hciuart8.state->rxdmastream, 0,
&g_hciuart8_config);
}
hciuart_dma_rxcallback(g_hciuart8.state->rxdmastream, 0,
&g_hciuart8_config);
#endif
spin_unlock_irqrestore(NULL, flags);
}
#endif

11
arch/arm/src/stm32/stm32_qencoder.c
View file

@ -322,6 +322,7 @@ struct stm32_lowerhalf_s
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
volatile int32_t position; /* The current position offset */
#endif
spinlock_t lock;
};
/****************************************************************************
@ -406,6 +407,7 @@ static struct stm32_lowerhalf_s g_tim1lower =
.ops = &g_qecallbacks,
.config = &g_tim1config,
.inuse = false,
.lock = SP_UNLOCKED,
};
#endif
@ -431,6 +433,7 @@ static struct stm32_lowerhalf_s g_tim2lower =
.ops = &g_qecallbacks,
.config = &g_tim2config,
.inuse = false,
.lock = SP_UNLOCKED,
};
#endif
@ -456,6 +459,7 @@ static struct stm32_lowerhalf_s g_tim3lower =
.ops = &g_qecallbacks,
.config = &g_tim3config,
.inuse = false,
.lock = SP_UNLOCKED,
};
#endif
@ -481,6 +485,7 @@ static struct stm32_lowerhalf_s g_tim4lower =
.ops = &g_qecallbacks,
.config = &g_tim4config,
.inuse = false,
.lock = SP_UNLOCKED,
};
#endif
@ -506,6 +511,7 @@ static struct stm32_lowerhalf_s g_tim5lower =
.ops = &g_qecallbacks,
.config = &g_tim5config,
.inuse = false,
.lock = SP_UNLOCKED,
};
#endif
@ -531,6 +537,7 @@ static struct stm32_lowerhalf_s g_tim8lower =
.ops = &g_qecallbacks,
.config = &g_tim8config,
.inuse = false,
.lock = SP_UNLOCKED,
};
#endif
@ -1196,7 +1203,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
/* Loop until we are certain that no interrupt occurred between samples */
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
do
{
position = priv->position;
@ -1204,7 +1211,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
verify = priv->position;
}
while (position != verify);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
/* Return the position measurement */

18
arch/arm/src/stm32/stm32_serial.c
View file

@ -491,6 +491,7 @@ struct up_dev_s
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR TXEN polarity */
#endif
const bool islpuart; /* Is this device a Low Power UART? */
spinlock_t lock; /* Spinlock */
};
/****************************************************************************
@ -783,6 +784,7 @@ static struct up_dev_s g_usart1priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -852,6 +854,7 @@ static struct up_dev_s g_usart2priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -921,6 +924,7 @@ static struct up_dev_s g_usart3priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -990,6 +994,7 @@ static struct up_dev_s g_uart4priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -1059,6 +1064,7 @@ static struct up_dev_s g_uart5priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -1128,6 +1134,7 @@ static struct up_dev_s g_usart6priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -1197,6 +1204,7 @@ static struct up_dev_s g_uart7priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -1266,6 +1274,7 @@ static struct up_dev_s g_uart8priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -1334,6 +1343,7 @@ static struct up_dev_s g_lpuart1priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -1442,11 +1452,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
{
irqstate_t flags;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
up_setusartint(priv, ie);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
}
/****************************************************************************
@ -1457,7 +1467,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
{
irqstate_t flags;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
if (ie)
{
@ -1498,7 +1508,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
up_setusartint(priv, 0);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
}
/****************************************************************************

10
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
View file

@ -250,6 +250,7 @@ struct stm32_serial_s
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
#endif
spinlock_t lock; /* Spinlock */
};
/****************************************************************************
@ -445,6 +446,7 @@ static struct stm32_serial_s g_usart1priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -506,6 +508,7 @@ static struct stm32_serial_s g_usart2priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -567,6 +570,7 @@ static struct stm32_serial_s g_usart3priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -632,6 +636,7 @@ static struct stm32_serial_s g_usart4priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -697,6 +702,7 @@ static struct stm32_serial_s g_usart5priv =
.rs485_dir_polarity = true,
# endif
# endif
.lock = SP_UNLOCKED,
};
#endif
@ -806,7 +812,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv,
{
irqstate_t flags;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&priv->lock);
if (ie)
{
@ -850,7 +856,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv,
stm32serial_setusartint(priv, 0);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&priv->lock, flags);
}
/****************************************************************************