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arm64: fix use arch-timer in SMP
reason: only one timer will be effective at a time. Signed-off-by: hujun5 <hujun5@xiaomi.com>
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parent
ea29217442
commit
c039ea77ba
1 changed files with 8 additions and 4 deletions
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@ -70,8 +70,11 @@ struct arm64_oneshot_lowerhalf_s
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void *arg; /* Argument that is passed to the handler */
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uint64_t cycle_per_tick; /* cycle per tick */
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oneshot_callback_t callback; /* Internal handler that receives callback */
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bool running; /* True: timer is running */
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bool init[CONFIG_SMP_NCPUS]; /* True: timer is init */
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/* which cpu timer is running, -1 indicate timer stoppd */
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int running;
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};
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/****************************************************************************
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@ -157,7 +160,7 @@ static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
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arm64_arch_timer_set_irq_mask(true);
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if (priv->callback && priv->running)
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if (priv->callback && priv->running == this_cpu())
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{
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/* Then perform the callback */
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@ -228,7 +231,7 @@ static int arm64_tick_cancel(struct oneshot_lowerhalf_s *lower,
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/* Disable int */
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priv->running = false;
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priv->running = -1;
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arm64_arch_timer_set_irq_mask(true);
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return OK;
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@ -281,7 +284,7 @@ static int arm64_tick_start(struct oneshot_lowerhalf_s *lower,
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priv->init[this_cpu()] = true;
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}
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priv->running = true;
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priv->running = this_cpu();
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next_cycle =
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arm64_arch_timer_count() / priv->cycle_per_tick * priv->cycle_per_tick +
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@ -374,6 +377,7 @@ struct oneshot_lowerhalf_s *arm64_oneshot_initialize(void)
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/* Initialize the lower-half driver structure */
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priv->lh.ops = &g_oneshot_ops;
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priv->running = -1;
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priv->cycle_per_tick = arm64_arch_timer_get_cntfrq() / TICK_PER_SEC;
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tmrinfo("cycle_per_tick %" PRIu64 "\n", priv->cycle_per_tick);
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