mirror of
https://github.com/apache/nuttx.git
synced 2025-01-13 02:48:37 +08:00
use small lock in following files:
arch/arm/src/stm32f0l0g0/stm32_serial_v2.c arch/arm/src/stm32f7/stm32_qencoder.c arch/arm/src/stm32f7/stm32_serial.c arch/arm/src/stm32h5/stm32_serial.c arch/arm/src/stm32h7/stm32_qencoder.c arch/arm/src/stm32h7/stm32_serial.c arch/arm/src/stm32l4/stm32l4_qencoder.c arch/arm/src/stm32l4/stm32l4_serial.c arch/arm/src/stm32l5/stm32l5_serial.c arch/arm/src/stm32u5/stm32_serial.c arch/arm/src/stm32wb/stm32wb_serial.c arch/arm/src/stm32wl5/stm32wl5_serial.c arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c arch/risc-v/src/rv32m1/rv32m1_serial.c Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
Xiang Xiao
parent
798695a4f7
commit
c96b8cdfdd
14 changed files with 140 additions and 48 deletions
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@ -158,6 +158,7 @@ struct up_dev_s
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const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
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const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
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#endif
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spinlock_t lock;
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};
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/****************************************************************************
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@ -285,6 +286,7 @@ static struct up_dev_s g_usart1priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -339,6 +341,7 @@ static struct up_dev_s g_usart2priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -393,6 +396,7 @@ static struct up_dev_s g_usart3priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -447,6 +451,7 @@ static struct up_dev_s g_usart4priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -534,11 +539,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
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{
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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up_setusartint(priv, ie);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/****************************************************************************
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@ -549,7 +554,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
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{
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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if (ie)
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{
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@ -593,7 +598,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
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up_setusartint(priv, 0);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/****************************************************************************
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@ -214,6 +214,7 @@ struct stm32_lowerhalf_s
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#ifdef HAVE_16BIT_TIMERS
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volatile int32_t position; /* The current position offset */
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#endif
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spinlock_t lock;
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};
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/****************************************************************************
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@ -296,6 +297,7 @@ static struct stm32_lowerhalf_s g_tim1lower =
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.ops = &g_qecallbacks,
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.config = &g_tim1config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -321,6 +323,7 @@ static struct stm32_lowerhalf_s g_tim2lower =
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.ops = &g_qecallbacks,
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.config = &g_tim2config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -346,6 +349,7 @@ static struct stm32_lowerhalf_s g_tim3lower =
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.ops = &g_qecallbacks,
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.config = &g_tim3config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -371,6 +375,7 @@ static struct stm32_lowerhalf_s g_tim4lower =
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.ops = &g_qecallbacks,
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.config = &g_tim4config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -396,6 +401,7 @@ static struct stm32_lowerhalf_s g_tim5lower =
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.ops = &g_qecallbacks,
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.config = &g_tim5config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -421,6 +427,7 @@ static struct stm32_lowerhalf_s g_tim8lower =
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.ops = &g_qecallbacks,
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.config = &g_tim8config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1034,7 +1041,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
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/* Loop until we are certain that no interrupt occurred between samples */
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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do
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{
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position = priv->position;
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@ -1042,7 +1049,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
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verify = priv->position;
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}
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while (position != verify);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Return the position measurement */
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@ -507,6 +507,7 @@ struct up_dev_s
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const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for
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* TX enabled */
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#endif
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spinlock_t lock;
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};
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#ifdef CONFIG_PM
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@ -832,6 +833,7 @@ static struct up_dev_s g_usart1priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -900,6 +902,7 @@ static struct up_dev_s g_usart2priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -968,6 +971,7 @@ static struct up_dev_s g_usart3priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1036,6 +1040,7 @@ static struct up_dev_s g_uart4priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1104,6 +1109,7 @@ static struct up_dev_s g_uart5priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1172,6 +1178,7 @@ static struct up_dev_s g_usart6priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1240,6 +1247,7 @@ static struct up_dev_s g_uart7priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1308,6 +1316,7 @@ static struct up_dev_s g_uart8priv =
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.rs485_dir_polarity = true,
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# endif
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#endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1408,11 +1417,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
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{
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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up_setusartint(priv, ie);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/****************************************************************************
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@ -1423,7 +1432,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
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{
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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if (ie)
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{
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@ -1467,7 +1476,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
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up_setusartint(priv, 0);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/****************************************************************************
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@ -296,6 +296,7 @@ struct stm32_serial_s
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const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
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#endif
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const bool islpuart; /* Is this device a Low Power UART? */
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spinlock_t lock;
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};
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/****************************************************************************
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@ -506,6 +507,7 @@ static struct stm32_serial_s g_lpuart1priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -566,6 +568,7 @@ static struct stm32_serial_s g_usart1priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -628,6 +631,7 @@ static struct stm32_serial_s g_usart2priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -690,6 +694,7 @@ static struct stm32_serial_s g_usart3priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -752,6 +757,7 @@ static struct stm32_serial_s g_uart4priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -814,6 +820,7 @@ static struct stm32_serial_s g_uart5priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -876,6 +883,7 @@ static struct stm32_serial_s g_usart6priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -938,6 +946,7 @@ static struct stm32_serial_s g_uart7priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1000,6 +1009,7 @@ static struct stm32_serial_s g_uart8priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1062,6 +1072,7 @@ static struct stm32_serial_s g_uart9priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1124,6 +1135,7 @@ static struct stm32_serial_s g_usart10priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1186,6 +1198,7 @@ static struct stm32_serial_s g_usart11priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1248,6 +1261,7 @@ static struct stm32_serial_s g_uart12priv =
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.rs485_dir_polarity = true,
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# endif
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# endif
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1375,11 +1389,11 @@ static void stm32serial_restoreusartint(struct stm32_serial_s *priv,
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{
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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stm32serial_setusartint(priv, ie);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/****************************************************************************
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@ -1391,7 +1405,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv,
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{
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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if (ie)
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{
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@ -1434,7 +1448,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv,
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stm32serial_setusartint(priv, 0);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/****************************************************************************
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@ -214,6 +214,7 @@ struct stm32_lowerhalf_s
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#ifdef HAVE_16BIT_TIMERS
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volatile int32_t position; /* The current position offset */
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#endif
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spinlock_t lock;
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};
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/****************************************************************************
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@ -296,6 +297,7 @@ static struct stm32_lowerhalf_s g_tim1lower =
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.ops = &g_qecallbacks,
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.config = &g_tim1config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -321,6 +323,7 @@ static struct stm32_lowerhalf_s g_tim2lower =
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.ops = &g_qecallbacks,
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.config = &g_tim2config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -346,6 +349,7 @@ static struct stm32_lowerhalf_s g_tim3lower =
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.ops = &g_qecallbacks,
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.config = &g_tim3config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -371,6 +375,7 @@ static struct stm32_lowerhalf_s g_tim4lower =
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.ops = &g_qecallbacks,
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.config = &g_tim4config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -396,6 +401,7 @@ static struct stm32_lowerhalf_s g_tim5lower =
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.ops = &g_qecallbacks,
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.config = &g_tim5config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -421,6 +427,7 @@ static struct stm32_lowerhalf_s g_tim8lower =
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.ops = &g_qecallbacks,
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.config = &g_tim8config,
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.inuse = false,
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.lock = SP_UNLOCKED,
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};
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#endif
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@ -1035,7 +1042,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
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/* Loop until we are certain that no interrupt occurred between samples */
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&priv->lock);
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do
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{
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position = priv->position;
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||||
|
|
@ -1043,7 +1050,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
|
|||
verify = priv->position;
|
||||
}
|
||||
while (position != verify);
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
/* Return the position measurement */
|
||||
|
||||
|
|
|
|||
|
|
@ -654,6 +654,7 @@ struct up_dev_s
|
|||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -981,6 +982,7 @@ static struct up_dev_s g_usart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1050,6 +1052,7 @@ static struct up_dev_s g_usart2priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1119,6 +1122,7 @@ static struct up_dev_s g_usart3priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1188,6 +1192,7 @@ static struct up_dev_s g_uart4priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1257,6 +1262,7 @@ static struct up_dev_s g_uart5priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1326,6 +1332,7 @@ static struct up_dev_s g_usart6priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1395,6 +1402,7 @@ static struct up_dev_s g_uart7priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1464,6 +1472,7 @@ static struct up_dev_s g_uart8priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1569,11 +1578,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
up_setusartint(priv, ie);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1585,7 +1594,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
if (ie)
|
||||
{
|
||||
|
|
@ -1629,7 +1638,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
|
|||
|
||||
up_setusartint(priv, 0);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -209,6 +209,7 @@ struct stm32l4_lowerhalf_s
|
|||
#ifdef HAVE_16BIT_TIMERS
|
||||
volatile int32_t position; /* The current position offset */
|
||||
#endif
|
||||
spinlock_t lock; /* Spinlock */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -289,6 +290,7 @@ static struct stm32l4_lowerhalf_s g_tim1lower =
|
|||
.ops = &g_qecallbacks,
|
||||
.config = &g_tim1config,
|
||||
.inuse = false,
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -312,6 +314,7 @@ static struct stm32l4_lowerhalf_s g_tim2lower =
|
|||
.ops = &g_qecallbacks,
|
||||
.config = &g_tim2config,
|
||||
.inuse = false,
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -335,6 +338,7 @@ static struct stm32l4_lowerhalf_s g_tim3lower =
|
|||
.ops = &g_qecallbacks,
|
||||
.config = &g_tim3config,
|
||||
.inuse = false,
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -358,6 +362,7 @@ static struct stm32l4_lowerhalf_s g_tim4lower =
|
|||
.ops = &g_qecallbacks,
|
||||
.config = &g_tim4config,
|
||||
.inuse = false,
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -381,6 +386,7 @@ static struct stm32l4_lowerhalf_s g_tim5lower =
|
|||
.ops = &g_qecallbacks,
|
||||
.config = &g_tim5config,
|
||||
.inuse = false,
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -404,6 +410,7 @@ static struct stm32l4_lowerhalf_s g_tim8lower =
|
|||
.ops = &g_qecallbacks,
|
||||
.config = &g_tim8config,
|
||||
.inuse = false,
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1036,7 +1043,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower,
|
|||
|
||||
/* Loop until we are certain that no interrupt occurred between samples */
|
||||
|
||||
spin_lock_irqsave(NULL);
|
||||
spin_lock_irqsave(&priv->lock);
|
||||
do
|
||||
{
|
||||
position = priv->position;
|
||||
|
|
@ -1044,7 +1051,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower,
|
|||
verify = priv->position;
|
||||
}
|
||||
while (position != verify);
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
/* Return the position measurement */
|
||||
|
||||
|
|
|
|||
|
|
@ -287,6 +287,7 @@ struct stm32l4_serial_s
|
|||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -496,6 +497,7 @@ static struct stm32l4_serial_s g_lpuart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -557,6 +559,7 @@ static struct stm32l4_serial_s g_usart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -618,6 +621,7 @@ static struct stm32l4_serial_s g_usart2priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -679,6 +683,7 @@ static struct stm32l4_serial_s g_usart3priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -740,6 +745,7 @@ static struct stm32l4_serial_s g_uart4priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -801,6 +807,7 @@ static struct stm32l4_serial_s g_uart5priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -904,11 +911,11 @@ static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
stm32l4serial_setusartint(priv, ie);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -920,7 +927,7 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
if (ie)
|
||||
{
|
||||
|
|
@ -968,7 +975,7 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv,
|
|||
|
||||
stm32l4serial_setusartint(priv, 0);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -290,6 +290,7 @@ struct stm32l5_serial_s
|
|||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -500,6 +501,7 @@ static struct stm32l5_serial_s g_lpuart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -559,6 +561,7 @@ static struct stm32l5_serial_s g_usart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -620,6 +623,7 @@ static struct stm32l5_serial_s g_usart2priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -681,6 +685,7 @@ static struct stm32l5_serial_s g_usart3priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -742,6 +747,7 @@ static struct stm32l5_serial_s g_uart4priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -803,6 +809,7 @@ static struct stm32l5_serial_s g_uart5priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -909,11 +916,11 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
stm32l5serial_setusartint(priv, ie);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -925,7 +932,7 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
if (ie)
|
||||
{
|
||||
|
|
@ -968,7 +975,7 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv,
|
|||
|
||||
stm32l5serial_setusartint(priv, 0);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -290,6 +290,7 @@ struct stm32_serial_s
|
|||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -500,6 +501,7 @@ static struct stm32_serial_s g_lpuart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -559,6 +561,7 @@ static struct stm32_serial_s g_usart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -620,6 +623,7 @@ static struct stm32_serial_s g_usart2priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -681,6 +685,7 @@ static struct stm32_serial_s g_usart3priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -742,6 +747,7 @@ static struct stm32_serial_s g_uart4priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -803,6 +809,7 @@ static struct stm32_serial_s g_uart5priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -925,7 +932,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
if (ie)
|
||||
{
|
||||
|
|
@ -968,7 +975,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv,
|
|||
|
||||
stm32serial_setusartint(priv, 0);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -231,6 +231,7 @@ struct stm32wb_serial_s
|
|||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -408,6 +409,7 @@ static struct stm32wb_serial_s g_lpuart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -469,6 +471,7 @@ static struct stm32wb_serial_s g_usart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -559,11 +562,11 @@ static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
stm32wb_serial_setusartint(priv, ie);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -575,7 +578,7 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
if (ie)
|
||||
{
|
||||
|
|
@ -623,7 +626,7 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv,
|
|||
|
||||
stm32wb_serial_setusartint(priv, 0);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -261,6 +261,7 @@ struct stm32wl5_serial_s
|
|||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -448,6 +449,7 @@ static struct stm32wl5_serial_s g_lpuart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -507,6 +509,7 @@ static struct stm32wl5_serial_s g_usart1priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -568,6 +571,7 @@ static struct stm32wl5_serial_s g_usart2priv =
|
|||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
# endif
|
||||
.lock = SP_UNLOCKED,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -664,11 +668,11 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
stm32wl5serial_setusartint(priv, ie);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -680,7 +684,7 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv,
|
|||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
if (ie)
|
||||
{
|
||||
|
|
@ -723,7 +727,7 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv,
|
|||
|
||||
stm32wl5serial_setusartint(priv, 0);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@
|
|||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static spinlock_t g_cc13xx_enablepwr_lock = SP_UNLOCKED;
|
||||
static uint16_t g_domain_usage[2];
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -66,13 +67,13 @@ void cc13xx_periph_enablepwr(uint32_t peripheral)
|
|||
|
||||
/* Remember that this peripheral needs power in this domain */
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&g_cc13xx_enablepwr_lock);
|
||||
g_domain_usage[dndx] |= (1 << pndx);
|
||||
|
||||
/* Make sure that power is enabled in that domain */
|
||||
|
||||
prcm_powerdomain_on(domain);
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&g_cc13xx_enablepwr_lock, flags);
|
||||
|
||||
/* Wait for the power domain to be ready. REVISIT: This really should be
|
||||
* in the critical section but this could take too long.
|
||||
|
|
@ -100,7 +101,7 @@ void cc13xx_periph_disablepwr(uint32_t peripheral)
|
|||
|
||||
/* This peripheral no longer needs power in this domain */
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
flags = spin_lock_irqsave(&g_cc13xx_enablepwr_lock);
|
||||
g_domain_usage[dndx] &= ~(1 << pndx);
|
||||
|
||||
/* If there are no peripherals needing power in this domain, then turn off
|
||||
|
|
@ -113,5 +114,5 @@ void cc13xx_periph_disablepwr(uint32_t peripheral)
|
|||
PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&g_cc13xx_enablepwr_lock, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -119,6 +119,7 @@ struct up_dev_s
|
|||
const uintptr_t pcc; /* Address of UART PCC clock gate */
|
||||
const uint32_t tx_gpio; /* LPUART TX GPIO pin configuration */
|
||||
const uint32_t rx_gpio; /* LPUART RX GPIO pin configuration */
|
||||
spinlock_t lock; /* Spinlock */
|
||||
uint32_t baud; /* Configured baud */
|
||||
uint16_t irq; /* IRQ associated with this UART */
|
||||
};
|
||||
|
|
@ -188,6 +189,7 @@ static struct up_dev_s g_uart0priv =
|
|||
.pcc = RV32M1_PCC_LPUART0,
|
||||
.tx_gpio = GPIO_LPUART0_TX,
|
||||
.rx_gpio = GPIO_LPUART0_RX,
|
||||
.lock = SP_UNLOCKED,
|
||||
.baud = CONFIG_LPUART0_BAUD,
|
||||
.irq = RV32M1_IRQ_LPUART0,
|
||||
};
|
||||
|
|
@ -223,6 +225,7 @@ static struct up_dev_s g_uart1priv =
|
|||
.pcc = RV32M1_PCC_LPUART1,
|
||||
.tx_gpio = GPIO_LPUART1_TX,
|
||||
.rx_gpio = GPIO_LPUART1_RX,
|
||||
.lock = SP_UNLOCKED,
|
||||
.baud = CONFIG_LPUART1_BAUD,
|
||||
.irq = RV32M1_IRQ_LPUART1,
|
||||
};
|
||||
|
|
@ -258,6 +261,7 @@ static struct up_dev_s g_uart2priv =
|
|||
.pcc = RV32M1_PCC_LPUART2,
|
||||
.tx_gpio = GPIO_LPUART2_TX,
|
||||
.rx_gpio = GPIO_LPUART2_RX,
|
||||
.lock = SP_UNLOCKED,
|
||||
.baud = CONFIG_LPUART2_BAUD,
|
||||
.irq = RV32M1_IRQ_LPUART2,
|
||||
};
|
||||
|
|
@ -293,6 +297,7 @@ static struct up_dev_s g_uart3priv =
|
|||
.pcc = RV32M1_PCC_LPUART3,
|
||||
.tx_gpio = GPIO_LPUART3_TX,
|
||||
.rx_gpio = GPIO_LPUART3_RX,
|
||||
.lock = SP_UNLOCKED,
|
||||
.baud = CONFIG_LPUART3_BAUD,
|
||||
.irq = RV32M1_IRQ_LPUART3,
|
||||
};
|
||||
|
|
@ -346,11 +351,11 @@ static void up_putreg(struct up_dev_s *priv, int offset, uint32_t value)
|
|||
|
||||
static void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
|
||||
{
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
irqstate_t flags = spin_lock_irqsave(&priv->lock);
|
||||
|
||||
up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, im);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -359,7 +364,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
|
|||
|
||||
static void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
|
||||
{
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
irqstate_t flags = spin_lock_irqsave(&priv->lock);
|
||||
uint32_t regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET);
|
||||
|
||||
/* Return the current interrupt mask value */
|
||||
|
|
@ -374,7 +379,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
|
|||
regval &= ~(LPUART_CTRL_TCIE | LPUART_CTRL_TIE | LPUART_CTRL_RIE);
|
||||
up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in a new issue