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Make Pirelli-DLP10 a true board configuration; Calypso no compiles without errors

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This commit is contained in:
Gregory Nutt 2013-05-05 09:10:47 -06:00
parent 4ac0990853
commit ca5641f2d7
18 changed files with 449 additions and 253 deletions
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2
ChangeLog
View file

@ -4669,5 +4669,5 @@
* drivers/mtd/m25px.c: Some rearchitecting to use the byte write
capability (when possible) and to use 4KB sectors for the erase block
size when the part supports it (Ken Pettit, 2013-5-3).
* configs/pirelli_dp10: Adds a configuration for the pirelli phone
* configs/pirelli_dpl10: Adds a configuration for the pirelli phone
(from Alan Alan Carvalho de Assis, 2013-5-3).

6
Documentation/README.html
View file

@ -92,6 +92,8 @@
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/ez80f910200zco/README.txt"><b><i>README.txt</i></b></a>
| | |- fire-stm32v2/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/fire-stm32v2/README.txt"><b><i>README.txt</i></b></a>
| | |- freedom-kl25z/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/freedom-kl25z/README.txt"><b><i>README.txt</i></b></a>
| | |- hymini-stm32v/
| | | |- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/hymini-stm32v/include/README.txt">include/README.txt</a>
| | | |- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/hymini-stm32v/RIDE/README.txt">RIDE/README.txt</a>
@ -128,6 +130,8 @@
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/mcu123-lpc214x/README.txt"><b><i>README.txt</i></b></a>
| | |- micropendous3/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/micropendous3/README.txt"><b><i>README.txt</i></b></a>
| | |- mikroe-stm32f4/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/mikroe-stm32f4/README.txt"><b><i>README.txt</i></b></a>
| | |- mirtoo/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/mirtoo/README.txt"><b><i>README.txt</i></b></a>
| | |- mx1ads/
@ -164,6 +168,8 @@
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/pic32-starterkit/README.txt"><b><i>README.txt</i></b></a>
| | |- pic32mx7mmb/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/pic32mx7mmb/README.txt"><b><i>README.txt</i></b></a>
| | |- pirelli_dpl10/
| | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/pirelli_dpl10/README.txt"><b><i>README.txt</i></b></a>
| | |- pjrc-8051/
| | | |- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/pjrc-8051/include/README.txt">include/README.txt</a>
| | | |- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/pjrc-8051/src/README.txt">src/README.txt</a>

6
README.txt
View file

@ -1021,6 +1021,8 @@ nuttx
| | `- README.txt
| |- fire-stm32v2/
| | `- README.txt
| |- freedom-kl25z/
| | `- README.txt
| |- hymini-stm32v/
| | |- include/README.txt
| | |- src/README.txt
@ -1056,6 +1058,8 @@ nuttx
| | `- README.txt
| |- micropendous3/
| | `- README.txt
| |- mikroe-stm32f/
| | `- README.txt
| |- mirtoo/
| | `- README.txt
| |- mx1ads/
@ -1092,6 +1096,8 @@ nuttx
| | `- README.txt
| |- pic32mx7mmb/
| | `- README.txt
| |- pirelli_dpl10/
| | `- README.txt
| |- pjrc-8051/
| | |- include/README.txt
| | |- src/README.txt

7
arch/arm/include/calypso/armio.h
View file

@ -34,19 +34,16 @@
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Prototypes for interrupt handling
****************************************************************************/
void calypso_kbd_irq();
void calypso_gpio_irq();
inline int calypso_kbd_irq(int irq, uint32_t *regs);
/****************************************************************************
* Initialize device, add /dev/... nodes
****************************************************************************/
void calypso_armio(void);
void calypso_keypad(void);

61
arch/arm/src/calypso/calypso_armio.c
View file

@ -47,30 +47,29 @@
* HW access
****************************************************************************/
#define BASE_ADDR_ARMIO 0xfffe4800
#define ARMIO_REG(x) ((void *)BASE_ADDR_ARMIO + (x))
#define BASE_ADDR_ARMIO 0xfffe4800
#define ARMIO_REG(x) (BASE_ADDR_ARMIO + (x))
enum armio_reg {
LATCH_IN = 0x00,
LATCH_OUT = 0x02,
IO_CNTL = 0x04,
CNTL_REG = 0x06,
LOAD_TIM = 0x08,
KBR_LATCH_REG = 0x0a,
KBC_REG = 0x0c,
BUZZ_LIGHT_REG = 0x0e,
LIGHT_LEVEL = 0x10,
BUZZER_LEVEL = 0x12,
GPIO_EVENT_MODE = 0x14,
KBD_GPIO_INT = 0x16,
KBD_GPIO_MASKIT = 0x18,
GPIO_DEBOUNCING = 0x1a,
GPIO_LATCH = 0x1c,
LATCH_IN = 0x00,
LATCH_OUT = 0x02,
IO_CNTL = 0x04,
CNTL_REG = 0x06,
LOAD_TIM = 0x08,
KBR_LATCH_REG = 0x0a,
KBC_REG = 0x0c,
BUZZ_LIGHT_REG = 0x0e,
LIGHT_LEVEL = 0x10,
BUZZER_LEVEL = 0x12,
GPIO_EVENT_MODE = 0x14,
KBD_GPIO_INT = 0x16,
KBD_GPIO_MASKIT = 0x18,
GPIO_DEBOUNCING = 0x1a,
GPIO_LATCH = 0x1c,
};
#define KBD_INT (1<<0)
#define GPIO_INT (1<<1)
#define KBD_INT (1 << 0)
#define GPIO_INT (1 << 1)
/****************************************************************************
* ARMIO interrupt handler
@ -80,25 +79,25 @@ enum armio_reg {
static int kbd_gpio_irq(int irq, uint32_t *regs)
{
calypso_kbd_irq();
return 0;
return calypso_kbd_irq(irq, regs);
}
/****************************************************************************
* Initialize ARMIO
****************************************************************************/
void calypso_armio(void)
{
/* Enable ARMIO clock */
putreg16(1<<5, ARMIO_REG(CNTL_REG));
/* Enable ARMIO clock */
/* Mask GPIO interrupt and keypad interrupt */
putreg16(KBD_INT|GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
putreg16(1<<5, ARMIO_REG(CNTL_REG));
/* Attach and enable the interrupt */
irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
up_enable_irq(IRQ_KEYPAD_GPIO);
/* Mask GPIO interrupt and keypad interrupt */
putreg16(KBD_INT|GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
/* Attach and enable the interrupt */
irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
up_enable_irq(IRQ_KEYPAD_GPIO);
}

280
arch/arm/src/calypso/calypso_irq.c
View file

@ -47,7 +47,9 @@
#include <stdint.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/calypso/memory.h>
#include <arch/calypso/clock.h>
#include "arm.h"
#include "up_arch.h"
@ -56,21 +58,22 @@
* Pre-processor Definitions
****************************************************************************/
#define BASE_ADDR_IRQ 0xfffffa00
#define BASE_ADDR_IBOOT_EXC 0x0080001C
#define BASE_ADDR_IRQ 0xfffffa00
#define BASE_ADDR_IBOOT_EXC 0x0080001C
enum irq_reg {
IT_REG1 = 0x00,
IT_REG2 = 0x02,
MASK_IT_REG1 = 0x08,
MASK_IT_REG2 = 0x0a,
IRQ_NUM = 0x10,
FIQ_NUM = 0x12,
IRQ_CTRL = 0x14,
enum irq_reg
{
IT_REG1 = 0x00,
IT_REG2 = 0x02,
MASK_IT_REG1 = 0x08,
MASK_IT_REG2 = 0x0a,
IRQ_NUM = 0x10,
FIQ_NUM = 0x12,
IRQ_CTRL = 0x14,
};
#define ILR_IRQ(x) (0x20 + (x*2))
#define IRQ_REG(x) ((void *)BASE_ADDR_IRQ + (x))
#define ILR_IRQ(x) (0x20 + (x*2))
#define IRQ_REG(x) (BASE_ADDR_IRQ + (x))
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@ -87,28 +90,29 @@ extern uint32_t _exceptions;
* Private Data
****************************************************************************/
static uint8_t default_irq_prio[] = {
[IRQ_WATCHDOG] = 0xff,
[IRQ_TIMER1] = 0xff,
[IRQ_TIMER2] = 0xff,
[IRQ_TSP_RX] = 0,
[IRQ_TPU_FRAME] = 3,
[IRQ_TPU_PAGE] = 0xff,
[IRQ_SIMCARD] = 0xff,
[IRQ_UART_MODEM] = 8,
[IRQ_KEYPAD_GPIO] = 4,
[IRQ_RTC_TIMER] = 9,
[IRQ_RTC_ALARM_I2C] = 10,
[IRQ_ULPD_GAUGING] = 2,
[IRQ_EXTERNAL] = 12,
[IRQ_SPI] = 0xff,
[IRQ_DMA] = 0xff,
[IRQ_API] = 0xff,
[IRQ_SIM_DETECT] = 0,
[IRQ_EXTERNAL_FIQ] = 7,
[IRQ_UART_IRDA] = 2,
[IRQ_ULPD_GSM_TIMER] = 1,
[IRQ_GEA] = 0xff,
static uint8_t default_irq_prio[] =
{
[IRQ_WATCHDOG] = 0xff,
[IRQ_TIMER1] = 0xff,
[IRQ_TIMER2] = 0xff,
[IRQ_TSP_RX] = 0,
[IRQ_TPU_FRAME] = 3,
[IRQ_TPU_PAGE] = 0xff,
[IRQ_SIMCARD] = 0xff,
[IRQ_UART_MODEM] = 8,
[IRQ_KEYPAD_GPIO] = 4,
[IRQ_RTC_TIMER] = 9,
[IRQ_RTC_ALARM_I2C] = 10,
[IRQ_ULPD_GAUGING] = 2,
[IRQ_EXTERNAL] = 12,
[IRQ_SPI] = 0xff,
[IRQ_DMA] = 0xff,
[IRQ_API] = 0xff,
[IRQ_SIM_DETECT] = 0,
[IRQ_EXTERNAL_FIQ] = 7,
[IRQ_UART_IRDA] = 2,
[IRQ_ULPD_GSM_TIMER] = 1,
[IRQ_GEA] = 0xff,
};
/****************************************************************************
@ -117,53 +121,66 @@ static uint8_t default_irq_prio[] = {
static void _irq_enable(enum irq_nr nr, int enable)
{
uint16_t *reg = IRQ_REG(MASK_IT_REG1);
uint16_t val;
uintptr_t reg = IRQ_REG(MASK_IT_REG1);
uint16_t val;
if (nr > 15) {
reg = IRQ_REG(MASK_IT_REG2);
nr -= 16;
}
if (nr > 15)
{
reg = IRQ_REG(MASK_IT_REG2);
nr -= 16;
}
val = getreg16(reg);
if (enable)
val &= ~(1 << nr);
else
val |= (1 << nr);
putreg16(val, reg);
val = getreg16(reg);
if (enable)
{
val &= ~(1 << nr);
}
else
{
val |= (1 << nr);
}
putreg16(val, reg);
}
static void set_default_priorities(void)
{
unsigned int i;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++) {
uint16_t val;
uint8_t prio = default_irq_prio[i];
if (prio > 31)
prio = 31;
for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++)
{
uint16_t val;
uint8_t prio = default_irq_prio[i];
val = getreg16(IRQ_REG(ILR_IRQ(i)));
val &= ~(0x1f << 2);
val |= prio << 2;
if (prio > 31)
{
prio = 31;
}
/* Make edge mode default. Hopefully causes less trouble */
val |= 0x02;
val = getreg16(IRQ_REG(ILR_IRQ(i)));
val &= ~(0x1f << 2);
val |= prio << 2;
putreg16(val, IRQ_REG(ILR_IRQ(i)));
}
/* Make edge mode default. Hopefully causes less trouble */
val |= 0x02;
putreg16(val, IRQ_REG(ILR_IRQ(i)));
}
}
/* Install the exception handlers to where the ROM loader jumps */
static void calypso_exceptions_install(void)
{
uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
uint32_t *exceptions_src = &_exceptions;
int i;
for (i = 0; i < 7; i++)
*exceptions_dst++ = *exceptions_src++;
uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
uint32_t *exceptions_src = &_exceptions;
int i;
for (i = 0; i < 7; i++)
{
*exceptions_dst++ = *exceptions_src++;
}
}
/****************************************************************************
@ -180,27 +197,32 @@ static void calypso_exceptions_install(void)
void up_irqinitialize(void)
{
/* Prepare hardware */
calypso_exceptions_install();
current_regs = NULL;
/* Prepare hardware */
/* Switch to internal ROM */
calypso_bootrom(1);
calypso_exceptions_install();
current_regs = NULL;
/* set default priorities */
set_default_priorities();
/* Switch to internal ROM */
/* mask all interrupts off */
putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
calypso_bootrom(1);
/* clear all pending interrupts */
putreg16(0, IRQ_REG(IT_REG1));
putreg16(0, IRQ_REG(IT_REG2));
/* Set default priorities */
set_default_priorities();
/* Mask all interrupts off */
putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
/* clear all pending interrupts */
putreg16(0, IRQ_REG(IT_REG1));
putreg16(0, IRQ_REG(IT_REG2));
/* Enable interrupts globally to the ARM core */
/* enable interrupts globally to the ARM core */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
irqrestore(SVC_MODE | PSR_F_BIT);
irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}
@ -214,8 +236,10 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
if((unsigned)irq < NR_IRQS)
_irq_enable(irq, 0);
if ((unsigned)irq < NR_IRQS)
{
_irq_enable(irq, 0);
}
}
/****************************************************************************
@ -228,8 +252,10 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
if((unsigned)irq < NR_IRQS)
_irq_enable(irq, 1);
if((unsigned)irq < NR_IRQS)
{
_irq_enable(irq, 1);
}
}
/****************************************************************************
@ -243,18 +269,22 @@ void up_enable_irq(int irq)
#ifndef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int nr, int prio)
{
uint16_t val;
uint16_t val;
if (prio == -1)
prio = default_irq_prio[nr];
if (prio == -1)
{
prio = default_irq_prio[nr];
}
if (prio > 31)
prio = 31;
if (prio > 31)
{
prio = 31;
}
val = prio << 2;
putreg16(val, IRQ_REG(ILR_IRQ(nr)));
val = prio << 2;
putreg16(val, IRQ_REG(ILR_IRQ(nr)));
return 0; // XXX: what's the return???
return 0;
}
#endif
@ -264,25 +294,28 @@ int up_prioritize_irq(int nr, int prio)
void up_decodeirq(uint32_t *regs)
{
uint8_t num, tmp;
uint32_t *saved_regs;
uint8_t num, tmp;
uint32_t *saved_regs;
/* XXX: What is this???
* Passed to but ignored in IRQ handlers
* Only valid meaning is apparently non-NULL == IRQ context */
saved_regs = (uint32_t *)current_regs;
current_regs = regs;
/* XXX: What is this???
* Passed to but ignored in IRQ handlers
* Only valid meaning is apparently non-NULL == IRQ context */
/* Detect & deliver the IRQ */
num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
irq_dispatch(num, regs);
saved_regs = (uint32_t *)current_regs;
current_regs = regs;
/* Start new IRQ agreement */
tmp = getreg8(IRQ_REG(IRQ_CTRL));
tmp |= 0x01;
putreg8(tmp, IRQ_REG(IRQ_CTRL));
/* Detect & deliver the IRQ */
current_regs = saved_regs;
num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
irq_dispatch(num, regs);
/* Start new IRQ agreement */
tmp = getreg8(IRQ_REG(IRQ_CTRL));
tmp |= 0x01;
putreg8(tmp, IRQ_REG(IRQ_CTRL));
current_regs = saved_regs;
}
/****************************************************************************
@ -291,23 +324,26 @@ void up_decodeirq(uint32_t *regs)
void calypso_fiq(void)
{
uint8_t num, tmp;
uint32_t *regs;
uint8_t num, tmp;
uint32_t *regs;
/* XXX: What is this???
* Passed to but ignored in IRQ handlers
* Only valid meaning is apparently non-NULL == IRQ context */
regs = (uint32_t *)current_regs;
current_regs = (uint32_t *)&num;
/* XXX: What is this???
* Passed to but ignored in IRQ handlers
* Only valid meaning is apparently non-NULL == IRQ context */
/* Detect & deliver like an IRQ but we are in FIQ context */
num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
irq_dispatch(num, regs);
regs = (uint32_t *)current_regs;
current_regs = (uint32_t *)&num;
/* Start new FIQ agreement */
tmp = getreg8(IRQ_REG(IRQ_CTRL));
tmp |= 0x02;
putreg8(tmp, IRQ_REG(IRQ_CTRL));
/* Detect & deliver like an IRQ but we are in FIQ context */
current_regs = regs;
num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
irq_dispatch(num, regs);
/* Start new FIQ agreement */
tmp = getreg8(IRQ_REG(IRQ_CTRL));
tmp |= 0x02;
putreg8(tmp, IRQ_REG(IRQ_CTRL));
current_regs = regs;
}

1
arch/arm/src/calypso/calypso_keypad.c
View file

@ -48,6 +48,7 @@
#include <arch/calypso/defines.h>
#include <arch/calypso/memory.h>
#include <arch/calypso/timer.h>
#include <arch/calypso/armio.h>
/****************************************************************************
* HW access

220
arch/arm/src/calypso/calypso_spi.c
View file

@ -40,6 +40,7 @@
#include <nuttx/config.h>
#include <nuttx/spi.h>
#include <unistd.h>
#include <debug.h>
#include "up_arch.h"
@ -55,11 +56,11 @@ extern int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din
struct calypso_spidev_s
{
struct spi_dev_s spidev; /* External driver interface */
int nbits; /* Number of transfered bits */
struct spi_dev_s spidev; /* External driver interface */
int nbits; /* Number of transfered bits */
#ifndef CONFIG_SPI_OWNBUS
sem_t exclsem; /* Mutual exclusion of devices */
sem_t exclsem; /* Mutual exclusion of devices */
#endif
};
@ -69,13 +70,13 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
#endif
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected)
bool selected)
{
}
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
{
return frequency;
return frequency;
}
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
@ -83,26 +84,29 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
}
/* Osmocom wrapper */
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{
((FAR struct calypso_spidev_s *)dev)->nbits = nbits;
((FAR struct calypso_spidev_s *)dev)->nbits = nbits;
}
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
FAR void *rxbuffer, size_t nwords)
{
FAR struct calypso_spidev_s *priv = (FAR struct calypso_spidev_s *)dev;
size_t i;
FAR struct calypso_spidev_s *priv = (FAR struct calypso_spidev_s *)dev;
size_t i;
for(i=0; i<nwords; i++)
spi_xfer(0, priv->nbits, txbuffer+i, rxbuffer+i);
for (i = 0; i < nwords; i++)
{
spi_xfer(0, priv->nbits, txbuffer+i, rxbuffer+i);
}
}
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
{
uint16_t buf = wd;
spi_exchange(dev, &buf, &buf, 1);
return buf;
uint16_t buf = wd;
spi_exchange(dev, &buf, &buf, 1);
return buf;
}
static const struct spi_ops_s g_spiops =
@ -130,103 +134,143 @@ static const struct spi_ops_s g_spiops =
static struct calypso_spidev_s g_spidev =
{
.spidev = { &g_spiops },
.nbits = 0,
.spidev = { &g_spiops },
.nbits = 0,
};
void spi_init(void)
{
putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
SPI_REG(REG_SET1));
putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
SPI_REG(REG_SET1));
putreg16(0x0001, SPI_REG(REG_SET2));
putreg16(0x0001, SPI_REG(REG_SET2));
}
int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
{
uint8_t bytes_per_xfer;
uint8_t reg_status, reg_ctrl = 0;
uint32_t tmp;
uint8_t bytes_per_xfer;
uint8_t reg_status, reg_ctrl = 0;
uint32_t tmp;
if (bitlen == 0)
return 0;
if (bitlen == 0)
{
return 0;
}
if (bitlen > 32)
return -1;
if (bitlen > 32)
{
return -1;
}
if (dev_idx > 4)
return -1;
if (dev_idx > 4)
{
return -1;
}
bytes_per_xfer = bitlen / 8;
if (bitlen % 8)
bytes_per_xfer ++;
bytes_per_xfer = bitlen / 8;
if (bitlen % 8)
{
bytes_per_xfer ++;
}
reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
if (bitlen <= 8) {
tmp = *(uint8_t *)dout;
tmp <<= 24 + (8-bitlen); /* align to MSB */
} else if (bitlen <= 16) {
tmp = *(uint16_t *)dout;
tmp <<= 16 + (16-bitlen); /* align to MSB */
} else {
tmp = *(uint32_t *)dout;
tmp <<= (32-bitlen); /* align to MSB */
}
dbg("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
dev_idx, bitlen, tmp);
if (bitlen <= 8)
{
tmp = *(uint8_t *)dout;
tmp <<= 24 + (8-bitlen); /* align to MSB */
}
else if (bitlen <= 16)
{
tmp = *(uint16_t *)dout;
tmp <<= 16 + (16-bitlen); /* align to MSB */
}
else
{
tmp = *(uint32_t *)dout;
tmp <<= (32-bitlen); /* align to MSB */
}
/* fill transmit registers */
putreg16(tmp >> 16, SPI_REG(REG_TX_MSB));
putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB));
dbg("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
dev_idx, bitlen, tmp);
/* initiate transfer */
if (din)
reg_ctrl |= SPI_CTRL_RDWR;
else
reg_ctrl |= SPI_CTRL_WR;
putreg16(reg_ctrl, SPI_REG(REG_CTRL));
dbg("reg_ctrl=0x%04x ", reg_ctrl);
/* fill transmit registers */
/* wait until the transfer is complete */
while (1) {
reg_status = getreg16(SPI_REG(REG_STATUS));
dbg("status=0x%04x ", reg_status);
if (din && (reg_status & SPI_STATUS_RE))
break;
else if (reg_status & SPI_STATUS_WE)
break;
}
/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
usleep(1000);
putreg16(tmp >> 16, SPI_REG(REG_TX_MSB));
putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB));
if (din) {
tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
tmp |= getreg16(SPI_REG(REG_RX_LSB));
dbg("data_in=0x%08x ", tmp);
/* initiate transfer */
if (bitlen <= 8)
*(uint8_t *)din = tmp & 0xff;
else if (bitlen <= 16)
*(uint16_t *)din = tmp & 0xffff;
else
*(uint32_t *)din = tmp;
}
dbg("\n");
if (din)
{
reg_ctrl |= SPI_CTRL_RDWR;
}
else
{
reg_ctrl |= SPI_CTRL_WR;
}
return 0;
putreg16(reg_ctrl, SPI_REG(REG_CTRL));
dbg("reg_ctrl=0x%04x ", reg_ctrl);
/* wait until the transfer is complete */
while (1)
{
reg_status = getreg16(SPI_REG(REG_STATUS));
dbg("status=0x%04x ", reg_status);
if (din && (reg_status & SPI_STATUS_RE))
{
break;
}
else if (reg_status & SPI_STATUS_WE)
{
break;
}
}
/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
usleep(1000);
if (din)
{
tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
tmp |= getreg16(SPI_REG(REG_RX_LSB));
dbg("data_in=0x%08x ", tmp);
if (bitlen <= 8)
{
*(uint8_t *)din = tmp & 0xff;
}
else if (bitlen <= 16)
{
*(uint16_t *)din = tmp & 0xffff;
}
else
{
*(uint32_t *)din = tmp;
}
}
dbg("\n");
return 0;
}
FAR struct spi_dev_s *up_spiinitialize(int port)
{
switch(port) {
case 0: /* SPI master device */
spi_init();
return (FAR struct spi_dev_s *)&g_spidev;
case 1: /* uWire device */
return NULL;
default:
return NULL;
}
switch (port)
{
case 0: /* SPI master device */
spi_init();
return (FAR struct spi_dev_s *)&g_spidev;
case 1: /* uWire device */
return NULL;
default:
return NULL;
}
}

11
configs/Kconfig
View file

@ -429,6 +429,13 @@ config ARCH_BOARD_PIC32_PIC32MX7MMB
This is the port NuttX to the Mikroelektronika PIC32MX7 Multimedia Board
(MMB). See http://www.mikroe.com/ for further information.
config ARCH_BOARD_PIRELLI_DPL10
bool "Pirelli DPL10 phone"
depends on ARCH_CHIP_CALYPSO
---help---
This directory contains the board support for Pirelli dpl10 phones. The
additions were made by Craig Comstock (with help form Alan Carvalho de Assis).
config ARCH_BOARD_PJRC_87C52
bool "PJRC 87C52 development system"
depends on ARCH_CHIP_8052
@ -742,6 +749,7 @@ config ARCH_BOARD
default "pcblogic-pic32mx" if ARCH_BOARD_PCBLOGICPIC32MX
default "pic32-starterkit" if ARCH_BOARD_PIC32_STARTERKIT
default "pic32mx7mmb" if ARCH_BOARD_PIC32_PIC32MX7MMB
default "pirelli_dpl10" if ARCH_BOARD_PIRELLI_DPL10
default "pjrc-8051" if ARCH_BOARD_PJRC_87C52
default "qemu-i486" if ARCH_BOARD_QEMU_I486
default "rgmp" if ARCH_BOARD_RGMP
@ -949,6 +957,9 @@ endif
if ARCH_BOARD_PIC32_PIC32MX7MMB
source "configs/pic32mx7mmb/Kconfig"
endif
if ARCH_BOARD_PIRELLI_DPL10
source "configs/pirelli_dpl10/Kconfig"
endif
if ARCH_BOARD_PJRC_87C52
source "configs/pjrc-8051/Kconfig"
endif

4
configs/README.txt
View file

@ -1938,8 +1938,8 @@ configs/pic32mx7mmb
configs/pirelli_dpl10
This directory contains the board support for pirelli dpl10 phones.
It is a variant of the compal_e88 config with the small change of enabling
the IrDA serial console.
It is a variant of the compal_e88 config with the small changes for the
differences in the board.
configs/pjrc-8051
8051 Microcontroller. This port uses the PJRC 87C52 development system

2
configs/pirelli_dpl10/README.txt
View file

@ -1,7 +1,7 @@
pirelli_dpl10
=============
This directory contains the board support for pirelli dpl10 phones.
This directory contains the board support for Pirelli dpl10 phones.
It is a variant of the compal_e88 configuration with the small change of
enabling the IrDA serial console:

6
configs/pirelli_dpl10/include/board.h Normal file
View file

@ -0,0 +1,6 @@
/************************************************************************
* configs/pirelli_dpl10/include/board.h
*
* Supposed to be empty
*
************************************************************************/

6
configs/pirelli_dpl10/include/power.h Normal file
View file

@ -0,0 +1,6 @@
/************************************************************************
* configs/pirelli_dpl10/include/power.h
*
* Supposed to be empty
*
************************************************************************/

2
configs/pirelli_dpl10/nsh_highram/Make.defs
View file

@ -123,5 +123,5 @@ MKDEP = $(TOPDIR)/tools/mkdeps.sh
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -wstrict-prototypes -Wshadow -g -pipe
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
HOSTLDFLAGS =

4
configs/pirelli_dpl10/nsh_highram/defconfig
View file

@ -40,8 +40,8 @@ CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP="calypso"
CONFIG_ARCH_CHIP_CALYPSO=y
CONFIG_ARCH_BOARD="compal_e88"
CONFIG_ARCH_BOARD_COMPALE88=y
CONFIG_ARCH_BOARD="pirelli_dpl10"
CONFIG_ARCH_BOARD_PIRELLI_DPL10=y
CONFIG_BOARD_LOOPSPERMSEC=1250
CONFIG_ROM_VECTORS=n
CONFIG_ARCH_LEDS=n

4
configs/pirelli_dpl10/src/.gitignore vendored Normal file
View file

@ -0,0 +1,4 @@
.depend
Make.dep

79
configs/pirelli_dpl10/src/Makefile Normal file
View file

@ -0,0 +1,79 @@
############################################################################
# configs/pirelli_dpl10/src/Makefile
#
# Copyright (C) 2007, 2008, 2013 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Copyright (C) 2011 Stefan Richter. All rights reserved.
# Author: Stefan Richter <ichgeh@l--putt.de>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = dummy.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
OBJS = $(AOBJS) $(COBJS)
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/arm
all: libboard$(LIBEXT)
$(AOBJS): %$(OBJEXT): %.S
$(call ASSEMBLE, $<, $@)
$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
libboard$(LIBEXT): $(OBJS)
$(call ARCHIVE, $@, $(OBJS))
.depend: Makefile $(SRCS)
$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) touch $@
depend: .depend
clean:
$(call DELFILE, libboard$(LIBEXT))
$(call CLEAN)
distclean: clean
$(call DELFILE, Make.dep)
$(call DELFILE, .depend)
-include Make.dep

1
configs/pirelli_dpl10/src/dummy.c Normal file
View file

@ -0,0 +1 @@
/* no libboard.a otherwise */