From ca5a9c711a7b9b70d84385a8523c54cf58a24e9e Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 10 Dec 2023 10:53:03 +0800 Subject: [PATCH] Remove @ and % tag from all comments and format the multiple line comments Signed-off-by: Xiang Xiao --- arch/arm/include/cxd56xx/gnss.h | 17 +- arch/arm/include/fvp-v8r-aarch32/chip.h | 2 +- arch/arm/src/armv7-m/etm.h | 4 +- arch/arm/src/armv8-m/etm.h | 4 +- arch/arm/src/cxd56xx/cxd56_scu.c | 39 +-- arch/arm/src/efm32/hardware/efm32_acmp.h | 4 +- arch/arm/src/efm32/hardware/efm32_adc.h | 4 +- arch/arm/src/efm32/hardware/efm32_aes.h | 4 +- arch/arm/src/efm32/hardware/efm32_burtc.h | 4 +- arch/arm/src/efm32/hardware/efm32_calibrate.h | 4 +- arch/arm/src/efm32/hardware/efm32_cmu.h | 4 +- arch/arm/src/efm32/hardware/efm32_dac.h | 4 +- arch/arm/src/efm32/hardware/efm32_devinfo.h | 4 +- arch/arm/src/efm32/hardware/efm32_dma.h | 4 +- arch/arm/src/efm32/hardware/efm32_emu.h | 4 +- arch/arm/src/efm32/hardware/efm32_gpio.h | 4 +- arch/arm/src/efm32/hardware/efm32_i2c.h | 4 +- arch/arm/src/efm32/hardware/efm32_lcd.h | 4 +- arch/arm/src/efm32/hardware/efm32_lesense.h | 4 +- arch/arm/src/efm32/hardware/efm32_letimer.h | 4 +- arch/arm/src/efm32/hardware/efm32_leuart.h | 4 +- arch/arm/src/efm32/hardware/efm32_msc.h | 4 +- arch/arm/src/efm32/hardware/efm32_pcnt.h | 4 +- arch/arm/src/efm32/hardware/efm32_prs.h | 4 +- arch/arm/src/efm32/hardware/efm32_rmu.h | 4 +- arch/arm/src/efm32/hardware/efm32_romtable.h | 4 +- arch/arm/src/efm32/hardware/efm32_rtc.h | 4 +- arch/arm/src/efm32/hardware/efm32_timer.h | 4 +- arch/arm/src/efm32/hardware/efm32_usb.h | 4 +- arch/arm/src/efm32/hardware/efm32_vcmp.h | 4 +- arch/arm/src/efm32/hardware/efm32_wdog.h | 4 +- .../src/efm32/hardware/efm32gg_memorymap.h | 4 +- .../src/efm32/hardware/efm32tg_memorymap.h | 4 +- arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h | 3 - arch/arm/src/nrf53/nrf53_serial.h | 2 +- arch/arm/src/nrf91/nrf91_serial.h | 2 +- arch/arm/src/phy62xx/error.h | 13 +- arch/arm/src/phy62xx/flash.h | 10 +- arch/arm/src/phy62xx/global_config.h | 8 +- arch/arm/src/phy62xx/gpio.h | 10 +- arch/arm/src/phy62xx/jump_function.h | 4 +- arch/arm/src/phy62xx/log.h | 10 +- arch/arm/src/phy62xx/uart.h | 10 +- arch/arm/src/rtl8720c/ameba_wdt.c | 3 +- arch/arm/src/sam34/sam4s_nand.c | 4 +- arch/arm/src/samd5e5/sam_usb.c | 4 +- arch/arm/src/samd5e5/sam_wdt.c | 7 +- arch/arm64/include/a64/chip.h | 2 +- arch/arm64/include/fvp-v8r/chip.h | 2 +- arch/arm64/include/goldfish/chip.h | 2 +- arch/arm64/include/imx8/chip.h | 2 +- arch/arm64/include/qemu/chip.h | 2 +- arch/arm64/include/rk3399/chip.h | 2 +- arch/arm64/src/common/arm64_fatal.h | 6 +- arch/arm64/src/common/arm64_mpu.c | 8 +- arch/risc-v/src/common/riscv_cpuidlestack.c | 3 +- arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c | 3 +- arch/risc-v/src/esp32c3/esp32c3_partition.c | 16 +- arch/risc-v/src/esp32c3/esp32c3_rsa.h | 4 +- arch/risc-v/src/esp32c3/esp32c3_rt_timer.c | 3 +- arch/risc-v/src/esp32c3/esp32c3_rt_timer.h | 12 +- arch/risc-v/src/esp32c3/esp32c3_wdt.h | 5 +- .../src/esp32c3/hardware/esp32c3_syscon.h | 6 +- .../src/esp32c3/hardware/regi2c_saradc.h | 3 +- .../risc-v/src/esp32c3/rom/esp32c3_spiflash.h | 9 +- arch/risc-v/src/hpm6750/hpm6750_clockconfig.h | 8 +- arch/sparc/include/sparc_v8/irq.h | 24 +- arch/xtensa/src/esp32/esp32_ble_adapter.c | 3 +- arch/xtensa/src/esp32/esp32_emac.c | 12 +- arch/xtensa/src/esp32/esp32_partition.c | 22 +- arch/xtensa/src/esp32/esp32_rt_timer.c | 3 +- arch/xtensa/src/esp32/esp32_rt_timer.h | 12 +- arch/xtensa/src/esp32/esp32_serial.c | 3 +- arch/xtensa/src/esp32/esp32_wlan.c | 3 +- arch/xtensa/src/esp32/hardware/esp32_pinmap.h | 3 +- arch/xtensa/src/esp32/rom/esp32_libc_stubs.h | 3 +- arch/xtensa/src/esp32s2/esp32s2_rt_timer.c | 3 +- arch/xtensa/src/esp32s2/esp32s2_rt_timer.h | 12 +- arch/xtensa/src/esp32s2/esp32s2_spiram.c | 7 +- arch/xtensa/src/esp32s2/esp32s2_spiram.h | 84 ++--- arch/xtensa/src/esp32s2/esp32s2_wdt.h | 5 +- .../src/esp32s2/hardware/esp32s2_i2cbbpll.h | 3 +- .../src/esp32s2/hardware/esp32s2_pinmap.h | 3 +- .../src/esp32s2/hardware/regi2c_bbpll.h | 5 +- .../src/esp32s2/rom/esp32s2_libc_stubs.h | 3 +- .../src/esp32s2/rom/esp32s2_opi_flash.h | 202 ++++++------ .../xtensa/src/esp32s2/rom/esp32s2_spiflash.h | 5 +- arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 3 +- arch/xtensa/src/esp32s3/esp32s3_lcd.c | 6 +- arch/xtensa/src/esp32s3/esp32s3_otg_device.c | 3 +- arch/xtensa/src/esp32s3/esp32s3_partition.c | 16 +- .../src/esp32s3/esp32s3_reset_reasons.h | 5 +- arch/xtensa/src/esp32s3/esp32s3_rt_timer.h | 12 +- arch/xtensa/src/esp32s3/esp32s3_spi_timing.c | 3 +- arch/xtensa/src/esp32s3/esp32s3_spiram.c | 17 +- arch/xtensa/src/esp32s3/esp32s3_spiram.h | 90 +++--- arch/xtensa/src/esp32s3/esp32s3_wdt.h | 5 +- .../src/esp32s3/hardware/esp32s3_pinmap.h | 3 +- .../src/esp32s3/hardware/regi2c_bbpll.h | 5 +- .../src/esp32s3/rom/esp32s3_libc_stubs.h | 3 +- .../src/esp32s3/rom/esp32s3_opi_flash.h | 178 +++++------ .../xtensa/src/esp32s3/rom/esp32s3_spiflash.h | 13 +- .../sam4s-xplained-pro/src/sam_nandflash.c | 7 +- .../stm32/nucleo-l152re/src/stm32_ili93418b.c | 3 +- .../include/nsh_romfsimg.h | 3 +- .../esp32s2/common/scripts/esp32s2_rom.ld | 3 +- .../esp32s3/common/scripts/esp32s3_rom_api.ld | 5 +- .../esp32s3/esp32s3-box/src/esp32s3-box.h | 6 +- drivers/misc/optee_msg.h | 136 ++++---- drivers/net/lan9250.c | 81 ++--- drivers/power/battery/axp202.c | 3 +- .../wireless/ieee80211/bcm43xxx/bcmf_ioctl.h | 8 +- .../wireless/spirit/include/spirit_radio.h | 4 +- include/netinet/if_ether.h | 3 +- include/netpacket/netlink.h | 13 +- include/nuttx/bits.h | 4 +- include/nuttx/ethtool.h | 65 ++-- include/nuttx/mmcsd.h | 4 +- include/nuttx/reset/reset.h | 16 +- include/nuttx/sensors/mpu9250.h | 6 +- include/nuttx/tee.h | 203 +++++------- include/nuttx/wireless/bluetooth/bt_uuid.h | 112 +++---- include/nuttx/wireless/ieee80211/ieee80211.h | 301 +++++++++--------- include/nuttx/wireless/lte/lte.h | 6 +- include/nuttx/wireless/wireless.h | 4 +- include/sys/videoio.h | 34 +- net/netlink/netlink.h | 106 +++--- 127 files changed, 986 insertions(+), 1298 deletions(-) diff --git a/arch/arm/include/cxd56xx/gnss.h b/arch/arm/include/cxd56xx/gnss.h index b9bb81ddb0..ab30ee009e 100644 --- a/arch/arm/include/cxd56xx/gnss.h +++ b/arch/arm/include/cxd56xx/gnss.h @@ -538,17 +538,15 @@ extern "C" #define CXD56_GNSS_IOCTL_SET_1PPS_OUTPUT 52 -/** - * Get the current 1PPS output setting +/* Get the current 1PPS output setting * - * @param[out] arg + * param[out] arg * enable(1) or disable(0) */ #define CXD56_GNSS_IOCTL_GET_1PPS_OUTPUT 53 -/** - * Get the firmware version +/* Get the firmware version * * param[in] arg * string array of CXD56_GNSS_VERSION_MAXLEN @@ -556,8 +554,7 @@ extern "C" #define CXD56_GNSS_IOCTL_GET_VERSION 54 -/** - * Sleep the firmware +/* Sleep the firmware * * param[in] arg * CXD56_GNSS_SLEEP(0) or CXD56_GNSS_DEEPSLEEP(1) @@ -565,8 +562,7 @@ extern "C" #define CXD56_GNSS_IOCTL_SLEEP 55 -/** - * Wake up the firmware +/* Wake up the firmware * * param arg * Parameter is Unnecessary. Set Zero. @@ -574,8 +570,7 @@ extern "C" #define CXD56_GNSS_IOCTL_WAKEUP 56 -/** - * Reset the firmware +/* Reset the firmware * * param arg * Parameter is Unnecessary. Set Zero. diff --git a/arch/arm/include/fvp-v8r-aarch32/chip.h b/arch/arm/include/fvp-v8r-aarch32/chip.h index 937063d400..71f2dc3c3b 100644 --- a/arch/arm/include/fvp-v8r-aarch32/chip.h +++ b/arch/arm/include/fvp-v8r-aarch32/chip.h @@ -27,7 +27,7 @@ #include -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm/src/armv7-m/etm.h b/arch/arm/src/armv7-m/etm.h index b379c1d525..1c200b39ee 100644 --- a/arch/arm/src/armv7-m/etm.h +++ b/arch/arm/src/armv7-m/etm.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/armv8-m/etm.h b/arch/arm/src/armv8-m/etm.h index f5ccfa7fe4..c99afe2a4d 100644 --- a/arch/arm/src/armv8-m/etm.h +++ b/arch/arm/src/armv8-m/etm.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/cxd56xx/cxd56_scu.c b/arch/arm/src/cxd56xx/cxd56_scu.c index 0403e19922..ceec239282 100644 --- a/arch/arm/src/cxd56xx/cxd56_scu.c +++ b/arch/arm/src/cxd56xx/cxd56_scu.c @@ -1693,8 +1693,7 @@ static int seq_scuirqhandler(int irq, void *context, void *arg) } } - /** - * Detect all FIFO underrun errors + /* Detect all FIFO underrun errors * This error may not happened because check reading bytes at seq_read(). * Thus, it is a program error when ERR1 detected. */ @@ -1888,8 +1887,7 @@ static int seq_fifoinit(struct seq_s *seq, int fifoid, uint16_t fsize) return -ENOMEM; } - /** - * FIFO IDs (* is unavailable) + /* FIFO IDs (* is unavailable) * D = Decimation FIFO * N = Normal FIFO * @@ -3165,8 +3163,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Enable/disable sign conversion feature + /* Enable/disable sign conversion feature * Arg: unsigned long, 0 = off, other = on */ @@ -3176,8 +3173,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Enable offset/gain adjustment preprocessing. + /* Enable offset/gain adjustment preprocessing. * Arg: Pointer of adjust_xyz_t * If arg is null, just enable offset/gain (use current setting value). */ @@ -3201,8 +3197,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Disable offset/gain adjustment preprocessing. + /* Disable offset/gain adjustment preprocessing. * Arg: None */ @@ -3212,8 +3207,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Set IIR filter position and coefficiencies. + /* Set IIR filter position and coefficiencies. * Arg: Pointer of struct math_filter_s */ @@ -3239,8 +3233,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Set event notifier + /* Set event notifier * Arg: Pointer of struct scuev_notify_s */ @@ -3266,8 +3259,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Set number of elements per sample for mathfunc + /* Set number of elements per sample for mathfunc * Arg: uint8_t */ @@ -3277,8 +3269,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Set decimation parameters + /* Set decimation parameters * Arg: Pointer of struct decimation_s */ @@ -3295,8 +3286,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) break; } - /** - * Now only save decimation parameters because decimation parameter + /* Now only save decimation parameters because decimation parameter * cannot be set while sequencer running. */ @@ -3306,8 +3296,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg) } break; - /** - * Set FIFO watermark + /* Set FIFO watermark * Arg: Pointer of struct scufifo_wm_s */ @@ -3418,15 +3407,13 @@ void scu_initialize(void) scufifo_initialize(); - /** - * If SCU clock has been already enabled, keep SCU running without loading + /* If SCU clock has been already enabled, keep SCU running without loading * and reset of SCU firmware. */ if (false == cxd56_scuseq_clock_is_enabled()) { - /** - * Enable SCU clock. This process must do before loading firmware + /* Enable SCU clock. This process must do before loading firmware * because SCU instruction RAM is not accessible. */ diff --git a/arch/arm/src/efm32/hardware/efm32_acmp.h b/arch/arm/src/efm32/hardware/efm32_acmp.h index 53be0e250a..e61d98738b 100644 --- a/arch/arm/src/efm32/hardware/efm32_acmp.h +++ b/arch/arm/src/efm32/hardware/efm32_acmp.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_adc.h b/arch/arm/src/efm32/hardware/efm32_adc.h index b42482f433..01673c325d 100644 --- a/arch/arm/src/efm32/hardware/efm32_adc.h +++ b/arch/arm/src/efm32/hardware/efm32_adc.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_aes.h b/arch/arm/src/efm32/hardware/efm32_aes.h index c99b5ea5f4..31db63c014 100644 --- a/arch/arm/src/efm32/hardware/efm32_aes.h +++ b/arch/arm/src/efm32/hardware/efm32_aes.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_burtc.h b/arch/arm/src/efm32/hardware/efm32_burtc.h index 5c9dc21036..6c0a486bf8 100644 --- a/arch/arm/src/efm32/hardware/efm32_burtc.h +++ b/arch/arm/src/efm32/hardware/efm32_burtc.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_calibrate.h b/arch/arm/src/efm32/hardware/efm32_calibrate.h index bf184a5244..82d11f81f8 100644 --- a/arch/arm/src/efm32/hardware/efm32_calibrate.h +++ b/arch/arm/src/efm32/hardware/efm32_calibrate.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_cmu.h b/arch/arm/src/efm32/hardware/efm32_cmu.h index dd2208f2db..2d163863c1 100644 --- a/arch/arm/src/efm32/hardware/efm32_cmu.h +++ b/arch/arm/src/efm32/hardware/efm32_cmu.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_dac.h b/arch/arm/src/efm32/hardware/efm32_dac.h index de84065fb7..82c5b670ba 100644 --- a/arch/arm/src/efm32/hardware/efm32_dac.h +++ b/arch/arm/src/efm32/hardware/efm32_dac.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_devinfo.h b/arch/arm/src/efm32/hardware/efm32_devinfo.h index e75532eb2b..5246009862 100644 --- a/arch/arm/src/efm32/hardware/efm32_devinfo.h +++ b/arch/arm/src/efm32/hardware/efm32_devinfo.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_dma.h b/arch/arm/src/efm32/hardware/efm32_dma.h index 2a3033550a..528f66f6d7 100644 --- a/arch/arm/src/efm32/hardware/efm32_dma.h +++ b/arch/arm/src/efm32/hardware/efm32_dma.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_emu.h b/arch/arm/src/efm32/hardware/efm32_emu.h index 3cfe957161..6b0a85768f 100644 --- a/arch/arm/src/efm32/hardware/efm32_emu.h +++ b/arch/arm/src/efm32/hardware/efm32_emu.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_gpio.h b/arch/arm/src/efm32/hardware/efm32_gpio.h index 5599de2bcd..c6bca5634a 100644 --- a/arch/arm/src/efm32/hardware/efm32_gpio.h +++ b/arch/arm/src/efm32/hardware/efm32_gpio.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_i2c.h b/arch/arm/src/efm32/hardware/efm32_i2c.h index 3ba4dac90d..b853c53092 100644 --- a/arch/arm/src/efm32/hardware/efm32_i2c.h +++ b/arch/arm/src/efm32/hardware/efm32_i2c.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_lcd.h b/arch/arm/src/efm32/hardware/efm32_lcd.h index 99bfd55661..5a6fadd302 100644 --- a/arch/arm/src/efm32/hardware/efm32_lcd.h +++ b/arch/arm/src/efm32/hardware/efm32_lcd.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_lesense.h b/arch/arm/src/efm32/hardware/efm32_lesense.h index 48fea94315..2eab4b454c 100644 --- a/arch/arm/src/efm32/hardware/efm32_lesense.h +++ b/arch/arm/src/efm32/hardware/efm32_lesense.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_letimer.h b/arch/arm/src/efm32/hardware/efm32_letimer.h index 4eb9d0b124..5fa36f2558 100644 --- a/arch/arm/src/efm32/hardware/efm32_letimer.h +++ b/arch/arm/src/efm32/hardware/efm32_letimer.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_leuart.h b/arch/arm/src/efm32/hardware/efm32_leuart.h index 03f78b8da3..26707c54de 100644 --- a/arch/arm/src/efm32/hardware/efm32_leuart.h +++ b/arch/arm/src/efm32/hardware/efm32_leuart.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_msc.h b/arch/arm/src/efm32/hardware/efm32_msc.h index 5df0bb84c1..06c933e633 100644 --- a/arch/arm/src/efm32/hardware/efm32_msc.h +++ b/arch/arm/src/efm32/hardware/efm32_msc.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_pcnt.h b/arch/arm/src/efm32/hardware/efm32_pcnt.h index 0a5c56fd0a..d23c8f8175 100644 --- a/arch/arm/src/efm32/hardware/efm32_pcnt.h +++ b/arch/arm/src/efm32/hardware/efm32_pcnt.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_prs.h b/arch/arm/src/efm32/hardware/efm32_prs.h index 79535fe464..d8bfa30b06 100644 --- a/arch/arm/src/efm32/hardware/efm32_prs.h +++ b/arch/arm/src/efm32/hardware/efm32_prs.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_rmu.h b/arch/arm/src/efm32/hardware/efm32_rmu.h index 65c295ff66..5035a72839 100644 --- a/arch/arm/src/efm32/hardware/efm32_rmu.h +++ b/arch/arm/src/efm32/hardware/efm32_rmu.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_romtable.h b/arch/arm/src/efm32/hardware/efm32_romtable.h index fb5a5a645c..4dab199d6b 100644 --- a/arch/arm/src/efm32/hardware/efm32_romtable.h +++ b/arch/arm/src/efm32/hardware/efm32_romtable.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_rtc.h b/arch/arm/src/efm32/hardware/efm32_rtc.h index 7855c2948b..eebd4ce6e3 100644 --- a/arch/arm/src/efm32/hardware/efm32_rtc.h +++ b/arch/arm/src/efm32/hardware/efm32_rtc.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_timer.h b/arch/arm/src/efm32/hardware/efm32_timer.h index e2df318117..7d43d054d3 100644 --- a/arch/arm/src/efm32/hardware/efm32_timer.h +++ b/arch/arm/src/efm32/hardware/efm32_timer.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_usb.h b/arch/arm/src/efm32/hardware/efm32_usb.h index 3ffa970ec5..300be5fa51 100644 --- a/arch/arm/src/efm32/hardware/efm32_usb.h +++ b/arch/arm/src/efm32/hardware/efm32_usb.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_vcmp.h b/arch/arm/src/efm32/hardware/efm32_vcmp.h index 5a2a97e9b3..062aa9702d 100644 --- a/arch/arm/src/efm32/hardware/efm32_vcmp.h +++ b/arch/arm/src/efm32/hardware/efm32_vcmp.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32_wdog.h b/arch/arm/src/efm32/hardware/efm32_wdog.h index eb6d379292..7081f9f554 100644 --- a/arch/arm/src/efm32/hardware/efm32_wdog.h +++ b/arch/arm/src/efm32/hardware/efm32_wdog.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h index 33931c6101..f4cc255df4 100644 --- a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/efm32/hardware/efm32tg_memorymap.h b/arch/arm/src/efm32/hardware/efm32tg_memorymap.h index 6b18065d6f..842ca68cb0 100644 --- a/arch/arm/src/efm32/hardware/efm32tg_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32tg_memorymap.h @@ -8,9 +8,9 @@ * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n + * claim that you wrote the original software. * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n + * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. diff --git a/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h b/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h index 99dd1952e4..58ad680585 100644 --- a/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h +++ b/arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h @@ -1,11 +1,9 @@ /**************************************************************************** * arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h * - * @note * Copyright(C) NXP Semiconductors, 2014 * All rights reserved. * - * @par * Software that is described herein is for illustrative purposes only * which provides customers with programming information regarding the * LPC products. This software is supplied "AS IS" without any warranties @@ -21,7 +19,6 @@ * application will be suitable for the specified use without further testing * or modification. * - * @par * Permission to use, copy, modify, and distribute this software and its * documentation is hereby granted, under NXP Semiconductors' and its * licensor's relevant copyrights in the software, without fee, provided that diff --git a/arch/arm/src/nrf53/nrf53_serial.h b/arch/arm/src/nrf53/nrf53_serial.h index 2b1d8edafc..17ff099b38 100644 --- a/arch/arm/src/nrf53/nrf53_serial.h +++ b/arch/arm/src/nrf53/nrf53_serial.h @@ -49,4 +49,4 @@ void nrf53_earlyserialinit(void); #endif -#endif /* __ARCH_ARM_SRC_NRF53_NRF53@_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_SERIAL_H */ diff --git a/arch/arm/src/nrf91/nrf91_serial.h b/arch/arm/src/nrf91/nrf91_serial.h index d439e12741..515d4a591a 100644 --- a/arch/arm/src/nrf91/nrf91_serial.h +++ b/arch/arm/src/nrf91/nrf91_serial.h @@ -49,4 +49,4 @@ void nrf91_earlyserialinit(void); #endif -#endif /* __ARCH_ARM_SRC_NRF91_NRF91@_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_NRF91_NRF91_SERIAL_H */ diff --git a/arch/arm/src/phy62xx/error.h b/arch/arm/src/phy62xx/error.h index 3c987b6c8e..3525e1fbf6 100644 --- a/arch/arm/src/phy62xx/error.h +++ b/arch/arm/src/phy62xx/error.h @@ -19,14 +19,11 @@ ****************************************************************************/ /**************************************************************************** - * @file error.h - * @brief Global error definition - * @version 0.0 - * @date 11. Feb. 2018 - * @author Eagle.Lao - * - * - * + * error.h + * Global error definition + * 0.0 + * 11. Feb. 2018 + * Eagle.Lao ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/phy62xx/flash.h b/arch/arm/src/phy62xx/flash.h index cf5d71f6e0..af32c0dd85 100644 --- a/arch/arm/src/phy62xx/flash.h +++ b/arch/arm/src/phy62xx/flash.h @@ -19,11 +19,11 @@ ****************************************************************************/ /**************************************************************************** - * @file flash.h - * @brief Contains all functions support for flash driver - * @version 0.0 - * @date 27. Nov. 2017 - * @author qing.han + * flash.h + * Contains all functions support for flash driver + * 0.0 + * 27. Nov. 2017 + * qing.han ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/phy62xx/global_config.h b/arch/arm/src/phy62xx/global_config.h index d12c637b30..4304cb717f 100644 --- a/arch/arm/src/phy62xx/global_config.h +++ b/arch/arm/src/phy62xx/global_config.h @@ -19,12 +19,10 @@ ****************************************************************************/ /**************************************************************************** - * @file global_config.h + * global_config.h * - * @brief This file contains the definitions of index of - - * global configuration which - * will be configured in APP project. + * This file contains the definitions of index of + * global configuration which will be configured in APP project. * * $Rev: $ * diff --git a/arch/arm/src/phy62xx/gpio.h b/arch/arm/src/phy62xx/gpio.h index 4ae50c01a6..e5094f431e 100644 --- a/arch/arm/src/phy62xx/gpio.h +++ b/arch/arm/src/phy62xx/gpio.h @@ -19,11 +19,11 @@ ****************************************************************************/ /**************************************************************************** - * @file gpio.h - * @brief Contains all functions support for gpio and iomux driver - * @version 0.0 - * @date 19. Oct. 2017 - * @author qing.han + * gpio.h + * Contains all functions support for gpio and iomux driver + * 0.0 + * 19. Oct. 2017 + * qing.han ****************************************************************************/ #ifndef __ARCH_ARM_SRC_PHY62XX_GPIO_H diff --git a/arch/arm/src/phy62xx/jump_function.h b/arch/arm/src/phy62xx/jump_function.h index 7f8239a066..7e9b1f35c7 100644 --- a/arch/arm/src/phy62xx/jump_function.h +++ b/arch/arm/src/phy62xx/jump_function.h @@ -20,9 +20,9 @@ /**************************************************************************** * - * @file jump_fucntion.h + * jump_fucntion.h * - * @brief This file contains the definitions of the macros and functions + * This file contains the definitions of the macros and functions * that are architecture dependent. The implementation of those is * implemented in the appropriate architecture directory. * diff --git a/arch/arm/src/phy62xx/log.h b/arch/arm/src/phy62xx/log.h index 008b21656c..8735608380 100644 --- a/arch/arm/src/phy62xx/log.h +++ b/arch/arm/src/phy62xx/log.h @@ -19,11 +19,11 @@ ****************************************************************************/ /**************************************************************************** - * @file log.h - * @brief Contains all functions support for uart driver - * @version 0.0 - * @date 31. Jan. 2018 - * @author eagle.han + * log.h + * Contains all functions support for uart driver + * 0.0 + * 31. Jan. 2018 + * eagle.han ****************************************************************************/ #ifndef ENABLE_LOG_ROM diff --git a/arch/arm/src/phy62xx/uart.h b/arch/arm/src/phy62xx/uart.h index 4cc1823a3d..ad9860f495 100644 --- a/arch/arm/src/phy62xx/uart.h +++ b/arch/arm/src/phy62xx/uart.h @@ -23,11 +23,11 @@ ****************************************************************************/ /**************************************************************************** - * @file uart.h - * @brief Contains all functions support for uart driver - * @version 0.0 - * @date 19. Oct. 2017 - * @author qing.han + * uart.h + * Contains all functions support for uart driver + * 0.0 + * 19. Oct. 2017 + * qing.han ****************************************************************************/ #ifndef __ARCH_ARM_SRC_PHY62XX_UART_H diff --git a/arch/arm/src/rtl8720c/ameba_wdt.c b/arch/arm/src/rtl8720c/ameba_wdt.c index ce7f3c58bc..b3c20bc564 100644 --- a/arch/arm/src/rtl8720c/ameba_wdt.c +++ b/arch/arm/src/rtl8720c/ameba_wdt.c @@ -38,8 +38,7 @@ * Private Types ****************************************************************************/ -/** - * This structure provides the private representation of the "lower-half" +/* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. */ diff --git a/arch/arm/src/sam34/sam4s_nand.c b/arch/arm/src/sam34/sam4s_nand.c index cd0bf743ce..a331029fb6 100644 --- a/arch/arm/src/sam34/sam4s_nand.c +++ b/arch/arm/src/sam34/sam4s_nand.c @@ -542,9 +542,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs) priv->cs = cs; priv->rb = GPIO_SMC_RB; - /* Initialize the NAND hardware for this CS */ - - /** + /* Initialize the NAND hardware for this CS * Note: The initialization is shown for the reference purpose only, and * for other MCUs, refer to the Package and Pinout chapter of the * respective data sheet. diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c index 628def461f..e1b25ce129 100644 --- a/arch/arm/src/samd5e5/sam_usb.c +++ b/arch/arm/src/samd5e5/sam_usb.c @@ -392,9 +392,7 @@ enum sam_hoststate_e USB_HOSTSTATE_CONFIGURED /* A valid configuration has been selected. */ }; -/** - * @brief USB HCD pipe states - */ +/* USB HCD pipe states */ enum usb_h_pipe_state { diff --git a/arch/arm/src/samd5e5/sam_wdt.c b/arch/arm/src/samd5e5/sam_wdt.c index a109b18bbf..13de218918 100644 --- a/arch/arm/src/samd5e5/sam_wdt.c +++ b/arch/arm/src/samd5e5/sam_wdt.c @@ -69,9 +69,7 @@ #define WDT_CLK_8192CYCLE 8192 #define WDT_CLK_16384CYCLE 16384 -/** - * \brief Macro is used to indicate the rate of second/millisecond - */ +/* Macro is used to indicate the rate of second/millisecond */ #define WDT_PERIOD_RATE 1000 @@ -79,8 +77,7 @@ * Private Types ****************************************************************************/ -/** - * This structure provides the private representation of the "lower-half" +/* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. */ diff --git a/arch/arm64/include/a64/chip.h b/arch/arm64/include/a64/chip.h index 85e0d5607e..f48a2c60df 100644 --- a/arch/arm64/include/a64/chip.h +++ b/arch/arm64/include/a64/chip.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm64/include/fvp-v8r/chip.h b/arch/arm64/include/fvp-v8r/chip.h index b37126473e..eb723d84ad 100644 --- a/arch/arm64/include/fvp-v8r/chip.h +++ b/arch/arm64/include/fvp-v8r/chip.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm64/include/goldfish/chip.h b/arch/arm64/include/goldfish/chip.h index 173b5194c5..57d0a0178c 100644 --- a/arch/arm64/include/goldfish/chip.h +++ b/arch/arm64/include/goldfish/chip.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm64/include/imx8/chip.h b/arch/arm64/include/imx8/chip.h index e38678f312..e919e6ab40 100644 --- a/arch/arm64/include/imx8/chip.h +++ b/arch/arm64/include/imx8/chip.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm64/include/qemu/chip.h b/arch/arm64/include/qemu/chip.h index 0703552d24..d2f09d3d32 100644 --- a/arch/arm64/include/qemu/chip.h +++ b/arch/arm64/include/qemu/chip.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm64/include/rk3399/chip.h b/arch/arm64/include/rk3399/chip.h index 76ae29ce9a..f48e001a86 100644 --- a/arch/arm64/include/rk3399/chip.h +++ b/arch/arm64/include/rk3399/chip.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */ +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ #define KB(x) ((x) << 10) #define MB(x) (KB(x) << 10) diff --git a/arch/arm64/src/common/arm64_fatal.h b/arch/arm64/src/common/arm64_fatal.h index e1d88bc97d..e0bddadcdd 100644 --- a/arch/arm64/src/common/arm64_fatal.h +++ b/arch/arm64/src/common/arm64_fatal.h @@ -21,11 +21,7 @@ #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H #define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H -/** - * @defgroup fatal_apis Fatal error APIs - * @ingroup kernel_apis - * @{ - */ +/* Fatal error APIs */ #define K_ERR_CPU_EXCEPTION (0) #define K_ERR_CPU_MODE32 (1) diff --git a/arch/arm64/src/common/arm64_mpu.c b/arch/arm64/src/common/arm64_mpu.c index 7f28dec3db..dcba9c97f7 100644 --- a/arch/arm64/src/common/arm64_mpu.c +++ b/arch/arm64/src/common/arm64_mpu.c @@ -90,9 +90,7 @@ static inline uint8_t get_num_regions(void) /* ARM Core MPU Driver API Implementation for ARM MPU */ -/** - * @brief enable the MPU - */ +/* Enable the MPU */ void arm64_core_mpu_enable(void) { @@ -109,9 +107,7 @@ void arm64_core_mpu_enable(void) ARM64_ISB(); } -/** - * @brief disable the MPU - */ +/* Disable the MPU */ void arm64_core_mpu_disable(void) { diff --git a/arch/risc-v/src/common/riscv_cpuidlestack.c b/arch/risc-v/src/common/riscv_cpuidlestack.c index ad2d6dcf3d..88625488c8 100644 --- a/arch/risc-v/src/common/riscv_cpuidlestack.c +++ b/arch/risc-v/src/common/riscv_cpuidlestack.c @@ -45,8 +45,7 @@ * Private Data ****************************************************************************/ -/** - * Note: +/* Note: * 1. QEMU-RV supports up to 8 cores currently. * 2. RISC-V requires a 16-byte stack alignment. */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c b/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c index 79eddf60e9..7bff497a0b 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c +++ b/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c @@ -1107,8 +1107,7 @@ static int32_t esp_queue_send_generic(void *queue, void *item, if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) { - /** - * BLE interrupt function will call this adapter function to send + /* BLE interrupt function will call this adapter function to send * message to message queue, so here we should call kernel API * instead of application API */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_partition.c b/arch/risc-v/src/esp32c3/esp32c3_partition.c index 55b315ea2f..ad5e48c4fa 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_partition.c +++ b/arch/risc-v/src/esp32c3/esp32c3_partition.c @@ -81,17 +81,15 @@ enum ota_img_ctrl_e enum ota_img_state_e { - /** - * Monitor the first boot. In bootloader of esp-idf this state is changed - * to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback. + /* Monitor the first boot. In bootloader of esp-idf this state is changed + * to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback. * - * So this driver doesn't use this state currently. + * So this driver doesn't use this state currently. */ OTA_IMG_NEW = 0x0, - /** - * First boot for this app was. If while the second boot this state is then + /* First boot for this app was. If while the second boot this state is then * it will be changed to ABORTED if this bootloader enable app rollback. * * So this driver doesn't use this state currently. @@ -107,8 +105,7 @@ enum ota_img_state_e OTA_IMG_INVALID = 0x3, - /** - * App could not confirm the workable or non-workable. In bootloader + /* App could not confirm the workable or non-workable. In bootloader * IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will * not selected to boot at all if this bootloader enable app rollback. * @@ -117,8 +114,7 @@ enum ota_img_state_e OTA_IMG_ABORTED = 0x4, - /** - * Undefined. App can boot and work without limits in esp-idf. + /* Undefined. App can boot and work without limits in esp-idf. * * This state is not used. */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rsa.h b/arch/risc-v/src/esp32c3/esp32c3_rsa.h index 51a3295c70..9d99ca5c9c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rsa.h +++ b/arch/risc-v/src/esp32c3/esp32c3_rsa.h @@ -73,9 +73,7 @@ extern "C" * Public Types ****************************************************************************/ -/** - * \brief - The RSA context structure. - */ +/* The RSA context structure. */ struct esp32c3_rsa_context_s { diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c index 0ba11c67b7..5880922492 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c +++ b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c @@ -433,8 +433,7 @@ static int rt_timer_isr(int irq, void *context, void *arg) if (!list_is_empty(&priv->runlist)) { - /** - * When stop/delete timer, in the same time the hardware timer + /* When stop/delete timer, in the same time the hardware timer * interrupt triggers, function "stop/delete" remove the timer * from running list, so the 1st timer is not which triggers. */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h index ff3b1591d4..86cb10897e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h +++ b/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h @@ -42,9 +42,7 @@ * Public Types ****************************************************************************/ -/** - * RT timer state - */ +/* RT timer state */ enum rt_timer_state_e { @@ -54,9 +52,7 @@ enum rt_timer_state_e RT_TIMER_DELETE /* Timer is to be delete */ }; -/** - * RT timer data structure - */ +/* RT timer data structure */ struct rt_timer_s { @@ -69,9 +65,7 @@ struct rt_timer_s struct list_node list; /* Working list */ }; -/** - * RT timer creation arguments data structure - */ +/* RT timer creation arguments data structure */ struct rt_timer_args_s { diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.h b/arch/risc-v/src/esp32c3/esp32c3_wdt.h index 61e78ee739..82b09d5f85 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt.h +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt.h @@ -73,10 +73,9 @@ enum esp32c3_wdt_stage_e ESP32C3_WDT_STAGE3 = 3 /* Stage 3 */ }; -/** - * Behavior of the WDT stage if it times out. +/* Behavior of the WDT stage if it times out. * - * @note These enum values should be compatible with the + * Note: These enum values should be compatible with the * corresponding register field values. */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h index 568271cc33..c7cf6b24b7 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h @@ -216,8 +216,7 @@ #define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF #define SYSTEM_WIFI_CLK_EN_S 0 -/** - * Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 +/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 * Bit15 not included here because of the bit now can't be cleared */ @@ -233,8 +232,7 @@ #define SYSTEM_WIFI_CLK_BT_EN_V 0x0 #define SYSTEM_WIFI_CLK_BT_EN_S 0 -/** - * Mask for clock bits used by both WIFI and Bluetooth, +/* Mask for clock bits used by both WIFI and Bluetooth, * bit 0, 3, 6, 7, 8, 9 */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h b/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h index 943c822458..f4fe0881ab 100644 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h +++ b/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h @@ -25,8 +25,7 @@ * Pre-processor Definitions ****************************************************************************/ -/** - * Register definitions for analog to calibrate initial code for getting a +/* Register definitions for analog to calibrate initial code for getting a * more precise voltage of SAR ADC. */ diff --git a/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h b/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h index aa5a87f392..1c1c4fb9cb 100644 --- a/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h +++ b/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h @@ -143,9 +143,7 @@ typedef struct uint16_t data; } esp_rom_spiflash_common_cmd_t; -/** - * Global ROM spiflash data, as used by legacy SPI flash functions - */ +/* Global ROM spiflash data, as used by legacy SPI flash functions */ struct spiflash_legacy_data_s { @@ -154,8 +152,7 @@ struct spiflash_legacy_data_s uint8_t sig_matrix; }; -/** - * Structure holding SPI flash access critical sections management functions. +/* Structure holding SPI flash access critical sections management functions. * * Flash API uses two types of functions for flash access management: * 1) Functions which prepare/restore flash cache and interrupts before @@ -186,7 +183,7 @@ struct spiflash_legacy_data_s * use OS primitives or even does not need them (multithreaded access is * not possible). * - * @note Structure and corresponding guard functions should not reside + * Note: Structure and corresponding guard functions should not reside * in flash. For example structure can be placed in DRAM and functions * in IRAM sections. */ diff --git a/arch/risc-v/src/hpm6750/hpm6750_clockconfig.h b/arch/risc-v/src/hpm6750/hpm6750_clockconfig.h index 6bdd4c05c5..ce5bb612c8 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_clockconfig.h +++ b/arch/risc-v/src/hpm6750/hpm6750_clockconfig.h @@ -35,9 +35,7 @@ * Public Types ****************************************************************************/ -/** - * @brief Clock nodes - */ +/* Clock nodes */ typedef enum { @@ -120,9 +118,7 @@ typedef enum clock_node_end, } clock_node_t; -/** - * @brief General clock sources - */ +/* General clock sources */ typedef enum { diff --git a/arch/sparc/include/sparc_v8/irq.h b/arch/sparc/include/sparc_v8/irq.h index ce034e802d..fa5c77b362 100644 --- a/arch/sparc/include/sparc_v8/irq.h +++ b/arch/sparc/include/sparc_v8/irq.h @@ -476,7 +476,7 @@ struct xcptcontext ****************************************************************************/ /* Macro to set the PSR. - * This macro sets the PSR register to the value in @a _psr. + * This macro sets the PSR register to the value in _psr. */ #define sparc_set_psr( _psr ) \ do { \ @@ -487,7 +487,7 @@ struct xcptcontext } while ( 0 ) /* Macro to obtain the PSR. - * This macro returns the current contents of the PSR register in @a _psr. + * This macro returns the current contents of the PSR register in _psr. */ #define sparc_get_psr( _psr ) \ do { \ @@ -503,7 +503,7 @@ struct xcptcontext } while ( 0 ) /* Macro to obtain the TBR. - * This macro returns the current contents of the TBR register in @a _tbr. + * This macro returns the current contents of the TBR register in _tbr. */ #define sparc_get_tbr( _tbr ) \ do { \ @@ -512,7 +512,7 @@ struct xcptcontext } while ( 0 ) /* Macro to set the TBR. - * This macro sets the TBR register to the value in @a _tbr. + * This macro sets the TBR register to the value in _tbr. */ #define sparc_set_tbr( _tbr ) \ do { \ @@ -520,7 +520,7 @@ struct xcptcontext } while ( 0 ) /* Macro to obtain the WIM. - * This macro returns the current contents of the WIM field in @a _wim. + * This macro returns the current contents of the WIM field in _wim. */ #define sparc_get_wim( _wim ) \ do { \ @@ -528,7 +528,7 @@ struct xcptcontext } while ( 0 ) /* Macro to set the WIM. - * This macro sets the WIM field to the value in @a _wim. + * This macro sets the WIM field to the value in _wim. */ #define sparc_set_wim( _wim ) \ do { \ @@ -539,7 +539,7 @@ struct xcptcontext } while ( 0 ) /* Macro to obtain the Y register. - * This macro returns the current contents of the Y register in @a _y. + * This macro returns the current contents of the Y register in _y. */ #define sparc_get_y( _y ) \ do { \ @@ -547,7 +547,7 @@ struct xcptcontext } while ( 0 ) /* Macro to set the Y register. - * This macro sets the Y register to the value in @a _y. + * This macro sets the Y register to the value in _y. */ #define sparc_set_y( _y ) \ do { \ @@ -565,7 +565,7 @@ struct xcptcontext /* SPARC disable processor interrupts. * This method is invoked to disable all maskable interrupts. - * @return This method returns the entire PSR contents. + * This method returns the entire PSR contents. */ static inline uint32_t sparc_disable_interrupts(void) @@ -577,7 +577,7 @@ static inline uint32_t sparc_disable_interrupts(void) /* SPARC enable processor interrupts. * This method is invoked to enable all maskable interrupts. - * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts. + * psr is the PSR returned by sparc_disable_interrupts. */ static inline void sparc_enable_interrupts(uint32_t psr) @@ -595,7 +595,7 @@ static inline void sparc_enable_interrupts(uint32_t psr) /* SPARC flash processor interrupts. * This method is invoked to temporarily enable all maskable interrupts. - * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts. + * _psr is the PSR returned by sparc_disable_interrupts. */ #define sparc_flash_interrupts( _psr ) \ @@ -606,7 +606,7 @@ static inline void sparc_enable_interrupts(uint32_t psr) /* SPARC obtain interrupt level. * This method is invoked to obtain the current interrupt disable level. - * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts. + * _level is the PSR returned by sparc_disable_interrupts. */ #define sparc_get_interrupt_level( _level ) \ diff --git a/arch/xtensa/src/esp32/esp32_ble_adapter.c b/arch/xtensa/src/esp32/esp32_ble_adapter.c index 818411fb4a..6c414936e2 100644 --- a/arch/xtensa/src/esp32/esp32_ble_adapter.c +++ b/arch/xtensa/src/esp32/esp32_ble_adapter.c @@ -1565,8 +1565,7 @@ static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) { - /** - * BLE interrupt function will call this adapter function to send + /* BLE interrupt function will call this adapter function to send * message to message queue, so here we should call kernel API * instead of application API */ diff --git a/arch/xtensa/src/esp32/esp32_emac.c b/arch/xtensa/src/esp32/esp32_emac.c index b73ff70290..a0b9787e1c 100644 --- a/arch/xtensa/src/esp32/esp32_emac.c +++ b/arch/xtensa/src/esp32/esp32_emac.c @@ -606,8 +606,7 @@ static int emac_config(void) return -ETIMEDOUT; } - /** - * Enable transmission options: + /* Enable transmission options: * * - 100M * - Full duplex @@ -620,8 +619,7 @@ static int emac_config(void) emac_set_reg(EMAC_FFR_OFFSET, EMAC_PMF_E); - /** - * Enable flow control options: + /* Enable flow control options: * * - PT-28 Time slot * - RX flow control @@ -634,8 +632,7 @@ static int emac_config(void) (EMAC_PAUSE_TIME << EMAC_CFPT_S); emac_set_reg(EMAC_FCR_OFFSET, regval); - /** - * Enable DMA options: + /* Enable DMA options: * * - Drop error frame * - Send frame when filled into FiFO @@ -645,8 +642,7 @@ static int emac_config(void) regval = EMAC_FSF_E | EMAC_FTF_E | EMAC_OSF_E; emac_set_reg(EMAC_DMA_OMR_OFFSET, regval); - /** - * Enable DMA bus options: + /* Enable DMA bus options: * * - Mixed burst mode * - Address align beast diff --git a/arch/xtensa/src/esp32/esp32_partition.c b/arch/xtensa/src/esp32/esp32_partition.c index 592280a367..6426a3196f 100644 --- a/arch/xtensa/src/esp32/esp32_partition.c +++ b/arch/xtensa/src/esp32/esp32_partition.c @@ -102,17 +102,15 @@ enum ota_img_ctrl enum ota_img_state { - /** - * Monitor the first boot. In bootloader of esp-idf this state is changed - * to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback. + /* Monitor the first boot. In bootloader of esp-idf this state is changed + * to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback. * - * So this driver doesn't use this state currently. + * So this driver doesn't use this state currently. */ OTA_IMG_NEW = 0x0, - /** - * First boot for this app was. If while the second boot this state is then + /* First boot for this app was. If while the second boot this state is then * it will be changed to ABORTED if this bootloader enable app rollback. * * So this driver doesn't use this state currently. @@ -128,8 +126,7 @@ enum ota_img_state OTA_IMG_INVALID = 0x3, - /** - * App could not confirm the workable or non-workable. In bootloader + /* App could not confirm the workable or non-workable. In bootloader * IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will * not selected to boot at all if this bootloader enable app rollback. * @@ -138,8 +135,7 @@ enum ota_img_state OTA_IMG_ABORTED = 0x4, - /** - * Undefined. App can boot and work without limits in esp-idf. + /* Undefined. App can boot and work without limits in esp-idf. * * This state is not used. */ @@ -674,8 +670,7 @@ static int partition_create_dev(const struct partition_info_priv *info, snprintf(path, PARTITION_MOUNTPTR_LEN_MAX, "%s/%s", g_path_base, info->label); - /** - * If SPI Flash encryption is enable, "APP", "OTA data" and "NVS keys" are + /* If SPI Flash encryption is enable, "APP", "OTA data" and "NVS keys" are * force to set as encryption partition. */ @@ -877,8 +872,7 @@ int esp32_partition_init(void) return -ENOMEM; } - /** - * Even without SPI Flash encryption, we can also use encrypted + /* Even without SPI Flash encryption, we can also use encrypted * MTD to read no-encrypted data. */ diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.c b/arch/xtensa/src/esp32/esp32_rt_timer.c index 70fe5d3fc2..27c1771506 100644 --- a/arch/xtensa/src/esp32/esp32_rt_timer.c +++ b/arch/xtensa/src/esp32/esp32_rt_timer.c @@ -411,8 +411,7 @@ static int rt_timer_isr(int irq, void *context, void *arg) if (!list_is_empty(&priv->runlist)) { - /** - * When stop/delete timer, in the same time the hardware timer + /* When stop/delete timer, in the same time the hardware timer * interrupt triggers, function "stop/delete" remove the timer * from running list, so the 1st timer is not which triggers. */ diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.h b/arch/xtensa/src/esp32/esp32_rt_timer.h index 64c2eb3129..5ca5903d54 100644 --- a/arch/xtensa/src/esp32/esp32_rt_timer.h +++ b/arch/xtensa/src/esp32/esp32_rt_timer.h @@ -42,9 +42,7 @@ * Public Types ****************************************************************************/ -/** - * RT timer state - */ +/* RT timer state */ enum rt_timer_state_e { @@ -54,9 +52,7 @@ enum rt_timer_state_e RT_TIMER_DELETE /* Timer is to be delete */ }; -/** - * RT timer data structure - */ +/* RT timer data structure */ struct rt_timer_s { @@ -69,9 +65,7 @@ struct rt_timer_s struct list_node list; /* Working list */ }; -/** - * RT timer creation arguments data structure - */ +/* RT timer creation arguments data structure */ struct rt_timer_args_s { diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index dc2ee151cd..9841c02ac7 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -643,8 +643,7 @@ static void esp32_dmasend(struct uart_dev_s *dev) uint8_t *alloctp = NULL; #endif - /** - * If the buffer comes from PSRAM, allocate a new one from + /* If the buffer comes from PSRAM, allocate a new one from * Internal SRAM. */ diff --git a/arch/xtensa/src/esp32/esp32_wlan.c b/arch/xtensa/src/esp32/esp32_wlan.c index 9afe45f74f..e85aa35729 100644 --- a/arch/xtensa/src/esp32/esp32_wlan.c +++ b/arch/xtensa/src/esp32/esp32_wlan.c @@ -887,8 +887,7 @@ static void wlan_rxpoll(void *arg) } #ifdef WLAN_RX_THRESHOLD - /** - * If received total bytes is larger than receive threshold, + /* If received total bytes is larger than receive threshold, * then do "unlock" to try to active applicantion to receive * data from low-level buffer of IP stack. */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_pinmap.h b/arch/xtensa/src/esp32/hardware/esp32_pinmap.h index 38949636b8..627b84e079 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_pinmap.h +++ b/arch/xtensa/src/esp32/hardware/esp32_pinmap.h @@ -29,8 +29,7 @@ * Pre-processor Definitions ****************************************************************************/ -/** - * Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better +/* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better * speed performance. */ diff --git a/arch/xtensa/src/esp32/rom/esp32_libc_stubs.h b/arch/xtensa/src/esp32/rom/esp32_libc_stubs.h index e63e1004cf..5ad98d3e4d 100644 --- a/arch/xtensa/src/esp32/rom/esp32_libc_stubs.h +++ b/arch/xtensa/src/esp32/rom/esp32_libc_stubs.h @@ -44,8 +44,7 @@ struct _reent; -/** - * @brief ESP32 ROM code contains implementations of some of C +/* ESP32 ROM code contains implementations of some of C * library functions. * Whenever a function in ROM needs to use a syscall, it calls a * pointer to the corresponding syscall implementation defined in diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c index 6c9940afad..b0b3d7a189 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c @@ -444,8 +444,7 @@ static int rt_timer_isr(int irq, void *context, void *arg) if (!list_is_empty(&priv->runlist)) { - /** - * When stop/delete timer, in the same time the hardware timer + /* When stop/delete timer, in the same time the hardware timer * interrupt triggers, function "stop/delete" remove the timer * from running list, so the 1st timer is not which triggers. */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h index 74c6286bcc..62030d4e2d 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h +++ b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h @@ -42,9 +42,7 @@ * Public Types ****************************************************************************/ -/** - * RT timer state - */ +/* RT timer state */ enum rt_timer_state_e { @@ -54,9 +52,7 @@ enum rt_timer_state_e RT_TIMER_DELETE /* Timer is to be delete */ }; -/** - * RT timer data structure - */ +/* RT timer data structure */ struct rt_timer_s { @@ -69,9 +65,7 @@ struct rt_timer_s struct list_node list; /* Working list */ }; -/** - * RT timer creation arguments data structure - */ +/* RT timer creation arguments data structure */ struct rt_timer_args_s { diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.c b/arch/xtensa/src/esp32s2/esp32s2_spiram.c index f05846cd9d..5c5f5e86fb 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spiram.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.c @@ -360,11 +360,10 @@ void IRAM_ATTR esp_spiram_writeback_cache(void) cache_writeback_all(); } -/** - * @brief If SPI RAM(PSRAM) has been initialized +/* If SPI RAM(PSRAM) has been initialized * - * @return true SPI RAM has been initialized successfully - * @return false SPI RAM hasn't been initialized or initialized failed + * Return true SPI RAM has been initialized successfully + * Return false SPI RAM hasn't been initialized or initialized failed */ bool esp_spiram_is_initialized(void) diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.h b/arch/xtensa/src/esp32s2/esp32s2_spiram.h index fc0fcf7c83..fe9e077db1 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spiram.h +++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.h @@ -34,57 +34,51 @@ extern "C" { #endif -/* @brief Initialize spiram interface/hardware. Normally called from +/* Initialize spiram interface/hardware. Normally called from * cpu_start.c. * - * @return ESP_OK on success + * Return ESP_OK on success */ int esp_spiram_init(void); -/** - * @brief Configure Cache/MMU for access to external SPI RAM. +/* Configure Cache/MMU for access to external SPI RAM. * * Normally this function is called from cpu_start, if * CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to * enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and * call this function later. * - * @attention this function must be called with flash cache disabled. + * Attention: this function must be called with flash cache disabled. */ void esp_spiram_init_cache(void); -/** - * @brief Memory test for SPI RAM. Should be called after SPI RAM is +/* Memory test for SPI RAM. Should be called after SPI RAM is * initialized and (in case of a dual-core system) the app CPU is online. * This test overwrites the memory with crap, so do not call after e.g. the * heap allocator has stored important stuff in SPI RAM. * - * @return true on success, false on failed memory test + * Return true on success, false on failed memory test */ bool esp_spiram_test(void); -/** - * @brief Add the initialized SPI RAM to the heap allocator. - */ +/* Add the initialized SPI RAM to the heap allocator. */ int esp_spiram_add_to_heapalloc(void); -/** - * @brief Get the available physical size of the attached SPI RAM chip +/* Get the available physical size of the attached SPI RAM chip * - * @note If ECC is enabled, the available physical size would be smaller + * Note If ECC is enabled, the available physical size would be smaller * than the physical size. See `CONFIG_SPIRAM_ECC_ENABLE` * - * @return Size in bytes, or 0 if no external RAM chip support compiled in. + * Return size in bytes, or 0 if no external RAM chip support compiled in. */ size_t esp_spiram_get_size(void); -/** - * @brief Force a writeback of the data in the SPI RAM cache. This is to be +/* Force a writeback of the data in the SPI RAM cache. This is to be * called whenever cache is disabled, because disabling cache on the ESP32 * discards the data in the SPI RAM cache. * @@ -93,46 +87,42 @@ size_t esp_spiram_get_size(void); void esp_spiram_writeback_cache(void); -/** - * @brief If SPI RAM(PSRAM) has been initialized +/* If SPI RAM(PSRAM) has been initialized * - * @return + * Return * - true SPI RAM has been initialized successfully * - false SPI RAM hasn't been initialized or initialized failed */ bool esp_spiram_is_initialized(void); -/** - * @brief get psram CS IO +/* get psram CS IO * * This interface should be called after PSRAM is enabled, otherwise it will * return an invalid value -1/0xff. * - * @return psram CS IO or -1/0xff if psram not enabled + * Return psram CS IO or -1/0xff if psram not enabled */ uint8_t esp_spiram_get_cs_io(void); -/** - * @brief Reserve a pool of internal memory for specific DMA/internal +/* Reserve a pool of internal memory for specific DMA/internal * allocations * - * @param size Size of reserved pool in bytes + * size Size of reserved pool in bytes * - * @return + * Return * - ESP_OK on success * - ESP_ERR_NO_MEM when no memory available for pool */ int esp_spiram_reserve_dma_pool(size_t size); -/** - * @brief If SPI RAM(PSRAM) has been initialized +/* If SPI RAM(PSRAM) has been initialized * - * @return - * - true SPI RAM has been initialized successfully - * - false SPI RAM hasn't been initialized or initialized failed + * Return + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed */ bool esp_spiram_is_initialized(void); @@ -142,26 +132,23 @@ bool esp_spiram_is_initialized(void); extern int _instruction_reserved_start; extern int _instruction_reserved_end; -/** - * @brief Get the start page number of the instruction in SPI flash +/* Get the start page number of the instruction in SPI flash * - * @return start page number + * Return start page number */ uint32_t instruction_flash_start_page_get(void); -/** - * @brief Get the end page number of the instruction in SPI flash +/* Get the end page number of the instruction in SPI flash * - * @return end page number + * Return end page number */ uint32_t instruction_flash_end_page_get(void); -/** - * @brief Get the offset of instruction from SPI flash to SPI RAM +/* Get the offset of instruction from SPI flash to SPI RAM * - * @return instruction offset + * Return instruction offset */ int instruction_flash2spiram_offset(void); @@ -173,26 +160,23 @@ int instruction_flash2spiram_offset(void); extern uint8_t _rodata_reserved_start[]; extern uint8_t _rodata_reserved_end[]; -/** - * @brief Get the start page number of the rodata in SPI flash +/* Get the start page number of the rodata in SPI flash * - * @return start page number + * Return start page number */ uint32_t rodata_flash_start_page_get(void); -/** - * @brief Get the end page number of the rodata in SPI flash +/* Get the end page number of the rodata in SPI flash * - * @return end page number + * Return end page number */ uint32_t rodata_flash_end_page_get(void); -/** - * @brief Get the offset number of rodata from SPI flash to SPI RAM +/* Get the offset number of rodata from SPI flash to SPI RAM * - * @return rodata offset + * Return rodata offset */ int rodata_flash2spiram_offset(void); diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt.h b/arch/xtensa/src/esp32s2/esp32s2_wdt.h index 08b48e7fda..385e8460ec 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt.h +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt.h @@ -74,10 +74,9 @@ enum esp32s2_wdt_stage_e ESP32S2_WDT_STAGE3 = 3 /* Stage 3 */ }; -/** - * Behavior of the WDT stage if it times out. +/* Behavior of the WDT stage if it times out. * - * @note These enum values should be compatible with the + * Note: These enum values should be compatible with the * corresponding register field values. */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h index 25c87e9a12..c71cf04b47 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h @@ -21,8 +21,7 @@ #ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H #define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H -/** - * Register definitions for digital PLL (BBPLL) +/* Register definitions for digital PLL (BBPLL) * * This file lists register fields of BBPLL, located on an internal * configuration bus. These definitions are used via macros defined in diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_pinmap.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_pinmap.h index 4b7ecf609b..d637a18714 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_pinmap.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_pinmap.h @@ -29,8 +29,7 @@ * Pre-processor Definitions ****************************************************************************/ -/** - * Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better +/* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better * speed performance. */ diff --git a/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h b/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h index 9cd617be77..763a0622bf 100644 --- a/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h +++ b/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h @@ -21,9 +21,8 @@ #ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H #define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H -/** - * @file regi2c_bbpll.h - * @brief Register definitions for digital PLL (BBPLL) +/* regi2c_bbpll.h + * Register definitions for digital PLL (BBPLL) * * This file lists register fields of BBPLL, located on an internal * configuration bus. These definitions are used via macros defined diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_libc_stubs.h b/arch/xtensa/src/esp32s2/rom/esp32s2_libc_stubs.h index 9101775437..fa6d95de4c 100644 --- a/arch/xtensa/src/esp32s2/rom/esp32s2_libc_stubs.h +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_libc_stubs.h @@ -44,8 +44,7 @@ struct _reent; -/** - * @brief ESP32-S2 ROM code contains implementations of some of C +/* ESP32-S2 ROM code contains implementations of some of C * library functions. * Whenever a function in ROM needs to use a syscall, it calls a * pointer to the corresponding syscall implementation defined in diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h b/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h index f5526f0cd3..5d9f609019 100644 --- a/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h @@ -138,53 +138,46 @@ typedef struct /* spi user mode command config */ -/** - * @brief Config the spi user command - * @param spi_num spi port - * @param pcmd pointer to accept the spi command struct +/* Config the spi user command + * spi_num spi port + * pcmd pointer to accept the spi command struct */ void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd); -/** - * @brief Start a spi user command sequence - * @param spi_num spi port - * @param rx_buf buffer pointer to receive data - * @param rx_len receive data length in byte - * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 - * @param is_write_erase to indicate whether this is a write or erase +/* Start a spi user command sequence + * spi_num spi port + * rx_buf buffer pointer to receive data + * rx_len receive data length in byte + * cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * is_write_erase to indicate whether this is a write or erase * operation, since the CPU would check permission */ void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); -/** - * @brief Config opi flash pads according to efuse settings. - */ +/* Config opi flash pads according to efuse settings. */ void esp_rom_opiflash_pin_config(void); -/** - * @brief Set SPI operation mode - * @param spi_num spi port - * @param mode Flash Read Mode +/* Set SPI operation mode + * spi_num spi port + * mode Flash Read Mode */ void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief Set data swap mode in DTR(DDR) mode - * @param spi_num spi port - * @param wr_swap to decide whether to swap fifo data in dtr write operation - * @param rd_swap to decide whether to swap fifo data in dtr read operation +/* Set data swap mode in DTR(DDR) mode + * spi_num spi port + * wr_swap to decide whether to swap fifo data in dtr write operation + * rd_swap to decide whether to swap fifo data in dtr read operation */ void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); -/** - * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) - * @param spi_num spi port +/* To send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * spi_num spi port */ void esp_rom_opiflash_mode_reset(int spi_num); @@ -193,21 +186,20 @@ void esp_rom_opiflash_mode_reset(int spi_num); /* MX25UM25645G opi flash interface */ -/** - * @brief To execute a flash operation command - * @param spi_num spi port - * @param mode Flash Read Mode - * @param cmd data to send in command field - * @param cmd_bit_len bit length of command field - * @param addr data to send in address field - * @param addr_bit_len bit length of address field - * @param dummy_bits bit length of dummy field - * @param mosi_data data buffer to be sent in mosi field - * @param mosi_bit_len bit length of data buffer to be sent in mosi field - * @param miso_data data buffer to accept data in miso field - * @param miso_bit_len bit length of data buffer to accept data in miso field - * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 - * @param is_write_erase_operation to indicate whether this a write or erase +/* To execute a flash operation command + * spi_num spi port + * mode Flash Read Mode + * cmd data to send in command field + * cmd_bit_len bit length of command field + * addr data to send in address field + * addr_bit_len bit length of address field + * dummy_bits bit length of dummy field + * mosi_data data buffer to be sent in mosi field + * mosi_bit_len bit length of data buffer to be sent in mosi field + * miso_data data buffer to accept data in miso field + * miso_bit_len bit length of data buffer to accept data in miso field + * cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * is_write_erase_operation to indicate whether this a write or erase * flash operation */ @@ -220,98 +212,89 @@ void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t cs_mask, bool is_write_erase_operation); -/** - * @brief send reset command to opi flash - * @param spi_num spi port - * @param mode Flash Operation Mode +/* end reset command to opi flash + * spi_num spi port + * mode Flash Operation Mode */ void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to read opi flash ID - * @note command format would be defined in initialization - * @param[out] out_id buffer to accept id - * @return flash operation result +/* To read opi flash ID + * Note command format would be defined in initialization + * out_id buffer to accept id + * Return flash operation result */ uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to read opi flash status register(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @return opi flash status value +/* To read opi flash status register(for MX25UM25645G) + * spi_num spi port + * mode Flash Operation Mode + * Return opi flash status value */ uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief wait opi flash status register to be idle - * @param spi_num spi port - * @param mode Flash Operation Mode +/* Wait opi flash status register to be idle + * spi_num spi port + * mode Flash Operation Mode */ void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to read the config register2(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @param addr the address of configure register - * @return value of config register2 +/* To read the config register2(for MX25UM25645G) + * spi_num spi port + * mode Flash Operation Mode + * addr the address of configure register + * Return value of config register2 */ uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr); -/** - * @brief to write the config register2(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @param addr the address of config register - * @param val the value to write +/* To write the config register2(for MX25UM25645G) + * spi_num spi port + * mode Flash Operation Mode + * addr the address of config register + * val the value to write */ void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val); -/** - * @brief to erase flash sector(for MX25UM25645G) - * @param spi_num spi port - * @param address the sector address to be erased - * @param mode Flash operation mode - * @return flash operation result +/* To erase flash sector(for MX25UM25645G) + * spi_num spi port + * address the sector address to be erased + * mode Flash operation mode + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to erase flash block(for MX25UM25645G) - * @param spi_num spi port - * @param address the block address to be erased - * @param mode Flash operation mode - * @return flash operation result +/* To erase flash block(for MX25UM25645G) + * spi_num spi port + * address the block address to be erased + * mode Flash operation mode + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to erase a flash area define by start address and length +/* To erase a flash area define by start address and length * (for MX25UM25645G) - * @param spi_num spi port - * @param start_addr the start address to be erased - * @param area_len the erea length to be erased - * @param mode flash operation mode - * @return flash operation result + * spi_num spi port + * start_addr the start address to be erased + * area_len the erea length to be erased + * mode flash operation mode + * Return flash operation result */ esp_rom_spiflash_result_t @@ -319,28 +302,26 @@ esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to read data from opi flash(for MX25UM25645G) - * @param spi_num spi port - * @param mode flash operation mode - * @param flash_addr flash address to read data from - * @param data_addr data buffer to accept the data - * @param len data length to be read - * @return flash operation result +/* T read data from opi flash(for MX25UM25645G) + * spi_num spi port + * mode flash operation mode + * flash_addr flash address to read data from + * data_addr data buffer to accept the data + * len data length to be read + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len); -/** - * @brief to write data to opi flash(for MX25UM25645G) - * @param spi_num spi port - * @param mode flash operation mode - * @param flash_addr flash address to write data to - * @param data_addr data buffer to write to flash - * @param len data length to write - * @return flash operation result +/* To write data to opi flash(for MX25UM25645G) + * spi_num spi port + * mode flash operation mode + * flash_addr flash address to write data to + * data_addr data buffer to write to flash + * len data length to write + * Return flash operation result */ esp_rom_spiflash_result_t @@ -348,11 +329,10 @@ esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len); -/** - * @brief to set opi flash operation mode(for MX25UM25645G) - * @param spi_num spi port - * @param cur_mode current operation mode - * @param target the target operation mode to be set +/* To set opi flash operation mode(for MX25UM25645G) + * spi_num spi port + * cur_mode current operation mode + * target the target operation mode to be set */ void esp_rom_opiflash_set_mode(int spi_num, diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h b/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h index 8dad19f18e..66ecaf6ed8 100644 --- a/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h @@ -143,8 +143,7 @@ typedef struct uint16_t data; } esp_rom_spiflash_common_cmd_t; -/** - * Structure holding SPI flash access critical sections management functions. +/* Structure holding SPI flash access critical sections management functions. * * Flash API uses two types of functions for flash access management: * 1) Functions which prepare/restore flash cache and interrupts before @@ -175,7 +174,7 @@ typedef struct * use OS primitives or even does not need them (multithreaded access is * not possible). * - * @note Structure and corresponding guard functions should not reside + * Note: Structure and corresponding guard functions should not reside * in flash. For example structure can be placed in DRAM and functions * in IRAM sections. */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c index a80a1da389..6684e8af1c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c @@ -1245,8 +1245,7 @@ static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) { - /** - * BLE interrupt function will call this adapter function to send + /* BLE interrupt function will call this adapter function to send * message to message queue, so here we should call kernel API * instead of application API */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_lcd.c b/arch/xtensa/src/esp32s3/esp32s3_lcd.c index 6fd1be2a0f..1615fcb1b6 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lcd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_lcd.c @@ -773,8 +773,7 @@ static void esp32s3_lcd_config(void) regval |= LCD_CAM_LCD_VSYNC_INT_ENA_M; esp32s3_lcd_putreg(LCD_CAM_LC_DMA_INT_ENA_REG, regval); - /** - * Set LCD screem parameters: + /* Set LCD screem parameters: * 1. RGB mode, ouput VSYNC/HSYNC/DE signal * 2. VT height * 3. VA height @@ -805,8 +804,7 @@ static void esp32s3_lcd_config(void) LCD_CAM_LCD_VSYNC_IDLE_POL_M; esp32s3_lcd_putreg(LCD_CAM_LCD_CTRL2_REG, regval); - /** - * Configure output mode: + /* Configure output mode: * 1. always output * 2. 16-bit word * 3. LCD mode diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c index bdc19e65bd..bb7ffc69fe 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c +++ b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c @@ -5594,8 +5594,7 @@ void xtensa_usbinitialize(void) esp32s3_configgpio(USB_IOMUX_DM, DRIVE_3); esp32s3_configgpio(USB_IOMUX_DP, DRIVE_3); - /** - * USB_OTG_IDDIG_IN_IDX: connected connector is mini-B side + /* USB_OTG_IDDIG_IN_IDX: connected connector is mini-B side * USB_SRP_BVALID_IN_IDX: HIGH to force USB device mode * USB_OTG_VBUSVALID_IN_IDX: receiving a valid Vbus from device * USB_OTG_AVALID_IN_IDX: HIGH to force USB host mode diff --git a/arch/xtensa/src/esp32s3/esp32s3_partition.c b/arch/xtensa/src/esp32s3/esp32s3_partition.c index 6702db638b..3a2e254ab4 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_partition.c +++ b/arch/xtensa/src/esp32s3/esp32s3_partition.c @@ -86,17 +86,15 @@ enum ota_img_ctrl_e enum ota_img_state_e { - /** - * Monitor the first boot. In bootloader of esp-idf this state is changed - * to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback. + /* Monitor the first boot. In bootloader of esp-idf this state is changed + * to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback. * - * So this driver doesn't use this state currently. + * So this driver doesn't use this state currently. */ OTA_IMG_NEW = 0x0, - /** - * First boot for this app was. If while the second boot this state is then + /* First boot for this app was. If while the second boot this state is then * it will be changed to ABORTED if this bootloader enable app rollback. * * So this driver doesn't use this state currently. @@ -112,8 +110,7 @@ enum ota_img_state_e OTA_IMG_INVALID = 0x3, - /** - * App could not confirm the workable or non-workable. In bootloader + /* App could not confirm the workable or non-workable. In bootloader * IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will * not selected to boot at all if this bootloader enable app rollback. * @@ -122,8 +119,7 @@ enum ota_img_state_e OTA_IMG_ABORTED = 0x4, - /** - * Undefined. App can boot and work without limits in esp-idf. + /* Undefined. App can boot and work without limits in esp-idf. * * This state is not used. */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h b/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h index 29491c88dc..600c316b22 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h +++ b/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h @@ -59,9 +59,8 @@ extern "C" *+-------------------------------------------------------------------------+ */ -/** - * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} - * @note refer to TRM: chapter +/* Naming conventions: RESET_REASON_{reset level}_{reset reason} + * Note refer to TRM: chapter */ typedef enum diff --git a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h index 8561aa0879..5bf725ea39 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h +++ b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h @@ -43,9 +43,7 @@ * Public Types ****************************************************************************/ -/** - * RT timer state - */ +/* RT timer state */ enum rt_timer_state_e { @@ -55,9 +53,7 @@ enum rt_timer_state_e RT_TIMER_DELETE /* Timer is to be delete */ }; -/** - * RT timer data structure - */ +/* RT timer data structure */ struct rt_timer_s { @@ -70,9 +66,7 @@ struct rt_timer_s struct list_node list; /* Working list */ }; -/** - * RT timer creation arguments data structure - */ +/* RT timer creation arguments data structure */ struct rt_timer_args_s { diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c index 5bcc8aebad..68c63c4f09 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c @@ -1440,8 +1440,7 @@ void IRAM_ATTR esp32s3_spi_timing_set_mspi_high_speed(bool spi1) void IRAM_ATTR esp32s3_spi_timing_set_mspi_low_speed(bool spi1) { - /** - * Here we are going to set the SPI1 frequency to be 20MHz, + /* Here we are going to set the SPI1 frequency to be 20MHz, * so we need to set SPI1 din_num and din_mode regs. * * Because SPI0 and SPI1 share the din_num and din_mode regs, diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.c b/arch/xtensa/src/esp32s3/esp32s3_spiram.c index fad579a396..8edf42e447 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiram.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.c @@ -451,11 +451,10 @@ void IRAM_ATTR esp_spiram_writeback_cache(void) cache_writeback_all(); } -/** - * @brief If SPI RAM(PSRAM) has been initialized +/* If SPI RAM(PSRAM) has been initialized * - * @return true SPI RAM has been initialized successfully - * @return false SPI RAM hasn't been initialized or initialized failed + * Return true SPI RAM has been initialized successfully + * Return false SPI RAM hasn't been initialized or initialized failed */ bool esp_spiram_is_initialized(void) @@ -468,10 +467,9 @@ uint8_t esp_spiram_get_cs_io(void) return psram_get_cs_io(); } -/** - * @brief Get allocable virtual start address +/* Get allocable virtual start address * - * @return Allocable virtual start address + * Return Allocable virtual start address */ uint32_t esp_spiram_allocable_vaddr_start(void) @@ -479,10 +477,9 @@ uint32_t esp_spiram_allocable_vaddr_start(void) return g_allocable_vaddr_start; } -/** - * @brief Get allocable virtual end address +/* Get allocable virtual end address * - * @return Allocable virtual end address + * Return Allocable virtual end address */ uint32_t esp_spiram_allocable_vaddr_end(void) diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.h b/arch/xtensa/src/esp32s3/esp32s3_spiram.h index 940a339da4..be46bf53a9 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiram.h +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.h @@ -34,57 +34,51 @@ extern "C" { #endif -/* @brief Initialize spiram interface/hardware. Normally called from +/* Initialize spiram interface/hardware. Normally called from * cpu_start.c. * - * @return ESP_OK on success + * Return ESP_OK on success */ int esp_spiram_init(void); -/** - * @brief Configure Cache/MMU for access to external SPI RAM. +/* Configure Cache/MMU for access to external SPI RAM. * * Normally this function is called from cpu_start, if * CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to * enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and * call this function later. * - * @attention this function must be called with flash cache disabled. + * Attention this function must be called with flash cache disabled. */ void esp_spiram_init_cache(void); -/** - * @brief Memory test for SPI RAM. Should be called after SPI RAM is +/* Memory test for SPI RAM. Should be called after SPI RAM is * initialized and (in case of a dual-core system) the app CPU is online. * This test overwrites the memory with crap, so do not call after e.g. the * heap allocator has stored important stuff in SPI RAM. * - * @return true on success, false on failed memory test + * Return true on success, false on failed memory test */ bool esp_spiram_test(void); -/** - * @brief Add the initialized SPI RAM to the heap allocator. - */ +/* Add the initialized SPI RAM to the heap allocator. */ int esp_spiram_add_to_heapalloc(void); -/** - * @brief Get the available physical size of the attached SPI RAM chip +/* Get the available physical size of the attached SPI RAM chip * - * @note If ECC is enabled, the available physical size would be smaller + * Note if ECC is enabled, the available physical size would be smaller * than the physical size. See `CONFIG_ESP32S3_SPIRAM_ECC_ENABLE` * - * @return Size in bytes, or 0 if no external RAM chip support compiled in. + * Return Size in bytes, or 0 if no external RAM chip support compiled in. */ size_t esp_spiram_get_size(void); -/** - * @brief Force a writeback of the data in the SPI RAM cache. This is to be +/* Force a writeback of the data in the SPI RAM cache. This is to be * called whenever cache is disabled, because disabling cache on the ESP32 * discards the data in the SPI RAM cache. * @@ -93,44 +87,40 @@ size_t esp_spiram_get_size(void); void esp_spiram_writeback_cache(void); -/** - * @brief If SPI RAM(PSRAM) has been initialized +/* If SPI RAM(PSRAM) has been initialized * - * @return + * Return * - true SPI RAM has been initialized successfully * - false SPI RAM hasn't been initialized or initialized failed */ bool esp_spiram_is_initialized(void); -/** - * @brief get psram CS IO +/* Get psram CS IO * * This interface should be called after PSRAM is enabled, otherwise it will * return an invalid value -1/0xff. * - * @return psram CS IO or -1/0xff if psram not enabled + * Return psram CS IO or -1/0xff if psram not enabled */ uint8_t esp_spiram_get_cs_io(void); -/** - * @brief Reserve a pool of internal memory for specific DMA/internal +/* Reserve a pool of internal memory for specific DMA/internal * allocations * - * @param size Size of reserved pool in bytes + * size Size of reserved pool in bytes * - * @return + * Return * - ESP_OK on success * - ESP_ERR_NO_MEM when no memory available for pool */ int esp_spiram_reserve_dma_pool(size_t size); -/** - * @brief If SPI RAM(PSRAM) has been initialized +/* If SPI RAM(PSRAM) has been initialized * - * @return + * Return * - true SPI RAM has been initialized successfully * - false SPI RAM hasn't been initialized or initialized failed */ @@ -142,26 +132,23 @@ bool esp_spiram_is_initialized(void); extern uint8_t _instruction_reserved_start[]; extern uint8_t _instruction_reserved_end[]; -/** - * @brief Get the start page number of the instruction in SPI flash +/* Get the start page number of the instruction in SPI flash * - * @return start page number + * Return start page number */ uint32_t instruction_flash_start_page_get(void); -/** - * @brief Get the end page number of the instruction in SPI flash +/* Get the end page number of the instruction in SPI flash * - * @return end page number + * Return end page number */ uint32_t instruction_flash_end_page_get(void); -/** - * @brief Get the offset of instruction from SPI flash to SPI RAM +/* Get the offset of instruction from SPI flash to SPI RAM * - * @return instruction offset + * Return instruction offset */ int instruction_flash2spiram_offset(void); @@ -173,44 +160,39 @@ int instruction_flash2spiram_offset(void); extern uint8_t _rodata_reserved_start[]; extern uint8_t _rodata_reserved_end[]; -/** - * @brief Get the start page number of the rodata in SPI flash +/* Get the start page number of the rodata in SPI flash * - * @return start page number + * Return start page number */ uint32_t rodata_flash_start_page_get(void); -/** - * @brief Get the end page number of the rodata in SPI flash +/* Get the end page number of the rodata in SPI flash * - * @return end page number + * Return end page number */ uint32_t rodata_flash_end_page_get(void); -/** - * @brief Get the offset number of rodata from SPI flash to SPI RAM +/* Get the offset number of rodata from SPI flash to SPI RAM * - * @return rodata offset + * Return rodata offset */ int rodata_flash2spiram_offset(void); #endif -/** - * @brief Get allocable virtual start address +/* Get allocable virtual start address * - * @return Allocable virtual start address + * Return Allocable virtual start address */ uint32_t esp_spiram_allocable_vaddr_start(void); -/** - * @brief Get allocable virtual end address +/* Get allocable virtual end address * - * @return Allocable virtual end address + * Return Allocable virtual end address */ uint32_t esp_spiram_allocable_vaddr_end(void); diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.h b/arch/xtensa/src/esp32s3/esp32s3_wdt.h index ae8b8f3efe..4beb711d1d 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wdt.h +++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.h @@ -95,10 +95,9 @@ enum esp32s3_wdt_stage_e ESP32S3_WDT_STAGE3 = 3 /* Stage 3 */ }; -/** - * Behavior of the WDT stage if it times out. +/* Behavior of the WDT stage if it times out. * - * @note These enum values should be compatible with the + * Note: These enum values should be compatible with the * corresponding register field values. */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_pinmap.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_pinmap.h index b77e6f031c..c354df4515 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_pinmap.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_pinmap.h @@ -29,8 +29,7 @@ * Pre-processor Definitions ****************************************************************************/ -/** - * Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better +/* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better * speed performance. */ diff --git a/arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h b/arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h index a696f1dbf4..d06a4015f8 100644 --- a/arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h +++ b/arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h @@ -21,9 +21,8 @@ #ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H #define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H -/** - * @file regi2c_bbpll.h - * @brief Register definitions for digital PLL (BBPLL) +/* regi2c_bbpll.h + * Register definitions for digital PLL (BBPLL) * * This file lists register fields of BBPLL, located on an internal * configuration bus. These definitions are used via macros defined diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h b/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h index 6740807433..ffc0d0f3d1 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h @@ -44,8 +44,7 @@ struct _reent; -/** - * @brief ESP32-S3 ROM code contains implementations of some of C +/* ESP32-S3 ROM code contains implementations of some of C * library functions. * Whenever a function in ROM needs to use a syscall, it calls a * pointer to the corresponding syscall implementation defined in diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h index e36b1a191d..7ac9219c2c 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h @@ -172,79 +172,69 @@ typedef struct extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def; -/** - * @brief init legacy driver for Octal Flash - */ +/* Init legacy driver for Octal Flash */ void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def); -/** - * @brief Config the spi user command - * @param spi_num spi port - * @param pcmd pointer to accept the spi command struct +/* Config the spi user command + * spi_num spi port + * pcmd pointer to accept the spi command struct */ void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd); -/** - * @brief Start a spi user command sequence - * @param spi_num spi port - * @param rx_buf buffer pointer to receive data - * @param rx_len receive data length in byte - * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 - * @param is_write_erase to indicate whether this is a write or erase +/* Start a spi user command sequence + * spi_num spi port + * rx_buf buffer pointer to receive data + * rx_len receive data length in byte + * cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * is_write_erase to indicate whether this is a write or erase * operation, since the CPU would check permission */ void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); -/** - * @brief Config opi flash pads according to efuse settings. - */ +/* Config opi flash pads according to efuse settings. */ void esp_rom_opiflash_pin_config(void); -/** - * @brief Set SPI read/write operation mode - * @param spi_num spi port - * @param mode Flash Read Mode +/* Set SPI read/write operation mode + * spi_num spi port + * mode Flash Read Mode */ void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief Set data swap mode in DTR(DDR) mode - * @param spi_num spi port - * @param wr_swap to decide whether to swap fifo data in dtr write operation - * @param rd_swap to decide whether to swap fifo data in dtr read operation +/* Set data swap mode in DTR(DDR) mode + * spi_num spi port + * wr_swap to decide whether to swap fifo data in dtr write operation + * rd_swap to decide whether to swap fifo data in dtr read operation */ void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); -/** - * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) - * @param spi_num spi port +/* To send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * spi_num spi port */ void esp_rom_opiflash_mode_reset(int spi_num); -/** - * @brief To execute a flash operation command - * @param spi_num spi port - * @param mode Flash Read Mode - * @param cmd data to send in command field - * @param cmd_bit_len bit length of command field - * @param addr data to send in address field - * @param addr_bit_len bit length of address field - * @param dummy_bits bit length of dummy field - * @param mosi_data data buffer to be sent in mosi field - * @param mosi_bit_len bit length of data buffer to be sent in mosi field - * @param miso_data data buffer to accept data in miso field - * @param miso_bit_len bit length of data buffer to accept data in miso field - * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 - * @param is_write_erase_operation to indicate whether this a write or erase +/* To execute a flash operation command + * spi_num spi port + * mode Flash Read Mode + * cmd data to send in command field + * cmd_bit_len bit length of command field + * addr data to send in address field + * addr_bit_len bit length of address field + * dummy_bits bit length of dummy field + * mosi_data data buffer to be sent in mosi field + * mosi_bit_len bit length of data buffer to be sent in mosi field + * miso_data data buffer to accept data in miso field + * miso_bit_len bit length of data buffer to accept data in miso field + * cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * is_write_erase_operation to indicate whether this a write or erase * flash operation */ @@ -257,110 +247,98 @@ void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t cs_mask, bool is_write_erase_operation); -/** - * @brief send reset command to opi flash - * @param spi_num spi port - * @param mode Flash Operation Mode +/* Send reset command to opi flash + * spi_num spi port + * mode Flash Operation Mode */ void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to read opi flash ID - * @note command format would be defined in initialization - * @param[out] out_id buffer to accept id - * @return flash operation result +/* To read opi flash ID + * command format would be defined in initialization + * out_id buffer to accept id + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id); -/** - * @brief to read opi flash status register - * @note command format would be defined in initialization - * @return opi flash status value +/* To read opi flash status register + * command format would be defined in initialization + * Return opi flash status value */ uint8_t esp_rom_opiflash_rdsr(void); -/** - * @brief wait opi flash status register to be idle - * @note command format would be defined in initialization - * @return flash operation result +/* Wait opi flash status register to be idle + * command format would be defined in initialization + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void); -/** - * @brief to erase flash sector - * @note command format would be defined in initialization - * @param sector_num the sector to be erased - * @return flash operation result +/* To erase flash sector + * command format would be defined in initialization + * sector_num the sector to be erased + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num); -/** - * @brief to erase flash block - * @note command format would be defined in initialization - * @param block_num the block to be erased - * @return flash operation result +/* Erase flash block + * command format would be defined in initialization + * block_num the block to be erased + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num); -/** - * @brief to erase a flash area define by start address and length - * @note command format would be defined in initialization - * @param start_addr the start address to be erased - * @param area_len the erea length to be erased - * @return flash operation result +/* To erase a flash area define by start address and length + * command format would be defined in initialization + * start_addr the start address to be erased + * area_len the erea length to be erased + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len); -/** - * @brief to read data from opi flash - * @note command format would be defined in initialization - * @param flash_addr flash address to read data from - * @param data_addr data buffer to accept the data - * @param len data length to be read - * @return flash operation result +/* To read data from opi flash + * command format would be defined in initialization + * flash_addr flash address to read data from + * data_addr data buffer to accept the data + * len data length to be read + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len); -/** - * @brief to write data to opi flash - * @note command format would be defined in initialization - * @param flash_addr flash address to write data to - * @param data_addr data buffer to write to flash - * @param len data length to write - * @return flash operation result +/* To write data to opi flash + * command format would be defined in initialization + * flash_addr flash address to write data to + * data_addr data buffer to write to flash + * len data length to write + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, const uint32_t *data_addr, int len); -/** - * @brief send WREN command - * @note command format would be defined in initialization - * @param arg not used, set to NULL - * @return flash operation result +/* Send WREN command + * command format would be defined in initialization + * arg not used, set to NULL + * Return flash operation result */ esp_rom_spiflash_result_t esp_rom_opiflash_wren(void *arg); -/** - * @brief to configure SPI0 read flash command format for cache - * @note command format would be defined in initialization - * +/* To configure SPI0 read flash command format for cache + * command format would be defined in initialization */ void diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h index 6341cfec21..183f8150e1 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h @@ -140,9 +140,7 @@ typedef struct uint16_t data; } esp_rom_spiflash_common_cmd_t; -/** - * Global ROM spiflash data, as used by legacy SPI flash functions - */ +/* Global ROM spiflash data, as used by legacy SPI flash functions */ struct spiflash_legacy_data_s { @@ -151,8 +149,7 @@ struct spiflash_legacy_data_s uint8_t sig_matrix; }; -/** - * Structure holding SPI flash access critical sections management functions. +/* Structure holding SPI flash access critical sections management functions. * * Flash API uses two types of functions for flash access management: * 1) Functions which prepare/restore flash cache and interrupts before @@ -183,9 +180,9 @@ struct spiflash_legacy_data_s * use OS primitives or even does not need them (multithreaded access is * not possible). * - * @note Structure and corresponding guard functions should not reside - * in flash. For example structure can be placed in DRAM and functions - * in IRAM sections. + * Note Structure and corresponding guard functions should not reside + * in flash. For example structure can be placed in DRAM and functions + * in IRAM sections. */ struct spiflash_guard_funcs diff --git a/boards/arm/sam34/sam4s-xplained-pro/src/sam_nandflash.c b/boards/arm/sam34/sam4s-xplained-pro/src/sam_nandflash.c index c0800d6c4c..bc87f8d964 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/src/sam_nandflash.c +++ b/boards/arm/sam34/sam4s-xplained-pro/src/sam_nandflash.c @@ -131,8 +131,7 @@ int board_nandflash_config(int cs) /* Configure the SMC cycle timing */ - /** - * Select 0. Chip Select 0 has been programmed with: + /* Select 0. Chip Select 0 has been programmed with: * NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) * NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) * TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). @@ -143,9 +142,7 @@ int board_nandflash_config(int cs) /* Configure the SMC mode */ - /** - * - * READ_MODE: + /* READ_MODE: * 0: The read operation is controlled by the NCS signal. * 1: The read operation is controlled by the NRD signal. * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c b/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c index 2b19edf4af..4e68f0b989 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c +++ b/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c @@ -204,8 +204,7 @@ static inline void write_byte(uint8_t data) { LCD_RD_SET; - /** - * This is simple to understand + /* This is simple to understand * * stm32_gpiowrite(GPIO_LCD_D0, GET_BIT(data, BIT0)); * stm32_gpiowrite(GPIO_LCD_D1, GET_BIT(data, BIT1)); diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h b/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h index ba67daa17e..3c51fc8af5 100644 --- a/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h +++ b/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h @@ -31,8 +31,7 @@ * ****************************************************************************/ -/** - * nsh_romfsetc.h +/* nsh_romfsetc.h * * This file is a stub for 'make export' purposes; the actual ROMFS * must be supplied by the library client. diff --git a/boards/xtensa/esp32s2/common/scripts/esp32s2_rom.ld b/boards/xtensa/esp32s2/common/scripts/esp32s2_rom.ld index 3924ed7dc3..492c081b50 100644 --- a/boards/xtensa/esp32s2/common/scripts/esp32s2_rom.ld +++ b/boards/xtensa/esp32s2/common/scripts/esp32s2_rom.ld @@ -18,8 +18,7 @@ * ****************************************************************************/ -/** - * ESP32-S2 ROM address table (except symbols from libgcc and libc) +/* ESP32-S2 ROM address table (except symbols from libgcc and libc) * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796 * * These are all weak symbols that could be overwritten in ESP-IDF. diff --git a/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld index 5cfc7df437..18172254ef 100644 --- a/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld +++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld @@ -18,9 +18,8 @@ * ****************************************************************************/ -/** - * ROM APIs - */ +/* ROM APIs */ + PROVIDE ( esp_rom_crc32_le = crc32_le ); PROVIDE ( esp_rom_crc16_le = crc16_le ); PROVIDE ( esp_rom_crc8_le = crc8_le ); diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3-box.h b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3-box.h index b83fff7bec..fffd8e8bb8 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3-box.h +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3-box.h @@ -44,8 +44,7 @@ #define DISPLAY_SPI 2 -/** - * CS: 5 +/* CS: 5 * CLK: 7 * MOSI: 6 * MISO: N/A @@ -64,8 +63,7 @@ #define TOUCHSCEEN_I2C 0 -/** - * SCL: 18 +/* SCL: 18 * SDA: 8 */ diff --git a/drivers/misc/optee_msg.h b/drivers/misc/optee_msg.h index 0be2b94224..31cf0b5146 100644 --- a/drivers/misc/optee_msg.h +++ b/drivers/misc/optee_msg.h @@ -16,8 +16,7 @@ #include #include -/** - * This file defines the OP-TEE message protocol (ABI) used to communicate +/* This file defines the OP-TEE message protocol (ABI) used to communicate * with an instance of OP-TEE running in secure world. * * This file is divided into two sections. @@ -45,16 +44,14 @@ #define OPTEE_MSG_ATTR_TYPE_MASK GENMASK(7, 0) -/** - * Meta parameter to be absorbed by the Secure OS and not passed +/* Meta parameter to be absorbed by the Secure OS and not passed * to the Trusted Application. - * * Currently only used with OPTEE_MSG_CMD_OPEN_SESSION. */ + #define OPTEE_MSG_ATTR_META BIT(8) -/** - * Pointer to a list of pages used to register user-defined SHM buffer. +/* Pointer to a list of pages used to register user-defined SHM buffer. * Used with OPTEE_MSG_ATTR_TYPE_TMEM_*. * buf_ptr should point to the beginning of the buffer. Buffer will contain * list of page addresses. OP-TEE core can reconstruct contiguous buffer from @@ -81,22 +78,22 @@ * architectures. If REE uses larger pages, it should divide them to 4KB * ones. */ + #define OPTEE_MSG_ATTR_NONCONTIG BIT(9) -/** - * Memory attributes for caching passed with temp memrefs. The actual value +/* Memory attributes for caching passed with temp memrefs. The actual value * used is defined outside the message protocol with the exception of * OPTEE_MSG_ATTR_CACHE_PREDEFINED which means the attributes already * defined for the memory range should be used. If optee_smc.h is used as * bearer of this protocol OPTEE_SMC_SHM_* is used for values. */ + #define OPTEE_MSG_ATTR_CACHE_SHIFT 16 #define OPTEE_MSG_ATTR_CACHE_MASK GENMASK(2, 0) #define OPTEE_MSG_ATTR_CACHE_PREDEFINED 0 -/** - * Same values as TEE_LOGIN_* from TEE Internal API - */ +/* Same values as TEE_LOGIN_* from TEE Internal API */ + #define OPTEE_MSG_LOGIN_PUBLIC 0x00000000 #define OPTEE_MSG_LOGIN_USER 0x00000001 #define OPTEE_MSG_LOGIN_GROUP 0x00000002 @@ -104,19 +101,17 @@ #define OPTEE_MSG_LOGIN_APPLICATION_USER 0x00000005 #define OPTEE_MSG_LOGIN_APPLICATION_GROUP 0x00000006 -/** - * Page size used in non-contiguous buffer entries - */ +/* Page size used in non-contiguous buffer entries */ + #define OPTEE_MSG_NONCONTIG_PAGE_SIZE 4096 #define OPTEE_MSG_FMEM_INVALID_GLOBAL_ID 0xffffffffffffffff -/** - * struct optee_msg_param_tmem - temporary memory reference parameter - * @buf_ptr: Address of the buffer - * @size: Size of the buffer - * @shm_ref: Temporary shared memory reference, pointer to a struct - * tee_shm +/* struct optee_msg_param_tmem - temporary memory reference parameter + * buf_ptr: Address of the buffer + * size: Size of the buffer + * shm_ref: Temporary shared memory reference, pointer to a struct + * tee_shm * * Secure and normal world communicates pointers as physical address * instead of the virtual address. This is because secure and normal world @@ -133,11 +128,10 @@ struct optee_msg_param_tmem uint64_t shm_ref; }; -/** - * struct optee_msg_param_rmem - registered memory reference parameter - * @offs: Offset into shared memory reference - * @size: Size of the buffer - * @shm_ref: Shared memory reference, pointer to a struct tee_shm +/* struct optee_msg_param_rmem - registered memory reference parameter + * offs: Offset into shared memory reference + * size: Size of the buffer + * shm_ref: Shared memory reference, pointer to a struct tee_shm */ struct optee_msg_param_rmem @@ -147,14 +141,13 @@ struct optee_msg_param_rmem uint64_t shm_ref; }; -/** - * struct optee_msg_param_fmem - ffa memory reference parameter - * @offs_lower: Lower bits of offset into shared memory reference - * @offs_upper: Upper bits of offset into shared memory reference - * @internal_offs: Internal offset into the first page of shared memory - * reference - * @size: Size of the buffer - * @global_id: Global identifier of Shared memory +/* struct optee_msg_param_fmem - ffa memory reference parameter + * offs_lower: Lower bits of offset into shared memory reference + * offs_upper: Upper bits of offset into shared memory reference + * internal_offs: Internal offset into the first page of shared memory + * reference + * size: Size of the buffer + * global_id: Global identifier of Shared memory */ struct optee_msg_param_fmem @@ -166,8 +159,7 @@ struct optee_msg_param_fmem uint64_t global_id; }; -/** - * struct optee_msg_param_value - opaque value parameter +/* struct optee_msg_param_value - opaque value parameter * * Value parameters are passed unchecked between normal and secure world. */ @@ -179,20 +171,19 @@ struct optee_msg_param_value uint64_t c; }; -/** - * struct optee_msg_param - parameter used together with struct optee_msg_arg - * @attr: attributes - * @tmem: parameter by temporary memory reference - * @rmem: parameter by registered memory reference - * @fmem: parameter by ffa registered memory reference - * @value: parameter by opaque value - * @octets: parameter by octet string +/* struct optee_msg_param - parameter used together with struct optee_msg_arg + * attr: attributes + * tmem: parameter by temporary memory reference + * rmem: parameter by registered memory reference + * fmem: parameter by ffa registered memory reference + * value: parameter by opaque value + * octets: parameter by octet string * - * @attr & OPTEE_MSG_ATTR_TYPE_MASK indicates if tmem, rmem or value is used + * attr & OPTEE_MSG_ATTR_TYPE_MASK indicates if tmem, rmem or value is used * in the union. OPTEE_MSG_ATTR_TYPE_VALUE_* indicates value or octets, - * OPTEE_MSG_ATTR_TYPE_TMEM_* indicates @tmem and + * OPTEE_MSG_ATTR_TYPE_TMEM_* indicates tmem and * OPTEE_MSG_ATTR_TYPE_RMEM_* or the alias PTEE_MSG_ATTR_TYPE_FMEM_* - * indicates @rmem or @fmem depending on the conduit. + * indicates rmem or fmem depending on the conduit. * OPTEE_MSG_ATTR_TYPE_NONE indicates that none of the members are used. */ @@ -209,19 +200,18 @@ struct optee_msg_param } u; }; -/** - * struct optee_msg_arg - call argument - * @cmd: Command, one of OPTEE_MSG_CMD_* or OPTEE_MSG_RPC_CMD_* - * @func: Trusted Application function, specific to the Trusted Application, - * used if cmd == OPTEE_MSG_CMD_INVOKE_COMMAND - * @session: In parameter for all OPTEE_MSG_CMD_* except - * OPTEE_MSG_CMD_OPEN_SESSION where it's an output parameter - * instead - * @cancel_id: Cancellation id, a unique value to identify this request - * @ret: return value - * @ret_origin: origin of the return value - * @num_params: number of parameters supplied to the OS Command - * @params: the parameters supplied to the OS Command +/* struct optee_msg_arg - call argument + * cmd: Command, one of OPTEE_MSG_CMD_* or OPTEE_MSG_RPC_CMD_* + * func: Trusted Application function, specific to the Trusted Application, + * used if cmd == OPTEE_MSG_CMD_INVOKE_COMMAND + * session: In parameter for all OPTEE_MSG_CMD_* except + * OPTEE_MSG_CMD_OPEN_SESSION where it's an output parameter + * instead + * cancel_id: Cancellation id, a unique value to identify this request + * ret: return value + * ret_origin: origin of the return value + * num_params: number of parameters supplied to the OS Command + * params: the parameters supplied to the OS Command * * All normal calls to Trusted OS uses this struct. If cmd requires further * information than what these fields hold it can be passed as a parameter @@ -245,14 +235,14 @@ struct optee_msg_arg struct optee_msg_param params[]; }; -/** - * OPTEE_MSG_GET_ARG_SIZE - return size of struct optee_msg_arg +/* OPTEE_MSG_GET_ARG_SIZE - return size of struct optee_msg_arg * - * @num_params: Number of parameters embedded in the struct optee_msg_arg + * num_params: Number of parameters embedded in the struct optee_msg_arg * * Returns the size of the struct optee_msg_arg together with the number * of embedded parameters. */ + #define OPTEE_MSG_GET_ARG_SIZE(num_params) \ (sizeof(struct optee_msg_arg) + \ sizeof(struct optee_msg_param) * (num_params)) @@ -261,30 +251,29 @@ struct optee_msg_arg * Part 2 - requests from normal world ****************************************************************************/ -/** - * Return the following UID if using API specified in this file without +/* Return the following UID if using API specified in this file without * further extensions: * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b. * Represented in 4 32-bit words in OPTEE_MSG_UID_0, OPTEE_MSG_UID_1, * OPTEE_MSG_UID_2, OPTEE_MSG_UID_3. */ + #define OPTEE_MSG_UID_0 0x384fb3e0 #define OPTEE_MSG_UID_1 0xe7f811e3 #define OPTEE_MSG_UID_2 0xaf630002 #define OPTEE_MSG_UID_3 0xa5d5c51b #define OPTEE_MSG_FUNCID_CALLS_UID 0xFF01 -/** - * Returns 2.0 if using API specified in this file without further +/* Returns 2.0 if using API specified in this file without further * extensions. Represented in 2 32-bit words in OPTEE_MSG_REVISION_MAJOR * and OPTEE_MSG_REVISION_MINOR */ + #define OPTEE_MSG_REVISION_MAJOR 2 #define OPTEE_MSG_REVISION_MINOR 0 #define OPTEE_MSG_FUNCID_CALLS_REVISION 0xFF03 -/** - * Get UUID of Trusted OS. +/* Get UUID of Trusted OS. * * Used by non-secure world to figure out which Trusted OS is installed. * Note that returned UUID is the UUID of the Trusted OS, not of the API. @@ -292,14 +281,14 @@ struct optee_msg_arg * Returns UUID in 4 32-bit words in the same way as * OPTEE_MSG_FUNCID_CALLS_UID described above. */ + #define OPTEE_MSG_OS_OPTEE_UUID_0 0x486178e0 #define OPTEE_MSG_OS_OPTEE_UUID_1 0xe7f811e3 #define OPTEE_MSG_OS_OPTEE_UUID_2 0xbc5e0002 #define OPTEE_MSG_OS_OPTEE_UUID_3 0xa5d5c51b #define OPTEE_MSG_FUNCID_GET_OS_UUID 0x0000 -/** - * Get revision of Trusted OS. +/* Get revision of Trusted OS. * * Used by non-secure world to figure out which version of the Trusted OS * is installed. Note that the returned revision is the revision of the @@ -308,10 +297,10 @@ struct optee_msg_arg * Returns revision in 2 32-bit words in the same way as * OPTEE_MSG_CALLS_REVISION described above. */ + #define OPTEE_MSG_FUNCID_GET_OS_REVISION 0x0001 -/** - * Do a secure call with struct optee_msg_arg as argument +/* Do a secure call with struct optee_msg_arg as argument * The OPTEE_MSG_CMD_* below defines what goes in struct optee_msg_arg::cmd * * OPTEE_MSG_CMD_OPEN_SESSION opens a session to a Trusted Application. @@ -352,6 +341,7 @@ struct optee_msg_arg * normal world unable to process asynchronous notifications. Typically * used when the driver is shut down. */ + #define OPTEE_MSG_CMD_OPEN_SESSION 0 #define OPTEE_MSG_CMD_INVOKE_COMMAND 1 #define OPTEE_MSG_CMD_CLOSE_SESSION 2 diff --git a/drivers/net/lan9250.c b/drivers/net/lan9250.c index e2bba33954..256371b160 100644 --- a/drivers/net/lan9250.c +++ b/drivers/net/lan9250.c @@ -84,8 +84,7 @@ # define LAN9250_SPI_ENABLE_SQI LAN9250_SPI_CMD_ENABLE_SQI #endif -/** - * LAN9250 interrupt trigger source: +/* LAN9250 interrupt trigger source: * * - PHY for checking link up or down * - TX data FIFO available @@ -923,8 +922,7 @@ static inline void lan9250_send_buffer(FAR struct lan9250_driver_s *priv, lan9250_buffer_dump(LAN9250_TXDFR, buffer, buflen); - /** - * LAN9250 SPI write command A fields: + /* LAN9250 SPI write command A fields: * * - TX packet length 4 bytes align * - First frame @@ -935,8 +933,7 @@ static inline void lan9250_send_buffer(FAR struct lan9250_driver_s *priv, SPI_CMD_WRITE_A_LS | buflen; lan9250_set_reg(priv, LAN9250_TXDFR, regval); - /** - * LAN9250 SPI write command B fields: + /* LAN9250 SPI write command B fields: * * - Packet TAG */ @@ -1059,8 +1056,7 @@ static inline void lan9250_sw_reset(FAR struct lan9250_driver_s *priv) lan9250_wait_ready(priv, LAN9250_BOTR, BOTR_MASK, BOTR_VAL, LAN9250_RESET_TIMEOUT); - /** - * Send a command to reset: + /* Send a command to reset: * * - Digital controller * - HMAC @@ -1104,8 +1100,7 @@ static void lan9250_set_txavailabe(FAR struct lan9250_driver_s *priv, if (enable) { - /** - * Configure FIFO level interrupt: + /* Configure FIFO level interrupt: * * - TX data available level: Ethernet maximum packet size, transform * this value to be block number with 64-byte align @@ -1124,8 +1119,7 @@ static void lan9250_set_txavailabe(FAR struct lan9250_driver_s *priv, } else { - /** - * Configure FIFO level interrupt: + /* Configure FIFO level interrupt: * * - TX data available level: 255, so that no interrupt triggers * - TX status level: 255, use maximum value so that this will not be @@ -1184,8 +1178,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) ninfo("Rev ID: %08x\n", regval & CIARR_CREV_M); - /** - * Configure TX FIFO size mode to be 8: + /* Configure TX FIFO size mode to be 8: * * - TX data FIFO size: 7680 * - RX data FIFO size: 7680 @@ -1196,8 +1189,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) regval = HWCFGR_MBO | (8 << HWCFGR_TXFS_S); lan9250_set_reg(priv, LAN9250_HWCFGR, regval); - /** - * Configure MAC automatic flow control: + /* Configure MAC automatic flow control: * * - Automatic flow control high level: 110 * - Automatic flow control low level: 55 @@ -1211,8 +1203,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) HMAFCCFGR_FCOAF; lan9250_set_reg(priv, LAN9250_HMAFCCFGR, regval); - /** - * Configure host MAC flow control: + /* Configure host MAC flow control: * * - Pause time: 15 * - Flow control @@ -1221,8 +1212,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) regval = (0xf << HMACFCR_PT_S) | HMACFCR_FLE; lan9250_set_macreg(priv, LAN9250_HMACFCR, regval); - /** - * Configure interrupt: + /* Configure interrupt: * * - Interrupt De-assertion interval: 10 * - Interrupt output to pin @@ -1234,8 +1224,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) ICFGR_IRQE | ICFGR_IRQBT; lan9250_set_reg(priv, LAN9250_ICFGR, regval); - /** - * Configure interrupt trigger source, please refer to macro + /* Configure interrupt trigger source, please refer to macro * LAN9250_INT_SOURCE. */ @@ -1245,8 +1234,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) lan9250_set_txavailabe(priv, false); - /** - * Configure RX: + /* Configure RX: * * - RX DMA counter: Ethernet maximum packet size * - RX data offset: 4, so that need read dummy before reading data @@ -1255,8 +1243,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) regval = (LAN9250_PKTBUF_SIZE << RXCFGR_RXDMAC_S) | (4 << RXCFGR_RXDO_S); lan9250_set_reg(priv, LAN9250_RXCFGR, regval); - /** - * Configure remote power management: + /* Configure remote power management: * * - Auto wakeup * - Disable 1588 clock @@ -1274,8 +1261,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) PMCR_WOLS | PMCR_PMEP | PMCR_PMEE; lan9250_set_reg(priv, LAN9250_PMCR, regval); - /** - * Configure PHY basic control: + /* Configure PHY basic control: * * - Auto-Negotiation for speed(10 or 100Mbsp) and direction * (half or full duplex) @@ -1283,8 +1269,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) lan9250_set_phyreg(priv, LAN9250_PHYBCR, PHYBCR_ANE); - /** - * Configure PHY auto-negotiation advertisement capability: + /* Configure PHY auto-negotiation advertisement capability: * * - Asymmetric pause * - Symmetric pause @@ -1302,8 +1287,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) #endif lan9250_set_phyreg(priv, LAN9250_PHYANAR, regval); - /** - * Configure PHY special mode: + /* Configure PHY special mode: * * - PHY mode = 111b, enable all capable and auto-nagotiation * - PHY address = 1, default value is fixed to 1 by manufacturer @@ -1312,8 +1296,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) regval = PHYSMR_PM_M | 1; lan9250_set_phyreg(priv, LAN9250_PHYSMR, regval); - /** - * Configure PHY special control or status indication: + /* Configure PHY special control or status indication: * * - Port auto-MDIX determined by bits 14 and 13 * - Auto-MDIX @@ -1323,8 +1306,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) regval = PHYSCOSIR_AMDIXC | PHYSCOSIR_AMDIXE | PHYSCOSIR_SQETD; lan9250_set_phyreg(priv, LAN9250_PHYSCOSIR, regval); - /** - * Configure PHY interrupt source: + /* Configure PHY interrupt source: * * - Link up * - Link down @@ -1333,8 +1315,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) regval = PHYIER_LU | PHYIER_LD; lan9250_set_phyreg(priv, LAN9250_PHYIER, regval); - /** - * Configure special control or status: + /* Configure special control or status: * * - Fixed to write 0000010b to reserved filed */ @@ -1345,8 +1326,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) lan9250_set_reg(priv, LAN9250_ISR, UINT32_MAX); - /** - * Configure HMAC control: + /* Configure HMAC control: * * - Automaticaly strip the pad field on incoming packets * - TX enable @@ -1458,8 +1438,7 @@ static int lan9250_transmit(FAR struct lan9250_driver_s *priv) lan9250_set_txavailabe(priv, true); - /** - * Enable the TX timeout watchdog (perhaps restarting the timer) + /* Enable the TX timeout watchdog (perhaps restarting the timer) * when free data space is not enough. */ @@ -1763,16 +1742,14 @@ static void lan9250_rxdone_isr(FAR struct lan9250_driver_s *priv) if (pktlen) { - /** - * Copy the data from the receive buffer to priv->dev.d_buf. + /* Copy the data from the receive buffer to priv->dev.d_buf. * ERDPT should be correctly positioned from the last call to * end_rdbuffer (above). */ lan9250_recv_buffer(priv, priv->dev.d_buf, pktlen); - /** - * Save the packet length (without the 4 byte CRC) + /* Save the packet length (without the 4 byte CRC) * in priv->dev.d_len. */ @@ -1815,8 +1792,7 @@ static void lan9250_int_worker(FAR void *arg) net_lock(); lan9250_lock_spi(priv); - /** - * There is no infinite loop check... if there are always pending + /* There is no infinite loop check... if there are always pending * interrupts, we are just broken. */ @@ -2002,8 +1978,7 @@ static void lan9250_int_worker(FAR void *arg) lan9250_unlock_spi(priv); net_unlock(); - /** - * Enable ISR_GPIO interrupts after unlocking net so that application + /* Enable ISR_GPIO interrupts after unlocking net so that application * could have chance to process Ethernet packet and free iob. */ @@ -2285,8 +2260,7 @@ static int lan9250_txavail(FAR struct net_driver_s *dev) (FAR struct lan9250_driver_s *)dev->d_private; irqstate_t flags; - /** - * Lock the SPI bus so that we have exclusive access for but SPI and + /* Lock the SPI bus so that we have exclusive access for but SPI and * LAN9250 SPI private data. */ @@ -2294,8 +2268,7 @@ static int lan9250_txavail(FAR struct net_driver_s *dev) flags = enter_critical_section(); - /** - * Since SPI is locked, so interrupt work must not really process when + /* Since SPI is locked, so interrupt work must not really process when * CPU run here, so: * * - priv->tx_available = true, TX data FIFO is available and its related diff --git a/drivers/power/battery/axp202.c b/drivers/power/battery/axp202.c index 1f362260cb..9187812b05 100644 --- a/drivers/power/battery/axp202.c +++ b/drivers/power/battery/axp202.c @@ -390,8 +390,7 @@ static int axp202_current(FAR struct battery_charger_dev_s *dev, int value) return ret; } - /** - * Charge current setting + /* Charge current setting * Icharge= [300+(Bit3-0)*100] mA */ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h index 5437fbb7da..9de31747f8 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h @@ -3177,8 +3177,8 @@ typedef enum #define WLC_DOT11_SC_STATUS_OFFSET (512) /* Enumerated list of event status codes - * @note : WLC_SUP values overlap other values, so it is necessary - * to check the event type + * Note : WLC_SUP values overlap other values, so it is necessary + * to check the event type */ typedef enum @@ -3255,8 +3255,8 @@ typedef enum #define WLC_E_DOT11_RC_REASON_OFFSET (768) /* Enumerated list of event reason codes - * @note : Several values overlap other values, so it is necessary - * to check the event type + * Note : Several values overlap other values, so it is necessary + * to check the event type */ typedef enum diff --git a/drivers/wireless/spirit/include/spirit_radio.h b/drivers/wireless/spirit/include/spirit_radio.h index bb377e296d..7ceed89ec0 100644 --- a/drivers/wireless/spirit/include/spirit_radio.h +++ b/drivers/wireless/spirit/include/spirit_radio.h @@ -783,7 +783,7 @@ int spirit_radio_convert_datarate(FAR struct spirit_library_s *spirit, * Returns the mantissa and exponent for a given bandwidth. Even if it is * possible to pass as parameter any value in the below mentioned range, the * API will search the closer value according to a fixed table of channel - * bandwidth values (@ref s_vectnBandwidth), as defined in the datasheet, + * bandwidth values (s_vectnBandwidth), as defined in the datasheet, * returning the corresponding mantissa and exponent value. * * Input Parameters: @@ -1167,7 +1167,7 @@ int spirit_radio_set_palevel_dbm(FAR struct spirit_library_s *spirit, * Returns a specific PA_LEVEL register, returning a value in dBm. * * NOTE: - * This function makes use of the @ref spirit_radio_convert_reg2power fcn to + * This function makes use of the spirit_radio_convert_reg2power fcn to * interpolate the power value. * * Input Parameters: diff --git a/include/netinet/if_ether.h b/include/netinet/if_ether.h index d1986f2fc3..b38cb138d4 100644 --- a/include/netinet/if_ether.h +++ b/include/netinet/if_ether.h @@ -38,8 +38,7 @@ #define ETH_P_IP ETHERTYPE_IP #define ETH_P_ARP ETHERTYPE_ARP -/** - * Ethernet Address Resolution Protocol. +/* Ethernet Address Resolution Protocol. * * See RFC 826 for protocol description. Structure below is adapted * to resolving internet addresses. Field names used correspond to diff --git a/include/netpacket/netlink.h b/include/netpacket/netlink.h index 0612883b34..2b443ac6a9 100644 --- a/include/netpacket/netlink.h +++ b/include/netpacket/netlink.h @@ -415,8 +415,7 @@ #define FRA_TABLE 2 /* Extended table id */ #define FRA_FWMASK 3 /* Mask for netfilter mark */ -/** - * nla_type (16 bits) +/* nla_type (16 bits) * +---+---+-------------------------------+ * | N | O | Attribute Type | * +---+---+-------------------------------+ @@ -474,14 +473,13 @@ struct nlmsgerr { int error; struct nlmsghdr msg; - /** - * Followed by the message contents unless NETLINK_CAP_ACK was set + + /* Followed by the message contents unless NETLINK_CAP_ACK was set * or the ACK indicates success (error == 0) * message length is aligned with NLMSG_ALIGN() */ - /** - * Followed by TLVs defined in enum nlmsgerr_attrs + /* Followed by TLVs defined in enum nlmsgerr_attrs * if NETLINK_EXT_ACK was set */ }; @@ -552,8 +550,7 @@ struct rtmsg uint32_t rtm_flags; }; -/** - * <------- NLA_HDRLEN ------> <-- NLA_ALIGN(payload)--> +/* <------- NLA_HDRLEN ------> <-- NLA_ALIGN(payload)--> * +---------------------+- - -+- - - - - - - - - -+- - -+ * | Header | Pad | Payload | Pad | * | (struct nlattr) | ing | | ing | diff --git a/include/nuttx/bits.h b/include/nuttx/bits.h index 138765eda3..371934ea25 100644 --- a/include/nuttx/bits.h +++ b/include/nuttx/bits.h @@ -53,8 +53,8 @@ #define BIT(nr) (1ul << (nr)) #define BIT_ULL(nr) (1ull << (nr)) -/* Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example +/* Create a contiguous bitmask starting at bit position l and ending at + * position h. For example * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. */ diff --git a/include/nuttx/ethtool.h b/include/nuttx/ethtool.h index 1d0c3191f6..cd0bbcbbf6 100644 --- a/include/nuttx/ethtool.h +++ b/include/nuttx/ethtool.h @@ -130,71 +130,70 @@ * Public Type Definitions ****************************************************************************/ -/** - * struct ethtool_cmd - DEPRECATED, link control and status +/* struct ethtool_cmd - DEPRECATED, link control and status * This structure is DEPRECATED, please use struct ethtool_link_settings. - * @cmd: Command number = %ETHTOOL_GSET or %ETHTOOL_SSET - * @supported: Bitmask of %SUPPORTED_* flags for the link modes, + * cmd: Command number = ETHTOOL_GSET or ETHTOOL_SSET + * supported: Bitmask of SUPPORTED_* flags for the link modes, * physical connectors and other link features for which the * interface supports autonegotiation or auto-detection. * Read-only. - * @advertising: Bitmask of %ADVERTISED_* flags for the link modes, + * advertising: Bitmask of ADVERTISED_* flags for the link modes, * physical connectors and other link features that are * advertised through autonegotiation or enabled for * auto-detection. - * @speed: Low bits of the speed, 1Mb units, 0 to INT_MAX or SPEED_UNKNOWN - * @duplex: Duplex mode; one of %DUPLEX_* - * @port: Physical connector type; one of %PORT_* - * @phy_address: MDIO address of PHY (transceiver); 0 or 255 if not + * speed: Low bits of the speed, 1Mb units, 0 to INT_MAX or SPEED_UNKNOWN + * duplex: Duplex mode; one of DUPLEX_* + * port: Physical connector type; one of PORT_* + * phy_address: MDIO address of PHY (transceiver); 0 or 255 if not * applicable. For clause 45 PHYs this is the PRTAD. - * @transceiver: Historically used to distinguish different possible + * transceiver: Historically used to distinguish different possible * PHY types, but not in a consistent way. Deprecated. - * @autoneg: Enable/disable autonegotiation and auto-detection; - * either %AUTONEG_DISABLE or %AUTONEG_ENABLE - * @mdio_support: Bitmask of %ETH_MDIO_SUPPORTS_* flags for the MDIO + * autoneg: Enable/disable autonegotiation and auto-detection; + * either AUTONEG_DISABLE or AUTONEG_ENABLE + * mdio_support: Bitmask of ETH_MDIO_SUPPORTS_* flags for the MDIO * protocols supported by the interface; 0 if unknown. * Read-only. - * @maxtxpkt: Historically used to report TX IRQ coalescing; now - * obsoleted by &struct ethtool_coalesce. Read-only; deprecated. - * @maxrxpkt: Historically used to report RX IRQ coalescing; now - * obsoleted by &struct ethtool_coalesce. Read-only; deprecated. - * @speed_hi: High bits of the speed, 1Mb units, 0 to INT_MAX or + * maxtxpkt: Historically used to report TX IRQ coalescing; now + * obsoleted by struct ethtool_coalesce. Read-only; deprecated. + * maxrxpkt: Historically used to report RX IRQ coalescing; now + * obsoleted by struct ethtool_coalesce. Read-only; deprecated. + * speed_hi: High bits of the speed, 1Mb units, 0 to INT_MAX or * SPEED_UNKNOWN - * @eth_tp_mdix: Ethernet twisted-pair MDI(-X) status; one of - * %ETH_TP_MDI_*. If the status is unknown or not applicable, the - * value will be %ETH_TP_MDI_INVALID. Read-only. - * @eth_tp_mdix_ctrl: Ethernet twisted pair MDI(-X) control; one of - * %ETH_TP_MDI_*. If MDI(-X) control is not implemented, reads - * yield %ETH_TP_MDI_INVALID and writes may be ignored or rejected. + * eth_tp_mdix: Ethernet twisted-pair MDI(-X) status; one of + * ETH_TP_MDI_*. If the status is unknown or not applicable, the + * value will be ETH_TP_MDI_INVALID. Read-only. + * eth_tp_mdix_ctrl: Ethernet twisted pair MDI(-X) control; one of + * ETH_TP_MDI_*. If MDI(-X) control is not implemented, reads + * yield ETH_TP_MDI_INVALID and writes may be ignored or rejected. * When written successfully, the link should be renegotiated if * necessary. - * @lp_advertising: Bitmask of %ADVERTISED_* flags for the link modes + * lp_advertising: Bitmask of ADVERTISED_* flags for the link modes * and other link features that the link partner advertised * through autonegotiation; 0 if unknown or not applicable. * Read-only. * - * The link speed in Mbps is split between @speed and @speed_hi. Use + * The link speed in Mbps is split between speed and speed_hi. Use * the ethtool_cmd_speed() and ethtool_cmd_speed_set() functions to * access it. * - * If autonegotiation is disabled, the speed and @duplex represent the + * If autonegotiation is disabled, the speed and duplex represent the * fixed link mode and are writable if the driver supports multiple * link modes. If it is enabled then they are read-only; if the link * is up they represent the negotiated link mode; if the link is down, - * the speed is 0, %SPEED_UNKNOWN or the highest enabled speed and - * @duplex is %DUPLEX_UNKNOWN or the best enabled duplex mode. + * the speed is 0, SPEED_UNKNOWN or the highest enabled speed and + * duplex is DUPLEX_UNKNOWN or the best enabled duplex mode. * * Some hardware interfaces may have multiple PHYs and/or physical * connectors fitted or do not allow the driver to detect which are - * fitted. For these interfaces @port and/or @phy_address may be - * writable, possibly dependent on @autoneg being %AUTONEG_DISABLE. + * fitted. For these interfaces port and/or phy_address may be + * writable, possibly dependent on autoneg being AUTONEG_DISABLE. * Otherwise, attempts to write different values may be ignored or * rejected. * * Users should assume that all fields not marked read-only are * writable and subject to validation by the driver. They should use - * %ETHTOOL_GSET to get the current values before making specific - * changes and then applying them with %ETHTOOL_SSET. + * ETHTOOL_GSET to get the current values before making specific + * changes and then applying them with ETHTOOL_SSET. * * Deprecated fields should be ignored by both users and drivers. **/ diff --git a/include/nuttx/mmcsd.h b/include/nuttx/mmcsd.h index bd5dfb4413..c3282174a2 100644 --- a/include/nuttx/mmcsd.h +++ b/include/nuttx/mmcsd.h @@ -111,9 +111,9 @@ struct mmc_ioc_cmd }; /* struct mmc_ioc_multi_cmd - multi command information - * @num_of_cmds: Number of commands to send. Must be equal to or less than + * num_of_cmds: Number of commands to send. Must be equal to or less than * MMC_IOC_MAX_CMDS. - * @cmds: Array of commands with length equal to 'num_of_cmds' + * cmds: Array of commands with length equal to 'num_of_cmds' */ struct mmc_ioc_multi_cmd diff --git a/include/nuttx/reset/reset.h b/include/nuttx/reset/reset.h index 7eb7e2d256..f01bc4b11d 100644 --- a/include/nuttx/reset/reset.h +++ b/include/nuttx/reset/reset.h @@ -38,17 +38,17 @@ struct reset_controller_dev; /* struct reset_control - a reset control - * @rcdev: A pointer to the reset controller device + * rcdev: A pointer to the reset controller device * this reset control belongs to - * @list: List entry for the rcdev's reset controller list - * @id: ID of the reset controller in the reset + * list: List entry for the rcdev's reset controller list + * id: ID of the reset controller in the reset * controller device - * @refcnt: Number of gets of this reset_control - * @acquired: Only one reset_control may be acquired for a given rcdev and + * refcnt: Number of gets of this reset_control + * acquired: Only one reset_control may be acquired for a given rcdev and * id. - * @shared: Is this a shared (1), or an exclusive (0) reset_control? - * @deassert_cnt: Number of times this reset line has been deasserted - * @triggered_count: Number of times this reset line has been reset. + * shared: Is this a shared (1), or an exclusive (0) reset_control? + * deassert_cnt: Number of times this reset line has been deasserted + * triggered_count: Number of times this reset line has been reset. * Currently only used for shared resets, which means that the value will * be either 0 or 1. */ diff --git a/include/nuttx/sensors/mpu9250.h b/include/nuttx/sensors/mpu9250.h index 1cb8523e6b..61157b6db5 100644 --- a/include/nuttx/sensors/mpu9250.h +++ b/include/nuttx/sensors/mpu9250.h @@ -34,15 +34,15 @@ * Pre-processor Definitions ****************************************************************************/ -/* Creates a mask of @m bits, i.e. MASK(2) -> 00000011 */ +/* Creates a mask of m bits, i.e. MASK(2) -> 00000011 */ #define MASK(m) (BIT(m) - 1) -/* Masks and shifts @v into bit field @m */ +/* Masks and shifts v into bit field m */ #define TO_BITFIELD(m,v) (((v) & MASK(m ##_WIDTH)) << (m ##_SHIFT)) -/* Un-masks and un-shifts bit field @m from @v */ +/* Un-masks and un-shifts bit field m from v */ #define FROM_BITFIELD(m,v) (((v) >> (m ##_SHIFT)) & MASK(m ##_WIDTH)) diff --git a/include/nuttx/tee.h b/include/nuttx/tee.h index a1ddf711b8..5a32c0d594 100644 --- a/include/nuttx/tee.h +++ b/include/nuttx/tee.h @@ -43,8 +43,7 @@ * Pre-processor Definitions ****************************************************************************/ -/** - * This file describes the API provided by a TEE driver to user space. +/* This file describes the API provided by a TEE driver to user space. * * Each TEE driver defines a TEE specific protocol which is used for the * data passed back and forth using TEE_IOC_CMD. @@ -64,28 +63,23 @@ #define TEE_MEMREF_NULL ((uint64_t)-1) /* NULL MemRef Buffer */ -/** - * TEE Implementation ID - */ +/* TEE Implementation ID */ #define TEE_IMPL_ID_OPTEE 1 #define TEE_IMPL_ID_AMDTEE 2 -/** - * OP-TEE specific capabilities - */ +/* OP-TEE specific capabilities */ #define TEE_OPTEE_CAP_TZ (1 << 0) -/** - * struct tee_ioctl_version_data - TEE version - * @impl_id: [out] TEE implementation id - * @impl_caps: [out] Implementation specific capabilities - * @gen_caps: [out] Generic capabilities, defined by TEE_GEN_CAPS_* above +/* struct tee_ioctl_version_data - TEE version + * impl_id: [out] TEE implementation id + * impl_caps: [out] Implementation specific capabilities + * gen_caps: [out] Generic capabilities, defined by TEE_GEN_CAPS_* above * - * Identifies the TEE implementation, @impl_id is one of TEE_IMPL_ID_* above. - * @impl_caps is implementation specific, for example TEE_OPTEE_CAP_* - * is valid when @impl_id == TEE_IMPL_ID_OPTEE. + * Identifies the TEE implementation, impl_id is one of TEE_IMPL_ID_* above. + * impl_caps is implementation specific, for example TEE_OPTEE_CAP_* + * is valid when impl_id == TEE_IMPL_ID_OPTEE. */ struct tee_ioctl_version_data @@ -95,19 +89,17 @@ struct tee_ioctl_version_data uint32_t gen_caps; }; -/** - * TEE_IOC_VERSION - query version of TEE +/* TEE_IOC_VERSION - query version of TEE * * Takes a tee_ioctl_version_data struct and returns with the TEE version * data filled in. */ #define TEE_IOC_VERSION _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 0) -/** - * struct tee_ioctl_shm_alloc_data - Shared memory allocate argument - * @size: [in/out] Size of shared memory to allocate - * @flags: [in/out] Flags to/from allocation. - * @id: [out] Identifier of the shared memory +/* struct tee_ioctl_shm_alloc_data - Shared memory allocate argument + * size: [in/out] Size of shared memory to allocate + * flags: [in/out] Flags to/from allocation. + * id: [out] Identifier of the shared memory * * The flags field should currently be zero as input. Updated by the call * with actual flags as defined by TEE_IOCTL_SHM_* above. @@ -121,8 +113,7 @@ struct tee_ioctl_shm_alloc_data int32_t id; }; -/** - * TEE_IOC_SHM_ALLOC - allocate shared memory +/* TEE_IOC_SHM_ALLOC - allocate shared memory * * Allocates shared memory between the user space process and secure OS. * @@ -135,12 +126,11 @@ struct tee_ioctl_shm_alloc_data #define TEE_IOC_SHM_ALLOC _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 1) -/** - * struct tee_ioctl_shm_register_fd_data - Shared memory registering argument - * @fd: [in] file descriptor identifying the shared memory - * @size: [out] Size of shared memory to allocate - * @flags: [in] Flags to/from allocation. - * @id: [out] Identifier of the shared memory +/* struct tee_ioctl_shm_register_fd_data - Shared memory registering argument + * fd: [in] file descriptor identifying the shared memory + * size: [out] Size of shared memory to allocate + * flags: [in] Flags to/from allocation. + * id: [out] Identifier of the shared memory * * The flags field should currently be zero as input. Updated by the call * with actual flags as defined by TEE_IOCTL_SHM_* above. @@ -155,22 +145,17 @@ struct tee_ioctl_shm_register_fd_data int32_t id; }; -/** - * Attributes for struct tee_ioctl_param, selects field in the union - */ +/* Attributes for struct tee_ioctl_param, selects field in the union */ #define TEE_IOCTL_PARAM_ATTR_TYPE_NONE 0 /* parameter not used */ -/** - * These defines value parameters (struct tee_ioctl_param_value) - */ +/* These defines value parameters (struct tee_ioctl_param_value) */ #define TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT 1 #define TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT 2 #define TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INOUT 3 /* input and output */ -/** - * These defines shared memory reference parameters (struct +/* These defines shared memory reference parameters (struct * tee_ioctl_param_memref) */ @@ -178,9 +163,7 @@ struct tee_ioctl_shm_register_fd_data #define TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT 6 #define TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT 7 /* input and output */ -/** - * Mask for the type part of the attribute, leaves room for more types - */ +/* Mask for the type part of the attribute, leaves room for more types */ #define TEE_IOCTL_PARAM_ATTR_TYPE_MASK 0xff @@ -192,8 +175,7 @@ struct tee_ioctl_shm_register_fd_data #define TEE_IOCTL_PARAM_ATTR_MASK \ (TEE_IOCTL_PARAM_ATTR_TYPE_MASK | TEE_IOCTL_PARAM_ATTR_META) -/** - * Matches TEEC_LOGIN_* in GP TEE Client API +/* Matches TEEC_LOGIN_* in GP TEE Client API * Are only defined for GP compliant TEEs */ @@ -204,8 +186,7 @@ struct tee_ioctl_shm_register_fd_data #define TEE_IOCTL_LOGIN_USER_APPLICATION 5 #define TEE_IOCTL_LOGIN_GROUP_APPLICATION 6 -/** - * Disallow user-space to use GP implementation specific login +/* Disallow user-space to use GP implementation specific login * method range (0x80000000 - 0xBFFFFFFF). This range is rather * being reserved for REE kernel clients or TEE implementation. */ @@ -217,24 +198,23 @@ struct tee_ioctl_shm_register_fd_data #define TEE_IOCTL_LOGIN_REE_KERNEL 0x80000000 -/** - * struct tee_ioctl_param - parameter - * @attr: attributes - * @a: if a memref, offset into the shared memory object, else a value +/* struct tee_ioctl_param - parameter + * attr: attributes + * a: if a memref, offset into the shared memory object, else a value * parameter - * @b: if a memref, size of the buffer, else a value parameter - * @c: if a memref, shared memory identifier, else a value parameter + * b: if a memref, size of the buffer, else a value parameter + * c: if a memref, shared memory identifier, else a value parameter * - * @attr & TEE_PARAM_ATTR_TYPE_MASK indicates if memref or value is used in + * attr & TEE_PARAM_ATTR_TYPE_MASK indicates if memref or value is used in * the union. TEE_PARAM_ATTR_TYPE_VALUE_* indicates value and * TEE_PARAM_ATTR_TYPE_MEMREF_* indicates memref. TEE_PARAM_ATTR_TYPE_NONE * indicates that none of the members are used. * * Shared memory is allocated with TEE_IOC_SHM_ALLOC which returns an * identifier representing the shared memory object. A memref can reference - * a part of a shared memory by specifying an offset (@a) and size (@b) of + * a part of a shared memory by specifying an offset (a) and size (b) of * the object. To supply the entire shared memory object set the offset - * (@a) to 0 and size (@b) to the previously returned size of the object. + * (a) to 0 and size (b) to the previously returned size of the object. */ struct tee_ioctl_param @@ -247,16 +227,15 @@ struct tee_ioctl_param #define TEE_IOCTL_UUID_LEN 16 -/** - * struct tee_ioctl_open_session_arg - Open session argument - * @uuid: [in] UUID of the Trusted Application - * @clnt_uuid: [in] UUID of client - * @clnt_login: [in] Login class of client, TEE_IOCTL_LOGIN_* above - * @cancel_id: [in] Cancellation id, a unique value to identify this request - * @session: [out] Session id - * @ret: [out] return value - * @ret_origin [out] origin of the return value - * @num_params [in] number of parameters following this struct +/* struct tee_ioctl_open_session_arg - Open session argument + * uuid: [in] UUID of the Trusted Application + * clnt_uuid: [in] UUID of client + * clnt_login: [in] Login class of client, TEE_IOCTL_LOGIN_* above + * cancel_id: [in] Cancellation id, a unique value to identify this request + * session: [out] Session id + * ret: [out] return value + * ret_origin [out] origin of the return value + * num_params [in] number of parameters following this struct */ struct tee_ioctl_open_session_arg @@ -275,8 +254,7 @@ struct tee_ioctl_open_session_arg struct tee_ioctl_param params[]; }; -/** - * TEE_IOC_OPEN_SESSION - opens a session to a Trusted Application +/* TEE_IOC_OPEN_SESSION - opens a session to a Trusted Application * * Takes a struct tee_ioctl_buf_data which contains a struct * tee_ioctl_open_session_arg followed by any array of struct @@ -285,15 +263,14 @@ struct tee_ioctl_open_session_arg #define TEE_IOC_OPEN_SESSION _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 2) -/** - * struct tee_ioctl_invoke_func_arg - Invokes a function in a Trusted +/* struct tee_ioctl_invoke_func_arg - Invokes a function in a Trusted * Application - * @func: [in] Trusted Application function, specific to the TA - * @session: [in] Session id - * @cancel_id: [in] Cancellation id, a unique value to identify this request - * @ret: [out] return value - * @ret_origin [out] origin of the return value - * @num_params [in] number of parameters following this struct + * func: [in] Trusted Application function, specific to the TA + * session: [in] Session id + * cancel_id: [in] Cancellation id, a unique value to identify this request + * ret: [out] return value + * ret_origin [out] origin of the return value + * num_params [in] number of parameters following this struct */ struct tee_ioctl_invoke_arg @@ -310,8 +287,7 @@ struct tee_ioctl_invoke_arg struct tee_ioctl_param params[]; }; -/** - * TEE_IOC_INVOKE - Invokes a function in a Trusted Application +/* TEE_IOC_INVOKE - Invokes a function in a Trusted Application * * Takes a struct tee_ioctl_buf_data which contains a struct * tee_invoke_func_arg followed by any array of struct tee_param @@ -319,10 +295,9 @@ struct tee_ioctl_invoke_arg #define TEE_IOC_INVOKE _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 3) -/** - * struct tee_ioctl_cancel_arg - Cancels an open session or invoke ioctl - * @cancel_id: [in] Cancellation id, a unique value to identify this request - * @session: [in] Session id, if the session is opened, else set to 0 +/* struct tee_ioctl_cancel_arg - Cancels an open session or invoke ioctl + * cancel_id: [in] Cancellation id, a unique value to identify this request + * session: [in] Session id, if the session is opened, else set to 0 */ struct tee_ioctl_cancel_arg @@ -331,14 +306,12 @@ struct tee_ioctl_cancel_arg uint32_t session; }; -/** - * TEE_IOC_CANCEL - Cancels an open session or invoke - */ +/* TEE_IOC_CANCEL - Cancels an open session or invoke */ #define TEE_IOC_CANCEL _IOC(TEE_IOC_MAGIC << 4, TEE_IOC_BASE + 0) -/** - * struct tee_ioctl_close_session_arg - Closes an open session - * @session: [in] Session id + +/* struct tee_ioctl_close_session_arg - Closes an open session + * session: [in] Session id */ struct tee_ioctl_close_session_arg @@ -346,20 +319,17 @@ struct tee_ioctl_close_session_arg uint32_t session; }; -/** - * TEE_IOC_CLOSE_SESSION - Closes a session - */ +/* TEE_IOC_CLOSE_SESSION - Closes a session */ #define TEE_IOC_CLOSE_SESSION _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 5) -/** - * struct tee_iocl_supp_recv_arg - Receive a request for a supplicant +/* struct tee_iocl_supp_recv_arg - Receive a request for a supplicant * function - * @func: [in] supplicant function - * @num_params [in/out] number of parameters following this struct + * func: [in] supplicant function + * num_params [in/out] number of parameters following this struct * - * @num_params is the number of params that tee-supplicant has room to - * receive when input, @num_params is the number of actual params + * num_params is the number of params that tee-supplicant has room to + * receive when input, num_params is the number of actual params * tee-supplicant receives when output. */ @@ -373,8 +343,7 @@ struct tee_iocl_supp_recv_arg struct tee_ioctl_param params[]; }; -/** - * TEE_IOC_SUPPL_RECV - Receive a request for a supplicant function +/* TEE_IOC_SUPPL_RECV - Receive a request for a supplicant function * * Takes a struct tee_ioctl_buf_data which contains a struct * tee_iocl_supp_recv_arg followed by any array of struct tee_param @@ -382,10 +351,9 @@ struct tee_iocl_supp_recv_arg #define TEE_IOC_SUPPL_RECV _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 6) -/** - * struct tee_iocl_supp_send_arg - Send a response to a received request - * @ret: [out] return value - * @num_params [in] number of parameters following this struct +/* struct tee_iocl_supp_send_arg - Send a response to a received request + * ret: [out] return value + * num_params [in] number of parameters following this struct */ struct tee_iocl_supp_send_arg @@ -398,8 +366,7 @@ struct tee_iocl_supp_send_arg struct tee_ioctl_param params[]; }; -/** - * TEE_IOC_SUPPL_SEND - Receive a request for a supplicant function +/* TEE_IOC_SUPPL_SEND - Receive a request for a supplicant function * * Takes a struct tee_ioctl_buf_data which contains a struct * tee_iocl_supp_send_arg followed by any array of struct tee_param @@ -407,12 +374,11 @@ struct tee_iocl_supp_send_arg #define TEE_IOC_SUPPL_SEND _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 7) -/** - * struct tee_ioctl_shm_register_data - Shared memory register argument - * @addr: [in] Start address of shared memory to register - * @length: [in/out] Length of shared memory to register - * @flags: [in/out] Flags to/from registration. - * @id: [out] Identifier of the shared memory +/* struct tee_ioctl_shm_register_data - Shared memory register argument + * addr: [in] Start address of shared memory to register + * length: [in/out] Length of shared memory to register + * flags: [in/out] Flags to/from registration. + * id: [out] Identifier of the shared memory * * The flags field should currently be zero as input. Updated by the call * with actual flags as defined by TEE_IOCTL_SHM_* above. @@ -427,8 +393,7 @@ struct tee_ioctl_shm_register_data int32_t id; }; -/** - * TEE_IOC_SHM_REGISTER_FD - register a shared memory from a file descriptor +/* TEE_IOC_SHM_REGISTER_FD - register a shared memory from a file descriptor * * Returns a file descriptor on success or < 0 on failure * @@ -438,10 +403,9 @@ struct tee_ioctl_shm_register_data #define TEE_IOC_SHM_REGISTER_FD _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 8) -/** - * struct tee_ioctl_buf_data - Variable sized buffer - * @buf_ptr: [in] A __user pointer to a buffer - * @buf_len: [in] Length of the buffer above +/* struct tee_ioctl_buf_data - Variable sized buffer + * buf_ptr: [in] A __user pointer to a buffer + * buf_len: [in] Length of the buffer above * * Used as argument for TEE_IOC_OPEN_SESSION, TEE_IOC_INVOKE, * TEE_IOC_SUPPL_RECV, and TEE_IOC_SUPPL_SEND below. @@ -453,8 +417,7 @@ struct tee_ioctl_buf_data uint64_t buf_len; }; -/** - * TEE_IOC_SHM_REGISTER - Register shared memory argument +/* TEE_IOC_SHM_REGISTER - Register shared memory argument * * Registers shared memory between the user space process and secure OS. * @@ -464,8 +427,8 @@ struct tee_ioctl_buf_data */ #define TEE_IOC_SHM_REGISTER _IOC(TEE_IOC_MAGIC << 8, TEE_IOC_BASE + 9) -/** - * Five syscalls are used when communicating with the TEE driver. + +/* Five syscalls are used when communicating with the TEE driver. * open(): opens the device associated with the driver * ioctl(): as described above operating on the file descriptor from open() * close(): two cases diff --git a/include/nuttx/wireless/bluetooth/bt_uuid.h b/include/nuttx/wireless/bluetooth/bt_uuid.h index beb35b862a..b8aa0f5109 100644 --- a/include/nuttx/wireless/bluetooth/bt_uuid.h +++ b/include/nuttx/wireless/bluetooth/bt_uuid.h @@ -44,170 +44,170 @@ * Pre-processor Definitions ****************************************************************************/ -/** @def BBT_UUID_GAP - * @brief Generic Access +/* BBT_UUID_GAP + * Generic Access */ #define BT_UUID_GAP 0x1800 -/** @def BBT_UUID_GATT - * @brief Generic Attribute +/* BBT_UUID_GATT + * Generic Attribute */ #define BT_UUID_GATT 0x1801 -/** @def BBT_UUID_CTS - * @brief Current Time Service +/* BBT_UUID_CTS + * Current Time Service */ #define BT_UUID_CTS 0x1805 -/** @def BBT_UUID_DIS - * @brief Device Information Service +/* BBT_UUID_DIS + * Device Information Service */ #define BT_UUID_DIS 0x180a -/** @def BBT_UUID_HRS - * @brief Heart Rate Service +/* BBT_UUID_HRS + * Heart Rate Service */ #define BT_UUID_HRS 0x180d -/** @def BBT_UUID_BAS - * @brief Battery Service +/* BBT_UUID_BAS + * Battery Service */ #define BT_UUID_BAS 0x180f -/** @def BT_UUID_GATT_PRIMARY - * @brief GATT Primary Service +/* BT_UUID_GATT_PRIMARY + * GATT Primary Service */ #define BT_UUID_GATT_PRIMARY 0x2800 -/** @def BT_UUID_GATT_SECONDARY - * @brief GATT Secondary Service +/* BT_UUID_GATT_SECONDARY + * GATT Secondary Service */ #define BT_UUID_GATT_SECONDARY 0x2801 -/** @def BT_UUID_GATT_INCLUDE - * @brief GATT Include Service +/* BT_UUID_GATT_INCLUDE + * GATT Include Service */ #define BT_UUID_GATT_INCLUDE 0x2802 -/** @def BT_UUID_GATT_CHRC - * @brief GATT Characteristic +/* BT_UUID_GATT_CHRC + * GATT Characteristic */ #define BT_UUID_GATT_CHRC 0x2803 -/** @def BT_UUID_GATT_CEP - * @brief GATT Characteristic Extended Properties +/* BT_UUID_GATT_CEP + * GATT Characteristic Extended Properties */ #define BT_UUID_GATT_CEP 0x2900 -/** @def BT_UUID_GATT_CUD - * @brief GATT Characteristic User Description +/* BT_UUID_GATT_CUD + * GATT Characteristic User Description */ #define BT_UUID_GATT_CUD 0x2901 -/** @def BT_UUID_GATT_CCC - * @brief GATT Client Characteristic Configuration +/* BT_UUID_GATT_CCC + * GATT Client Characteristic Configuration */ #define BT_UUID_GATT_CCC 0x2902 -/** @def BT_UUID_GAP_DEVICE_NAME - * @brief GAP Characteristic Device Name +/* BT_UUID_GAP_DEVICE_NAME + * GAP Characteristic Device Name */ #define BT_UUID_GAP_DEVICE_NAME 0x2a00 -/** @def BT_UUID_GAP_APPEARANCE - * @brief GAP Characteristic Appearance +/* BT_UUID_GAP_APPEARANCE + * GAP Characteristic Appearance */ #define BT_UUID_GAP_APPEARANCE 0x2a01 -/** @def BT_UUID_BAS_BATTERY_LEVEL - * @brief BAS Characteristic Battery Level +/* BT_UUID_BAS_BATTERY_LEVEL + * BAS Characteristic Battery Level */ #define BT_UUID_BAS_BATTERY_LEVEL 0x2a19 -/** @def BT_UUID_DIS_SYSTEM_ID - * @brief DIS Characteristic System ID +/* BT_UUID_DIS_SYSTEM_ID + * DIS Characteristic System ID */ #define BT_UUID_DIS_SYSTEM_ID 0x2a23 -/** @def BT_UUID_DIS_MODEL_NUMBER_STRING - * @brief DIS Characteristic Model Number String +/* BT_UUID_DIS_MODEL_NUMBER_STRING + * DIS Characteristic Model Number String */ #define BT_UUID_DIS_MODEL_NUMBER_STRING 0x2a24 -/** @def BT_UUID_DIS_SERIAL_NUMBER_STRING - * @brief DIS Characteristic Serial Number String +/* BT_UUID_DIS_SERIAL_NUMBER_STRING + * DIS Characteristic Serial Number String */ #define BT_UUID_DIS_SERIAL_NUMBER_STRING 0x2a25 -/** @def BT_UUID_DIS_FIRMWARE_REVISION_STRING - * @brief DIS Characteristic Firmware Revision String +/* BT_UUID_DIS_FIRMWARE_REVISION_STRING + * DIS Characteristic Firmware Revision String */ #define BT_UUID_DIS_FIRMWARE_REVISION_STRING 0x2a26 -/** @def BT_UUID_DIS_HARDWARE_REVISION_STRING - * @brief DIS Characteristic Hardware Revision String +/* BT_UUID_DIS_HARDWARE_REVISION_STRING + * DIS Characteristic Hardware Revision String */ #define BT_UUID_DIS_HARDWARE_REVISION_STRING 0x2a27 -/** @def BT_UUID_DIS_SOFTWARE_REVISION_STRING - * @brief DIS Characteristic Software Revision String +/* BT_UUID_DIS_SOFTWARE_REVISION_STRING + * DIS Characteristic Software Revision String */ #define BT_UUID_DIS_SOFTWARE_REVISION_STRING 0x2a28 -/** @def BT_UUID_DIS_MANUFACTURER_NAME_STRING - * @brief DIS Characteristic Manufacturer Name String +/* BT_UUID_DIS_MANUFACTURER_NAME_STRING + * DIS Characteristic Manufacturer Name String */ #define BT_UUID_DIS_MANUFACTURER_NAME_STRING 0x2a29 -/** @def BT_UUID_DIS_PNP_ID - * @brief DIS Characteristic PnP ID +/* BT_UUID_DIS_PNP_ID + * DIS Characteristic PnP ID */ #define BT_UUID_DIS_PNP_ID 0x2a50 -/** @def BT_UUID_CTS_CURRENT_TIME - * @brief CTS Characteristic Current Time +/* BT_UUID_CTS_CURRENT_TIME + * CTS Characteristic Current Time */ #define BT_UUID_CTS_CURRENT_TIME 0x2a2b -/** @def BT_UUID_HR_MEASUREMENT - * @brief HRS Characteristic Measurement Interval +/* BT_UUID_HR_MEASUREMENT + * HRS Characteristic Measurement Interval */ #define BT_UUID_HRS_MEASUREMENT 0x2a37 -/** @def BT_UUID_HRS_BODY_SENSOR - * @brief HRS Characteristic Body Sensor Location +/* BT_UUID_HRS_BODY_SENSOR + * HRS Characteristic Body Sensor Location */ #define BT_UUID_HRS_BODY_SENSOR 0x2a38 -/** @def BT_UUID_HR_CONTROL_POINT - * @brief HRS Characteristic Control Point +/* BT_UUID_HR_CONTROL_POINT + * HRS Characteristic Control Point */ #define BT_UUID_HRS_CONTROL_POINT 0x2a39 diff --git a/include/nuttx/wireless/ieee80211/ieee80211.h b/include/nuttx/wireless/ieee80211/ieee80211.h index a7db43a830..f21372e0c9 100644 --- a/include/nuttx/wireless/ieee80211/ieee80211.h +++ b/include/nuttx/wireless/ieee80211/ieee80211.h @@ -404,7 +404,7 @@ struct ieee80211_qos_hdr }; /* ieee80211_has_tods - check if IEEE80211_FCTL_TODS is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_tods(uint16_t fc) @@ -413,7 +413,7 @@ static inline bool ieee80211_has_tods(uint16_t fc) } /* ieee80211_has_fromds - check if IEEE80211_FCTL_FROMDS is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_fromds(uint16_t fc) @@ -423,7 +423,7 @@ static inline bool ieee80211_has_fromds(uint16_t fc) /* ieee80211_has_a4 - check if IEEE80211_FCTL_TODS and * IEEE80211_FCTL_FROMDS are set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_a4(uint16_t fc) @@ -433,7 +433,7 @@ static inline bool ieee80211_has_a4(uint16_t fc) } /* ieee80211_has_morefrags - check if IEEE80211_FCTL_MOREFRAGS is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_morefrags(uint16_t fc) @@ -442,7 +442,7 @@ static inline bool ieee80211_has_morefrags(uint16_t fc) } /* ieee80211_has_retry - check if IEEE80211_FCTL_RETRY is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_retry(uint16_t fc) @@ -451,7 +451,7 @@ static inline bool ieee80211_has_retry(uint16_t fc) } /* ieee80211_has_pm - check if IEEE80211_FCTL_PM is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_pm(uint16_t fc) @@ -460,7 +460,7 @@ static inline bool ieee80211_has_pm(uint16_t fc) } /* ieee80211_has_moredata - check if IEEE80211_FCTL_MOREDATA is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_moredata(uint16_t fc) @@ -469,7 +469,7 @@ static inline bool ieee80211_has_moredata(uint16_t fc) } /* ieee80211_has_protected - check if IEEE80211_FCTL_PROTECTED is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_protected(uint16_t fc) @@ -478,7 +478,7 @@ static inline bool ieee80211_has_protected(uint16_t fc) } /* ieee80211_has_order - check if IEEE80211_FCTL_ORDER is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_has_order(uint16_t fc) @@ -487,7 +487,7 @@ static inline bool ieee80211_has_order(uint16_t fc) } /* ieee80211_is_mgmt - check if type is IEEE80211_FTYPE_MGMT - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_mgmt(uint16_t fc) @@ -497,7 +497,7 @@ static inline bool ieee80211_is_mgmt(uint16_t fc) } /* ieee80211_is_ctl - check if type is IEEE80211_FTYPE_CTL - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_ctl(uint16_t fc) @@ -507,7 +507,7 @@ static inline bool ieee80211_is_ctl(uint16_t fc) } /* ieee80211_is_data - check if type is IEEE80211_FTYPE_DATA - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_data(uint16_t fc) @@ -517,7 +517,7 @@ static inline bool ieee80211_is_data(uint16_t fc) } /* ieee80211_is_ext - check if type is IEEE80211_FTYPE_EXT - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_ext(uint16_t fc) @@ -528,7 +528,7 @@ static inline bool ieee80211_is_ext(uint16_t fc) /* ieee80211_is_data_qos - check if type is IEEE80211_FTYPE_DATA * and IEEE80211_STYPE_QOS_DATA is set - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_data_qos(uint16_t fc) @@ -544,7 +544,7 @@ static inline bool ieee80211_is_data_qos(uint16_t fc) /* ieee80211_is_data_present - check if type is IEEE80211_FTYPE_DATA * and has data - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_data_present(uint16_t fc) @@ -559,7 +559,7 @@ static inline bool ieee80211_is_data_present(uint16_t fc) /* ieee80211_is_assoc_req - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_ASSOC_REQ - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_assoc_req(uint16_t fc) @@ -570,7 +570,7 @@ static inline bool ieee80211_is_assoc_req(uint16_t fc) /* ieee80211_is_assoc_resp - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_ASSOC_RESP - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_assoc_resp(uint16_t fc) @@ -581,7 +581,7 @@ static inline bool ieee80211_is_assoc_resp(uint16_t fc) /* ieee80211_is_reassoc_req - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_REASSOC_REQ - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_reassoc_req(uint16_t fc) @@ -592,7 +592,7 @@ static inline bool ieee80211_is_reassoc_req(uint16_t fc) /* ieee80211_is_reassoc_resp - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_REASSOC_RESP - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_reassoc_resp(uint16_t fc) @@ -603,7 +603,7 @@ static inline bool ieee80211_is_reassoc_resp(uint16_t fc) /* ieee80211_is_probe_req - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_PROBE_REQ - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_probe_req(uint16_t fc) @@ -614,7 +614,7 @@ static inline bool ieee80211_is_probe_req(uint16_t fc) /* ieee80211_is_probe_resp - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_PROBE_RESP - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_probe_resp(uint16_t fc) @@ -625,7 +625,7 @@ static inline bool ieee80211_is_probe_resp(uint16_t fc) /* ieee80211_is_beacon - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_BEACON - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_beacon(uint16_t fc) @@ -636,7 +636,7 @@ static inline bool ieee80211_is_beacon(uint16_t fc) /* ieee80211_is_s1g_beacon - check if IEEE80211_FTYPE_EXT && * IEEE80211_STYPE_S1G_BEACON - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_s1g_beacon(uint16_t fc) @@ -648,7 +648,7 @@ static inline bool ieee80211_is_s1g_beacon(uint16_t fc) /* ieee80211_next_tbtt_present - check if IEEE80211_FTYPE_EXT && * IEEE80211_STYPE_S1G_BEACON && IEEE80211_S1G_BCN_NEXT_TBTT - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_next_tbtt_present(uint16_t fc) @@ -660,7 +660,7 @@ static inline bool ieee80211_next_tbtt_present(uint16_t fc) /* ieee80211_is_s1g_short_beacon - check if next tbtt present bit is set. * Only true for S1G beacons when they're short. - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_s1g_short_beacon(uint16_t fc) @@ -669,7 +669,7 @@ static inline bool ieee80211_is_s1g_short_beacon(uint16_t fc) } /* ieee80211_is_atim - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_ATIM - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_atim(uint16_t fc) @@ -680,7 +680,7 @@ static inline bool ieee80211_is_atim(uint16_t fc) /* ieee80211_is_disassoc - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_DISASSOC - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_disassoc(uint16_t fc) @@ -690,7 +690,7 @@ static inline bool ieee80211_is_disassoc(uint16_t fc) } /* ieee80211_is_auth - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_AUTH - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_auth(uint16_t fc) @@ -701,7 +701,7 @@ static inline bool ieee80211_is_auth(uint16_t fc) /* ieee80211_is_deauth - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_DEAUTH - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_deauth(uint16_t fc) @@ -712,7 +712,7 @@ static inline bool ieee80211_is_deauth(uint16_t fc) /* ieee80211_is_action - check if IEEE80211_FTYPE_MGMT && * IEEE80211_STYPE_ACTION - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_action(uint16_t fc) @@ -723,7 +723,7 @@ static inline bool ieee80211_is_action(uint16_t fc) /* ieee80211_is_back_req - check if IEEE80211_FTYPE_CTL && * IEEE80211_STYPE_BACK_REQ - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_back_req(uint16_t fc) @@ -734,7 +734,7 @@ static inline bool ieee80211_is_back_req(uint16_t fc) /* ieee80211_is_back - check if IEEE80211_FTYPE_CTL && * IEEE80211_STYPE_BACK - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_back(uint16_t fc) @@ -745,7 +745,7 @@ static inline bool ieee80211_is_back(uint16_t fc) /* ieee80211_is_pspoll - check if IEEE80211_FTYPE_CTL && * IEEE80211_STYPE_PSPOLL - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_pspoll(uint16_t fc) @@ -755,7 +755,7 @@ static inline bool ieee80211_is_pspoll(uint16_t fc) } /* ieee80211_is_rts - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_RTS - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_rts(uint16_t fc) @@ -765,7 +765,7 @@ static inline bool ieee80211_is_rts(uint16_t fc) } /* ieee80211_is_cts - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_CTS - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_cts(uint16_t fc) @@ -775,7 +775,7 @@ static inline bool ieee80211_is_cts(uint16_t fc) } /* ieee80211_is_ack - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_ACK - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_ack(uint16_t fc) @@ -785,7 +785,7 @@ static inline bool ieee80211_is_ack(uint16_t fc) } /* ieee80211_is_cfend - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_CFEND - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_cfend(uint16_t fc) @@ -796,7 +796,7 @@ static inline bool ieee80211_is_cfend(uint16_t fc) /* ieee80211_is_cfendack - check if IEEE80211_FTYPE_CTL && * IEEE80211_STYPE_CFENDACK - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_cfendack(uint16_t fc) @@ -807,7 +807,7 @@ static inline bool ieee80211_is_cfendack(uint16_t fc) /* ieee80211_is_nullfunc - check if frame is a regular * (non-QoS) nullfunc frame - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_nullfunc(uint16_t fc) @@ -817,7 +817,7 @@ static inline bool ieee80211_is_nullfunc(uint16_t fc) } /* ieee80211_is_qos_nullfunc - check if frame is a QoS nullfunc frame - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_qos_nullfunc(uint16_t fc) @@ -828,7 +828,7 @@ static inline bool ieee80211_is_qos_nullfunc(uint16_t fc) /* ieee80211_is_any_nullfunc - check if frame is regular or QoS * nullfunc frame - * @fc: frame control bytes in little-endian byteorder + * fc: frame control bytes in little-endian byteorder */ static inline bool ieee80211_is_any_nullfunc(uint16_t fc) @@ -837,7 +837,7 @@ static inline bool ieee80211_is_any_nullfunc(uint16_t fc) } /* ieee80211_is_bufferable_mmpdu - check if frame is bufferable MMPDU - * @fc: frame control field in little-endian byteorder + * fc: frame control field in little-endian byteorder */ static inline bool ieee80211_is_bufferable_mmpdu(uint16_t fc) @@ -853,7 +853,7 @@ static inline bool ieee80211_is_bufferable_mmpdu(uint16_t fc) } /* ieee80211_is_first_frag - check if IEEE80211_SCTL_FRAG is not set - * @seq_ctrl: frame sequence control bytes in little-endian byteorder + * seq_ctrl: frame sequence control bytes in little-endian byteorder */ static inline bool ieee80211_is_first_frag(uint16_t seq_ctrl) @@ -862,7 +862,7 @@ static inline bool ieee80211_is_first_frag(uint16_t seq_ctrl) } /* ieee80211_is_frag - check if a frame is a fragment - * @hdr: 802.11 header of the frame + * hdr: 802.11 header of the frame */ static inline bool ieee80211_is_frag(struct ieee80211_hdr *hdr) @@ -889,7 +889,7 @@ struct ieee80211s_hdr /* enum ieee80211_preq_flags - mesh PREQ element flags * - * @IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield + * IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield */ enum ieee80211_preq_flags @@ -899,8 +899,8 @@ enum ieee80211_preq_flags /* enum ieee80211_preq_target_flags - mesh PREQ element per target flags * - * @IEEE80211_PREQ_TO_FLAG: target only subfield - * @IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield + * IEEE80211_PREQ_TO_FLAG: target only subfield + * IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield */ enum ieee80211_preq_target_flags @@ -962,7 +962,7 @@ struct ieee80211_ext_chansw_ie }; /* struct ieee80211_sec_chan_offs_ie - secondary channel offset IE - * @sec_chan_offs: secondary channel offset, + * sec_chan_offs: secondary channel offset, * uses IEEE80211_HT_PARAM_CHA_SEC_* values here * This structure represents the "Secondary Channel Offset element" */ @@ -1030,12 +1030,12 @@ struct ieee80211_meshconf_ie /* enum mesh_config_capab_flags * Mesh Configuration IE capability field flags * - * @IEEE80211_MESHCONF_CAPAB_ACCEPT_PLINKS: STA is willing to establish + * IEEE80211_MESHCONF_CAPAB_ACCEPT_PLINKS: STA is willing to establish * additional mesh peerings with other mesh STAs - * @IEEE80211_MESHCONF_CAPAB_FORWARDING: the STA forwards MSDUs - * @IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING: TBTT adjustment procedure + * IEEE80211_MESHCONF_CAPAB_FORWARDING: the STA forwards MSDUs + * IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING: TBTT adjustment procedure * is ongoing - * @IEEE80211_MESHCONF_CAPAB_POWER_SAVE_LEVEL: + * IEEE80211_MESHCONF_CAPAB_POWER_SAVE_LEVEL: * STA is in deep sleep mode or has * neighbors in deep sleep mode */ @@ -1084,17 +1084,17 @@ enum ieee80211_ht_chanwidth_values }; /* enum ieee80211_opmode_bits - VHT operating mode field bits - * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK: channel width mask - * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ: 20 MHz channel width - * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ: 40 MHz channel width - * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_80MHZ: 80 MHz channel width - * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_160MHZ: 160 MHz or 80+80 MHz channel + * IEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK: channel width mask + * IEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ: 20 MHz channel width + * IEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ: 40 MHz channel width + * IEEE80211_OPMODE_NOTIF_CHANWIDTH_80MHZ: 80 MHz channel width + * IEEE80211_OPMODE_NOTIF_CHANWIDTH_160MHZ: 160 MHz or 80+80 MHz channel * width - * @IEEE80211_OPMODE_NOTIF_BW_160_80P80: 160 / 80+80 MHz indicator flag - * @IEEE80211_OPMODE_NOTIF_RX_NSS_MASK: number of spatial streams mask + * IEEE80211_OPMODE_NOTIF_BW_160_80P80: 160 / 80+80 MHz indicator flag + * IEEE80211_OPMODE_NOTIF_RX_NSS_MASK: number of spatial streams mask * (the NSS value is the value of this field + 1) - * @IEEE80211_OPMODE_NOTIF_RX_NSS_SHIFT: number of spatial streams shift - * @IEEE80211_OPMODE_NOTIF_RX_NSS_TYPE_BF: indicates streams in SU-MIMO PPDU + * IEEE80211_OPMODE_NOTIF_RX_NSS_SHIFT: number of spatial streams shift + * IEEE80211_OPMODE_NOTIF_RX_NSS_TYPE_BF: indicates streams in SU-MIMO PPDU * using a beamforming steering matrix */ @@ -1115,11 +1115,11 @@ enum ieee80211_vht_opmode_bits * These are defined in IEEE802.11-2016ah Table 10-20 * as BSS Channel Width * - * @IEEE80211_S1G_CHANWIDTH_1MHZ: 1MHz operating channel - * @IEEE80211_S1G_CHANWIDTH_2MHZ: 2MHz operating channel - * @IEEE80211_S1G_CHANWIDTH_4MHZ: 4MHz operating channel - * @IEEE80211_S1G_CHANWIDTH_8MHZ: 8MHz operating channel - * @IEEE80211_S1G_CHANWIDTH_16MHZ: 16MHz operating channel + * IEEE80211_S1G_CHANWIDTH_1MHZ: 1MHz operating channel + * IEEE80211_S1G_CHANWIDTH_2MHZ: 2MHz operating channel + * IEEE80211_S1G_CHANWIDTH_4MHZ: 4MHz operating channel + * IEEE80211_S1G_CHANWIDTH_8MHZ: 8MHz operating channel + * IEEE80211_S1G_CHANWIDTH_16MHZ: 16MHz operating channel */ enum ieee80211_s1g_chanwidth @@ -1709,12 +1709,12 @@ struct ieee80211_bar #define IEEE80211_HT_MCS_MASK_LEN 10 /* struct ieee80211_mcs_info - MCS information - * @rx_mask: RX mask - * @rx_highest: highest supported RX rate. If set represents + * rx_mask: RX mask + * rx_highest: highest supported RX rate. If set represents * the highest supported RX data rate in units of 1 Mbps. * If this field is 0 this value should not be used to * consider the highest RX data rate supported. - * @tx_params: TX parameters + * tx_params: TX parameters */ struct ieee80211_mcs_info @@ -1925,15 +1925,15 @@ struct ieee80211_ht_operation #define WLAN_HT_SMPS_CONTROL_DYNAMIC 3 /* struct ieee80211_vht_mcs_info - VHT MCS information - * @rx_mcs_map: RX MCS map 2 bits for each stream, total 8 streams - * @rx_highest: Indicates highest long GI VHT PPDU data rate + * rx_mcs_map: RX MCS map 2 bits for each stream, total 8 streams + * rx_highest: Indicates highest long GI VHT PPDU data rate * STA can receive. Rate expressed in units of 1 Mbps. * If this field is 0 this value should not be used to * consider the highest RX data rate supported. * The top 3 bits of this field indicate the Maximum NSTS,total * (a beamformee capability.) - * @tx_mcs_map: TX MCS map 2 bits for each stream, total 8 streams - * @tx_highest: Indicates highest long GI VHT PPDU data rate + * tx_mcs_map: TX MCS map 2 bits for each stream, total 8 streams + * tx_highest: Indicates highest long GI VHT PPDU data rate * STA can transmit. Rate expressed in units of 1 Mbps. * If this field is 0 this value should not be used to * consider the highest TX data rate supported. @@ -1960,14 +1960,14 @@ struct ieee80211_vht_mcs_info #define IEEE80211_VHT_EXT_NSS_BW_CAPABLE (1 << 13) /* enum ieee80211_vht_mcs_support - VHT MCS support definitions - * @IEEE80211_VHT_MCS_SUPPORT_0_7: MCSes 0-7 are supported for the + * IEEE80211_VHT_MCS_SUPPORT_0_7: MCSes 0-7 are supported for the * number of streams - * @IEEE80211_VHT_MCS_SUPPORT_0_8: MCSes 0-8 are supported - * @IEEE80211_VHT_MCS_SUPPORT_0_9: MCSes 0-9 are supported - * @IEEE80211_VHT_MCS_NOT_SUPPORTED: This number of streams isn't supported + * IEEE80211_VHT_MCS_SUPPORT_0_8: MCSes 0-8 are supported + * IEEE80211_VHT_MCS_SUPPORT_0_9: MCSes 0-9 are supported + * IEEE80211_VHT_MCS_NOT_SUPPORTED: This number of streams isn't supported * - * These definitions are used in each 2-bit subfield of the @rx_mcs_map - * and @tx_mcs_map fields of &struct ieee80211_vht_mcs_info, which are + * These definitions are used in each 2-bit subfield of the rx_mcs_map + * and tx_mcs_map fields of &struct ieee80211_vht_mcs_info, which are * both split into 8 subfields by number of streams. These values indicate * which MCSes are supported for the number of streams the value appears * for. @@ -1985,8 +1985,8 @@ enum ieee80211_vht_mcs_support * * This structure is the "VHT capabilities element" as * described in 802.11ac D3.0 8.4.2.160 - * @vht_cap_info: VHT capability info - * @supp_mcs: VHT MCS supported rates + * vht_cap_info: VHT capability info + * supp_mcs: VHT MCS supported rates */ struct ieee80211_vht_cap @@ -1995,13 +1995,12 @@ struct ieee80211_vht_cap struct ieee80211_vht_mcs_info supp_mcs; }; -/** - * enum ieee80211_vht_chanwidth - VHT channel width - * @IEEE80211_VHT_CHANWIDTH_USE_HT: use the HT operation IE to +/* enum ieee80211_vht_chanwidth - VHT channel width + * IEEE80211_VHT_CHANWIDTH_USE_HT: use the HT operation IE to * determine the channel width (20 or 40 MHz) - * @IEEE80211_VHT_CHANWIDTH_80MHZ: 80 MHz bandwidth - * @IEEE80211_VHT_CHANWIDTH_160MHZ: 160 MHz bandwidth - * @IEEE80211_VHT_CHANWIDTH_80P80MHZ: 80+80 MHz bandwidth + * IEEE80211_VHT_CHANWIDTH_80MHZ: 80 MHz bandwidth + * IEEE80211_VHT_CHANWIDTH_160MHZ: 160 MHz bandwidth + * IEEE80211_VHT_CHANWIDTH_80P80MHZ: 80+80 MHz bandwidth */ enum ieee80211_vht_chanwidth @@ -2016,10 +2015,10 @@ enum ieee80211_vht_chanwidth * * This structure is the "VHT operation element" as * described in 802.11ac D3.0 8.4.2.161 - * @chan_width: Operating channel width - * @center_freq_seg0_idx: center freq segment 0 index - * @center_freq_seg1_idx: center freq segment 1 index - * @basic_mcs_set: VHT Basic MCS rate set + * chan_width: Operating channel width + * center_freq_seg0_idx: center freq segment 0 index + * center_freq_seg1_idx: center freq segment 1 index + * basic_mcs_set: VHT Basic MCS rate set */ struct ieee80211_vht_operation @@ -2045,11 +2044,11 @@ struct ieee80211_he_cap_elem #define IEEE80211_TX_RX_MCS_NSS_DESC_MAX_LEN 5 /* enum ieee80211_he_mcs_support - HE MCS support definitions - * @IEEE80211_HE_MCS_SUPPORT_0_7: MCSes 0-7 are supported for the + * IEEE80211_HE_MCS_SUPPORT_0_7: MCSes 0-7 are supported for the * number of streams - * @IEEE80211_HE_MCS_SUPPORT_0_9: MCSes 0-9 are supported - * @IEEE80211_HE_MCS_SUPPORT_0_11: MCSes 0-11 are supported - * @IEEE80211_HE_MCS_NOT_SUPPORTED: This number of streams isn't supported + * IEEE80211_HE_MCS_SUPPORT_0_9: MCSes 0-9 are supported + * IEEE80211_HE_MCS_SUPPORT_0_11: MCSes 0-11 are supported + * IEEE80211_HE_MCS_NOT_SUPPORTED: This number of streams isn't supported * * These definitions are used in each 2-bit subfield of the rx_mcs_* * and tx_mcs_* fields of &struct ieee80211_he_mcs_nss_supp, which are @@ -2071,17 +2070,17 @@ enum ieee80211_he_mcs_support * This structure holds the data required for the Tx/Rx HE MCS NSS Support * Field described in P802.11ax_D2.0 section 9.4.2.237.4 * - * @rx_mcs_80: Rx MCS map 2 bits for each stream, total 8 streams, + * rx_mcs_80: Rx MCS map 2 bits for each stream, total 8 streams, * for channel widths less than 80MHz. - * @tx_mcs_80: Tx MCS map 2 bits for each stream, total 8 streams, + * tx_mcs_80: Tx MCS map 2 bits for each stream, total 8 streams, * for channel widths less than 80MHz. - * @rx_mcs_160: Rx MCS map 2 bits for each stream, total 8 streams, + * rx_mcs_160: Rx MCS map 2 bits for each stream, total 8 streams, * for channel width 160MHz. - * @tx_mcs_160: Tx MCS map 2 bits for each stream, total 8 streams, + * tx_mcs_160: Tx MCS map 2 bits for each stream, total 8 streams, * for channel width 160MHz. - * @rx_mcs_80p80: Rx MCS map 2 bits for each stream, total 8 streams, + * rx_mcs_80p80: Rx MCS map 2 bits for each stream, total 8 streams, * for channel width 80p80MHz. - * @tx_mcs_80p80: Tx MCS map 2 bits for each stream, total 8 streams, + * tx_mcs_80p80: Tx MCS map 2 bits for each stream, total 8 streams, * for channel width 80p80MHz. */ @@ -2106,7 +2105,7 @@ struct ieee80211_he_operation uint32_t he_oper_params; uint16_t he_mcs_nss_set; - /* Optional 0,1,3,4,5,7 or 8 bytes: depends on @he_oper_params */ + /* Optional 0,1,3,4,5,7 or 8 bytes: depends on he_oper_params */ uint8_t optional[]; }; @@ -2121,7 +2120,7 @@ struct ieee80211_he_spr { uint8_t he_sr_control; - /* Optional 0 to 19 bytes: depends on @he_sr_control */ + /* Optional 0 to 19 bytes: depends on he_sr_control */ uint8_t optional[]; }; @@ -2197,13 +2196,13 @@ struct ieee80211_mu_edca_param_set #define IEEE80211_VHT_CAP_EXT_NSS_BW_MASK 0xc0000000 /* ieee80211_get_vht_max_nss - return max NSS for a given bandwidth/MCS - * @cap: VHT capabilities of the peer - * @bw: bandwidth to use - * @mcs: MCS index to use - * @ext_nss_bw_capable: indicates whether or not the local transmitter + * cap: VHT capabilities of the peer + * bw: bandwidth to use + * mcs: MCS index to use + * ext_nss_bw_capable: indicates whether or not the local transmitter * (rate scaling algorithm) can deal with the new logic * (dot11VHTExtendedNSSBWCapable) - * @max_vht_nss: current maximum NSS as advertised by the STA in + * max_vht_nss: current maximum NSS as advertised by the STA in * operating mode notification, can be 0 in which case the * capability data will be used to derive this (from MCS support) * @@ -2561,11 +2560,11 @@ ieee80211_he_ppe_size(uint8_t ppe_thres_hdr, const uint8_t *phy_cap_info) #define IEEE80211_HE_OPERATION_BSS_COLOR_DISABLED 0x80000000 /* ieee80211_he_6ghz_oper - HE 6 GHz operation Information field - * @primary: primary channel - * @control: control flags - * @ccfs0: channel center frequency segment 0 - * @ccfs1: channel center frequency segment 1 - * @minrate: minimum rate (in 1 Mbps units) + * primary: primary channel + * control: control flags + * ccfs0: channel center frequency segment 0 + * ccfs1: channel center frequency segment 1 + * minrate: minimum rate (in 1 Mbps units) */ struct ieee80211_he_6ghz_oper @@ -2584,11 +2583,11 @@ struct ieee80211_he_6ghz_oper }; /* ieee80211_he_oper_size - calculate 802.11ax HE Operations IE size - * @he_oper_ie: byte data of the He Operations IE, stating from the byte + * he_oper_ie: byte data of the He Operations IE, stating from the byte * after the ext ID byte. It is assumed that he_oper_ie has at least * sizeof(struct ieee80211_he_operation) bytes, the caller must have * validated this. - * @return the actual size of the IE data (not including header), + * return the actual size of the IE data (not including header), * or 0 on error */ @@ -2622,10 +2621,10 @@ ieee80211_he_oper_size(const uint8_t *he_oper_ie) } /* ieee80211_he_6ghz_oper - obtain 6 GHz operation field - * @he_oper: HE operation element (must be pre-validated for size) - * but may be %NULL + * he_oper: HE operation element (must be pre-validated for size) + * but may be NULL * - * Return: a pointer to the 6 GHz operation field, or %NULL + * Return: a pointer to the 6 GHz operation field, or NULL */ static inline const struct ieee80211_he_6ghz_oper * @@ -2657,11 +2656,11 @@ ieee80211_he_6ghz_oper(const struct ieee80211_he_operation *he_oper) #define IEEE80211_HE_SPR_HESIGA_SR_VAL15_ALLOWED BIT(4) /* ieee80211_he_spr_size - calculate 802.11ax HE Spatial Reuse IE size - * @he_spr_ie: byte data of the He Spatial Reuse IE, stating from the byte + * he_spr_ie: byte data of the He Spatial Reuse IE, stating from the byte * after the ext ID byte. It is assumed that he_spr_ie has at least * sizeof(struct ieee80211_he_spr) bytes, the caller must have validated * this - * @return the actual size of the IE data (not including header), + * return the actual size of the IE data (not including header), * or 0 on error */ @@ -3491,31 +3490,31 @@ enum ieee80211_tdls_actioncode }; /* Extended Channel Switching capability to be set in the 1st byte of - * the @WLAN_EID_EXT_CAPABILITY information element + * the WLAN_EID_EXT_CAPABILITY information element */ #define WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING BIT(2) /* Multiple BSSID capability is set in the 6th bit of 3rd byte of the - * @WLAN_EID_EXT_CAPABILITY information element + * WLAN_EID_EXT_CAPABILITY information element */ #define WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT BIT(6) -/* TDLS capabilities in the 4th byte of @WLAN_EID_EXT_CAPABILITY */ +/* TDLS capabilities in the 4th byte of WLAN_EID_EXT_CAPABILITY */ #define WLAN_EXT_CAPA4_TDLS_BUFFER_STA BIT(4) #define WLAN_EXT_CAPA4_TDLS_PEER_PSM BIT(5) #define WLAN_EXT_CAPA4_TDLS_CHAN_SWITCH BIT(6) /* Interworking capabilities are set in 7th bit of 4th byte of the - * @WLAN_EID_EXT_CAPABILITY information element + * WLAN_EID_EXT_CAPABILITY information element */ #define WLAN_EXT_CAPA4_INTERWORKING_ENABLED BIT(7) /* TDLS capabililites to be enabled in the 5th byte of the - * @WLAN_EID_EXT_CAPABILITY information element + * WLAN_EID_EXT_CAPABILITY information element */ #define WLAN_EXT_CAPA5_TDLS_ENABLED BIT(5) @@ -3530,7 +3529,7 @@ enum ieee80211_tdls_actioncode #define WLAN_EXT_CAPA8_MAX_MSDU_IN_AMSDU_LSB BIT(7) #define WLAN_EXT_CAPA9_MAX_MSDU_IN_AMSDU_MSB BIT(0) -/* Fine Timing Measurement Initiator - bit 71 of @WLAN_EID_EXT_CAPABILITY +/* Fine Timing Measurement Initiator - bit 71 of WLAN_EID_EXT_CAPABILITY * information element */ @@ -3562,8 +3561,8 @@ enum ieee80211_tdls_actioncode /* enum ieee80211_mesh_sync_method - mesh synchronization method identifier * - * @IEEE80211_SYNC_METHOD_NEIGHBOR_OFFSET: the default synchronization method - * @IEEE80211_SYNC_METHOD_VENDOR: a vendor specific synchronization method + * IEEE80211_SYNC_METHOD_NEIGHBOR_OFFSET: the default synchronization method + * IEEE80211_SYNC_METHOD_VENDOR: a vendor specific synchronization method * that will be specified in a vendor specific information element */ @@ -3576,8 +3575,8 @@ enum ieee80211_mesh_sync_method /* enum ieee80211_mesh_path_protocol * mesh path selection protocol identifier * - * @IEEE80211_PATH_PROTOCOL_HWMP: the default path selection protocol - * @IEEE80211_PATH_PROTOCOL_VENDOR: a vendor specific protocol that will + * IEEE80211_PATH_PROTOCOL_HWMP: the default path selection protocol + * IEEE80211_PATH_PROTOCOL_VENDOR: a vendor specific protocol that will * be specified in a vendor specific information element */ @@ -3589,8 +3588,8 @@ enum ieee80211_mesh_path_protocol /* enum ieee80211_mesh_path_metric - mesh path selection metric identifier * - * @IEEE80211_PATH_METRIC_AIRTIME: the default path selection metric - * @IEEE80211_PATH_METRIC_VENDOR: a vendor specific metric that will be + * IEEE80211_PATH_METRIC_AIRTIME: the default path selection metric + * IEEE80211_PATH_METRIC_VENDOR: a vendor specific metric that will be * specified in a vendor specific information element */ @@ -3605,14 +3604,14 @@ enum ieee80211_mesh_path_metric * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA * mode * - * @IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default) - * @IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than + * IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default) + * IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than * this value - * @IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA + * IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA * supports the proactive PREQ with proactive PREP subfield set to 0 - * @IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA + * IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA * supports the proactive PREQ with proactive PREP subfield set to 1 - * @IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports + * IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports * the proactive RANN */ @@ -3703,8 +3702,8 @@ enum ieee80211_timeout_interval_type }; /* struct ieee80211_timeout_interval_ie - Timeout Interval element - * @type: type, see &enum ieee80211_timeout_interval_type - * @value: timeout interval value + * type: type, see &enum ieee80211_timeout_interval_type + * value: timeout interval value */ struct ieee80211_timeout_interval_ie @@ -3717,10 +3716,10 @@ struct ieee80211_timeout_interval_ie * * This structure refers to "BSS Max idle period element" * - * @max_idle_period: indicates the time period during which a station can + * max_idle_period: indicates the time period during which a station can * refrain from transmitting frames to its associated AP without being * disassociated. In units of 1000 TUs. - * @idle_options: indicates the options associated with the BSS idle + * idle_options: indicates the options associated with the BSS idle * capability as specified in &enum ieee80211_idle_options. */ @@ -3759,9 +3758,9 @@ enum ieee80211_sa_query_action * * This structure refers to "Multiple BSSID-index element" * - * @bssid_index: BSSID index - * @dtim_period: optional, overrides transmitted BSS dtim period - * @dtim_count: optional, overrides transmitted BSS dtim count + * bssid_index: BSSID index + * dtim_period: optional, overrides transmitted BSS dtim period + * dtim_count: optional, overrides transmitted BSS dtim count */ struct ieee80211_bssid_index @@ -3775,8 +3774,8 @@ struct ieee80211_bssid_index * * This structure refers to "Multiple BSSID Configuration element" * - * @bssid_count: total number of active BSSIDs in the set - * @profile_periodicity: the least number of beacon frames need to be + * bssid_count: total number of active BSSIDs in the set + * profile_periodicity: the least number of beacon frames need to be * received in order to discover all the nontransmitted BSSIDs in the set. */ @@ -3907,7 +3906,7 @@ struct ieee80211_he_6ghz_capa #define IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS 0x2000 /* ieee80211_get_qos_ctl - get pointer to qos control bytes - * @hdr: the frame + * hdr: the frame * * The qos ctrl bytes come after the frame_control, duration, seq_num * and 3 or 4 addresses of length ETH_ALEN. @@ -3924,7 +3923,7 @@ static inline uint8_t *ieee80211_get_qos_ctl(struct ieee80211_hdr *hdr) } /* ieee80211_get_tid - get qos TID - * @hdr: the frame + * hdr: the frame */ static inline uint8_t ieee80211_get_tid(struct ieee80211_hdr *hdr) @@ -3935,7 +3934,7 @@ static inline uint8_t ieee80211_get_tid(struct ieee80211_hdr *hdr) } /* ieee80211_get_SA - get pointer to SA - * @hdr: the frame + * hdr: the frame * * Given an 802.11 frame, this function returns the offset * to the source address (SA). It does not verify that the @@ -3954,7 +3953,7 @@ static inline uint8_t *ieee80211_get_sa(struct ieee80211_hdr *hdr) } /* ieee80211_get_DA - get pointer to DA - * @hdr: the frame + * hdr: the frame * * Given an 802.11 frame, this function returns the offset * to the destination address (DA). It does not verify that @@ -3973,7 +3972,7 @@ static inline uint8_t *ieee80211_get_da(struct ieee80211_hdr *hdr) /* _ieee80211_is_robust_mgmt_frame - check if frame is a robust management * frame - * @hdr: the frame (buffer must include at least the first octet of payload) + * hdr: the frame (buffer must include at least the first octet of payload) */ static inline bool _ieee80211_is_robust_mgmt_frame(struct ieee80211_hdr *hdr) diff --git a/include/nuttx/wireless/lte/lte.h b/include/nuttx/wireless/lte/lte.h index afc822a9d1..cea69d72ae 100644 --- a/include/nuttx/wireless/lte/lte.h +++ b/include/nuttx/wireless/lte/lte.h @@ -679,7 +679,7 @@ typedef struct lte_getpin uint8_t enable; /* PIN status. Refer to the this parameter only - * when enable is @ref LTE_ENABLE. + * when enable is LTE_ENABLE. */ uint8_t status; @@ -1144,7 +1144,7 @@ typedef struct lte_pdn uint8_t ipaddr_num; - /* IP address information. See @ref lte_ipaddr_t */ + /* IP address information. See lte_ipaddr_t */ lte_ipaddr_t address[LTE_PDN_IPADDR_MAX_COUNT]; @@ -1464,7 +1464,7 @@ struct ltefw_injectdata_s * - LTE_RESULT_ERROR * * [in] version : The version information of the modem. - * See @ref lte_version_t + * See lte_version_t */ typedef void (*get_ver_cb_t)(uint32_t result, lte_version_t *version); diff --git a/include/nuttx/wireless/wireless.h b/include/nuttx/wireless/wireless.h index 62c2f9f1a4..53b16e333d 100644 --- a/include/nuttx/wireless/wireless.h +++ b/include/nuttx/wireless/wireless.h @@ -461,8 +461,8 @@ struct iw_freq struct iw_quality { - uint8_t qual; /* link quality (%retries, SNR, - * %missed beacons or better...) */ + uint8_t qual; /* link quality (retries, SNR, + * missed beacons or better...) */ uint8_t level; /* signal level (dBm) */ uint8_t noise; /* noise level (dBm) */ uint8_t updated; /* Flags to know if updated */ diff --git a/include/sys/videoio.h b/include/sys/videoio.h index 81b1444b16..1576bd51c9 100644 --- a/include/sys/videoio.h +++ b/include/sys/videoio.h @@ -918,9 +918,9 @@ struct v4l2_pix_format typedef struct v4l2_pix_format v4l2_pix_format_t; /* struct v4l2_plane_pix_format - additional, per-plane format definition - * @sizeimage: maximum size in bytes required for data, for which + * sizeimage: maximum size in bytes required for data, for which * this plane will be used - * @bytesperline: distance in bytes between the leftmost pixels in two + * bytesperline: distance in bytes between the leftmost pixels in two * adjacent lines */ @@ -932,17 +932,17 @@ struct v4l2_plane_pix_format }; /* struct v4l2_pix_format_mplane - multiplanar format definition - * @width: image width in pixels - * @height: image height in pixels - * @pixelformat: little endian four character code (fourcc) - * @field: enum v4l2_field; field order (for interlaced video) - * @colorspace: enum v4l2_colorspace; supplemental to pixelformat - * @plane_fmt: per-plane information - * @num_planes: number of planes for this format - * @flags: format flags (V4L2_PIX_FMT_FLAG_*) - * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding - * @quantization: enum v4l2_quantization, colorspace quantization - * @xfer_func: enum v4l2_xfer_func, colorspace transfer function + * width: image width in pixels + * height: image height in pixels + * pixelformat: little endian four character code (fourcc) + * field: enum v4l2_field; field order (for interlaced video) + * colorspace: enum v4l2_colorspace; supplemental to pixelformat + * plane_fmt: per-plane information + * num_planes: number of planes for this format + * flags: format flags (V4L2_PIX_FMT_FLAG_*) + * ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding + * quantization: enum v4l2_quantization, colorspace quantization + * xfer_func: enum v4l2_xfer_func, colorspace transfer function */ struct v4l2_pix_format_mplane @@ -1073,10 +1073,10 @@ struct v4l2_event_src_change #define V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ (1 << 0) /* struct v4l2_event_motion_det - motion detection event - * @flags: if V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ is set, then the - * frame_sequence field is valid. - * @frame_sequence: the frame sequence number associated with this event. - * @region_mask: which regions detected motion. + * flags: if V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ is set, then the + * frame_sequence field is valid. + * frame_sequence: the frame sequence number associated with this event. + * region_mask: which regions detected motion. */ struct v4l2_event_motion_det diff --git a/net/netlink/netlink.h b/net/netlink/netlink.h index c86882266f..c2b83ed0fa 100644 --- a/net/netlink/netlink.h +++ b/net/netlink/netlink.h @@ -50,12 +50,11 @@ #ifdef CONFIG_NET_NETLINK -/** - * nla_for_each_attr - iterate over a stream of attributes - * @pos: loop counter, set to current attribute - * @head: head of attribute stream - * @len: length of attribute stream - * @rem: initialized to len, holds bytes currently remaining in stream +/* nla_for_each_attr - iterate over a stream of attributes + * pos: loop counter, set to current attribute + * head: head of attribute stream + * len: length of attribute stream + * rem: initialized to len, holds bytes currently remaining in stream */ #define nla_for_each_attr(pos, head, len, rem) \ @@ -82,31 +81,27 @@ } \ while (0) -/** - * nla_data - head of payload - * @nla: netlink attribute +/* nla_data - head of payload + * nla: netlink attribute */ #define nla_data(nla) ((FAR void *)((FAR char *)(nla) + NLA_HDRLEN)) -/** - * nla_len - length of payload - * @nla: netlink attribute +/* nla_len - length of payload + * nla: netlink attribute */ #define nla_len(nla) ((nla)->nla_len - NLA_HDRLEN) -/** - * nla_type - attribute type - * @nla: netlink attribute +/* nla_type - attribute type + * nla: netlink attribute */ #define nla_type(nla) ((nla)->nla_type & NLA_TYPE_MASK) -/** - * nla_ok - check if the netlink attribute fits into the remaining bytes - * @nla: netlink attribute - * @remaining: number of bytes remaining in attribute stream +/* nla_ok - check if the netlink attribute fits into the remaining bytes + * nla: netlink attribute + * remaining: number of bytes remaining in attribute stream */ #define nla_ok(nla, remaining) \ @@ -114,59 +109,52 @@ (nla)->nla_len >= sizeof(*(nla)) && \ (nla)->nla_len <= (remaining)) -/** - * nlmsg_msg_size - length of netlink message not including padding - * @payload: length of message payload +/* nlmsg_msg_size - length of netlink message not including padding + * payload: length of message payload */ #define nlmsg_msg_size(payload) (NLMSG_HDRLEN + (payload)) -/** - * nlmsg_len - length of message payload - * @nlh: netlink message header +/* nlmsg_len - length of message payload + * nlh: netlink message header */ #define nlmsg_len(nlh) ((nlh)->nlmsg_len - NLMSG_HDRLEN) -/** - * nlmsg_attrlen - length of attributes data - * @nlh: netlink message header - * @hdrlen: length of family specific header +/* nlmsg_attrlen - length of attributes data + * nlh: netlink message header + * hdrlen: length of family specific header */ #define nlmsg_attrlen(nlh, hdrlen) (nlmsg_len(nlh) - NLMSG_ALIGN(hdrlen)) -/** - * nlmsg_data - head of message payload - * @nlh: netlink message header +/* nlmsg_data - head of message payload + * nlh: netlink message header */ #define nlmsg_data(nlh) ((FAR void *)((FAR char *)(nlh) + NLMSG_HDRLEN)) -/** - * nla_get_in_addr - return payload of IPv4 address attribute - * @nla: IPv4 address netlink attribute +/* nla_get_in_addr - return payload of IPv4 address attribute + * nla: IPv4 address netlink attribute */ #define nla_get_in_addr(nla) (*(FAR uint32_t *)nla_data(nla)) -/** - * nlmsg_attrdata - head of attributes data - * @nlh: netlink message header - * @hdrlen: length of family specific header +/* nlmsg_attrdata - head of attributes data + * nlh: netlink message header + * hdrlen: length of family specific header */ #define nlmsg_attrdata(nlh, hdrlen) \ ((FAR struct nlattr *)((FAR char *)nlmsg_data(nlh) + NLMSG_ALIGN(hdrlen))) -/** - * nlmsg_parse - parse attributes of a netlink message - * @nlh: netlink message header - * @hdrlen: length of family specific header - * @tb: destination array with maxtype+1 elements - * @maxtype: maximum attribute type to be expected - * @policy: validation policy - * @extack: extended ACK report struct +/* nlmsg_parse - parse attributes of a netlink message + * nlh: netlink message header + * hdrlen: length of family specific header + * tb: destination array with maxtype+1 elements + * maxtype: maximum attribute type to be expected + * policy: validation policy + * extack: extended ACK report struct * * See nla_parse() */ @@ -210,9 +198,7 @@ struct netlink_conn_s sq_queue_t resplist; /* Singly linked list of responses */ }; -/** - * Standard attribute types to specify validation policy - */ +/* Standard attribute types to specify validation policy */ enum { @@ -236,13 +222,12 @@ enum NLA_TYPE_MAX = NLA_BITFIELD32, }; -/** - * struct netlink_ext_ack - netlink extended ACK report struct - * @_msg: message string to report - don't access directly, use - * %nl_set_err_msg_attr - * @bad_attr: attribute with error - * @cookie: cookie data to return to userspace (for success) - * @cookie_len: actual cookie data length +/* struct netlink_ext_ack - netlink extended ACK report struct + * _msg: message string to report - don't access directly, use + * nl_set_err_msg_attr + * bad_attr: attribute with error + * cookie: cookie data to return to userspace (for success) + * cookie_len: actual cookie data length */ struct netlink_ext_ack @@ -253,10 +238,9 @@ struct netlink_ext_ack uint8_t cookie_len; }; -/** - * struct nla_policy - attribute validation policy - * @type: Type of attribute or NLA_UNSPEC - * @len: Type specific length of payload +/* struct nla_policy - attribute validation policy + * type: Type of attribute or NLA_UNSPEC + * len: Type specific length of payload * * Policies are defined as arrays of this struct, the array must be * accessible by attribute type up to the highest identifier to be expected.