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arch/intel64: allow to attach handlers to ISR
arch/intel64: allow to attach handlers to ISR Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
Xiang Xiao
parent
6f4f50e2fe
commit
cfaeb74dd3
3 changed files with 53 additions and 176 deletions
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@ -135,115 +135,12 @@ static uint64_t *common_handler(int irq, uint64_t *regs)
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: isr_handler
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*
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* Description:
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* This gets called from ISR vector handling logic in broadwell_vectors.S
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*
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****************************************************************************/
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uint64_t *isr_handler(uint64_t *regs, uint64_t irq)
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{
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struct tcb_s **running_task = &g_running_tasks[this_cpu()];
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struct tcb_s *tcb;
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if (*running_task != NULL)
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{
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(*running_task)->xcp.regs = regs;
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}
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board_autoled_on(LED_INIRQ);
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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/* Doesn't return */
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PANIC();
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/* To keep the compiler happy */
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return regs;
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#else
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DEBUGASSERT(!up_interrupt_context());
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/* Set irq flag */
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up_set_interrupt_context(true);
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switch (irq)
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{
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case 0:
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case 16:
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__asm__ volatile("fnclex":::"memory");
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nxsig_kill(this_task()->pid, SIGFPE);
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break;
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default:
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/* Let's say, all ISR are asserted when REALLY BAD things happened.
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* Don't even brother to recover, just dump the regs and PANIC.
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*/
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_alert("PANIC:\n");
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_alert("Exception %" PRId64 " occurred "
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"with error code %" PRId64 ":\n",
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irq, regs[REG_ERRCODE]);
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PANIC_WITH_REGS("panic", regs);
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up_trash_cpu();
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break;
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}
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tcb = this_task();
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/* Check for a context switch. If a context switch occurred, then
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* g_current_regs will have a different value than it did on entry. If an
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* interrupt level context switch has occurred, then the establish the
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* correct address environment before returning from the interrupt.
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*/
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if (*running_task != tcb)
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{
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#ifdef CONFIG_ARCH_ADDRENV
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/* Make sure that the address environment for the previously
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* running task is closed down gracefully (data caches dump,
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* MMU flushed) and set up the address environment for the new
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* thread at the head of the ready-to-run list.
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*/
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addrenv_switch(NULL);
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#endif
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/* Update scheduler parameters */
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nxsched_suspend_scheduler(*running_task);
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nxsched_resume_scheduler(tcb);
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/* Record the new "running" task when context switch occurred.
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* g_running_tasks[] is only used by assertion logic for reporting
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* crashes.
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*/
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*running_task = tcb;
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/* Restore the cpu lock */
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restore_critical_section(tcb, this_cpu());
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}
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/* Clear irq flag */
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up_set_interrupt_context(false);
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return tcb->xcp.regs;
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#endif
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}
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/****************************************************************************
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* Name: irq_handler
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*
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* Description:
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* This gets called from IRQ vector handling logic in intel64_vectors.S
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* This gets called from IRQ or ISR vector handling logic in
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* intel64_vectors.S
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*
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****************************************************************************/
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@ -40,7 +40,9 @@
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#include <arch/board/board.h>
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#include <nuttx/spinlock.h>
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#include <nuttx/signal.h>
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#include "sched/sched.h"
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#include "x86_64_internal.h"
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#include "intel64_cpu.h"
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#include "intel64.h"
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@ -430,10 +432,6 @@ static inline void up_idtinit(void)
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setidt(&g_idt_entries, sizeof(struct idt_entry_s) * NR_IRQS - 1);
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}
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_color_intstack
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*
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@ -453,6 +451,43 @@ static inline void x86_64_color_intstack(void)
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# define x86_64_color_intstack()
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#endif
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/****************************************************************************
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* Name: x86_64_fault_panic_isr
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****************************************************************************/
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static int x86_64_fault_panic_isr(int irq, void *c, void *arg)
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{
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uint64_t *regs = (uint64_t *)running_regs();
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/* Let's say, all ISR are asserted when REALLY BAD things happened.
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* Don't even brother to recover, just dump the regs and PANIC.
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*/
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_alert("PANIC:\n");
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_alert("Exception %" PRId32 " occurred "
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"with error code %" PRId64 ":\n",
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irq, regs[REG_ERRCODE]);
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PANIC_WITH_REGS("panic", regs);
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up_trash_cpu();
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return 0;
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}
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/****************************************************************************
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* Name: x86_64_fault_kill_isr
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****************************************************************************/
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static int x86_64_fault_kill_isr(int irq, void *c, void *arg)
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{
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__asm__ volatile("fnclex":::"memory");
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nxsig_kill(running_task()->pid, SIGFPE);
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -503,6 +538,15 @@ void up_irqinitialize(void)
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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up_irq_restore(X86_64_RFLAGS_IF);
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#endif
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/* Attach default handlers for faults */
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irq_attach(ISR0, x86_64_fault_kill_isr, NULL);
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irq_attach(ISR6, x86_64_fault_panic_isr, NULL);
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irq_attach(ISR8, x86_64_fault_panic_isr, NULL);
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irq_attach(ISR13, x86_64_fault_panic_isr, NULL);
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irq_attach(ISR14, x86_64_fault_panic_isr, NULL);
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irq_attach(ISR16, x86_64_fault_kill_isr, NULL);
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}
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/****************************************************************************
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@ -41,7 +41,6 @@
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****************************************************************************/
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.globl irq_handler
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.globl isr_handler
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.globl irq_xcp_regs
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.globl g_interrupt_stack
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.globl g_interrupt_stack_end
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@ -69,7 +68,7 @@ vector_isr\intno:
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pushq %rdi
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pushq %rsi
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movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
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jmp isr_common /* Go to the common ISR handler code. */
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jmp irq_common /* Go to the common IRQ handler code. */
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.endm
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/* This macro creates a stub for an ISR which passes it's own
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@ -87,7 +86,7 @@ vector_isr\intno:
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pushq %rdi
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pushq %rsi
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movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
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jmp isr_common /* Go to the common ISR handler code. */
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jmp irq_common /* Go to the common IRQ handler code. */
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.endm
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/* This macro creates a stub for an IRQ - the first parameter is
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@ -692,69 +691,6 @@ vector_isr\intno:
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IRQ 255, IRQ255
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.balign 16
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/****************************************************************************
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* Name: isr_common
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*
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* Description:
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* This is the common ISR logic. It saves the processor state, sets up for
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* kernel mode segments, calls the C-level fault handler, and finally
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* restores the stack frame.
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*
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****************************************************************************/
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isr_common:
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/* Already swap to the interrupt stack */
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/* stack is automatically recovered by iretq using task state */
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/* x86_64 don't have pusha, we have to do things manually */
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/* RDI and RSI are pushed above for handling IRQ no */
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pushq %rdx
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pushq %rcx
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pushq %r8
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pushq %r9
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %rbp
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pushq %rbx
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pushq %rax
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xor %rax, %rax /* Reset rax */
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mov %ds, %ax /* Lower 16-bits of rax. */
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pushq %rax /* Save the data segment descriptor */
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mov %es, %ax /* Lower 16-bits of rax. */
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pushq %rax /* Save the data segment descriptor */
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mov %gs, %ax /* Lower 16-bits of rax. */
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pushq %rax /* Save the data segment descriptor */
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mov %fs, %ax /* Lower 16-bits of rax. */
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pushq %rax /* Save the data segment descriptor */
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/* Align to 64-bytes boundary */
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leaq -(XMMAREA_REG_ALIGN * 8)(%rsp), %rsp
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/* Save xmm registers */
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leaq -XCPTCONTEXT_XMM_AREA_SIZE(%rsp), %rsp
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#ifndef CONFIG_ARCH_X86_64_HAVE_XSAVE
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fxsaveq (%rsp)
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#else
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movl $XSAVE_STATE_COMPONENTS, %eax
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xor %edx, %edx
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xsave (%rsp)
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#endif
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/* The current value of the SP points to the beginning of the state save
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* structure. Save that in RDI as the input parameter to isr_handler.
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*/
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mov %rsp, %rdi
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call isr_handler
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jmp .Lreturn
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.size isr_common, . - isr_common
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/****************************************************************************
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* Name: irq_common
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*
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@ -850,7 +786,7 @@ irq_common:
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add $8, %rsp
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popq %rdi
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/* The common return point for both isr_handler and irq_handler */
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/* The common return point for irq_handler */
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.Lreturn:
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