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arm64/sctlr: Allows thread to independent control the switch of sctlr

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The method is the same as the method of saving the current DAIF state of the thread
It will pave the way for the future implementation of hwasan's memory management
Allows each thread to independently control the mte switch function

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This commit is contained in:
wangmingrong1 2025-01-06 20:17:55 +08:00 committed by Xiang Xiao
parent 724797e05c
commit d22e6d7489
4 changed files with 19 additions and 2 deletions
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3
arch/arm64/include/irq.h
View file

@ -153,10 +153,11 @@
#define REG_SPSR (33)
#define REG_SP_EL0 (34)
#define REG_EXE_DEPTH (35)
#define REG_SCTLR_EL1 (36)
/* In Armv8-A Architecture, the stack must align with 16 byte */
#define ARM64_CONTEXT_REGS (36)
#define ARM64_CONTEXT_REGS (37)
#define ARM64_CONTEXT_SIZE (8 * ARM64_CONTEXT_REGS)
#ifdef CONFIG_ARCH_FPU

5
arch/arm64/src/common/arm64_initialstate.c
View file

@ -86,6 +86,11 @@ void arm64_new_task(struct tcb_s * tcb)
xcp->regs[REG_SPSR] = SPSR_MODE_EL1H;
#endif
xcp->regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1);
#ifdef CONFIG_ARM64_MTE
xcp->regs[REG_SCTLR_EL1] |= SCTLR_TCF1_BIT;
#endif
#ifdef CONFIG_SUPPRESS_INTERRUPTS
xcp->regs[REG_SPSR] |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT);
#endif /* CONFIG_SUPPRESS_INTERRUPTS */

8
arch/arm64/src/common/arm64_vector_table.S
View file

@ -80,9 +80,12 @@
#endif
stp \xreg0, \xreg1, [sp, #8 * REG_ELR]
mrs \xreg0, sctlr_el1
str \xreg0, [sp, #8 * REG_SCTLR_EL1]
mrs \xreg0, sp_el0
mrs \xreg1, tpidrro_el0
stp \xreg0, \xreg1, [sp, #8 * REG_SP_EL0]
stp \xreg0, \xreg1, [sp, #8 * REG_SP_EL0]
/* Increment exception depth */
@ -268,6 +271,9 @@ SECTION_FUNC(text, arm64_exit_exception)
msr spsr_el1, x1
#endif
ldr x0, [sp, #8 * REG_SCTLR_EL1]
msr sctlr_el1, x0
ldp x0, x1, [sp, #8 * REG_SP_EL0]
msr sp_el0, x0
msr tpidrro_el0, x1

5
arch/arm64/src/common/arm64_vectors.S
View file

@ -84,6 +84,9 @@ SECTION_FUNC(text, up_saveusercontext)
#endif
stp x4, x5, [x0, #8 * REG_ELR]
mrs x4, sctlr_el1
str x4, [x0, #8 * REG_SCTLR_EL1]
ret
/****************************************************************************
@ -115,6 +118,8 @@ SECTION_FUNC(text, arm64_jump_to_user)
and x0, x0, #~SPSR_MODE_MASK
#orr x0, x0, #SPSR_MODE_EL0T # EL0T=0x00, out of range for orr
str x0, [sp, #8 * REG_SPSR]
mrs x0, sctlr_el1
str x0, [sp, #8 * REG_SCTLR_EL1]
b arm64_exit_exception
#endif