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Add initial support for NXP S32K3 MCU family

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Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
This commit is contained in:
Jari van Ewijk 2022-07-22 10:25:50 +02:00 committed by Xiang Xiao
parent 51a845ce54
commit dd1096695d
95 changed files with 49153 additions and 0 deletions
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12
arch/arm/Kconfig
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@ -248,6 +248,14 @@ config ARCH_CHIP_S32K1XX
---help---
NPX S32K1XX architectures (ARM Cortex-M0+ and Cortex-M4F).
config ARCH_CHIP_S32K3XX
bool "NXP S32K3XX"
select ARCH_HAVE_MPU
select ARCH_HAVE_RAMFUNCS
select ARM_HAVE_MPU_UNIFIED
---help---
NPX S32K3XX architectures (ARM Cortex-M7).
config ARCH_CHIP_SAMA5
bool "Atmel SAMA5"
select ARCH_CORTEXA5
@ -873,6 +881,7 @@ config ARCH_CHIP
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "rp2040" if ARCH_CHIP_RP2040
default "s32k1xx" if ARCH_CHIP_S32K1XX
default "s32k3xx" if ARCH_CHIP_S32K3XX
default "sama5" if ARCH_CHIP_SAMA5
default "samd2l2" if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
@ -1220,6 +1229,9 @@ endif
if ARCH_CHIP_S32K1XX
source "arch/arm/src/s32k1xx/Kconfig"
endif
if ARCH_CHIP_S32K3XX
source arch/arm/src/s32k3xx/Kconfig
endif
if ARCH_CHIP_MAX326XX
source "arch/arm/src/max326xx/Kconfig"
endif

61
arch/arm/include/s32k3xx/chip.h Normal file
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@ -0,0 +1,61 @@
/****************************************************************************
* arch/arm/include/s32k3xx/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_INCLUDE_S32K3XX_CHIP_H
#define __ARCH_ARM_INCLUDE_S32K3XX_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* NVIC priority levels *****************************************************/
/* Each priority field holds a priority value. The lower the value, the
* greater the priority of the corresponding interrupt.
*/
/* Supports 16 programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_S32K3XX_CHIP_H */

82
arch/arm/include/s32k3xx/irq.h Normal file
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@ -0,0 +1,82 @@
/****************************************************************************
* arch/arm/include/s32k3xx/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_S32K3XX_IRQ_H
#define __ARCH_ARM_INCLUDE_S32K3XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds to the vector number and hence maps directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define S32K3XX_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Initial Stack Pointer */
/* Vector 1: Initial Program Counter (not handled as an IRQ) */
#define S32K3XX_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt */
#define S32K3XX_IRQ_HARDFAULT (3) /* Vector 3: Hard Fault */
#define S32K3XX_IRQ_MEMFAULT (4) /* Vector 4: Memory Management Fault */
#define S32K3XX_IRQ_BUSFAULT (5) /* Vector 5: Bus Fault */
#define S32K3XX_IRQ_USAGEFAULT (6) /* Vector 6: Usage Fault */
/* Vector 7: Reserved */
/* Vector 8: Reserved */
/* Vector 9: Reserved */
/* Vector 10: Reserved */
#define S32K3XX_IRQ_SVCALL (11) /* Vector 11: Supervisor Call */
#define S32K3XX_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define S32K3XX_IRQ_PENDSV (14) /* Vector 14: Pendable System Service Request */
#define S32K3XX_IRQ_SYSTICK (15) /* Vector 15: System Tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific.
*/
#define S32K3XX_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */
/****************************************************************************
* Included Files
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_S32K344)
# include <arch/chip/s32k3x4_irq.h>
#else
# error Unrecognized S32K3XX part
#endif
#endif /* __ARCH_ARM_INCLUDE_S32K3XX_IRQ_H */

292
arch/arm/include/s32k3xx/s32k3x4_irq.h Normal file
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@ -0,0 +1,292 @@
/****************************************************************************
* arch/arm/include/s32k3xx/s32k3x4_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_S32K3XX_S32K3X4_IRQ_H
#define __ARCH_ARM_INCLUDE_S32K3XX_S32K3X4_IRQ_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds to the vector number and hence maps directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16).
* These definitions are chip-specific.
*/
/* CPU to CPU and Directed Interrupts */
#define S32K3XX_IRQ_CPU_TO_CPU1 (S32K3XX_IRQ_EXTINT + 0) /* 0: CPU to CPU interupt 0 (Core 0 --> Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU2 (S32K3XX_IRQ_EXTINT + 1) /* 1: CPU to CPU interupt 1 (Core 0 --> Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU3 (S32K3XX_IRQ_EXTINT + 2) /* 2: CPU to CPU interupt 2 (Core 0 <-- Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU4 (S32K3XX_IRQ_EXTINT + 3) /* 3: CPU to CPU interupt 3 (Core 0 <-- Core 1) */
/* Shared Peripheral Interrupts - On-Platform Vectors */
#define S32K3XX_IRQ_DMA_CH0 (S32K3XX_IRQ_EXTINT + 4) /* 4: DMA transfer complete and error CH0 */
#define S32K3XX_IRQ_DMA_CH1 (S32K3XX_IRQ_EXTINT + 5) /* 5: DMA transfer complete and error CH1 */
#define S32K3XX_IRQ_DMA_CH2 (S32K3XX_IRQ_EXTINT + 6) /* 6: DMA transfer complete and error CH2 */
#define S32K3XX_IRQ_DMA_CH3 (S32K3XX_IRQ_EXTINT + 7) /* 7: DMA transfer complete and error CH3 */
#define S32K3XX_IRQ_DMA_CH4 (S32K3XX_IRQ_EXTINT + 8) /* 8: DMA transfer complete and error CH4 */
#define S32K3XX_IRQ_DMA_CH5 (S32K3XX_IRQ_EXTINT + 9) /* 9: DMA transfer complete and error CH5 */
#define S32K3XX_IRQ_DMA_CH6 (S32K3XX_IRQ_EXTINT + 10) /* 10: DMA transfer complete and error CH6 */
#define S32K3XX_IRQ_DMA_CH7 (S32K3XX_IRQ_EXTINT + 11) /* 11: DMA transfer complete and error CH7 */
#define S32K3XX_IRQ_DMA_CH8 (S32K3XX_IRQ_EXTINT + 12) /* 12: DMA transfer complete and error CH8 */
#define S32K3XX_IRQ_DMA_CH9 (S32K3XX_IRQ_EXTINT + 13) /* 13: DMA transfer complete and error CH9 */
#define S32K3XX_IRQ_DMA_CH10 (S32K3XX_IRQ_EXTINT + 14) /* 14: DMA transfer complete and error CH10 */
#define S32K3XX_IRQ_DMA_CH11 (S32K3XX_IRQ_EXTINT + 15) /* 15: DMA transfer complete and error CH11 */
#define S32K3XX_IRQ_DMA_CH12 (S32K3XX_IRQ_EXTINT + 16) /* 16: DMA transfer complete and error CH12 */
#define S32K3XX_IRQ_DMA_CH13 (S32K3XX_IRQ_EXTINT + 17) /* 17: DMA transfer complete and error CH13 */
#define S32K3XX_IRQ_DMA_CH14 (S32K3XX_IRQ_EXTINT + 18) /* 18: DMA transfer complete and error CH14 */
#define S32K3XX_IRQ_DMA_CH15 (S32K3XX_IRQ_EXTINT + 19) /* 19: DMA transfer complete and error CH15 */
#define S32K3XX_IRQ_DMA_CH16 (S32K3XX_IRQ_EXTINT + 20) /* 20: DMA transfer complete and error CH16 */
#define S32K3XX_IRQ_DMA_CH17 (S32K3XX_IRQ_EXTINT + 21) /* 21: DMA transfer complete and error CH17 */
#define S32K3XX_IRQ_DMA_CH18 (S32K3XX_IRQ_EXTINT + 22) /* 22: DMA transfer complete and error CH18 */
#define S32K3XX_IRQ_DMA_CH19 (S32K3XX_IRQ_EXTINT + 23) /* 23: DMA transfer complete and error CH19 */
#define S32K3XX_IRQ_DMA_CH20 (S32K3XX_IRQ_EXTINT + 24) /* 24: DMA transfer complete and error CH20 */
#define S32K3XX_IRQ_DMA_CH21 (S32K3XX_IRQ_EXTINT + 25) /* 25: DMA transfer complete and error CH21 */
#define S32K3XX_IRQ_DMA_CH22 (S32K3XX_IRQ_EXTINT + 26) /* 26: DMA transfer complete and error CH22 */
#define S32K3XX_IRQ_DMA_CH23 (S32K3XX_IRQ_EXTINT + 27) /* 27: DMA transfer complete and error CH23 */
#define S32K3XX_IRQ_DMA_CH24 (S32K3XX_IRQ_EXTINT + 28) /* 28: DMA transfer complete and error CH24 */
#define S32K3XX_IRQ_DMA_CH25 (S32K3XX_IRQ_EXTINT + 29) /* 29: DMA transfer complete and error CH25 */
#define S32K3XX_IRQ_DMA_CH26 (S32K3XX_IRQ_EXTINT + 30) /* 30: DMA transfer complete and error CH26 */
#define S32K3XX_IRQ_DMA_CH27 (S32K3XX_IRQ_EXTINT + 31) /* 31: DMA transfer complete and error CH27 */
#define S32K3XX_IRQ_DMA_CH28 (S32K3XX_IRQ_EXTINT + 32) /* 32: DMA transfer complete and error CH28 */
#define S32K3XX_IRQ_DMA_CH29 (S32K3XX_IRQ_EXTINT + 33) /* 33: DMA transfer complete and error CH29 */
#define S32K3XX_IRQ_DMA_CH30 (S32K3XX_IRQ_EXTINT + 34) /* 34: DMA transfer complete and error CH30 */
#define S32K3XX_IRQ_DMA_CH31 (S32K3XX_IRQ_EXTINT + 35) /* 35: DMA transfer complete and error CH31 */
#define S32K3XX_IRQ_ERM_SBE (S32K3XX_IRQ_EXTINT + 36) /* 36: Error Reporting Module single bit ECC error interrupt */
#define S32K3XX_IRQ_ERM_MBE (S32K3XX_IRQ_EXTINT + 37) /* 37: Error Reporting Module multi bit ECC error interrupt */
#define S32K3XX_IRQ_MCM_FPU (S32K3XX_IRQ_EXTINT + 38) /* 38: Miscellaneous Control Module FPU interrupts */
#define S32K3XX_IRQ_STM0 (S32K3XX_IRQ_EXTINT + 39) /* 39: System Timer Module 0 interrupt */
#define S32K3XX_IRQ_STM1 (S32K3XX_IRQ_EXTINT + 40) /* 40: System Timer Module 1 interrupt */
#define S32K3XX_IRQ_RESERVED41 (S32K3XX_IRQ_EXTINT + 41) /* 41: Reserved */
#define S32K3XX_IRQ_SWT0 (S32K3XX_IRQ_EXTINT + 42) /* 42: System Watchdog Timer 0 initial time-out interrupt */
#define S32K3XX_IRQ_SWT1 (S32K3XX_IRQ_EXTINT + 43) /* 43: System Watchdog Timer 1 initial time-out interrupt */
#define S32K3XX_IRQ_RESERVED44 (S32K3XX_IRQ_EXTINT + 44) /* 44: Reserved */
#define S32K3XX_IRQ_CTI0 (S32K3XX_IRQ_EXTINT + 45) /* 45: Cross Trigger Interface interrupt 0 */
#define S32K3XX_IRQ_CTI1 (S32K3XX_IRQ_EXTINT + 46) /* 46: Cross Trigger Interface interrupt 1 */
#define S32K3XX_IRQ_RESERVED47 (S32K3XX_IRQ_EXTINT + 47) /* 47: Reserved */
/* Shared Peripheral Interrupts - Off-Platform Vectors */
#define S32K3XX_IRQ_PFLASH_OP (S32K3XX_IRQ_EXTINT + 48) /* 48: Platform Flash Memory Controller program or erase operation completed */
#define S32K3XX_IRQ_PFLASH_WDOG (S32K3XX_IRQ_EXTINT + 49) /* 49: Platform Flash Memory Controller main/express watchdog time-out interrupt */
#define S32K3XX_IRQ_PFLASH_WDOGALT (S32K3XX_IRQ_EXTINT + 50) /* 50: Platform Flash Memory Controller alternate watchdog time-out interrupt */
#define S32K3XX_IRQ_MC_RGM (S32K3XX_IRQ_EXTINT + 51) /* 51: Reset Generation Module interrupt */
#define S32K3XX_IRQ_PMC (S32K3XX_IRQ_EXTINT + 52) /* 52: Power Management Controller interrupts */
#define S32K3XX_IRQ_SIUL2_VEC0 (S32K3XX_IRQ_EXTINT + 53) /* 53: System Integration Unit Lite 2 external interrupt vector 0 */
#define S32K3XX_IRQ_SIUL2_VEC1 (S32K3XX_IRQ_EXTINT + 54) /* 54: System Integration Unit Lite 2 external interrupt vector 1 */
#define S32K3XX_IRQ_SIUL2_VEC2 (S32K3XX_IRQ_EXTINT + 55) /* 55: System Integration Unit Lite 2 external interrupt vector 2 */
#define S32K3XX_IRQ_SIUL2_VEC3 (S32K3XX_IRQ_EXTINT + 56) /* 56: System Integration Unit Lite 2 external interrupt vector 3 */
#define S32K3XX_IRQ_RESERVED57 (S32K3XX_IRQ_EXTINT + 57) /* 57: Reserved */
#define S32K3XX_IRQ_RESERVED58 (S32K3XX_IRQ_EXTINT + 58) /* 58: Reserved */
#define S32K3XX_IRQ_RESERVED59 (S32K3XX_IRQ_EXTINT + 59) /* 59: Reserved */
#define S32K3XX_IRQ_RESERVED60 (S32K3XX_IRQ_EXTINT + 60) /* 60: Reserved */
#define S32K3XX_IRQ_EMIOS0_20_23 (S32K3XX_IRQ_EXTINT + 61) /* 61: eMIOS0 interrupt requests 20-23 */
#define S32K3XX_IRQ_EMIOS0_16_19 (S32K3XX_IRQ_EXTINT + 62) /* 62: eMIOS0 interrupt requests 16-19 */
#define S32K3XX_IRQ_EMIOS0_12_15 (S32K3XX_IRQ_EXTINT + 63) /* 63: eMIOS0 interrupt requests 12-15 */
#define S32K3XX_IRQ_EMIOS0_8_11 (S32K3XX_IRQ_EXTINT + 64) /* 64: eMIOS0 interrupt requests 8-11 */
#define S32K3XX_IRQ_EMIOS0_4_7 (S32K3XX_IRQ_EXTINT + 65) /* 65: eMIOS0 interrupt requests 4-7 */
#define S32K3XX_IRQ_EMIOS0_0_3 (S32K3XX_IRQ_EXTINT + 66) /* 66: eMIOS0 interrupt requests 0-3 */
#define S32K3XX_IRQ_RESERVED67 (S32K3XX_IRQ_EXTINT + 67) /* 67: Reserved */
#define S32K3XX_IRQ_RESERVED68 (S32K3XX_IRQ_EXTINT + 68) /* 68: Reserved */
#define S32K3XX_IRQ_EMIOS1_20_23 (S32K3XX_IRQ_EXTINT + 69) /* 69: eMIOS1 interrupt requests 20-23 */
#define S32K3XX_IRQ_EMIOS1_16_19 (S32K3XX_IRQ_EXTINT + 70) /* 70: eMIOS1 interrupt requests 16-19 */
#define S32K3XX_IRQ_EMIOS1_12_15 (S32K3XX_IRQ_EXTINT + 71) /* 71: eMIOS1 interrupt requests 12-15 */
#define S32K3XX_IRQ_EMIOS1_8_11 (S32K3XX_IRQ_EXTINT + 72) /* 72: eMIOS1 interrupt requests 8-11 */
#define S32K3XX_IRQ_EMIOS1_4_7 (S32K3XX_IRQ_EXTINT + 73) /* 73: eMIOS1 interrupt requests 4-7 */
#define S32K3XX_IRQ_EMIOS1_0_3 (S32K3XX_IRQ_EXTINT + 74) /* 74: eMIOS1 interrupt requests 0-3 */
#define S32K3XX_IRQ_RESERVED75 (S32K3XX_IRQ_EXTINT + 75) /* 75: Reserved */
#define S32K3XX_IRQ_RESERVED76 (S32K3XX_IRQ_EXTINT + 76) /* 76: Reserved */
#define S32K3XX_IRQ_EMIOS2_20_23 (S32K3XX_IRQ_EXTINT + 77) /* 77: eMIOS2 interrupt requests 20-23 */
#define S32K3XX_IRQ_EMIOS2_16_19 (S32K3XX_IRQ_EXTINT + 78) /* 78: eMIOS2 interrupt requests 16-19 */
#define S32K3XX_IRQ_EMIOS2_12_15 (S32K3XX_IRQ_EXTINT + 79) /* 79: eMIOS2 interrupt requests 12-15 */
#define S32K3XX_IRQ_EMIOS2_8_11 (S32K3XX_IRQ_EXTINT + 80) /* 80: eMIOS2 interrupt requests 8-11 */
#define S32K3XX_IRQ_EMIOS2_4_7 (S32K3XX_IRQ_EXTINT + 81) /* 81: eMIOS2 interrupt requests 4-7 */
#define S32K3XX_IRQ_EMIOS2_0_3 (S32K3XX_IRQ_EXTINT + 82) /* 82: eMIOS2 interrupt requests 0-3 */
#define S32K3XX_IRQ_WKPU (S32K3XX_IRQ_EXTINT + 83) /* 83: Wakeup Unit interrupts */
#define S32K3XX_IRQ_CMU0 (S32K3XX_IRQ_EXTINT + 84) /* 84: Clock Monitoring Unit 0 interrupt */
#define S32K3XX_IRQ_CMU1 (S32K3XX_IRQ_EXTINT + 85) /* 85: Clock Monitoring Unit 1 interrupt */
#define S32K3XX_IRQ_CMU2 (S32K3XX_IRQ_EXTINT + 86) /* 86: Clock Monitoring Unit 2 interrupt */
#define S32K3XX_IRQ_BCTU (S32K3XX_IRQ_EXTINT + 87) /* 87: Body Cross Triggering Unit interrupts */
#define S32K3XX_IRQ_RESERVED88 (S32K3XX_IRQ_EXTINT + 88) /* 88: Reserved */
#define S32K3XX_IRQ_RESERVED89 (S32K3XX_IRQ_EXTINT + 89) /* 89: Reserved */
#define S32K3XX_IRQ_RESERVED90 (S32K3XX_IRQ_EXTINT + 90) /* 90: Reserved */
#define S32K3XX_IRQ_RESERVED91 (S32K3XX_IRQ_EXTINT + 91) /* 91: Reserved */
#define S32k3XX_IRQ_LCU0 (S32K3XX_IRQ_EXTINT + 92) /* 92: Logic Control Unit 0 interrupts */
#define S32k3XX_IRQ_LCU1 (S32K3XX_IRQ_EXTINT + 93) /* 93: Logic Control Unit 1 interrupts */
#define S32K3XX_IRQ_RESERVED94 (S32K3XX_IRQ_EXTINT + 94) /* 94: Reserved */
#define S32K3XX_IRQ_RESERVED95 (S32K3XX_IRQ_EXTINT + 95) /* 95: Reserved */
#define S32k3XX_IRQ_PIT0 (S32K3XX_IRQ_EXTINT + 96) /* 96: Periodic Interrupt Timer 0 interrupts */
#define S32k3XX_IRQ_PIT1 (S32K3XX_IRQ_EXTINT + 97) /* 97: Periodic Interrupt Timer 1 interrupts */
#define S32k3XX_IRQ_PIT2 (S32K3XX_IRQ_EXTINT + 98) /* 98: Periodic Interrupt Timer 2 interrupts */
#define S32K3XX_IRQ_RESERVED99 (S32K3XX_IRQ_EXTINT + 99) /* 99: Reserved */
#define S32K3XX_IRQ_RESERVED100 (S32K3XX_IRQ_EXTINT + 100) /* 100: Reserved */
#define S32K3XX_IRQ_RESERVED101 (S32K3XX_IRQ_EXTINT + 101) /* 101: Reserved */
#define S32K3XX_IRQ_RTC (S32K3XX_IRQ_EXTINT + 102) /* 102: Real Time Clock interrupts */
#define S32K3XX_IRQ_RESERVED103 (S32K3XX_IRQ_EXTINT + 103) /* 103: Reserved */
#define S32K3XX_IRQ_RESERVED104 (S32K3XX_IRQ_EXTINT + 104) /* 104: Reserved */
#define S32K3XX_IRQ_EMAC_COMMON (S32K3XX_IRQ_EXTINT + 105) /* 105: Ethernet MAC common interrupts */
#define S32K3XX_IRQ_EMAC_TX (S32K3XX_IRQ_EXTINT + 106) /* 106: Ethernet MAC TX interrupts */
#define S32K3XX_IRQ_EMAC_RX (S32K3XX_IRQ_EXTINT + 107) /* 107: Ethernet MAC RX interrupts */
#define S32K3XX_IRQ_EMAC_SAFETY (S32K3XX_IRQ_EXTINT + 108) /* 108: Ethernet MAC safety interrupts */
#define S32K3XX_IRQ_FLEXCAN0_0 (S32K3XX_IRQ_EXTINT + 109) /* 109: FlexCAN 0 interrupts 0 */
#define S32K3XX_IRQ_FLEXCAN0_1 (S32K3XX_IRQ_EXTINT + 110) /* 110: FlexCAN 0 interrupts 1 */
#define S32K3XX_IRQ_FLEXCAN0_2 (S32K3XX_IRQ_EXTINT + 111) /* 111: FlexCAN 0 interrupts 2 */
#define S32K3XX_IRQ_FLEXCAN0_3 (S32K3XX_IRQ_EXTINT + 112) /* 112: FlexCAN 0 interrupts 3 */
#define S32K3XX_IRQ_FLEXCAN1_0 (S32K3XX_IRQ_EXTINT + 113) /* 113: FlexCAN 1 interrupts 0 */
#define S32K3XX_IRQ_FLEXCAN1_1 (S32K3XX_IRQ_EXTINT + 114) /* 114: FlexCAN 1 interrupts 1 */
#define S32K3XX_IRQ_FLEXCAN1_2 (S32K3XX_IRQ_EXTINT + 115) /* 115: FlexCAN 1 interrupts 2 */
#define S32K3XX_IRQ_FLEXCAN2_0 (S32K3XX_IRQ_EXTINT + 116) /* 116: FlexCAN 2 interrupts 0 */
#define S32K3XX_IRQ_FLEXCAN2_1 (S32K3XX_IRQ_EXTINT + 117) /* 117: FlexCAN 2 interrupts 1 */
#define S32K3XX_IRQ_FLEXCAN2_2 (S32K3XX_IRQ_EXTINT + 118) /* 118: FlexCAN 2 interrupts 2 */
#define S32K3XX_IRQ_FLEXCAN3_0 (S32K3XX_IRQ_EXTINT + 119) /* 119: FlexCAN 3 interrupts 0 */
#define S32K3XX_IRQ_FLEXCAN3_1 (S32K3XX_IRQ_EXTINT + 120) /* 120: FlexCAN 3 interrupts 1 */
#define S32K3XX_IRQ_FLEXCAN4_0 (S32K3XX_IRQ_EXTINT + 121) /* 121: FlexCAN 4 interrupts 0 */
#define S32K3XX_IRQ_FLEXCAN4_1 (S32K3XX_IRQ_EXTINT + 122) /* 122: FlexCAN 4 interrupts 1 */
#define S32K3XX_IRQ_FLEXCAN5_0 (S32K3XX_IRQ_EXTINT + 123) /* 123: FlexCAN 5 interrupts 0 */
#define S32K3XX_IRQ_FLEXCAN5_1 (S32K3XX_IRQ_EXTINT + 124) /* 124: FlexCAN 5 interrupts 1 */
#define S32K3XX_IRQ_RESERVED125 (S32K3XX_IRQ_EXTINT + 125) /* 125: Reserved */
#define S32K3XX_IRQ_RESERVED126 (S32K3XX_IRQ_EXTINT + 126) /* 126: Reserved */
#define S32K3XX_IRQ_RESERVED127 (S32K3XX_IRQ_EXTINT + 127) /* 127: Reserved */
#define S32K3XX_IRQ_RESERVED128 (S32K3XX_IRQ_EXTINT + 128) /* 128: Reserved */
#define S32K3XX_IRQ_RESERVED129 (S32K3XX_IRQ_EXTINT + 129) /* 129: Reserved */
#define S32K3XX_IRQ_RESERVED130 (S32K3XX_IRQ_EXTINT + 130) /* 130: Reserved */
#define S32K3XX_IRQ_RESERVED131 (S32K3XX_IRQ_EXTINT + 131) /* 131: Reserved */
#define S32K3XX_IRQ_RESERVED132 (S32K3XX_IRQ_EXTINT + 132) /* 132: Reserved */
#define S32K3XX_IRQ_RESERVED133 (S32K3XX_IRQ_EXTINT + 133) /* 133: Reserved */
#define S32K3XX_IRQ_RESERVED134 (S32K3XX_IRQ_EXTINT + 134) /* 134: Reserved */
#define S32K3XX_IRQ_RESERVED135 (S32K3XX_IRQ_EXTINT + 135) /* 135: Reserved */
#define S32K3XX_IRQ_RESERVED136 (S32K3XX_IRQ_EXTINT + 136) /* 136: Reserved */
#define S32K3XX_IRQ_RESERVED137 (S32K3XX_IRQ_EXTINT + 137) /* 137: Reserved */
#define S32K3XX_IRQ_RESERVED138 (S32K3XX_IRQ_EXTINT + 138) /* 138: Reserved */
#define S32K3XX_IRQ_FLEXIO (S32K3XX_IRQ_EXTINT + 139) /* 139: FlexIO interrupt */
#define S32K3XX_IRQ_RESERVED140 (S32K3XX_IRQ_EXTINT + 140) /* 140: Reserved */
#define S32K3XX_IRQ_LPUART0 (S32K3XX_IRQ_EXTINT + 141) /* 141: LPUART0 interrupts */
#define S32K3XX_IRQ_LPUART1 (S32K3XX_IRQ_EXTINT + 142) /* 142: LPUART1 interrupts */
#define S32K3XX_IRQ_LPUART2 (S32K3XX_IRQ_EXTINT + 143) /* 143: LPUART2 interrupts */
#define S32K3XX_IRQ_LPUART3 (S32K3XX_IRQ_EXTINT + 144) /* 144: LPUART3 interrupts */
#define S32K3XX_IRQ_LPUART4 (S32K3XX_IRQ_EXTINT + 145) /* 145: LPUART4 interrupts */
#define S32K3XX_IRQ_LPUART5 (S32K3XX_IRQ_EXTINT + 146) /* 146: LPUART5 interrupts */
#define S32K3XX_IRQ_LPUART6 (S32K3XX_IRQ_EXTINT + 147) /* 147: LPUART6 interrupts */
#define S32K3XX_IRQ_LPUART7 (S32K3XX_IRQ_EXTINT + 148) /* 148: LPUART7 interrupts */
#define S32K3XX_IRQ_LPUART8 (S32K3XX_IRQ_EXTINT + 149) /* 149: LPUART8 interrupts */
#define S32K3XX_IRQ_LPUART9 (S32K3XX_IRQ_EXTINT + 150) /* 150: LPUART9 interrupts */
#define S32K3XX_IRQ_LPUART10 (S32K3XX_IRQ_EXTINT + 151) /* 151: LPUART10 interrupts */
#define S32K3XX_IRQ_LPUART11 (S32K3XX_IRQ_EXTINT + 152) /* 152: LPUART11 interrupts */
#define S32K3XX_IRQ_LPUART12 (S32K3XX_IRQ_EXTINT + 153) /* 153: LPUART12 interrupts */
#define S32K3XX_IRQ_LPUART13 (S32K3XX_IRQ_EXTINT + 154) /* 154: LPUART13 interrupts */
#define S32K3XX_IRQ_LPUART14 (S32K3XX_IRQ_EXTINT + 155) /* 155: LPUART14 interrupts */
#define S32K3XX_IRQ_LPUART15 (S32K3XX_IRQ_EXTINT + 156) /* 156: LPUART15 interrupts */
#define S32K3XX_IRQ_RESERVED157 (S32K3XX_IRQ_EXTINT + 157) /* 157: Reserved */
#define S32K3XX_IRQ_RESERVED158 (S32K3XX_IRQ_EXTINT + 158) /* 158: Reserved */
#define S32K3XX_IRQ_RESERVED159 (S32K3XX_IRQ_EXTINT + 159) /* 159: Reserved */
#define S32K3XX_IRQ_RESERVED160 (S32K3XX_IRQ_EXTINT + 160) /* 160: Reserved */
#define S32K3XX_IRQ_LPI2C0 (S32K3XX_IRQ_EXTINT + 161) /* 161: LPI2C0 interrupts */
#define S32K3XX_IRQ_LPI2C1 (S32K3XX_IRQ_EXTINT + 162) /* 162: LPI2C1 interrupts */
#define S32K3XX_IRQ_RESERVED163 (S32K3XX_IRQ_EXTINT + 163) /* 163: Reserved */
#define S32K3XX_IRQ_RESERVED164 (S32K3XX_IRQ_EXTINT + 164) /* 164: Reserved */
#define S32K3XX_IRQ_LPSPI0 (S32K3XX_IRQ_EXTINT + 165) /* 165: LPSPI0 interrupt */
#define S32K3XX_IRQ_LPSPI1 (S32K3XX_IRQ_EXTINT + 166) /* 166: LPSPI1 interrupt */
#define S32K3XX_IRQ_LPSPI2 (S32K3XX_IRQ_EXTINT + 167) /* 167: LPSPI2 interrupt */
#define S32K3XX_IRQ_LPSPI3 (S32K3XX_IRQ_EXTINT + 168) /* 168: LPSPI3 interrupt */
#define S32K3XX_IRQ_LPSPI4 (S32K3XX_IRQ_EXTINT + 169) /* 169: LPSPI4 interrupt */
#define S32K3XX_IRQ_LPSPI5 (S32K3XX_IRQ_EXTINT + 170) /* 170: LPSPI5 interrupt */
#define S32K3XX_IRQ_RESERVED171 (S32K3XX_IRQ_EXTINT + 171) /* 171: Reserved */
#define S32K3XX_IRQ_RESERVED172 (S32K3XX_IRQ_EXTINT + 172) /* 172: Reserved */
#define S32K3XX_IRQ_QSPI (S32K3XX_IRQ_EXTINT + 173) /* 173: Quad SPI interrupts */
#define S32K3XX_IRQ_SAI0 (S32K3XX_IRQ_EXTINT + 174) /* 174: SAI0 interrupts */
#define S32K3XX_IRQ_SAI1 (S32K3XX_IRQ_EXTINT + 175) /* 175: SAI1 interrupts */
#define S32K3XX_IRQ_RESERVED176 (S32K3XX_IRQ_EXTINT + 176) /* 176: Reserved */
#define S32K3XX_IRQ_RESERVED177 (S32K3XX_IRQ_EXTINT + 177) /* 177: Reserved */
#define S32K3XX_IRQ_JDC (S32K3XX_IRQ_EXTINT + 178) /* 178: JTAG Data Communication interrupt */
#define S32K3XX_IRQ_RESERVED177 (S32K3XX_IRQ_EXTINT + 179) /* 179: Reserved */
#define S32K3XX_IRQ_ADC0 (S32K3XX_IRQ_EXTINT + 180) /* 180: ADC0 interrupts */
#define S32K3XX_IRQ_ADC1 (S32K3XX_IRQ_EXTINT + 181) /* 181: ADC1 interrupts */
#define S32K3XX_IRQ_ADC2 (S32K3XX_IRQ_EXTINT + 182) /* 182: ADC2 interrupts */
#define S32K3XX_IRQ_LPCMP0 (S32K3XX_IRQ_EXTINT + 183) /* 183: LPCMP0 interrupt */
#define S32K3XX_IRQ_LPCMP1 (S32K3XX_IRQ_EXTINT + 184) /* 184: LPCMP1 interrupt */
#define S32K3XX_IRQ_LPCMP2 (S32K3XX_IRQ_EXTINT + 185) /* 185: LPCMP2 interrupt */
#define S32K3XX_IRQ_RESERVED186 (S32K3XX_IRQ_EXTINT + 186) /* 186: Reserved */
#define S32K3XX_IRQ_RESERVED187 (S32K3XX_IRQ_EXTINT + 187) /* 187: Reserved */
#define S32K3XX_IRQ_RESERVED188 (S32K3XX_IRQ_EXTINT + 188) /* 188: Reserved */
#define S32K3XX_IRQ_FCCU0 (S32K3XX_IRQ_EXTINT + 189) /* 189: Fault Collection Control Unit interrupt 0 */
#define S32K3XX_IRQ_FCCU1 (S32K3XX_IRQ_EXTINT + 190) /* 190: Fault Collection Control Unit interrupt 1 */
#define S32K3XX_IRQ_STCU (S32K3XX_IRQ_EXTINT + 191) /* 191: Self-Test Control Unit interrupts */
#define S32K3XX_IRQ_MU0_MUB_EX0 (S32K3XX_IRQ_EXTINT + 192) /* 192: Messaging Unit 0, Interface B, exception 0 */
#define S32K3XX_IRQ_MU0_MUB_EX1 (S32K3XX_IRQ_EXTINT + 193) /* 193: Messaging Unit 0, Interface B, exception 1 */
#define S32K3XX_IRQ_MU0_MUB_EX2 (S32K3XX_IRQ_EXTINT + 194) /* 194: Messaging Unit 0, Interface B, exception 2 */
#define S32K3XX_IRQ_MU1_MUB_EX0 (S32K3XX_IRQ_EXTINT + 195) /* 195: Messaging Unit 1, Interface B, exception 0 */
#define S32K3XX_IRQ_MU1_MUB_EX1 (S32K3XX_IRQ_EXTINT + 196) /* 196: Messaging Unit 1, Interface B, exception 1 */
#define S32K3XX_IRQ_MU1_MUB_EX2 (S32K3XX_IRQ_EXTINT + 197) /* 197: Messaging Unit 1, Interface B, exception 2 */
#define S32K3XX_IRQ_RESERVED198 (S32K3XX_IRQ_EXTINT + 198) /* 198: Reserved */
#define S32K3XX_IRQ_RESERVED199 (S32K3XX_IRQ_EXTINT + 199) /* 199: Reserved */
#define S32K3XX_IRQ_RESERVED200 (S32K3XX_IRQ_EXTINT + 200) /* 200: Reserved */
#define S32K3XX_IRQ_RESERVED201 (S32K3XX_IRQ_EXTINT + 201) /* 201: Reserved */
#define S32K3XX_IRQ_MU2_MUA_EX0 (S32K3XX_IRQ_EXTINT + 202) /* 202: Messaging Unit 2, Interface A, exception 0 */
#define S32K3XX_IRQ_MU2_MUA_EX1 (S32K3XX_IRQ_EXTINT + 203) /* 203: Messaging Unit 2, Interface A, exception 1 */
#define S32K3XX_IRQ_MU2_MUA_EX2 (S32K3XX_IRQ_EXTINT + 204) /* 204: Messaging Unit 2, Interface A, exception 2 */
#define S32K3XX_IRQ_MU2_MUB_EX0 (S32K3XX_IRQ_EXTINT + 205) /* 205: Messaging Unit 2, Interface B, exception 0 */
#define S32K3XX_IRQ_MU2_MUB_EX1 (S32K3XX_IRQ_EXTINT + 206) /* 206: Messaging Unit 2, Interface B, exception 1 */
#define S32K3XX_IRQ_MU2_MUB_EX2 (S32K3XX_IRQ_EXTINT + 207) /* 207: Messaging Unit 2, Interface B, exception 2 */
#define S32K3XX_IRQ_RST_FCCU (S32K3XX_IRQ_EXTINT + 208) /* 208: FCCU failure to react interrupt */
#define S32K3XX_IRQ_RST_STCU (S32K3XX_IRQ_EXTINT + 209) /* 209: STCU critical failure interrupt */
#define S32K3XX_IRQ_RST_RGM (S32K3XX_IRQ_EXTINT + 210) /* 210: RGM functional reset escalation interrupt */
#define S32K3XX_IRQ_RST_CMU0 (S32K3XX_IRQ_EXTINT + 211) /* 211: CMU0 reset reaction interrupt */
#define S32K3XX_IRQ_RST_PLL_LOL (S32K3XX_IRQ_EXTINT + 212) /* 212: PLL Loss of Lock (LOL) interrupt */
#define S32K3XX_IRQ_RST_CORECLK (S32K3XX_IRQ_EXTINT + 213) /* 213: CORE_CLK_FAIL CMU reset reaction interrupt */
#define S32K3XX_IRQ_RESERVED214 (S32K3XX_IRQ_EXTINT + 214) /* 214: Reserved */
#define S32K3XX_IRQ_RST_AIPSPCLK (S32K3XX_IRQ_EXTINT + 215) /* 215: AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt */
#define S32K3XX_IRQ_RESERVED216 (S32K3XX_IRQ_EXTINT + 216) /* 216: Reserved */
#define S32K3XX_IRQ_RST_HSECLK (S32K3XX_IRQ_EXTINT + 217) /* 217: HSE_CLK_FAIL CMU reset reaction interrupt */
#define S32K3XX_IRQ_RST_CGMCLK (S32K3XX_IRQ_EXTINT + 218) /* 218: Clock Generation Module clkdiv failed */
#define S32K3XX_IRQ_RESERVED219 (S32K3XX_IRQ_EXTINT + 219) /* 219: Reserved */
#define S32K3XX_IRQ_RST_HSE (S32K3XX_IRQ_EXTINT + 220) /* 220: HSE Tamper interrupt */
#define S32K3XX_IRQ_RST_HSESNVS (S32K3XX_IRQ_EXTINT + 221) /* 221: HSE SNVS Tamper interrupt */
#define S32K3XX_IRQ_RST_MDMDAP (S32K3XX_IRQ_EXTINT + 222) /* 222: MDM DAP destructive reset interrupt */
#define S32K3XX_IRQ_RST_PIN (S32K3XX_IRQ_EXTINT + 223) /* 223: Pin reset interrupt */
#define S32K3XX_IRQ_RESERVED224 (S32K3XX_IRQ_EXTINT + 224) /* 224: Reserved */
#define S32K3XX_IRQ_RESERVED225 (S32K3XX_IRQ_EXTINT + 225) /* 225: Reserved */
#define S32K3XX_IRQ_RESERVED226 (S32K3XX_IRQ_EXTINT + 226) /* 226: Reserved */
#define S32K3XX_IRQ_RESERVED227 (S32K3XX_IRQ_EXTINT + 227) /* 227: Reserved */
#define S32K3XX_IRQ_RESERVED228 (S32K3XX_IRQ_EXTINT + 228) /* 228: Reserved */
#define S32K3XX_IRQ_RESERVED229 (S32K3XX_IRQ_EXTINT + 229) /* 229: Reserved */
#define S32K3XX_IRQ_RESERVED230 (S32K3XX_IRQ_EXTINT + 230) /* 230: Reserved */
#define S32K3XX_IRQ_RESERVED231 (S32K3XX_IRQ_EXTINT + 231) /* 231: Reserved */
#define S32K3XX_IRQ_NEXTINT (232)
#define S32K3XX_IRQ_NIRQS (S32K3XX_IRQ_EXTINT + S32K3XX_IRQ_NEXTINT)
/* Total number of IRQs */
#define NR_IRQS (S32K3XX_IRQ_NIRQS)
#endif /* __ARCH_ARM_INCLUDE_S32K3XX_S32K3X4_IRQ_H */

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############################################################################
# arch/arm/src/s32k3xx/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Copyright 2022 NXP
# Common ARM and Cortex-M7 files
include armv7-m/Make.defs
# Required S32K3 files
CHIP_ASRCS += startup.S
CHIP_CSRCS = s32k3xx_irq.c s32k3xx_clrpend.c s32k3xx_flashboot.c
CHIP_CSRCS += s32k3xx_start.c s32k3xx_lowputc.c s32k3xx_clockconfig.c
CHIP_CSRCS += s32k3xx_periphclocks.c s32k3xx_pin.c s32k3xx_pingpio.c
CHIP_CSRCS += s32k3xx_idle.c s32k3xx_allocateheap.c
# Configuration-dependent S32K3 files
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += s32k3xx_timerisr.c
endif
ifeq ($(CONFIG_S32K3XX_LPUART),y)
CHIP_CSRCS += s32k3xx_serial.c
endif
ifeq ($(CONFIG_S32K3XX_GPIOIRQ),y)
CHIP_CSRCS += s32k3xx_pinirq.c
endif
ifeq ($(CONFIG_S32K3XX_EDMA),y)
CHIP_CSRCS += s32k3xx_pindma.c
CHIP_CSRCS += s32k3xx_edma.c
endif
ifeq ($(CONFIG_S32K3XX_LPI2C),y)
CHIP_CSRCS += s32k3xx_lpi2c.c
endif
ifeq ($(CONFIG_S32K3XX_LPSPI),y)
CHIP_CSRCS += s32k3xx_lpspi.c
endif
ifeq ($(CONFIG_S32K3XX_ENET),y)
CHIP_CSRCS += s32k3xx_emac.c
endif
ifeq ($(CONFIG_S32K3XX_FLEXCAN),y)
CHIP_CSRCS += s32k3xx_flexcan.c
endif
ifeq ($(CONFIG_S32K3XX_FS26),y)
CHIP_CSRCS += s32k3xx_fs26.c
endif
ifeq ($(CONFIG_S32K3XX_QSPI),y)
CHIP_CSRCS += s32k3xx_qspi.c
endif
# Make sure that the S32K3 common directory in included in the VPATH
VPATH += chip/common
VPATH += chip/s32k3xx

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/****************************************************************************
* arch/arm/src/s32k3xx/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_CHIP_H
#define __ARCH_ARM_SRC_S32K3XX_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file.
* Other chip hardware files should then include this file for the proper
* setup.
*/
#include <arch/irq.h>
#include "hardware/s32k3xx_memorymap.h"
/* The common ARMv6/7-M vector handling logic expects the following
* definitions in this file.
* ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/s32k3xx/irq.h header file.
*/
#define ARMV6M_PERIPHERAL_INTERRUPTS S32K3XX_IRQ_NEXTINT
#define ARMV7M_PERIPHERAL_INTERRUPTS S32K3XX_IRQ_NEXTINT
/* Cache line sizes (in bytes)for the S32K3XX */
#define ARMV7M_DCACHE_LINESIZE 32 /* 4 bytes */
#define ARMV7M_ICACHE_LINESIZE 64 /* 8 bytes */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_S32K3XX_CHIP_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_AXBS_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_AXBS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* AXBS Register Offsets ****************************************************/
#define S32K3XX_AXBS_PRS0_OFFSET (0x0000) /* Priority Slave Register 0 (PRS0) */
#define S32K3XX_AXBS_CRS0_OFFSET (0x0010) /* Control Register 0 (CRS0) */
#define S32K3XX_AXBS_PRS1_OFFSET (0x0100) /* Priority Slave Register 1 (PRS1) */
#define S32K3XX_AXBS_CRS1_OFFSET (0x0110) /* Control Register 1 (CRS1) */
#define S32K3XX_AXBS_PRS2_OFFSET (0x0200) /* Priority Slave Register 2 (PRS2) */
#define S32K3XX_AXBS_CRS2_OFFSET (0x0210) /* Control Register 2 (CRS2) */
#define S32K3XX_AXBS_PRS3_OFFSET (0x0300) /* Priority Slave Register 3 (PRS3) */
#define S32K3XX_AXBS_CRS3_OFFSET (0x0310) /* Control Register 3 (CRS3) */
#define S32K3XX_AXBS_PRS4_OFFSET (0x0400) /* Priority Slave Register 4 (PRS4) */
#define S32K3XX_AXBS_CRS4_OFFSET (0x0410) /* Control Register 4 (CRS4) */
#define S32K3XX_AXBS_PRS5_OFFSET (0x0500) /* Priority Slave Register 5 (PRS5) */
#define S32K3XX_AXBS_CRS5_OFFSET (0x0510) /* Control Register 5 (CRS5) */
#define S32K3XX_AXBS_PRS6_OFFSET (0x0600) /* Priority Slave Register 6 (PRS6) */
#define S32K3XX_AXBS_CRS6_OFFSET (0x0610) /* Control Register 6 (CRS6) */
/* AXBS Register Addresses **************************************************/
#define S32K3XX_AXBS_PRS0 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS0_OFFSET)
#define S32K3XX_AXBS_CRS0 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS0_OFFSET)
#define S32K3XX_AXBS_PRS1 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS1_OFFSET)
#define S32K3XX_AXBS_CRS1 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS1_OFFSET)
#define S32K3XX_AXBS_PRS2 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS2_OFFSET)
#define S32K3XX_AXBS_CRS2 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS2_OFFSET)
#define S32K3XX_AXBS_PRS3 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS3_OFFSET)
#define S32K3XX_AXBS_CRS3 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS3_OFFSET)
#define S32K3XX_AXBS_PRS4 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS4_OFFSET)
#define S32K3XX_AXBS_CRS4 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS4_OFFSET)
#define S32K3XX_AXBS_PRS5 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS5_OFFSET)
#define S32K3XX_AXBS_CRS5 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS5_OFFSET)
#define S32K3XX_AXBS_PRS6 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS6_OFFSET)
#define S32K3XX_AXBS_CRS6 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS6_OFFSET)
/* AXBS Register Bitfield Definitions ***************************************/
/* Priority Slave Register n (PRSn) */
#define AXBS_PRS_M0_SHIFT (0) /* Bit 0-2: Master 0 Priority (M0) */
#define AXBS_PRS_M0_MASK (0x07 << AXBS_PRS_M0_SHIFT)
/* Bit 3: Reserved */
#define AXBS_PRS_M1_SHIFT (4) /* Bit 4-6: Master 1 Priority (M1) */
#define AXBS_PRS_M1_MASK (0x07 << AXBS_PRS_M1_SHIFT)
/* Bit 7: Reserved */
#define AXBS_PRS_M2_SHIFT (8) /* Bit 8-10: Master 2 Priority (M2) */
#define AXBS_PRS_M2_MASK (0x07 << AXBS_PRS_M2_SHIFT)
/* Bit 11: Reserved */
#define AXBS_PRS_M3_SHIFT (12) /* Bit 12-14: Master 3 Priority (M3) */
#define AXBS_PRS_M3_MASK (0x07 << AXBS_PRS_M3_SHIFT)
/* Bit 15: Reserved */
#define AXBS_PRS_M4_SHIFT (16) /* Bit 16-18: Master 4 Priority (M4) */
#define AXBS_PRS_M4_MASK (0x07 << AXBS_PRS_M4_SHIFT)
/* Bits 19-31: Reserved */
/* Control Register n (CRSn) */
#define AXBS_CRS_PARK_SHIFT (0) /* Bits 0-2: Determines which master port the slave parks on when (PARK) */
#define AXBS_CRS_PARK_MASK (0x07 << AXBS_CRS_PARK_SHIFT)
/* Bit 3: Reserved */
#define AXBS_CRS_PCTL_SHIFT (4) /* Bits 4-5: Parking Control (PCTL) */
#define AXBS_CRS_PCTL_MASK (0x03 << AXBS_CRS_PCTL_SHIFT)
# define AXBS_CRS_PCTL_PARK (0x00 << AXBS_CRS_PCTL_SHIFT) /* Slave port parks on the master port defined by the PARK bit field */
# define AXBS_CRS_PCTL_LAST (0x01 << AXBS_CRS_PCTL_SHIFT) /* Slave port parks on the last master port in control */
# define AXBS_CRS_PCTL_LPOW (0x02 << AXBS_CRS_PCTL_SHIFT) /* Low-power park */
/* Bits 7-6: Reserved */
#define AXBS_CRS_ARB_SHIFT (8) /* Bits 8-9: Arbitration Mode (ARB) */
#define AXBS_CRS_ARB_MASK (0x03 << AXBS_CRS_ARB_SHIFT)
# define AXBS_CRS_ARB_FIX (0x00 << AXBS_CRS_ARB_SHIFT) /* Fixed priority */
# define AXBS_CRS_ARB_RR (0x01 << AXBS_CRS_ARB_SHIFT) /* Round-robin (rotating) priority */
/* Bits 10-15: Reserved */
#define AXBS_CRS_HPE0 (1 << 16) /* Bit 16: High Priority Elevation 0 (HPE0) */
#define AXBS_CRS_HPE1 (1 << 17) /* Bit 17: High Priority Elevation 1 (HPE1) */
#define AXBS_CRS_HPE2 (1 << 18) /* Bit 18: High Priority Elevation 2 (HPE2) */
#define AXBS_CRS_HPE3 (1 << 19) /* Bit 19: High Priority Elevation 3 (HPE3) */
#define AXBS_CRS_HPE4 (1 << 20) /* Bit 20: High Priority Elevation 4 (HPE4) */
/* Bits 21-29: Reserved */
#define AXBS_CRS_HLP (1 << 30) /* Bit 30: Halt Low Priority (HLP) */
#define AXBS_CRS_RO (1 << 31) /* Bit 31: Read Only (RO) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_AXBS_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DCM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DCM Register Offsets *****************************************************/
#define S32K3XX_DCM_DCMSTAT_OFFSET (0x0000) /* DCM Status (DCMSTAT) */
#define S32K3XX_DCM_DCMLCC_OFFSET (0x0004) /* LC and LC Control (DCMLCC) */
#define S32K3XX_DCM_DCMLCS_OFFSET (0x0008) /* LC Scan Status (DCMLCS) */
#define S32K3XX_DCM_DCMMISC_OFFSET (0x001c) /* DCM Miscellaneous (DCMMISC) */
#define S32K3XX_DCM_DCMDEB_OFFSET (0x0020) /* Debug Status and Configuration (DCMDEB) */
#define S32K3XX_DCM_DCMEC_OFFSET (0x002c) /* DCF Error Count (DCMEC) */
#define S32K3XX_DCM_DCMSRR1_OFFSET (0x0030) /* DCF Scan Report 1 (DCMSRR1) */
#define S32K3XX_DCM_DCMSRR2_OFFSET (0x0034) /* DCF Scan Report 2 (DCMSRR2) */
#define S32K3XX_DCM_DCMSRR3_OFFSET (0x0038) /* DCF Scan Report 3 (DCMSRR3) */
#define S32K3XX_DCM_DCMSRR4_OFFSET (0x003c) /* DCF Scan Report 4 (DCMSRR4) */
#define S32K3XX_DCM_DCMSRR5_OFFSET (0x0040) /* DCF Scan Report 5 (DCMSRR5) */
#define S32K3XX_DCM_DCMSRR6_OFFSET (0x0044) /* DCF Scan Report 6 (DCMSRR6) */
#define S32K3XX_DCM_DCMSRR7_OFFSET (0x0048) /* DCF Scan Report 7 (DCMSRR7) */
#define S32K3XX_DCM_DCMSRR8_OFFSET (0x004c) /* DCF Scan Report 8 (DCMSRR8) */
#define S32K3XX_DCM_DCMSRR9_OFFSET (0x0050) /* DCF Scan Report 9 (DCMSRR9) */
#define S32K3XX_DCM_DCMSRR10_OFFSET (0x0054) /* DCF Scan Report 10 (DCMSRR10) */
#define S32K3XX_DCM_DCMSRR11_OFFSET (0x0058) /* DCF Scan Report 11 (DCMSRR11) */
#define S32K3XX_DCM_DCMSRR12_OFFSET (0x005c) /* DCF Scan Report 12 (DCMSRR12) */
#define S32K3XX_DCM_DCMSRR13_OFFSET (0x0060) /* DCF Scan Report 13 (DCMSRR13) */
#define S32K3XX_DCM_DCMSRR14_OFFSET (0x0064) /* DCF Scan Report 14 (DCMSRR14) */
#define S32K3XX_DCM_DCMSRR15_OFFSET (0x0068) /* DCF Scan Report 15 (DCMSRR15) */
#define S32K3XX_DCM_DCMSRR16_OFFSET (0x006c) /* DCF Scan Report 16 (DCMSRR16) */
#define S32K3XX_DCM_DCMLCS2_OFFSET (0x0080) /* LC Scan Status 2 (DCMLCS2) */
#define S32K3XX_DCM_GPR_DCMROD1_OFFSET (0x0200) /* Read Only GPR On Destructive Reset Register 1 (DCMROD1) */
#define S32K3XX_DCM_GPR_DCMROD3_OFFSET (0x0208) /* Read Only GPR On Destructive Reset Register 3 (DCMROD3) */
#define S32K3XX_DCM_GPR_DCMROD4_OFFSET (0x020c) /* Read Only GPR On Destructive Reset Register 4 (DCMROD4) */
#define S32K3XX_DCM_GPR_DCMROD5_OFFSET (0x0210) /* Read Only GPR On Destructive Reset Register 5 (DCMROD5) */
#define S32K3XX_DCM_GPR_DCMROF1_OFFSET (0x0300) /* Read Only GPR On Functional Reset Register 1 (DCMROF1) */
#define S32K3XX_DCM_GPR_DCMROF2_OFFSET (0x0304) /* Read Only GPR On Functional Reset Register 2 (DCMROF2) */
#define S32K3XX_DCM_GPR_DCMROF3_OFFSET (0x0308) /* Read Only GPR On Functional Reset Register 3 (DCMROF3) */
#define S32K3XX_DCM_GPR_DCMROF4_OFFSET (0x030c) /* Read Only GPR On Functional Reset Register 4 (DCMROF4) */
#define S32K3XX_DCM_GPR_DCMROF5_OFFSET (0x0310) /* Read Only GPR On Functional Reset Register 5 (DCMROF5) */
#define S32K3XX_DCM_GPR_DCMROF6_OFFSET (0x0314) /* Read Only GPR On Functional Reset Register 6 (DCMROF6) */
#define S32K3XX_DCM_GPR_DCMROF7_OFFSET (0x0318) /* Read Only GPR On Functional Reset Register 7 (DCMROF7) */
#define S32K3XX_DCM_GPR_DCMROF8_OFFSET (0x031c) /* Read Only GPR On Functional Reset Register 8 (DCMROF8) */
#define S32K3XX_DCM_GPR_DCMROF9_OFFSET (0x0320) /* Read Only GPR On Functional Reset Register 9 (DCMROF9) */
#define S32K3XX_DCM_GPR_DCMROF10_OFFSET (0x0324) /* Read Only GPR On Functional Reset Register 10 (DCMROF10) */
#define S32K3XX_DCM_GPR_DCMROF11_OFFSET (0x0328) /* Read Only GPR On Functional Reset Register 11 (DCMROF11) */
#define S32K3XX_DCM_GPR_DCMROF12_OFFSET (0x032c) /* Read Only GPR On Functional Reset Register 12 (DCMROF12) */
#define S32K3XX_DCM_GPR_DCMROF13_OFFSET (0x0330) /* Read Only GPR On Functional Reset Register 13 (DCMROF13) */
#define S32K3XX_DCM_GPR_DCMROF14_OFFSET (0x0334) /* Read Only GPR On Functional Reset Register 14 (DCMROF14) */
#define S32K3XX_DCM_GPR_DCMROF15_OFFSET (0x0338) /* Read Only GPR On Functional Reset Register 15 (DCMROF15) */
#define S32K3XX_DCM_GPR_DCMROF16_OFFSET (0x033c) /* Read Only GPR On Functional Reset Register 16 (DCMROF16) */
#define S32K3XX_DCM_GPR_DCMROF17_OFFSET (0x0340) /* Read Only GPR On Functional Reset Register 17 (DCMROF17) */
#define S32K3XX_DCM_GPR_DCMROF19_OFFSET (0x0348) /* Read Only GPR On Functional Reset Register 19 (DCMROF19) */
#define S32K3XX_DCM_GPR_DCMROF20_OFFSET (0x034c) /* Read Only GPR On Functional Reset Register 20 (DCMROF20) */
#define S32K3XX_DCM_GPR_DCMROF21_OFFSET (0x0350) /* Read Only GPR On Functional Reset Register 21 (DCMROF21) */
#define S32K3XX_DCM_GPR_DCMRWP1_OFFSET (0x0400) /* Read Write GPR On Power On Reset Register 1 (DCMRWP1) */
#define S32K3XX_DCM_GPR_DCMRWP3_OFFSET (0x0408) /* Read Write GPR On Power On Reset Register 3 (DCMRWP3) */
#define S32K3XX_DCM_GPR_DCMRWD2_OFFSET (0x0504) /* Read Write GPR On Destructive Reset Register 2 (DCMRWD2) */
#define S32K3XX_DCM_GPR_DCMRWD3_OFFSET (0x0508) /* Read Write GPR On Destructive Reset Register 3 (DCMRWD3) */
#define S32K3XX_DCM_GPR_DCMRWD4_OFFSET (0x050c) /* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */
#define S32K3XX_DCM_GPR_DCMRWD5_OFFSET (0x0510) /* Read Write GPR On Destructive Reset Register 5 (DCMRWD5) */
#define S32K3XX_DCM_GPR_DCMRWD6_OFFSET (0x0514) /* Read Write GPR On Destructive Reset Register 6 (DCMRWD6) */
#define S32K3XX_DCM_GPR_DCMRWD7_OFFSET (0x0518) /* Read Write GPR On Destructive Reset Register 7 (DCMRWD7) */
#define S32K3XX_DCM_GPR_DCMRWD8_OFFSET (0x051c) /* Read Write GPR On Destructive Reset Register 8 (DCMRWD8) */
#define S32K3XX_DCM_GPR_DCMRWD9_OFFSET (0x0520) /* Read Write GPR On Destructive Reset Register 9 (DCMRWD9) */
#define S32K3XX_DCM_GPR_DCMRWF1_OFFSET (0x0600) /* Read Write GPR On Functional Reset Register 1 (DCMRWF1) */
#define S32K3XX_DCM_GPR_DCMRWF2_OFFSET (0x0604) /* Read Write GPR On Functional Reset Register 2 (DCMRWF2) */
#define S32K3XX_DCM_GPR_DCMRWF4_OFFSET (0x060c) /* Read Write GPR On Functional Reset Register 4 (DCMRWF4) */
#define S32K3XX_DCM_GPR_DCMRWF5_OFFSET (0x0610) /* Read Write GPR On Functional Reset Register 5 (DCMRWF5) */
#define S32K3XX_DCM_GPR_DCMROPP1_OFFSET (0x0700) /* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */
#define S32K3XX_DCM_GPR_DCMROPP2_OFFSET (0x0704) /* Read Only GPR On PMCPOR Reset Register 2 (DCMROPP2) */
#define S32K3XX_DCM_GPR_DCMROPP3_OFFSET (0x0708) /* Read Only GPR On PMCPOR Reset Register 3 (DCMROPP3) */
#define S32K3XX_DCM_GPR_DCMROPP4_OFFSET (0x070c) /* Read Only GPR On PMCPOR Reset Register 4 (DCMROPP4) */
/* DCM Register Addresses ***************************************************/
#define S32K3XX_DCM_DCMSTAT (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSTAT_OFFSET)
#define S32K3XX_DCM_DCMLCC (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMLCC_OFFSET)
#define S32K3XX_DCM_DCMLCS (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMLCS_OFFSET)
#define S32K3XX_DCM_DCMMISC (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMMISC_OFFSET)
#define S32K3XX_DCM_DCMDEB (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMDEB_OFFSET)
#define S32K3XX_DCM_DCMEC (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMEC_OFFSET)
#define S32K3XX_DCM_DCMSRR1 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR1_OFFSET)
#define S32K3XX_DCM_DCMSRR2 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR2_OFFSET)
#define S32K3XX_DCM_DCMSRR3 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR3_OFFSET)
#define S32K3XX_DCM_DCMSRR4 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR4_OFFSET)
#define S32K3XX_DCM_DCMSRR5 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR5_OFFSET)
#define S32K3XX_DCM_DCMSRR6 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR6_OFFSET)
#define S32K3XX_DCM_DCMSRR7 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR7_OFFSET)
#define S32K3XX_DCM_DCMSRR8 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR8_OFFSET)
#define S32K3XX_DCM_DCMSRR9 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR9_OFFSET)
#define S32K3XX_DCM_DCMSRR10 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR10_OFFSET)
#define S32K3XX_DCM_DCMSRR11 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR11_OFFSET)
#define S32K3XX_DCM_DCMSRR12 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR12_OFFSET)
#define S32K3XX_DCM_DCMSRR13 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR13_OFFSET)
#define S32K3XX_DCM_DCMSRR14 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR14_OFFSET)
#define S32K3XX_DCM_DCMSRR15 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR15_OFFSET)
#define S32K3XX_DCM_DCMSRR16 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR16_OFFSET)
#define S32K3XX_DCM_DCMLCS2 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMLCS2_OFFSET)
#define S32K3XX_DCM_GPR_DCMROD1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD1_OFFSET)
#define S32K3XX_DCM_GPR_DCMROD3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD3_OFFSET)
#define S32K3XX_DCM_GPR_DCMROD4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD4_OFFSET)
#define S32K3XX_DCM_GPR_DCMROD5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD5_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF1_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF2_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF3_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF4_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF5_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF6 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF6_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF7 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF7_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF8 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF8_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF9 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF9_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF10 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF10_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF11 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF11_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF12 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF12_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF13 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF13_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF14 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF14_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF15 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF15_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF16 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF16_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF17 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF17_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF19 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF19_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF20 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF20_OFFSET)
#define S32K3XX_DCM_GPR_DCMROF21 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF21_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWP1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWP1_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWP3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWP3_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD2_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD3_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD4_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD5_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD6 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD6_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD7 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD7_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD8 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD8_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWD9 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD9_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWF1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF1_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWF2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF2_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWF4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF4_OFFSET)
#define S32K3XX_DCM_GPR_DCMRWF5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF5_OFFSET)
#define S32K3XX_DCM_GPR_DCMROPP1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP1_OFFSET)
#define S32K3XX_DCM_GPR_DCMROPP2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP2_OFFSET)
#define S32K3XX_DCM_GPR_DCMROPP3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP3_OFFSET)
#define S32K3XX_DCM_GPR_DCMROPP4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP4_OFFSET)
/* DCM Register Bitfield Definitions ****************************************/
/* DCM Status (DCMSTAT) */
#define DCM_DCMSTAT_DCMDONE (1 << 0) /* Bit 0: DCM Scanning Status (DCMDONE) */
#define DCM_DCMSTAT_DCMERR (1 << 1) /* Bit 1: DCM completion with error status (DCMERR) */
/* Bits 2-3: Reserved */
#define DCM_DCMSTAT_DCMLCST (1 << 4) /* Bit 4: LC Scanning Status (DCMLCST) */
/* Bits 5-7: Reserved */
#define DCM_DCMSTAT_DCMUTS (1 << 8) /* Bit 8: DCM UTEST DCF Scanning Status (DCMUTS) */
#define DCM_DCMSTAT_DCMOTAS (1 << 9) /* Bit 9: DCM OTA Scanning Status (DCMOTAS) */
#define DCM_DCMSTAT_DCMDBGPS (1 << 10) /* Bit 10: Debug Password Scanning Status (DCMDBGPS) */
/* Bits 11-31: Reserved */
/* LC and LC Control (DCMLCC) */
#define DCM_DCMLCC_DCMCLC_SHIFT (0) /* Bits 0-2: Current LC (DCMCLC) */
#define DCM_DCMLCC_DCMCLC_MASK (0x07 << DCM_DCMLCC_DCMCLC_SHIFT)
#define DCM_DCMLCC_DCMLCFN (1 << 3) /* Bit 3: Force LC (DCMLCFN) */
#define DCM_DCMLCC_DCMRLC_SHIFT (0) /* Bits 4-6: Real LC (DCMRLC) */
#define DCM_DCMLCC_DCMRLC_MASK (0x07 << DCM_DCMLCC_DCMRLC_SHIFT)
/* Bit 7: Reserved */
#define DCM_DCMLCC_DCMFLC_SHIFT (8) /* Bits 8-9: Force Next LC (DCMFLC) */
#define DCM_DCMLCC_DCMFLC_MASK (0x03 << DCM_DCMLCC_DCMFLC_SHIFT)
/* Bits 10-31: Reserved */
/* LC Scan Status (DCMLCS) */
#define DCM_DCMLCS_DCMLCSS1 (1 << 0) /* Bit 0: MCU_PROD Scan Status (DCMLCSS1) */
#define DCM_DCMLCS_DCMLCC1_SHIFT (1) /* Bits 1-3: MCU_PROD Marking (DCMLCC1) */
#define DCM_DCMLCS_DCMLCC1_MASK (0x07 << DCM_DCMLCS_DCMLCC1_SHIFT)
# define DCM_DCMLCS_DCMLCC1_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Not scanned yet */
# define DCM_DCMLCS_DCMLCC1_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Marked as active */
# define DCM_DCMLCS_DCMLCC1_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Marked as inactive */
# define DCM_DCMLCS_DCMLCC1_ERASED (0x03 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Region is erased/virgin */
# define DCM_DCMLCS_DCMLCC1_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Marked as inactive by an unknown pattern */
# define DCM_DCMLCS_DCMLCC1_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Scanning timed out */
#define DCM_DCMLCS_DCMLCE1 (1 << 4) /* Bit 4: MCU_PROD ECC Errors (DCMLCE1) */
#define DCM_DCMLCS_DCMLCFE1 (1 << 5) /* Bit 5: MCU_PROD Flash Memory Error Check (DCMLCFE1) */
#define DCM_DCMLCS_DCMLCSS2 (1 << 6) /* Bit 6: CUST_DEL Scan Status (DCMLCSS2) */
#define DCM_DCMLCS_DCMLCC2_SHIFT (7) /* Bits 7-9: CUST_DEL Marking (DCMLCC2) */
#define DCM_DCMLCS_DCMLCC2_MASK (0x07 << DCM_DCMLCS_DCMLCC2_SHIFT)
# define DCM_DCMLCS_DCMLCC2_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Not scanned yet */
# define DCM_DCMLCS_DCMLCC2_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Marked as active */
# define DCM_DCMLCS_DCMLCC2_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Marked as inactive */
# define DCM_DCMLCS_DCMLCC2_ERASED (0x03 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Region is erased/virgin */
# define DCM_DCMLCS_DCMLCC2_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Marked as inactive by an unknown pattern */
# define DCM_DCMLCS_DCMLCC2_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Scanning timed out */
#define DCM_DCMLCS_DCMLCE2 (1 << 10) /* Bit 10: CUST_DEL ECC Errors (DCMLCE2) */
#define DCM_DCMLCS_DCMLCFE2 (1 << 11) /* Bit 11: CUST_DEL Flash Memory Error Check (DCMLCFE2) */
#define DCM_DCMLCS_DCMLCSS3 (1 << 12) /* Bit 12: OEM_PROD Scan Status (DCMLCSS3) */
#define DCM_DCMLCS_DCMLCC3_SHIFT (13) /* Bits 13-15: OEM_PROD Marking (DCMLCC3) */
#define DCM_DCMLCS_DCMLCC3_MASK (0x07 << DCM_DCMLCS_DCMLCC3_SHIFT)
# define DCM_DCMLCS_DCMLCC3_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Not scanned yet */
# define DCM_DCMLCS_DCMLCC3_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Marked as active */
# define DCM_DCMLCS_DCMLCC3_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Marked as inactive */
# define DCM_DCMLCS_DCMLCC3_ERASED (0x03 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Region is erased/virgin */
# define DCM_DCMLCS_DCMLCC3_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Marked as inactive by an unknown pattern */
# define DCM_DCMLCS_DCMLCC3_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Scanning timed out */
#define DCM_DCMLCS_DCMLCE3 (1 << 16) /* Bit 16: OEM_PROD ECC Errors (DCMLCE3) */
#define DCM_DCMLCS_DCMLCFE3 (1 << 17) /* Bit 17: OEM_PROD Flash Memory Error Check (DCMLCFE3) */
#define DCM_DCMLCS_DCMLCSS4 (1 << 18) /* Bit 18: IN_FIELD Scan Status (DCMLCSS4) */
#define DCM_DCMLCS_DCMLCC4_SHIFT (19) /* Bits 19-21: IN_FIELD Marking (DCMLCC4) */
#define DCM_DCMLCS_DCMLCC4_MASK (0x07 << DCM_DCMLCS_DCMLCC4_SHIFT)
# define DCM_DCMLCS_DCMLCC4_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Not scanned yet */
# define DCM_DCMLCS_DCMLCC4_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Marked as active */
# define DCM_DCMLCS_DCMLCC4_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Marked as inactive */
# define DCM_DCMLCS_DCMLCC4_ERASED (0x03 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Region is erased/virgin */
# define DCM_DCMLCS_DCMLCC4_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Marked as inactive by an unknown pattern */
# define DCM_DCMLCS_DCMLCC4_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Scanning timed out */
#define DCM_DCMLCS_DCMLCE4 (1 << 22) /* Bit 22: IN_FIELD ECC Errors (DCMLCE4) */
#define DCM_DCMLCS_DCMLCFE4 (1 << 23) /* Bit 23: IN_FIELD Flash Memory Error Check (DCMLCFE4) */
#define DCM_DCMLCS_DCMLCSS5 (1 << 24) /* Bit 24: Pre-FA Scan Status (DCMLCSS5) */
#define DCM_DCMLCS_DCMLCC5_SHIFT (25) /* Bits 25-27: Pre-FA Marking (DCMLCC5) */
#define DCM_DCMLCS_DCMLCC5_MASK (0x07 << DCM_DCMLCS_DCMLCC5_SHIFT)
# define DCM_DCMLCS_DCMLCC5_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Not scanned yet */
# define DCM_DCMLCS_DCMLCC5_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Marked as active */
# define DCM_DCMLCS_DCMLCC5_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Marked as inactive */
# define DCM_DCMLCS_DCMLCC5_ERASED (0x03 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Region is erased/virgin */
# define DCM_DCMLCS_DCMLCC5_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Marked as inactive by an unknown pattern */
# define DCM_DCMLCS_DCMLCC5_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Scanning timed out */
#define DCM_DCMLCS_DCMLCE5 (1 << 28) /* Bit 28: Pre-FA ECC Errors (DCMLCE5) */
#define DCM_DCMLCS_DCMLCFE5 (1 << 29) /* Bit 29: Pre-FA Flash Memory Error Check (DCMLCFE5) */
/* Bits 30-31: Reserved */
/* DCM Miscellaneous (DCMMISC) */
/* Bits 0-9: Reserved */
#define DCM_DCMMISC_DCMDBGT (1 << 10) /* Bit 10: DBG Section Error (DCMDBGT) */
#define DCM_DCMMISC_DCMDBGE (1 << 11) /* Bit 11: DCM ECC error on DBG sections (DCMDBGE) */
/* Bits 12-27: Reserved */
#define DCM_DCMMISC_DCMCERS (1 << 28) /* Bits 28: DCF Client Errors (DCMCERS) */
/* Bit 29: Reserved */
#define DCM_DCMMISC_MRKLSTRCHK (1 << 30) /* Bit 30: MRK Local Storage Check (MRKLSTRCHK) */
/* Bit 31: Reserved */
/* Debug Status and Configuration (DCMDEB) */
/* Bit 0: Reserved */
#define DCM_DCMDEB_DCM_APPDBG_STAT (1 << 1) /* Bit 1: DCM Authentication Engine Status (DCM_APPDBG_STAT) */
/* Bits 2-15: Reserved */
#define DCM_DCMDEB_APPDBG_STAT_SOC (1 << 16) /* Bit 16: Application Debug Status (APPDBG_STAT_SOC) */
/* Bits 17-31: Reserved */
/* DCF Error Count (DCMEC) */
#define DCM_DCMEC_DCMECT_SHIFT (0) /* Bits 0-15: Error Count (DCMECT) */
#define DCM_DCMEC_DCMECT_MASK (0xffff << DCM_DCMEC_DCMECT_SHIFT)
/* Bits 16-31: Reserved */
/* DCF Scan Report (DCMSRRn) */
#define DCM_DCMSSR_DCMDCFE_SHIFT (0) /* Bits 0-20: Flash Memory Address (DCMDCFE1) */
#define DCM_DCMSSR_DCMDCFE_MASK (0x1fffff << DCM_DCMSSR1_DCMDCFE1_SHIFT)
/* Bits 21-23: Reserved */
#define DCM_DCMSSR_DCMDCFF_SHIFT (24) /* Bits 24-26: DCF Record Location (DCMDCFF1) */
#define DCM_DCMSSR_DCMDCFF_MASK (0x1fffff << DCM_DCMSSR1_DCMDCFE1_SHIFT)
#define DCM_DCMSSR_DCMESF (1 << 27) /* Bit 27: Flash Memory Error (DCMESF1) */
#define DCM_DCMSSR_DCMESD (1 << 28) /* Bit 28: Chip Side Error (DCMESD1) */
#define DCM_DCMSSR_DCMDCFT (1 << 29) /* Bit 29: Scanning Timeout On Flash Memory (DCMDCFT1) */
/* Bit 30-31: Reserved */
/* LC Scan Status 2 (DCMLCS2) */
#define DCM_DCMLCS2_DCMLCSS6 (1 << 0) /* Bit 0: FA Scan Status (DCMLCSS6) */
#define DCM_DCMLCS2_DCMLCC6_SHIFT (1) /* Bits 1-3: FA Marking (DCMLCC6) */
#define DCM_DCMLCS2_DCMLCC6_MASK (0x07 << DCM_DCMLCS2_DCMLCC6_SHIFT)
# define DCM_DCMLCS2_DCMLCC6_NOSCAN (0x00 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Not scanned yet */
# define DCM_DCMLCS2_DCMLCC6_ACTIVE (0x01 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Marked as active */
# define DCM_DCMLCS2_DCMLCC6_INACTIVE (0x02 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Marked as inactive */
# define DCM_DCMLCS2_DCMLCC6_ERASED (0x03 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Region is erased/virgin */
# define DCM_DCMLCS2_DCMLCC6_UNKNOWN (0x05 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Marked as inactive by an unknown pattern */
# define DCM_DCMLCS2_DCMLCC6_TIMEOUT (0x06 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Scanning timed out */
#define DCM_DCMLCS2_DCMLCE6 (1 << 4) /* Bit 4: FA ECC Errors (DCMLCE6) */
#define DCM_DCMLCS2_DCMLCFE6 (1 << 5) /* Bit 5: Flash Memory Error Check (DCMLCFE6) */
/* Bits 6-31: Reserved */
/* Read Only GPR On Destructive Reset Register 1 (DCMROD1) */
#define DCM_GPR_DCMROD1_PCU_ISO_STATUS (1 << 0) /* Bit 0: PCU Input Isolation status on previous standb entry (PCU_ISO_STATUS) */
#define DCM_GPR_DCMROD1_HSE_DCF_VIO (1 << 1) /* Bit 1: DCF violation from HSE (HSE_DCF_VIO) */
#define DCM_GPR_DCMROD1_KEY_RESP_READY (1 << 2) /* Bit 2: Key Response Ready (KEY_RESP_READY) */
/* Bits 3-31: Reserved */
/* Read Only GPR On Destructive Reset Register 3 (DCMROD3) */
#define DCM_GPR_DCMROD3_CM7_0_LOCKUP (1 << 0) /* Bit 0: CM7_0 Core Lockup Status (CM7_0_LOCKUP) */
#define DCM_GPR_DCMROD3_CM7_1_LOCKUP (1 << 1) /* Bit 0: CM7_1 Core Lockup Status (CM7_1_LOCKUP) */
#define DCM_GPR_DCMROD3_HSE_LOCKUP (1 << 2) /* Bit 2: HSE Core Lockup Status (HSE_LOCKUP) */
#define DCM_GPR_DCMROD3_CM7_RCCU1_ALARM (1 << 3) /* Bit 3: Cortex M7 Cores Lockstep Error Status (CM7_RCCU1_ALARM) */
#define DCM_GPR_DCMROD3_CM7_RCCU2_ALARM (1 << 4) /* Bit 4: Cortex M7 Cores Redundant Lockstep Error Status (CM7_RCCU2_ALARM) */
#define DCM_GPR_DCMROD3_TCM_GSKT_ALARM (1 << 5) /* Bit 5: TCM IAHB Gasket Monitor Alarm Status (TCM_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM (1 << 6) /* Bit 6: Status of IAHB gasket safety alarm from DMA system AXBS IAHB gasket (DMA_SYS_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM (1 << 7) /* Bit 7: Status of IAHB gasket safety alarm from DMA periph AXBS IAHB gasket (DMA_PERIPH_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_SYS_AXBS_ALARM (1 << 8) /* Bit 8: System AXBS Safety Alarm Status (SYS_AXBS_ALARM) */
#define DCM_GPR_DCMROD3_DMA_AXBS_ALARM (1 << 9) /* Bit 9: DMA AXBS_Lite Safety Alarm Status (DMA_AXBS_ALARM) */
/* Bit 10: Reserved */
#define DCM_GPR_DCMROD3_HSE_GSKT_ALARM (1 << 11) /* Bit 11: HSE IAHB Gasket Alarm Status (HSE_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_QSPI_GSKT_ALARM (1 << 12) /* Bit 12: QSPI IAHB Gasket Alarm Status (QSPI_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM (1 << 13) /* Bit 13: AIPS1 IAHB Gasket Alarm Status (AIPS1_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM (1 << 14) /* Bit 14: AIPS2 IAHB Gasket Alarm Status (AIPS2_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_ADDR_EDC_ERR (1 << 15) /* Bit 15: Status of integrity error on addresses for safety (ADDR_EDC_ERR) */
#define DCM_GPR_DCMROD3_DATA_EDC_ERR (1 << 16) /* Bit 16: Status of integrity error on data for safety (DATA_EDC_ERR) */
#define DCM_GPR_DCMROD3_TCM_AXBS_ALARM (1 << 17) /* Bit 17: TCM AHB Splitter Safety Alarm Status (TCM_AXBS_ALARM) */
#define DCM_GPR_DCMROD3_EMAC_GSKT_ALARM (1 << 18) /* Bit 18: EMAC IAHB Gasket Alarm Status (EMAC_GSKT_ALARM) */
#define DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM (1 << 19) /* Bit 19: PERIPH AXBS_Lite Safety Alarm Status (PERIPH_AXBS_ALARM) */
/* Bits 20-21: Reserved */
#define DCM_GPR_DCMROD3_LC_ERR (1 << 22) /* Bit 22: Error in Lifecycle Scanning (LC_ERR) */
/* Bit 23: Reserved */
#define DCM_GPR_DCMROD3_PRAM1_ECC_ERR (1 << 24) /* Bit 24: Multi bit ECC error from SRAM1 (PRAM1_ECC_ERR) */
#define DCM_GPR_DCMROD3_PRAM0_ECC_ERR (1 << 25) /* Bit 25: Multi bit ECC error from SRAM0 (PRAM0_ECC_ERR) */
#define DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR (1 << 26) /* Bit 26: Multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR) */
#define DCM_GPR_DCMROD3_CM7_1_DCDATA_ECC_ERR (1 << 27) /* Bit 27: Multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR) */
#define DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR (1 << 28) /* Bit 28: Multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR) */
#define DCM_GPR_DCMROD3_CM7_1_DCTAG_ECC_ERR (1 << 29) /* Bit 29: Multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR) */
#define DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR (1 << 30) /* Bit 30: Multi bit ECC error from CM7_0 ICache data memory (CM7_0_ICDATA_ECC_ERR) */
#define DCM_GPR_DCMROD3_CM7_1_ICDATA_ECC_ERR (1 << 31) /* Bit 31: Multi bit ECC error from CM7_1 ICache data memory (CM7_1_ICDATA_ECC_ERR) */
/* Read Only GPR On Destructive Reset Register 4 (DCMROD4) */
#define DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR (1 << 0) /* Bit 0: Multi bit ECC error from CM7_0 ICache tag memory (CM7_0_ICTAG_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_1_ICTAG_ECC_ERR (1 << 1) /* Bit 1: Multi bit ECC error from CM7_1 ICache tag memory (CM7_1_ICTAG_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR (1 << 2) /* Bit 2: Uncorrectable ECC error reported from CM7_0 Instruction TCM memory (CM7_0_ITCM_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR (1 << 3) /* Bit 3: Uncorrectable ECC error reported from CM7_0 Data TCM memory block 0 (CM7_0_DTCM0_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR (1 << 4) /* Bit 4: Uncorrectable ECC error reported from CM7_1 Data TCM memory block 1 (CM7_0_DTCM1_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR (1 << 5) /* Bit 5: Uncorrectable ECC error reported from CM7_1 Instruction TCM memory (CM7_1_ITCM_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR (1 << 6) /* Bit 6: Uncorrectable ECC error reported from CM7_1 Data TCM memory block 0 (CM7_1_DTCM0_ECC_ERR) */
#define DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR (1 << 7) /* Bit 7: Uncorrectable ECC error reported from CM7_1 Data TCM memory block 1 (CM7_1_DTCM1_ECC_ERR) */
#define DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR (1 << 8) /* Bit 8: Uncorrectable ECC error reported from DMA_TCD memory (DMA_TCD_RAM_ECC_ERR) */
#define DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM (1 << 9) /* Bit 9: Status of PRAM0 safety alarm (PRAM0_FCCU_ALARM) */
#define DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM (1 << 10) /* Bit 10: Status of PRAM1 safety alarm (PRAM1_FCCU_ALARM) */
#define DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR (1 << 11) /* Bit 11: HSE RAM Uncorrectable ECC status (HSE_RAM_ECC_ERR) */
#define DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR (1 << 12) /* Bit 12: Flash0 Code ECC Uncorrectable Error (PF0_CODE_ECC_ERR) */
#define DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR (1 << 13) /* Bit 13: Flash0 Data ECC Uncorrectable Error (PF0_DATA_ECC_ERR) */
#define DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR (1 << 14) /* Bit 14: Flash1 Code ECC Uncorrectable Error (PF1_CODE_ECC_ERR) */
#define DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR (1 << 15) /* Bit 15: Flash1 Data ECC Uncorrectable Error (PF1_DATA_ECC_ERR) */
#define DCM_GPR_DCMROD4_PF2_CODE_ECC_ERR (1 << 16) /* Bit 16: Flash2 Code ECC Uncorrectable Error (PF2_CODE_ECC_ERR) */
#define DCM_GPR_DCMROD4_PF2_DATA_ECC_ERR (1 << 17) /* Bit 17: Flash2 Data ECC Uncorrectable Error (PF2_DATA_ECC_ERR) */
#define DCM_GPR_DCMROD4_FLASH_EDC_ERR (1 << 18) /* Bit 18: Status of flash ECC correction error through EDC reported by FMU (FLASH_EDC_ERR) */
#define DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR (1 << 19) /* Bit 19: Flash Address Encode Error (FLASH_ADDR_ENC_ERR) */
#define DCM_GPR_DCMROD4_FLASH_REF_ERR (1 << 20) /* Bit 20: Flash reference current loss or read voltage error while previous read(s) (FLASH_REF_ERR) */
#define DCM_GPR_DCMROD4_FLASH_RST_ERR (1 << 21) /* Bit 21: Flash Reset Error Status (FLASH_RST_ERR) */
#define DCM_GPR_DCMROD4_FLASH_SCAN_ERR (1 << 22) /* Bit 22: Error while DCM flash scanning process due to invalid data (FLASH_SCAN_ERR) */
/* Bit 23: Reserved */
#define DCM_GPR_DCMROD4_FLASH_ECC_ERR (1 << 24) /* Bit 24: ECC Error from Flash Controller (FLASH_ECC_ERR) */
#define DCM_GPR_DCMROD4_FLASH_ACCESS_ERR (1 << 25) /* Bit 25: Transaction Monitor Mismatch Error from Flash Controller (FLASH_ACCESS_ERR) */
#define DCM_GPR_DCMROD4_VDD1P1_GNG_ERR (1 << 26) /* Bit 26: Go/no-go indicator for VDD1PD1 (double bond) supply going to PLL (VDD1P1_GNG_ERR) */
#define DCM_GPR_DCMROD4_VDD2P5_GNG_ERR (1 << 27) /* Bit 27: Go/no-go indicator for VDD_HV_FLA (double bond) supply going to FXOSC and PLL (VDD2P5_GNG_ERR) */
/* Bit 28: Reserved */
#define DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR (1 << 29) /* Bit 29: Accidental Partial Test Activation (TEST_ACTIVATION_0_ERR) */
#define DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR (1 << 30) /* Bit 30: Accidental Partial Test Activation (TEST_ACTIVATION_1_ERR) */
/* Bit 31: Reserved */
/* Read Only GPR On Destructive Reset Register 5 (DCMROD5) */
/* Bit 0: Reserved */
#define DCM_GPR_DCMROD5_INTM_0_ERR (1 << 1) /* Bit 1: Interrupt monitor0 error reported by INTM (INTM_0_ERR) */
#define DCM_GPR_DCMROD5_INTM_1_ERR (1 << 2) /* Bit 2: Interrupt monitor1 error reported by INTM (INTM_0_ERR) */
#define DCM_GPR_DCMROD5_INTM_2_ERR (1 << 3) /* Bit 3: Interrupt monitor2 error reported by INTM (INTM_0_ERR) */
#define DCM_GPR_DCMROD5_INTM_3_ERR (1 << 4) /* Bit 4: Interrupt monitor3 error reported by INTM (INTM_0_ERR) */
#define DCM_GPR_DCMROD5_SW_NCF_0 (1 << 5) /* Bit 5: Status of DCMRWF1[FCCU_SW_NCF0] (SW_NCF_0) */
#define DCM_GPR_DCMROD5_SW_NCF_1 (1 << 6) /* Bit 6: Status of DCMRWF1[FCCU_SW_NCF1] (SW_NCF_1) */
#define DCM_GPR_DCMROD5_SW_NCF_2 (1 << 7) /* Bit 7: Status of DCMRWF1[FCCU_SW_NCF2] (SW_NCF_2) */
#define DCM_GPR_DCMROD5_SW_NCF_3 (1 << 8) /* Bit 8: Status of DCMRWF1[FCCU_SW_NCF3] (SW_NCF_3) */
#define DCM_GPR_DCMROD5_STCU_NCF (1 << 9) /* Bit 9: STCU non-critical fault / BIST result error (STCU_NCF) */
#define DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR (1 << 10) /* Bit 10: Indicates an accidental backdoor access on memories (MBIST_ACTIVATION_ERR) */
#define DCM_GPR_DCMROD5_STCU_BIST_USER_CF (1 << 11) /* Bit 11: L/M BIST enabled accidentally (STCU_BIST_USER_CF) */
#define DCM_GPR_DCMROD5_MTR_BUS_ERR (1 << 12) /* Bit 12: Fault reported due to illegal access on MTR (MTR_BUS_ERR) */
#define DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR (1 << 13) /* Bit 13: Monitoring of unintended debug activation (DEBUG_ACTIVATION_ERR) */
#define DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR (1 << 14) /* Bit 14: Integrity (EDC) error on TCM read data for safety (TCM_RDATA_EDC_ERR) */
#define DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR (1 << 15) /* Bit 15: Integrity (EDC) error on EMAC read data for safety (EMAC_RDATA_EDC_ERR) */
/* Bit 16: Reserved */
#define DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR (1 << 17) /* Bit 17: Integrity (EDC) error on eDMA read data for safety (DMA_RDATA_EDC_ERR) */
#define DCM_GPR_DCMROD5_CM7_1_AHBP_RDATA_EDC_ERR (1 << 18) /* Bit 18: Integrity error on CM7_1 peripheral read data for safety (CM7_1_AHBP_RDATA_EDC_ERR) */
#define DCM_GPR_DCMROD5_CM7_1_AHBM_RDATA_EDC_ERR (1 << 19) /* Bit 19: Integrity error on CM7_1 main read data for safety (CM7_1_AHBM_RDATA_EDC_ERR) */
#define DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR (1 << 20) /* Bit 18: Integrity error on CM7_0 peripheral read data for safety (CM7_0_AHBP_RDATA_EDC_ERR) */
#define DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR (1 << 21) /* Bit 19: Integrity error on CM7_0 main read data for safety (CM7_0_AHBM_RDATA_EDC_ERR) */
#define DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR (1 << 22) /* Bit 22: Integrity (EDC) error on HSE read data for safety (HSE_RDATA_EDC_ERR) */
/* Bits 23-31: Reserved */
/* Read Only GPR On Functional Reset Register 1 (DCMROF1) */
#define DCM_GPR_DCMROF1_EMAC_MDC_CHID_0 (1 << 0) /* Bit 0: EMAC DMA Channel ID0 Status (EMAC_MDC_CHID_0) */
#define DCM_GPR_DCMROF1_EMAC_MDC_CHID_1 (1 << 1) /* Bit 1: EMAC DMA Channel ID0 Status (EMAC_MDC_CHID_0) */
/* Bits 2-31: Reserved */
/* Read Only GPR On Functional Reset Register n (DCMROFn, n=2..17) */
#define DCM_GPR_DCMROF2_17_DCF_SDID_SHIFT (0) /* Bits 0-31: Configuration bits of DCF client SDID x (DCF_SDIDx) */
#define DCM_GPR_DCMROF2_17_DCF_SDID_MASK (0xffffffff << DCM_GPR_DCMROF2_17_DCF_SDID_SHIFT)
/* Read Only GPR On Functional Reset Register 19 (DCMROF19) */
/* Bits 0-28: Reserved */
#define DCM_GPR_DCMROF19_LOCKSTEP_EN (1 << 29) /* Bit 29: Lockstep Enable (LOCKSTEP_EN) */
#define DCM_GPR_DCMROF19_DCM_DONE (1 << 30) /* Bit 30: DCM Done (DCM_DONE) */
#define DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED (1 << 31) /* Bit 31: FCCU EOUT Dedicated (FCCU_EOUT_DEDICATED) */
/* Read Only GPR On Functional Reset Register 20 (DCMROF20) */
#define DCM_GPR_DCMROF20_POR_WDG_EN (1 << 0) /* Bit 0: Indicates the status of POR_WDG as configured in DCF record (POR_WDG_EN) */
#define DCM_GPR_DCMROF20_LMAUTO_DIS (1 << 1) /* Bit 1: PMC last mile automatic crossover from boot regulation feature support (LMAUTO_DIS) */
#define DCM_GPR_DCMROF20_CM7_TCM_WS_EN (1 << 2) /* Bit 2: Status of CM7 DTCM and ITCM waitstates as configured in DCF record (CM7_TCM_WS_EN) */
#define DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP (1 << 3) /* Bit 3: Status of DMA AXBS IAHB gasket as configured in DCF record (DMA_AXBS_IAHB_BYP) */
/* Bit 4: Reserved */
#define DCM_GPR_DCMROF20_QSPI_IAHB_BYP (1 << 5) /* Bit 5: Status of QSPI IAHB gasket as configured in DCF record (QSPI_IAHB_BYP) */
#define DCM_GPR_DCMROF20_AIPS_IAHB_BYP (1 << 6) /* Bit 6: Status of AIPS1/2 IAHB gasket as configured in DCF record (AIPS_IAHB_BYP) */
/* Bits 7-17: Reserved */
#define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT (18) /* Bits 18-31: Destructive Reset Escalation (DCF_DEST_RST_ESC) */
#define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_MASK (0x3fff << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT)
# define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_DIS (0x0000 << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT) /* Destructive Reset Escalation disabled */
# define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_EN (0x0001 << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT) /* Destructive Rest Escalation enabled */
/* Read Only GPR On Functional Reset Register 21 (DCMROF21) */
#define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT (0) /* Bits 0-17: Destructive Reset Escalation (DCF_DEST_RST_ESC) */
#define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_MASK (0x03ffff << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT)
# define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_DIS (0x000000 << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT) /* Destructive Reset Escalation disabled */
# define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_EN (0x000001 << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT) /* Destructive Rest Escalation enabled */
/* Bit 18: Reserved */
#define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT (19) /* Bits 19-20: HSE Clock Mode Option (HSE_CLK_MODE_OPTION) */
#define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_MASK (0x03 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT)
# define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_A (0x00 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT) /* Applicable for clocking option A */
# define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_CDEF (0x01 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT) /* Applicable for clocking options C, D, E, E2 and F */
# define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_B (0x02 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT) /* Applicable for clocking option B */
/* Read Write GPR On Power On Reset Register 1 (DCMRWP1) */
/* Bits 0-2: Reserved */
#define DCM_GPR_DCMRWP1_CLKOUT_STANDBY (1 << 3) /* Bit 3: Clockout standby expose over functional and destructive reset (CLKOUT_STANDBY) */
/* Bits 4-7: Reserved */
#define DCM_GPR_DCMRWP1_STANDBY_PWDOG_DIS (1 << 8) /* Bit 8: Disables the standby entry and exit monitoring window of the POR WDOG (STANDBY_PWDOG_DIS) */
#define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT (9) /* Bits 9-10: Trims for POR WDG timeout value (POR_WDOG_TRIM) */
#define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_MASK (0x03 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT)
# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_6_25MS (0x00 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 06.25ms */
# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_12_5MS (0x01 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 12.50ms */
# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_25MS (0x02 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 25.00ms */
# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_50MS (0x03 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 50.00ms */
/* Bits 11-31: Reserved */
/* Read Write GPR On Power On Reset Register 3 (DCMRWP3) */
/* Bits 0-8: Reserved */
#define DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI (1 << 9) /* Bit 9: Configures a destructive reset to interrupt (DEST_RST9_AS_IPI) */
/* Bits 10-31: Reserved */
/* Read Write GPR On Destructive Reset Register 2 (DCMRWD2) */
/* Bits 0-6: Reserved */
#define DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST (1 << 7) /* Bit 7: Controls the EOUT state during selftest (EOUT_STAT_DUR_STEST) */
/* Bits 8-31: Reserved */
/* Read Write GPR On Destructive Reset Register 3 (DCMRWD3) */
#define DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN (1 << 0) /* Bit 0: Enable fault monitoring at FCCU NCF 0 for CM7_0 core lockup (CM7_0_LOCKUP_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_LOCKUP_EN (1 << 1) /* Bit 1: Enable fault monitoring at FCCU NCF 0 for CM7_1 core lockup (CM7_1_LOCKUP_EN) */
/* Bit 2: Reserved */
#define DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN (1 << 3) /* Bit 3: Enable fault monitoring at FCCU NCF 0 for Cortex M7 cores lockstep error (CM7_RCCU1_ALARM_EN) */
#define DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN (1 << 4) /* Bit 4: Enable fault monitoring at FCCU NCF 0 for Cortex M7 cores redundant lockstep error (CM7_RCCU2_ALARM_EN) */
#define DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN (1 << 5) /* Bit 5: Enable fault monitoring at FCCU NCF 1 for TCM IAHB Gasket monitor alarm (TCM_GSKT_ALRM_EN) */
#define DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN (1 << 6) /* Bit 6: Enable fault monitoring at FCCU NCF 1 for IAHB gasket safety alarm from DMA system AXBS IAHB gasket (DMA_SYS_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN (1 << 7) /* Bit 7: Enable fault monitoring at FCCU NCF 1 for IAHB gasket safety alarm from DMA periph AXBS IAHB gasket (DMA_PERIPH_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN (1 << 8) /* Bit 8: Enable fault monitoring at FCCU NCF 1 for system AXBS safety alarm (SYS_AXBS_ALARM_EN) */
#define DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN (1 << 9) /* Bit 9: Enable fault monitoring at FCCU NCF 1 for DMA AXBS_Lite safety alarm (DMA_AXBS_ALARM_EN) */
/* Bit 10: Reserved */
#define DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN (1 << 11) /* Bit 11: Enable fault monitoring at FCCU NCF 1 for HSE IAHB gasket alarm (HSE_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN (1 << 12) /* Bit 12: Enable fault monitoring at FCCU NCF 1 for QSPI IAHB gasket alarm (QSPI_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN (1 << 13) /* Bit 13: Enable fault monitoring at FCCU NCF 1 for AIPS1 IAHB gasket alarm (AIPS1_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN (1 << 14) /* Bit 14: Enable fault monitoring at FCCU NCF 1 for AIPS2 IAHB gasket alarm (AIPS2_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN (1 << 15) /* Bit 15: Enable fault monitoring at FCCU NCF 1 for integrity error on address for safety (ADDR_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN (1 << 16) /* Bit 16: Enable fault monitoring at FCCU NCF 1 for integrity error on data for safety (DATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN (1 << 17) /* Bit 17: Enable fault monitoring at FCCU NCF 1 for TCM AHB splitter safety alarm (TCM_AXBS_ALARM_EN) */
#define DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN (1 << 18) /* Bit 18: Enable fault monitoring at FCCU NCF 1 for EMAC IAHB gasket alarm (EMAC_GSKT_ALARM_EN) */
#define DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN (1 << 19) /* Bit 19: Enable fault monitoring at FCCU NCF 1 for PERIPH AXBS_Lite safety alarm (PERIPH_AXBS_ALARM_EN) */
/* Bits 20-21: Reserved */
#define DCM_GPR_DCMRWD3_LC_ERR_EN (1 << 22) /* Bit 22: Enable fault monitoring at FCCU NCF 3 for error in lifecycle scanning (LC_ERR_EN) */
/* Bits 23: Reserved */
#define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM1 (PRAM1_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM0 (PRAM0_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
/* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */
#define DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN (1 << 0) /* Bit 0: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache tag memory (CM7_0_ICTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_1_ICTAG_ECC_ERR_EN (1 << 1) /* Bit 1: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache tag memory (CM7_1_ICTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN (1 << 2) /* Bit 2: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_0 Instruction TCM memory (CM7_0_ITCM_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN (1 << 3) /* Bit 3: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_0 Data TCM memory block 0 (CM7_0_DTCM0_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN (1 << 4) /* Bit 4: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_0 Data TCM memory block 1 (CM7_0_DTCM1_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN (1 << 5) /* Bit 5: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_1 Instruction TCM memory (CM7_1_ITCM_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN (1 << 6) /* Bit 6: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_1 Data TCM memory block 0 (CM7_1_DTCM0_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN (1 << 7) /* Bit 7: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_1 Data TCM memory block 1 (CM7_1_DTCM1_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN (1 << 8) /* Bit 8: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error reported from DMA_TCD memory (DMA_TCD_RAM_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN (1 << 9) /* Bit 9: Enable fault monitoring at FCCU NCF 2 for PRAM0 safety alarm (PRAM0_FCCU_ALARM_EN) */
#define DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN (1 << 10) /* Bit 10: Enable fault monitoring at FCCU NCF 2 for PRAM1 safety alarm (PRAM1_FCCU_ALARM_EN) */
#define DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN (1 << 11) /* Bit 11: Enable fault monitoring at FCCU NCF 2 for HSE RAM Uncorrectable ECC (HSE_RAM_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN (1 << 12) /* Bit 12: Enable fault monitoring at FCCU NCF 3 for Flash0 code ECC uncorrectable error (PF0_CODE_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN (1 << 13) /* Bit 13: Enable fault monitoring at FCCU NCF 3 for Flash0 data ECC uncorrectable error (PF0_DATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN (1 << 14) /* Bit 14: Enable fault monitoring at FCCU NCF 3 for Flash1 code ECC uncorrectable error (PF1_CODE_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN (1 << 15) /* Bit 15: Enable fault monitoring at FCCU NCF 3 for Flash1 data ECC uncorrectable error (PF1_DATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PF2_CODE_ECC_ERR_EN (1 << 16) /* Bit 16: Enable fault monitoring at FCCU NCF 3 for Flash2 code ECC uncorrectable error (PF2_CODE_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_PF2_DATA_ECC_ERR_EN (1 << 17) /* Bit 17: Enable fault monitoring at FCCU NCF 3 for Flash2 data ECC uncorrectable error (PF2_DATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN (1 << 18) /* Bit 18: Enable fault monitoring at FCCU NCF 3 for Flash ECC correction error through EDC reported by FMU (FLASH_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN (1 << 19) /* Bit 19: Enable fault monitoring at FCCU NCF 3 for flash address encode error (FLASH_ADDR_ENC_ERR_EN) */
#define DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN (1 << 20) /* Bit 20: Enable fault monitoring at FCCU NCF 3 for flash reference current loss or read voltage error while previous read(s) (FLASH_REF_ERR_EN) */
#define DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN (1 << 21) /* Bit 21: Enable fault monitoring at FCCU NCF 3 for flash reset error (FLASH_RST_ERR_EN) */
#define DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN (1 << 22) /* Bit 22: Enable fault monitoring at FCCU NCF 3 for error while DCM flash scanning process due to invalid data (FLASH_SCAN_ERR_EN) */
/* Bit 23: Reserved */
#define DCM_GPR_DCMRWD4_FLASH_ECC_ERR_EN (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 3 for ECC error from Flash Controller (FLASH_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 3 for transaction monitor mismatch (FLASH_ACCESS_ERR_EN) */
#define DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 4 for Go/No-go indicator for VDD1PD1 (double bond) supply going to PLL (VDD1P1_GNG_ERR_EN) */
#define DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 4 for Go/No-go indicator for VDD_HV_FLA (double bond) supply going to FXOSC and PLL (VDD2P5_GNG_ERR_EN) */
/* Bit 28: Reserved */
#define DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 5 for accidental partial test activation (TEST_ACTIVATION_0_ERR_EN) */
#define DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 5 for accidental partial test activation (TEST_ACTIVATION_1_ERR_EN) */
/* Bit 31: Reserved */
/* Read Write GPR On Destructive Reset Register 5 (DCMRWD5) */
/* Bit 0: Reserved */
#define DCM_GPR_DCMRWD5_INTM_0_ERR_EN (1 << 1) /* Bit 1: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 0 error reported by INTM (INTM_0_ERR_EN) */
#define DCM_GPR_DCMRWD5_INTM_1_ERR_EN (1 << 2) /* Bit 2: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 1 error reported by INTM (INTM_1_ERR_EN) */
#define DCM_GPR_DCMRWD5_INTM_2_ERR_EN (1 << 3) /* Bit 3: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 2 error reported by INTM (INTM_2_ERR_EN) */
#define DCM_GPR_DCMRWD5_INTM_3_ERR_EN (1 << 4) /* Bit 4: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 3 error reported by INTM (INTM_3_ERR_EN) */
#define DCM_GPR_DCMRWD5_SW_NCF_0_EN (1 << 5) /* Bit 5: Enable fault monitoring at FCCU NCF 7 for Software NFC0 (SW_NCF_0_EN) */
#define DCM_GPR_DCMRWD5_SW_NCF_1_EN (1 << 6) /* Bit 6: Enable fault monitoring at FCCU NCF 7 for Software NFC1 (SW_NCF_1_EN) */
#define DCM_GPR_DCMRWD5_SW_NCF_2_EN (1 << 7) /* Bit 7: Enable fault monitoring at FCCU NCF 7 for Software NFC2 (SW_NCF_2_EN) */
#define DCM_GPR_DCMRWD5_SW_NCF_3_EN (1 << 8) /* Bit 8: Enable fault monitoring at FCCU NCF 7 for Software NFC3 (SW_NCF_3_EN) */
#define DCM_GPR_DCMRWD5_STCU_NCF_EN (1 << 9) /* Bit 9: Enable fault monitoring at FCCU NCF 5 for STCU non-critical fault / BIST result error (STCU_NCF_EN) */
#define DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN (1 << 10) /* Bit 10: Enable fault monitoring at FCCU NCF 5 for accidental backdoor access on memories (MBIST_ACTIVATION_ERR_EN) */
#define DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN (1 << 11) /* Bit 11: Enable fault monitoring at FCCU NCF 5 for L/M BIST enabled accidentally (STCU_BIST_USER_CF_EN) */
#define DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN (1 << 12) /* Bit 12: Enable fault monitoring at FCCU NFC 5 for fault reported due to illegal access on MTR (MTR_BUS_ERR_EN) */
#define DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN (1 << 13) /* Bit 13: Enable fault monitoring at FCCU NCF 5 for monitoring of unintended debug activation (DEBUG_ACTIVATION_ERR_EN) */
#define DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN (1 << 14) /* Bit 14: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on TCM read data for safety (TCM_RDATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN (1 << 15) /* Bit 15: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on EMAC read data for safety (EMAC_RDATA_EDC_ERR_EN) */
/* Bit 16: Reserved */
#define DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN (1 << 17) /* Bit 17: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on eDMA read data for safety (DMA_RDATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD5_CM7_1_AHBP_RDATA_EDC_ERR_EN (1 << 18) /* Bit 18: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_1 peripheral read data for safety (CM7_1_AHBP_RDATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD5_CM7_1_AHBM_RDATA_EDC_ERR_EN (1 << 19) /* Bit 19: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_1 main read data for safety (CM7_1_AHBM_RDATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN (1 << 20) /* Bit 20: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_0 peripheral read data for safety (CM7_0_AHBP_RDATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN (1 << 21) /* Bit 21: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_0 main read data for safety (CM7_0_AHBM_RDATA_EDC_ERR_EN) */
#define DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN (1 << 22) /* Bit 22: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on HSE read data for safety (HSE_RDATA_EDC_ERR_EN) */
/* Bits 23-31: Reserved */
/* Read Write GPR On Destructive Reset Register 6 (DCMRWD6) */
#define DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0 (1 << 0) /* Bit 0: EDMA debug disable bit for CM7_0 (EDMA_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0 (1 << 1) /* Bit 1: FCCU debug disable bit for CM7_0 (FCCU_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0 (1 << 2) /* Bit 2: LCU0 debug disable bit for CM7_0 (LCU0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0 (1 << 3) /* Bit 3: LCU1 debug disable bit for CM7_0 (LCU1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0 (1 << 4) /* Bit 4: EMIOS0 debug disable bit for CM7_0 (EMIOS0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0 (1 << 5) /* Bit 5: EMIOS1 debug disable bit for CM7_0 (EMIOS1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0 (1 << 6) /* Bit 6: EMIOS2 debug disable bit for CM7_0 (EMIOS2_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0 (1 << 7) /* Bit 7: RTC debug disable bit for CM7_0 (RTC_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0 (1 << 8) /* Bit 8: SWT0 debug disable bit for CM7_0 (SWT0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0 (1 << 9) /* Bit 9: SWT1 debug disable bit for CM7_0 (SWT1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0 (1 << 10) /* Bit 10: STM0 debug disable bit for CM7_0 (STM0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0 (1 << 11) /* Bit 11: STM1 debug disable bit for CM7_0 (STM1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0 (1 << 12) /* Bit 12: PIT0 debug disable bit for CM7_0 (PIT0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0 (1 << 13) /* Bit 13: PIT1 debug disable bit for CM7_0 (PIT1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0 (1 << 14) /* Bit 14: PIT2 debug disable bit for CM7_0 (PIT2_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0 (1 << 15) /* Bit 15: LPSPI0 debug disable bit for CM7_0 (LPSPI0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0 (1 << 16) /* Bit 16: LPSPI1 debug disable bit for CM7_0 (LPSPI1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0 (1 << 17) /* Bit 17: LPSPI2 debug disable bit for CM7_0 (LPSPI2_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0 (1 << 18) /* Bit 18: LPSPI3 debug disable bit for CM7_0 (LPSPI3_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0 (1 << 19) /* Bit 19: LPSPI4 debug disable bit for CM7_0 (LPSPI4_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0 (1 << 20) /* Bit 20: LPSPI5 debug disable bit for CM7_0 (LPSPI5_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0 (1 << 21) /* Bit 21: LPI2C0 debug disable bit for CM7_0 (LPI2C0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0 (1 << 22) /* Bit 22: LPI2C1 debug disable bit for CM7_0 (LPI2C1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0 (1 << 23) /* Bit 23: FLEXIO debug disable bit for CM7_0 (FLEXIO_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0 (1 << 24) /* Bit 24: FLEXCAN0 debug disable bit for CM7_0 (FLEXCAN0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0 (1 << 25) /* Bit 25: FLEXCAN1 debug disable bit for CM7_0 (FLEXCAN1_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0 (1 << 26) /* Bit 26: FLEXCAN2 debug disable bit for CM7_0 (FLEXCAN2_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0 (1 << 27) /* Bit 27: FLEXCAN3 debug disable bit for CM7_0 (FLEXCAN3_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0 (1 << 28) /* Bit 28: FLEXCAN4 debug disable bit for CM7_0 (FLEXCAN4_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0 (1 << 29) /* Bit 29: FLEXCAN5 debug disable bit for CM7_0 (FLEXCAN5_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0 (1 << 30) /* Bit 30: SAI0 debug disable bit for CM7_0 (SAI0_DBG_DIS_CM7_0) */
#define DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0 (1 << 31) /* Bit 31: SAI1 debug disable bit for CM7_0 (SAI1_DBG_DIS_CM7_0) */
/* Read Write GPR On Destructive Reset Register 7 (DCMRWD7) */
#define DCM_GPR_DCMRWD7_I3C_DBG_DIS_CM7_0 (1 << 0) /* Bit 0: I3C debug disable bit for CM7_0 (I3C_DBG_DIS_CM7_0) */
/* Bits 1-31: Reserved */
/* Read Write GPR On Destructive Reset Register 8 (DCMRWD8) */
#define DCM_GPR_DCMRWD8_EDMA_DBG_DIS_CM7_1 (1 << 0) /* Bit 0: EDMA debug disable bit for CM7_1 (EDMA_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FCCU_DBG_DIS_CM7_1 (1 << 1) /* Bit 1: FCCU debug disable bit for CM7_1 (FCCU_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LCU0_DBG_DIS_CM7_1 (1 << 2) /* Bit 2: LCU0 debug disable bit for CM7_1 (LCU0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LCU1_DBG_DIS_CM7_1 (1 << 3) /* Bit 3: LCU1 debug disable bit for CM7_1 (LCU1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_EMIOS0_DBG_DIS_CM7_1 (1 << 4) /* Bit 4: EMIOS0 debug disable bit for CM7_1 (EMIOS0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_EMIOS1_DBG_DIS_CM7_1 (1 << 5) /* Bit 5: EMIOS1 debug disable bit for CM7_1 (EMIOS1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_EMIOS2_DBG_DIS_CM7_1 (1 << 6) /* Bit 6: EMIOS2 debug disable bit for CM7_1 (EMIOS2_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_RTC_DBG_DIS_CM7_1 (1 << 7) /* Bit 7: RTC debug disable bit for CM7_1 (RTC_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_SWT0_DBG_DIS_CM7_1 (1 << 8) /* Bit 8: SWT0 debug disable bit for CM7_1 (SWT0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_SWT1_DBG_DIS_CM7_1 (1 << 9) /* Bit 9: SWT1 debug disable bit for CM7_1 (SWT1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_STM0_DBG_DIS_CM7_1 (1 << 10) /* Bit 10: STM0 debug disable bit for CM7_1 (STM0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_STM1_DBG_DIS_CM7_1 (1 << 11) /* Bit 11: STM1 debug disable bit for CM7_1 (STM1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_PIT0_DBG_DIS_CM7_1 (1 << 12) /* Bit 12: PIT0 debug disable bit for CM7_1 (PIT0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_PIT1_DBG_DIS_CM7_1 (1 << 13) /* Bit 13: PIT1 debug disable bit for CM7_1 (PIT1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_PIT2_DBG_DIS_CM7_1 (1 << 14) /* Bit 14: PIT2 debug disable bit for CM7_1 (PIT2_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPSPI0_DBG_DIS_CM7_1 (1 << 15) /* Bit 15: LPSPI0 debug disable bit for CM7_1 (LPSPI0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPSPI1_DBG_DIS_CM7_1 (1 << 16) /* Bit 16: LPSPI1 debug disable bit for CM7_1 (LPSPI1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPSPI2_DBG_DIS_CM7_1 (1 << 17) /* Bit 17: LPSPI2 debug disable bit for CM7_1 (LPSPI2_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPSPI3_DBG_DIS_CM7_1 (1 << 18) /* Bit 18: LPSPI3 debug disable bit for CM7_1 (LPSPI3_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPSPI4_DBG_DIS_CM7_1 (1 << 19) /* Bit 19: LPSPI4 debug disable bit for CM7_1 (LPSPI4_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPSPI5_DBG_DIS_CM7_1 (1 << 20) /* Bit 20: LPSPI5 debug disable bit for CM7_1 (LPSPI5_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPI2C0_DBG_DIS_CM7_1 (1 << 21) /* Bit 21: LPI2C0 debug disable bit for CM7_1 (LPI2C0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_LPI2C1_DBG_DIS_CM7_1 (1 << 22) /* Bit 22: LPI2C1 debug disable bit for CM7_1 (LPI2C1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXIO_DBG_DIS_CM7_1 (1 << 23) /* Bit 23: FLEXIO debug disable bit for CM7_1 (FLEXIO_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXCAN0_DBG_DIS_CM7_1 (1 << 24) /* Bit 24: FLEXCAN0 debug disable bit for CM7_1 (FLEXCAN0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXCAN1_DBG_DIS_CM7_1 (1 << 25) /* Bit 25: FLEXCAN1 debug disable bit for CM7_1 (FLEXCAN1_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXCAN2_DBG_DIS_CM7_1 (1 << 26) /* Bit 26: FLEXCAN2 debug disable bit for CM7_1 (FLEXCAN2_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXCAN3_DBG_DIS_CM7_1 (1 << 27) /* Bit 27: FLEXCAN3 debug disable bit for CM7_1 (FLEXCAN3_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXCAN4_DBG_DIS_CM7_1 (1 << 28) /* Bit 28: FLEXCAN4 debug disable bit for CM7_1 (FLEXCAN4_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_FLEXCAN5_DBG_DIS_CM7_1 (1 << 29) /* Bit 29: FLEXCAN5 debug disable bit for CM7_1 (FLEXCAN5_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_SAI0_DBG_DIS_CM7_1 (1 << 30) /* Bit 30: SAI0 debug disable bit for CM7_1 (SAI0_DBG_DIS_CM7_1) */
#define DCM_GPR_DCMRWD8_SAI1_DBG_DIS_CM7_1 (1 << 31) /* Bit 31: SAI1 debug disable bit for CM7_1 (SAI1_DBG_DIS_CM7_1) */
/* Read Write GPR On Destructive Reset Register 9 (DCMRWD9) */
#define DCM_GPR_DCMRWD9_I3C_DBG_DIS_CM7_1 (1 << 0) /* Bit 0: I3C debug disable bit for CM7_1 (I3C_DBG_DIS_CM7_1) */
/* Bits 1-31: Reserved */
/* Read Write GPR On Functional Reset Register 1 (DCMRWF1) */
#define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL (1 << 0) /* Bit 0: Select between EMAC and STM for CAN timestamping (CAN_TIMESTAMP_SEL) */
# define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_EMAC (1 << 0) /* EMAC selected for CAN timestamping */
# define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_STM0 (1 << 1) /* STM0 selected for CAN timestamping */
#define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN (1 << 1) /* Bit 1: Enables CAN timestamping feature for all FlexCANs (CAN_TIMESTAMP_EN) */
#define DCM_GPR_DCMRWF1_FCCU_SW_NCF0 (1 << 2) /* Bit 2: Control to initiate Software NFC to FCCU (FCCU_SW_NFC0) */
#define DCM_GPR_DCMRWF1_FCCU_SW_NCF1 (1 << 3) /* Bit 3: Control to initiate Software NFC to FCCU (FCCU_SW_NFC1) */
#define DCM_GPR_DCMRWF1_FCCU_SW_NCF2 (1 << 4) /* Bit 4: Control to initiate Software NFC to FCCU (FCCU_SW_NFC2) */
#define DCM_GPR_DCMRWF1_FCCU_SW_NCF3 (1 << 5) /* Bit 5: Control to initiate Software NFC to FCCU (FCCU_SW_NFC3) */
/* Bit 6: Reserved */
#define DCM_GPR_DCMRWF1_RMII_MII_SEL (1 << 7) /* Bit 7: Selects between MII and RMII mode of ethernet (RMII_MII_SEL) */
# define DCM_GPR_DCMRWF1_RMII_MII_SEL_MII (0 << 7) /* MII mode */
# define DCM_GPR_DCMRWF1_RMII_MII_SEL_RMII (1 << 7) /* RMII mode */
/* Bits 8-14: Reserved */
#define DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH (1 << 15) /* Bit 15: Controls the IO controls latching in low frequency RUN mode to reduce power consumption on VDD_HV_B domain pins (VDD_HV_B_IO_CTRL_LATCH) */
#define DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG (1 << 16) /* Bit 16: Controls the IO state in standby mode (STANDBY_IO_CONFIG) */
/* Bits 17-19: Reserved */
#define DCM_GPR_DCMRWF1_SUPPLY_MON_EN (1 << 20) /* Bit 20: Enable the supply voltage monitoring by ADC (SUPPLY_MON_SEL) */
#define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT (21) /* Bits 21-23: Selects the source of voltage used by ADC for supply monitoring (SUPPLY_MON_SEL) */
#define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_MASK (0x07 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT)
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_HV_A (0x00 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_HV_A_DIV */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_HV_B (0x01 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_HV_B_DIV */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_1_5 (0x02 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_1.5_DIV */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_2_5 (0x03 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_2.5_OSC */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_HOT (0x04 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PD1_HOT_POINT */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_COLD (0x05 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PD1_COLD_POINT */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_PLL (0x06 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PLL */
# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_PD0 (0x07 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PD0 */
#define DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN (1 << 24) /* Bit 24: Enable VSS_LV monitoring (VSS_LV_ANMUX_EN) */
#define DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN (1 << 25) /* Bit 25: Enable 2:1 divider for VDD_HV_A for supply voltage monitoring by ADC (VDD_HV_A_VLT_DVDR_EN) */
#define DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN (1 << 26) /* Bit 26: Enable 2:1 divider for VDD_HV_B for supply voltage monitoring by ADC (VDD_HV_B_VLT_DVDR_EN) */
#define DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN (1 << 27) /* Bit 27: Enable 2:1 divider for VDD1P5 for supply voltage monitoring by ADC (VDD_1_5_VLT_DVDR_EN) */
/* Bits 28-31: Reserved */
/* Read Write GPR On Functional Reset Register 2 (DCMRWF2) */
/* Bits 0-2: Reserved */
#define DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT (1 << 3) /* Bit 3: Bypass the DCM scanning on standby exit (DCM_SCAN_BYP_STDBY_EXT) */
#define DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT (1 << 4) /* Bit 4: Bypass the FIRC trimming on standby exit (FIRC_TRIM_BYP_STDBY_EXT) */
#define DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT (1 << 5) /* Bit 5: Bypass the PMC trimming and RGM DCF loading on standby exit (PMC_TRIM_RGM_DCF_BYP_STDBY_EXT) */
#define DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT (1 << 6) /* Bit 6: Bypass the SIRC trimming on standby exit (SIRC_TRIM_BYP_STDBY_EXT) */
/* Bits 7-15: Reserved */
#define DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS (1 << 16) /* Enable the HSE IAHB gasket bypass out of standby mode (HSE_GSKT_BYPASS) */
/* Bits 17-31: Reserved */
/* Read Write GPR On Functional Reset Register 4 (DCMRWF4) */
/* Bit 0: Reserved */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8 (1 << 1) /* Bit 1: Selects GPIO45 to drive ADC0_S8 (MUX_MODE_EN_ADC0_S8) */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9 (1 << 2) /* Bit 2: Selects GPIO46 to drive ADC0_S9 (MUX_MODE_EN_ADC0_S9) */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14 (1 << 3) /* Bit 3: Selects GPIO32 to drive ADC1_S14 (MUX_MODE_EN_ADC1_S14) */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15 (1 << 4) /* Bit 4: Selects GPIO33 to drive ADC1_S15 (MUX_MODE_EN_ADC1_S15) */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22 (1 << 5) /* Bit 5: Selects GPIO114 to drive ADC1_S22 (MUX_MODE_EN_ADC1_S22) */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23 (1 << 6) /* Bit 6: Selects GPIO115 to drive ADC1_S23 (MUX_MODE_EN_ADC1_S23) */
/* Bits 7-8: Reserved */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8 (1 << 9) /* Bit 9: Selects GPIO45 to drive ADC2_S8 (MUX_MODE_EN_ADC2_S8) */
#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9 (1 << 10) /* Bit 10: Selects GPIO46 to drive ADC2_S9 (MUX_MODE_EN_ADC2_S9) */
/* Bits 11-12: Reserved */
#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP (1 << 13) /* Bit 13: Bypass glitch filter on TRGMUX input63 (GLITCH_FIL_TRG_IN0_BYP) */
#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP (1 << 14) /* Bit 14: Bypass glitch filter on TRGMUX input62 (GLITCH_FIL_TRG_IN1_BYP) */
#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP (1 << 15) /* Bit 15: Bypass glitch filter on TRGMUX input61 (GLITCH_FIL_TRG_IN2_BYP) */
#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP (1 << 16) /* Bit 16: Bypass glitch filter on TRGMUX input60 (GLITCH_FIL_TRG_IN3_BYP) */
#define DCM_GPR_DCMRWF4_CM7_0_CPUWAIT (1 << 17) /* Bit 17: Put CM7_0 core into wait mode (CM7_0_CPUWAIT) */
#define DCM_GPR_DCMRWF4_CM7_1_CPUWAIT (1 << 18) /* Bit 18: Put CM7_1 core into wait mode (CM7_1_CPUWAIT) */
/* Bits 19-31: Reserved */
/* Read Write GPR On Functional Reset Register 5 (DCMRWF5) */
#define DCM_GPR_DCMRWF5_BOOT_MODE (1 << 0) /* Bit 0: Selects the boot mode after exiting standby mode (BOOT_MODE) */
# define DCM_GPR_DCMRWF5_BOOT_MODE_NORMAL (0 << 0) /* Normal */
# define DCM_GPR_DCMRWF5_BOOT_MODE_FAST (1 << 0) /* Fast Standby */
#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT (1) /* Bits 1-31: Cortex-M7_0 base address of vector table to be used after exiting (fast) standby mode (BOOT_ADDRESS) */
#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT)
/* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT0 (1 << 0) /* Bit 0: Status of functional reset sequence process FUNC0 when POR_WDG overflows (POR_WDG_STAT0) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT1 (1 << 1) /* Bit 1: Status of functional reset sequence process FUNC1 when POR_WDG overflows (POR_WDG_STAT1) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT2 (1 << 2) /* Bit 2: Status of functional reset sequence process FUNC2 when POR_WDG overflows (POR_WDG_STAT2) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT3 (1 << 3) /* Bit 3: Status of functional reset sequence process FUNC3 when POR_WDG overflows (POR_WDG_STAT3) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT4 (1 << 4) /* Bit 4: Status of functional reset sequence process FUNC4 when POR_WDG overflows (POR_WDG_STAT4) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT5 (1 << 5) /* Bit 5: Status of functional reset sequence process FUNC5 when POR_WDG overflows (POR_WDG_STAT5) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT6 (1 << 6) /* Bit 6: Status of functional reset sequence process FUNC6 when POR_WDG overflows (POR_WDG_STAT6) */
/* Bits 7-9: Reserved */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT10 (1 << 10) /* Bit 10: Status of functional reset sequence process FUNC7 when POR_WDG overflows (POR_WDG_STAT10) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT11 (1 << 11) /* Bit 11: Status of functional reset sequence process FUNC8 when POR_WDG overflows (POR_WDG_STAT11) */
/* Bits 12-13: Reserved */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT14 (1 << 14) /* Bit 14: Status of functional reset sequence process FUNC9 when POR_WDG overflows (POR_WDG_STAT14) */
/* Bits 15-16: Reserved */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT17 (1 << 17) /* Bit 17: Status of functional reset sequence process FUNC10 when POR_WDG overflows (POR_WDG_STAT17) */
/* Bits 18-19: Reserved */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT20 (1 << 20) /* Bit 20: Status of functional reset sequence process DEST0 when POR_WDG overflows (POR_WDG_STAT20) */
/* Bits 21-28: Reserved */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT29 (1 << 29) /* Bit 29: Status of standby entry request initiated by MC_ME when POR_WDG overflows (POR_WDG_STAT29) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT30 (1 << 30) /* Bit 30: Status of standby exit acknowledgement by MC_PCU when POR_WDG overflows (POR_WDG_STAT30) */
#define DCM_GPR_DCMROPP1_POR_WDG_STAT31 (1 << 31) /* Bit 31: MC_RGM reset event (if occurred) while the device is in STANDBY mode (POR_WDG_STAT31) */
/* Read Only GPR On PMCPOR Reset Register 2 (DCMROPP2) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT32 (1 << 0) /* Bit 0: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT32) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT33 (1 << 1) /* Bit 1: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT33) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT34 (1 << 2) /* Bit 2: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT34) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT35 (1 << 3) /* Bit 3: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT35) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT36 (1 << 4) /* Bit 4: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT36) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT37 (1 << 5) /* Bit 5: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT37) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT38 (1 << 6) /* Bit 6: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT38) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT39 (1 << 7) /* Bit 7: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT39) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT40 (1 << 8) /* Bit 8: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT40) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT41 (1 << 9) /* Bit 9: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT41) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT42 (1 << 10) /* Bit 10: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT42) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT43 (1 << 11) /* Bit 11: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT43) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT44 (1 << 12) /* Bit 12: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT44) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT45 (1 << 13) /* Bit 13: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT45) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT46 (1 << 14) /* Bit 14: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT46) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT47 (1 << 15) /* Bit 15: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT47) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT48 (1 << 16) /* Bit 16: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT48) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT49 (1 << 17) /* Bit 17: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT49) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT50 (1 << 18) /* Bit 18: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT50) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT51 (1 << 19) /* Bit 19: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT51) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT52 (1 << 20) /* Bit 20: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT52) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT53 (1 << 21) /* Bit 21: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT53) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT54 (1 << 22) /* Bit 22: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT54) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT55 (1 << 23) /* Bit 23: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT55) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT56 (1 << 24) /* Bit 24: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT56) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT57 (1 << 25) /* Bit 25: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT57) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT58 (1 << 26) /* Bit 26: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT58) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT59 (1 << 27) /* Bit 27: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT59) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT60 (1 << 28) /* Bit 28: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT60) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT61 (1 << 29) /* Bit 29: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT61) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT62 (1 << 30) /* Bit 30: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT62) */
#define DCM_GPR_DCMROPP2_POR_WDG_STAT63 (1 << 31) /* Bit 31: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT63) */
/* Read Only GPR On PMCPOR Reset Register 3 (DCMROPP3) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT64 (1 << 0) /* Bit 0: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT64) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT65 (1 << 1) /* Bit 1: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT65) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT66 (1 << 2) /* Bit 2: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT66) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT67 (1 << 3) /* Bit 3: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT67) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT68 (1 << 4) /* Bit 4: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT68) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT69 (1 << 5) /* Bit 5: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT69) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT70 (1 << 6) /* Bit 6: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT70) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT71 (1 << 7) /* Bit 7: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT71) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT72 (1 << 8) /* Bit 8: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT72) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT73 (1 << 9) /* Bit 9: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT73) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT74 (1 << 10) /* Bit 10: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT74) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT75 (1 << 11) /* Bit 11: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT75) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT76 (1 << 12) /* Bit 12: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT76) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT77 (1 << 13) /* Bit 13: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT77) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT78 (1 << 14) /* Bit 14: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT78) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT79 (1 << 15) /* Bit 15: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT79) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT80 (1 << 16) /* Bit 16: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT80) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT81 (1 << 17) /* Bit 17: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT81) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT82 (1 << 18) /* Bit 18: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT82) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT83 (1 << 19) /* Bit 19: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT83) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT84 (1 << 20) /* Bit 20: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT84) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT85 (1 << 21) /* Bit 21: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT85) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT86 (1 << 22) /* Bit 22: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT86) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT87 (1 << 23) /* Bit 23: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT87) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT88 (1 << 24) /* Bit 24: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT88) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT89 (1 << 25) /* Bit 25: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT89) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT90 (1 << 26) /* Bit 26: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT90) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT91 (1 << 27) /* Bit 27: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT91) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT92 (1 << 28) /* Bit 28: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT92) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT93 (1 << 29) /* Bit 29: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT93) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT94 (1 << 30) /* Bit 30: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT94) */
#define DCM_GPR_DCMROPP3_POR_WDG_STAT95 (1 << 31) /* Bit 31: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT95) */
/* Read Only GPR On PMCPOR Reset Register 4 (DCMROPP4) */
#define DCM_GPR_DCMROPP4_POR_WDG_STAT96 (1 << 0) /* Bit 0: POR_WDG reset event if POR_WDG initiates a POR sequence (POR_WDG_STAT96) */
/* Bits 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DCM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DMAMUX Register Offsets **************************************************/
#define S32K3XX_DMAMUX_CHCFG3_OFFSET (0x00) /* Channel Configuration Register 3 (CHCFG3) */
#define S32K3XX_DMAMUX_CHCFG2_OFFSET (0x01) /* Channel Configuration Register 2 (CHCFG2) */
#define S32K3XX_DMAMUX_CHCFG1_OFFSET (0x02) /* Channel Configuration Register 1 (CHCFG1) */
#define S32K3XX_DMAMUX_CHCFG0_OFFSET (0x03) /* Channel Configuration Register 0 (CHCFG0) */
#define S32K3XX_DMAMUX_CHCFG7_OFFSET (0x04) /* Channel Configuration Register 7 (CHCFG7) */
#define S32K3XX_DMAMUX_CHCFG6_OFFSET (0x05) /* Channel Configuration Register 6 (CHCFG6) */
#define S32K3XX_DMAMUX_CHCFG5_OFFSET (0x06) /* Channel Configuration Register 5 (CHCFG5) */
#define S32K3XX_DMAMUX_CHCFG4_OFFSET (0x07) /* Channel Configuration Register 4 (CHCFG4) */
#define S32K3XX_DMAMUX_CHCFG11_OFFSET (0x08) /* Channel Configuration Register 11 (CHCFG11) */
#define S32K3XX_DMAMUX_CHCFG10_OFFSET (0x09) /* Channel Configuration Register 10 (CHCFG10) */
#define S32K3XX_DMAMUX_CHCFG9_OFFSET (0x0a) /* Channel Configuration Register 9 (CHCFG9) */
#define S32K3XX_DMAMUX_CHCFG8_OFFSET (0x0b) /* Channel Configuration Register 8 (CHCFG8) */
#define S32K3XX_DMAMUX_CHCFG15_OFFSET (0x0c) /* Channel Configuration Register 15 (CHCFG15) */
#define S32K3XX_DMAMUX_CHCFG14_OFFSET (0x0d) /* Channel Configuration Register 14 (CHCFG14) */
#define S32K3XX_DMAMUX_CHCFG13_OFFSET (0x0e) /* Channel Configuration Register 13 (CHCFG13) */
#define S32K3XX_DMAMUX_CHCFG12_OFFSET (0x0f) /* Channel Configuration Register 12 (CHCFG12) */
#define S32K3XX_DMAMUX_CHCFG_OFFSET(n) ((n) + 3 - 2 * ((n) % 4))
#define S32K3XX_DMAMUX0_CHCFG(n) (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG_OFFSET(n))
#define S32K3XX_DMAMUX1_CHCFG(n) (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG_OFFSET(n))
/* DMAMUX Register Addresses ************************************************/
#define S32K3XX_DMAMUX0_CHCFG3 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG3_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG2 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG2_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG1 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG1_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG0 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG0_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG7 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG7_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG6 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG6_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG5 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG5_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG4 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG4_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG11 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG11_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG10 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG10_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG9 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG9_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG8 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG8_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG15 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG15_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG14 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG14_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG13 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG13_OFFSET)
#define S32K3XX_DMAMUX0_CHCFG12 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG12_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG3 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG3_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG2 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG2_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG1 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG1_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG0 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG0_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG7 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG7_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG6 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG6_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG5 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG5_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG4 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG4_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG11 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG11_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG10 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG10_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG9 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG9_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG8 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG8_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG15 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG15_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG14 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG14_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG13 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG13_OFFSET)
#define S32K3XX_DMAMUX1_CHCFG12 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG12_OFFSET)
/* DMAMUX Register Bitfield Definitions *************************************/
#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (SOURCE) */
#define DMAMUX_CHCFG_SOURCE_MASK (0x3f << DMAMUX_CHCFG_SOURCE_SHIFT)
#define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable (TRIG) */
#define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable (ENBL) */
#define DMAMUX_CHCFG_MASK (0xff) /* Bits 0-7 */
#define DMAMUX_CHCFG_DMAMUX1 (1 << 15) /* Bit 15: DMAMUX1 Selection */
/* DMA Request sources */
/** edma_mux0 **/
#define DMA_REQ_DISABLED0 0 ///< Channel disabled (default)
#define DMA_REQ_SIUL_0 1 ///< SIUL DMA request 0
#define DMA_REQ_SIUL_1 2 ///< SIUL DMA request 1
#define DMA_REQ_SIUL_2 3 ///< SIUL DMA request 2
#define DMA_REQ_SIUL_3 4 ///< SIUL DMA request 3
#define DMA_REQ_SIUL_4 5 ///< SIUL DMA request 4
#define DMA_REQ_SIUL_5 6 ///< SIUL DMA request 5
#define DMA_REQ_SIUL_6 7 ///< SIUL DMA request 6
#define DMA_REQ_SIUL_7 8 ///< SIUL DMA request 7
#define DMA_REQ_BCTU_FIFO1 10 ///< BCTU DMA FIFO1 request
#define DMA_REQ_BCTU_0 10 ///< BCTU DMA request 0
#define DMA_REQ_BCTU_1 11 ///< BCTU DMA request 1
#define DMA_REQ_EMIOS0_0 12 ///< eMIOS0 DMA request ch0
#define DMA_REQ_EMIOS0_1 13 ///< eMIOS0 DMA request ch1
#define DMA_REQ_EMIOS0_9 14 ///< eMIOS0 DMA request ch9
#define DMA_REQ_EMIOS0_10 15 ///< eMIOS0 DMA request ch10
#define DMA_REQ_EMIOS1_0 16 ///< eMIOS1 DMA request ch0
#define DMA_REQ_EMIOS1_1 17 ///< eMIOS1 DMA request ch1
#define DMA_REQ_EMIOS1_9 18 ///< eMIOS1 DMA request ch9
#define DMA_REQ_EMIOS1_10 19 ///< eMIOS1 DMA request ch10
#define DMA_REQ_EMIOS2_0 20 ///< eMIOS2 DMA request ch0
#define DMA_REQ_EMIOS2_1 21 ///< eMIOS2 DMA request ch1
#define DMA_REQ_EMIOS2_9 22 ///< eMIOS2 DMA request ch9
#define DMA_REQ_EMIOS2_10 23 ///< eMIOS2 DMA request ch10
#define DMA_REQ_LCU0_0 24 ///< LCU0 DMA request 0
#define DMA_REQ_LCU1_0 25 ///< LCU1 DMA request 0
#define DMA_REQ_RESERVED1 26 ///< RESERVED
#define DMA_REQ_RESERVED2 27 ///< RESERVED
#define DMA_REQ_RESERVED3 28 ///< RESERVED
#define DMA_REQ_FLEXCAN0 29 ///< FLEXCAN0 DMA request
#define DMA_REQ_FLEXCAN1 30 ///< FLEXCAN1 DMA request
#define DMA_REQ_FLEXCAN2 31 ///< FLEXCAN2 DMA request
#define DMA_REQ_FLEXCAN3 32 ///< FLEXCAN3 DMA request
#define DMA_REQ_FLEXIO_0 33 ///< FLEXIO DMA shifter0 | timer0 request
#define DMA_REQ_FLEXIO_1 34 ///< FLEXIO DMA shifter1 | timer1 request
#define DMA_REQ_FLEXIO_2 35 ///< FLEXIO DMA shifter2 | timer2 request
#define DMA_REQ_FLEXIO_3 36 ///< FLEXIO DMA shifter3 | timer3 request
#define DMA_REQ_LPUART08_TX 37 ///< LPUART0 | LPUART8 DMA transmit request
#define DMA_REQ_LPUART08_RX 38 ///< LPUART0 | LPUART8 DMA receive request
#define DMA_REQ_LPUART19_TX 39 ///< LPUART1 | LPUART9 DMA transmit request
#define DMA_REQ_LPUART19_RX 40 ///< LPUART1 | LPUART9 DMA receive request
#define DMA_REQ_LPI2C0_RX 41 ///< LPI2C0 DMA receive | receive slave request
#define DMA_REQ_LPI2C0_TX 42 ///< LPI2C0 DMA transmit | transmit slave request
#define DMA_REQ_LPSPI0_TX 43 ///< LPSPI0 DMA transmit request
#define DMA_REQ_LPSPI0_RX 44 ///< LPSPI0 DMA receive request
#define DMA_REQ_LPSPI1_TX 45 ///< LPSPI1 DMA transmit request
#define DMA_REQ_LPSPI1_RX 46 ///< LPSPI1 DMA receive request
#define DMA_REQ_LPSPI2_TX 47 ///< LPSPI2 DMA transmit request
#define DMA_REQ_LPSPI2_RX 48 ///< LPSPI2 DMA receive request
#define DMA_REQ_LPSPI3_TX 49 ///< LPSPI3 DMA transmit request
#define DMA_REQ_LPSPI3_RX 50 ///< LPSPI3 DMA receive request
#define DMA_REQ_I3C0_RX 51 ///< I3C0 DMA receive request
#define DMA_REQ_I3C0_TX 52 ///< I3C0 DMA transmit request
#define DMA_REQ_QSPI_RX 53 ///< QSPI DMA receive buffer drain request
#define DMA_REQ_QSPI_TX 54 ///< QSPI DMA transmit buffer fill request
#define DMA_REQ_SAI0_RX 55 ///< SAI0 DMA receive request
#define DMA_REQ_SAI0_TX 56 ///< SAI0 DMA transmit request
#define DMA_REQ_RESERVED4 57 ///< RESERVED
#define DMA_REQ_ADC0 58 ///< ADC0 DMA request
#define DMA_REQ_ADC1 59 ///< ADC1 DMA request
#define DMA_REQ_ADC2 60 ///< ADC2 DMA request
#define DMA_REQ_LPCMP0 61 ///< LPCMP0 DMA request
#define DMA_REQ_ENABLED0 62 ///< Always enabled
#define DMA_REQ_ENABLED1 63 ///< Always enabled */
/** edma_mux1 **/
#define DMA_REQ_DISABLED1 DMAMUX_CHCFG_DMAMUX1 | 0 ///< Channel disabled (default)
#define DMA_REQ_SIUL_8 DMAMUX_CHCFG_DMAMUX1 | 1 ///< SIUL DMA request 8
#define DMA_REQ_SIUL_9 DMAMUX_CHCFG_DMAMUX1 | 2 ///< SIUL DMA request 9
#define DMA_REQ_SIUL_10 DMAMUX_CHCFG_DMAMUX1 | 3 ///< SIUL DMA request 10
#define DMA_REQ_SIUL_11 DMAMUX_CHCFG_DMAMUX1 | 4 ///< SIUL DMA request 11
#define DMA_REQ_SIUL_12 DMAMUX_CHCFG_DMAMUX1 | 5 ///< SIUL DMA request 12
#define DMA_REQ_SIUL_13 DMAMUX_CHCFG_DMAMUX1 | 6 ///< SIUL DMA request 13
#define DMA_REQ_SIUL_14 DMAMUX_CHCFG_DMAMUX1 | 7 ///< SIUL DMA request 14
#define DMA_REQ_SIUL_15 DMAMUX_CHCFG_DMAMUX1 | 8 ///< SIUL DMA request 15
#define DMA_REQ_BCTU_FIFO2 DMAMUX_CHCFG_DMAMUX1 | 9 ///< BCTU DMA FIFO2 request
#define DMA_REQ_BCTU_2 DMAMUX_CHCFG_DMAMUX1 | 10 ///< BCTU DMA request 2
#define DMA_REQ_EMIOS0_16 DMAMUX_CHCFG_DMAMUX1 | 11 ///< eMIOS0 DMA request ch16
#define DMA_REQ_EMIOS0_17 DMAMUX_CHCFG_DMAMUX1 | 12 ///< eMIOS0 DMA request ch17
#define DMA_REQ_EMIOS0_18 DMAMUX_CHCFG_DMAMUX1 | 13 ///< eMIOS0 DMA request ch18
#define DMA_REQ_EMIOS0_19 DMAMUX_CHCFG_DMAMUX1 | 14 ///< eMIOS0 DMA request ch19
#define DMA_REQ_EMIOS1_16 DMAMUX_CHCFG_DMAMUX1 | 15 ///< eMIOS1 DMA request ch16
#define DMA_REQ_EMIOS1_17 DMAMUX_CHCFG_DMAMUX1 | 16 ///< eMIOS1 DMA request ch17
#define DMA_REQ_EMIOS1_18 DMAMUX_CHCFG_DMAMUX1 | 17 ///< eMIOS1 DMA request ch18
#define DMA_REQ_EMIOS1_19 DMAMUX_CHCFG_DMAMUX1 | 18 ///< eMIOS1 DMA request ch19
#define DMA_REQ_EMIOS2_16 DMAMUX_CHCFG_DMAMUX1 | 19 ///< eMIOS2 DMA request ch16
#define DMA_REQ_EMIOS2_17 DMAMUX_CHCFG_DMAMUX1 | 20 ///< eMIOS2 DMA request ch17
#define DMA_REQ_EMIOS2_18 DMAMUX_CHCFG_DMAMUX1 | 21 ///< eMIOS2 DMA request ch18
#define DMA_REQ_EMIOS2_19 DMAMUX_CHCFG_DMAMUX1 | 22 ///< eMIOS2 DMA request ch19
#define DMA_REQ_LCU0_1 DMAMUX_CHCFG_DMAMUX1 | 23 ///< LCU0 DMA request 1
#define DMA_REQ_LCU0_2 DMAMUX_CHCFG_DMAMUX1 | 24 ///< LCU1 DMA request 2
#define DMA_REQ_LCU1_1 DMAMUX_CHCFG_DMAMUX1 | 25 ///< LCU1 DMA request 1
#define DMA_REQ_LCU1_2 DMAMUX_CHCFG_DMAMUX1 | 26 ///< LCU1 DMA request 2
#define DMA_REQ_ENET_0 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[0] DMA request
#define DMA_REQ_ENET_1 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[1] DMA request
#define DMA_REQ_ENET_2 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[2] DMA request
#define DMA_REQ_ENET_3 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[3] DMA request
#define DMA_REQ_RESERVED5 DMAMUX_CHCFG_DMAMUX1 | 28 ///< RESERVED
#define DMA_REQ_RESERVED6 DMAMUX_CHCFG_DMAMUX1 | 29 ///< RESERVED
#define DMA_REQ_FLECAN4 DMAMUX_CHCFG_DMAMUX1 | 30 ///< FLEXCAN4 DMA request
#define DMA_REQ_FLECAN5 DMAMUX_CHCFG_DMAMUX1 | 31 ///< FLEXCAN5 DMA request
#define DMA_REQ_RESERVED7 DMAMUX_CHCFG_DMAMUX1 | 32 ///< RESERVED
#define DMA_REQ_RESERVED8 DMAMUX_CHCFG_DMAMUX1 | 33 ///< RESERVED
#define DMA_REQ_FLEXIO_4 DMAMUX_CHCFG_DMAMUX1 | 34 ///< FLEXIO DMA shifter4 | timer4 request
#define DMA_REQ_FLEXIO_5 DMAMUX_CHCFG_DMAMUX1 | 35 ///< FLEXIO DMA shifter5 | timer5 request
#define DMA_REQ_FLEXIO_6 DMAMUX_CHCFG_DMAMUX1 | 36 ///< FLEXIO DMA shifter6 | timer6 request
#define DMA_REQ_FLEXIO_7 DMAMUX_CHCFG_DMAMUX1 | 37 ///< FLEXIO DMA shifter7 | timer7 request
#define DMA_REQ_LPUART210_TX DMAMUX_CHCFG_DMAMUX1 | 38 ///< LPUART2 | LPUART10 DMA transmit request
#define DMA_REQ_LPUART210_RX DMAMUX_CHCFG_DMAMUX1 | 39 ///< LPUART2 | LPUART10 DMA receive request
#define DMA_REQ_LPUART311_TX DMAMUX_CHCFG_DMAMUX1 | 40 ///< LPUART3 | LPUART11 DMA transmit request
#define DMA_REQ_LPUART311_RX DMAMUX_CHCFG_DMAMUX1 | 41 ///< LPUART3 | LPUART11 DMA receive request
#define DMA_REQ_LPUART412_TX DMAMUX_CHCFG_DMAMUX1 | 42 ///< LPUART4 | LPUART12 DMA transmit request
#define DMA_REQ_LPUART412_RX DMAMUX_CHCFG_DMAMUX1 | 43 ///< LPUART4 | LPUART12 DMA receive request
#define DMA_REQ_LPUART513_TX DMAMUX_CHCFG_DMAMUX1 | 44 ///< LPUART5 | LPUART13 DMA transmit request
#define DMA_REQ_LPUART513_RX DMAMUX_CHCFG_DMAMUX1 | 45 ///< LPUART5 | LPUART13 DMA receive request
#define DMA_REQ_LPUART614_TX DMAMUX_CHCFG_DMAMUX1 | 46 ///< LPUART6 | LPUART14 DMA transmit request
#define DMA_REQ_LPUART614_RX DMAMUX_CHCFG_DMAMUX1 | 47 ///< LPUART6 | LPUART14 DMA receive request
#define DMA_REQ_LPUART715_TX DMAMUX_CHCFG_DMAMUX1 | 48 ///< LPUART7 | LPUART15 DMA transmit request
#define DMA_REQ_LPUART715_RX DMAMUX_CHCFG_DMAMUX1 | 49 ///< LPUART7 | LPUART15 DMA receive request
#define DMA_REQ_LPI2C1_RX DMAMUX_CHCFG_DMAMUX1 | 50 ///< LPI2C1 DMA receive | receive slave request
#define DMA_REQ_LPI2C1_TX DMAMUX_CHCFG_DMAMUX1 | 51 ///< LPI2C1 DMA transmit | transmit slave request
#define DMA_REQ_LPSPI4_TX DMAMUX_CHCFG_DMAMUX1 | 52 ///< LPSPI4 DMA transmit request
#define DMA_REQ_LPSPI4_RX DMAMUX_CHCFG_DMAMUX1 | 53 ///< LPSPI4 DMA receive request
#define DMA_REQ_LPSPI5_TX DMAMUX_CHCFG_DMAMUX1 | 54 ///< LPSPI5 DMA transmit request
#define DMA_REQ_LPSPI5_RX DMAMUX_CHCFG_DMAMUX1 | 55 ///< LPSPI5 DMA receive request
#define DMA_REQ_SAI1_RX DMAMUX_CHCFG_DMAMUX1 | 56 ///< SAI1 DMA RX request
#define DMA_REQ_SAI1_TX DMAMUX_CHCFG_DMAMUX1 | 57 ///< SAI1 DMA TX request
#define DMA_REQ_RESERVED9 DMAMUX_CHCFG_DMAMUX1 | 58 ///< RESERVED
#define DMA_REQ_RESERVED10 DMAMUX_CHCFG_DMAMUX1 | 59 ///< RESERVED
#define DMA_REQ_LPCMP1 DMAMUX_CHCFG_DMAMUX1 | 60 ///< LPCMP1 DMA request
#define DMA_REQ_LPCMP2 DMAMUX_CHCFG_DMAMUX1 | 61 ///< LPCMP2 DMA request
#define DMA_REQ_ENABLED2 DMAMUX_CHCFG_DMAMUX1 | 62 ///< Always enabled
#define DMA_REQ_ENABLED3 DMAMUX_CHCFG_DMAMUX1 | 63 ///< Always enabled
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EIM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EIM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* EIM Register Offsets *****************************************************/
#define S32K3XX_EIM_EIMCR_OFFSET (0x0000) /* Error Injection Module Configuration Register (EIMCR) */
#define S32K3XX_EIM_EICHEN_OFFSET (0x0004) /* Error Injection Channel Enable Register (EICHEN) */
/* Note: Not all Error Injection Channel Descriptors consist of 6 words.
* See the S32K3xx Reference Manual for more information and to check which
* registers are available.
*/
#define S32K3XX_EIM_EICHD_WORD0_OFFSET(n) (0x0100 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0) */
#define S32K3XX_EIM_EICHD_WORD1_OFFSET(n) (0x0104 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1) */
#define S32K3XX_EIM_EICHD_WORD2_OFFSET(n) (0x0108 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 2 (EICHDn_WORD2) */
#define S32K3XX_EIM_EICHD_WORD3_OFFSET(n) (0x010c + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 3 (EICHDn_WORD3) */
#define S32K3XX_EIM_EICHD_WORD4_OFFSET(n) (0x0110 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 4 (EICHDn_WORD4) */
#define S32K3XX_EIM_EICHD_WORD5_OFFSET(n) (0x0114 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 5 (EICHDn_WORD5) */
#define S32K3XX_EIM_EICHD_WORD6_OFFSET(n) (0x0118 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 6 (EICHDn_WORD6) */
/* EIM Register Addresses ***************************************************/
#define S32K3XX_EIM_EIMCR (S32K3XX_EIM_BASE + S32K3XX_EIM_EIMCR_OFFSET)
#define S32K3XX_EIM_EICHEN (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHEN_OFFSET)
#define S32K3XX_EIM_EICHD_WORD0(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD0_OFFSET(n))
#define S32K3XX_EIM_EICHD_WORD1(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD1_OFFSET(n))
#define S32K3XX_EIM_EICHD_WORD2(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD2_OFFSET(n))
#define S32K3XX_EIM_EICHD_WORD3(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD3_OFFSET(n))
#define S32K3XX_EIM_EICHD_WORD4(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD4_OFFSET(n))
#define S32K3XX_EIM_EICHD_WORD5(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD5_OFFSET(n))
#define S32K3XX_EIM_EICHD_WORD6(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD6_OFFSET(n))
/* EIM Register Bitfield Definitions ****************************************/
/* Error Injection Module Configuration Register (EIMCR) */
#define EIM_EIMCR_GEIEN (1 << 0) /* Bit 0: Global Error Injection Enable (GEIEN) */
/* Bits 1-31: Reserved */
/* Error Injection Channel Enable Register (EICHEN) */
/* Bit 0: Reserved */
#define EIM_EICHEN_EICH30EN (1 << 1) /* Bit 1: Error Injection Channel 30 Enable (EICH30EN) */
#define EIM_EICHEN_EICH29EN (1 << 2) /* Bit 2: Error Injection Channel 29 Enable (EICH29EN) */
#define EIM_EICHEN_EICH28EN (1 << 3) /* Bit 3: Error Injection Channel 28 Enable (EICH28EN) */
#define EIM_EICHEN_EICH27EN (1 << 4) /* Bit 4: Error Injection Channel 27 Enable (EICH27EN) */
#define EIM_EICHEN_EICH26EN (1 << 5) /* Bit 5: Error Injection Channel 26 Enable (EICH26EN) */
#define EIM_EICHEN_EICH25EN (1 << 6) /* Bit 6: Error Injection Channel 25 Enable (EICH25EN) */
#define EIM_EICHEN_EICH24EN (1 << 7) /* Bit 7: Error Injection Channel 24 Enable (EICH24EN) */
#define EIM_EICHEN_EICH23EN (1 << 8) /* Bit 8: Error Injection Channel 23 Enable (EICH23EN) */
#define EIM_EICHEN_EICH22EN (1 << 9) /* Bit 9: Error Injection Channel 22 Enable (EICH22EN) */
#define EIM_EICHEN_EICH21EN (1 << 10) /* Bit 10: Error Injection Channel 21 Enable (EICH21EN) */
#define EIM_EICHEN_EICH20EN (1 << 11) /* Bit 11: Error Injection Channel 20 Enable (EICH20EN) */
#define EIM_EICHEN_EICH19EN (1 << 12) /* Bit 12: Error Injection Channel 19 Enable (EICH19EN) */
#define EIM_EICHEN_EICH18EN (1 << 13) /* Bit 13: Error Injection Channel 18 Enable (EICH18EN) */
#define EIM_EICHEN_EICH17EN (1 << 14) /* Bit 14: Error Injection Channel 17 Enable (EICH17EN) */
#define EIM_EICHEN_EICH16EN (1 << 15) /* Bit 15: Error Injection Channel 16 Enable (EICH16EN) */
#define EIM_EICHEN_EICH15EN (1 << 16) /* Bit 16: Error Injection Channel 15 Enable (EICH15EN) */
#define EIM_EICHEN_EICH14EN (1 << 17) /* Bit 17: Error Injection Channel 14 Enable (EICH14EN) */
#define EIM_EICHEN_EICH13EN (1 << 18) /* Bit 18: Error Injection Channel 13 Enable (EICH13EN) */
#define EIM_EICHEN_EICH12EN (1 << 19) /* Bit 19: Error Injection Channel 12 Enable (EICH12EN) */
#define EIM_EICHEN_EICH11EN (1 << 20) /* Bit 20: Error Injection Channel 11 Enable (EICH11EN) */
#define EIM_EICHEN_EICH10EN (1 << 21) /* Bit 21: Error Injection Channel 10 Enable (EICH10EN) */
#define EIM_EICHEN_EICH9EN (1 << 22) /* Bit 22: Error Injection Channel 9 Enable (EICH9EN) */
#define EIM_EICHEN_EICH8EN (1 << 23) /* Bit 23: Error Injection Channel 8 Enable (EICH8EN) */
#define EIM_EICHEN_EICH7EN (1 << 24) /* Bit 24: Error Injection Channel 7 Enable (EICH7EN) */
#define EIM_EICHEN_EICH6EN (1 << 25) /* Bit 25: Error Injection Channel 6 Enable (EICH6EN) */
#define EIM_EICHEN_EICH5EN (1 << 26) /* Bit 26: Error Injection Channel 5 Enable (EICH5EN) */
#define EIM_EICHEN_EICH4EN (1 << 27) /* Bit 27: Error Injection Channel 4 Enable (EICH4EN) */
#define EIM_EICHEN_EICH3EN (1 << 28) /* Bit 28: Error Injection Channel 3 Enable (EICH3EN) */
#define EIM_EICHEN_EICH2EN (1 << 29) /* Bit 29: Error Injection Channel 2 Enable (EICH2EN) */
#define EIM_EICHEN_EICH1EN (1 << 30) /* Bit 30: Error Injection Channel 1 Enable (EICH1EN) */
#define EIM_EICHEN_EICH0EN (1 << 31) /* Bit 31: Error Injection Channel 0 Enable (EICH0EN) */
/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=0,1,2) */
/* Bits 0-23: Reserved */
#define EIM_EICHD0_2_WORD0_CHKBIT_SHIFT (24) /* Bits 24-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD0_2_WORD0_CHKBIT_MASK (0xff << EIM_EICHD0_2_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor 3, Word 0 (EICHD3_WORD0) */
/* Bits 0-17: Reserved */
#define EIM_EICHD3_WORD0_CHKBIT_SHIFT (18) /* Bits 18-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD3_WORD0_CHKBIT_MASK (0x3fff << EIM_EICHD3_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor 4, Word 0 (EICHD4_WORD0) */
/* Bits 0-15: Reserved */
#define EIM_EICHD4_WORD0_CHKBIT_SHIFT (16) /* Bits 16-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD4_WORD0_CHKBIT_MASK (0xffff << EIM_EICHD4_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=5,6,7) */
/* Bits 0-3: Reserved */
#define EIM_EICHD5_7_WORD0_CHKBIT_SHIFT (4) /* Bits 4-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD5_7_WORD0_CHKBIT_MASK (0x0fffffff << EIM_EICHD5_7_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor 8, Word 0 (EICHD8_WORD0) */
/* Bits 0-17: Reserved */
#define EIM_EICHD8_WORD0_CHKBIT_SHIFT (18) /* Bits 18-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD8_WORD0_CHKBIT_MASK (0x3fff << EIM_EICHD8_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor 9, Word 0 (EICHD9_WORD0) */
/* Bits 0-15: Reserved */
#define EIM_EICHD9_WORD0_CHKBIT_SHIFT (16) /* Bits 16-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD9_WORD0_CHKBIT_MASK (0xffff << EIM_EICHD9_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=10,11,12) */
/* Bits 0-3: Reserved */
#define EIM_EICHD10_12_WORD0_CHKBIT_SHIFT (4) /* Bits 4-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD10_12_WORD0_CHKBIT_MASK (0x0fffffff << EIM_EICHD10_12_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=13,...,18) */
/* Bits 0-23: Reserved */
#define EIM_EICHD13_18_WORD0_CHKBIT_SHIFT (24) /* Bits 24-31: Checkbit Mask (CHKBIT_MASK) */
#define EIM_EICHD13_18_WORD0_CHKBIT_MASK (0xff << EIM_EICHD13_18_WORD0_CHKBIT_SHIFT)
/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=0,1,2) */
#define EIM_EICHD0_2_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD0_2_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD0_2_WORD1_B0_3DATA_SHIFT)
/* Error Injection Channel Descriptor 3, Word 1 (EICHD3_WORD1) */
#define EIM_EICHD3_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-11: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD3_WORD1_B0_3DATA_MASK (0x0fff << EIM_EICHD3_WORD1_B0_3DATA_SHIFT)
/* Bits 12-31: Reserved */
/* Error Injection Channel Descriptor 4, Word 1 (EICHD4_WORD1) */
#define EIM_EICHD4_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD4_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD4_WORD1_B0_3DATA_SHIFT)
/* Error Injection Channel Descriptor 5, Word 1 (EICHD5_WORD1) */
#define EIM_EICHD5_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-7: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD5_WORD1_B0_3DATA_MASK (0xff << EIM_EICHD5_WORD1_B0_3DATA_SHIFT)
/* Bits 8-31: Reserved */
/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=6,7) */
#define EIM_EICHD6_7_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD6_7_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD6_7_WORD1_B0_3DATA_SHIFT)
/* Error Injection Channel Descriptor 8, Word 1 (EICHD8_WORD1) */
#define EIM_EICHD8_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-11: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD8_WORD1_B0_3DATA_MASK (0x0fff << EIM_EICHD8_WORD1_B0_3DATA_SHIFT)
/* Bits 12-31: Reserved */
/* Error Injection Channel Descriptor 9, Word 1 (EICHD9_WORD1) */
#define EIM_EICHD9_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD9_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD9_WORD1_B0_3DATA_SHIFT)
/* Error Injection Channel Descriptor 10, Word 1 (EICHD10_WORD1) */
#define EIM_EICHD10_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-7: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD10_WORD1_B0_3DATA_MASK (0xff << EIM_EICHD10_WORD1_B0_3DATA_SHIFT)
/* Bits 8-31: Reserved */
/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=11,...,18) */
#define EIM_EICHD11_18_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD11_18_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD11_18_WORD1_B0_3DATA_SHIFT)
/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=19,...,26) */
#define EIM_EICHD19_26_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-27: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD19_26_WORD1_B0_3DATA_MASK (0x0fffffff << EIM_EICHD19_26_WORD1_B0_3DATA_SHIFT)
/* Bits 28-31: Reserved */
/* Error Injection Channel Descriptor 27, Word 1 (EICHD27_WORD1) */
#define EIM_EICHD27_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-29: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD27_WORD1_B0_3DATA_MASK (0x3fffffff << EIM_EICHD27_WORD1_B0_3DATA_SHIFT)
/* Bits 30-31: Reserved */
/* Error Injection Channel Descriptor 28, Word 1 (EICHD28_WORD1) */
#define EIM_EICHD28_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-23: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD28_WORD1_B0_3DATA_MASK (0xffffff << EIM_EICHD28_WORD1_B0_3DATA_SHIFT)
/* Bits 24-31: Reserved */
/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=29,30) */
#define EIM_EICHD29_30_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-17: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
#define EIM_EICHD29_30_WORD1_B0_3DATA_MASK (0x03ffff << EIM_EICHD29_30_WORD1_B0_3DATA_SHIFT)
/* Bits 18-31: Reserved */
/* Error Injection Channel Descriptor n, Word 2 (EICHDn_WORD2) */
#define EIM_EICHD_WORD2_B4_7DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 4-7 (B4_7DATA_MASK) */
#define EIM_EICHD_WORD2_B4_7DATA_MASK (0xffffffff << EIM_EICHD_WORD2_B4_7DATA_SHIFT)
/* Error Injection Channel Descriptor n, Word 3 (EICHDn_WORD3) */
#define EIM_EICHD_WORD3_B8_11DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 8-11 (B8_11DATA_MASK) */
#define EIM_EICHD_WORD3_B8_11DATA_MASK (0xffffffff << EIM_EICHD_WORD3_B8_11DATA_SHIFT)
/* Error Injection Channel Descriptor n, Word 4 (EICHDn_WORD4) */
#define EIM_EICHD_WORD4_B12_15DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 12-15 (B12_15DATA_MASK) */
#define EIM_EICHD_WORD4_B12_15DATA_MASK (0xffffffff << EIM_EICHD_WORD4_B12_15DATA_SHIFT)
/* Error Injection Channel Descriptor n, Word 5 (EICHDn_WORD5) */
#define EIM_EICHD_WORD5_B16_19DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 16-19 (B16_19DATA_MASK) */
#define EIM_EICHD_WORD5_B16_19DATA_MASK (0xffffffff << EIM_EICHD_WORD5_B16_19DATA_SHIFT)
/* Error Injection Channel Descriptor n, Word 6 (EICHDn_WORD6) */
#define EIM_EICHD_WORD6_B20_23DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 20-23 (B20_23DATA_MASK) */
#define EIM_EICHD_WORD6_B20_23DATA_MASK (0xffffffff << EIM_EICHD_WORD6_B20_23DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EIM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* eMIOS Register Offsets ***************************************************/
#define S32K3XX_EMIOS_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
#define S32K3XX_EMIOS_GFLAG_OFFSET (0x0004) /* Global Flag Register (GFLAG) */
#define S32K3XX_EMIOS_OUDIS_OFFSET (0x0008) /* Output Update Disable Register (OUDIS) */
#define S32K3XX_EMIOS_UCDIS_OFFSET (0x000c) /* Disable Channel Register (UCDIS) */
#define S32K3XX_EMIOS_A_OFFSET(n) ((n) * 0x0020 + 0x0020) /* UC A n (An) */
#define S32K3XX_EMIOS_B_OFFSET(n) ((n) * 0x0020 + 0x0024) /* UC B n (Bn) */
#define S32K3XX_EMIOS_CNT_OFFSET(n) ((n) * 0x0020 + 0x0028) /* UC Counter n (CNTn) */
#define S32K3XX_EMIOS_C_OFFSET(n) ((n) * 0x0020 + 0x002c) /* UC Control n (Cn) */
#define S32K3XX_EMIOS_S_OFFSET(n) ((n) * 0x0020 + 0x0030) /* UC Status n (Sn) */
#define S32K3XX_EMIOS_ALTA_OFFSET(n) ((n) * 0x0020 + 0x0034) /* Alternate Address n (ALTAn) */
#define S32K3XX_EMIOS_C2_OFFSET(n) ((n) * 0x0020 + 0x0038) /* UC Control 2 n (C2_n) */
/* eMIOS Register Addresses *************************************************/
#define S32K3XX_EMIOS0_MCR (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_MCR_OFFSET)
#define S32K3XX_EMIOS0_GFLAG (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_GFLAG_OFFSET)
#define S32K3XX_EMIOS0_OUDIS (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_OUDIS_OFFSET)
#define S32K3XX_EMIOS0_UCDIS (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_UCDIS_OFFSET)
#define S32K3XX_EMIOS0_A(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_A_OFFSET(n))
#define S32K3XX_EMIOS0_B(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_B_OFFSET(n))
#define S32K3XX_EMIOS0_CNT(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_CNT_OFFSET(n))
#define S32K3XX_EMIOS0_C(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_C_OFFSET(n))
#define S32K3XX_EMIOS0_S(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_S_OFFSET(n))
#define S32K3XX_EMIOS0_ALTA(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_ALTA_OFFSET(n))
#define S32K3XX_EMIOS0_C2(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_C2_OFFSET(n))
#define S32K3XX_EMIOS1_MCR (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_MCR_OFFSET)
#define S32K3XX_EMIOS1_GFLAG (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_GFLAG_OFFSET)
#define S32K3XX_EMIOS1_OUDIS (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_OUDIS_OFFSET)
#define S32K3XX_EMIOS1_UCDIS (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_UCDIS_OFFSET)
#define S32K3XX_EMIOS1_A(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_A_OFFSET(n))
#define S32K3XX_EMIOS1_B(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_B_OFFSET(n))
#define S32K3XX_EMIOS1_CNT(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_CNT_OFFSET(n))
#define S32K3XX_EMIOS1_C(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_C_OFFSET(n))
#define S32K3XX_EMIOS1_S(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_S_OFFSET(n))
#define S32K3XX_EMIOS1_ALTA(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_ALTA_OFFSET(n))
#define S32K3XX_EMIOS1_C2(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_C2_OFFSET(n))
#define S32K3XX_EMIOS2_MCR (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_MCR_OFFSET)
#define S32K3XX_EMIOS2_GFLAG (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_GFLAG_OFFSET)
#define S32K3XX_EMIOS2_OUDIS (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_OUDIS_OFFSET)
#define S32K3XX_EMIOS2_UCDIS (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_UCDIS_OFFSET)
#define S32K3XX_EMIOS2_A(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_A_OFFSET(n))
#define S32K3XX_EMIOS2_B(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_B_OFFSET(n))
#define S32K3XX_EMIOS2_CNT(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_CNT_OFFSET(n))
#define S32K3XX_EMIOS2_C(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_C_OFFSET(n))
#define S32K3XX_EMIOS2_S(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_S_OFFSET(n))
#define S32K3XX_EMIOS2_ALTA(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_ALTA_OFFSET(n))
#define S32K3XX_EMIOS2_C2(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_C2_OFFSET(n))
/* eMIOS Register Bitfield Definitions **************************************/
/* Module Configuration Register (MCR) */
/* Bits 0-7: Reserved */
#define EMIOS_MCR_GPRE_SHIFT (8) /* Bits 8-15: Global Prescaler (GPRE) */
#define EMIOS_MCR_GPRE_MASK (0xff << EMIOS_MCR_GPRE_SHIFT)
#define EMIOS_MCR_GPRE(n) (((n) << EMIOS_MCR_GPRE_SHIFT) & EMIOS_MCR_GPRE_MASK)
/* Bits 16-25: Reserved */
#define EMIOS_MCR_GPREN (1 << 26) /* Bit 26: Global Prescaler Enable (GPREN) */
/* Bit 27: Reserved */
#define EMIOS_MCR_GTBE (1 << 28) /* Bit 28: Global Timebase Enable (GTBE) */
#define EMIOS_MCR_FRZ (1 << 29) /* Bit 29: Freeze (FRZ) */
#define EMIOS_MCR_MDIS (1 << 30) /* Bit 30: Module Disable (MDIS) */
/* Bit 31: Reserved */
/* Global Flag Register (GFLAG) */
#define EMIOS_GFLAG_F0 (1 << 0) /* Bit 0: Mirror of UC 0 FLAG (F0) */
#define EMIOS_GFLAG_F1 (1 << 1) /* Bit 1: Mirror of UC 1 FLAG (F1) */
#define EMIOS_GFLAG_F2 (1 << 2) /* Bit 2: Mirror of UC 2 FLAG (F2) */
#define EMIOS_GFLAG_F3 (1 << 3) /* Bit 3: Mirror of UC 3 FLAG (F3) */
#define EMIOS_GFLAG_F4 (1 << 4) /* Bit 4: Mirror of UC 4 FLAG (F4) */
#define EMIOS_GFLAG_F5 (1 << 5) /* Bit 5: Mirror of UC 5 FLAG (F5) */
#define EMIOS_GFLAG_F6 (1 << 6) /* Bit 6: Mirror of UC 6 FLAG (F6) */
#define EMIOS_GFLAG_F7 (1 << 7) /* Bit 7: Mirror of UC 7 FLAG (F7) */
#define EMIOS_GFLAG_F8 (1 << 8) /* Bit 8: Mirror of UC 8 FLAG (F8) */
#define EMIOS_GFLAG_F9 (1 << 9) /* Bit 9: Mirror of UC 9 FLAG (F9) */
#define EMIOS_GFLAG_F10 (1 << 10) /* Bit 10: Mirror of UC 10 FLAG (F10) */
#define EMIOS_GFLAG_F11 (1 << 11) /* Bit 11: Mirror of UC 11 FLAG (F11) */
#define EMIOS_GFLAG_F12 (1 << 12) /* Bit 12: Mirror of UC 12 FLAG (F12) */
#define EMIOS_GFLAG_F13 (1 << 13) /* Bit 13: Mirror of UC 13 FLAG (F13) */
#define EMIOS_GFLAG_F14 (1 << 14) /* Bit 14: Mirror of UC 14 FLAG (F14) */
#define EMIOS_GFLAG_F15 (1 << 15) /* Bit 15: Mirror of UC 15 FLAG (F15) */
#define EMIOS_GFLAG_F16 (1 << 16) /* Bit 16: Mirror of UC 16 FLAG (F16) */
#define EMIOS_GFLAG_F17 (1 << 17) /* Bit 17: Mirror of UC 17 FLAG (F17) */
#define EMIOS_GFLAG_F18 (1 << 18) /* Bit 18: Mirror of UC 18 FLAG (F18) */
#define EMIOS_GFLAG_F19 (1 << 19) /* Bit 19: Mirror of UC 19 FLAG (F19) */
#define EMIOS_GFLAG_F20 (1 << 20) /* Bit 20: Mirror of UC 20 FLAG (F20) */
#define EMIOS_GFLAG_F21 (1 << 21) /* Bit 21: Mirror of UC 21 FLAG (F21) */
#define EMIOS_GFLAG_F22 (1 << 22) /* Bit 22: Mirror of UC 22 FLAG (F22) */
#define EMIOS_GFLAG_F23 (1 << 23) /* Bit 23: Mirror of UC 23 FLAG (F23) */
/* Bits 24-31: Reserved */
/* Output Update Disable Register (OUDIS) */
#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */
#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */
#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */
#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */
#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */
#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */
#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */
#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */
#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */
#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */
#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */
#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */
#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */
#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */
#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */
#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */
#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */
#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */
#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */
#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */
#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */
#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */
#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */
#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */
#define EMIOS_OUDIS_OU(n) (1 << n) /* Bit n: Channel n Output Update Disable (OU23) */
/* Bits 24-31: Reserved */
/* Disable Channel Register (UCDIS) */
#define EMIOS_UCDIS_OU0 (1 << 0) /* Bit 0: Disable UC 0 (UCDIS0) */
#define EMIOS_UCDIS_OU1 (1 << 1) /* Bit 1: Disable UC 1 (UCDIS1) */
#define EMIOS_UCDIS_OU2 (1 << 2) /* Bit 2: Disable UC 2 (UCDIS2) */
#define EMIOS_UCDIS_OU3 (1 << 3) /* Bit 3: Disable UC 3 (UCDIS3) */
#define EMIOS_UCDIS_OU4 (1 << 4) /* Bit 4: Disable UC 4 (UCDIS4) */
#define EMIOS_UCDIS_OU5 (1 << 5) /* Bit 5: Disable UC 5 (UCDIS5) */
#define EMIOS_UCDIS_OU6 (1 << 6) /* Bit 6: Disable UC 6 (UCDIS6) */
#define EMIOS_UCDIS_OU7 (1 << 7) /* Bit 7: Disable UC 7 (UCDIS7) */
#define EMIOS_UCDIS_OU8 (1 << 8) /* Bit 8: Disable UC 8 (UCDIS8) */
#define EMIOS_UCDIS_OU9 (1 << 9) /* Bit 9: Disable UC 9 (UCDIS9) */
#define EMIOS_UCDIS_OU10 (1 << 10) /* Bit 10: Disable UC 10 (UCDIS10) */
#define EMIOS_UCDIS_OU11 (1 << 11) /* Bit 11: Disable UC 11 (UCDIS11) */
#define EMIOS_UCDIS_OU12 (1 << 12) /* Bit 12: Disable UC 12 (UCDIS12) */
#define EMIOS_UCDIS_OU13 (1 << 13) /* Bit 13: Disable UC 13 (UCDIS13) */
#define EMIOS_UCDIS_OU14 (1 << 14) /* Bit 14: Disable UC 14 (UCDIS14) */
#define EMIOS_UCDIS_OU15 (1 << 15) /* Bit 15: Disable UC 15 (UCDIS15) */
#define EMIOS_UCDIS_OU16 (1 << 16) /* Bit 16: Disable UC 16 (UCDIS16) */
#define EMIOS_UCDIS_OU17 (1 << 17) /* Bit 17: Disable UC 17 (UCDIS17) */
#define EMIOS_UCDIS_OU18 (1 << 18) /* Bit 18: Disable UC 18 (UCDIS18) */
#define EMIOS_UCDIS_OU19 (1 << 19) /* Bit 19: Disable UC 19 (UCDIS19) */
#define EMIOS_UCDIS_OU20 (1 << 20) /* Bit 20: Disable UC 20 (UCDIS20) */
#define EMIOS_UCDIS_OU21 (1 << 21) /* Bit 21: Disable UC 21 (UCDIS21) */
#define EMIOS_UCDIS_OU22 (1 << 22) /* Bit 22: Disable UC 22 (UCDIS22) */
#define EMIOS_UCDIS_OU23 (1 << 23) /* Bit 23: Disable UC 23 (UCDIS23) */
/* Bits 24-31: Reserved */
/* UC A n (An) */
#define EMIOS_A_SHIFT (0) /* Bits 0-15: A */
#define EMIOS_A_MASK (0xffff << EMIOS_A_SHIFT)
#define EMIOS_A(n) ((n << EMIOS_A_SHIFT) & EMIOS_A_MASK)
/* Bits 16-31: Reserved */
/* UC B n (Bn) */
#define EMIOS_B_SHIFT (0) /* Bits 0-15: B */
#define EMIOS_B_MASK (0xffff << EMIOS_B_SHIFT)
#define EMIOS_B(n) ((n << EMIOS_B_SHIFT) & EMIOS_B_MASK)
/* Bits 16-31: Reserved */
/* UC Counter n (CNTn) */
#define EMIOS_CNT_C_SHIFT (0) /* Bits 0-15: Internal Counter Value (C) */
#define EMIOS_CNT_C_MASK (0xffff << EMIOS_CNT_C_SHIFT)
/* Bits 16-31: Reserved */
/* UC Control n (Cn) */
#define EMIOS_C_MODE_SHIFT (0) /* Bits 0-6: Mode Selection (MODE) - NOTE: See S32K3XX Reference Manual for all options! */
#define EMIOS_C_MODE_MASK (0x7f << EMIOS_C_MODE_SHIFT)
# define EMIOS_C_MODE_GPIN (0x00 << EMIOS_C_MODE_SHIFT) /* 000_0000: General-Purpose Input mode */
# define EMIOS_C_MODE_GPOUT (0x01 << EMIOS_C_MODE_SHIFT) /* 000_0001: General-Purpose Output mode */
# define EMIOS_C_MODE_SAIC (0x02 << EMIOS_C_MODE_SHIFT) /* 000_0010: Single Action Input Capture mode */
# define EMIOS_C_MODE_SAIC_EDGE (0x42 << EMIOS_C_MODE_SHIFT) /* 100_0010: Single Action Input Capture mode (with edge capturing) */
# define EMIOS_C_MODE_SAOC (0x03 << EMIOS_C_MODE_SHIFT) /* 000_0011: Single Action Output Capture mode */
# define EMIOS_C_MODE_IPWM (0x04 << EMIOS_C_MODE_SHIFT) /* 000_0100: Input Pulse Width Measurement mode */
# define EMIOS_C_MODE_IPM (0x05 << EMIOS_C_MODE_SHIFT) /* 000_0101: Input Period Measurement mode */
# define EMIOS_C_MODE_DAOC_BMATCH (0x06 << EMIOS_C_MODE_SHIFT) /* 000_0110: Double Action Output Compare mode (with FLAG = 1 on B match) */
# define EMIOS_C_MODE_DAOC_ABMATCH (0x07 << EMIOS_C_MODE_SHIFT) /* 000_0111: Double Action Output Compare mode (with FLAG = 1 on A and B match) */
# define EMIOS_C_MODE_PEC_CONT (0x0a << EMIOS_C_MODE_SHIFT) /* 000_1010: Pulse Edge Counting mode (continuous) */
# define EMIOS_C_MODE_PEC_SINGLE (0x0b << EMIOS_C_MODE_SHIFT) /* 000_1011: Pulse Edge Counting mode (single-shot) */
# define EMIOS_C_MODE_MC_UPCNT_CLRSTRT_INTCLK (0x10 << EMIOS_C_MODE_SHIFT) /* 001_0000: Modulus Counter mode (up counter with clear on match start, internal clock source) */
# define EMIOS_C_MODE_MC_UPCNT_CLRSTRT_EXTCLK (0x11 << EMIOS_C_MODE_SHIFT) /* 001_0001: Modulus Counter mode (up counter with clear on match start, external clock source) */
# define EMIOS_C_MODE_MC_UPCNT_CLREND_INTCLK (0x12 << EMIOS_C_MODE_SHIFT) /* 001_0010: Modulus Counter mode (up counter with clear on match end, internal clock source) */
# define EMIOS_C_MODE_MC_UPCNT_CLREND_EXTCLK (0x13 << EMIOS_C_MODE_SHIFT) /* 001_0011: Modulus Counter mode (up counter with clear on match end, external clock source) */
# define EMIOS_C_MODE_MC_UPDOWNCNT_CLRSTRT_INTCLK (0x14 << EMIOS_C_MODE_SHIFT) /* 001_0100: Modulus Counter mode (up/down counter with clear on match start, internal clock source) */
# define EMIOS_C_MODE_MC_UPDOWNCNT_CLRSTRT_EXTCLK (0x15 << EMIOS_C_MODE_SHIFT) /* 001_0101: Modulus Counter mode (up/down counter with clear on match start, external clock source) */
# define EMIOS_C_MODE_MC_UPDOWNCNT_CLREND_INTCLK (0x16 << EMIOS_C_MODE_SHIFT) /* 001_0110: Modulus Counter mode (up/down counter with clear on match end, internal clock source) */
# define EMIOS_C_MODE_MC_UPDOWNCNT_CLREND_EXTCLK (0x17 << EMIOS_C_MODE_SHIFT) /* 001_0111: Modulus Counter mode (up/down counter with clear on match end, external clock source) */
# define EMIOS_C_MODE_OPWMT (0x26 << EMIOS_C_MODE_SHIFT) /* 010_0110: Output PWM with Trigger mode */
# define EMIOS_C_MODE_MCB_UPCNT_INTCLK (0x50 << EMIOS_C_MODE_SHIFT) /* 101_0000: Modulus Counter Buffered mode (up counter, internal clock source) */
# define EMIOS_C_MODE_MCB_UPCNT_EXTCLK (0x51 << EMIOS_C_MODE_SHIFT) /* 101_0001: Modulus Counter Buffered mode (up counter, external clock source) */
# define EMIOS_C_MODE_MCB_UPDOWNCNT_FSTRT_INTCLK (0x54 << EMIOS_C_MODE_SHIFT) /* 101_0100: Modulus Counter Buffered mode (up/down counter with flag set on match start, internal clock source) */
# define EMIOS_C_MODE_MCB_UPDOWNCNT_FSTRT_EXTCLK (0x55 << EMIOS_C_MODE_SHIFT) /* 101_0101: Modulus Counter Buffered mode (up/down counter with flag set on match start, external clock source) */
# define EMIOS_C_MODE_MCB_UPDOWNCNT_FBND_INTCLK (0x56 << EMIOS_C_MODE_SHIFT) /* 101_0110: Modulus Counter Buffered mode (up/down counter with flag set on period boundary, internal clock source) */
# define EMIOS_C_MODE_MCB_UPDOWNCNT_FBND_EXTCLK (0x57 << EMIOS_C_MODE_SHIFT) /* 101_0111: Modulus Counter Buffered mode (up/down counter with flag set on period boundary, external clock source) */
# define EMIOS_C_MODE_OPWFMB_BMATCH (0x58 << EMIOS_C_MODE_SHIFT) /* 101_1000: Output Pulse Width and Frequency Modulation Buffered mode (BS1 match) */
# define EMIOS_C_MODE_OPWFMB_ABMATCH (0x5a << EMIOS_C_MODE_SHIFT) /* 101_1010: Output Pulse Width and Frequency Modulation Buffered mode (AS1 or BS1 match) */
# define EMIOS_C_MODE_OPWMCB_TRAIL_FTRAIL (0x5c << EMIOS_C_MODE_SHIFT) /* 101_1100: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with trailing edge dead time, input capture flag asserted on trailing edge) */
# define EMIOS_C_MODE_OPWMCB_TRAIL_FBOTH (0x5e << EMIOS_C_MODE_SHIFT) /* 101_1110: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with trailing edge dead time, input capture flag asserted on both edges) */
# define EMIOS_C_MODE_OPWMCB_LEAD_FTRAIL (0x5d << EMIOS_C_MODE_SHIFT) /* 101_1101: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with leading edge dead time, input capture flag asserted on trailing edge) */
# define EMIOS_C_MODE_OPWMCB_LEAD_FBOTH (0x5f << EMIOS_C_MODE_SHIFT) /* 101_1111: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with leading edge dead time, input capture flag asserted on both edges) */
# define EMIOS_C_MODE_OPWMB_BMATCH (0x60 << EMIOS_C_MODE_SHIFT) /* 110_0000: Output PWM Buffered mode (BS1 match) */
# define EMIOS_C_MODE_OPWMB_ABMATCH (0x62 << EMIOS_C_MODE_SHIFT) /* 110_0010: Output PWM Buffered mode (AS1 or BS1 match) */
#define EMIOS_C_EDPOL (1 << 7) /* Bit 7: Edge Polarity (EDPOL) */
#define EMIOS_C_EDSEL (1 << 8) /* Bit 8: Edge Selection (EDSEL) */
#define EMIOS_C_BSL_SHIFT (9) /* Bits 9-10: Bus Select (BSL) */
#define EMIOS_C_BSL_MASK (0x03 << EMIOS_C_BSL_SHIFT)
# define EMIOS_C_BSL_BUSA (0x00 << EMIOS_C_BSL_SHIFT) /* Counter bus A for all channels */
# define EMIOS_C_BSL_BUSBCD (0x01 << EMIOS_C_BSL_SHIFT) /* Counter bus B for channels 0-7, C for 8-15, D for 16-23, E for 24-31 */
# define EMIOS_C_BSL_BUSF (0x02 << EMIOS_C_BSL_SHIFT) /* Counter bus F */
# define EMIOS_C_BSL_INTCNT (0x03 << EMIOS_C_BSL_SHIFT) /* Internal counter for all channels */
/* Bit 11: Reserved */
#define EMIOS_C_FORCMB (1 << 12) /* Bit 12: Force Match B (FORCMB) */
#define EMIOS_C_FORCMA (1 << 13) /* Bit 13: Force Match A (FORCMA) */
/* Bits 14-16: Reserved */
#define EMIOS_C_FEN (1 << 17) /* Bit 17: Flag Enable (FEN) */
#define EMIOS_C_FCK (1 << 18) /* Bit 18: Filter Clock Select (FCK) */
#define EMIOS_C_IF_SHIFT (19) /* Bits 19-22: Input Filter (IF) */
#define EMIOS_C_IF_MASK (0x0f << EMIOS_C_IF_SHIFT)
# define EMIOS_C_IF_BYPASS (0x00 << EMIOS_C_IF_SHIFT) /* Bypassed. Input signal is synchronized before arriving at the digital filter. */
# define EMIOS_C_IF_2CYCLES (0x01 << EMIOS_C_IF_SHIFT) /* 2 Filter Clock Cycles */
# define EMIOS_C_IF_4CYCLES (0x02 << EMIOS_C_IF_SHIFT) /* 4 Filter Clock Cycles */
# define EMIOS_C_IF_8CYCLES (0x04 << EMIOS_C_IF_SHIFT) /* 8 Filter Clock Cycles */
# define EMIOS_C_IF_16CYCLES (0x08 << EMIOS_C_IF_SHIFT) /* 16 Filter Clock Cycles */
/* Bit 23: Reserved */
#define EMIOS_C_DMA (1 << 24) /* Bit 24: Direct Memory Access (DMA) */
#define EMIOS_C_UCPREN (1 << 25) /* Bit 25: Prescaler Enable (UCPREN) */
#define EMIOS_C_UCPRE_SHIFT (26) /* Bits 26-27: Prescaler (UCPRE) */
#define EMIOS_C_UCPRE_MASK (0x03 << EMIOS_C_UCPRE_SHIFT)
# define EMIOS_C_UCPRE_DIV1 (0x00 << EMIOS_C_UCPRE_SHIFT) /* Divide by 1 */
# define EMIOS_C_UCPRE_DIV2 (0x01 << EMIOS_C_UCPRE_SHIFT) /* Divide by 2 */
# define EMIOS_C_UCPRE_DIV3 (0x02 << EMIOS_C_UCPRE_SHIFT) /* Divide by 3 */
# define EMIOS_C_UCPRE_DIV4 (0x03 << EMIOS_C_UCPRE_SHIFT) /* Divide by 4 */
#define EMIOS_C_ODISSL_SHIFT (28) /* Bits 28-29: Output Disable Select (ODISSL) */
#define EMIOS_C_ODISSL_MASK (0x03 << EMIOS_C_ODISSL_SHIFT)
# define EMIOS_C_ODISSL_IN0 (0x00 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 0 */
# define EMIOS_C_ODISSL_IN1 (0x01 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 1 */
# define EMIOS_C_ODISSL_IN2 (0x02 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 2 */
# define EMIOS_C_ODISSL_IN3 (0x03 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 3 */
#define EMIOS_C_ODIS (1 << 30) /* Bit 30: Output Disable (ODIS) */
#define EMIOS_C_FREN (1 << 31) /* Bit 31: Freeze Enable (FREN) */
/* UC Status n (Sn) */
#define EMIOS_S_FLAG (1 << 0) /* Bit 0: Flag indicating input capture or match event (FLAG) */
#define EMIOS_S_UCOUT (1 << 1) /* Bit 1: UC Output Pin state (UCOUT) */
#define EMIOS_S_UCIN (1 << 2) /* Bit 2: UC Input Pin state (UCIN) */
/* Bits 3-14: Reserved */
#define EMIOS_S_OVFL (1 << 15) /* Bit 15: Overflow (OVFL) */
/* Bits 16-30: Reserved */
#define EMIOS_S_OVR (1 << 31) /* Bit 31: Overrun (OVR) */
/* Alternate Address n (ALTAn) */
#define EMIOS_ALTA_SHIFT (0) /* Bits 0-15: Alternate Address */
#define EMIOS_ALTA_MASK (0xffff << EMIOS_ALTA_SHIFT)
/* Bits 16-31: Reserved */
/* UC Control 2 n (C2_n) */
#define EMIOS_C2_UCRELDEL_INT_SHIFT (0) /* Bits 0-4: Reload Signal Output Delay Interval */
#define EMIOS_C2_UCRELDEL_INT_MASK (0x1f << EMIOS_C2_UCRELDEL_INT_SHIFT)
/* Bits 5-13: Reserved */
#define EMIOS_C2_UCPRECLK (1 << 14) /* Bit 14: Prescaler Clock Source (UCPRECLK) */
/* Bit 15: Reserved */
#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
#define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT)
#define EMIOS_C2_UCEXTPRE(n) ((n << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
/* Bits 20-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_firc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FIRC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FIRC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* FIRC Register Offsets ****************************************************/
#define S32K3XX_FIRC_STATUS_OFFSET (0x04) /* Status Register (STATUS) */
#define S32K3XX_FIRC_STDBY_EN_OFFSET (0x08) /* Standby Enable Register (STDBY_EN) */
/* FIRC Register Addresses **************************************************/
#define S32K3XX_FIRC_STATUS (S32K3XX_FIRC_BASE + S32K3XX_FIRC_STATUS_OFFSET)
#define S32K3XX_FIRC_STDBY_EN (S32K3XX_FIRC_BASE + S32K3XX_FIRC_STDBY_EN_OFFSET)
/* FIRC Register Bitfield Definitions ***************************************/
/* Status Register (STATUS) */
#define FIRC_STATUS (1 << 0) /* Bit 0: Status bit for FIRC (STATUS) */
# define FIRC_STATUS_OFF (0 << 0) /* FIRC is off or unstable */
# define FIRC_STATUS_ON (1 << 0) /* FIRC is on and stable */
/* Bits 1-31: Reserved */
/* Standby Enable Register (STDBY_EN) */
#define FIRC_STDBY_EN (1 << 0) /* Bit 0: Enables FIRC in standby mode (STDBY_EN) */
# define FIRC_STDBY_DIS (0 << 0) /* Disables FIRC in standby mode */
/* Bit 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FIRC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FLEXIO_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FLEXIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* FlexIO Register Offsets **************************************************/
#define S32K3XX_FLEXIO_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */
#define S32K3XX_FLEXIO_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */
#define S32K3XX_FLEXIO_CTRL_OFFSET (0x0008) /* FlexIO Control Register (CTRL) */
#define S32K3XX_FLEXIO_PIN_OFFSET (0x000c) /* Pin State Register (PIN) */
#define S32K3XX_FLEXIO_SHIFTSTAT_OFFSET (0x0010) /* Shifter Status Register (SHIFTSTAT) */
#define S32K3XX_FLEXIO_SHIFTERR_OFFSET (0x0014) /* Shifter Error Register (SHIFTERR) */
#define S32K3XX_FLEXIO_TIMSTAT_OFFSET (0x0018) /* Timer Status Register (TIMSTAT) */
#define S32K3XX_FLEXIO_SHIFTSIEN_OFFSET (0x0020) /* Shifter Status Interrupt Enable (SHIFTSIEN) */
#define S32K3XX_FLEXIO_SHIFTEIEN_OFFSET (0x0024) /* Shifter Error Interrupt Enable (SHIFTEIEN) */
#define S32K3XX_FLEXIO_TIMIEN_OFFSET (0x0028) /* Timer Interrupt Enable Register (TIMIEN) */
#define S32K3XX_FLEXIO_SHIFTSDEN_OFFSET (0x0030) /* Shifter Status DMA Enable (SHIFTSDEN) */
#define S32K3XX_FLEXIO_TIMERSDEN_OFFSET (0x0038) /* Timer Status DMA Enable (TIMERSDEN) */
#define S32K3XX_FLEXIO_SHIFTSTATE_OFFSET (0x0040) /* Shifter State Register (SHIFTSTATE) */
#define S32K3XX_FLEXIO_TRGSTAT_OFFSET (0x0048) /* Trigger Status Register (TRGSTAT) */
#define S32K3XX_FLEXIO_TRIGIEN_OFFSET (0x004c) /* External Trigger Interrupt Enable Register (TRIGIEN) */
#define S32K3XX_FLEXIO_PINSTAT_OFFSET (0x0050) /* Pin Status Register (PINSTAT) */
#define S32K3XX_FLEXIO_PINIEN_OFFSET (0x0054) /* Pin Interrupt Enable Register (PINIEN) */
#define S32K3XX_FLEXIO_PINREN_OFFSET (0x0058) /* Pin Rising Edge Enable Register (PINREN) */
#define S32K3XX_FLEXIO_PINFEN_OFFSET (0x005c) /* Pin Falling Edge Enable Register (PINFEN) */
#define S32K3XX_FLEXIO_PINOUTD_OFFSET (0x0060) /* Pin Output Data Register (PINOUTD) */
#define S32K3XX_FLEXIO_PINOUTE_OFFSET (0x0064) /* Pin Output Enable Register (PINOUTE) */
#define S32K3XX_FLEXIO_PINOUTDIS_OFFSET (0x0068) /* Pin Output Disable Register (PINOUTDIS) */
#define S32K3XX_FLEXIO_PINOUTCLR_OFFSET (0x006c) /* Pin Output Clear Register (PINOUTCLR) */
#define S32K3XX_FLEXIO_PINOUTSET_OFFSET (0x0070) /* Pin Output Set Register (PINOUTSET) */
#define S32K3XX_FLEXIO_PINOUTTOG_OFFSET (0x0074) /* Pin Output Toggle Register (PINOUTTOG) */
#define S32K3XX_FLEXIO_SHIFTCTL0_OFFSET (0x0080) /* Shifter Control 0 Register (SHIFTCTL0) */
#define S32K3XX_FLEXIO_SHIFTCTL1_OFFSET (0x0084) /* Shifter Control 1 Register (SHIFTCTL1) */
#define S32K3XX_FLEXIO_SHIFTCTL2_OFFSET (0x0088) /* Shifter Control 2 Register (SHIFTCTL2) */
#define S32K3XX_FLEXIO_SHIFTCTL3_OFFSET (0x008c) /* Shifter Control 3 Register (SHIFTCTL3) */
#define S32K3XX_FLEXIO_SHIFTCTL4_OFFSET (0x0090) /* Shifter Control 4 Register (SHIFTCTL4) */
#define S32K3XX_FLEXIO_SHIFTCTL5_OFFSET (0x0094) /* Shifter Control 5 Register (SHIFTCTL5) */
#define S32K3XX_FLEXIO_SHIFTCTL6_OFFSET (0x0098) /* Shifter Control 6 Register (SHIFTCTL6) */
#define S32K3XX_FLEXIO_SHIFTCTL7_OFFSET (0x009c) /* Shifter Control 7 Register (SHIFTCTL7) */
#define S32K3XX_FLEXIO_SHIFTCFG0_OFFSET (0x0100) /* Shifter Configuration 0 Register (SHIFTCFG0) */
#define S32K3XX_FLEXIO_SHIFTCFG1_OFFSET (0x0104) /* Shifter Configuration 1 Register (SHIFTCFG1) */
#define S32K3XX_FLEXIO_SHIFTCFG2_OFFSET (0x0108) /* Shifter Configuration 2 Register (SHIFTCFG2) */
#define S32K3XX_FLEXIO_SHIFTCFG3_OFFSET (0x010c) /* Shifter Configuration 3 Register (SHIFTCFG3) */
#define S32K3XX_FLEXIO_SHIFTCFG4_OFFSET (0x0110) /* Shifter Configuration 4 Register (SHIFTCFG4) */
#define S32K3XX_FLEXIO_SHIFTCFG5_OFFSET (0x0114) /* Shifter Configuration 5 Register (SHIFTCFG5) */
#define S32K3XX_FLEXIO_SHIFTCFG6_OFFSET (0x0118) /* Shifter Configuration 6 Register (SHIFTCFG6) */
#define S32K3XX_FLEXIO_SHIFTCFG7_OFFSET (0x011c) /* Shifter Configuration 7 Register (SHIFTCFG7) */
#define S32K3XX_FLEXIO_SHIFTBUF0_OFFSET (0x0200) /* Shifter Buffer 0 Register (SHIFTBUF0) */
#define S32K3XX_FLEXIO_SHIFTBUF1_OFFSET (0x0204) /* Shifter Buffer 1 Register (SHIFTBUF1) */
#define S32K3XX_FLEXIO_SHIFTBUF2_OFFSET (0x0208) /* Shifter Buffer 2 Register (SHIFTBUF2) */
#define S32K3XX_FLEXIO_SHIFTBUF3_OFFSET (0x020c) /* Shifter Buffer 3 Register (SHIFTBUF3) */
#define S32K3XX_FLEXIO_SHIFTBUF4_OFFSET (0x0210) /* Shifter Buffer 4 Register (SHIFTBUF4) */
#define S32K3XX_FLEXIO_SHIFTBUF5_OFFSET (0x0214) /* Shifter Buffer 5 Register (SHIFTBUF5) */
#define S32K3XX_FLEXIO_SHIFTBUF6_OFFSET (0x0218) /* Shifter Buffer 6 Register (SHIFTBUF6) */
#define S32K3XX_FLEXIO_SHIFTBUF7_OFFSET (0x021c) /* Shifter Buffer 7 Register (SHIFTBUF7) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS0_OFFSET (0x0280) /* Shifter Buffer 0 Bit Swapped Register (SHIFTBUFBIS0) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS1_OFFSET (0x0284) /* Shifter Buffer 1 Bit Swapped Register (SHIFTBUFBIS1) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS2_OFFSET (0x0288) /* Shifter Buffer 2 Bit Swapped Register (SHIFTBUFBIS2) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS3_OFFSET (0x028c) /* Shifter Buffer 3 Bit Swapped Register (SHIFTBUFBIS3) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS4_OFFSET (0x0290) /* Shifter Buffer 4 Bit Swapped Register (SHIFTBUFBIS4) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS5_OFFSET (0x0294) /* Shifter Buffer 5 Bit Swapped Register (SHIFTBUFBIS5) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS6_OFFSET (0x0298) /* Shifter Buffer 6 Bit Swapped Register (SHIFTBUFBIS6) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS7_OFFSET (0x029c) /* Shifter Buffer 7 Bit Swapped Register (SHIFTBUFBIS7) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS0_OFFSET (0x0300) /* Shifter Buffer 0 Byte Swapped Register (SHIFTBUFBYS0) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS1_OFFSET (0x0304) /* Shifter Buffer 1 Byte Swapped Register (SHIFTBUFBYS1) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS2_OFFSET (0x0308) /* Shifter Buffer 2 Byte Swapped Register (SHIFTBUFBYS2) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS3_OFFSET (0x030c) /* Shifter Buffer 3 Byte Swapped Register (SHIFTBUFBYS3) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS4_OFFSET (0x0310) /* Shifter Buffer 4 Byte Swapped Register (SHIFTBUFBYS4) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS5_OFFSET (0x0314) /* Shifter Buffer 5 Byte Swapped Register (SHIFTBUFBYS5) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS6_OFFSET (0x0318) /* Shifter Buffer 6 Byte Swapped Register (SHIFTBUFBYS6) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS7_OFFSET (0x031c) /* Shifter Buffer 7 Byte Swapped Register (SHIFTBUFBYS7) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS0_OFFSET (0x0380) /* Shifter Buffer 0 Bit Byte Swapped Register (SHIFTBUFBBS0) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS1_OFFSET (0x0384) /* Shifter Buffer 1 Bit Byte Swapped Register (SHIFTBUFBBS1) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS2_OFFSET (0x0388) /* Shifter Buffer 2 Bit Byte Swapped Register (SHIFTBUFBBS2) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS3_OFFSET (0x038c) /* Shifter Buffer 3 Bit Byte Swapped Register (SHIFTBUFBBS3) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS4_OFFSET (0x0390) /* Shifter Buffer 4 Bit Byte Swapped Register (SHIFTBUFBBS4) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS5_OFFSET (0x0394) /* Shifter Buffer 5 Bit Byte Swapped Register (SHIFTBUFBBS5) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS6_OFFSET (0x0398) /* Shifter Buffer 6 Bit Byte Swapped Register (SHIFTBUFBBS6) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS7_OFFSET (0x039c) /* Shifter Buffer 7 Bit Byte Swapped Register (SHIFTBUFBBS7) */
#define S32K3XX_FLEXIO_TIMCTL0_OFFSET (0x0400) /* Timer Control 0 Register (TIMCTL0) */
#define S32K3XX_FLEXIO_TIMCTL1_OFFSET (0x0404) /* Timer Control 1 Register (TIMCTL1) */
#define S32K3XX_FLEXIO_TIMCTL2_OFFSET (0x0408) /* Timer Control 2 Register (TIMCTL2) */
#define S32K3XX_FLEXIO_TIMCTL3_OFFSET (0x040c) /* Timer Control 3 Register (TIMCTL3) */
#define S32K3XX_FLEXIO_TIMCTL4_OFFSET (0x0410) /* Timer Control 4 Register (TIMCTL4) */
#define S32K3XX_FLEXIO_TIMCTL5_OFFSET (0x0414) /* Timer Control 5 Register (TIMCTL5) */
#define S32K3XX_FLEXIO_TIMCTL6_OFFSET (0x0418) /* Timer Control 6 Register (TIMCTL6) */
#define S32K3XX_FLEXIO_TIMCTL7_OFFSET (0x041c) /* Timer Control 7 Register (TIMCTL7) */
#define S32K3XX_FLEXIO_TIMCFG0_OFFSET (0x0480) /* Timer Configuration 0 Register (TIMCFG0) */
#define S32K3XX_FLEXIO_TIMCFG1_OFFSET (0x0484) /* Timer Configuration 1 Register (TIMCFG1) */
#define S32K3XX_FLEXIO_TIMCFG2_OFFSET (0x0488) /* Timer Configuration 2 Register (TIMCFG2) */
#define S32K3XX_FLEXIO_TIMCFG3_OFFSET (0x048c) /* Timer Configuration 3 Register (TIMCFG3) */
#define S32K3XX_FLEXIO_TIMCFG4_OFFSET (0x0490) /* Timer Configuration 4 Register (TIMCFG4) */
#define S32K3XX_FLEXIO_TIMCFG5_OFFSET (0x0494) /* Timer Configuration 5 Register (TIMCFG5) */
#define S32K3XX_FLEXIO_TIMCFG6_OFFSET (0x0498) /* Timer Configuration 6 Register (TIMCFG6) */
#define S32K3XX_FLEXIO_TIMCFG7_OFFSET (0x049c) /* Timer Configuration 7 Register (TIMCFG7) */
#define S32K3XX_FLEXIO_TIMCMP0_OFFSET (0x0500) /* Timer Compare 0 Register (TIMCMP0) */
#define S32K3XX_FLEXIO_TIMCMP1_OFFSET (0x0504) /* Timer Compare 1 Register (TIMCMP1) */
#define S32K3XX_FLEXIO_TIMCMP2_OFFSET (0x0508) /* Timer Compare 2 Register (TIMCMP2) */
#define S32K3XX_FLEXIO_TIMCMP3_OFFSET (0x050c) /* Timer Compare 3 Register (TIMCMP3) */
#define S32K3XX_FLEXIO_TIMCMP4_OFFSET (0x0510) /* Timer Compare 4 Register (TIMCMP4) */
#define S32K3XX_FLEXIO_TIMCMP5_OFFSET (0x0514) /* Timer Compare 5 Register (TIMCMP5) */
#define S32K3XX_FLEXIO_TIMCMP6_OFFSET (0x0518) /* Timer Compare 6 Register (TIMCMP6) */
#define S32K3XX_FLEXIO_TIMCMP7_OFFSET (0x051c) /* Timer Compare 7 Register (TIMCMP7) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS0_OFFSET (0x0680) /* Shifter Buffer 0 Nibble Byte Swapped Register (SHIFTBUFNBS0) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS1_OFFSET (0x0684) /* Shifter Buffer 1 Nibble Byte Swapped Register (SHIFTBUFNBS1) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS2_OFFSET (0x0688) /* Shifter Buffer 2 Nibble Byte Swapped Register (SHIFTBUFNBS2) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS3_OFFSET (0x068c) /* Shifter Buffer 3 Nibble Byte Swapped Register (SHIFTBUFNBS3) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS4_OFFSET (0x0690) /* Shifter Buffer 4 Nibble Byte Swapped Register (SHIFTBUFNBS4) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS5_OFFSET (0x0694) /* Shifter Buffer 5 Nibble Byte Swapped Register (SHIFTBUFNBS5) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS6_OFFSET (0x0698) /* Shifter Buffer 6 Nibble Byte Swapped Register (SHIFTBUFNBS6) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS7_OFFSET (0x069c) /* Shifter Buffer 7 Nibble Byte Swapped Register (SHIFTBUFNBS7) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS0_OFFSET (0x0700) /* Shifter Buffer 0 Half Word Swapped Register (SHIFTBUFHWS0) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS1_OFFSET (0x0704) /* Shifter Buffer 1 Half Word Swapped Register (SHIFTBUFHWS1) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS2_OFFSET (0x0708) /* Shifter Buffer 2 Half Word Swapped Register (SHIFTBUFHWS2) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS3_OFFSET (0x071c) /* Shifter Buffer 3 Half Word Swapped Register (SHIFTBUFHWS3) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS4_OFFSET (0x0710) /* Shifter Buffer 4 Half Word Swapped Register (SHIFTBUFHWS4) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS5_OFFSET (0x0714) /* Shifter Buffer 5 Half Word Swapped Register (SHIFTBUFHWS5) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS6_OFFSET (0x0718) /* Shifter Buffer 6 Half Word Swapped Register (SHIFTBUFHWS6) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS7_OFFSET (0x071c) /* Shifter Buffer 7 Half Word Swapped Register (SHIFTBUFHWS7) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS0_OFFSET (0x0780) /* Shifter Buffer 0 Nibble Swapped Register (SHIFTBUFNIS0) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS1_OFFSET (0x0784) /* Shifter Buffer 1 Nibble Swapped Register (SHIFTBUFNIS1) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS2_OFFSET (0x0788) /* Shifter Buffer 2 Nibble Swapped Register (SHIFTBUFNIS2) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS3_OFFSET (0x078c) /* Shifter Buffer 3 Nibble Swapped Register (SHIFTBUFNIS3) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS4_OFFSET (0x0790) /* Shifter Buffer 4 Nibble Swapped Register (SHIFTBUFNIS4) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS5_OFFSET (0x0794) /* Shifter Buffer 5 Nibble Swapped Register (SHIFTBUFNIS5) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS6_OFFSET (0x0798) /* Shifter Buffer 6 Nibble Swapped Register (SHIFTBUFNIS6) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS7_OFFSET (0x079c) /* Shifter Buffer 7 Nibble Swapped Register (SHIFTBUFNIS7) */
#define S32K3XX_FLEXIO_SHIFTBUFOES0_OFFSET (0x0800) /* Shifter Buffer 0 Odd Even Swapped Register (SHIFTBUFOES0) */
#define S32K3XX_FLEXIO_SHIFTBUFOES1_OFFSET (0x0804) /* Shifter Buffer 1 Odd Even Swapped Register (SHIFTBUFOES1) */
#define S32K3XX_FLEXIO_SHIFTBUFOES2_OFFSET (0x0808) /* Shifter Buffer 2 Odd Even Swapped Register (SHIFTBUFOES2) */
#define S32K3XX_FLEXIO_SHIFTBUFOES3_OFFSET (0x080c) /* Shifter Buffer 3 Odd Even Swapped Register (SHIFTBUFOES3) */
#define S32K3XX_FLEXIO_SHIFTBUFOES4_OFFSET (0x0810) /* Shifter Buffer 4 Odd Even Swapped Register (SHIFTBUFOES4) */
#define S32K3XX_FLEXIO_SHIFTBUFOES5_OFFSET (0x0814) /* Shifter Buffer 5 Odd Even Swapped Register (SHIFTBUFOES5) */
#define S32K3XX_FLEXIO_SHIFTBUFOES6_OFFSET (0x0818) /* Shifter Buffer 6 Odd Even Swapped Register (SHIFTBUFOES6) */
#define S32K3XX_FLEXIO_SHIFTBUFOES7_OFFSET (0x081c) /* Shifter Buffer 7 Odd Even Swapped Register (SHIFTBUFOES7) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS0_OFFSET (0x0880) /* Shifter Buffer 0 Even Odd Swapped Register (SHIFTBUFEOS0) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS1_OFFSET (0x0884) /* Shifter Buffer 1 Even Odd Swapped Register (SHIFTBUFEOS1) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS2_OFFSET (0x0888) /* Shifter Buffer 2 Even Odd Swapped Register (SHIFTBUFEOS2) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS3_OFFSET (0x088c) /* Shifter Buffer 3 Even Odd Swapped Register (SHIFTBUFEOS3) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS4_OFFSET (0x0890) /* Shifter Buffer 4 Even Odd Swapped Register (SHIFTBUFEOS4) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS5_OFFSET (0x0894) /* Shifter Buffer 5 Even Odd Swapped Register (SHIFTBUFEOS5) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS6_OFFSET (0x0898) /* Shifter Buffer 6 Even Odd Swapped Register (SHIFTBUFEOS6) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS7_OFFSET (0x089c) /* Shifter Buffer 7 Even Odd Swapped Register (SHIFTBUFEOS7) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS0_OFFSET (0x0900) /* Shifter Buffer 0 Halfword Byte Swapped Register (SHIFTBUFHBS0) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS1_OFFSET (0x0904) /* Shifter Buffer 1 Halfword Byte Swapped Register (SHIFTBUFHBS1) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS2_OFFSET (0x0908) /* Shifter Buffer 2 Halfword Byte Swapped Register (SHIFTBUFHBS2) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS3_OFFSET (0x090c) /* Shifter Buffer 3 Halfword Byte Swapped Register (SHIFTBUFHBS3) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS4_OFFSET (0x0910) /* Shifter Buffer 4 Halfword Byte Swapped Register (SHIFTBUFHBS4) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS5_OFFSET (0x0914) /* Shifter Buffer 5 Halfword Byte Swapped Register (SHIFTBUFHBS5) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS6_OFFSET (0x0918) /* Shifter Buffer 6 Halfword Byte Swapped Register (SHIFTBUFHBS6) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS7_OFFSET (0x091c) /* Shifter Buffer 7 Halfword Byte Swapped Register (SHIFTBUFHBS7) */
#define S32K3XX_FLEXIO_SHIFTCTL_OFFSET(n) (0x0080 + ((n) << 2)) /* Shifter Control n Register (SHIFTCTLn) */
#define S32K3XX_FLEXIO_SHIFTCFG_OFFSET(n) (0x0100 + ((n) << 2)) /* Shifter Configuration n Register (SHIFTCFGn) */
#define S32K3XX_FLEXIO_SHIFTBUF_OFFSET(n) (0x0200 + ((n) << 2)) /* Shifter Buffer n Register (SHIFTBUFn) */
#define S32K3XX_FLEXIO_SHIFTBUFBIS_OFFSET(n) (0x0280 + ((n) << 2)) /* Shifter Buffer n Bit Swapped Register (SHIFTBUFBISn) */
#define S32K3XX_FLEXIO_SHIFTBUFBYS_OFFSET(n) (0x0300 + ((n) << 2)) /* Shifter Buffer n Byte Swapped Register (SHIFTBUFBYSn) */
#define S32K3XX_FLEXIO_SHIFTBUFBBS_OFFSET(n) (0x0380 + ((n) << 2)) /* Shifter Buffer n Bit Byte Swapped Register (SHIFTBUFBBSn) */
#define S32K3XX_FLEXIO_TIMCTL_OFFSET(n) (0x0400 + ((n) << 2)) /* Timer Control n Register (TIMCTLn) */
#define S32K3XX_FLEXIO_TIMCFG_OFFSET(n) (0x0480 + ((n) << 2)) /* Timer Configuration n Register (TIMCFGn) */
#define S32K3XX_FLEXIO_TIMCMP_OFFSET(n) (0x0500 + ((n) << 2)) /* Timer Compare n Register (TIMCMPn) */
#define S32K3XX_FLEXIO_SHIFTBUFNBS_OFFSET(n) (0x0680 + ((n) << 2)) /* Shifter Buffer n Nibble Byte Swapped Register (SHIFTBUFNBSn) */
#define S32K3XX_FLEXIO_SHIFTBUFHWS_OFFSET(n) (0x0700 + ((n) << 2)) /* Shifter Buffer n Half Word Swapped Register (SHIFTBUFHWSn) */
#define S32K3XX_FLEXIO_SHIFTBUFNIS_OFFSET(n) (0x0780 + ((n) << 2)) /* Shifter Buffer n Nibble Swapped Register (SHIFTBUFNISn) */
#define S32K3XX_FLEXIO_SHIFTBUFOES_OFFSET(n) (0x0800 + ((n) << 2)) /* Shifter Buffer n Odd Even Swapped Register (SHIFTBUFOESn) */
#define S32K3XX_FLEXIO_SHIFTBUFEOS_OFFSET(n) (0x0880 + ((n) << 2)) /* Shifter Buffer n Even Odd Swapped Register (SHIFTBUFEOSn) */
#define S32K3XX_FLEXIO_SHIFTBUFHBS_OFFSET(n) (0x0900 + ((n) << 2)) /* Shifter Buffer n Halfword Byte Swapped Register (SHIFTBUFHBSn) */
/* FlexIO Register Addresses ************************************************/
#define S32K3XX_FLEXIO_VERID (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_VERID_OFFSET)
#define S32K3XX_FLEXIO_PARAM (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PARAM_OFFSET)
#define S32K3XX_FLEXIO_CTRL (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_CTRL_OFFSET)
#define S32K3XX_FLEXIO_PIN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PIN_OFFSET)
#define S32K3XX_FLEXIO_SHIFTSTAT (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTSTAT_OFFSET)
#define S32K3XX_FLEXIO_SHIFTERR (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTERR_OFFSET)
#define S32K3XX_FLEXIO_TIMSTAT (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMSTAT_OFFSET)
#define S32K3XX_FLEXIO_SHIFTSIEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTSIEN_OFFSET)
#define S32K3XX_FLEXIO_SHIFTEIEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTEIEN_OFFSET)
#define S32K3XX_FLEXIO_TIMIEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMIEN_OFFSET)
#define S32K3XX_FLEXIO_SHIFTSDEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTSDEN_OFFSET)
#define S32K3XX_FLEXIO_TIMERSDEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMERSDEN_OFFSET)
#define S32K3XX_FLEXIO_SHIFTSTATE (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTSTATE_OFFSET)
#define S32K3XX_FLEXIO_TRGSTAT (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TRGSTAT_OFFSET)
#define S32K3XX_FLEXIO_TRIGIEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TRIGIEN_OFFSET)
#define S32K3XX_FLEXIO_PINSTAT (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINSTAT_OFFSET)
#define S32K3XX_FLEXIO_PINIEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINIEN_OFFSET)
#define S32K3XX_FLEXIO_PINREN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINREN_OFFSET)
#define S32K3XX_FLEXIO_PINFEN (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINFEN_OFFSET)
#define S32K3XX_FLEXIO_PINOUTD (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINOUTD_OFFSET)
#define S32K3XX_FLEXIO_PINOUTE (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINOUTE_OFFSET)
#define S32K3XX_FLEXIO_PINOUTDIS (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINOUTDIS_OFFSET)
#define S32K3XX_FLEXIO_PINOUTCLR (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINOUTCLR_OFFSET)
#define S32K3XX_FLEXIO_PINOUTSET (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINOUTSET_OFFSET)
#define S32K3XX_FLEXIO_PINOUTTOG (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_PINOUTTOG_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCFG7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUF7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBIS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBYS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFBBS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS7_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL0_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL1_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL2_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL3_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL4_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL5_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL6_OFFSET)
#define S32K3XX_FLEXIO_TIMCTL7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL7_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG0_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG1_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG2_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG3_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG4_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG5_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG6_OFFSET)
#define S32K3XX_FLEXIO_TIMCFG7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG7_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP0_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP1_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP2_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP3_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP4_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP5_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP6_OFFSET)
#define S32K3XX_FLEXIO_TIMCMP7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNBS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHWS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFNIS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFOES7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFEOS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS0 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS0_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS1 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS1_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS2 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS2_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS3 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS3_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS4 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS4_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS5 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS5_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS6 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS6_OFFSET)
#define S32K3XX_FLEXIO_SHIFTBUFHBS7 (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS7_OFFSET)
#define S32K3XX_FLEXIO_SHIFTCTL(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCTL_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTCFG(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTCFG_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUF(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUF_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFBIS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBIS_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFBYS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBYS_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFBBS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFBBS_OFFSET(n))
#define S32K3XX_FLEXIO_TIMCTL(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCTL_OFFSET(n))
#define S32K3XX_FLEXIO_TIMCFG(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCFG_OFFSET(n))
#define S32K3XX_FLEXIO_TIMCMP(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_TIMCMP_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFNBS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNBS_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFHWS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHWS_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFNIS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFNIS_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFOES(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFOES_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFEOS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFEOS_OFFSET(n))
#define S32K3XX_FLEXIO_SHIFTBUFHBS(n) (S32K3XX_FLEXIO_BASE + S32K3XX_FLEXIO_SHIFTBUFHBS_OFFSET(n))
/* Register Bit Definitions *************************************************/
/* Version ID Register (VERID) */
#define FLEXIO_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Specification Number (FEATURE) */
#define FLEXIO_VERID_FEATURE_MASK (0xffff << FLEXIO_VERID_FEATURE_SHIFT)
#define FLEXIO_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define FLEXIO_VERID_MINOR_MASK (0xff << FLEXIO_VERID_MINOR_SHIFT)
#define FLEXIO_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define FLEXIO_VERID_MAJOR_MASK (0xff << FLEXIO_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define FLEXIO_PARAM_SHIFTER_SHIFT (0) /* Bits 0-7: Shifter Number (SHIFTER) */
#define FLEXIO_PARAM_SHIFTER_MASK (0xff << FLEXIO_PARAM_SHIFTER_SHIFT)
#define FLEXIO_PARAM_TIMER_SHIFT (8) /* Bits 8-15: Timer Number (TIMER) */
#define FLEXIO_PARAM_TIMER_MASK (0xff << FLEXIO_PARAM_TIMER_SHIFT)
#define FLEXIO_PARAM_PIN_SHIFT (16) /* Bits 16-23: Pin Number (PIN) */
#define FLEXIO_PARAM_PIN_MASK (0xff << FLEXIO_PARAM_PIN_SHIFT)
#define FLEXIO_PARAM_TRIGGER_SHIFT (24) /* Bits 24-31: Trigger Number (TRIGGER) */
#define FLEXIO_PARAM_TRIGGER_MASK (0xff << FLEXIO_PARAM_TRIGGER_SHIFT)
/* FlexIO Control Register (CTRL) */
#define FLEXIO_CTRL_FLEXEN (1 << 0) /* Bit 0: FlexIO Enable (FLEXEN) */
# define FLEXIO_CTRL_FLEXEN_DIS (0 << 0) /* FlexIO module is disabled */
# define FLEXIO_CTRL_FLEXEN_ENA (1 << 0) /* FlexIO module is enabled */
#define FLEXIO_CTRL_SWRST (1 << 1) /* Bit 1: Software Reset (SWRST) */
# define FLEXIO_CTRL_SWRST_DIS (0 << 1) /* Software reset is disabled */
# define FLEXIO_CTRL_SWRST_ENA (1 << 1) /* Software reset is enabled */
#define FLEXIO_CTRL_FASTACC (1 << 2) /* Bit 2: Fast Access (FASTACC) */
# define FLEXIO_CTRL_FASTACC_NORMAL (0 << 2) /* Configures for normal register accesses to FlexIO */
# define FLEXIO_CTRL_FASTACC_FAST (1 << 2) /* Configures for fast register accesses to FlexIO */
/* Bits 3-29: Reserved */
#define FLEXIO_CTRL_DBGE (1 << 30) /* Bit 30: Debug Enable (DBGE) */
# define FLEXIO_CTRL_DBGE_DIS (0 << 30) /* FlexIO is disabled in debug modes */
# define FLEXIO_CTRL_DBGE_ENA (1 << 30) /* FlexIO is enabled in debug modes */
/* Bit 31: Reserved */
/* Pin State Register (PIN) */
#define FLEXIO_PIN_PDI_SHIFT (0) /* Bits 0-31: Pin Data Input (PDI) */
#define FLEXIO_PIN_PDI_MASK (0xffffffff << FLEXIO_PIN_PDI_SHIFT)
/* Shifter Status Register (SHIFTSTAT) */
#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0) /* Bits 0-7: Shifter Status Flag (SSF) */
#define FLEXIO_SHIFTSTAT_SSF_MASK (0xff << FLEXIO_SHIFTSTAT_SSF_SHIFT)
/* Bits 8-31: Reserved */
/* Shifter Error Register (SHIFTERR) */
#define FLEXIO_SHIFTERR_SEF_SHIFT (0) /* Bits 0-7: Shifter Error Flags (SEF) */
#define FLEXIO_SHIFTERR_SEF_MASK (0xff << FLEXIO_SHIFTERR_SEF_SHIFT)
/* Bits 8-31: Reserved */
/* Timer Status Register (TIMSTAT) */
#define FLEXIO_TIMSTAT_TSF_SHIFT (0) /* Bits 0-7: Timer Status Flags (TSF) */
#define FLEXIO_TIMSTAT_TSF_MASK (0xff << FLEXIO_TIMSTAT_TSF_SHIFT)
/* Bits 8-31: Reserved */
/* Shifter Status Interrupt Enable (SHIFTSIEN) */
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0) /* Bits 0-7: Shifter Status Interrupt Enable (SSIE) */
#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xff << FLEXIO_SHIFTSIEN_SSIE_SHIFT)
/* Bits 8-31: Reserved */
/* Shifter Error Interrupt Enable (SHIFTEIEN) */
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0) /* Bits 0-7: Shifter Error Interrupt Enable (SEIE) */
#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xff << FLEXIO_SHIFTEIEN_SEIE_SHIFT)
/* Bits 8-31: Reserved */
/* Timer Interrupt Enable Register (TIMIEN) */
#define FLEXIO_TIMIEN_TEIE_SHIFT (0) /* Bits 0-7: Timer Status Interrupt Enable (TEIE) */
#define FLEXIO_TIMIEN_TEIE_MASK (0xff << FLEXIO_TIMIEN_TEIE_SHIFT)
/* Bits 8-31: Reserved */
/* Shifter Status DMA Enable (SHIFTSDEN) */
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0) /* Bits 0-7: Shifter Status DMA Enable (SSDE) */
#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xff << FLEXIO_SHIFTSDEN_SSDE_SHIFT)
/* Bits 8-31: Reserved */
/* Timer Status DMA Enable (TIMERSDEN) */
#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0) /* Bits 0-7: Timer Status DMA Enable (TSDE) */
#define FLEXIO_TIMERSDEN_TSDE_MASK (0xff << FLEXIO_TIMERSDEN_TSDE_SHIFT)
/* Bits 8-31: Reserved */
/* Shifter State Register (SHIFTSTATE) */
#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0) /* Bits 0-2: Current State Pointer (STATE) */
#define FLEXIO_SHIFTSTATE_STATE_MASK (0x07 << FLEXIO_SHIFTSTATE_STATE_SHIFT)
/* Bits 3-31: Reserved */
/* Trigger Status Register (TRGSTAT) */
#define FLEXIO_TRGSTAT_ETSF_SHIFT (0) /* Bits 0-3: External Trigger Status Flags (ETSF) */
#define FLEXIO_TRGSTAT_ETSF_MASK (0x0f << FLEXIO_TRGSTAT_ETSF_SHIFT)
/* Bits 4-31: Reserved */
/* External Trigger Interrupt Enable Register (TRIGIEN) */
#define FLEXIO_TRIGIEN_TRIE_SHIFT (0) /* Bits 0-3: External Trigger Interrupt Enable (TRIE) */
#define FLEXIO_TRIGIEN_TRIE_MASK (0x0f << FLEXIO_TRIGIEN_TRIE_SHIFT)
/* Bits 4-31: Reserved */
/* Pin Status Register (PINSTAT) */
#define FLEXIO_PINSTAT_PSF_SHIFT (0) /* Bits 0-31: Pin Status Flags (PSF) */
#define FLEXIO_PINSTAT_PSF_MASK (0xffffffff << FLEXIO_PINSTAT_PSF_SHIFT)
/* Pin Interrupt Enable Register (PINIEN) */
#define FLEXIO_PINIEN_PSIE_SHIFT (0) /* Bits 0-31: Pin Status Interrupt Enable (PSIE) */
#define FLEXIO_PINIEN_PSIE_MASK (0xffffffff << FLEXIO_PINIEN_PSIE_SHIFT)
/* Pin Rising Edge Enable Register (PINREN) */
#define FLEXIO_PINREN_PRE_SHIFT (0) /* Bits 0-31: Pin Rising Edge (PRE) */
#define FLEXIO_PINREN_PRE_MASK (0xffffffff << FLEXIO_PINREN_PRE_SHIFT)
/* Pin Falling Edge Enable Register (PINFEN) */
#define FLEXIO_PINFEN_PFE_SHIFT (0) /* Bits 0-31: Pin Falling Edge (PFE) */
#define FLEXIO_PINFEN_PFE_MASK (0xffffffff << FLEXIO_PINFEN_PFE_SHIFT)
/* Pin Output Data Register (PINOUTD) */
#define FLEXIO_PINOUTD_OUTD_SHIFT (0) /* Bits 0-31: Output Data (OUTD) */
#define FLEXIO_PINOUTD_OUTD_MASK (0xffffffff << FLEXIO_PINOUTD_OUTD_SHIFT)
/* Pin Output Enable Register (PINOUTE) */
#define FLEXIO_PINOUTE_OUTE_SHIFT (0) /* Bits 0-31: Output Enable (OUTE) */
#define FLEXIO_PINOUTE_OUTE_MASK (0xffffffff << FLEXIO_PINOUTE_OUTE_SHIFT)
/* Pin Output Disable Register (PINOUTDIS) */
#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0) /* Bits 0-31: Output Disable (OUTDIS) */
#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xffffffff << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)
/* Pin Output Clear Register (PINOUTCLR) */
#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0) /* Bits 0-31: Output Clear (OUTCLR) */
#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xffffffff << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)
/* Pin Output Set Register (PINOUTSET) */
#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0) /* Bits 0-31: Output Set (OUTSET) */
#define FLEXIO_PINOUTSET_OUTSET_MASK (0xffffffff << FLEXIO_PINOUTSET_OUTSET_SHIFT)
/* Pin Output Toggle Register (PINOUTTOG) */
#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0) /* Bits 0-31: Output Toggle (OUTTOG) */
#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xffffffff << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)
/* Shifter Control n Register (SHIFTCTLn) */
#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0) /* Bits 0-2: Shifter Mode (SMOD) */
#define FLEXIO_SHIFTCTL_SMOD_MASK (0x07 << FLEXIO_SHIFTCTL_SMOD_SHIFT)
# define FLEXIO_SHIFTCTL_SMOD_DIS (0x00 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* Disabled */
# define FLEXIO_SHIFTCTL_SMOD_RX (0x01 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* Receive mode */
# define FLEXIO_SHIFTCTL_SMOD_TX (0x02 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* Transmit mode */
# define FLEXIO_SHIFTCTL_SMOD_STORE (0x04 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* Match Store mode */
# define FLEXIO_SHIFTCTL_SMOD_CONT (0x05 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* Match Continuous mode */
# define FLEXIO_SHIFTCTL_SMOD_STATE (0x06 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* State mode */
# define FLEXIO_SHIFTCTL_SMOD_LOGIC (0x07 << FLEXIO_SHIFTCTL_SMOD_SHIFT) /* Logic mode */
/* Bits 3-6: Reserved */
#define FLEXIO_SHIFTCTL_PINPOL (1 << 7) /* Bit 7: Shifter Pin Polarity (PINPOL) */
# define FLEXIO_SHIFTCTL_PINPOL_HI (0 << 7) /* Pin is active high */
# define FLEXIO_SHIFTCTL_PINPOL_LO (1 << 7) /* Pin is active low */
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8) /* Bits 8-12: Shifter Pin Select (PINSEL) */
#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1f << FLEXIO_SHIFTCTL_PINSEL_SHIFT)
# define FLEXIO_SHIFTCTL_PINSEL(n) (((n) << FLEXIO_SHIFTCTL_PINSEL_SHIFT) & FLEXIO_SHIFTCTL_PINSEL_MASK)
/* Bits 13-15: Reserved */
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16) /* Bits 16-17: Shifter Pin Configuration (PINCFG) */
#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x03 << FLEXIO_SHIFTCTL_PINCFG_SHIFT)
# define FLEXIO_SHIFTCTL_PINCFG_DIS (0x00 << FLEXIO_SHIFTCTL_PINCFG_SHIFT) /* Shifter pin output disabled */
# define FLEXIO_SHIFTCTL_PINCFG_OD (0x01 << FLEXIO_SHIFTCTL_PINCFG_SHIFT) /* Shifter pin open drain or bidirectional output enable */
# define FLEXIO_SHIFTCTL_PINCFG_BID (0x02 << FLEXIO_SHIFTCTL_PINCFG_SHIFT) /* Shifter pin bidirectional output data */
# define FLEXIO_SHIFTCTL_PINCFG_OUT (0x03 << FLEXIO_SHIFTCTL_PINCFG_SHIFT) /* Shifter pin output */
/* Bits 18-22: Reserved */
#define FLEXIO_SHIFTCTL_TIMPOL (1 << 23) /* Bit 23: Timer Polarity (TIMPOL) */
# define FLEXIO_SHIFTCTL_TIMPOL_PE (0 << 23) /* Shift on posedge of Shift clock */
# define FLEXIO_SHIFTCTL_TIMPOL_NE (1 << 23) /* Shift on negedge of Shift clock */
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24) /* Bits 24-26: Timer Select (TIMSEL) */
#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x07 << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)
# define FLEXIO_SHIFTCTL_TIMSEL(n) (((n) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/* Bits 27-31: Reserved */
/* Shifter Configuration n Register (SHIFTCFGn) */
#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0) /* Bits 0-1: Shifter Start bit (SSTART) */
#define FLEXIO_SHIFTCFG_SSTART_MASK (0x03 << FLEXIO_SHIFTCFG_SSTART_SHIFT)
# define FLEXIO_SHIFTCFG_SSTART_DIS (0x00 << FLEXIO_SHIFTCFG_SSTART_SHIFT) /* Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable */
# define FLEXIO_SHIFTCFG_SSTART_DIS_SH (0x01 << FLEXIO_SHIFTCFG_SSTART_SHIFT) /* Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift */
# define FLEXIO_SHIFTCFG_SSTART_ZERO (0x02 << FLEXIO_SHIFTCFG_SSTART_SHIFT) /* Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 */
# define FLEXIO_SHIFTCFG_SSTART_ONE (0x03 << FLEXIO_SHIFTCFG_SSTART_SHIFT) /* Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 */
/* Bits 2-3: Reserved */
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4) /* Bits 4-5: Shifter Stop bit (SSTOP) */
#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x03 << FLEXIO_SHIFTCFG_SSTOP_SHIFT)
# define FLEXIO_SHIFTCFG_SSTOP_DIS (0x00 << FLEXIO_SHIFTCFG_SSTOP_SHIFT) /* Stop bit disabled for transmitter/receiver/match store */
# define FLEXIO_SHIFTCFG_SSTOP_ZERO (0x02 << FLEXIO_SHIFTCFG_SSTOP_SHIFT) /* Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 */
# define FLEXIO_SHIFTCFG_SSTOP_ONE (0x03 << FLEXIO_SHIFTCFG_SSTOP_SHIFT) /* Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 */
/* Bits 6-7: Reserved */
#define FLEXIO_SHIFTCFG_INSRC (1 << 8) /* Bit 8: Input Source (INSRC) */
# define FLEXIO_SHIFTCFG_INSRC_PIN (0 << 8) /* Pin */
# define FLEXIO_SHIFTCFG_INSRC_SHIFTER (1 << 8) /* Shifter N+1 Output */
#define FLEXIO_SHIFTCFG_LATST (1 << 9) /* Bit 9: Late Store (LATST) */
# define FLEXIO_SHIFTCFG_LATST_PRE (0 << 9) /* Shift register stores the pre-shift register state */
# define FLEXIO_SHIFTCFG_LATST_POST (1 << 9) /* Shift register stores the post-shift register state */
/* Bits 10-11: Reserved */
#define FLEXIO_SHIFTCFG_SSIZE (1 << 12) /* Bit 12: Shifter Size (SSIZE) */
# define FLEXIO_SHIFTCFG_SSIZE_32 (0 << 12) /* Shift register is 32-bit */
# define FLEXIO_SHIFTCFG_SSIZE_24 (1 << 12) /* Shift register is 24-bit */
/* Bits 13-15: Reserved */
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16) /* Bits 16-20: Parallel Width (PWIDTH) */
#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1f << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)
# define FLEXIO_SHIFTCFG_PWIDTH_1 (0x00 << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) /* 1-bit shift */
# define FLEXIO_SHIFTCFG_PWIDTH_2 (0x01 << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) /* 2-bit shift */
# define FLEXIO_SHIFTCFG_PWIDTH_4 (0x02 << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) /* 4-bit shift */
# define FLEXIO_SHIFTCFG_PWIDTH_8 (0x04 << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) /* 8-bit shift */
# define FLEXIO_SHIFTCFG_PWIDTH_16 (0x08 << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) /* 16-bit shift */
# define FLEXIO_SHIFTCFG_PWIDTH_32 (0x10 << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) /* 32-bit shift */
/* Bits 21-31: Reserved */
/* Shifter Buffer n Register (SHIFTBUFn) */
#define FLEXIO_SHIFTBUF_SHIFT (0) /* Bits 0-31: Shift Buffer (SHIFTBUF) */
#define FLEXIO_SHIFTBUF_MASK (0xffffffff << FLEXIO_SHIFTBUF_SHIFT)
/* Shifter Buffer n Bit Swapped Register (SHIFTBUFBISn) */
#define FLEXIO_SHIFTBUFBIS_SHIFT (0) /* Bits 0-31: Shift Buffer (bit swapped) (SHIFTBUFBIS) */
#define FLEXIO_SHIFTBUFBIS_MASK (0xffffffff << FLEXIO_SHIFTBUFBIS_SHIFT)
/* Shifter Buffer n Byte Swapped Register (SHIFTBUFBYSn) */
#define FLEXIO_SHIFTBUFBYS_SHIFT (0) /* Bits 0-31: Shift Buffer (byte swapped) (SHIFTBUFBYS) */
#define FLEXIO_SHIFTBUFBYS_MASK (0xffffffff << FLEXIO_SHIFTBUFBYS_SHIFT)
/* Shifter Buffer n Byte Swapped Register (SHIFTBUFBBSn) */
#define FLEXIO_SHIFTBUFBBS_SHIFT (0) /* Bits 0-31: Shift Buffer (bit and byte swapped) (SHIFTBUFBBS) */
#define FLEXIO_SHIFTBUFBBS_MASK (0xffffffff << FLEXIO_SHIFTBUFBBS_SHIFT)
/* Timer Control n Register (TIMCTLn) */
#define FLEXIO_TIMCTL_TIMOD_SHIFT (0) /* Bits 0-2: Timer Mode (TIMOD) */
#define FLEXIO_TIMCTL_TIMOD_MASK (0x07 << FLEXIO_TIMCTL_TIMOD_SHIFT)
# define FLEXIO_TIMCTL_TIMOD_DIS (0x00 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Timer Disabled */
# define FLEXIO_TIMCTL_TIMOD_8BBAUD (0x01 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Dual 8-bit counters baud mode */
# define FLEXIO_TIMCTL_TIMOD_8BPWMHI (0x02 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Dual 8-bit counters PWM high mode */
# define FLEXIO_TIMCTL_TIMOD_16BCNT (0x03 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Single 16-bit counter mode */
# define FLEXIO_TIMCTL_TIMOD_16BDIS (0x04 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Single 16-bit counter disable mode */
# define FLEXIO_TIMCTL_TIMOD_8BWORD (0x05 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Dual 8-bit counters word mode */
# define FLEXIO_TIMCTL_TIMOD_8BPWMLO (0x06 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Dual 8-bit counters PWM low mode */
# define FLEXIO_TIMCTL_TIMOD_16BINCAP (0x07 << FLEXIO_TIMCTL_TIMOD_SHIFT) /* Single 16-bit input capture mode */
/* Bits 3-4: Reserved */
#define FLEXIO_TIMCTL_ONETIM (1 << 5) /* Bit 5: Timer One Time Operation (ONETIM) */
#define FLEXIO_TIMCTL_PININS (1 << 6) /* Bit 6: Timer Pin Input Select (PININS) */
# define FLEXIO_TIMCTL_PININS_PINSEL (0 << 6) /* Timer pin input and output are selected by PINSEL */
# define FLEXIO_TIMCTL_PININS_PLUS1 (1 << 6) /* Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL */
#define FLEXIO_TIMCTL_PINPOL (1 << 7) /* Bit 7: Timer Pin Polarity (PINPOL) */
# define FLEXIO_TIMCTL_PINPOL_HI (0 << 7) /* Pin is active high */
# define FLEXIO_TIMCTL_PINPOL_LO (1 << 7) /* Pin is active low */
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-12: Timer Pin Select (PINSEL) */
#define FLEXIO_TIMCTL_PINSEL_MASK (0x1f << FLEXIO_TIMCTL_PINSEL_SHIFT)
# define FLEXIO_TIMCTL_PINSEL(n) (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK)
/* Bits 13-15: Reserved */
#define FLEXIO_TIMCTL_PINCFG_SHIFT (16) /* Bits 16-17: Timer Pin Configuration (PINCFG) */
#define FLEXIO_TIMCTL_PINCFG_MASK (0x03 << FLEXIO_TIMCTL_PINCFG_SHIFT)
# define FLEXIO_TIMCTL_PINCFG_DIS (0x00 << FLEXIO_TIMCTL_PINCFG_SHIFT) /* Timer pin output disabled */
# define FLEXIO_TIMCTL_PINCFG_OD (0x01 << FLEXIO_TIMCTL_PINCFG_SHIFT) /* Timer pin open drain or bidirectional output enable */
# define FLEXIO_TIMCTL_PINCFG_BID (0x02 << FLEXIO_TIMCTL_PINCFG_SHIFT) /* Timer pin bidirectional output data */
# define FLEXIO_TIMCTL_PINCFG_OUT (0x03 << FLEXIO_TIMCTL_PINCFG_SHIFT) /* Timer pin output */
/* Bits 18-21: Reserved */
#define FLEXIO_TIMCTL_TRGSRC (1 << 22) /* Bit 22: Trigger Source (TRGSRC) */
# define FLEXIO_TIMCTL_TRGSRC_EXT (0 << 22) /* External trigger selected */
# define FLEXIO_TIMCTL_TRGSRC_INT (1 << 22) /* Internal trigger selected */
#define FLEXIO_TIMCTL_TRGPOL (1 << 23) /* Bit 23: Trigger Polarity (TRGPOL) */
# define FLEXIO_TIMCTL_TRGPOL_HI (0 << 23) /* Trigger active high */
# define FLEXIO_TIMCTL_TRGPOL_LO (1 << 23) /* Trigger active low */
#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24) /* Bits 24-29: Trigger Select (TRGSEL) */
#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3f << FLEXIO_TIMCTL_TRGSEL_SHIFT)
# define FLEXIO_TIMCTL_TRGSEL_EXT(n) (((n) << FLEXIO_TIMCTL_TRGSEL_SHIFT) & FLEXIO_TIMCTL_TRGSEL_MASK) /* External trigger n input */
# define FLEXIO_TIMCTL_TRGSEL_PIN(n) (((2*(n)) << FLEXIO_TIMCTL_TRGSEL_SHIFT) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Pin n input */
# define FLEXIO_TIMCTL_TRGSEL_SHIFTER(n) (((4*(n)+1) << FLEXIO_TIMCTL_TRGSEL_SHIFT) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Shifter n status flag */
# define FLEXIO_TIMCTL_TRGSEL_TIMER(n) (((4*(n)+3) << FLEXIO_TIMCTL_TRGSEL_SHIFT) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Timer n trigger output */
/* Bits 30-31: Reserved */
/* Timer Configuration n Register (TIMCFGn) */
/* Bit 0: Reserved */
#define FLEXIO_TIMCFG_TSTART (1 << 1) /* Bit 1: Timer Start Bit (TSTART) */
# define FLEXIO_TIMCFG_TSTART_DIS (0 << 1) /* Start bit disabled */
# define FLEXIO_TIMCFG_TSTART_ENA (1 << 1) /* Start bit enabled */
/* Bits 2-3: Reserved */
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */
#define FLEXIO_TIMCFG_TSTOP_MASK (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT)
# define FLEXIO_TIMCFG_TSTOP_DIS (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */
# define FLEXIO_TIMCFG_TSTOP_TIMCMP (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */
# define FLEXIO_TIMCFG_TSTOP_TIMDIS (0x02 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer disable */
# define FLEXIO_TIMCFG_TSTOP_BOTH (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */
/* Bits 6-7: Reserved */
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */
#define FLEXIO_TIMCFG_TIMENA_MASK (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT)
# define FLEXIO_TIMCFG_TIMENA_ALWAYS (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */
# define FLEXIO_TIMCFG_TIMENA_TIMENA (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */
# define FLEXIO_TIMCFG_TIMENA_TRGHI (0x02 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Trigger high */
# define FLEXIO_TIMCFG_TIMENA_TRGHIPIN (0x03 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Trigger high and Pin high */
# define FLEXIO_TIMCFG_TIMENA_PINRIS (0x04 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Pin rising edge */
# define FLEXIO_TIMCFG_TIMENA_PINTRG (0x05 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Pin rising edge and Trigger high */
# define FLEXIO_TIMCFG_TIMENA_TRGRIS (0x06 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Trigger rising edge */
# define FLEXIO_TIMCFG_TIMENA_TRGBOTH (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Trigger rising or falling edge */
/* Bit 11: Reserved */
#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12) /* Bits 12-14: Timer Disable (TIMDIS) */
#define FLEXIO_TIMCFG_TIMDIS_MASK (0x07 << FLEXIO_TIMCFG_TIMDIS_SHIFT)
# define FLEXIO_TIMCFG_TIMDIS_NEVER (0x00 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer never disabled */
# define FLEXIO_TIMCFG_TIMDIS_TIMDIS (0x01 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer disabled on Timer N-1 disable */
# define FLEXIO_TIMCFG_TIMDIS_TIMCMP (0x02 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer disabled on Timer compare (upper 8-bits match and decrement) */
# define FLEXIO_TIMCFG_TIMDIS_CMPTRGLO (0x03 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low */
# define FLEXIO_TIMCFG_TIMDIS_PIN (0x04 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer disabled on Pin rising or falling edge */
# define FLEXIO_TIMCFG_TIMDIS_PINTRGHI (0x05 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer disabled on Pin rising or falling edge provided Trigger is high */
# define FLEXIO_TIMCFG_TIMDIS_TRG (0x06 << FLEXIO_TIMCFG_TIMDIS_SHIFT) /* Timer disabled on Trigger falling edge */
/* Bit 15: Reserved */
#define FLEXIO_TIMCFG_TIMRST_SHIFT (16) /* Bits 16-18: Timer Reset (TIMRST) */
#define FLEXIO_TIMCFG_TIMRST_MASK (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT)
# define FLEXIO_TIMCFG_TIMRST_NEVER (0x00 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer never reset */
# define FLEXIO_TIMCFG_TIMRST_OUTHI (0x01 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Timer Output high */
# define FLEXIO_TIMCFG_TIMRST_PINOUT (0x02 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Timer Pin equal to Timer Output */
# define FLEXIO_TIMCFG_TIMRST_TRGOUT (0x03 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Timer Trigger equal to Timer Output */
# define FLEXIO_TIMCFG_TIMRST_PINRIS (0x04 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Timer Pin rising edge */
# define FLEXIO_TIMCFG_TIMRST_TRGRIS (0x06 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising edge */
# define FLEXIO_TIMCFG_TIMRST_TRGBOTH (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */
/* Bit 19: Reserved */
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-22: Timer Decrement (TIMDEC) */
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT)
# define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */
# define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */
# define FLEXIO_TIMCFG_TIMDEC_PINBOTHPIN (0x02 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Pin input (both edges), Shift clock equals Pin input */
# define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTRGIN (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Trigger input */
# define FLEXIO_TIMCFG_TIMDEC_CLKDIV16TIMOUT (0x04 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output */
# define FLEXIO_TIMCFG_TIMDEC_CLKDIV256TIMOUT (0x05 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output */
# define FLEXIO_TIMCFG_TIMDEC_PINRISPIN (0x06 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Pin input (rising edge), Shift clock equals Pin input */
# define FLEXIO_TIMCFG_TIMDEC_TRGINRISTRGIN (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input */
/* Bit 23: Reserved */
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT)
# define FLEXIO_TIMCFG_TIMOUT_ONE (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */
# define FLEXIO_TIMCFG_TIMOUT_ZERO (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */
# define FLEXIO_TIMCFG_TIMOUT_ONERST (0x02 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and on timer reset */
# define FLEXIO_TIMCFG_TIMOUT_ZERORST (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and on timer reset */
/* Bits 26-31: Reserved */
/* Timer Compare n Register (TIMCMPn) */
#define FLEXIO_TIMCMP_CMP_SHIFT (0) /* Bits 0-15: Timer Compare Value (CMP) */
#define FLEXIO_TIMCMP_CMP_MASK (0xffff << FLEXIO_TIMCMP_CMP_SHIFT)
/* Bits 16-31: Reserved */
/* Shifter Buffer n Nibble Byte Swapped Register (SHIFTBUFNBSn) */
#define FLEXIO_SHIFTBUFNBS_SHIFT (0) /* Bits 0-31: Shift Buffer (nibble swapped within each byte) (SHIFTBUFNBS) */
#define FLEXIO_SHIFTBUFNBS_MASK (0xffffffff << FLEXIO_SHIFTBUFNBS_SHIFT)
/* Shifter Buffer n Half Word Swapped Register (SHIFTBUFHWSn) */
#define FLEXIO_SHIFTBUFHWS_SHIFT (0) /* Bits 0-31: Shift Buffer (half word swapped) (SHIFTBUFHWS) */
#define FLEXIO_SHIFTBUFHWS_MASK (0xffffffff << FLEXIO_SHIFTBUFHWS_SHIFT)
/* Shifter Buffer n Nibble Swapped Register (SHIFTBUFNISn) */
#define FLEXIO_SHIFTBUFNIS_SHIFT (0) /* Bits 0-31: Shift Buffer (nibble swapped) (SHIFTBUFNIS) */
#define FLEXIO_SHIFTBUFNIS_MASK (0xffffffff << FLEXIO_SHIFTBUFNIS_SHIFT)
/* Shifter Buffer n Odd Even Swapped Register (SHIFTBUFOESn) */
#define FLEXIO_SHIFTBUFOES_SHIFT (0) /* Bits 0-31: Shift Buffer (odd and even bits partitioned) (SHIFTBUFOES) */
#define FLEXIO_SHIFTBUFOES_MASK (0xffffffff << FLEXIO_SHIFTBUFOES_SHIFT)
/* Shifter Buffer n Even Odd Swapped Register (SHIFTBUFEOSn) */
#define FLEXIO_SHIFTBUFEOS_SHIFT (0) /* Bits 0-31: Shift Buffer (even and odd bits partitioned) (SHIFTBUFEOS) */
#define FLEXIO_SHIFTBUFEOS_MASK (0xffffffff << FLEXIO_SHIFTBUFEOS_SHIFT)
/* Shifter Buffer n Halfword Byte Swapped Register (SHIFTBUFHBSn) */
#define FLEXIO_SHIFTBUFHBS_SHIFT (0) /* Bits 0-31: Shift Buffer (halfword byte swapped) (SHIFTBUFHBS) */
#define FLEXIO_SHIFTBUFHBS_MASK (0xffffffff << FLEXIO_SHIFTBUFHBS_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FLEXIO_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_fmu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FMU_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FMU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* FMU Register Offsets *****************************************************/
#define S32K3XX_FMU_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
#define S32K3XX_FMU_MCRS_OFFSET (0x0004) /* Module Configuration Status Register (MCRS) */
#define S32K3XX_FMU_MCRE_OFFSET (0x0008) /* Extended Module Configuration Register (MCRE) */
#define S32K3XX_FMU_CTL_OFFSET (0x000c) /* Module Control Register (CTL) */
#define S32K3XX_FMU_ADR_OFFSET (0x0010) /* Address Register (ADR) */
#define S32K3XX_FMU_PEADR_OFFSET (0x0014) /* Program and Erase Address Register (PEADR) */
#define S32K3XX_FMU_SPELOCK_OFFSET (0x0050) /* Sector Program and Erase Hardware Lock (SPELOCK) */
#define S32K3XX_FMU_SSPELOCK_OFFSET (0x0054) /* Super Sector Program and Erase Hardware Lock (SSPELOCK) */
#define S32K3XX_FMU_XSPELOCK_OFFSET (0x0070) /* Express Sector Program and Erase Hardware Lock (XSPELOCK) */
#define S32K3XX_FMU_XSSPELOCK_OFFSET (0x0074) /* Express Super Sector Program and Erase Hardware Lock (XSSPELOCK) */
#define S32K3XX_FMU_TMD_OFFSET (0x0090) /* Test Mode Disable Password Check (TMD) */
#define S32K3XX_FMU_UT0_OFFSET (0x0094) /* UTest 0 (UT0) */
#define S32K3XX_FMU_UM0_OFFSET (0x0098) /* UMISR0 (UM0) */
#define S32K3XX_FMU_UM1_OFFSET (0x009c) /* UMISR1 (UM1) */
#define S32K3XX_FMU_UM2_OFFSET (0x00a0) /* UMISR2 (UM2) */
#define S32K3XX_FMU_UM3_OFFSET (0x00a4) /* UMISR3 (UM3) */
#define S32K3XX_FMU_UM4_OFFSET (0x00a8) /* UMISR4 (UM4) */
#define S32K3XX_FMU_UM5_OFFSET (0x00ac) /* UMISR5 (UM5) */
#define S32K3XX_FMU_UM6_OFFSET (0x00b0) /* UMISR6 (UM6) */
#define S32K3XX_FMU_UM7_OFFSET (0x00b4) /* UMISR7 (UM7) */
#define S32K3XX_FMU_UM8_OFFSET (0x00b8) /* UMISR8 (UM8) */
#define S32K3XX_FMU_UM9_OFFSET (0x00bc) /* UMISR9 (UM9) */
#define S32K3XX_FMU_UD0_OFFSET (0x00d0) /* UTest Data 0 (UD0) */
#define S32K3XX_FMU_UD1_OFFSET (0x00d4) /* UTest Data 1 (UD1) */
#define S32K3XX_FMU_UD2_OFFSET (0x00d8) /* UTest Data 2 (UD2) */
#define S32K3XX_FMU_UD3_OFFSET (0x00dc) /* UTest Data 3 (UD3) */
#define S32K3XX_FMU_UD4_OFFSET (0x00e0) /* UTest Data 4 (UD4) */
#define S32K3XX_FMU_UD5_OFFSET (0x00e4) /* UTest Data 5 (UD5) */
#define S32K3XX_FMU_UA0_OFFSET (0x00e8) /* UTest Address 0 (UA0) */
#define S32K3XX_FMU_UA1_OFFSET (0x00ec) /* UTest Address 1 (UA1) */
#define S32K3XX_FMU_XMCR_OFFSET (0x00f0) /* Express Module Configuration Register (XMCR) */
#define S32K3XX_FMU_XPEADR_OFFSET (0x00f4) /* Express Program Address Register (XPEADR) */
#define S32K3XX_FMU_DATA_OFFSET(n) (0x0100 + ((n) << 2)) /* Program Data (DATAn) */
/* FMU Register Addresses ***************************************************/
#define S32K3XX_FMU_MCR (S32K3XX_FMU_BASE + S32K3XX_FMU_MCR_OFFSET)
#define S32K3XX_FMU_MCRS (S32K3XX_FMU_BASE + S32K3XX_FMU_MCRS_OFFSET)
#define S32K3XX_FMU_MCRE (S32K3XX_FMU_BASE + S32K3XX_FMU_MCRE_OFFSET)
#define S32K3XX_FMU_CTL (S32K3XX_FMU_BASE + S32K3XX_FMU_CTL_OFFSET)
#define S32K3XX_FMU_ADR (S32K3XX_FMU_BASE + S32K3XX_FMU_ADR_OFFSET)
#define S32K3XX_FMU_PEADR (S32K3XX_FMU_BASE + S32K3XX_FMU_PEADR_OFFSET)
#define S32K3XX_FMU_SPELOCK (S32K3XX_FMU_BASE + S32K3XX_FMU_SPELOCK_OFFSET)
#define S32K3XX_FMU_SSPELOCK (S32K3XX_FMU_BASE + S32K3XX_FMU_SSPELOCK_OFFSET)
#define S32K3XX_FMU_XSPELOCK (S32K3XX_FMU_BASE + S32K3XX_FMU_XSPELOCK_OFFSET)
#define S32K3XX_FMU_XSSPELOCK (S32K3XX_FMU_BASE + S32K3XX_FMU_XSSPELOCK_OFFSET)
#define S32K3XX_FMU_TMD (S32K3XX_FMU_BASE + S32K3XX_FMU_TMD_OFFSET)
#define S32K3XX_FMU_UT0 (S32K3XX_FMU_BASE + S32K3XX_FMU_UT0_OFFSET)
#define S32K3XX_FMU_UM0 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM0_OFFSET)
#define S32K3XX_FMU_UM1 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM1_OFFSET)
#define S32K3XX_FMU_UM2 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM2_OFFSET)
#define S32K3XX_FMU_UM3 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM3_OFFSET)
#define S32K3XX_FMU_UM4 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM4_OFFSET)
#define S32K3XX_FMU_UM5 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM5_OFFSET)
#define S32K3XX_FMU_UM6 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM6_OFFSET)
#define S32K3XX_FMU_UM7 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM7_OFFSET)
#define S32K3XX_FMU_UM8 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM8_OFFSET)
#define S32K3XX_FMU_UM9 (S32K3XX_FMU_BASE + S32K3XX_FMU_UM9_OFFSET)
#define S32K3XX_FMU_UD0 (S32K3XX_FMU_BASE + S32K3XX_FMU_UD0_OFFSET)
#define S32K3XX_FMU_UD1 (S32K3XX_FMU_BASE + S32K3XX_FMU_UD1_OFFSET)
#define S32K3XX_FMU_UD2 (S32K3XX_FMU_BASE + S32K3XX_FMU_UD2_OFFSET)
#define S32K3XX_FMU_UD3 (S32K3XX_FMU_BASE + S32K3XX_FMU_UD3_OFFSET)
#define S32K3XX_FMU_UD4 (S32K3XX_FMU_BASE + S32K3XX_FMU_UD4_OFFSET)
#define S32K3XX_FMU_UD5 (S32K3XX_FMU_BASE + S32K3XX_FMU_UD5_OFFSET)
#define S32K3XX_FMU_UA0 (S32K3XX_FMU_BASE + S32K3XX_FMU_UA0_OFFSET)
#define S32K3XX_FMU_UA1 (S32K3XX_FMU_BASE + S32K3XX_FMU_UA1_OFFSET)
#define S32K3XX_FMU_XMCR (S32K3XX_FMU_BASE + S32K3XX_FMU_XMCR_OFFSET)
#define S32K3XX_FMU_XPEADR (S32K3XX_FMU_BASE + S32K3XX_FMU_XPEADR_OFFSET)
#define S32K3XX_FMU_DATA(n) (S32K3XX_FMU_BASE + S32K3XX_FMU_DATA_OFFSET(n))
/* FMU Register Bitfield Definitions ****************************************/
/* Module Configuration Register (MCR) */
#define FMU_MCR_EHV (1 << 0) /* Bit 0: Enable High Voltage (EHV) */
# define FMU_MCR_EHV_DIS (0 << 0) /* Flash memory is not enabled to perform a high voltage operation */
# define FMU_MCR_EHV_ENA (1 << 0) /* Flash memory is enabled to perform a high voltage operation */
/* Bits 1-3: Reserved */
#define FMU_MCR_ERS (1 << 4) /* Bit 4: Erase (ERS) */
#define FMU_MCR_ESS (1 << 5) /* Bit 5: Erase Size Select (ESS) */
# define FMU_MCR_ESS_SECTOR (0 << 5) /* Flash memory erase is on a sector */
# define FMU_MCR_ESS_BLOCK (1 << 5) /* Flash memory erase is on a block */
/* Bits 6-7: Reserved */
#define FMU_MCR_PGM (1 << 8) /* Bit 8: Program (PGM) */
# define FMU_MCR_PGM_NOTEXEC (0 << 8) /* Flash memory not executing a program sequence */
# define FMU_MCR_PGM_EXEC (1 << 8) /* Flash memory executing a program sequence */
/* Bits 9-11: Reserved */
#define FMU_MCR_WDIE (1 << 12) /* Bit 12: Watch Dog Interrupt Enable (WDIE) */
/* Bits 13-14: Reserved */
#define FMU_MCR_PECIE (1 << 15) /* Bit 15: Program/Erase Complete Interrupt Enable (PECIE) */
#define FMU_MCR_PEID_SHIFT (16) /* Bits 16-23: Program and Erase Master/Domain ID (PEID) */
#define FMU_MCR_PEID_MASK (0xff << FMU_MCR_PEID_SHIFT)
/* Bits 24-31: Reserved */
/* Module Configuration Status Register (MCRS) */
#define FMU_MCRS_RE (1 << 0) /* Bit 0: Reset Error (RE) */
/* Bits 1-7: Reserved */
#define FMU_MCRS_TSPELOCK (1 << 8) /* Bit 8: UTest NVM Program and Erase Lock (TSPELOCK) */
#define FMU_MCRS_EPEG (1 << 9) /* Bit 9: ECC Enabled Program/Erase Good (EPEG) */
/* Bits 10-11: Reserved */
#define FMU_MCRS_WDI (1 << 12) /* Bit 12: Watch Dog Interrupt (WDI) */
/* Bit 13: Reserved */
#define FMU_MCRS_PEG (1 << 14) /* Bit 14: Program/Erase Good (PEG) */
#define FMU_MCRS_DONE (1 << 15) /* Bit 15: State Machine Status (DONE) */
#define FMU_MCRS_PES (1 << 16) /* Bit 16: Program and Erase Sequence Error (PES) */
#define FMU_MCRS_PEP (1 << 17) /* Bit 17: Program and Erase Protection Error (PEP) */
/* Bits 18-19: Reserved */
#define FMU_MCRS_RWE (1 << 20) /* Bit 20: Read-While-Write Event Error (RWE) */
/* Bits 21-23: Reserved */
#define FMU_MCRS_RRE (1 << 24) /* Bit 24: Read Reference Error (RRE) */
#define FMU_MCRS_RVE (1 << 25) /* Bit 25: Read Voltage Error (RVE) */
/* Bits 26-27: Reserved */
#define FMU_MCRS_EEE (1 << 28) /* Bit 28: EDC after ECC Error (EEE) */
#define FMU_MCRS_AEE (1 << 29) /* Bit 29: Address Encode Error (AEE) */
#define FMU_MCRS_SBC (1 << 30) /* Bit 30: Single Bit Correction (SBC) */
#define FMU_MCRS_EER (1 << 31) /* Bit 31: ECC Event Error (EER) */
/* Extended Module Configuration Register (MCRE) */
/* Bits 0-5: Reserved */
#define FMU_MCRE_N256K_SHIFT (6) /* Bits 6-7: Number of 256 KB Blocks (N256K) */
#define FMU_MCRE_N256K_MASK (0x03 << FMU_MCRE_N256K_SHIFT)
# define FMU_MCRE_N256K_0 (0x00 << FMU_MCRE_N256K_SHIFT) /* Zero 256 KB blocks */
# define FMU_MCRE_N256K_1 (0x01 << FMU_MCRE_N256K_SHIFT) /* One 256 KB block */
# define FMU_MCRE_N256K_2 (0x02 << FMU_MCRE_N256K_SHIFT) /* Two 256 KB blocks */
# define FMU_MCRE_N256K_4 (0x03 << FMU_MCRE_N256K_SHIFT) /* Four 256 KB blocks */
/* Bits 8-13: Reserved */
#define FMU_MCRE_N512K_SHIFT (14) /* Bits 14-15: Number of 512 KB Blocks (N512K) */
#define FMU_MCRE_N512K_MASK (0x03 << FMU_MCRE_N512K_SHIFT)
# define FMU_MCRE_N512K_0 (0x00 << FMU_MCRE_N512K_SHIFT) /* Zero 512 KB blocks */
# define FMU_MCRE_N512K_1 (0x01 << FMU_MCRE_N512K_SHIFT) /* One 512 KB block */
# define FMU_MCRE_N512K_2 (0x02 << FMU_MCRE_N512K_SHIFT) /* Two 512 KB blocks */
# define FMU_MCRE_N512K_4 (0x03 << FMU_MCRE_N512K_SHIFT) /* Four 512 KB blocks */
/* Bits 16-20: Reserved */
#define FMU_MCRE_N1M_SHIFT (14) /* Bits 21-23: Number of 1 MB Blocks (N1M) */
#define FMU_MCRE_N1M_MASK (0x07 << FMU_MCRE_N1M_SHIFT)
# define FMU_MCRE_N1M_0 (0x00 << FMU_MCRE_N1M_SHIFT) /* Zero 1 MB blocks */
# define FMU_MCRE_N1M_1 (0x01 << FMU_MCRE_N1M_SHIFT) /* One 1 MB block */
# define FMU_MCRE_N1M_2 (0x02 << FMU_MCRE_N1M_SHIFT) /* Two 1 MB blocks */
# define FMU_MCRE_N1M_3 (0x03 << FMU_MCRE_N1M_SHIFT) /* Three 1 MB blocks */
# define FMU_MCRE_N1M_4 (0x04 << FMU_MCRE_N1M_SHIFT) /* Four 1 MB blocks */
/* Bits 24-31: Reserved */
/* Module Control Register (CTL) */
/* Bits 0-7: Reserved */
#define FMU_CTL_RWSC_SHIFT (8) /* Bits 8-12: Wait State Control (RWSC) */
#define FMU_CTL_RWSC_MASK (0x1f << FMU_CTL_RWSC_SHIFT)
# define FMU_CTL_RWSC(n) (((n) << FMU_CTL_RWSC_SHIFT) & FMU_CTL_RWSC_MASK)
# define FMU_CTL_RWSC1 (0x01 << FMU_CTL_RWSC_SHIFT) /* One additional wait state is added */
# define FMU_CTL_RWSC2 (0x02 << FMU_CTL_RWSC_SHIFT) /* Two additional wait states are added */
# define FMU_CTL_RWSC3 (0x03 << FMU_CTL_RWSC_SHIFT) /* Three additional wait states are added */
# define FMU_CTL_RWSC4 (0x04 << FMU_CTL_RWSC_SHIFT) /* Four additional wait states are added */
# define FMU_CTL_RWSC5 (0x05 << FMU_CTL_RWSC_SHIFT) /* Five additional wait states are added */
# define FMU_CTL_RWSC6 (0x06 << FMU_CTL_RWSC_SHIFT) /* Six additional wait states are added */
# define FMU_CTL_RWSC7 (0x07 << FMU_CTL_RWSC_SHIFT) /* Seven additional wait states are added */
# define FMU_CTL_RWSC8 (0x08 << FMU_CTL_RWSC_SHIFT) /* Eight additional wait states are added */
/* Bits 13-14: Reserved */
#define FMU_CTL_RWSL (1 << 15) /* Bit 15: Read Wait State Lock (RWSL) */
/* Bits 16-31: Reserved */
/* Address Register (ADR) */
/* Bit 0: Reserved */
#define FMU_ADR_ADDR_SHIFT (1) /* Bits 1-18: Address (ADDR) */
#define FMU_ADR_ADDR_MASK (0x03ffff << FMU_ADR_ADDR_SHIFT)
#define FMU_ADR_A0 (1 << 19) /* Bit 19: Address Region 0 (A0) */
#define FMU_ADR_A1 (1 << 20) /* Bit 20: Address Region 1 (A1) */
#define FMU_ADR_A2 (1 << 21) /* Bit 21: Address Region 2 (A2) */
#define FMU_ADR_A3 (1 << 22) /* Bit 22: Address Region 3 (A3) */
#define FMU_ADR_A4 (1 << 23) /* Bit 23: Address Region 4 (A4) */
#define FMU_ADR_A5 (1 << 24) /* Bit 24: Address Region 5 (A5) */
/* Bits 25-30: Reserved */
#define FMU_ADR_SAD (1 << 31) /* Bit 31: UTest NVM Address (SAD) */
/* Program and Erase Address Register (PEADR) */
/* Bits 0-4: Reserved */
#define FMU_PEADR_PEADDR_SHIFT (5) /* Bits 5-18: Program and Erase Address (PEADDR) */
#define FMU_PEADR_PEADDR_MASK (0x3fff << FMU_PEADR_PEADDR_SHIFT)
#define FMU_PEADR_PEA0 (1 << 19) /* Bit 19: Program and Erase Address Region 0 (PEA0) */
#define FMU_PEADR_PEA1 (1 << 20) /* Bit 20: Program and Erase Address Region 1 (PEA1) */
#define FMU_PEADR_PEA2 (1 << 21) /* Bit 21: Program and Erase Address Region 2 (PEA2) */
#define FMU_PEADR_PEA3 (1 << 22) /* Bit 22: Program and Erase Address Region 3 (PEA3) */
#define FMU_PEADR_PEA4 (1 << 23) /* Bit 23: Program and Erase Address Region 4 (PEA4) */
#define FMU_PEADR_PEA5 (1 << 24) /* Bit 24: Program and Erase Address Region 5 (PEA5) */
/* Bits 25-30: Reserved */
#define FMU_PEADR_PEASAD (1 << 31) /* Bit 31: UTest NVM Program and Erase Address (PEASAD) */
/* Sector Program and Erase Hardware Lock (SPELOCK) */
#define FMU_SPELOCK_SHIFT (0) /* Bits 0-31: Sector Program and Erase Lock (SPELOCK) */
#define FMU_SPELOCK_MASK (0xffffffff << FMU_SPELOCK_SHIFT)
/* Super Sector Program and Erase Hardware Lock (SSPELOCK) */
#define FMU_SSPELOCK_SHIFT (0) /* Bits 0-11: Super Sector Program and Erase Lock (SSPELOCK) */
#define FMU_SSPELOCK_MASK (0x0fff << FMU_SSPELOCK_SHIFT)
/* Bits 12-31: Reserved */
/* Express Sector Program and Erase Hardware Lock (XSPELOCK) */
#define FMU_XSPELOCK_SHIFT (0) /* Bits 0-31: Express Sector Program and Erase Lock (XSPELOCK) */
#define FMU_XSPELOCK_MASK (0xffffffff << FMU_XSPELOCK_SHIFT)
/* Express Super Sector Program and Erase Hardware Lock (XSSPELOCK) */
#define FMU_XSSPELOCK_SHIFT (0) /* Bits 0-11: Super Sector Program and Erase Lock (XSSPELOCK) */
#define FMU_XSSPELOCK_MASK (0x0fff << FMU_XSSPELOCK_SHIFT)
/* Bits 12-31: Reserved */
/* Test Mode Disable Password Check (TMD) */
#define FMU_TMD_PWD_SHIFT (0) /* Bits 0-31: Password Challenge (PWD) */
#define FMU_TMD_PWD_MASK (0xffffffff << FMU_TMD_PWD_SHIFT)
/* UTest 0 (UT0) */
#define FMU_UT0_AID (1 << 0) /* Bit 0: Array Integrity Done (AID) */
#define FMU_UT0_AIE (1 << 1) /* Bit 1: Array Integrity Enable (AIE) */
#define FMU_UT0_AIS (1 << 2) /* Bit 2: Array Integrity Sequence (AIS) */
/* Bit 3: Reserved */
#define FMU_UT0_MRV (1 << 4) /* Bit 4: Margin Read Value (MRV) */
#define FMU_UT0_MRE (1 << 5) /* Bit 5: Margin Read Enable (MRE) */
#define FMU_UT0_AISUS (1 << 6) /* Bit 6: Array Integrity Suspend (AISUS) */
/* Bit 7: Reserved */
#define FMU_UT0_AIBPE (1 << 8) /* Bit 8: Array Integrity Break Point Enable (AIBPE) */
#define FMU_UT0_NAIBP (1 << 9) /* Bit 9: Next Array Integrity Break Point (NAIBP) */
/* Bits 10-11: Reserved */
#define FMU_UT0_EIE (1 << 12) /* Bit 12: ECC Data Input Enable (EIE) */
#define FMU_UT0_EDIE (1 << 13) /* Bit 13: EDC after ECC Data Input Enable (EDIE) */
#define FMU_UT0_AEIE (1 << 14) /* Bit 14: Address Encode Invert Enable (AEIE) */
#define FMU_UT0_RRIE (1 << 15) /* Bit 15: Read Reference Input Enable (RRIE) */
/* Bits 16-29: Reserved */
#define FMU_UT0_SBCE (1 << 30) /* Bit 30: Single Bit Correction Enable (SBCE) */
#define FMU_UT0_UTE (1 << 31) /* Bit 31: UTest Enable (UTE) */
/* UMISRn (UMn) */
#define FMU_UM_MISR_SHIFT (0) /* Bits 0-31: MISR */
#define FMU_UM_MISR_MASK (0xffffffff << FMU_UM_MISR_SHIFT)
/* UMISR9 (UM9) */
#define FMU_UM9_MISR (1 << 0) /* Bit 0: MISR */
/* Bits 1-31: Reserved */
/* UTest Data n (UDn, n=0,1,3,4) */
#define FMU_UD0134_EDATA_SHIFT (0) /* Bits 0-31: ECC Data (EDATA) */
#define FMU_UD0134_EDATA_MASK (0xffffffff << FMU_UD0134_EDATA_SHIFT)
/* UTest Data n (UDn, n=2,5) */
#define FMU_UD25_EDATAC_SHIFT (0) /* Bits 0-7: ECC Data Check Bits (EDATAC) */
#define FMU_UD25_EDATAC_MASK (0xff << FMU_UD25_EDATAC_SHIFT)
/* Bits 8-23: Reserved */
#define FMU_UD25_ED0 (1 << 24) /* Bit 24: ECC Logic Check Double Word 0 (ED0) */
#define FMU_UD25_ED1 (1 << 25) /* Bit 25: ECC Logic Check Double Word 1 (ED1) */
#define FMU_UD25_ED2 (1 << 26) /* Bit 26: ECC Logic Check Double Word 2 (ED2) */
#define FMU_UD25_ED3 (1 << 27) /* Bit 27: ECC Logic Check Double Word 3 (ED3) */
/* Bits 28-31: Reserved */
/* UTest Address 0 (UA0) */
#define FMU_UA0_SHIFT (0) /* Bits 0-31: Address Encode Invert (AEI) */
#define FMU_UA0_MASK (0xffffffff << FMU_UA0_SHIFT)
/* UTest Address 1 (UA1) */
#define FMU_UA1_SHIFT (0) /* Bits 0-19: Address Encode Invert (AEI) */
#define FMU_UA1_MASK (0x0fffff << FMU_UA1_SHIFT)
/* Bits 20-31: Reserved */
/* Express Module Configuration Register (XMCR) */
#define FMU_XMCR_XEHV (1 << 0) /* Bit 0: Express Enable High Voltage (XEHV) */
/* Bits 1-7: Reserved */
#define FMU_XMCR_XPGM (1 << 8) /* Bit 8: Express Program (XPGM) */
#define FMU_XMCR_XEPEG (1 << 9) /* Bit 9: Express ECC Enabled Program Good (XEPEG) */
/* Bit 10: Reserved */
#define FMU_XMCR_XWDIE (1 << 11) /* Bit 11: Express Watch Dog Interrupt Enable (XWDIE) */
#define FMU_XMCR_XWDI (1 << 12) /* Bit 12: Express Watch Dog Interrupt (XWDI) */
#define FMU_XMCR_XDOK (1 << 13) /* Bit 13: Express Data OK (XDOK) */
#define FMU_XMCR_XPEG (1 << 14) /* Bit 14: Express Program Good (XPEG) */
#define FMU_XMCR_XDONE (1 << 15) /* Bit 15: Express State Machine Status (XDONE) */
#define FMU_XMCR_XPEID_SHIFT (16) /* Bits 16-23: Express Program Master/Domain ID */
#define FMU_XMCR_XPEID_MASK (0xff << FMU_XMCR_XPEID_SHIFT)
/* Bits 24-31: Reserved */
/* Express Program Address Register (XPEADR) */
/* Bits 0-4: Reserved */
#define FMU_XPEADR_XPEADDR_SHIFT (5) /* Bits 5-18: Express Program Address (XPEADDR) */
#define FMU_XPEADR_XPEADDR_MASK (0x3fff << FMU_XPEADR_XPEADDR_SHIFT)
#define FMU_XPEADR_XPEA0 (1 << 19) /* Bit 19: Express Program and Erase Address Region 0 (XPEA0) */
#define FMU_XPEADR_XPEA1 (1 << 20) /* Bit 20: Express Program and Erase Address Region 1 (XPEA1) */
#define FMU_XPEADR_XPEA2 (1 << 21) /* Bit 21: Express Program and Erase Address Region 2 (XPEA2) */
#define FMU_XPEADR_XPEA3 (1 << 22) /* Bit 22: Express Program and Erase Address Region 3 (XPEA3) */
#define FMU_XPEADR_XPEA4 (1 << 23) /* Bit 23: Express Program and Erase Address Region 4 (XPEA4) */
#define FMU_XPEADR_XPEA5 (1 << 24) /* Bit 24: Express Program and Erase Address Region 5 (XPEA5) */
/* Bits 25-31: Reserved */
/* Program Data (DATAn) */
#define FMU_DATA_SHIFT (0) /* Bits 0-31: Program Data (PDATA) */
#define FMU_DATA_MASK (0xffffffff << FMU_DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FMU_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MCU TO FS26 **************************************************************/
#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
/* FS26 General device status ***********************************************/
#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
/* FS26 Data encoding********************************************************/
#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
#define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
/* FS26 SPI register map */
#define FS26_M_DEVICE_ID (0x0) /* */
#define FS26_M_PROGID (0x1) /* */
#define FS26_M_STATUS (0x2) /* */
#define FS26_M_TSD_FLG (0x3) /* */
#define FS26_M_TSD_MSK (0x4) /* */
#define FS26_M_REG_FLG (0x5) /* */
#define FS26_M_REG_MSK (0x6) /* */
#define FS26_M_VSUP_FLG (0x7) /* */
#define FS26_M_VSUP_MSK (0x8) /* */
#define FS26_M_WIO_FLG (0x9) /* */
#define FS26_M_WIO_MSK (0xA) /* */
#define FS26_M_COM_FLG (0xB) /* */
#define FS26_M_COM_MSK (0xC) /* */
#define FS26_M_SYS_CFG (0xD) /* */
#define FS26_M_TSD_CFG (0xE) /* */
#define FS26_M_REG_CFG (0xF) /* */
#define FS26_M_WIO_CFG (0x10) /* */
#define FS26_M_REG_CTRL1 (0x11) /* */
#define FS26_M_REG_CTRL2 (0x12) /* */
#define FS26_M_AMUX_CTRL (0x13) /* */
#define FS26_M_LDT_CFG1 (0x14) /* */
#define FS26_M_LDT_CFG2 (0x15) /* */
#define FS26_M_LDT_CFG3 (0x16) /* */
#define FS26_M_LDT_CTRL (0x17) /* */
#define FS26_M_MEMORY0 (0x18) /* */
#define FS26_M_MEMORY1 (0x19) /* */
/* FS26 Fail safe register map */
#define FS26_FS_GRL_FLAGS (0x40) /* */
#define FS26_FS_I_OVUV_SAFE_REACTION1 (0x41) /* */
#define FS26_FS_I_NOT_OVUV_SAFE_REACTION1 (0x42) /* */
#define FS26_FS_I_OVUV_SAFE_REACTION2 (0x43) /* */
#define FS26_FS_I_NOT_OVUV_SAFE_REACTION2 (0x44) /* */
#define FS26_FS_I_WD_CFG (0x45) /* */
#define FS26_FS_I_NOT_WD_CFG (0x46) /* */
#define FS26_FS_I_SAFE_INPUTS (0x47) /* */
#define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */
#define FS26_FS_I_FSSM (0x49) /* */
#define FS26_FS_I_NOT_FSSM (0x4A) /* */
#define FS26_FS_WDW_DURATION (0x4B) /* */
#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */
#define FS26_FS_WD_ANSWER (0x4D) /* */
#define FS26_FS_WD_TOKEN (0x4E) /* */
#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */
#define FS26_FS_OVUV_REG_STATUS (0x50) /* */
#define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */
#define FS26_FS_SAFE_IOS_1 (0x52) /* */
#define FS26_FS_SAFE_IOS_2 (0x53) /* */
#define FS26_FS_DIAG_SAFETY1 (0x54) /* */
#define FS26_FS_DIAG_SAFETY2 (0x55) /* */
#define FS26_FS_INTB_MASK (0x56) /* */
#define FS26_FS_STATES (0x57) /* */
#define FS26_FS_LP_REQ (0x58) /* */
#define FS26_FS_LDT_LPSEL (0x59) /* */
/* FS_I_OVUV_SAFE_REACTION1 register */
#define VMON_PRE_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_PRE */
#define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
# define VMON_PRE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_OV_FS_REACTION_SHIFT)
# define VMON_PRE_OV_FS_REACTION_FS0B (0x1 << VMON_PRE_OV_FS_REACTION_SHIFT)
# define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
#define VMON_PRE_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_PRE */
#define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
# define VMON_PRE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_UV_FS_REACTION_SHIFT)
# define VMON_PRE_UV_FS_REACTION_FS0B (0x1 << VMON_PRE_UV_FS_REACTION_SHIFT)
# define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
#define VMON_CORE_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_CORE */
#define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
# define VMON_CORE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_OV_FS_REACTION_SHIFT)
# define VMON_CORE_OV_FS_REACTION_FS0B (0x1 << VMON_CORE_OV_FS_REACTION_SHIFT)
# define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
#define VMON_CORE_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_CORE */
#define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
# define VMON_CORE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_UV_FS_REACTION_SHIFT)
# define VMON_CORE_UV_FS_REACTION_FS0B (0x1 << VMON_CORE_UV_FS_REACTION_SHIFT)
# define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
#define VMON_LDO1_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO1 */
#define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
# define VMON_LDO1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_OV_FS_REACTION_SHIFT)
# define VMON_LDO1_OV_FS_REACTION_FS0B (0x1 << VMON_LDO1_OV_FS_REACTION_SHIFT)
# define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
#define VMON_LDO1_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO1 */
#define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
# define VMON_LDO1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_UV_FS_REACTION_SHIFT)
# define VMON_LDO1_UV_FS_REACTION_FS0B (0x1 << VMON_LDO1_UV_FS_REACTION_SHIFT)
# define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
#define VMON_LDO2_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO2 */
#define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
# define VMON_LDO2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_OV_FS_REACTION_SHIFT)
# define VMON_LDO2_OV_FS_REACTION_FS0B (0x1 << VMON_LDO2_OV_FS_REACTION_SHIFT)
# define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
#define VMON_LDO2_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO2 */
#define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
# define VMON_LDO2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_UV_FS_REACTION_SHIFT)
# define VMON_LDO2_UV_FS_REACTION_FS0B (0x1 << VMON_LDO2_UV_FS_REACTION_SHIFT)
# define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
/* FS_I_OVUV_SAFE_REACTION2 register */
#define VMON_EXT_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_EXT */
#define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
# define VMON_EXT_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_OV_FS_REACTION_SHIFT)
# define VMON_EXT_OV_FS_REACTION_FS0B (0x1 << VMON_EXT_OV_FS_REACTION_SHIFT)
# define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
#define VMON_EXT_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_EXT */
#define VMON_EXT_UV_FS_REACTION_MASK (0x3 << VMON_EXT_UV_FS_REACTION_SHIFT)
# define VMON_EXT_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_UV_FS_REACTION_SHIFT)
# define VMON_EXT_UV_FS_REACTION_FS0B (0x1 << VMON_EXT_UV_FS_REACTION_SHIFT)
# define VMON_EXT_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_UV_FS_REACTION_SHIFT)
#define VMON_REF_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_REF */
#define VMON_REF_OV_FS_REACTION_MASK (0x3 << VMON_REF_OV_FS_REACTION_SHIFT)
# define VMON_REF_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_OV_FS_REACTION_SHIFT)
# define VMON_REF_OV_FS_REACTION_FS0B (0x1 << VMON_REF_OV_FS_REACTION_SHIFT)
# define VMON_REF_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_OV_FS_REACTION_SHIFT)
#define VMON_REF_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_REF */
#define VMON_REF_UV_FS_REACTION_MASK (0x3 << VMON_REF_UV_FS_REACTION_SHIFT)
# define VMON_REF_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_UV_FS_REACTION_SHIFT)
# define VMON_REF_UV_FS_REACTION_FS0B (0x1 << VMON_REF_UV_FS_REACTION_SHIFT)
# define VMON_REF_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_UV_FS_REACTION_SHIFT)
#define VMON_TRK2_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK2 */
#define VMON_TRK2_OV_FS_REACTION_MASK (0x3 << VMON_TRK2_OV_FS_REACTION_SHIFT)
# define VMON_TRK2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_OV_FS_REACTION_SHIFT)
# define VMON_TRK2_OV_FS_REACTION_FS0B (0x1 << VMON_TRK2_OV_FS_REACTION_SHIFT)
# define VMON_TRK2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_OV_FS_REACTION_SHIFT)
#define VMON_TRK2_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK2 */
#define VMON_TRK2_UV_FS_REACTION_MASK (0x3 << VMON_TRK2_UV_FS_REACTION_SHIFT)
# define VMON_TRK2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_UV_FS_REACTION_SHIFT)
# define VMON_TRK2_UV_FS_REACTION_FS0B (0x1 << VMON_TRK2_UV_FS_REACTION_SHIFT)
# define VMON_TRK2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_UV_FS_REACTION_SHIFT)
#define VMON_TRK1_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK1 */
#define VMON_TRK1_OV_FS_REACTION_MASK (0x3 << VMON_TRK1_OV_FS_REACTION_SHIFT)
# define VMON_TRK1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_OV_FS_REACTION_SHIFT)
# define VMON_TRK1_OV_FS_REACTION_FS0B (0x1 << VMON_TRK1_OV_FS_REACTION_SHIFT)
# define VMON_TRK1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_OV_FS_REACTION_SHIFT)
#define VMON_TRK1_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK1 */
#define VMON_TRK1_UV_FS_REACTION_MASK (0x3 << VMON_TRK1_UV_FS_REACTION_SHIFT)
# define VMON_TRK1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_UV_FS_REACTION_SHIFT)
# define VMON_TRK1_UV_FS_REACTION_FS0B (0x1 << VMON_TRK1_UV_FS_REACTION_SHIFT)
# define VMON_TRK1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_UV_FS_REACTION_SHIFT)
/* FS26_FS_I_WD_CFG register */
#define WD_ERR_LIMIT_SHIFT (14) /* Watchdog error counter limit */
#define WD_ERR_LIMIT_MASK (0x3 << WD_ERR_LIMIT_SHIFT)
# define WD_ERR_LIMIT_8 (0x0 << WD_ERR_LIMIT_SHIFT)
# define WD_ERR_LIMIT_6 (0x1 << WD_ERR_LIMIT_SHIFT)
# define WD_ERR_LIMIT_4 (0x2 << WD_ERR_LIMIT_SHIFT)
# define WD_ERR_LIMIT_2 (0x3 << WD_ERR_LIMIT_SHIFT)
#define WD_RFR_LIMIT_SHIFT (11) /* Watchdog refresh counter limit */
#define WD_RFR_LIMIT_MASK (0x3 << WD_RFR_LIMIT_SHIFT)
# define WD_RFR_LIMIT_6 (0x0 << WD_RFR_LIMIT_SHIFT)
# define WD_RFR_LIMIT_4 (0x1 << WD_RFR_LIMIT_SHIFT)
# define WD_RFR_LIMIT_2 (0x2 << WD_RFR_LIMIT_SHIFT)
# define WD_RFR_LIMIT_1 (0x3 << WD_RFR_LIMIT_SHIFT)
#define WD_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE output in case of BAD Watchdog (data or timing) */
#define WD_FS_REACTION_MASK (0x3 << WD_FS_REACTION_SHIFT)
# define WD_FS_REACTION_NO_ACTION (0x0 << WD_FS_REACTION_SHIFT)
# define WD_FS_REACTION_FS0B (0x1 << WD_FS_REACTION_SHIFT)
# define WD_FS_REACTION_RSTB_FS0B (0x2 << WD_FS_REACTION_SHIFT)
#define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */
#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT))
#define WD_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
#define WD_ERR_CNT_MASK (0xF << WD_ERR_CNT_SHIFT)
#define WD_ERR_CNT(n) ((n & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : ((n & (0x7 << WD_RFR_CNT_SHIFT)))
/* FS26_FS_I_SAFE_INPUTS register */
#define FCCU_CFG_SHIFT (13) /* FCCU Monitoring Configuration */
#define FCCU_CFG_MASK (0x7 << FCCU_CFG_SHIFT)
# define FCCU_CFG_NO_MONITORING (0x0 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU1_FCCU2_PAIR (0x1 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU1_FCCU2_SINGLE (0x2 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU1_ONLY (0x3 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU2_ONLY (0x4 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU1_FCCU2_PWM (0x5 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU1_PWM_FCCU2_SINGLE (0x6 << FCCU_CFG_SHIFT)
# define FCCU_CFG_FCCU2_PWM_FCCU1_SINGLE (0x7 << FCCU_CFG_SHIFT)
#define FCCU12_FLT_POL_SHIFT (12) /* FCCU12 Fault Polarity */
#define FCCU12_FLT_POL_MASK (0x1 << FCCU12_FLT_POL_SHIFT)
#define FCCU12_FLT_POL_FCCU1_0_FCCU2_1_IS_FAULT (0x0 << FCCU12_FLT_POL_SHIFT)
#define FCCU12_FLT_POL_FCCU1_1_FCCU2_0_IS_FAULT (0x1 << FCCU12_FLT_POL_SHIFT)
#define FCCU1_FLT_POL_SHIFT (11) /* FCCU1 Fault Polarity */
#define FCCU1_FLT_POL_MASK (0x1 << FCCU1_FLT_POL_SHIFT)
#define FCCU1_FLT_POL_LOW (0x0 << FCCU1_FLT_POL_SHIFT)
#define FCCU1_FLT_POL_HIGH (0x1 << FCCU1_FLT_POL_SHIFT)
#define FCCU2_FLT_POL_SHIFT (10) /* FCCU2 Fault Polarity */
#define FCCU2_FLT_POL_MASK (0x1 << FCCU2_FLT_POL_SHIFT)
#define FCCU2_FLT_POL_LOW (0x0 << FCCU2_FLT_POL_SHIFT)
#define FCCU2_FLT_POL_HIGH (0x1 << FCCU2_FLT_POL_SHIFT)
#define FCCU12_FS_REACTION_SHIFT (9) /* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU12 */
#define FCCU12_FS_REACTION_MASK (0x1 << FCCU12_FS_REACTION_SHIFT)
#define FCCU12_FS_REACTION FCCU12_FS_REACTION_MASK
#define FCCU1_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU1 */
#define FCCU1_FS_REACTION_MASK (0x1 << FCCU1_FS_REACTION_SHIFT)
#define FCCU1_FS_REACTION FCCU1_FS_REACTION_MASK
#define FCCU2_FS_REACTION_SHIFT (7) /* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU2 */
#define FCCU2_FS_REACTION_MASK (0x1 << FCCU2_FS_REACTION_SHIFT)
#define FCCU2_FS_REACTION FCCU2_FS_REACTION_MASK
#define ERRMON_FLT_POLARITY_SHIFT (5) /* ERRORMON Fault Polarity */
#define ERRMON_FLT_POLARITY_MASK (0x1 << ERRMON_FLT_POLARITY_SHIFT)
#define ERRMON_FLT_POLARITY_LOW (0x0 << ERRMON_FLT_POLARITY_SHIFT)
#define ERRMON_FLT_POLARITY_HIGH (0x1 << ERRMON_FLT_POLARITY_SHIFT)
#define ERRMON_ACK_TIME_SHIFT (3) /* Acknowledge timing following a fault detection on ERRMON */
#define ERRMON_ACK_TIME_MASK (0x3 << ERRMON_ACK_TIME_SHIFT)
# define ERRMON_ACK_TIME_1MS (0x0 << ERRMON_ACK_TIME_SHIFT)
# define ERRMON_ACK_TIME_8MS (0x1 << ERRMON_ACK_TIME_SHIFT)
# define ERRMON_ACK_TIME_16MS (0x2 << ERRMON_ACK_TIME_SHIFT)
# define ERRMON_ACK_TIME_32MS (0x3 << ERRMON_ACK_TIME_SHIFT)
#define ERRMON_FS_REACTION_SHIFT (2) /* Reaction on RSTB or Fail Safe output in case of fault detection on ERRMON */
#define ERRMON_FS_REACTION_MASK (0x1 << FCCU2_FS_REACTION_SHIFT)
#define ERRMON_FS_REACTION FCCU2_FS_REACTION_MASK
#define FCCU12_FILT_SHIFT (0) /* FCCU pin filtering time settings */
#define FCCU12_FILT_MASK (0x3 << FCCU12_FILT_SHIFT)
# define FCCU12_FILT_3US (0x0 << FCCU12_FILT_SHIFT)
# define FCCU12_FILT_6US (0x1 << FCCU12_FILT_SHIFT)
# define FCCU12_FILT_10US (0x2 << FCCU12_FILT_SHIFT)
# define FCCU12_FILT_20US (0x3 << FCCU12_FILT_SHIFT)
/* FS26_FS_I_FSSM register */
#define FLT_ERR_CNT_LIMIT_SHIFT (14) /* Configure the maximum level of the fault counter */
#define FLT_ERR_CNT_LIMIT_MASK (0x3 << FLT_ERR_CNT_LIMIT_SHIFT)
# define FLT_ERR_CNT_LIMIT_2 (0x0 << FLT_ERR_CNT_LIMIT_SHIFT)
# define FLT_ERR_CNT_LIMIT_6 (0x1 << FLT_ERR_CNT_LIMIT_SHIFT)
# define FLT_ERR_CNT_LIMIT_8 (0x2 << FLT_ERR_CNT_LIMIT_SHIFT)
# define FLT_ERR_CNT_LIMIT_12 (0x3 << FLT_ERR_CNT_LIMIT_SHIFT)
#define FLT_ERR_REACTION_SHIFT (8) /* Configure the RSTB and FS0B behavior when fault error counter ≥ intermediate value */
#define FLT_ERR_REACTION_MASK (0x3 << FLT_ERR_REACTION_SHIFT)
# define FLT_ERR_REACTION_NO_EFFECT (0x0 << FLT_ERR_REACTION_SHIFT)
# define FLT_ERR_REACTION_FS0B (0x1 << FLT_ERR_REACTION_SHIFT)
# define FLT_ERR_REACTION_RSTB_FS0B (0x2 << FLT_ERR_REACTION_SHIFT)
#define RSTB_DUR_SHIFT (9) /* Reset duration configuration */
#define RSTB_DUR_MASK (0x1 << RSTB_DUR_SHIFT)
#define RSTB_DUR_1MS RSTB_DUR_MASK
#define RSTB_DUR_10MS (0)
#define BACKUP_SAFETY_PATH_FS0B_SHIFT (7) /* Assert RSTB in case a short to high is detected on FS0B */
#define BACKUP_SAFETY_PATH_FS0B_MASK (0x1 << BACKUP_SAFETY_PATH_FS0B_SHIFT)
#define BACKUP_SAFETY_PATH_FS0B BACKUP_SAFETY_PATH_FS0B_MASK
#define BACKUP_SAFETY_PATH_FS1B_SHIFT (6) /* Assert RSTB in case a short to high is detected on FS1B */
#define BACKUP_SAFETY_PATH_FS1B_MASK (0x1 << BACKUP_SAFETY_PATH_FS1B_SHIFT)
#define BACKUP_SAFETY_PATH_FS1B BACKUP_SAFETY_PATH_FS1B_MASK
#define CLK_MON_DIS_SHIFT (5) /* Disable CLK Monitoring */
#define CLK_MON_DIS_MASK (0x1 << CLK_MON_DIS_SHIFT)
#define CLK_MON_DIS CLK_MON_DIS_MASK
#define DIS8S_SHIFT (4) /* Disable 8s RSTB timer */
#define DIS8S_MASK (0x1 << DIS8S_SHIFT)
#define DIS8S DIS8S_MASK
#define FLT_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
#define FLT_ERR_CNT_MASK (0xF << FLT_ERR_CNT_SHIFT)
#define FLT_ERR_CNT(n) ((n & (0x7 << FLT_ERR_CNT_SHIFT)) > 12) ? (12) : ((n & (0x7 << FLT_ERR_CNT_SHIFT)))
/* FS26_FS_WDW_DURATION register */
#define WDW_PERIOD_SHIFT (12) /* Watchdog window period */
#define WDW_PERIOD_MASK (0xF << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_DISABLE (0x0 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_1MS (0x1 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_2MS (0x2 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_3MS (0x3 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_4MS (0x4 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_6MS (0x5 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_8MS (0x6 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_12MS (0x7 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_16MS (0x8 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_24MS (0x9 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_32MS (0xA << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_64MS (0xB << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_128MS (0xC << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_256MS (0xD << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_512MS (0xE << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_1024MS (0xF << WDW_PERIOD_SHIFT)
#define WDW_DC_SHIFT (6) /* Watchdog window duty cycle */
#define WDW_DC_MASK (0x7 << WDW_DC_SHIFT)
# define WDW_DC_31_68 (0x0 << WDW_PERIOD_SHIFT)
# define WDW_DC_37_62 (0x1 << WDW_PERIOD_SHIFT)
# define WDW_DC_50_50 (0x2 << WDW_PERIOD_SHIFT)
# define WDW_DC_62_37 (0x3 << WDW_PERIOD_SHIFT)
# define WDW_DC_68_31 (0x4 << WDW_PERIOD_SHIFT)
#define WDW_RECOVERY_SHIFT (0) /* Watchdog window period */
#define WDW_RECOVERY_MASK (0xF << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_DISABLE (0x0 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_1MS (0x1 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_2MS (0x2 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_3MS (0x3 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_4MS (0x4 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_6MS (0x5 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_8MS (0x6 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_12MS (0x7 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_16MS (0x8 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_24MS (0x9 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_32MS (0xA << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_64MS (0xB << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_128MS (0xC << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_256MS (0xD << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_512MS (0xE << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_1024MS (0xF << WDW_RECOVERY_SHIFT)
/* FS26_FS_DIAG_SAFETY1 register */
#define BAD_WD_DATA_SHIFT (10) /* Bad WD refresh, Error in the data */
#define BAD_WD_DATA_MASK (0x1 << BAD_WD_DATA_SHIFT)
#define BAD_WD_DATA BAD_WD_DATA_MASK
#define BAD_WD_TIMING_SHIFT (9) /* Bad WD refresh, Error in the timing */
#define BAD_WD_TIMING_MASK (0x1 << BAD_WD_TIMING_SHIFT)
#define BAD_WD_TIMING BAD_WD_TIMING_MASK
#define ABIST1_PASS_SHIFT (8) /* ABIST 1 pass */
#define ABIST1_PASS_MASK (0x1 << ABIST1_PASS_SHIFT)
#define ABIST1_PASS ABIST1_PASS_MASK
#define ABIST2_PASS_SHIFT (7) /* ABIST 2 pass */
#define ABIST2_PASS_MASK (0x1 << ABIST2_PASS_SHIFT)
#define ABIST2_PASS ABIST2_PASS_MASK
#define ABIST2_DONE_SHIFT (6) /* ABIST 2 done */
#define ABIST2_DONE_MASK (0x1 << ABIST2_DONE_SHIFT)
#define ABIST2_DONE ABIST2_DONE_MASK
#define SPI_FS_CLK_SHIFT (5) /* SPI CLK error */
#define SPI_FS_CLK_MASK (0x1 << SPI_FS_CLK_SHIFT)
#define SPI_FS_CLK SPI_FS_CLK_MASK
#define SPI_FS_REQ_SHIFT (4) /* SPI invalid read/write error */
#define SPI_FS_REQ_MASK (0x1 << SPI_FS_REQ_SHIFT)
#define SPI_FS_REQ SPI_FS_REQ_MASK
#define SPI_FS_CRC_SHIFT (3) /* SPI CRC error */
#define SPI_FS_CRC_MASK (0x1 << SPI_FS_CRC_SHIFT)
#define SPI_FS_CRC SPI_FS_CRC_MASK
#define FS_OSC_DRIFT_SHIFT (2) /* FS OSC drift */
#define FS_OSC_DRIFT_MASK (0x1 << FS_OSC_DRIFT_SHIFT)
#define FS_OSC_DRIFT FS_OSC_DRIFT_MASK
#define LBIST_STATUS_SHIFT (0) /* LBIST STATUS */
#define LBIST_STATUS_MASK (0x3 << LBIST_STATUS_SHIFT)
#define LBIST_STATUS LBIST_STATUS_MASK
# define LBIST_STATUS_FAIL (0x0 << LBIST_STATUS_SHIFT)
# define LBIST_STATUS_BYPASSED (0x1 << LBIST_STATUS_SHIFT)
# define LBIST_STATUS_FAIL2 (0x2 << LBIST_STATUS_SHIFT)
# define LBIST_STATUS_OK (0x3 << LBIST_STATUS_SHIFT)
/* FS26_FS_STATES register */
#define EXIT_DBG_MODE_SHIFT (14) /* Leave debug mode */
#define EXIT_DBG_MODE_MASK (0x1 << EXIT_DBG_MODE_SHIFT)
#define EXIT_DBG_MODE EXIT_DBG_MODE_MASK
#define DBG_MODE_SHIFT (13) /* debug mode */
#define DBG_MODE_MASK (0x1 << DBG_MODE_SHIFT)
#define DBG_MODE DBG_MODE_MASK
#define OTP_CORRUPT_SHIFT (12) /* OTP crc error */
#define OTP_CORRUPT_MASK (0x1 << OTP_CORRUPT_SHIFT)
#define OTP_CORRUPT OTP_CORRUPT_MASK
#define REG_CORRUPT_SHIFT (11) /* INIT register error */
#define REG_CORRUPT_MASK (0x1 << REG_CORRUPT_SHIFT)
#define REG_CORRUPT REG_CORRUPT_MASK
#define FS_STATES_SHIFT (0) /* LBIST STATUS */
#define FS_STATES_MASK (0x1F << FS_STATES_SHIFT)
#define FS_STATES FS_STATES_MASK
# define FS_STATES_DEBUG_ENTRY (0x4 << FS_STATES_SHIFT)
# define FS_STATES_ENABLE_MON (0x6 << FS_STATES_SHIFT)
# define FS_STATES_RSTB_RELEASE (0x8 << FS_STATES_SHIFT)
# define FS_STATES_INIT_FS (0x9 << FS_STATES_SHIFT)
# define FS_STATES_SAFETY_OUT_NOT (0xA << FS_STATES_SHIFT)
# define FS_STATES_NORMAL (0xB << FS_STATES_SHIFT)
/* FS26_FS_GRL_FLAGS register */
#define FS_COM_G_SHIFT (15) /* Report an issue in the communication (SPI) */
#define FS_COM_G_MASK (0x1 << FS_COM_G_SHIFT)
#define FS_COM_G FS_COM_G_MASK
#define FS_WD_G_SHIFT (14) /* Report an issue on the Watchdog Refresh */
#define FS_WD_G_MASK (0x1 << FS_WD_G_SHIFT)
#define FS_WD_G FS_WD_G_MASK
#define FS_IO_G_SHIFT (13) /* Report an issue in one of the Fail Safe IOs */
#define FS_IO_G_MASK (0x1 << FS_IO_G_SHIFT)
#define FS_IO_G FS_IO_G_MASK
#define FS_REG_OVUV_G_SHIFT (12) /* Report an issue in one of the voltage monitoring (OV or UV) */
#define FS_REG_OVUV_G_MASK (0x1 << FS_REG_OVUV_G_SHIFT)
#define FS_REG_OVUV_G FS_REG_OVUV_G_MASK
#define FS_BIST_G_SHIFT (11) /* Report an issue on BIST (Logical or Analog) */
#define FS_BIST_G_MASK (0x1 << FS_BIST_G_SHIFT)
#define FS_BIST_G FS_BIST_G_MASK
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FXOSC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FXOSC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* FXOSC Register Offsets ***************************************************/
#define S32K3XX_FXOSC_CTRL_OFFSET (0x00) /* FXOSC Control Register (CTRL) */
#define S32K3XX_FXOSC_STAT_OFFSET (0x04) /* Oscillator Status Register (STAT) */
/* FXOSC Register Addresses *************************************************/
#define S32K3XX_FXOSC_CTRL (S32K3XX_FXOSC_BASE + S32K3XX_FXOSC_CTRL_OFFSET)
#define S32K3XX_FXOSC_STAT (S32K3XX_FXOSC_BASE + S32K3XX_FXOSC_STAT_OFFSET)
/* FXOSC Register Bitfield Definitions **************************************/
/* FXOSC Control Register (CTRL) */
#define FXOSC_CTRL_OSCON (1 << 0) /* Bit 0: Enables FXOSC (OSCON) */
# define FXOSC_CTRL_OSCOFF (0 << 0) /* Disables FXOSC */
/* Bits 1-3: Reserved */
#define FXOSC_CTRL_GM_SEL_SHIFT (4) /* Bits 4-7: Crystal overdrive protection, transconductance selection (GM_SEL) */
#define FXOSC_CTRL_GM_SEL_MASK (0x0f << FXOSC_CTRL_GM_SEL_SHIFT)
# define FXOSC_CTRL_GM_SEL_0X (0x00 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0x */
# define FXOSC_CTRL_GM_SEL_0_1004X (0x01 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.1004x */
# define FXOSC_CTRL_GM_SEL_0_2009X (0x02 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.2009x */
# define FXOSC_CTRL_GM_SEL_0_3013X (0x03 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.3013x */
# define FXOSC_CTRL_GM_SEL_0_2343X (0x04 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.2343x */
# define FXOSC_CTRL_GM_SEL_0_3348X (0x05 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.3348x */
# define FXOSC_CTRL_GM_SEL_0_4345X (0x06 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.4345x */
# define FXOSC_CTRL_GM_SEL_0_5349X (0x07 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.5349x */
# define FXOSC_CTRL_GM_SEL_0_4679X (0x08 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.4679x */
# define FXOSC_CTRL_GM_SEL_0_5684X (0x09 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.5684x */
# define FXOSC_CTRL_GM_SEL_0_6681X (0x0a << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.6681x */
# define FXOSC_CTRL_GM_SEL_0_7678X (0x0b << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.7678x */
# define FXOSC_CTRL_GM_SEL_0_7016X (0x0c << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.7016x */
# define FXOSC_CTRL_GM_SEL_0_8013X (0x0d << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.8013x */
# define FXOSC_CTRL_GM_SEL_0_9003X (0x0e << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.9003x */
# define FXOSC_CTRL_GM_SEL_1X (0x0f << FXOSC_CTRL_GM_SEL_SHIFT) /* 1x */
/* Bits 8-15: Reserved */
#define FXOSC_CTRL_EOCV_SHIFT (16) /* Bits 16-23: End of count value (EOCV) */
#define FXOSC_CTRL_EOCV_MASK (0xff << FXOSC_CTRL_EOCV_SHIFT)
#define FXOSC_CTRL_EOCV(n) ((n << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
#define FXOSC_CTRL_COMP_EN (1 << 24) /* Bit 24: Comparator enable (COMP_EN) */
# define FXOSC_CTRL_COMP_DIS (0 << 24) /* Comparator disable */
/* Bits 25-30: Reserved */
#define FXOSC_CTRL_OSC_BYP (1 << 31) /* Bit 31: Oscillator bypass (OSC_BYP) */
/* Oscillator Status Register (STAT) */
/* Bits 0-30: Reserved */
#define FXOSC_STAT_OSC_STAT (1 << 31) /* Bit 31: Crystal oscilator status (OSC_STAT) */
# define FXOSC_STAT_OSC_STAT_OFF (0 << 31) /* Crystal oscillator is off or not stable */
# define FXOSC_STAT_OSC_STAT_ON (1 << 31) /* Crystal oscillator is on and providing a stable clock */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FXOSC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_hse.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_HSE_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_HSE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* HSE Register Offsets *****************************************************/
#define S32K3XX_HSE_CONFIG_REG0_OFFSET (0x1c) /* General Purpose Configuration 0 (CONFIG_REG0) */
#define S32K3XX_HSE_CONFIG_REG6_OFFSET (0x34) /* General Purpose Configuration 6 (CONFIG_REG6) */
#define S32K3XX_HSE_CONFIG_RAMPR_OFFSET (0x38) /* Configuration RAM Protected Region (CONFIG_RAMPR) */
#define S32K3XX_HSE_CONFIG_CFPRL_OFFSET (0x3c) /* Configuration Code Flash Memory Active Block (CONFIG_CFPRL) */
#define S32K3XX_HSE_CONFIG_CFPRH_OFFSET (0x40) /* Configuration Code Flash Memory Passive Block (CONFIG_CFPRH) */
#define S32K3XX_HSE_CONFIG_DFPR_OFFSET (0x44) /* Configuration Data Flash Memory Protected Region (CONFIG_DFPR) */
#define S32K3XX_HSE_CONFIG_PE_LOCK_OFFSET (0x50) /* Configuration Program and Erase Lock (CONFIG_PE_LOCK) */
#define S32K3XX_HSE_CONFIG_RAMPR_ALT_OFFSET (0x54) /* Configuration RAM Protected Region Alternate (CONFIG_RAMPR_ALT) */
#define S32K3XX_HSE_CONFIG_CFPRL_ALT_OFFSET (0x58) /* Configuration Code Flash Memory Active Block Alternative (CONFIG_CFPRL_ALT) */
#define S32K3XX_HSE_CONFIG_CFPRH_ALT_OFFSET (0x5c) /* Configuration Code Flash Memory Passive Block Alternative (CONFIG_CFPRH_ALT) */
#define S32K3XX_HSE_CONFIG_DFPR_ALT_OFFSET (0x60) /* Configuration Data Flash Memory Protected Region Alternative (CONFIG_DFPR_ALT) */
#define S32K3XX_HSE_CONFIG_REG_GPR_OFFSET (0x64) /* Configuration REG_GPR (CONFIG_REG_GPR) */
/* HSE Register Addresses ***************************************************/
#define S32K3XX_HSE_CONFIG_REG0 (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_REG0_OFFSET)
#define S32K3XX_HSE_CONFIG_REG6 (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_REG6_OFFSET)
#define S32K3XX_HSE_CONFIG_RAMPR (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_RAMPR_OFFSET)
#define S32K3XX_HSE_CONFIG_CFPRL (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_CFPRL_OFFSET)
#define S32K3XX_HSE_CONFIG_CFPRH (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_CFPRH_OFFSET)
#define S32K3XX_HSE_CONFIG_DFPR (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_DFPR_OFFSET)
#define S32K3XX_HSE_CONFIG_PE_LOCK (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_PE_LOCK_OFFSET)
#define S32K3XX_HSE_CONFIG_RAMPR_ALT (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_RAMPR_ALT_OFFSET)
#define S32K3XX_HSE_CONFIG_CFPRL_ALT (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_CFPRL_ALT_OFFSET)
#define S32K3XX_HSE_CONFIG_CFPRH_ALT (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_CFPRH_ALT_OFFSET)
#define S32K3XX_HSE_CONFIG_DFPR_ALT (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_DFPR_ALT_OFFSET)
#define S32K3XX_HSE_CONFIG_REG_GPR (S32K3XX_HSE_BASE + S32K3XX_HSE_CONFIG_REG_GPR_OFFSET)
/* HSE Register Bitfield Definitions ****************************************/
/* General Purpose Configuration 0 (CONFIG_REG0) */
/* Bits 0-5: Reserved */
#define HSE_CONFIG_REG0_EDB (1 << 6) /* Bit 6: Hardware Debugger Attached (EDB) */
/* Bits 7-31: Reserved */
/* General Purpose Configuration 6 (CONFIG_REG6) */
#define HSE_CONFIG_REG6_QUADSPI_SDID_PCTL (1 << 0) /* Bit 0: QuadSPI Clock Gating (QUADSPI_SDID_PCTL) */
/* Bit 1: Reserved */
#define HSE_CONFIG_REG6_EMAC_CLOCK_GATE (1 << 2) /* Bit 2: Ethernet Clock Gating (EMAC_CLOCK_GATE) */
/* Bit 3: Reserved */
#define HSE_CONFIG_REG6_FLEXIO_CLOCK_GATE (1 << 4) /* Bit 4: FlexIO Clock Gating (FLEXIO_CLOCK_GATE) */
#define HSE_CONFIG_REG6_SAI_SDID_PCTL (1 << 5) /* Bit 5: SAI0 and SAI1 Clock Gating (SAI_SDID_PCTL) */
/* Bits 6-30: Reserved */
#define HSE_CONFIG_REG6_HL (1 << 31) /* Bit 31: Hard Lock (HL) */
/* Configuration RAM Protected Region (CONFIG_RAMPR) */
/* Bits 0-4: Reserved */
#define HSE_CONFIG_RAMPR_SECURE_SIZE_SHIFT (5) /* Bits 5-20: Secure Size (SECURE_SIZE) */
#define HSE_CONFIG_RAMPR_SECURE_SIZE_MASK (0xffff << HSE_CONFIG_RAMPR_SECURE_SIZE_SHIFT)
/* Bits 21-29: Reserved */
#define HSE_CONFIG_RAMPR_SOFT_LOCK (1 << 30) /* Bit 30: Soft Lock (SOFT_LOCK) */
#define HSE_CONFIG_RAMPR_HARD_LOCK (1 << 31) /* Bit 31: Hard Lock (HARD_LOCK) */
/* Configuration Code Flash Memory Active Block (CONFIG_CFPRL) */
/* Bits 0-12: Reserved */
#define HSE_CONFIG_CFPRL_SECURE_SIZE_SHIFT (13) /* Bits 13-20: Secure Size (SECURE_SIZE) */
#define HSE_CONFIG_CFPRL_SECURE_SIZE_MASK (0xff << HSE_CONFIG_CFPRL_SECURE_SIZE_SHIFT)
/* Bits 21-29: Reserved */
#define HSE_CONFIG_CFPRL_SOFT_LOCK (1 << 30) /* Bit 30: Soft Lock (SOFT_LOCK) */
#define HSE_CONFIG_CFPRL_HARD_LOCK (1 << 31) /* Bit 31: Hard Lock (HARD_LOCK) */
/* Configuration Code Flash Memory Passive Block (CONFIG_CFPRH) */
/* Bits 0-12: Reserved */
#define HSE_CONFIG_CFPRH_SECURE_SIZE_SHIFT (13) /* Bits 13-20: Secure Size (SECURE_SIZE) */
#define HSE_CONFIG_CFPRH_SECURE_SIZE_MASK (0xff << HSE_CONFIG_CFPRH_SECURE_SIZE_SHIFT)
/* Bits 21-29: Reserved */
#define HSE_CONFIG_CFPRH_SOFT_LOCK (1 << 30) /* Bit 30: Soft Lock (SOFT_LOCK) */
#define HSE_CONFIG_CFPRH_HARD_LOCK (1 << 31) /* Bit 31: Hard Lock (HARD_LOCK) */
/* Configuration Data Flash Memory Protected Region (CONFIG_DFPR) */
/* Bits 0-12: Reserved */
#define HSE_CONFIG_DFPR_SECURE_SIZE_SHIFT (13) /* Bits 13-20: Secure Size (SECURE_SIZE) */
#define HSE_CONFIG_DFPR_SECURE_SIZE_MASK (0xff << HSE_CONFIG_DFPR_SECURE_SIZE_SHIFT)
/* Bits 21-29: Reserved */
#define HSE_CONFIG_DFPR_SOFT_LOCK (1 << 30) /* Bit 30: Soft Lock (SOFT_LOCK) */
#define HSE_CONFIG_DFPR_HARD_LOCK (1 << 31) /* Bit 31: Hard Lock (HARD_LOCK) */
/* Configuration Program and Erase Lock (CONFIG_PE_LOCK) */
/* Bits 0-11: Reserved */
#define HSE_CONFIG_PE_LOCK_BLOCK_0 (1 << 12) /* Bit 12: Program/Erase Lock for Block 0 (PE_LOCK_BLOCK_0) */
#define HSE_CONFIG_PE_LOCK_BLOCK_1 (1 << 13) /* Bit 13: Program/Erase Lock for Block 1 (PE_LOCK_BLOCK_1) */
#define HSE_CONFIG_PE_LOCK_BLOCK_2 (1 << 14) /* Bit 14: Program/Erase Lock for Block 2 (PE_LOCK_BLOCK_2) */
#define HSE_CONFIG_PE_LOCK_BLOCK_3 (1 << 15) /* Bit 15: Program/Erase Lock for Block 3 (PE_LOCK_BLOCK_3) */
#define HSE_CONFIG_PE_LOCK_BLOCK_4 (1 << 16) /* Bit 16: Program/Erase Lock for Block 4 (PE_LOCK_BLOCK_4) */
/* Bit 17: Reserved */
#define HSE_CONFIG_PE_LOCK_UTEST (1 << 18) /* Bit 18: Program/Erase Lock for UTEST (PE_LOCK_UTEST) */
/* Bits 19-31: Reserved */
/* Configuration RAM Protected Region Alternate (CONFIG_RAMPR_ALT) */
#define HSE_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_SHIFT (0) /* Bits 0-31: Invert Value RAMPR (INVERT_VALUE_RAMPR) */
#define HSE_CONFIG_RAMPR_ALT_INVERT_VALUE_RAMPR_MASK (0xffffffff)
/* Configuration Code Flash Memory Active Block Alternative
* (CONFIG_CFPRL_ALT)
*/
#define HSE_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRL_SHIFT (0) /* Bits 0-31: Invert Value CFPRL (INVERT_VALUE_CFPRL) */
#define HSE_CONFIG_CFPRL_ALT_INVERT_VALUE_CFPRL_MASK (0xffffffff)
/* Configuration Code Flash Memory Passive Block Alternative
* (CONFIG_CFPRH_ALT)
*/
#define HSE_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRH_SHIFT (0) /* Bits 0-31: Invert Value CFPRH (INVERT_VALUE_CFPRH) */
#define HSE_CONFIG_CFPRH_ALT_INVERT_VALUE_CFPRH_MASK (0xffffffff)
/* Configuration Data Flash Memory Protected Region Alternative
* (CONFIG_DFPR_ALT)
*/
#define HSE_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_SHIFT (0) /* Bits 0-31: Invert Value DFPR (INVERT_VALUE_DFPR) */
#define HSE_CONFIG_DFPR_ALT_INVERT_VALUE_DFPR_MASK (0xffffffff)
/* Configuration REG_GPR (CONFIG_REG_GPR) */
#define HSE_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT (0) /* Bits 0-1: FIRC Divider (FIRC_DIV_SEL) */
#define HSE_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK (0x03 << HSE_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT)
# define HSE_CONFIG_REG_GPR_FIRC_DIV_SEL2 (0x00 << HSE_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT) /* Didivded by 2 */
# define HSE_CONFIG_REG_GPR_FIRC_DIV_SEL16 (0x02 << HSE_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT) /* Didivded by 16 */
/* Bits 2-28: Reserved */
#define HSE_CONFIG_REG_GPR_APP_CORE_ACC_SHIFT (29) /* Bits 29-31: APP_CORE_ACC */
#define HSE_CONFIG_REG_GPR_APP_CORE_ACC_MASK (0x07 << HSE_CONFIG_REG_GPR_APP_CORE_ACC_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_HSE_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_intm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_INTM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_INTM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* INTM Register Offsets ****************************************************/
#define S32K3XX_INTM_MM_OFFSET (0x00) /* Monitor Mode Register (INTM_MM) */
#define S32K3XX_INTM_IACK_OFFSET (0x04) /* Interrupt Acknowledge Register (ITNM_IACK) */
#define S32K3XX_INTM_IRQSEL0_OFFSET (0x08) /* Interrupt Request Select 0 Register (INTM_IRQSEL0) */
#define S32K3XX_INTM_LATENCY0_OFFSET (0x0c) /* INTM_LATENCY0 Register */
#define S32K3XX_INTM_TIMER0_OFFSET (0x10) /* Timer 0 Register (INTM_TIMER0) */
#define S32K3XX_INTM_STATUS0_OFFSET (0x14) /* Status 0 Register (INTM_STATUS0) */
#define S32K3XX_INTM_IRQSEL1_OFFSET (0x18) /* Interrupt Request Select 1 Register (INTM_IRQSEL1) */
#define S32K3XX_INTM_LATENCY1_OFFSET (0x1c) /* INTM_LATENCY1 Register */
#define S32K3XX_INTM_TIMER1_OFFSET (0x20) /* Timer 1 Register (INTM_TIMER1) */
#define S32K3XX_INTM_STATUS1_OFFSET (0x24) /* Status 1 Register (INTM_STATUS1) */
#define S32K3XX_INTM_IRQSEL2_OFFSET (0x28) /* Interrupt Request Select 2 Register (INTM_IRQSEL2) */
#define S32K3XX_INTM_LATENCY2_OFFSET (0x2c) /* INTM_LATENCY2 Register */
#define S32K3XX_INTM_TIMER2_OFFSET (0x30) /* Timer 2 Register (INTM_TIMER2) */
#define S32K3XX_INTM_STATUS2_OFFSET (0x34) /* Status 2 Register (INTM_STATUS2) */
#define S32K3XX_INTM_IRQSEL3_OFFSET (0x38) /* Interrupt Request Select 3 Register (INTM_IRQSEL3) */
#define S32K3XX_INTM_LATENCY3_OFFSET (0x3c) /* INTM_LATENCY3 Register */
#define S32K3XX_INTM_TIMER3_OFFSET (0x40) /* Timer 3 Register (INTM_TIMER3) */
#define S32K3XX_INTM_STATUS3_OFFSET (0x44) /* Status 3 Register (INTM_STATUS3) */
/* INTM Register Addresses **************************************************/
#define S32K3XX_INTM_MM (S32K3XX_INTM_BASE + S32K3XX_INTM_MM_OFFSET)
#define S32K3XX_INTM_IACK (S32K3XX_INTM_BASE + S32K3XX_INTM_IACK_OFFSET)
#define S32K3XX_INTM_IRQSEL0 (S32K3XX_INTM_BASE + S32K3XX_INTM_IRQSEL0_OFFSET)
#define S32K3XX_INTM_LATENCY0 (S32K3XX_INTM_BASE + S32K3XX_INTM_LATENCY0_OFFSET)
#define S32K3XX_INTM_TIMER0 (S32K3XX_INTM_BASE + S32K3XX_INTM_TIMER0_OFFSET)
#define S32K3XX_INTM_STATUS0 (S32K3XX_INTM_BASE + S32K3XX_INTM_STATUS0_OFFSET)
#define S32K3XX_INTM_IRQSEL1 (S32K3XX_INTM_BASE + S32K3XX_INTM_IRQSEL1_OFFSET)
#define S32K3XX_INTM_LATENCY1 (S32K3XX_INTM_BASE + S32K3XX_INTM_LATENCY1_OFFSET)
#define S32K3XX_INTM_TIMER1 (S32K3XX_INTM_BASE + S32K3XX_INTM_TIMER1_OFFSET)
#define S32K3XX_INTM_STATUS1 (S32K3XX_INTM_BASE + S32K3XX_INTM_STATUS1_OFFSET)
#define S32K3XX_INTM_IRQSEL2 (S32K3XX_INTM_BASE + S32K3XX_INTM_IRQSEL2_OFFSET)
#define S32K3XX_INTM_LATENCY2 (S32K3XX_INTM_BASE + S32K3XX_INTM_LATENCY2_OFFSET)
#define S32K3XX_INTM_TIMER2 (S32K3XX_INTM_BASE + S32K3XX_INTM_TIMER2_OFFSET)
#define S32K3XX_INTM_STATUS2 (S32K3XX_INTM_BASE + S32K3XX_INTM_STATUS2_OFFSET)
#define S32K3XX_INTM_IRQSEL3 (S32K3XX_INTM_BASE + S32K3XX_INTM_IRQSEL3_OFFSET)
#define S32K3XX_INTM_LATENCY3 (S32K3XX_INTM_BASE + S32K3XX_INTM_LATENCY3_OFFSET)
#define S32K3XX_INTM_TIMER3 (S32K3XX_INTM_BASE + S32K3XX_INTM_TIMER3_OFFSET)
#define S32K3XX_INTM_STATUS3 (S32K3XX_INTM_BASE + S32K3XX_INTM_STATUS3_OFFSET)
/* INTM Register Bitfield Definitions ***************************************/
/* Monitor Mode Register (INTM_MM) */
#define INTM_MM (1 << 0) /* Bit 0: Monitor Mode (MM) */
/* Bits 1-31: Reserved */
/* Interrupt Acknowledge Register (ITNM_IACK) */
#define INTM_IACK_IRQ_SHIFT (0) /* Bits 0-9: Interrupt Request Number to stop INTM_TIMERn (IRQ)*/
#define INTM_IACK_IRQ_MASK (0x03ff << INTM_IACK_IRQ_SHIFT)
/* Bits 10-31: Reserved */
/* Interrupt Request Select n Register (INTM_IRQSELn) */
#define INTM_IRQSEL_IRQ_SHIFT (0) /* Bits 0-9: Interrupt Request Number to Monitor (IRQ) */
#define INTM_IRQSEL_IRQ_MASK (0x03ff << INTM_IRQSEL_IRQ_SHIFT)
/* Bits 10-31: Reserved */
/* INTM_LATENCYn Register */
#define INTM_LATENCY_LAT_SHIFT (0) /* Bits 0-23: Maximum number of INTM clock cycles allowed for the monitored interrupt request (LAT) */
#define INTM_LATENCY_LAT_MASK (0xffffff << INTM_LATENCY_LAT_SHIFT)
# define INTM_LATENCY_LAT_MAX (0xfffffd << INTM_LATENCY_LAT_SHIFT) /* Maximum allowed latency, see reference manual */
/* Bits 24-31: Reserved */
/* Timer n Register (INTM_TIMERn) */
#define INTM_TIMER_SHIFT (0) /* Bits 0-23: Count the number of INTM clock cycles (TIMER) */
#define INTM_TIMER_MASK (0xffffff << INTM_TIMER_SHIFT)
/* Bits 24-31: Reserved */
/* Status n Register (INTM_STATUSn) */
#define INTM_STATUS (1 << 0) /* Bit 0: Monitor status (STATUS) */
/* Bits 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_INTM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPI2C_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPI2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPI2C Register Offsets ***************************************************/
#define S32K3XX_LPI2C_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */
#define S32K3XX_LPI2C_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */
#define S32K3XX_LPI2C_MCR_OFFSET (0x0010) /* Master Control Register (MCR) */
#define S32K3XX_LPI2C_MSR_OFFSET (0x0014) /* Master Status Register (MSR) */
#define S32K3XX_LPI2C_MIER_OFFSET (0x0018) /* Master Interrupt Enable Register (MIER) */
#define S32K3XX_LPI2C_MDER_OFFSET (0x001c) /* Master DMA Enable Register (MDER) */
#define S32K3XX_LPI2C_MCFGR0_OFFSET (0x0020) /* Master Config Register 0 (MCFGR0) */
#define S32K3XX_LPI2C_MCFGR1_OFFSET (0x0024) /* Master Config Register 1 (MCFGR1) */
#define S32K3XX_LPI2C_MCFGR2_OFFSET (0x0028) /* Master Config Register 2 (MCFGR2) */
#define S32K3XX_LPI2C_MCFGR3_OFFSET (0x002c) /* Master Config Register 3 (MCFGR3) */
#define S32K3XX_LPI2C_MDMR_OFFSET (0x0040) /* Master Data Match Register (MDMR) */
#define S32K3XX_LPI2C_MCCR0_OFFSET (0x0048) /* Master Clock Configuration Register 0 (MCCR0) */
#define S32K3XX_LPI2C_MCCR1_OFFSET (0x0050) /* Master Clock Configuration Register 1 (MCCR1) */
#define S32K3XX_LPI2C_MFCR_OFFSET (0x0058) /* Master FIFO Control Register (MFCR) */
#define S32K3XX_LPI2C_MFSR_OFFSET (0x005c) /* Master FIFO Status Register (MFSR) */
#define S32K3XX_LPI2C_MTDR_OFFSET (0x0060) /* Master Transmit Data Register (MTDR) */
#define S32K3XX_LPI2C_MRDR_OFFSET (0x0070) /* Master Receive Data Register (MRDR) */
#define S32K3XX_LPI2C_SCR_OFFSET (0x0110) /* Slave Control Register (SCR) */
#define S32K3XX_LPI2C_SSR_OFFSET (0x0114) /* Slave Status Register (SSR) */
#define S32K3XX_LPI2C_SIER_OFFSET (0x0118) /* Slave Interrupt Enable Register (SIER) */
#define S32K3XX_LPI2C_SDER_OFFSET (0x011c) /* Slave DMA Enable Register (SDER) */
#define S32K3XX_LPI2C_SCFGR1_OFFSET (0x0124) /* Slave Config Register 1 (SCFGR1) */
#define S32K3XX_LPI2C_SCFGR2_OFFSET (0x0128) /* Slave Config Register 2 (SCFGR2) */
#define S32K3XX_LPI2C_SAMR_OFFSET (0x0140) /* Slave Address Match Register (SAMR) */
#define S32K3XX_LPI2C_SASR_OFFSET (0x0150) /* Slave Address Status Register (SASR) */
#define S32K3XX_LPI2C_STAR_OFFSET (0x0154) /* Slave Transmit ACK Register (STAR) */
#define S32K3XX_LPI2C_STDR_OFFSET (0x0160) /* Slave Transmit Data Register (STDR) */
#define S32K3XX_LPI2C_SRDR_OFFSET (0x0170) /* Slave Receive Data Register (SRDR) */
/* LPI2C Register Addresses *************************************************/
#define S32K3XX_LPI2C0_VERID (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_VERID_OFFSET)
#define S32K3XX_LPI2C0_PARAM (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_PARAM_OFFSET)
#define S32K3XX_LPI2C0_MCR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCR_OFFSET)
#define S32K3XX_LPI2C0_MSR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MSR_OFFSET)
#define S32K3XX_LPI2C0_MIER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MIER_OFFSET)
#define S32K3XX_LPI2C0_MDER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDER_OFFSET)
#define S32K3XX_LPI2C0_MCFGR0 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET)
#define S32K3XX_LPI2C0_MCFGR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET)
#define S32K3XX_LPI2C0_MCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
#define S32K3XX_LPI2C0_MCFGR3 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET)
#define S32K3XX_LPI2C0_MDMR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDMR_OFFSET)
#define S32K3XX_LPI2C0_MCCR0 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCCR0_OFFSET)
#define S32K3XX_LPI2C0_MCCR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCCR1_OFFSET)
#define S32K3XX_LPI2C0_MFCR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MFCR_OFFSET)
#define S32K3XX_LPI2C0_MFSR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MFSR_OFFSET)
#define S32K3XX_LPI2C0_MTDR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MTDR_OFFSET)
#define S32K3XX_LPI2C0_MRDR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MRDR_OFFSET)
#define S32K3XX_LPI2C0_SCR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCR_OFFSET)
#define S32K3XX_LPI2C0_SSR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SSR_OFFSET)
#define S32K3XX_LPI2C0_SIER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET)
#define S32K3XX_LPI2C0_SDER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SDER_OFFSET)
#define S32K3XX_LPI2C0_SCFGR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET)
#define S32K3XX_LPI2C0_SCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET)
#define S32K3XX_LPI2C0_SAMR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SAMR_OFFSET)
#define S32K3XX_LPI2C0_SASR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SASR_OFFSET)
#define S32K3XX_LPI2C0_STAR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_STAR_OFFSET)
#define S32K3XX_LPI2C0_STDR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_STDR_OFFSET)
#define S32K3XX_LPI2C0_SRDR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SRDR_OFFSET)
#define S32K3XX_LPI2C1_VERID (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_VERID_OFFSET)
#define S32K3XX_LPI2C1_PARAM (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_PARAM_OFFSET)
#define S32K3XX_LPI2C1_MCR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCR_OFFSET)
#define S32K3XX_LPI2C1_MSR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MSR_OFFSET)
#define S32K3XX_LPI2C1_MIER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MIER_OFFSET)
#define S32K3XX_LPI2C1_MDER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDER_OFFSET)
#define S32K3XX_LPI2C1_MCFGR0 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET)
#define S32K3XX_LPI2C1_MCFGR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET)
#define S32K3XX_LPI2C1_MCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
#define S32K3XX_LPI2C1_MCFGR3 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET)
#define S32K3XX_LPI2C1_MDMR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDMR_OFFSET)
#define S32K3XX_LPI2C1_MCCR0 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCCR0_OFFSET)
#define S32K3XX_LPI2C1_MCCR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCCR1_OFFSET)
#define S32K3XX_LPI2C1_MFCR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MFCR_OFFSET)
#define S32K3XX_LPI2C1_MFSR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MFSR_OFFSET)
#define S32K3XX_LPI2C1_MTDR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MTDR_OFFSET)
#define S32K3XX_LPI2C1_MRDR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MRDR_OFFSET)
#define S32K3XX_LPI2C1_SCR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCR_OFFSET)
#define S32K3XX_LPI2C1_SSR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SSR_OFFSET)
#define S32K3XX_LPI2C1_SIER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET)
#define S32K3XX_LPI2C1_SDER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SDER_OFFSET)
#define S32K3XX_LPI2C1_SCFGR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET)
#define S32K3XX_LPI2C1_SCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET)
#define S32K3XX_LPI2C1_SAMR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SAMR_OFFSET)
#define S32K3XX_LPI2C1_SASR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SASR_OFFSET)
#define S32K3XX_LPI2C1_STAR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_STAR_OFFSET)
#define S32K3XX_LPI2C1_STDR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_STDR_OFFSET)
#define S32K3XX_LPI2C1_SRDR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SRDR_OFFSET)
/* LPI2C Register Bitfield Definitions **************************************/
/* Version ID Register (VERID) */
#define LPI2C_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Specification Number (FEATURE) */
#define LPI2C_VERID_FEATURE_MASK (0xffff << LPI2C_VERID_FEATURE_SHIFT)
# define LPI2C_VERID_FEATURE_MSTRONL (0x0002 << LPI2C_VERID_FEATURE_SHIFT) /* Master only, with standard feature set */
# define LPI2C_VERID_FEATURE_MSTRSLV (0x0003 << LPI2C_VERID_FEATURE_SHIFT) /* Master and slave, with standard feature set */
#define LPI2C_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPI2C_VERID_MINOR_MASK (0xff << LPI2C_VERID_MINOR_SHIFT)
#define LPI2C_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPI2C_VERID_MAJOR_MASK (0xff << LPI2C_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPI2C_PARAM_MTXFIFO_SHIFT (0) /* Bits 0-3: Master Transmit FIFO Size (MTXFIFO) */
#define LPI2C_PARAM_MTXFIFO_MASK (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_1_WORDS (0x00 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_2_WORDS (0x01 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_4_WORDS (0x02 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_8_WORDS (0x03 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_16_WORDS (0x04 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_32_WORDS (0x05 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_64_WORDS (0x06 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_128_WORDS (0x07 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_256_WORDS (0x08 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_512_WORDS (0x09 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_1024_WORDS (0x0a << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_2048_WORDS (0x0b << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_4096_WORDS (0x0c << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_8192_WORDS (0x0d << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_16384_WORDS (0x0e << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_32768_WORDS (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT)
/* Bits 4-7: Reserved */
#define LPI2C_PARAM_MRXFIFO_SHIFT (8) /* Bits 8-11: Master Receive FIFO Size (MRXFIFO) */
#define LPI2C_PARAM_MRXFIFO_MASK (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_1_WORDS (0x00 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_2_WORDS (0x01 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_4_WORDS (0x02 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_8_WORDS (0x03 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_16_WORDS (0x04 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_32_WORDS (0x05 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_64_WORDS (0x06 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_128_WORDS (0x07 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_256_WORDS (0x08 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_512_WORDS (0x09 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_1024_WORDS (0x0a << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_2048_WORDS (0x0b << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_4096_WORDS (0x0c << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_8192_WORDS (0x0d << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_16384_WORDS (0x0e << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_32768_WORDS (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT)
/* Bits 12-31: Reserved */
/* Master Control Register (MCR) */
#define LPI2C_MCR_MEN (1 << 0) /* Bit 0: Master Enable (MEN) */
#define LPI2C_MCR_RST (1 << 1) /* Bit 1: Software Reset (RST) */
#define LPI2C_MCR_DOZEN (1 << 2) /* Bit 2: Doze Mode Enable (DOZEN) */
#define LPI2C_MCR_DBGEN (1 << 3) /* Bit 3: Debug Enable (DBGEN) */
/* Bits 4-7: Reserved */
#define LPI2C_MCR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */
#define LPI2C_MCR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */
/* Bits 10-31: Reserved */
/* Master Status Register (MSR) */
#define LPI2C_MSR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */
#define LPI2C_MSR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */
/* Bits 2-7: Reserved */
#define LPI2C_MSR_EPF (1 << 8) /* Bit 8: End Packet Flag (EPF) */
#define LPI2C_MSR_SDF (1 << 9) /* Bit 9: STOP Detect Flag (SDF) */
#define LPI2C_MSR_NDF (1 << 10) /* Bit 10: NACK Detect Flag (NDF) */
#define LPI2C_MSR_ALF (1 << 11) /* Bit 11: Arbitration Lost Flag (ALF) */
#define LPI2C_MSR_FEF (1 << 12) /* Bit 12: FIFO Error Flag (FEF) */
#define LPI2C_MSR_PLTF (1 << 13) /* Bit 13: Pin Low Timeout Flag (PLTF) */
#define LPI2C_MSR_DMF (1 << 14) /* Bit 14: Data Match Flag (DMF) */
/* Bits 15-23: Reserved */
#define LPI2C_MSR_MBF (1 << 24) /* Bit 24: Master Busy Flag (MBF) */
#define LPI2C_MSR_BBF (1 << 25) /* Bit 25: Bus Busy Flag (BBF) */
/* Bits 26-31: Reserved */
#define LPI2C_MSR_ERROR_MASK (LPI2C_MSR_NDF | LPI2C_MSR_ALF | LPI2C_MSR_FEF)
/* Master Interrupt Enable Register (MIER) */
#define LPI2C_MIER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */
#define LPI2C_MIER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */
/* Bits 2-7: Reserved */
#define LPI2C_MIER_EPIE (1 << 8) /* Bit 8: End Packet Interrupt Enable (EPIE) */
#define LPI2C_MIER_SDIE (1 << 9) /* Bit 9: STOP Detect Interrupt Enable (SDIE) */
#define LPI2C_MIER_NDIE (1 << 10) /* Bit 10: NACK Detect Interrupt Enable (NDIE) */
#define LPI2C_MIER_ALIE (1 << 11) /* Bit 11: Arbitration Lost Interrupt Enable (ALIE) */
#define LPI2C_MIER_FEIE (1 << 12) /* Bit 12: FIFO Error Interrupt Enable (FEIE) */
#define LPI2C_MIER_PLTIE (1 << 13) /* Bit 13: Pin Low Timeout Interrupt Enable (PLTIE) */
#define LPI2C_MIER_DMIE (1 << 14) /* Bit 14: Data Match Interrupt Enable (DMIE) */
/* Bits 15-31: Reserved */
/* Master DMA Enable Register (MDER) */
#define LPI2C_MDER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */
#define LPI2C_MDER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */
/* Bits 2-31: Reserved */
/* Master Config Register 0 (MCFGR0) */
#define LPI2C_MCFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable (HREN) */
#define LPI2C_MCFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity (HRPOL) */
#define LPI2C_MCFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select (HRSEL) */
/* Bits 3-7: Reserved */
#define LPI2C_MCFGR0_CIRFIFO (1 << 8) /* Bit 8: Circular FIFO Enable (CIRFIFO) */
#define LPI2C_MCFGR0_RDMO (1 << 9) /* Bit 9: Receive Data Match Only (RDMO) */
/* Bits 10-31: Reserved */
/* Master Config Register 1 (MCFGR1) */
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0) /* Bits 0-2: Prescaler (PRESCALE) */
#define LPI2C_MCFGR1_PRESCALE_MASK (0x07 << LPI2C_MCFGR1_PRESCALE_SHIFT)
# define LPI2C_MCFGR1_PRESCALE(n) (((n) << LPI2C_MCFGR1_PRESCALE_SHIFT) & LPI2C_MCFGR1_PRESCALE_MASK)
# define LPI2C_MCFGR1_PRESCALE_1 (0x00 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 1 */
# define LPI2C_MCFGR1_PRESCALE_2 (0x01 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 2 */
# define LPI2C_MCFGR1_PRESCALE_4 (0x02 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 4 */
# define LPI2C_MCFGR1_PRESCALE_8 (0x03 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 8 */
# define LPI2C_MCFGR1_PRESCALE_16 (0x04 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 16 */
# define LPI2C_MCFGR1_PRESCALE_32 (0x05 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 32 */
# define LPI2C_MCFGR1_PRESCALE_64 (0x06 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 64 */
# define LPI2C_MCFGR1_PRESCALE_128 (0x07 << LPI2C_MCFGR1_PRESCALE_SHIFT) /* Divide by 128 */
/* Bits 3-7: Reserved */
#define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Bit 8: Automatic STOP Generation (AUTOSTOP) */
#define LPI2C_MCFGR1_IGNACK (1 << 9) /* Bit 9: Ignore NACK (IGNACK) */
#define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Bit 10: Timeout Configuration (TIMECFG) */
/* Bits 11-15: Reserved */
#define LPI2C_MCFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration (MATCFG) */
#define LPI2C_MCFGR1_MATCFG_MASK (0x07 << LPI2C_MCFGR1_MATCFG_SHIFT)
# define LPI2C_MCFGR1_MATCFG(n) (((n) << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
# define LPI2C_MCFGR1_MATCFG_DISABLE (0x00 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is disabled */
# define LPI2C_MCFGR1_MATCFG2 (0x02 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1]) */
# define LPI2C_MCFGR1_MATCFG3 (0x03 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) */
# define LPI2C_MCFGR1_MATCFG4 (0x04 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1]) */
# define LPI2C_MCFGR1_MATCFG5 (0x05 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1]) */
# define LPI2C_MCFGR1_MATCFG6 (0x06 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) */
# define LPI2C_MCFGR1_MATCFG7 (0x07 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) */
/* Bits 19-23: Reserved */
#define LPI2C_MCFGR1_PINCFG_SHIFT (24) /* Bits 24-26: Pin Configuration (PINCFG) */
#define LPI2C_MCFGR1_PINCFG_MASK (0x07 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG(n) (((n) << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
# define LPI2C_MCFGR1_PINCFG0 (0x00 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Bi-directional open drain for master and slave */
# define LPI2C_MCFGR1_PINCFG1 (0x01 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Output-only (ultra-fast mode) open drain for master and slave */
# define LPI2C_MCFGR1_PINCFG2 (0x02 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Bi-directional push-pull for master and slave */
# define LPI2C_MCFGR1_PINCFG3 (0x03 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Input only for master and slave, SCLS/SDAS: Output-only push-pull for master and slave */
# define LPI2C_MCFGR1_PINCFG4 (0x04 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Bi-directional open drain for master, SCLS/SDAS: Bi-directional open drain for slave */
# define LPI2C_MCFGR1_PINCFG5 (0x05 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Output-only (ultra-fast mode) open drain for master, SCLS/SDAS: Output-only for slave */
# define LPI2C_MCFGR1_PINCFG6 (0x06 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Bi-directional push-pull for master, SCLS/SDAS: Bi-directional push-pull for slave */
# define LPI2C_MCFGR1_PINCFG7 (0x07 << LPI2C_MCFGR1_PINCFG_SHIFT) /* SCL/SDA: Input only for master and slave, SCLS/SDAS: Inverted output-only push-pull for master and slave */
/* Bits 27-31: Reserved */
/* Master Config Register 2 (MCFGR2) */
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0) /* Bits 0-11: Bus Idle Timeout (BUSIDLE) */
#define LPI2C_MCFGR2_BUSIDLE_MASK (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT)
#define LPI2C_MCFGR2_BUSIDLE_DISABLE (0x0000 << LPI2C_MCFGR2_BUSIDLE_SHIFT)
# define LPI2C_MCFGR2_BUSIDLE(n) (((n) << LPI2C_MCFGR2_BUSIDLE_SHIFT) & LPI2C_MCFGR2_BUSIDLE_MASK)
/* Bits 12-15: Reserved */
#define LPI2C_MCFGR2_FILTSCL_SHIFT (16) /* Bits 16-19: Glitch Filter SCL (FILTSCL) */
#define LPI2C_MCFGR2_FILTSCL_MASK (0x0f << LPI2C_MCFGR2_FILTSCL_SHIFT)
#define LPI2C_MCFGR2_FILTSCL_DISABLE (0x00 << LPI2C_MCFGR2_FILTSCL_SHIFT)
# define LPI2C_MCFGR2_FILTSCL_CYCLES(n) (((n) << LPI2C_MCFGR2_FILTSCL_SHIFT) & LPI2C_MCFGR2_FILTSCL_MASK)
/* Bits 20-23: Reserved */
#define LPI2C_MCFGR2_FILTSDA_SHIFT (24) /* Bits 24-27: Glitch Filter SDA (FILTSDA) */
#define LPI2C_MCFGR2_FILTSDA_MASK (0x0f << LPI2C_MCFGR2_FILTSDA_SHIFT)
#define LPI2C_MCFGR2_FILTSDA_DISABLE (0x00 << LPI2C_MCFGR2_FILTSDA_SHIFT)
# define LPI2C_MCFGR2_FILTSDA_CYCLES(n) (((n) << LPI2C_MCFGR2_FILTSDA_SHIFT) & LPI2C_MCFGR2_FILTSDA_MASK)
/* Bits 28-31: Reserved */
/* Master Config Register 3 (MCFGR3) */
/* Bits 0-7: Reserved */
#define LPI2C_MCFGR3_PINLOW_SHIFT (8) /* Bits 8-19: Pin Low Timeout (PINLOW) */
#define LPI2C_MCFGR3_PINLOW_MASK (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT)
# define LPI2C_MCFGR3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFGR3_PINLOW_SHIFT) & LPI2C_MCFGR3_PINLOW_MASK)
/* Bits 20-31: Reserved */
/* Master Data Match Register (MDMR) */
#define LPI2C_MDMR_MATCH0_SHIFT (0) /* Bits 0-7: Match 0 Value (MATCH0) */
#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT)
# define LPI2C_MDMR_MATCH0(n) (((n) << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
/* Bits 8-15: Reserved */
#define LPI2C_MDMR_MATCH1_SHIFT (16) /* Bits 16-23: Match 1 Value (MATCH1) */
#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT)
# define LPI2C_MDMR_MATCH1(n) (((n) << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
/* Bits 24-31: Reserved */
/* Master Clock Configuration Register 0 (MCCR0) */
#define LPI2C_MCCR0_CLKLO_SHIFT (0) /* Bits 0-5: Clock Low Period (CLKLO) */
#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT)
# define LPI2C_MCCR0_CLKLO(n) (((n) << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
/* Bits 6-7: Reserved */
#define LPI2C_MCCR0_CLKHI_SHIFT (8) /* Bits 8-13: Clock High Period (CLKHI) */
#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT)
# define LPI2C_MCCR0_CLKHI(n) (((n) << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
/* Bits 14-15: Reserved */
#define LPI2C_MCCR0_SETHOLD_SHIFT (16) /* Bits 16-21: Setup Hold Delay (SETHOLD) */
#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT)
# define LPI2C_MCCR0_SETHOLD(n) (((n) << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
/* Bits 22-23: Reserved */
#define LPI2C_MCCR0_DATAVD_SHIFT (24) /* Bits 24-29: Data Valid Delay (DATAVD) */
#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT)
# define LPI2C_MCCR0_DATAVD(n) (((n) << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
/* Bits 30-31: Reserved */
/* Master Clock Configuration Register 1 (MCCR1) */
#define LPI2C_MCCR1_CLKLO_SHIFT (0) /* Bits 0-5: Clock Low Period (CLKLO) */
#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT)
# define LPI2C_MCCR1_CLKLO(n) (((n) << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
/* Bits 6-7: Reserved */
#define LPI2C_MCCR1_CLKHI_SHIFT (8) /* Bits 8-13: Clock High Period (CLKHI) */
#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT)
# define LPI2C_MCCR1_CLKHI(n) (((n) << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
/* Bits 14-15: Reserved */
#define LPI2C_MCCR1_SETHOLD_SHIFT (16) /* Bits 16-21: Setup Hold Delay (SETHOLD) */
#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT)
# define LPI2C_MCCR1_SETHOLD(n) (((n) << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
/* Bits 22-23: Reserved */
#define LPI2C_MCCR1_DATAVD_SHIFT (24) /* Bits 24-29: Data Valid Delay (DATAVD) */
#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT)
# define LPI2C_MCCR1_DATAVD(n) (((n) << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
/* Bits 30-31: Reserved */
/* Master FIFO Control Register (MFCR) */
#define LPI2C_MFCR_TXWATER_SHIFT (0) /* Bits 0-1: Transmit FIFO Watermark (TXWATER) */
#define LPI2C_MFCR_TXWATER_MASK (0x03 << LPI2C_MFCR_TXWATER_SHIFT)
# define LPI2C_MFCR_TXWATER(n) (((n) << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK)
/* Bits 2-15: Reserved */
#define LPI2C_MFCR_RXWATER_SHIFT (16) /* Bits 16-17: Receive FIFO Watermark (RXWATER) */
#define LPI2C_MFCR_RXWATER_MASK (0x03 << LPI2C_MFCR_RXWATER_SHIFT)
# define LPI2C_MFCR_RXWATER(n) (((n) << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK)
/* Bits 18-31: Reserved */
/* Master FIFO Status Register (MFSR) */
#define LPI2C_MFSR_TXCOUNT_SHIFT (0) /* Bits 0-2: Transmit FIFO Count (TXCOUNT) */
#define LPI2C_MFSR_TXCOUNT_MASK (0x07 << LPI2C_MFSR_TXCOUNT_SHIFT)
/* Bits 15-2 Reserved */
#define LPI2C_MFSR_RXCOUNT_SHIFT (16) /* Bits 16-18: Receive FIFO Count (RXCOUNT) */
#define LPI2C_MFSR_RXCOUNT_MASK (0x07 << LPI2C_MFSR_RXCOUNT_SHIFT)
/* Bits 18-31: Reserved */
/* Master Transmit Data Register (MTDR) */
#define LPI2C_MTDR_DATA_SHIFT (0) /* Bits 0-7: Transmit Data (DATA) */
#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT)
# define LPI2C_MTDR_DATA(n) (((n) << LPI2C_MTDR_DATA_SHIFT) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_SHIFT (8) /* Bits 8-10: Command Data (CMD) */
#define LPI2C_MTDR_CMD_MASK (0x07 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD(n) (((n) << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
# define LPI2C_MTDR_CMD_TXD (0x00 << LPI2C_MTDR_CMD_SHIFT) /* Transmit DATA[7:0] */
# define LPI2C_MTDR_CMD_RXD (0x01 << LPI2C_MTDR_CMD_SHIFT) /* Receive (DATA[7:0] + 1) bytes */
# define LPI2C_MTDR_CMD_STOP (0x02 << LPI2C_MTDR_CMD_SHIFT) /* Generate STOP condition */
# define LPI2C_MTDR_CMD_RXD_DISC (0x03 << LPI2C_MTDR_CMD_SHIFT) /* Receive and discard (DATA[7:0] + 1) bytes */
# define LPI2C_MTDR_CMD_START (0x04 << LPI2C_MTDR_CMD_SHIFT) /* Generate (repeated) START and transmit address in DATA[7:0] */
# define LPI2C_MTDR_CMD_START_NACK (0x05 << LPI2C_MTDR_CMD_SHIFT) /* Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. */
# define LPI2C_MTDR_CMD_START_HI (0x06 << LPI2C_MTDR_CMD_SHIFT) /* Generate (repeated) START and transmit address in DATA[7:0] using high speed mode */
# define LPI2C_MTDR_CMD_START_HI_NACK (0x07 << LPI2C_MTDR_CMD_SHIFT) /* Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.*/
/* Bits 11-31: Reserved */
/* Master Receive Data Register (MRDR) */
#define LPI2C_MRDR_DATA_SHIFT (0) /* Bits 0-7: Receive Data (DATA) */
#define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT)
/* Bits 8-13: Reserved */
#define LPI2C_MRDR_RXEMPTY (1 << 14) /* Bit 14: RX Empty (RXEMPTY) */
/* Bits 15-31: Reserved */
/* Slave Control Register (SCR) */
#define LPI2C_SCR_SEN (1 << 0) /* Bit 0: Slave Enable (SEN) */
#define LPI2C_SCR_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bits 2-3: Reserved */
#define LPI2C_SCR_FILTEN (1 << 4) /* Bit 4: Filter Enable (FILTEN) */
#define LPI2C_SCR_FILTDZ (1 << 5) /* Bit 5: Filter Doze Enable (FILTDZ) */
/* Bits 6-7: Reserved */
#define LPI2C_SCR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */
#define LPI2C_SCR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */
/* Bits 10-31: Reserved */
/* Slave Status Register (SSR) */
#define LPI2C_SSR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */
#define LPI2C_SSR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */
#define LPI2C_SSR_AVF (1 << 2) /* Bit 2: Address Valid Flag (AVF) */
#define LPI2C_SSR_TAF (1 << 3) /* Bit 3: Transmit ACK Flag (TAF) */
/* Bits 4-7: Reserved */
#define LPI2C_SSR_RSF (1 << 8) /* Bit 8: Repeated Start Flag (RSF) */
#define LPI2C_SSR_SDF (1 << 9) /* Bit 9: STOP Detect Flag (SDF) */
#define LPI2C_SSR_BEF (1 << 10) /* Bit 10: Bit Error Flag (BEF) */
#define LPI2C_SSR_FEF (1 << 11) /* Bit 11: FIFO Error Flag (FEF) */
#define LPI2C_SSR_AM0F (1 << 12) /* Bit 12: Address Match 0 Flag (AM0F) */
#define LPI2C_SSR_AM1F (1 << 13) /* Bit 13: Address Match 1 Flag (AM1F) */
#define LPI2C_SSR_GCF (1 << 14) /* Bit 14: General Call Flag (GCF) */
#define LPI2C_SSR_SARF (1 << 15) /* Bit 15: SMBus Alert Response Flag (SARF) */
/* Bits 16-23: Reserved */
#define LPI2C_MSR_SBF (1 << 24) /* Bit 24: Slave Busy Flag (SBF) */
#define LPI2C_MSR_BBF (1 << 25) /* Bit 25: Bus Busy Flag (BBF) */
/* Bits 26-31: Reserved */
/* Slave Interrupt Enable Register (SIER) */
#define LPI2C_SIER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */
#define LPI2C_SIER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */
#define LPI2C_SIER_AVIE (1 << 2) /* Bit 2: Address Valid Interrupt Enable (AVIE) */
#define LPI2C_SIER_TAIE (1 << 3) /* Bit 3: Transmit ACK Interrupt Enable (TAIE) */
/* Bits 4-7: Reserved */
#define LPI2C_SIER_RSIE (1 << 8) /* Bit 8: Repeated Start Interrupt Enable (RSIE) */
#define LPI2C_SIER_SDIE (1 << 9) /* Bit 9: STOP Detect Interrupt Enable (SDIE) */
#define LPI2C_SIER_BEIE (1 << 10) /* Bit 10: Bit Error Interrupt Enable (BEIE) */
#define LPI2C_SIER_FEIE (1 << 11) /* Bit 11: FIFO Error Interrupt Enable (FEIE) */
#define LPI2C_SIER_AM0IE (1 << 12) /* Bit 12: Address Match 0 Interrupt Enable (AM0IE) */
#define LPI2C_SIER_AM1IE (1 << 13) /* Bit 13: Address Match 1 Interrupt Enable (AM1IE) */
#define LPI2C_SIER_GCIE (1 << 14) /* Bit 14: General Call Interrupt Enable (GCIE) */
#define LPI2C_SIER_SARIE (1 << 15) /* Bit 15: SMBus Alert Response Interrupt Enable (SARIE) */
/* Bits 16-31: Reserved */
/* Slave DMA Enable Register (SDER) */
#define LPI2C_SDER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */
#define LPI2C_SDER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */
#define LPI2C_SDER_AVDE (1 << 2) /* Bit 2: Address Valid DMA Enable (AVDE) */
/* Bits 3-31: Reserved */
/* Slave Configuration Register 1 (SCFGR1) */
#define LPI2C_SCFGR1_ADRSTALL (1 << 0) /* Bit 0: Address SCL Stall (ADRSTALL) */
#define LPI2C_SCFGR1_RXSTALL (1 << 1) /* Bit 1: RX SCL Stall (RXSTALL) */
#define LPI2C_SCFGR1_TXSTALL (1 << 2) /* Bit 2: TX Data SCL Stall (TXDSTALL) */
#define LPI2C_SCFGR1_ACKSTALL (1 << 3) /* Bit 3: ACK SCL Stall (ACKSTALL) */
/* Bits 4-7: Reserved */
#define LPI2C_SCFGR1_GCEN (1 << 8) /* Bit 8: General Call Enable (GCEN) */
#define LPI2C_SCFGR1_SAEN (1 << 9) /* Bit 9: SMBus Alert Enable (SAEN) */
#define LPI2C_SCFGR1_TXCFG (1 << 10) /* Bit 10: Transmit Flag Configuration (TXCFG) */
#define LPI2C_SCFGR1_RXCFG (1 << 11) /* Bit 11: Receive Data Configuration (RXCFG) */
#define LPI2C_SCFGR1_IGNACK (1 << 12) /* Bit 12: Ignore NACK (IGNACK) */
#define LPI2C_SCFGR1_HSMEN (1 << 13) /* Bit 13: High Speed Mode Enable (HSMEN) */
/* Bits 14-15: Reserved */
#define LPI2C_SCFG1_ADDRCFG_SHIFT (16) /* Bits 16-18: Address Configuration (ADDRCFG) */
#define LPI2C_SCFG1_ADDRCFG_MASK (0x07 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG(n) (((n) << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
# define LPI2C_SCFG1_ADDRCFG0 (0x00 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address match 0 (7-bit) */
# define LPI2C_SCFG1_ADDRCFG1 (0x01 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address match 0 (10-bit) */
# define LPI2C_SCFG1_ADDRCFG2 (0x02 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address match 0 (7-bit) or Address match 1 (7-bit) */
# define LPI2C_SCFG1_ADDRCFG3 (0x03 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address match 0 (10-bit) or Address match 1 (10-bit) */
# define LPI2C_SCFG1_ADDRCFG4 (0x04 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address match 0 (7-bit) or Address match 1 (10-bit) */
# define LPI2C_SCFG1_ADDRCFG5 (0x05 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address match 0 (10-bit) or Address match 1 (7-bit) */
# define LPI2C_SCFG1_ADDRCFG6 (0x06 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* From Address match 0 (7-bit) to Address match 1 (7-bit) */
# define LPI2C_SCFG1_ADDRCFG7 (0x07 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* From Address match 0 (10-bit) to Address match 1 (10-bit) */
/* Bits 19-31: Reserved */
/* Slave Configuration Register 2 (SCFGR2) */
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0) /* Bits 0-3: Clock Hold Time (CLKHOLD) */
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xff << LPI2C_SCFGR2_CLKHOLD_SHIFT)
# define LPI2C_SCFGR2_CLKHOLD(n) (((n) & LPI2C_SCFGR2_CLKHOLD_MASK) << LPI2C_SCFGR2_CLKHOLD_SHIFT)
/* Bits 4-7: Reserved */
#define LPI2C_SCFGR2_DATAVD_SHIFT (8) /* Bits 8-13: Data Valid Delay (DATAVD) */
#define LPI2C_SCFGR2_DATAVD_MASK (0x3f << LPI2C_SCFGR2_DATAVD_SHIFT)
# define LPI2C_SCFGR2_DATAVD(n) (((n) << LPI2C_SCFGR2_DATAVD_SHIFT) & LPI2C_SCFGR2_DATAVD_MASK)
/* Bits 14-15: Reserved */
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16) /* Bits 16-19: Glitch Filter SCL (FILTSCL) */
#define LPI2C_SCFGR2_FILTSCL_MASK (0xff << LPI2C_SCFGR2_FILTSCL_SHIFT)
#define LPI2C_SCFGR2_FILTSCL_DISABLE (0x00 << LPI2C_SCFGR2_FILTSCL_SHIFT)
# define LPI2C_SCFGR2_FILTSCL_CYCLES(n) (((n) << LPI2C_SCFGR2_FILTSCL_SHIFT) & LPI2C_SCFGR2_FILTSCL_MASK)
/* Bits 20-23: Reserved */
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24) /* Bits 24-27: Glitch Filter SDA (FILTSDA) */
#define LPI2C_SCFGR2_FILTSDA_MASK (0xff << LPI2C_SCFGR2_FILTSDA_SHIFT)
#define LPI2C_SCFGR2_FILTSDA_DISABLE (0x00 << LPI2C_SCFGR2_FILTSDA_SHIFT)
# define LPI2C_SCFGR2_FILTSDA_CYCLES(n) (((n) << LPI2C_SCFGR2_FILTSDA_SHIFT) & LPI2C_SCFGR2_FILTSDA_MASK)
/* Bits 28-31: Reserved */
/* Slave Address Match Register (SAMR) */
/* Bit 0: Reserved */
#define LPI2C_SAMR_ADDR0_SHIFT (1) /* Bits 1-10: Address 0 Value (ADDR0) */
#define LPI2C_SAMR_ADDR0_MASK (0x03ff << LPI2C_SAMR_ADDR0_SHIFT)
# define LPI2C_SAMR_ADDR0(n) (((n) << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
/* Bits 11-16: Reserved */
#define LPI2C_SAMR_ADDR1_SHIFT (17) /* Bits 17-26: Address 1 Value (ADDR1) */
#define LPI2C_SAMR_ADDR1_MASK (0x03ff << LPI2C_SAMR_ADDR1_SHIFT)
# define LPI2C_SAMR_ADDR1(n) (((n) << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
/* Bits 27-31: Reserved */
/* Slave Address Status Register (SASR) */
#define LPI2C_SASR_RADDR_SHIFT (0) /* Bits 0-10: Received Address (RADDR) */
#define LPI2C_SASR_RADDR_MASK (0x07ff << LPI2C_SASR_RADDR_SHIFT)
/* Bits 11-13: Reserved */
#define LPI2C_SASR_ANV (1 << 14) /* Bit 14: Address Not Valid (ANV) */
/* Bits 15-31: Reserved */
/* Slave Transmit ACK Register (STAR) */
#define LPI2C_STAR_TXNACK (1 << 0) /* Bit 0: Transmit NACK (TXNACK) */
/* Bits 1-31: Reserved */
/* Slave Transmit Data Register (STDR) */
#define LPI2C_STDR_DATA_SHIFT (0) /* Bits 0-7: Transmit Data (DATA) */
#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT)
# define LPI2C_STDR_DATA(n) (((n) << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
/* Bits 8-31: Reserved */
/* Slave Receive Data Register (SRDR) */
#define LPI2C_SRDR_DATA_SHIFT (0) /* Bits 0-7: Receive Data (DATA) */
#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT)
# define LPI2C_SRDR_DATA(n) (((n) << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
/* Bits 8-13: Reserved */
#define LPI2C_SRDR_RXEMPTY (1 << 14) /* Bit 14: RX Empty (RXEMPTY) */
#define LPI2C_SRDR_SOF (1 << 15) /* Bit 15: Start Of Frame (SOF) */
/* Bits 16-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPI2C_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_lpspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPSPI_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPSPI Register Offsets ***************************************************/
#define S32K3XX_LPSPI_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */
#define S32K3XX_LPSPI_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */
#define S32K3XX_LPSPI_CR_OFFSET (0x0010) /* Control Register (CR) */
#define S32K3XX_LPSPI_SR_OFFSET (0x0014) /* Status Register (SR) */
#define S32K3XX_LPSPI_IER_OFFSET (0x0018) /* Interrupt Enable Register (IER) */
#define S32K3XX_LPSPI_DER_OFFSET (0x001c) /* DMA Enable Register (DER) */
#define S32K3XX_LPSPI_CFGR0_OFFSET (0x0020) /* Configuration Register 0 (CFGR0) */
#define S32K3XX_LPSPI_CFGR1_OFFSET (0x0024) /* Configuration Register 1 (CFGR1) */
#define S32K3XX_LPSPI_DMR0_OFFSET (0x0030) /* Data Match Register 0 (DMR0) */
#define S32K3XX_LPSPI_DMR1_OFFSET (0x0034) /* Data Match Register 1 (DMR1) */
#define S32K3XX_LPSPI_CCR_OFFSET (0x0040) /* Clock Configuration Register (CCR) */
#define S32K3XX_LPSPI_CCR1_OFFSET (0x0044) /* Clock Configuration Register 1 (CCR1) */
#define S32K3XX_LPSPI_FCR_OFFSET (0x0058) /* FIFO Control Register (FCR) */
#define S32K3XX_LPSPI_FSR_OFFSET (0x005c) /* FIFO Status Register (FSR) */
#define S32K3XX_LPSPI_TCR_OFFSET (0x0060) /* Transmit Command Register (TCR) */
#define S32K3XX_LPSPI_TDR_OFFSET (0x0064) /* Transmit Data Register (TDR) */
#define S32K3XX_LPSPI_RSR_OFFSET (0x0070) /* Receive Status Register (RSR) */
#define S32K3XX_LPSPI_RDR_OFFSET (0x0074) /* Receive Data Register (RDR) */
#define S32K3XX_LPSPI_RDROR_OFFSET (0x0078) /* Receive Data Read Only Register (RDROR) */
#define S32K3XX_LPSPI_TCBR_OFFSET (0x03fc) /* Transmit Command Burst Register (TCBR) */
#define S32K3XX_LPSPI_TDBR_OFFSET(n) (0x0400 + ((n) << 2)) /* Transmit Data Burst Register n=0..127 (TDBRn) */
#define S32K3XX_LPSPI_RDBR_OFFSET(n) (0x0600 + ((n) << 2)) /* Receive Data Burst Register n=0..127 (RDBRn) */
/* LPSPI Register Addresses *************************************************/
#define S32K3XX_LPSPI0_VERID (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_VERID_OFFSET)
#define S32K3XX_LPSPI0_PARAM (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_PARAM_OFFSET)
#define S32K3XX_LPSPI0_CR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_CR_OFFSET)
#define S32K3XX_LPSPI0_SR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_SR_OFFSET)
#define S32K3XX_LPSPI0_IER (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_IER_OFFSET)
#define S32K3XX_LPSPI0_DER (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_DER_OFFSET)
#define S32K3XX_LPSPI0_CFGR0 (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_CFGR0_OFFSET)
#define S32K3XX_LPSPI0_CFGR1 (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_CFGR1_OFFSET)
#define S32K3XX_LPSPI0_DMR0 (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_DMR0_OFFSET)
#define S32K3XX_LPSPI0_DMR1 (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_DMR1_OFFSET)
#define S32K3XX_LPSPI0_CCR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_CCR_OFFSET)
#define S32K3XX_LPSPI0_CCR1 (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_CCR1_OFFSET)
#define S32K3XX_LPSPI0_FCR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_FCR_OFFSET)
#define S32K3XX_LPSPI0_FSR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_FSR_OFFSET)
#define S32K3XX_LPSPI0_TCR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_TCR_OFFSET)
#define S32K3XX_LPSPI0_TDR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_TDR_OFFSET)
#define S32K3XX_LPSPI0_RSR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_RSR_OFFSET)
#define S32K3XX_LPSPI0_RDR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_RDR_OFFSET)
#define S32K3XX_LPSPI0_RDROR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_RDROR_OFFSET)
#define S32K3XX_LPSPI0_TCBR (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_TCBR_OFFSET)
#define S32K3XX_LPSPI0_TDBR(n) (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_TDBR_OFFSET(n))
#define S32K3XX_LPSPI0_RDBR(n) (S32K3XX_LPSPI0_BASE + S32K3XX_LPSPI_RDBR_OFFSET(n))
#define S32K3XX_LPSPI1_VERID (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_VERID_OFFSET)
#define S32K3XX_LPSPI1_PARAM (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_PARAM_OFFSET)
#define S32K3XX_LPSPI1_CR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_CR_OFFSET)
#define S32K3XX_LPSPI1_SR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_SR_OFFSET)
#define S32K3XX_LPSPI1_IER (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_IER_OFFSET)
#define S32K3XX_LPSPI1_DER (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_DER_OFFSET)
#define S32K3XX_LPSPI1_CFGR0 (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_CFGR0_OFFSET)
#define S32K3XX_LPSPI1_CFGR1 (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_CFGR1_OFFSET)
#define S32K3XX_LPSPI1_DMR0 (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_DMR0_OFFSET)
#define S32K3XX_LPSPI1_DMR1 (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_DMR1_OFFSET)
#define S32K3XX_LPSPI1_CCR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_CCR_OFFSET)
#define S32K3XX_LPSPI1_CCR1 (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_CCR1_OFFSET)
#define S32K3XX_LPSPI1_FCR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_FCR_OFFSET)
#define S32K3XX_LPSPI1_FSR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_FSR_OFFSET)
#define S32K3XX_LPSPI1_TCR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_TCR_OFFSET)
#define S32K3XX_LPSPI1_TDR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_TDR_OFFSET)
#define S32K3XX_LPSPI1_RSR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_RSR_OFFSET)
#define S32K3XX_LPSPI1_RDR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_RDR_OFFSET)
#define S32K3XX_LPSPI1_RDROR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_RDROR_OFFSET)
#define S32K3XX_LPSPI1_TCBR (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_TCBR_OFFSET)
#define S32K3XX_LPSPI1_TDBR(n) (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_TDBR_OFFSET(n))
#define S32K3XX_LPSPI1_RDBR(n) (S32K3XX_LPSPI1_BASE + S32K3XX_LPSPI_RDBR_OFFSET(n))
#define S32K3XX_LPSPI2_VERID (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_VERID_OFFSET)
#define S32K3XX_LPSPI2_PARAM (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_PARAM_OFFSET)
#define S32K3XX_LPSPI2_CR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_CR_OFFSET)
#define S32K3XX_LPSPI2_SR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_SR_OFFSET)
#define S32K3XX_LPSPI2_IER (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_IER_OFFSET)
#define S32K3XX_LPSPI2_DER (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_DER_OFFSET)
#define S32K3XX_LPSPI2_CFGR0 (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_CFGR0_OFFSET)
#define S32K3XX_LPSPI2_CFGR1 (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_CFGR1_OFFSET)
#define S32K3XX_LPSPI2_DMR0 (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_DMR0_OFFSET)
#define S32K3XX_LPSPI2_DMR1 (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_DMR1_OFFSET)
#define S32K3XX_LPSPI2_CCR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_CCR_OFFSET)
#define S32K3XX_LPSPI2_CCR1 (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_CCR1_OFFSET)
#define S32K3XX_LPSPI2_FCR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_FCR_OFFSET)
#define S32K3XX_LPSPI2_FSR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_FSR_OFFSET)
#define S32K3XX_LPSPI2_TCR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_TCR_OFFSET)
#define S32K3XX_LPSPI2_TDR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_TDR_OFFSET)
#define S32K3XX_LPSPI2_RSR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_RSR_OFFSET)
#define S32K3XX_LPSPI2_RDR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_RDR_OFFSET)
#define S32K3XX_LPSPI2_RDROR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_RDROR_OFFSET)
#define S32K3XX_LPSPI2_TCBR (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_TCBR_OFFSET)
#define S32K3XX_LPSPI2_TDBR(n) (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_TDBR_OFFSET(n))
#define S32K3XX_LPSPI2_RDBR(n) (S32K3XX_LPSPI2_BASE + S32K3XX_LPSPI_RDBR_OFFSET(n))
#define S32K3XX_LPSPI3_VERID (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_VERID_OFFSET)
#define S32K3XX_LPSPI3_PARAM (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_PARAM_OFFSET)
#define S32K3XX_LPSPI3_CR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_CR_OFFSET)
#define S32K3XX_LPSPI3_SR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_SR_OFFSET)
#define S32K3XX_LPSPI3_IER (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_IER_OFFSET)
#define S32K3XX_LPSPI3_DER (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_DER_OFFSET)
#define S32K3XX_LPSPI3_CFGR0 (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_CFGR0_OFFSET)
#define S32K3XX_LPSPI3_CFGR1 (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_CFGR1_OFFSET)
#define S32K3XX_LPSPI3_DMR0 (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_DMR0_OFFSET)
#define S32K3XX_LPSPI3_DMR1 (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_DMR1_OFFSET)
#define S32K3XX_LPSPI3_CCR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_CCR_OFFSET)
#define S32K3XX_LPSPI3_CCR1 (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_CCR1_OFFSET)
#define S32K3XX_LPSPI3_FCR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_FCR_OFFSET)
#define S32K3XX_LPSPI3_FSR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_FSR_OFFSET)
#define S32K3XX_LPSPI3_TCR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_TCR_OFFSET)
#define S32K3XX_LPSPI3_TDR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_TDR_OFFSET)
#define S32K3XX_LPSPI3_RSR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_RSR_OFFSET)
#define S32K3XX_LPSPI3_RDR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_RDR_OFFSET)
#define S32K3XX_LPSPI3_RDROR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_RDROR_OFFSET)
#define S32K3XX_LPSPI3_TCBR (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_TCBR_OFFSET)
#define S32K3XX_LPSPI3_TDBR(n) (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_TDBR_OFFSET(n))
#define S32K3XX_LPSPI3_RDBR(n) (S32K3XX_LPSPI3_BASE + S32K3XX_LPSPI_RDBR_OFFSET(n))
#define S32K3XX_LPSPI4_VERID (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_VERID_OFFSET)
#define S32K3XX_LPSPI4_PARAM (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_PARAM_OFFSET)
#define S32K3XX_LPSPI4_CR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_CR_OFFSET)
#define S32K3XX_LPSPI4_SR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_SR_OFFSET)
#define S32K3XX_LPSPI4_IER (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_IER_OFFSET)
#define S32K3XX_LPSPI4_DER (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_DER_OFFSET)
#define S32K3XX_LPSPI4_CFGR0 (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_CFGR0_OFFSET)
#define S32K3XX_LPSPI4_CFGR1 (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_CFGR1_OFFSET)
#define S32K3XX_LPSPI4_DMR0 (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_DMR0_OFFSET)
#define S32K3XX_LPSPI4_DMR1 (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_DMR1_OFFSET)
#define S32K3XX_LPSPI4_CCR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_CCR_OFFSET)
#define S32K3XX_LPSPI4_CCR1 (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_CCR1_OFFSET)
#define S32K3XX_LPSPI4_FCR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_FCR_OFFSET)
#define S32K3XX_LPSPI4_FSR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_FSR_OFFSET)
#define S32K3XX_LPSPI4_TCR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_TCR_OFFSET)
#define S32K3XX_LPSPI4_TDR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_TDR_OFFSET)
#define S32K3XX_LPSPI4_RSR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_RSR_OFFSET)
#define S32K3XX_LPSPI4_RDR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_RDR_OFFSET)
#define S32K3XX_LPSPI4_RDROR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_RDROR_OFFSET)
#define S32K3XX_LPSPI4_TCBR (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_TCBR_OFFSET)
#define S32K3XX_LPSPI4_TDBR(n) (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_TDBR_OFFSET(n))
#define S32K3XX_LPSPI4_RDBR(n) (S32K3XX_LPSPI4_BASE + S32K3XX_LPSPI_RDBR_OFFSET(n))
#define S32K3XX_LPSPI5_VERID (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_VERID_OFFSET)
#define S32K3XX_LPSPI5_PARAM (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_PARAM_OFFSET)
#define S32K3XX_LPSPI5_CR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_CR_OFFSET)
#define S32K3XX_LPSPI5_SR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_SR_OFFSET)
#define S32K3XX_LPSPI5_IER (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_IER_OFFSET)
#define S32K3XX_LPSPI5_DER (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_DER_OFFSET)
#define S32K3XX_LPSPI5_CFGR0 (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_CFGR0_OFFSET)
#define S32K3XX_LPSPI5_CFGR1 (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_CFGR1_OFFSET)
#define S32K3XX_LPSPI5_DMR0 (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_DMR0_OFFSET)
#define S32K3XX_LPSPI5_DMR1 (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_DMR1_OFFSET)
#define S32K3XX_LPSPI5_CCR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_CCR_OFFSET)
#define S32K3XX_LPSPI5_CCR1 (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_CCR1_OFFSET)
#define S32K3XX_LPSPI5_FCR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_FCR_OFFSET)
#define S32K3XX_LPSPI5_FSR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_FSR_OFFSET)
#define S32K3XX_LPSPI5_TCR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_TCR_OFFSET)
#define S32K3XX_LPSPI5_TDR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_TDR_OFFSET)
#define S32K3XX_LPSPI5_RSR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_RSR_OFFSET)
#define S32K3XX_LPSPI5_RDR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_RDR_OFFSET)
#define S32K3XX_LPSPI5_RDROR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_RDROR_OFFSET)
#define S32K3XX_LPSPI5_TCBR (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_TCBR_OFFSET)
#define S32K3XX_LPSPI5_TDBR(n) (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_TDBR_OFFSET(n))
#define S32K3XX_LPSPI5_RDBR(n) (S32K3XX_LPSPI5_BASE + S32K3XX_LPSPI_RDBR_OFFSET(n))
/* LPSPI Register Bitfield Definitions **************************************/
/* Version ID Register (VERID) */
#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number (FEATURE) */
#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT)
#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT)
#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT)
#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT)
#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number (PCSNUM) */
#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT)
/* Bits 24-31: Reserved */
/* Control Register (CR) */
#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable (MEN) */
#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bit 2: Reserved */
#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable (DBGEN) */
/* Bits 4-7: Reserved */
#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */
#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */
/* Bits 10-31: Reserved */
/* Status Register (SR) */
#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */
#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */
/* Bits 2-7: Reserved */
#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag (WCF) */
#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag (FCF) */
#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag (TCF) */
#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag (TEF) */
#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag (REF) */
#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag (DMF) */
/* Bits 14-23: Reserved */
#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag (MBF) */
/* Bits 25-31: Reserved */
/* Interrupt Enable Register (IER) */
#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */
#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */
/* Bits 2-7: Reserved */
#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable (WCIE) */
#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable (FCIE) */
#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable (TCIE) */
#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable (TEIE) */
#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable (REIE) */
#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable (DMIE) */
/* Bits 14-31: Reserved */
/* DMA Enable Register (DER) */
#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */
#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */
/* Bits 2-31: Reserved */
/* Configuration Register 0 (CFGR0) */
#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable (HREN) */
#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity (HRPOL) */
# define LPSPI_CFGR0_HRPOL_HIGH (0 << 1) /* HREQ pin or input trigger is active high */
# define LPSPI_CFGR0_HRPOL_LOW (1 << 1) /* HREQ pin or input trigger is active low */
#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select (HRSEL) */
# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */
# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */
#define LPSPI_CFGR0_HRDIR (1 << 3) /* Bit 3: Host Request Direction (HRDIR) */
# define LPSPI_CFGR0_HRDIR_INPUT (0 << 3) /* HREQ pin is configured as input */
# define LPSPI_CFGR0_HRDIR_OUTPUT (1 << 3) /* HREQ pin is configured as output */
/* Bits 4-7: Reserved */
#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bit 8: Circular FIFO Enable (CIRCFIFO) */
#define LPSPI_CFGR0_RDMO (1 << 9) /* Bit 9: Receive Data Match Only (RDMO) */
# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* Received data is stored in the receive FIFO as in normal operations */
# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* Received data is discarded unless the Data Match Flag (DMF) is set */
/* Bits 10-31: Reserved */
/* Configuration Register 1 (CFGR1) */
#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode (MASTER) */
#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point (SAMPLE) */
# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */
# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */
#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS (AUTOPCS) */
#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall (NOSTALL) */
#define LPSPI_CFGR1_PARTIAL (1 << 4) /* Bit 4: Partial Enable (PARTIAL) */
/* Bits 5-7: Reserved */
#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-15: Peripheral Chip Select Polarity (PCSPOL) */
#define LPSPI_CFGR1_PCSPOL_MASK (0xff << LPSPI_CFGR1_PCSPOL_SHIFT)
# define LPSPI_CFGR1_PCSPOL_LOW(n) (0 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active low */
# define LPSPI_CFGR1_PCSPOL_HIGH(n) (1 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active high */
#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration (MATCFG) */
#define LPSPI_CFGR1_MATCFG_MASK (0x07 << LPSPI_CFGR1_MATCFG_SHIFT)
#define LPSPI_CFGR1_MATCFG_DIS (0x00 << LPSPI_CFGR1_MATCFG_SHIFT) /* Match is disabled */
/* Bits 19-23: Reserved */
#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration (PINCFG) */
#define LPSPI_CFGR1_PINCFG_MASK (0x03 << LPSPI_CFGR1_PINCFG_SHIFT)
# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0x00 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */
# define LPSPI_CFGR1_PINCFG_SIN_SIN (0x01 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (0x02 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SIN (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */
# define LPSPI_CFGR1_PINCFG(n) ((n) << LPSPI_CFGR1_PINCFG_SHIFT)
#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config (OUTCFG) */
# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */
# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */
#define LPSPI_CFGR1_PCSCFG_SHIFT (27) /* Bits 27-28: Peripheral Chip Select Configuration (PCSCFG) */
#define LPSPI_CFGR1_PCSCFG_MASK (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT)
# define LPSPI_CFGR1_PCSCFG_PCS (0x00 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for chip select function */
# define LPSPI_CFGR1_PCSCFG_4BIT (0x01 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:3] are configured for half-duplex 4-bit transfers */
# define LPSPI_CFGR1_PCSCFG_8BIT (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for half-duplex 4-bit and 8-bit transfers */
/* Bits 29-31: Reserved */
/* Data Match Register 0 (DMR0) */
#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value (MATCH0) */
#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT)
/* Data Match Register 0 (DMR1) */
#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value (MATCH1) */
#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT)
/* Clock Configuration Register (CCR) */
#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider (SCKDIV) */
#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT)
# define LPSPI_CCR_SCKDIV(n) (((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers (DBT) */
#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT)
# define LPSPI_CCR_DBT(n) (((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay (PCSSCK) */
#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT)
# define LPSPI_CCR_PCSSCK(n) (((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay (SCKPCS) */
#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT)
# define LPSPI_CCR_SCKPCS(n) (((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT) & LPSPI_CCR_SCKPCS_MASK)
/* Clock Configuration Register 1 (CCR1) */
#define LPSPI_CCR1_SCKSET_SHIFT (0) /* Bits 0-7: SCK Setup (SCKSET) */
#define LPSPI_CCR1_SCKSET_MASK (0xff << LPSPI_CCR1_SCKSET_SHIFT)
#define LPSPI_CCR1_SCKHLD_SHIFT (8) /* Bits 8-15: SCK Hold (SCKHLD) */
#define LPSPI_CCR1_SCKHLD_MASK (0xff << LPSPI_CCR1_SCKHLD_SHIFT)
#define LPSPI_CCR1_PCSPCS_SHIFT (16) /* Bits 16-23: PCS to PCS Delay (PCSPCS) */
#define LPSPI_CCR1_PCSPCS_MASK (0xff << LPSPI_CCR1_PCSPCS_SHIFT)
#define LPSPI_CCR1_SCKSCK_SHIFT (24) /* Bits 24-31: SCK Inter-Frame Delay (SCKSCK) */
#define LPSPI_CCR1_SCKSCK_MASK (0xff << LPSPI_CCR1_SCKSCK_SHIFT)
/* FIFO Control Register (FCR) */
#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-1: Transmit FIFO Watermark (TXWATER) */
#define LPSPI_FCR_TXWATER_MASK (0x03 << LPSPI_FCR_TXWATER_SHIFT)
# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT)
/* Bits 2-15: Reserved */
#define LPSPI_FCR_RXWATER_SHIFT (16) /* Bits 16-17: Receive FIFO Watermark (RXWATER) */
#define LPSPI_FCR_RXWATER_MASK (0x03 << LPSPI_FCR_RXWATER_SHIFT)
# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT)
/* Bits 18-31: Reserved */
/* FIFO Status Register (FSR) */
#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-2: Transmit FIFO Count (TXCOUNT) */
#define LPSPI_FSR_TXCOUNT_MASK (0x07 << LPSPI_FSR_TXCOUNT_SHIFT)
/* Bits 3-15: Reserved */
#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-18: Receive FIFO Count (RXCOUNT) */
#define LPSPI_FSR_RXCOUNT_MASK (0x07 << LPSPI_FSR_RXCOUNT_SHIFT)
/* Bits 19-31: Reserved */
/* Transmit Command Register (TCR) */
#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size (FRAMESZ) */
#define LPSPI_TCR_FRAMESZ_MASK (0x0fff << LPSPI_TCR_FRAMESZ_SHIFT)
# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT)
/* Bits 12-15: Reserved */
#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width (WIDTH) */
#define LPSPI_TCR_WIDTH_MASK (0x03 << LPSPI_TCR_WIDTH_SHIFT)
# define LPSPI_TCR_WIDTH_1BIT (0x00 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */
# define LPSPI_TCR_WIDTH_2BIT (0x01 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */
# define LPSPI_TCR_WIDTH_4BIT (0x02 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */
# define LPSPI_TCR_WIDTH_8BIT (0x03 << LPSPI_TCR_WIDTH_SHIFT) /* 8 bit transfer */
#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask (TXMSK) */
#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask (RXMSK) */
#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command (CONTC) */
#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer (CONT) */
#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap (BYSW) */
#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First (LSBF) */
# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-26: Peripheral Chip Select (PCS) */
#define LPSPI_TCR_PCS_MASK (0x07 << LPSPI_TCR_PCS_SHIFT)
# define LPSPI_TCR_PCS_0 (0x00 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[0] */
# define LPSPI_TCR_PCS_1 (0x01 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[1] */
# define LPSPI_TCR_PCS_2 (0x02 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[2] */
# define LPSPI_TCR_PCS_3 (0x03 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[3] */
# define LPSPI_TCR_PCS_4 (0x04 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[4] */
# define LPSPI_TCR_PCS_5 (0x05 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[5] */
# define LPSPI_TCR_PCS_6 (0x06 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[6] */
# define LPSPI_TCR_PCS_7 (0x07 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[7] */
#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value (PRESCALE) */
#define LPSPI_TCR_PRESCALE_MASK (0x07 << LPSPI_TCR_PRESCALE_SHIFT)
# define LPSPI_TCR_PRESCALE_DIV1 (0x00 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */
# define LPSPI_TCR_PRESCALE_DIV2 (0x01 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */
# define LPSPI_TCR_PRESCALE_DIV4 (0x02 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */
# define LPSPI_TCR_PRESCALE_DIV8 (0x03 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */
# define LPSPI_TCR_PRESCALE_DIV16 (0x04 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */
# define LPSPI_TCR_PRESCALE_DIV32 (0x05 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */
# define LPSPI_TCR_PRESCALE_DIV64 (0x06 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */
# define LPSPI_TCR_PRESCALE_DIV128 (0x07 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */
# define LPSPI_TCR_PRESCALE(n) ((n) << LPSPI_TCR_PRESCALE_SHIFT)
#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase (CPHA) */
# define LPSPI_TCR_CPHA_CAPTURED (0 << 30) /* Data is captured on the leading edge of SCK and changed on the following edge of SCK */
# define LPSPI_TCR_CPHA_CHANGED (1 << 30) /* Data is changed on the leading edge of SCK and captured on the following edge of SCK */
#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity (CPOL) */
# define LPSPI_TCR_CPOL_LOW (0 << 31) /* The inactive state value of SCK is low */
# define LPSPI_TCR_CPOL_HIGH (1 << 31) /* The inactive state value of SCK is high */
/* Transmit Data Register (TDR) */
#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data (DATA) */
#define LPSPI_TDR_DATA_MASK (0xffffffff << LPSPI_TDR_DATA_SHIFT)
/* Receive Status Register (RSR) */
#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame (SOF) */
#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty (RXEMPTY) */
/* Bits 2-31: Reserved */
/* Receive Data Register (RDR) */
#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */
#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT)
/* Receive Data Read Only Register (RDROR) */
#define LPSPI_RDROR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */
#define LPSPI_RDROR_DATA_MASK (0xffffffff << LPSPI_RDROR_DATA_SHIFT)
/* Transmit Command Burst Register (TCBR) */
#define LPSPI_TCBR_DATA_SHIFT (0) /* Bits 0-31: Command Data (DATA) */
#define LPSPI_TCBR_DATA_MASK (0xffffffff << LPSPI_TCBR_DATA_SHIFT)
/* Transmit Data Burst Register (TDBR) */
#define LPSPI_TDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */
#define LPSPI_TDBR_DATA_MASK (0xffffffff << LPSPI_TDBR_DATA_SHIFT)
/* Receive Data Burst Register (RDBR) */
#define LPSPI_RDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */
#define LPSPI_RDBR_DATA_MASK (0xffffffff << LPSPI_RDBR_DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPSPI_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_lpuart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPUART_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPUART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPUART Register Offsets **************************************************/
#define S32K3XX_LPUART_VERID_OFFSET (0x00) /* Version ID Register (VERID) */
#define S32K3XX_LPUART_PARAM_OFFSET (0x04) /* Parameter Register (PARAM) */
#define S32K3XX_LPUART_GLOBAL_OFFSET (0x08) /* LPUART Global Register (GLOBAL) */
#define S32K3XX_LPUART_PINCFG_OFFSET (0x0c) /* LPUART Pin Configuration Register (PINCFG) */
#define S32K3XX_LPUART_BAUD_OFFSET (0x10) /* LPUART Baud Rate Register (BAUD) */
#define S32K3XX_LPUART_STAT_OFFSET (0x14) /* LPUART Status Register (STAT) */
#define S32K3XX_LPUART_CTRL_OFFSET (0x18) /* LPUART Control Register (CTRL) */
#define S32K3XX_LPUART_DATA_OFFSET (0x1c) /* LPUART Data Register (DATA) */
#define S32K3XX_LPUART_MATCH_OFFSET (0x20) /* LPUART Match Address Register (MATCH) */
#define S32K3XX_LPUART_MODIR_OFFSET (0x24) /* LPUART Modem IrDA Register (MODIR) */
#define S32K3XX_LPUART_FIFO_OFFSET (0x28) /* LPUART FIFO Register (FIFO) */
#define S32K3XX_LPUART_WATER_OFFSET (0x2c) /* LPUART Watermark Register (WATER) */
#define S32K3XX_LPUART_DATARO_OFFSET (0x30) /* Data read-only Register (DATARO) */
/* LPUART Register Addresses ************************************************/
#define S32K3XX_LPUART0_VERID (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART0_PARAM (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART0_GLOBAL (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART0_PINCFG (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART0_BAUD (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART0_STAT (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART0_CTRL (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART0_DATA (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART0_MATCH (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART0_MODIR (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART0_FIFO (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART0_WATER (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART0_DATARO (S32K3XX_LPUART0_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART1_VERID (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART1_PARAM (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART1_GLOBAL (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART1_PINCFG (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART1_BAUD (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART1_STAT (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART1_CTRL (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART1_DATA (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART1_MATCH (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART1_MODIR (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART1_FIFO (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART1_WATER (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART1_DATARO (S32K3XX_LPUART1_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART2_VERID (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART2_PARAM (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART2_GLOBAL (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART2_PINCFG (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART2_BAUD (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART2_STAT (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART2_CTRL (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART2_DATA (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART2_MATCH (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART2_MODIR (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART2_FIFO (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART2_WATER (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART2_DATARO (S32K3XX_LPUART2_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART3_VERID (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART3_PARAM (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART3_GLOBAL (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART3_PINCFG (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART3_BAUD (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART3_STAT (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART3_CTRL (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART3_DATA (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART3_MATCH (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART3_MODIR (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART3_FIFO (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART3_WATER (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART3_DATARO (S32K3XX_LPUART3_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART4_VERID (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART4_PARAM (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART4_GLOBAL (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART4_PINCFG (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART4_BAUD (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART4_STAT (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART4_CTRL (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART4_DATA (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART4_MATCH (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART4_MODIR (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART4_FIFO (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART4_WATER (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART4_DATARO (S32K3XX_LPUART4_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART5_VERID (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART5_PARAM (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART5_GLOBAL (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART5_PINCFG (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART5_BAUD (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART5_STAT (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART5_CTRL (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART5_DATA (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART5_MATCH (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART5_MODIR (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART5_FIFO (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART5_WATER (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART5_DATARO (S32K3XX_LPUART5_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART6_VERID (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART6_PARAM (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART6_GLOBAL (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART6_PINCFG (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART6_BAUD (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART6_STAT (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART6_CTRL (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART6_DATA (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART6_MATCH (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART6_MODIR (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART6_FIFO (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART6_WATER (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART6_DATARO (S32K3XX_LPUART6_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART7_VERID (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART7_PARAM (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART7_GLOBAL (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART7_PINCFG (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART7_BAUD (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART7_STAT (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART7_CTRL (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART7_DATA (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART7_MATCH (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART7_MODIR (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART7_FIFO (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART7_WATER (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART7_DATARO (S32K3XX_LPUART7_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART8_VERID (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART8_PARAM (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART8_GLOBAL (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART8_PINCFG (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART8_BAUD (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART8_STAT (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART8_CTRL (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART8_DATA (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART8_MATCH (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART8_MODIR (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART8_FIFO (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART8_WATER (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART8_DATARO (S32K3XX_LPUART8_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART9_VERID (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART9_PARAM (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART9_GLOBAL (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART9_PINCFG (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART9_BAUD (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART9_STAT (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART9_CTRL (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART9_DATA (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART9_MATCH (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART9_MODIR (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART9_FIFO (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART9_WATER (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART9_DATARO (S32K3XX_LPUART9_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART10_VERID (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART10_PARAM (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART10_GLOBAL (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART10_PINCFG (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART10_BAUD (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART10_STAT (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART10_CTRL (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART10_DATA (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART10_MATCH (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART10_MODIR (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART10_FIFO (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART10_WATER (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART10_DATARO (S32K3XX_LPUART10_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART11_VERID (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART11_PARAM (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART11_GLOBAL (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART11_PINCFG (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART11_BAUD (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART11_STAT (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART11_CTRL (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART11_DATA (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART11_MATCH (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART11_MODIR (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART11_FIFO (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART11_WATER (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART11_DATARO (S32K3XX_LPUART11_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART12_VERID (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART12_PARAM (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART12_GLOBAL (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART12_PINCFG (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART12_BAUD (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART12_STAT (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART12_CTRL (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART12_DATA (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART12_MATCH (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART12_MODIR (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART12_FIFO (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART12_WATER (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART12_DATARO (S32K3XX_LPUART12_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART13_VERID (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART13_PARAM (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART13_GLOBAL (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART13_PINCFG (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART13_BAUD (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART13_STAT (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART13_CTRL (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART13_DATA (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART13_MATCH (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART13_MODIR (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART13_FIFO (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART13_WATER (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART13_DATARO (S32K3XX_LPUART13_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART14_VERID (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART14_PARAM (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART14_GLOBAL (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART14_PINCFG (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART14_BAUD (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART14_STAT (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART14_CTRL (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART14_DATA (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART14_MATCH (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART14_MODIR (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART14_FIFO (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART14_WATER (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART14_DATARO (S32K3XX_LPUART14_BASE + S32K3XX_LPUART_DATARO_OFFSET)
#define S32K3XX_LPUART15_VERID (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_VERID_OFFSET)
#define S32K3XX_LPUART15_PARAM (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_PARAM_OFFSET)
#define S32K3XX_LPUART15_GLOBAL (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_GLOBAL_OFFSET)
#define S32K3XX_LPUART15_PINCFG (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_PINCFG_OFFSET)
#define S32K3XX_LPUART15_BAUD (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_BAUD_OFFSET)
#define S32K3XX_LPUART15_STAT (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_STAT_OFFSET)
#define S32K3XX_LPUART15_CTRL (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_CTRL_OFFSET)
#define S32K3XX_LPUART15_DATA (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_DATA_OFFSET)
#define S32K3XX_LPUART15_MATCH (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_MATCH_OFFSET)
#define S32K3XX_LPUART15_MODIR (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_MODIR_OFFSET)
#define S32K3XX_LPUART15_FIFO (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_FIFO_OFFSET)
#define S32K3XX_LPUART15_WATER (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_WATER_OFFSET)
#define S32K3XX_LPUART15_DATARO (S32K3XX_LPUART15_BASE + S32K3XX_LPUART_DATARO_OFFSET)
/* Register bit definitions *************************************************/
/* Version ID Register (VERID) */
#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number (FEATURE) */
#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT)
# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */
# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */
#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT)
#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT)
#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT)
/* Bits 16-31: Reserved */
/* LPUART Global Register (GLOBAL) */
/* Bit 0: Reserved */
#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bits 2-31: Reserved */
/* LPUART Pin Configuration Register (PINCFG) */
#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select (TRGSEL) */
#define LPUART_PINCFG_TRGSEL_MASK (0x03 << LPUART_PINCFG_TRGSEL_SHIFT)
# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */
# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */
# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */
# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */
/* Bits 2-31: Reserved */
/* LPUART Baud Rate Register (BAUD) */
#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor (SBR) */
#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
# define LPUART_BAUD_SBR(n) ((n) << LPUART_BAUD_SBR_SHIFT)
#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select (SBNS) */
#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable (RXEDGIE) */
#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable (LBKDIE) */
#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable (RESYNCDIS) */
#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling (BOTHEDGE) */
#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration (MATCFG) */
#define LPUART_BAUD_MATCFG_MASK (0x03 << LPUART_BAUD_MATCFG_SHIFT)
# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */
/* Bit 20: Reserved */
#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable (RDMAE) */
/* Bit 22: Reserved */
#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable (TDMAE) */
#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Oversampling Ratio (OSR) */
#define LPUART_BAUD_OSR_MASK (0x0f << LPUART_BAUD_OSR_SHIFT)
# define LPUART_BAUD_OSR(n) (((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */
#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode Select (M10) */
#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 (MAEN2) */
#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 (MAEN1) */
/* LPUART Status Register (STAT) */
#define LPUART_STAT_LBKFE (1 << 0) /* Bit 0: LIN Break Flag Enable (LBKFE) */
#define LPUART_STAT_AME (1 << 1) /* Bit 1: Address Mark Enable (AME) */
/* Bits 2-13: Reserved */
#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag (MA2F) */
#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag (MA1F) */
#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag (PF) */
#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag (FE) */
#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag (NF) */
#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag (OR) */
#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag (IDLE) */
#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag (RDRF) */
#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag (TC) */
#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag (TDRE) */
#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag (RAF) */
#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable (LBKDE) */
#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length (BRK13) */
#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect (RWUID) */
#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion (RXINV) */
#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First (MSBF) */
#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag (RXEDGIF) */
#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag (LBKDIF) */
/* LPUART Control Register (CTRL) */
#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */
# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */
# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */
#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */
#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */
#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */
#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */
#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */
#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */
#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */
#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */
#define LPUART_CTRL_IDLECFG_MASK (0x07 << LPUART_CTRL_IDLECFG_SHIFT)
# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select (M7) */
/* Bits 12-13: Reserved */
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable (MA2IE) */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable (MA1IE) */
#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break (SBK) */
#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control (RWU) */
#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable (RE) */
#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable (TE) */
#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable (ILIE) */
#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable (RIE) */
#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable (TCIE) */
#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable (TIE) */
#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable (PEIE) */
#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable (FEIE) */
#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable (NEIE) */
#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable (ORIE) */
#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion (TXINV) */
#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode (TXDIR) */
#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 (R9T8) */
#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 (R8T9) */
#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \
LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \
LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \
LPUART_CTRL_MA2IE)
/* LPUART Data Register (DATA) */
#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 (DATA)*/
#define LPUART_DATA_MASK (0x03ff << LPUART_DATA_SHIFT)
#define LPUART_DATA_LINBRK (1 << 10) /* Bit 10: LIN Break (LINBRK) */
#define LPUART_DATA_STATUS_SHIFT (11) /* Bits 11-15: Status */
#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line (IDLINE) */
#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty (RXEMPT) */
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character (FRETSC) */
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error (PARITYE) */
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy Data Received (NOISY) */
/* Bits 16-31: Reserved */
/* LPUART Match Address Register (MATCH) */
#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 (MA1) */
#define LPUART_MATCH_MA1_MASK (0x03ff << LPUART_MATCH_MA1_SHIFT)
# define LPUART_MATCH_MA1(n) ((n) << LPUART_MATCH_MA1_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 (MA2) */
#define LPUART_MATCH_MA2_MASK (0x03ff << LPUART_MATCH_MA2_SHIFT)
# define LPUART_MATCH_MA2(n) ((n) << LPUART_MATCH_MA2_SHIFT)
/* Bits 26-31: Reserved */
/* LPUART Modem IrDA Register (MODIR) */
#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable (TXCTSE) */
#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable (TXRTSE) */
#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity (TXRTSPOL) */
#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable (RXRTSE) */
#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration (TXCTSC) */
# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */
# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */
#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source (TXCTSSRC) */
# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* CTS input is CTS_B pin */
# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* CTS input is receiver address match result */
/* Bits 6-7: Reserved */
#define LPUART_MODIR_RTSWATER_SHIFT (8) /* Bits 8-9: Receive RTS Configuration (RTSWATER) */
#define LPUART_MODIR_RTSWATER_MASK (0x03 << LPUART_MODIR_RTSWATER_SHIFT)
# define LPUART_MODIR_RTSWATER(n) ((n) << LPUART_MODIR_RTSWATER_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse (TNP) */
#define LPUART_MODIR_TNP_MASK (0x03 << LPUART_MODIR_TNP_SHIFT)
# define LPUART_MODIR_TNP(n) (((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */
#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable (IREN) */
/* Bits 19-31: Reserved */
/* LPUART FIFO Register (FIFO) */
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO Buffer Depth (RXFIFOSIZE) */
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x07 << LPUART_FIFO_RXFIFOSIZE_SHIFT)
# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 dataword */
# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable (RXFE) */
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO Buffer Depth (TXFIFOSIZE) */
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x07 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 dataword */
# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable (TXFE) */
#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable (RXUFE) */
#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable (TXOFE) */
#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable (RXIDEN) */
#define LPUART_FIFO_RXIDEN_MASK (0x07 << LPUART_FIFO_RXIDEN_SHIFT)
# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */
# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 character */
# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 characters */
# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 characters */
# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 characters */
# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 characters */
# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 characters */
# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 characters */
/* Bit 13: Reserved */
#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO Flush (RXFLUSH) */
#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO Flush (TXFLUSH) */
#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver FIFO Underflow Flag (RXUF) */
#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter FIFO Overflow Flag (TXOF) */
/* Bits 18-21: Reserved */
#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty (RXEMPT) */
#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty (TXEMPT) */
/* Bits 24-31: Reserved */
/* LPUART Watermark Register (WATER) */
#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-1: Transmit Watermark (TXWATER) */
#define LPUART_WATER_TXWATER_MASK (0x03 << LPUART_WATER_TXWATER_SHIFT)
# define LPUART_WATER_TXWATER(n) ((n) << LPUART_WATER_TXWATER_SHIFT)
/* Bits 2-7: Reserved */
#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-10: Transmit Counter (TXCOUNT) */
#define LPUART_WATER_TXCOUNT_MASK (0x07 << LPUART_WATER_TXCOUNT_SHIFT)
# define LPUART_WATER_TXCOUNT(n) ((n) << LPUART_WATER_TXCOUNT_SHIFT)
/* Bits 11-15: Reserved */
#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-17: Receive Watermark (RXWATER) */
#define LPUART_WATER_RXWATER_MASK (0x03 << LPUART_WATER_RXWATER_SHIFT)
# define LPUART_WATER_RXWATER(n) ((n) << LPUART_WATER_RXWATER_SHIFT)
/* Bits 18-23: Reserved */
#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-26: Receive Counter (RXCOUNT) */
#define LPUART_WATER_RXCOUNT_MASK (0x07 << LPUART_WATER_RXCOUNT_SHIFT)
# define LPUART_WATER_RXCOUNT(n) ((n) << LPUART_WATER_RXCOUNT_SHIFT)
/* Bits 27-31: Reserved */
/* Data read-only Register (DATARO) */
#define LPUART_DATARO_DATA_SHIFT (0) /* Bits 0-15: Receive Data (DATA) */
#define LPUART_DATARO_DATA_MASK (0xffff << LPUART_DATARO_DATA_SHIFT)
/* Bits 16-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_LPUART_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_mc_cgm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_CGM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_CGM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MC_CGM Register Offsets **************************************************/
#define S32K3XX_MC_CGM_PCFS_SFDUR_OFFSET (0x0000) /* PCFS Step Duration Register (PCFS_SDUR) */
#define S32K3XX_MC_CGM_PCFS_DIVC8_OFFSET (0x0058) /* PCFS Divider Change 8 Register (PCFS_DIVC8) */
#define S32K3XX_MC_CGM_PCFS_DIVE8_OFFSET (0x005c) /* PCFS Divider End 8 Register (PCFS_DIVE8) */
#define S32K3XX_MC_CGM_PCFS_DIVS8_OFFSET (0x0060) /* PCFS Divider Start 8 Register (PCFS_DIVS8) */
#define S32K3XX_MC_CGM_MUX_0_CSC_OFFSET (0x0300) /* Clock Mux 0 Select Control Register (MUX_0_CSC) */
#define S32K3XX_MC_CGM_MUX_0_CSS_OFFSET (0x0304) /* Clock Mux 0 Select Status Register (MUX_0_CSS) */
#define S32K3XX_MC_CGM_MUX_0_DC_0_OFFSET (0x0308) /* Clock Mux 0 Divider 0 Control Register (MUX_0_DC_0) */
#define S32K3XX_MC_CGM_MUX_0_DC_1_OFFSET (0x030c) /* Clock Mux 0 Divider 1 Control Register (MUX_0_DC_1) */
#define S32K3XX_MC_CGM_MUX_0_DC_2_OFFSET (0x0310) /* Clock Mux 0 Divider 2 Control Register (MUX_0_DC_2) */
#define S32K3XX_MC_CGM_MUX_0_DC_3_OFFSET (0x0314) /* Clock Mux 0 Divider 3 Control Register (MUX_0_DC_3) */
#define S32K3XX_MC_CGM_MUX_0_DC_4_OFFSET (0x0318) /* Clock Mux 0 Divider 4 Control Register (MUX_0_DC_4) */
#define S32K3XX_MC_CGM_MUX_0_DC_5_OFFSET (0x031c) /* Clock Mux 0 Divider 5 Control Register (MUX_0_DC_5) */
#define S32K3XX_MC_CGM_MUX_0_DC_6_OFFSET (0x0320) /* Clock Mux 0 Divider 6 Control Register (MUX_0_DC_6) */
#define S32K3XX_MC_CGM_MUX_0_DIV_TRIG_CTRL_OFFSET (0x0334) /* Clock Mux 0 Divider Trigger Control Register (MUX_0_DIV_TRIG_CTRL) */
#define S32K3XX_MC_CGM_MUX_0_DIV_TRIG_OFFSET (0x0338) /* Clock Mux 0 Divider Trigger Register (MUX_0_DIV_TRIG) */
#define S32K3XX_MC_CGM_MUX_0_DIV_UPD_STAT_OFFSET (0x033c) /* Clock Mux 0 Divider Update Status Register (MUX_0_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_1_CSC_OFFSET (0x0340) /* Clock Mux 1 Select Control Register (MUX_1_CSC) */
#define S32K3XX_MC_CGM_MUX_1_CSS_OFFSET (0x0344) /* Clock Mux 1 Select Status Register (MUX_1_CSS) */
#define S32K3XX_MC_CGM_MUX_1_DC_0_OFFSET (0x0348) /* Clock Mux 1 Divider 0 Control Register (MUX_1_DC_0) */
#define S32K3XX_MC_CGM_MUX_1_DIV_UPD_STAT_OFFSET (0x037c) /* Clock Mux 1 Divider Update Status Register (MUX_1_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_2_CSC_OFFSET (0x0380) /* Clock Mux 2 Select Control Register (MUX_2_CSC) */
#define S32K3XX_MC_CGM_MUX_2_CSS_OFFSET (0x0384) /* Clock Mux 2 Select Status Register (MUX_2_CSS) */
#define S32K3XX_MC_CGM_MUX_2_DC_0_OFFSET (0x0388) /* Clock Mux 2 Divider 0 Control Register (MUX_2_DC_0) */
#define S32K3XX_MC_CGM_MUX_2_DIV_UPD_STAT_OFFSET (0x03bc) /* Clock Mux 2 Divider Update Status Register (MUX_2_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_3_CSC_OFFSET (0x03c0) /* Clock Mux 3 Select Control Register (MUX_3_CSC) */
#define S32K3XX_MC_CGM_MUX_3_CSS_OFFSET (0x03c4) /* Clock Mux 3 Select Status Register (MUX_3_CSS) */
#define S32K3XX_MC_CGM_MUX_3_DC_0_OFFSET (0x03c8) /* Clock Mux 3 Divider 0 Control Register (MUX_3_DC_0) */
#define S32K3XX_MC_CGM_MUX_3_DIV_UPD_STAT_OFFSET (0x03fc) /* Clock Mux 3 Divider Update Status Register (MUX_3_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_4_CSC_OFFSET (0x0400) /* Clock Mux 4 Select Control Register (MUX_4_CSC) */
#define S32K3XX_MC_CGM_MUX_4_CSS_OFFSET (0x0404) /* Clock Mux 4 Select Status Register (MUX_4_CSS) */
#define S32K3XX_MC_CGM_MUX_4_DC_0_OFFSET (0x0408) /* Clock Mux 4 Divider 0 Control Register (MUX_4_DC_0) */
#define S32K3XX_MC_CGM_MUX_4_DIV_UPD_STAT_OFFSET (0x043c) /* Clock Mux 4 Divider Update Status Register (MUX_4_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_5_CSC_OFFSET (0x0440) /* Clock Mux 5 Select Control Register (MUX_5_CSC) */
#define S32K3XX_MC_CGM_MUX_5_CSS_OFFSET (0x0444) /* Clock Mux 5 Select Status Register (MUX_5_CSS) */
#define S32K3XX_MC_CGM_MUX_5_DC_0_OFFSET (0x0448) /* Clock Mux 5 Divider 0 Control Register (MUX_5_DC_0) */
#define S32K3XX_MC_CGM_MUX_5_DIV_UPD_STAT_OFFSET (0x047c) /* Clock Mux 5 Divider Update Status Register (MUX_5_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_6_CSC_OFFSET (0x0480) /* Clock Mux 6 Select Control Register (MUX_6_CSC) */
#define S32K3XX_MC_CGM_MUX_6_CSS_OFFSET (0x0484) /* Clock Mux 6 Select Status Register (MUX_6_CSS) */
#define S32K3XX_MC_CGM_MUX_6_DC_0_OFFSET (0x0488) /* Clock Mux 6 Divider 0 Control Register (MUX_6_DC_0) */
#define S32K3XX_MC_CGM_MUX_6_DIV_UPD_STAT_OFFSET (0x04bc) /* Clock Mux 6 Divider Update Status Register (MUX_6_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_7_CSC_OFFSET (0x04c0) /* Clock Mux 7 Select Control Register (MUX_7_CSC) */
#define S32K3XX_MC_CGM_MUX_7_CSS_OFFSET (0x04c4) /* Clock Mux 7 Select Status Register (MUX_7_CSS) */
#define S32K3XX_MC_CGM_MUX_7_DC_0_OFFSET (0x04c8) /* Clock Mux 7 Divider 0 Control Register (MUX_7_DC_0) */
#define S32K3XX_MC_CGM_MUX_7_DIV_UPD_STAT_OFFSET (0x04fc) /* Clock Mux 7 Divider Update Status Register (MUX_7_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_8_CSC_OFFSET (0x0500) /* Clock Mux 8 Select Control Register (MUX_8_CSC) */
#define S32K3XX_MC_CGM_MUX_8_CSS_OFFSET (0x0504) /* Clock Mux 8 Select Status Register (MUX_8_CSS) */
#define S32K3XX_MC_CGM_MUX_8_DC_0_OFFSET (0x0508) /* Clock Mux 8 Divider 0 Control Register (MUX_8_DC_0) */
#define S32K3XX_MC_CGM_MUX_8_DIV_UPD_STAT_OFFSET (0x053c) /* Clock Mux 8 Divider Update Status Register (MUX_8_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_9_CSC_OFFSET (0x0540) /* Clock Mux 9 Select Control Register (MUX_9_CSC) */
#define S32K3XX_MC_CGM_MUX_9_CSS_OFFSET (0x0544) /* Clock Mux 9 Select Status Register (MUX_9_CSS) */
#define S32K3XX_MC_CGM_MUX_9_DC_0_OFFSET (0x0548) /* Clock Mux 9 Divider 0 Control Register (MUX_9_DC_0) */
#define S32K3XX_MC_CGM_MUX_9_DIV_UPD_STAT_OFFSET (0x057c) /* Clock Mux 9 Divider Update Status Register (MUX_9_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_10_CSC_OFFSET (0x0580) /* Clock Mux 10 Select Control Register (MUX_10_CSC) */
#define S32K3XX_MC_CGM_MUX_10_CSS_OFFSET (0x0584) /* Clock Mux 10 Select Status Register (MUX_10_CSS) */
#define S32K3XX_MC_CGM_MUX_10_DC_0_OFFSET (0x0588) /* Clock Mux 10 Divider 0 Control Register (MUX_10_DC_0) */
#define S32K3XX_MC_CGM_MUX_10_DIV_UPD_STAT_OFFSET (0x05bc) /* Clock Mux 10 Divider Update Status Register (MUX_10_DIV_UPD_STAT) */
#define S32K3XX_MC_CGM_MUX_11_CSC_OFFSET (0x05c0) /* Clock Mux 11 Select Control Register (MUX_11_CSC) */
#define S32K3XX_MC_CGM_MUX_11_CSS_OFFSET (0x05c4) /* Clock Mux 11 Select Status Register (MUX_11_CSS) */
#define S32K3XX_MC_CGM_MUX_11_DC_0_OFFSET (0x05c8) /* Clock Mux 11 Divider 0 Control Register (MUX_11_DC_0) */
#define S32K3XX_MC_CGM_MUX_11_DIV_UPD_STAT_OFFSET (0x05fc) /* Clock Mux 11 Divider Update Status Register (MUX_11_DIV_UPD_STAT) */
/* Relative offset to S32K3XX_MC_CGM_MUX_X_CSC_OFFSET */
#define S32K3XX_MC_CGM_MUX_X_CSC_OFFSET (0x0000) /* Clock Mux X Select Control Register (MUX_X_CSC) */
#define S32K3XX_MC_CGM_MUX_X_CSS_OFFSET (0x0004) /* Clock Mux X Select Status Register (MUX_X_CSS) */
#define S32K3XX_MC_CGM_MUX_X_DC_0_OFFSET (0x0008) /* Clock Mux X Divider 0 Control Register (MUX_X_DC_0) */
#define S32K3XX_MC_CGM_MUX_X_DIV_UPD_STAT_OFFSET (0x003c) /* Clock Mux X Divider Update Status Register (MUX_X_DIV_UPD_STAT) */
/* MC_CGM Register Addresses ************************************************/
#define S32K3XX_MC_CGM_PCFS_SFDUR (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_PCFS_SFDUR_OFFSET)
#define S32K3XX_MC_CGM_PCFS_DIVC8 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_PCFS_DIVC8_OFFSET)
#define S32K3XX_MC_CGM_PCFS_DIVE8 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_PCFS_DIVE8_OFFSET)
#define S32K3XX_MC_CGM_PCFS_DIVS8 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_PCFS_DIVS8_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_1 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_1_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_2 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_2_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_3 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_3_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_4 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_4_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_5 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_5_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DC_6 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DC_6_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DIV_TRIG_CTRL (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DIV_TRIG_CTRL_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DIV_TRIG (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DIV_TRIG_OFFSET)
#define S32K3XX_MC_CGM_MUX_0_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_0_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_1_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_1_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_1_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_1_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_1_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_1_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_1_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_1_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_2_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_2_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_2_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_2_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_2_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_2_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_2_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_2_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_3_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_3_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_3_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_3_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_3_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_3_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_3_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_3_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_4_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_4_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_4_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_4_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_4_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_4_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_4_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_4_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_5_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_5_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_5_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_5_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_5_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_5_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_5_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_5_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_6_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_6_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_6_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_6_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_6_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_6_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_6_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_6_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_7_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_7_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_7_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_7_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_7_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_7_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_7_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_7_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_8_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_8_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_8_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_8_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_8_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_8_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_8_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_8_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_9_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_9_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_9_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_9_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_9_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_9_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_9_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_9_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_10_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_10_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_10_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_10_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_10_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_10_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_10_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_10_DIV_UPD_STAT_OFFSET)
#define S32K3XX_MC_CGM_MUX_11_CSC (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_11_CSC_OFFSET)
#define S32K3XX_MC_CGM_MUX_11_CSS (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_11_CSS_OFFSET)
#define S32K3XX_MC_CGM_MUX_11_DC_0 (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_11_DC_0_OFFSET)
#define S32K3XX_MC_CGM_MUX_11_DIV_UPD_STAT (S32K3XX_MC_CGM_BASE + S32K3XX_MC_CGM_MUX_11_DIV_UPD_STAT_OFFSET)
/* MC_CGM Register Bitfield Definitions *************************************/
/* PCFS Step Duration Register (PCFS_SDUR) */
#define MC_CGM_PCFS_SDUR_SHIFT (0) /* Bits 0-15: Step duration (SDUR) */
#define MC_CGM_PCFS_SDUR_MASK (0xffff << MC_CGM_PCFS_SDUR_SHIFT)
/* Bits 16-31: Reserved */
/* PCFS Divider Change 8 Register (PCFS_DIVC8) */
#define MC_CGM_PCFS_DIVC8_RATE_SHIFT (0) /* Bits 0-7: Divider change rate (RATE) */
#define MC_CGM_PCFS_DIVC8_RATE_MASK (0xff << MC_CGM_PCFS_DIVC8_RATE_SHIFT)
/* Bits 8-15: Reserved */
#define MC_CGM_PCFS_DIVC8_INIT_SHIFT (16) /* Bits 16-31: Divider change initial value (INIT) */
#define MC_CGM_PCFS_DIVC8_INIT_MASK (0xffff << MC_CGM_PCFS_DIVC8_INIT_SHIFT)
/* PCFS Divider End 8 Register (PCFS_DIVE8) */
#define MC_CGM_PCFS_DIVE8_DIVE_SHIFT (0) /* Bits 0-19: Divider end value (DIVE) */
#define MC_CGM_PCFS_DIVE8_DIVE_MASK (0x0fffff << MC_CGM_PCFS_DIVE8_DIVE_SHIFT)
/* Bits 20-31: Reserved */
/* PCFS Divider Start 8 Register (PCFS_DIVS8) */
#define MC_CGM_PCFS_DIVS8_DIVS_SHIFT (0) /* Bits 0-19: Divider start value (DIVS) */
#define MC_CGM_PCFS_DIVS8_DIVS_MASK (0x0fffff << MC_CGM_PCFS_DIVS8_DIVS_SHIFT)
/* Bits 20-31: Reserved */
/* Clock Mux n Divider n Control Register (MC_CGM_MUX_n_DC_n) */
#define MC_CGM_MUX_DC_DE (1 << 31) /* Bit 31: Divider Enable (DE) */
#define MC_CGM_MUX_DC_DIV_SHIFT (16) /* Bit 16-19: Divider (DIV) */
#define MC_CGM_MUX_DC_DIV_MASK (0xf << MC_CGM_MUX_DC_DIV_SHIFT) /* Bit 16-19: Divider (DIV) */
#define MC_CGM_MUX_DC_DIV(n) ((0xf & (n-1)) << MC_CGM_MUX_DC_DIV_SHIFT) /* Bit 16-19: Divider (DIV) */
/* Clock Mux n Select Control Register (MUX_n_CSC) */
#define MC_CGM_MUX_CSC_RAMPUP (1 << 0) /* Bit 0: PCFS ramp-up (RAMPUP) */
#define MC_CGM_MUX_CSC_RAMPDOWN (1 << 1) /* Bit 1: PCFS ramp-down (RAMPDOWN) */
#define MC_CGM_MUX_CSC_CLK_SW (1 << 2) /* Bit 2: Clock switch (CLK_SW) */
#define MC_CGM_MUX_CSC_CG (1 << 2) /* Bit 2: Clock gate (CG) */
#define MC_CGM_MUX_CSC_SAFE_SW (1 << 3) /* Bit 3: Safe clock request (SAFE_SW) */
#define MC_CGM_MUX_CSC_FCG (1 << 3) /* Bit 3: Force clock gate (FCG) */
/* Bits 4-23: Reserved */
#define MC_CGM_MUX_CSC_SELCTL_SHIFT (24) /* Bits 24-29: Clock source selection control (SELCTL) */
#define MC_CGM_MUX_0_CSC_SELCTL_MASK (0x0f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_1_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_2_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_3_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_4_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_5_CSC_SELCTL_MASK (0x3f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_6_CSC_SELCTL_MASK (0x3f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_7_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_8_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_9_CSC_SELCTL_MASK (0x1f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_10_CSC_SELCTL_MASK (0x0f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_11_CSC_SELCTL_MASK (0x0f << MC_CGM_MUX_CSC_SELCTL_SHIFT)
#define MC_CGM_MUX_CSC_SELCTL_FIRC (0x00 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* FIRC */
#define MC_CGM_MUX_CSC_SELCTL_SIRC (0x01 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* SIRC */
#define MC_CGM_MUX_CSC_SELCTL_FXOSC (0x02 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* FXOSC */
#define MC_CGM_MUX_CSC_SELCTL_SXOSC (0x04 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* SXOSC */
#define MC_CGM_MUX_CSC_SELCTL_PLL_PHI0_CLK (0x08 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* PLL_PHI0_CLK */
#define MC_CGM_MUX_CSC_SELCTL_PLL_PHI1_CLK (0x09 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* PLL_PHI1_CLK */
#define MC_CGM_MUX_CSC_SELCTL_CORE_CLK (0x10 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* CORE_CLK */
#define MC_CGM_MUX_CSC_SELCTL_HSE_CLK (0x13 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* HSE_CLK */
#define MC_CGM_MUX_CSC_SELCTL_AIPS_PLAT_CLK (0x16 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* AIPS_PLAT_CLK */
#define MC_CGM_MUX_CSC_SELCTL_AIPS_SLOW_CLK (0x17 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* AIPS_SLOW_CLK */
#define MC_CGM_MUX_CSC_SELCTL_EMAC_RMII_TX_CLK (0x18 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* EMAC_RMII_TX_CLK */
#define MC_CGM_MUX_CSC_SELCTL_EMAC_RX_CLK (0x19 << MC_CGM_MUX_CSC_SELCTL_SHIFT) /* EMAC_RX_CLK */
/* Bits 30-31: Reserved */
/* Clock Mux n Select Status Register (MUX_n_CSS) */
#define MC_CGM_MUX_CSS_RAMPUP (1 << 0) /* Bit 0: PCFS ramp-up (RAMPUP) */
#define MC_CGM_MUX_CSS_RAMPDOWN (1 << 1) /* Bit 1: PCFS ramp-down (RAMPDOWN) */
#define MC_CGM_MUX_CSS_CLK_SW (1 << 2) /* Bit 2: Clock switch (CLK_SW) */
#define MC_CGM_MUX_CSS_SAFE_SW (1 << 3) /* Bit 3: Safe clock request (SAFE_SW) */
/* Bit 4-15: Reserved */
#define MC_CGM_MUX_CSS_SWIP (1 << 16) /* Bit 16: Switch in progress (SWIP) */
#define MC_CGM_MUX_CSS_GRIP (1 << 16) /* Bit 16: Grating request is in progress (GRIP) */
#define MC_CGM_MUX_CSS_SWTRG_SHIFT (17) /* Bits 17-19: Switch trigger cause (SWTRG) */
#define MC_CGM_MUX_CSS_SWTRG_MASK (0x07 << MC_CGM_MUX_CSS_SWTRG_SHIFT)
#define MC_CGM_MUX_CSS_SWTRG_RQS (0x01 << MC_CGM_MUX_CSS_SWTRG_SHIFT) /* Switch after request succeeded */
#define MC_CGM_MUX_CSS_SWTRG_RQFINT (0x02 << MC_CGM_MUX_CSS_SWTRG_SHIFT) /* Switch after the request failed because of an inactive target clock and the current clock is FIRC */
#define MC_CGM_MUX_CSS_SWTRG_RQFINC (0x03 << MC_CGM_MUX_CSS_SWTRG_SHIFT) /* Switch after the request failed because of an inactive current clock and the current clock is FIRC */
#define MC_CGM_MUX_CSS_SWTRG_SCRQ (0x04 << MC_CGM_MUX_CSS_SWTRG_SHIFT) /* Switch to FIRC because of a safe clock request or reset succeeded */
#define MC_CGM_MUX_CSS_SWTRG_SCRQPI (0x05 << MC_CGM_MUX_CSS_SWTRG_SHIFT) /* Switch to FIRC because of a safe clock request or reset succeeded, but the previous current clock source was inactive */
#define MC_CGM_MUX_CSS_CS (1 << 17) /* Bit 17: Clock status (CS) */
/* Bits 20-23: Reserved */
#define MC_CGM_MUX_CSS_SELSTAT_SHIFT (24) /* Bits 24-29: Clock source selection status (SELSTAT) */
#define MC_CGM_MUX_0_CSS_SELSTAT_MASK (0x0f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_1_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_2_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_3_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_4_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_5_CSS_SELSTAT_MASK (0x3f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_6_CSS_SELSTAT_MASK (0x3f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_7_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_8_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_9_CSS_SELSTAT_MASK (0x1f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_10_CSS_SELSTAT_MASK (0x0f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_11_CSS_SELSTAT_MASK (0x0f << MC_CGM_MUX_CSS_SELSTAT_SHIFT)
#define MC_CGM_MUX_CSS_SELSTAT_FIRC (0x00 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* FIRC */
#define MC_CGM_MUX_CSS_SELSTAT_SIRC (0x01 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* SIRC */
#define MC_CGM_MUX_CSS_SELSTAT_FXOSC (0x02 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* FXOSC */
#define MC_CGM_MUX_CSS_SELSTAT_SXOSC (0x04 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* SXOSC */
#define MC_CGM_MUX_CSS_SELSTAT_PLL_PHI0_CLK (0x08 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* PLL_PHI0_CLK */
#define MC_CGM_MUX_CSS_SELSTAT_PLL_PHI1_CLK (0x09 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* PLL_PHI1_CLK */
#define MC_CGM_MUX_CSS_SELSTAT_CORE_CLK (0x10 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* CORE_CLK */
#define MC_CGM_MUX_CSS_SELSTAT_HSE_CLK (0x13 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* HSE_CLK */
#define MC_CGM_MUX_CSC_SELSTAT_AIPS_PLAT_CLK (0x16 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* AIPS_PLAT_CLK */
#define MC_CGM_MUX_CSC_SELSTAT_AIPS_SLOW_CLK (0x17 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* AIPS_SLOW_CLK */
#define MC_CGM_MUX_CSC_SELSTAT_EMAC_RMII_TX_CLK (0x18 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* EMAC_RMII_TX_CLK */
#define MC_CGM_MUX_CSC_SELSTAT_EMAC_RX_CLK (0x19 << MC_CGM_MUX_CSS_SELSTAT_SHIFT) /* EMAC_RX_CLK */
/* Bits 30-31: Reserved */
/* Clock Mux 0 Divider Trigger Control Register (MUX_0_DIV_TRIG_CTRL) */
#define MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL (1 << 0) /* Bit 0: Trigger control (TCTL) */
/* Bits 1-30: Reserved */
#define MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN (31 << 0) /* Bit 31: Halt handshake enable (HHEN) */
/* Clock Mux 0 Divider Trigger Register (MUX_0_DIV_TRIG) */
#define MC_CGM_MUX_0_DIV_TRIG_SHIFT (0) /* Bits 0-31: Trigger for divider update (TRIGGER) */
#define MC_CGM_MUX_0_DIV_TRIG_MASK (0xffffffff << MC_CGM_MUX_0_DIV_TRIG_SHIFT)
/* Clock Mux n Divider Update Status Register (MUX_n_DIV_UPD_STAT) */
#define MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT (1 << 0) /* Bit 0: Divider status for clock mux 0 (DIV_STAT) */
/* Bits 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_CGM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_mc_me.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_ME_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_ME_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MC_ME Register Offsets ***************************************************/
#define S32K3XX_MC_ME_CTL_KEY_OFFSET (0x0000) /* Control Key Register (CTL_KEY) */
#define S32K3XX_MC_ME_MODE_CONF_OFFSET (0x0004) /* Mode Configuration Register (MODE_CONF) */
#define S32K3XX_MC_ME_MODE_UPD_OFFSET (0x0008) /* Mode Update Register (MODE_UPD) */
#define S32K3XX_MC_ME_MODE_STAT_OFFSET (0x000c) /* Mode Status Register (MODE_STAT) */
#define S32K3XX_MC_ME_MAIN_COREID_OFFSET (0x0010) /* Main Core ID Register (MAIN_COREID) */
#define S32K3XX_MC_ME_PRTN0_PCONF_OFFSET (0x0100) /* Partition 0 Process Configuration Register (PRTN0_PCONF) */
#define S32K3XX_MC_ME_PRTN0_PUPD_OFFSET (0x0104) /* Partition 0 Process Update Register (PRTN0_PUPD) */
#define S32K3XX_MC_ME_PRTN0_STAT_OFFSET (0x0108) /* Partition 0 Status Register (PRTN0_STAT) */
#define S32K3XX_MC_ME_PRTN0_COFB1_STAT_OFFSET (0x0114) /* Partition 0 COFB Set 1 Clock Status Register (PRTN0_COFB1_STAT) */
#define S32K3XX_MC_ME_PRTN0_COFB1_CLKEN_OFFSET (0x0134) /* Partition 0 COFB Set 1 Clock Enable Register (PRTN0_COFB1_CLKEN) */
#define S32K3XX_MC_ME_PRTN0_CORE0_PCONF_OFFSET (0x0140) /* Partition 0 Core 0 Process Configuration Register (PRTN0_CORE0_PCONF) */
#define S32K3XX_MC_ME_PRTN0_CORE0_PUPD_OFFSET (0x0144) /* Partition 0 Core 0 Process Update Register (PRTN0_CORE0_PUPD) */
#define S32K3XX_MC_ME_PRTN0_CORE0_STAT_OFFSET (0x0148) /* Partition 0 Core 0 Status Register (PRTN0_CORE0_STAT) */
#define S32K3XX_MC_ME_PRTN0_CORE0_ADDR_OFFSET (0x014c) /* Partition 0 Core 0 Address Register (PRTN0_CORE0_ADDR) */
#define S32K3XX_MC_ME_PRTN0_CORE1_PCONF_OFFSET (0x0160) /* Partition 0 Core 1 Process Configuration Register (PRTN0_CORE1_PCONF) */
#define S32K3XX_MC_ME_PRTN0_CORE1_PUPD_OFFSET (0x0164) /* Partition 0 Core 1 Process Update Register (PRTN0_CORE1_PUPD) */
#define S32K3XX_MC_ME_PRTN0_CORE1_STAT_OFFSET (0x0168) /* Partition 0 Core 1 Status Register (PRTN0_CORE1_STAT) */
#define S32K3XX_MC_ME_PRTN0_CORE1_ADDR_OFFSET (0x016c) /* Partition 0 Core 1 Address Register (PRTN0_CORE1_ADDR) */
#define S32K3XX_MC_ME_PRTN0_CORE2_STAT_OFFSET (0x0188) /* Partition 0 Core 2 Status Register (PRTN0_CORE2_STAT) */
#define S32K3XX_MC_ME_PRTN0_CORE2_ADDR_OFFSET (0x018c) /* Partition 0 Core 2 Address Register (PRTN0_CORE2_ADDR) */
#define S32K3XX_MC_ME_PRTN1_PCONF_OFFSET (0x0300) /* Partition 1 Process Configuration Register (PRTN1_PCONF) */
#define S32K3XX_MC_ME_PRTN1_PUPD_OFFSET (0x0304) /* Partition 1 Process Update Register (PRTN1_PUPD) */
#define S32K3XX_MC_ME_PRTN1_STAT_OFFSET (0x0308) /* Partition 1 Status Register (PRTN1_STAT) */
#define S32K3XX_MC_ME_PRTN1_COFB0_STAT_OFFSET (0x0310) /* Partition 1 COFB Set 0 Clock Status Register (PRTN1_COFB0_STAT) */
#define S32K3XX_MC_ME_PRTN1_COFB1_STAT_OFFSET (0x0314) /* Partition 1 COFB Set 1 Clock Status Register (PRTN1_COFB1_STAT) */
#define S32K3XX_MC_ME_PRTN1_COFB2_STAT_OFFSET (0x0318) /* Partition 1 COFB Set 2 Clock Status Register (PRTN1_COFB2_STAT) */
#define S32K3XX_MC_ME_PRTN1_COFB3_STAT_OFFSET (0x031c) /* Partition 1 COFB Set 3 Clock Status Register (PRTN1_COFB3_STAT) */
#define S32K3XX_MC_ME_PRTN1_COFB0_CLKEN_OFFSET (0x0330) /* Partition 1 COFB Set 0 Clock Enable Register (PRTN1_COFB0_CLKEN) */
#define S32K3XX_MC_ME_PRTN1_COFB1_CLKEN_OFFSET (0x0334) /* Partition 1 COFB Set 1 Clock Enable Register (PRTN1_COFB1_CLKEN) */
#define S32K3XX_MC_ME_PRTN1_COFB2_CLKEN_OFFSET (0x0338) /* Partition 1 COFB Set 2 Clock Enable Register (PRTN1_COFB2_CLKEN) */
#define S32K3XX_MC_ME_PRTN1_COFB3_CLKEN_OFFSET (0x033c) /* Partition 1 COFB Set 3 Clock Enable Register (PRTN1_COFB3_CLKEN) */
#define S32K3XX_MC_ME_PRTN2_PCONF_OFFSET (0x0500) /* Partition 2 Process Configuration Register (PRTN2_PCONF) */
#define S32K3XX_MC_ME_PRTN2_PUPD_OFFSET (0x0504) /* Partition 2 Process Update Register (PRTN2_PUPD) */
#define S32K3XX_MC_ME_PRTN2_STAT_OFFSET (0x0508) /* Partition 2 Status Register (PRTN2_STAT) */
#define S32K3XX_MC_ME_PRTN2_COFB0_STAT_OFFSET (0x0510) /* Partition 2 COFB Set 0 Clock Status Register (PRTN2_COFB0_STAT) */
#define S32K3XX_MC_ME_PRTN2_COFB1_STAT_OFFSET (0x0514) /* Partition 2 COFB Set 1 Clock Status Register (PRTN2_COFB1_STAT) */
#define S32K3XX_MC_ME_PRTN2_COFB0_CLKEN_OFFSET (0x0530) /* Partition 2 COFB Set 0 Clock Enable Register (PRTN2_COFB0_CLKEN) */
#define S32K3XX_MC_ME_PRTN2_COFB1_CLKEN_OFFSET (0x0534) /* Partition 2 COFB Set 1 Clock Enable Register (PRTN2_COFB1_CLKEN) */
/* MC_ME Register Addresses *************************************************/
#define S32K3XX_MC_ME_CTL_KEY (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_CTL_KEY_OFFSET)
#define S32K3XX_MC_ME_MODE_CONF (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_MODE_CONF_OFFSET)
#define S32K3XX_MC_ME_MODE_UPD (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_MODE_UPD_OFFSET)
#define S32K3XX_MC_ME_MODE_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_MODE_STAT_OFFSET)
#define S32K3XX_MC_ME_MAIN_COREID (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_MAIN_COREID_OFFSET)
#define S32K3XX_MC_ME_PRTN0_PCONF (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_PCONF_OFFSET)
#define S32K3XX_MC_ME_PRTN0_PUPD (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_PUPD_OFFSET)
#define S32K3XX_MC_ME_PRTN0_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN0_COFB1_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_COFB1_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN0_COFB1_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_COFB1_CLKEN_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE0_PCONF (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE0_PCONF_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE0_PUPD (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE0_PUPD_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE0_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE0_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE0_ADDR (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE0_ADDR_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE1_PCONF (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE1_PCONF_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE1_PUPD (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE1_PUPD_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE1_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE1_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE1_ADDR (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE1_ADDR_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE2_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE2_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN0_CORE2_ADDR (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN0_CORE2_ADDR_OFFSET)
#define S32K3XX_MC_ME_PRTN1_PCONF (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_PCONF_OFFSET)
#define S32K3XX_MC_ME_PRTN1_PUPD (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_PUPD_OFFSET)
#define S32K3XX_MC_ME_PRTN1_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB0_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB0_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB1_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB1_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB2_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB2_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB3_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB3_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB0_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB0_CLKEN_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB1_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB1_CLKEN_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB2_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB2_CLKEN_OFFSET)
#define S32K3XX_MC_ME_PRTN1_COFB3_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN1_COFB3_CLKEN_OFFSET)
#define S32K3XX_MC_ME_PRTN2_PCONF (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_PCONF_OFFSET)
#define S32K3XX_MC_ME_PRTN2_PUPD (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_PUPD_OFFSET)
#define S32K3XX_MC_ME_PRTN2_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN2_COFB0_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_COFB0_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN2_COFB1_STAT (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_COFB1_STAT_OFFSET)
#define S32K3XX_MC_ME_PRTN2_COFB0_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_COFB0_CLKEN_OFFSET)
#define S32K3XX_MC_ME_PRTN2_COFB1_CLKEN (S32K3XX_MC_ME_BASE + S32K3XX_MC_ME_PRTN2_COFB1_CLKEN_OFFSET)
/* MC_ME Register Bitfield Definitions **************************************/
/* Control Key Register (CTL_KEY) */
#define MC_ME_CTL_KEY_SHIFT (0) /* Bits 0-15: Control Key (KEY) */
#define MC_ME_CTL_KEY_MASK (0xffff << MC_ME_CTL_KEY_SHIFT)
#define MC_ME_CTL_KEY(n) ((0xffff & (n)) << MC_ME_CTL_KEY_SHIFT)
/* Bits 16-31: Reserved */
/* Mode Configuration Register (MODE_CONF) */
#define MC_ME_MODE_CONF_DEST_RST (1 << 0) /* Bit 0: Destructive reset request (DEST_RST) */
#define MC_ME_MODE_CONF_FUNC_RST (1 << 1) /* Bit 1: Functional reset request (FUNC_RST) */
/* Bits 2-14: Reserved */
#define MC_ME_MODE_CONF_STANDBY (1 << 15) /* Bit 15: Standby request (STANDBY) */
/* Bits 16-31: Reserved */
/* Mode Update Register (MODE_UPD) */
#define MC_ME_MODE_UPD (1 << 0) /* Bit 0: Mode update (MODE_UPD) */
/* Bits 1-31: Reserved */
/* Mode Status Register (MODE_STAT) */
#define MC_ME_MODE_STAT_PREV_MODE (1 << 0) /* Bit 0: Previous mode (PREV_MODE) */
/* Bits 1-31: Reserved */
/* Main Core ID Register (MAIN_COREID) */
#define MC_ME_MAIN_COREID_CIDX_SHIFT (0) /* Bits 0-2: Core index (CIDX) */
#define MC_ME_MAIN_COREID_CIDX_MASK (0x07 << MC_ME_MAIN_COREID_CIDX_SHIFT)
/* Bits 3-7: Reserved */
#define MC_ME_MAIN_COREID_PIDX_SHIFT (8) /* Bits 8-12: Partition index (PIDX) */
#define MC_ME_MAIN_COREID_PIDX_MASK (0x1f << MC_ME_MAIN_COREID_PIDX_SHIFT)
/* Bits 13-31: Reserved */
/* Partition n Process Configuration Register (PRTNn_PCONF) */
#define MC_ME_PRTN_PCONF_PCE (1 << 0) /* Bit 0: Partition clock enable (PCE) */
/* Bits 1-31: Reserved */
/* Partition n Process Update Register (PRTNn_PUPD) */
#define MC_ME_PRTN_PUPD_PCUD (1 << 0) /* Bit 0: Partition clock update (PCUD) */
/* Bits 1-31: Reserved */
/* Partition n Status Register (PRTN_STAT) */
#define MC_ME_PRTN_STAT_PCS (1 << 0) /* Bit 0: Partition clock status (PCS) */
/* Bits 1-31: Reserved */
/* Partition 0 COFB Set 1 Clock Status Register (PRTN0_COFB1_STAT) */
#define MC_ME_PRTN0_COFB1_STAT_TRGMUX (1 << 0) /* Bit 0: TRGMUX clock status (BLOCK32) */
#define MC_ME_PRTN0_COFB1_STAT_BCTU (1 << 1) /* Bit 1: BCTU clock status (BLOCK33) */
#define MC_ME_PRTN0_COFB1_STAT_EMIOS0 (1 << 2) /* Bit 2: EMIOS0 clock status (BLOCK34) */
#define MC_ME_PRTN0_COFB1_STAT_EMIOS1 (1 << 3) /* Bit 3: EMIOS1 clock status (BLOCK35) */
#define MC_ME_PRTN0_COFB1_STAT_EMIOS2 (1 << 4) /* Bit 4: EMIOS2 clock status (BLOCK36) */
/* Bit 5: Reserved */
#define MC_ME_PRTN0_COFB1_STAT_LCU0 (1 << 6) /* Bit 6: LCU0 clock status (BLOCK38) */
#define MC_ME_PRTN0_COFB1_STAT_LCU1 (1 << 7) /* Bit 7: LCU1 clock status (BLOCK39) */
#define MC_ME_PRTN0_COFB1_STAT_ADC0 (1 << 8) /* Bit 8: ADC0 clock status (BLOCK40) */
#define MC_ME_PRTN0_COFB1_STAT_ADC1 (1 << 9) /* Bit 9: ADC1 clock status (BLOCK41) */
#define MC_ME_PRTN0_COFB1_STAT_ADC2 (1 << 10) /* Bit 10: ADC2 clock status (BLOCK42) */
/* Bit 11: Reserved */
#define MC_ME_PRTN0_COFB1_STAT_PIT0 (1 << 12) /* Bit 12: PIT0 clock status (BLOCK44) */
#define MC_ME_PRTN0_COFB1_STAT_PIT1 (1 << 13) /* Bit 13: PIT1 clock status (BLOCK45) */
#define MC_ME_PRTN0_COFB1_STAT_MU2_MUA (1 << 14) /* Bit 14: MU2_MUA clock status (BLOCK46) */
#define MC_ME_PRTN0_COFB1_STAT_MU2_MUB (1 << 15) /* Bit 15: MU2_MUB clock status (BLOCK47) */
/* Bits 16-31: Reserved */
/* Partition 0 COFB Set 1 Clock Enable Register (PRTN0_COFB1_CLKEN) */
#define MC_ME_PRTN0_COFB1_CLKEN_TRGMUX (1 << 0) /* Bit 0: TRGMUX clock enable (REQ32) */
#define MC_ME_PRTN0_COFB1_CLKEN_BCTU (1 << 1) /* Bit 1: BCTU clock enable (REQ33) */
#define MC_ME_PRTN0_COFB1_CLKEN_EMIOS0 (1 << 2) /* Bit 2: EMIOS0 clock enable (REQ34) */
#define MC_ME_PRTN0_COFB1_CLKEN_EMIOS1 (1 << 3) /* Bit 3: EMIOS1 clock enable (REQ35) */
#define MC_ME_PRTN0_COFB1_CLKEN_EMIOS2 (1 << 4) /* Bit 4: EMIOS2 clock enable (REQ36) */
/* Bit 5: Reserved */
#define MC_ME_PRTN0_COFB1_CLKEN_LCU0 (1 << 6) /* Bit 6: LCU0 clock enable (REQ38) */
#define MC_ME_PRTN0_COFB1_CLKEN_LCU1 (1 << 7) /* Bit 7: LCU1 clock enable (REQ39) */
#define MC_ME_PRTN0_COFB1_CLKEN_ADC0 (1 << 8) /* Bit 8: ADC0 clock enable (REQ40) */
#define MC_ME_PRTN0_COFB1_CLKEN_ADC1 (1 << 9) /* Bit 9: ADC1 clock enable (REQ41) */
#define MC_ME_PRTN0_COFB1_CLKEN_ADC2 (1 << 10) /* Bit 10: ADC2 clock enable (REQ42) */
/* Bit 11: Reserved */
#define MC_ME_PRTN0_COFB1_CLKEN_PIT0 (1 << 12) /* Bit 12: PIT0 clock enable (REQ44) */
#define MC_ME_PRTN0_COFB1_CLKEN_PIT1 (1 << 13) /* Bit 13: PIT1 clock enable (REQ45) */
#define MC_ME_PRTN0_COFB1_CLKEN_MU2_MUA (1 << 14) /* Bit 14: MU2_MUA clock enable (REQ46) */
#define MC_ME_PRTN0_COFB1_CLKEN_MU2_MUB (1 << 15) /* Bit 15: MU2_MUB clock enable (REQ47) */
#define MC_ME_PRTN0_COFB1_CLKEN_I3C (1 << 16) /* Bit 16: I3C clock enable (REQ48) */
/* Bits 17-31: Reserved */
/* Partition 0 Core n Process Configuration Register (PRTN0_COREn_PCONF) */
#define MC_ME_PRTN0_CORE_PCONF (1 << 0) /* Bit 0: Core n clock enable (CCE) */
/* Bits 1-31: Reserved */
/* Partition 0 Core n Process Update Register (PRTN0_COREn_PUPD) */
#define MC_ME_PRTN0_CORE_PUPD (1 << 0) /* Bit 0: Core n clock update (CCUPD) */
/* Bits 1-31: Reserved */
/* Partition 0 Core n Status Register (PRTN0_COREn_STAT) */
#define MC_ME_PRTN0_CORE_STAT (1 << 0) /* Bit 0: Core n clock process status (CCS) */
/* Bits 1-30: Reserved */
#define MC_ME_PRTN0_CORE_WFI (1 << 31) /* Bit 31: Wait for interrupt status (WFI) */
/* Partition 0 Core n Address Register (PRTN0_COREn_ADDR) */
/* Bits 0-1: Reserved */
#define MC_ME_PRTN0_CORE_ADDR_SHIFT (2) /* Bits 2-31: Address (ADDR) */
#define MC_ME_PRTN0_CORE_ADDR_MASK (0x3fffffff << MC_ME_PRTN0_CORE0_ADDR_SHIFT)
/* Partition 1 COFB Set 0 Clock Status Register (PRTN1_COFB0_STAT) */
#define MC_ME_PRTN1_COFB0_STAT_AXBS (1 << 0) /* Bit 0: AXBS clock status (BLOCK0) */
#define MC_ME_PRTN1_COFB0_STAT_XBIC0 (1 << 1) /* Bit 1: XBIC clock status (BLOCK1) */
#define MC_ME_PRTN1_COFB0_STAT_XBIC1 (1 << 2) /* Bit 2: XBIC clock status (BLOCK2) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA (1 << 3) /* Bit 3: eDMA clock status (BLOCK3) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD0 (1 << 4) /* Bit 4: eDMA TCD0 clock status (BLOCK4) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD1 (1 << 5) /* Bit 5: eDMA TCD1 clock status (BLOCK5) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD2 (1 << 6) /* Bit 6: eDMA TCD2 clock status (BLOCK6) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD3 (1 << 7) /* Bit 7: eDMA TCD3 clock status (BLOCK7) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD4 (1 << 8) /* Bit 8: eDMA TCD4 clock status (BLOCK8) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD5 (1 << 9) /* Bit 9: eDMA TCD5 clock status (BLOCK9) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD6 (1 << 10) /* Bit 10: eDMA TCD6 clock status (BLOCK10) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD7 (1 << 11) /* Bit 11: eDMA TCD7 clock status (BLOCK11) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD8 (1 << 12) /* Bit 12: eDMA TCD8 clock status (BLOCK12) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD9 (1 << 13) /* Bit 13: eDMA TCD9 clock status (BLOCK13) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD10 (1 << 14) /* Bit 14: eDMA TCD10 clock status (BLOCK14) */
#define MC_ME_PRTN1_COFB0_STAT_EDMA_TCD11 (1 << 15) /* Bit 15: eDMA TCD11 clock status (BLOCK15) */
#define MC_ME_PRTN1_COFB0_STAT_DEBUG_APB0 (1 << 16) /* Bit 16: Debug_APB clock status (BLOCK16) */
#define MC_ME_PRTN1_COFB0_STAT_DEBUG_APB1 (1 << 17) /* Bit 17: Debug_APB clock status (BLOCK17) */
#define MC_ME_PRTN1_COFB0_STAT_DEBUG_APB2 (1 << 18) /* Bit 18: Debug_APB clock status (BLOCK18) */
#define MC_ME_PRTN1_COFB0_STAT_DEBUG_APB3 (1 << 19) /* Bit 19: Debug_APB clock status (BLOCK19) */
#define MC_ME_PRTN1_COFB0_STAT_DEBUG_APB4 (1 << 20) /* Bit 20: Debug_APB clock status (BLOCK20) */
#define MC_ME_PRTN1_COFB0_STAT_SDA_AP (1 << 21) /* Bit 21: SDA-AP clock status (BLOCK21) */
#define MC_ME_PRTN1_COFB0_STAT_EIM (1 << 22) /* Bit 22: EIM clock status (BLOCK22) */
#define MC_ME_PRTN1_COFB0_STAT_ERM (1 << 23) /* Bit 23: ERM clock status (BLOCK23) */
#define MC_ME_PRTN1_COFB0_STAT_MSCM (1 << 24) /* Bit 24: MSCM clock status (BLOCK24) */
#define MC_ME_PRTN1_COFB0_STAT_PRAMC0 (1 << 25) /* Bit 25: PRAMC0 clock status (BLOCK25) */
#define MC_ME_PRTN1_COFB0_STAT_PFLASH (1 << 26) /* Bit 26: PFLASH clock status (BLOCK26) */
#define MC_ME_PRTN1_COFB0_STAT_PFASH_ALT (1 << 27) /* Bit 27: PFLASH_alt clock status (BLOCK27) */
#define MC_ME_PRTN1_COFB0_STAT_SWT0 (1 << 28) /* Bit 28: SWT0 clock status (BLOCK28) */
#define MC_ME_PRTN1_COFB0_STAT_STM0 (1 << 29) /* Bit 29: STM0 clock status (BLOCK29) */
#define MC_ME_PRTN1_COFB0_STAT_XRDC (1 << 30) /* Bit 30: XRDC clock status (BLOCK30) */
#define MC_ME_PRTN1_COFB0_STAT_INTM (1 << 31) /* Bit 31: INTM clock status (BLOCK31) */
/* Partition 1 COFB Set 1 Clock Status Register (PRTN1_COFB1_STAT) */
#define MC_ME_PRTN1_COFB1_STAT_DMAMUX0 (1 << 0) /* Bit 0: DMAMUX0 clock status (BLOCK32) */
#define MC_ME_PRTN1_COFB1_STAT_DMAMUX1 (1 << 1) /* Bit 1: DMAMUX1 clock status (BLOCK33) */
#define MC_ME_PRTN1_COFB1_STAT_RTC (1 << 2) /* Bit 2: RTC clock status (BLOCK34) */
#define MC_ME_PRTN1_COFB1_STAT_MC_RGM (1 << 3) /* Bit 3: MC_RGM clock status (BLOCK35) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC0_HSE0 (1 << 4) /* Bit 4: SIUL_VIRTWRAPPER_PDAC0_HSE clock status (BLOCK36) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC0_HSE1 (1 << 5) /* Bit 5: SIUL_VIRTWRAPPER_PDAC0_HSE clock status (BLOCK37) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC1_M7_0_0 (1 << 6) /* Bit 6: SIUL_VIRTWRAPPER_PDAC1_M7_0 clock status (BLOCK38) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC1_M7_0_1 (1 << 7) /* Bit 7: SIUL_VIRTWRAPPER_PDAC1_M7_0 clock status (BLOCK39) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC2_M7_1_0 (1 << 8) /* Bit 8: SIUL_VIRTWRAPPER_PDAC2_M7_1 clock status (BLOCK40) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC2_M7_1_1 (1 << 9) /* Bit 9: SIUL_VIRTWRAPPER_PDAC2_M7_1 clock status (BLOCK41) */
#define MC_ME_PRTN1_COFB1_STAT_SIUL_VIRTWRAPPER_PDAC3 (1 << 10) /* Bit 10: SIUL_VIRTWRAPPER_PDAC3 clock status (BLOCK42) */
#define MC_ME_PRTN1_COFB1_STAT_DCM (1 << 11) /* Bit 11: DCM clock status (BLOCK43) */
/* Bit 12: Reserved */
#define MC_ME_PRTN1_COFB1_STAT_WKPU (1 << 13) /* Bit 13: WKPU clock status (BLOCK45) */
/* Bit 14: Reserved */
#define MC_ME_PRTN1_COFB1_STAT_CMU (1 << 15) /* Bit 15: CMU0-5 clock status (BLOCK47) */
/* Bit 16: Reserved */
#define MC_ME_PRTN1_COFB1_STAT_TSPC (1 << 17) /* Bit 17: TSPC clock status (BLOCK49) */
#define MC_ME_PRTN1_COFB1_STAT_SIRC (1 << 18) /* Bit 18: SIRC clock status (BLOCK50) */
#define MC_ME_PRTN1_COFB1_STAT_SXOSC (1 << 19) /* Bit 19: SXOSC clock status (BLOCK51) */
#define MC_ME_PRTN1_COFB1_STAT_FIRC (1 << 20) /* Bit 20: FIRC clock status (BLOCK52) */
#define MC_ME_PRTN1_COFB1_STAT_FXOSC (1 << 21) /* Bit 21: FXOSC clock status (BLOCK53) */
#define MC_ME_PRTN1_COFB1_STAT_MC_CGM (1 << 22) /* Bit 22: MC_CGM clock status (BLOCK54) */
#define MC_ME_PRTN1_COFB1_STAT_MC_ME (1 << 23) /* Bit 23: MC_ME clock status (BLOCK55) */
#define MC_ME_PRTN1_COFB1_STAT_PLL (1 << 24) /* Bit 24: PLL clock status (BLOCK56) */
/* Bit 25: Reserved */
#define MC_ME_PRTN1_COFB1_STAT_PMC (1 << 26) /* Bit 26: PMC clock status (BLOCK58) */
#define MC_ME_PRTN1_COFB1_STAT_FMU (1 << 27) /* Bit 27: FMU clock status (BLOCK59) */
#define MC_ME_PRTN1_COFB1_STAT_FMU_ALT (1 << 28) /* Bit 28: FMU_alt clock status (BLOCK60) */
/* Bits 29-30: Reserved */
#define MC_ME_PRTN1_COFB1_STAT_PIT2 (1 << 31) /* Bit 31: PIT2 clock status (BLOCK63) */
/* Partition 1 COFB Set 2 Clock Status Register (PRTN1_COFB2_STAT) */
/* Bit 0: Reserved */
#define MC_ME_PRTN1_COFB2_STAT_FLEXCAN0 (1 << 1) /* Bit 1: FlexCAN0 clock status (BLOCK65) */
#define MC_ME_PRTN1_COFB2_STAT_FLEXCAN1 (1 << 2) /* Bit 2: FlexCAN1 clock status (BLOCK66) */
#define MC_ME_PRTN1_COFB2_STAT_FLEXCAN2 (1 << 3) /* Bit 3: FlexCAN2 clock status (BLOCK67) */
#define MC_ME_PRTN1_COFB2_STAT_FLEXCAN3 (1 << 4) /* Bit 4: FlexCAN3 clock status (BLOCK68) */
#define MC_ME_PRTN1_COFB2_STAT_FLEXCAN4 (1 << 5) /* Bit 5: FlexCAN4 clock status (BLOCK69) */
#define MC_ME_PRTN1_COFB2_STAT_FLEXCAN5 (1 << 6) /* Bit 6: FlexCAN5 clock status (BLOCK70) */
/* Bits 7-8: Reserved */
#define MC_ME_PRTN1_COFB2_STAT_FLEXIO (1 << 9) /* Bit 9: FlexIO clock status (BLOCK73) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART0 (1 << 10) /* Bit 10: LPUART0 clock status (BLOCK74) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART1 (1 << 11) /* Bit 11: LPUART1 clock status (BLOCK75) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART2 (1 << 12) /* Bit 12: LPUART2 clock status (BLOCK76) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART3 (1 << 13) /* Bit 13: LPUART3 clock status (BLOCK77) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART4 (1 << 14) /* Bit 14: LPUART4 clock status (BLOCK78) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART5 (1 << 15) /* Bit 15: LPUART5 clock status (BLOCK79) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART6 (1 << 16) /* Bit 16: LPUART6 clock status (BLOCK80) */
#define MC_ME_PRTN1_COFB2_STAT_LPUART7 (1 << 17) /* Bit 17: LPUART7 clock status (BLOCK81) */
/* Bits 18-19: Reserved */
#define MC_ME_PRTN1_COFB2_STAT_LPI2C0 (1 << 20) /* Bit 20: LPI2C0 clock status (BLOCK84) */
#define MC_ME_PRTN1_COFB2_STAT_LPI2C1 (1 << 21) /* Bit 21: LPI2C1 clock status (BLOCK85) */
#define MC_ME_PRTN1_COFB2_STAT_LPSPI0 (1 << 22) /* Bit 22: LPSPI0 clock status (BLOCK86) */
#define MC_ME_PRTN1_COFB2_STAT_LPSPI1 (1 << 23) /* Bit 23: LPSPI1 clock status (BLOCK87) */
#define MC_ME_PRTN1_COFB2_STAT_LPSPI2 (1 << 24) /* Bit 24: LPSPI2 clock status (BLOCK88) */
#define MC_ME_PRTN1_COFB2_STAT_LPSPI3 (1 << 25) /* Bit 25: LPSPI3 clock status (BLOCK89) */
/* Bit 26: Reserved */
#define MC_ME_PRTN1_COFB2_STAT_SAI0 (1 << 27) /* Bit 27: SAI0 clock status (BLOCK91) */
#define MC_ME_PRTN1_COFB2_STAT_LPCMP0 (1 << 28) /* Bit 28: LPCMP0 clock status (BLOCK92) */
#define MC_ME_PRTN1_COFB2_STAT_LPCMP1 (1 << 29) /* Bit 29: LPCMP1 clock status (BLOCK93) */
/* Bit 30: Reserved */
#define MC_ME_PRTN1_COFB2_STAT_TMU (1 << 31) /* Bit 31: TMU clock status (BLOCK95) */
/* Partition 1 COFB Set 3 Clock Status Register (PRTN1_COFB3_STAT) */
#define MC_ME_PRTN1_COFB3_STAT_CRC (1 << 0) /* Bit 0: CRC clock status (BLOCK96) */
#define MC_ME_PRTN1_COFB3_STAT_FCCU (1 << 1) /* Bit 1: FCCU clock status (BLOCK97) */
#define MC_ME_PRTN1_COFB3_STAT_MTR (1 << 2) /* Bit 2: MTR clock status (BLOCK98) */
#define MC_ME_PRTN1_COFB3_STAT_HSE (1 << 3) /* Bit 3: HSE clock status (BLOCK99) */
/* Bit 4: Reserved */
#define MC_ME_PRTN1_COFB3_STAT_JDC (1 << 5) /* Bit 5: JDC clock status (BLOCK101) */
/* Bit 6: Reserved */
#define MC_ME_PRTN1_COFB3_STAT_CONFIG_GPR (1 << 7) /* Bit 7: CONFIG_GPR clock status (BLOCK103) */
#define MC_ME_PRTN1_COFB3_STAT_STCU2 (1 << 8) /* Bit 8: STCU2 clock status (BLOCK104) */
/* Bits 9-11: Reserved */
#define MC_ME_PRTN1_COFB3_STAT_SELFTEST_GPR (1 << 12) /* Bit 12: SELFTEST_GPR clock status (BLOCK108) */
/* Bits 13-31: Reserved */
/* Partition 1 COFB Set 0 Clock Enable Register (PRTN1_COFB0_CLKEN) */
/* Bits 0-2: Reserved */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA (1 << 3) /* Bit 3: eDMA clock enable (REQ3) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD0 (1 << 4) /* Bit 4: eDMA TCD0 clock enable (REQ4) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD1 (1 << 5) /* Bit 5: eDMA TCD1 clock enable (REQ5) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD2 (1 << 6) /* Bit 6: eDMA TCD2 clock enable (REQ6) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD3 (1 << 7) /* Bit 7: eDMA TCD3 clock enable (REQ7) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD4 (1 << 8) /* Bit 8: eDMA TCD4 clock enable (REQ8) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD5 (1 << 9) /* Bit 9: eDMA TCD5 clock enable (REQ9) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD6 (1 << 10) /* Bit 10: eDMA TCD6 clock enable (REQ10) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD7 (1 << 11) /* Bit 11: eDMA TCD7 clock enable (REQ11) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD8 (1 << 12) /* Bit 12: eDMA TCD8 clock enable (REQ12) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD9 (1 << 13) /* Bit 13: eDMA TCD9 clock enable (REQ13) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD10 (1 << 14) /* Bit 14: eDMA TCD10 clock enable (REQ14) */
#define MC_ME_PRTN1_COFB0_CLKEN_EDMA_TCD11 (1 << 15) /* Bit 15: eDMA TCD11 clock enable (REQ15) */
/* Bits 16-20: Reserved */
#define MC_ME_PRTN1_COFB0_CLKEN_SDA_AP (1 << 21) /* Bit 21: SDA-AP clock enable (REQ21) */
#define MC_ME_PRTN1_COFB0_CLKEN_EIM (1 << 22) /* Bit 22: EIM clock enable (REQ22) */
#define MC_ME_PRTN1_COFB0_CLKEN_ERM (1 << 23) /* Bit 23: ERM clock enable (REQ23) */
#define MC_ME_PRTN1_COFB0_CLKEN_MSCM (1 << 24) /* Bit 24: MSCM clock enable (REQ24) */
/* Bits 25-27: Reserved */
#define MC_ME_PRTN1_COFB0_CLKEN_SWT0 (1 << 28) /* Bit 28: SWT0 clock enable (REQ28) */
#define MC_ME_PRTN1_COFB0_CLKEN_STM0 (1 << 29) /* Bit 29: STM0 clock enable (REQ29) */
/* Bit 30: Reserved */
#define MC_ME_PRTN1_COFB0_CLKEN_INTM (1 << 31) /* Bit 31: INTM clock enable (REQ31) */
/* Partition 1 COFB Set 1 Clock Enable Register (PRTN1_COFB1_CLKEN) */
#define MC_ME_PRTN1_COFB1_CLKEN_DMAMUX0 (1 << 0) /* Bit 0: DMAMUX0 clock enable (REQ32) */
#define MC_ME_PRTN1_COFB1_CLKEN_DMAMUX1 (1 << 1) /* Bit 1: DMAMUX1 clock enable (REQ33) */
#define MC_ME_PRTN1_COFB1_CLKEN_RTC (1 << 2) /* Bit 2: RTC clock enable (REQ34) */
/* Bits 3-9: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_SIUL_VIRTWRAPPER_PDAC3 (1 << 10) /* Bit 10: SIUL_VIRTWRAPPER_PDAC3 clock enable (REQ42) */
/* Bits 11-12: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_WKPU (1 << 13) /* Bit 13: WKPU clock enable (REQ45) */
/* Bit 14: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_CMU (1 << 15) /* Bit 15: CMU0-5 clock enable (REQ47) */
/* Bit 16: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_TSPC (1 << 17) /* Bit 17: TSPC clock enable (REQ49) */
/* Bit 18: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_SXOSC (1 << 19) /* Bit 19: SXOSC clock enable (REQ51) */
/* Bit 20: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_FXOSC (1 << 21) /* Bit 21: FXOSC clock enable (REQ53) */
/* Bits 22-23: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_PLL (1 << 24) /* Bit 24: PLL clock enable (REQ56) */
/* BIts 25-30: Reserved */
#define MC_ME_PRTN1_COFB1_CLKEN_PIT2 (1 << 31) /* Bit 31: PIT2 clock enable (REQ63) */
/* Partition 1 COFB Set 2 Clock Enable Register (PRTN1_COFB2_CLKEN) */
/* Bit 0: Reserved */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXCAN0 (1 << 1) /* Bit 1: FlexCAN0 clock enable (REQ65) */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXCAN1 (1 << 2) /* Bit 2: FlexCAN1 clock enable (REQ66) */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXCAN2 (1 << 3) /* Bit 3: FlexCAN2 clock enable (REQ67) */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXCAN3 (1 << 4) /* Bit 4: FlexCAN3 clock enable (REQ68) */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXCAN4 (1 << 5) /* Bit 5: FlexCAN4 clock enable (REQ69) */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXCAN5 (1 << 6) /* Bit 6: FlexCAN5 clock enable (REQ70) */
/* Bits 7-8: Reserved */
#define MC_ME_PRTN1_COFB2_CLKEN_FLEXIO (1 << 9) /* Bit 9: FlexIO clock enable (REQ73) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART0 (1 << 10) /* Bit 10: LPUART0 clock enable (REQ74) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART1 (1 << 11) /* Bit 11: LPUART1 clock enable (REQ75) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART2 (1 << 12) /* Bit 12: LPUART2 clock enable (REQ76) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART3 (1 << 13) /* Bit 13: LPUART3 clock enable (REQ77) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART4 (1 << 14) /* Bit 14: LPUART4 clock enable (REQ78) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART5 (1 << 15) /* Bit 15: LPUART5 clock enable (REQ79) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART6 (1 << 16) /* Bit 16: LPUART6 clock enable (REQ80) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPUART7 (1 << 17) /* Bit 17: LPUART7 clock enable (REQ81) */
/* Bits 18-19: Reserved */
#define MC_ME_PRTN1_COFB2_CLKEN_LPI2C0 (1 << 20) /* Bit 20: LPI2C0 clock enable (REQ84) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPI2C1 (1 << 21) /* Bit 21: LPI2C1 clock enable (REQ85) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPSPI0 (1 << 22) /* Bit 22: LPSPI0 clock enable (REQ86) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPSPI1 (1 << 23) /* Bit 23: LPSPI1 clock enable (REQ87) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPSPI2 (1 << 24) /* Bit 24: LPSPI2 clock enable (REQ88) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPSPI3 (1 << 25) /* Bit 25: LPSPI3 clock enable (REQ89) */
/* Bit 26: Reserved */
#define MC_ME_PRTN1_COFB2_CLKEN_SAI0 (1 << 27) /* Bit 27: SAI0 clock enable (REQ91) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPCMP0 (1 << 28) /* Bit 28: LPCMP0 clock enable (REQ92) */
#define MC_ME_PRTN1_COFB2_CLKEN_LPCMP1 (1 << 29) /* Bit 29: LPCMP1 clock enable (REQ93) */
/* Bit 30: Reserved */
#define MC_ME_PRTN1_COFB2_CLKEN_TMU (1 << 31) /* Bit 31: TMU clock enable (REQ95) */
/* Partition 1 COFB Set 3 Clock Enable Register (PRTN1_COFB3_CLKEN) */
#define MC_ME_PRTN1_COFB3_CLKEN_CRC (1 << 0) /* Bit 0: CRC clock enable (REQ96) */
/* Bits 1-7: Reserved */
#define MC_ME_PRTN1_COFB3_CLKEN_STCU2 (1 << 8) /* Bit 8: STCU2 clock enable (REQ104) */
/* Bits 9-31: Reserved */
/* Partition 2 COFB Set 0 Clock Status Register (PRTN2_COFB0_STAT) */
#define MC_ME_PRTN2_COFB0_STAT_XBIC2 (1 << 0) /* Bit 0: XBIC2 clock status (BLOCK0) */
#define MC_ME_PRTN2_COFB0_STAT_XBIC3 (1 << 1) /* Bit 1: XBIC3 clock status (BLOCK1) */
/* Bits 2-3: Reserved */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD12 (1 << 4) /* Bit 4: eDMA TCD12 clock status (BLOCK4) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD13 (1 << 5) /* Bit 5: eDMA TCD13 clock status (BLOCK5) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD14 (1 << 6) /* Bit 6: eDMA TCD14 clock status (BLOCK6) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD15 (1 << 7) /* Bit 7: eDMA TCD15 clock status (BLOCK7) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD16 (1 << 8) /* Bit 8: eDMA TCD16 clock status (BLOCK8) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD17 (1 << 9) /* Bit 9: eDMA TCD17 clock status (BLOCK9) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD18 (1 << 10) /* Bit 10: eDMA TCD18 clock status (BLOCK10) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD19 (1 << 11) /* Bit 11: eDMA TCD19 clock status (BLOCK11) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD20 (1 << 12) /* Bit 12: eDMA TCD20 clock status (BLOCK12) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD21 (1 << 13) /* Bit 13: eDMA TCD21 clock status (BLOCK13) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD22 (1 << 14) /* Bit 14: eDMA TCD22 clock status (BLOCK14) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD23 (1 << 15) /* Bit 15: eDMA TCD23 clock status (BLOCK15) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD24 (1 << 16) /* Bit 16: eDMA TCD24 clock status (BLOCK16) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD25 (1 << 17) /* Bit 17: eDMA TCD25 clock status (BLOCK17) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD26 (1 << 18) /* Bit 18: eDMA TCD26 clock status (BLOCK18) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD27 (1 << 19) /* Bit 19: eDMA TCD27 clock status (BLOCK19) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD28 (1 << 20) /* Bit 20: eDMA TCD28 clock status (BLOCK20) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD29 (1 << 21) /* Bit 21: eDMA TCD29 clock status (BLOCK21) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD30 (1 << 22) /* Bit 22: eDMA TCD30 clock status (BLOCK22) */
#define MC_ME_PRTN2_COFB0_STAT_EDMA_TCD31 (1 << 23) /* Bit 23: eDMA TCD31 clock status (BLOCK23) */
#define MC_ME_PRTN2_COFB0_STAT_SEMA42 (1 << 24) /* Bit 24: SEMA42 clock status (BLOCK24) */
#define MC_ME_PRTN2_COFB0_STAT_PRAMC1 (1 << 25) /* Bit 25: PRAMC1 clock status (BLOCK25) */
/* Bit 26: Reserved */
#define MC_ME_PRTN2_COFB0_STAT_SWT1 (1 << 27) /* Bit 27: SWT1 clock status (BLOCK27) */
/* Bit 28: Reserved */
#define MC_ME_PRTN2_COFB0_STAT_STM1 (1 << 29) /* Bit 29: STM1 clock status (BLOCK29) */
/* Bit 30-31: Reserved */
/* Partition 2 COFB Set 1 Clock Status Register (PRTN2_COFB1_STAT) */
#define MC_ME_PRTN2_COFB1_STAT_EMAC (1 << 0) /* Bit 0: EMAC clock status (BLOCK32) */
/* Bits 1-2: Reserved */
#define MC_ME_PRTN2_COFB1_STAT_LPUART8 (1 << 3) /* Bit 3: LPUART8 clock status (BLOCK35) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART9 (1 << 4) /* Bit 4: LPUART9 clock status (BLOCK36) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART10 (1 << 5) /* Bit 5: LPUART10 clock status (BLOCK37) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART11 (1 << 6) /* Bit 6: LPUART11 clock status (BLOCK38) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART12 (1 << 7) /* Bit 7: LPUART12 clock status (BLOCK39) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART13 (1 << 8) /* Bit 8: LPUART13 clock status (BLOCK40) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART14 (1 << 9) /* Bit 9: LPUART14 clock status (BLOCK41) */
#define MC_ME_PRTN2_COFB1_STAT_LPUART15 (1 << 10) /* Bit 10: LPUART15 clock status (BLOCK42) */
/* Bits 11-14: Reserved */
#define MC_ME_PRTN2_COFB1_STAT_LPSPI4 (1 << 15) /* Bit 15: LPSPI4 clock status (BLOCK47) */
#define MC_ME_PRTN2_COFB1_STAT_LPSPI5 (1 << 16) /* Bit 16: LPSPI5 clock status (BLOCK48) */
/* Bits 17-18: Reserved */
#define MC_ME_PRTN2_COFB1_STAT_QSPI (1 << 19) /* Bit 19: QuadSPI clock status (BLOCK51) */
/* Bit 20-22: Reserved */
#define MC_ME_PRTN2_COFB1_STAT_SAI1 (1 << 23) /* Bit 23: SAI1 clock status (BLOCK55) */
/* Bits 24-25: Reserved */
#define MC_ME_PRTN2_COFB1_STAT_LCMP2 (1 << 26) /* Bit 26: LPCMP2 clock status (BLOCK58) */
#define MC_ME_PRTN2_COFB1_STAT_HSE (1 << 27) /* Bit 27: HSE clock status (BLOCK59) */
/* Bit 28-29: Reserved */
#define MC_ME_PRTN2_COFB1_STAT_CM7_0_TCM (1 << 30) /* Bit 30: CM7_0_TCM clock status (BLOCK62) */
#define MC_ME_PRTN2_COFB1_STAT_CM7_1_TCM (1 << 31) /* Bit 31: CM7_1_TCM clock status (BLOCK63) */
/* Partition 2 COFB Set 0 Clock Enable Register (PRTN2_COFB0_CLKEN) */
/* Bits 0-3: Reserved */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD12 (1 << 4) /* Bit 4: eDMA TCD12 clock enable (REQ4) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD13 (1 << 5) /* Bit 5: eDMA TCD13 clock enable (REQ5) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD14 (1 << 6) /* Bit 6: eDMA TCD14 clock enable (REQ6) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD15 (1 << 7) /* Bit 7: eDMA TCD15 clock enable (REQ7) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD16 (1 << 8) /* Bit 8: eDMA TCD16 clock enable (REQ8) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD17 (1 << 9) /* Bit 9: eDMA TCD17 clock enable (REQ9) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD18 (1 << 10) /* Bit 10: eDMA TCD18 clock enable (REQ10) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD19 (1 << 11) /* Bit 11: eDMA TCD19 clock enable (REQ11) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD20 (1 << 12) /* Bit 12: eDMA TCD20 clock enable (REQ12) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD21 (1 << 13) /* Bit 13: eDMA TCD21 clock enable (REQ13) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD22 (1 << 14) /* Bit 14: eDMA TCD22 clock enable (REQ14) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD23 (1 << 15) /* Bit 15: eDMA TCD23 clock enable (REQ15) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD24 (1 << 16) /* Bit 16: eDMA TCD24 clock enable (REQ16) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD25 (1 << 17) /* Bit 17: eDMA TCD25 clock enable (REQ17) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD26 (1 << 18) /* Bit 18: eDMA TCD26 clock enable (REQ18) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD27 (1 << 19) /* Bit 19: eDMA TCD27 clock enable (REQ19) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD28 (1 << 20) /* Bit 20: eDMA TCD28 clock enable (REQ20) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD29 (1 << 21) /* Bit 21: eDMA TCD29 clock enable (REQ21) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD30 (1 << 22) /* Bit 22: eDMA TCD30 clock enable (REQ22) */
#define MC_ME_PRTN2_COFB0_CLKEN_EDMA_TCD31 (1 << 23) /* Bit 23: eDMA TCD31 clock enable (REQ23) */
#define MC_ME_PRTN2_COFB0_CLKEN_SEMA42 (1 << 24) /* Bit 24: SEMA42 clock enable (REQ24) */
/* Bits 25-26: Reserved */
#define MC_ME_PRTN2_COFB0_CLKEN_SWT1 (1 << 27) /* Bit 27: SWT1 clock enable (REQ27) */
/* Bit 28: Reserved */
#define MC_ME_PRTN2_COFB0_CLKEN_STM1 (1 << 29) /* Bit 29: STM1 clock enable (REQ29) */
/* Bit 30-31: Reserved */
/* Partition 2 COFB Set 1 Clock Enable Register (PRTN2_COFB1_CLKEN) */
#define MC_ME_PRTN2_COFB1_CLKEN_EMAC (1 << 0) /* Bit 0: EMAC clock enable (REQ32) */
/* Bits 1-2: Reserved */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART8 (1 << 3) /* Bit 3: LPUART8 clock enable (REQ35) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART9 (1 << 4) /* Bit 4: LPUART9 clock enable (REQ36) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART10 (1 << 5) /* Bit 5: LPUART10 clock enable (REQ37) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART11 (1 << 6) /* Bit 6: LPUART11 clock enable (REQ38) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART12 (1 << 7) /* Bit 7: LPUART12 clock enable (REQ39) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART13 (1 << 8) /* Bit 8: LPUART13 clock enable (REQ40) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART14 (1 << 9) /* Bit 9: LPUART14 clock enable (REQ41) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPUART15 (1 << 10) /* Bit 10: LPUART15 clock enable (REQ42) */
/* Bits 11-14: Reserved */
#define MC_ME_PRTN2_COFB1_CLKEN_LPSPI4 (1 << 15) /* Bit 15: LPSPI4 clock enable (REQ47) */
#define MC_ME_PRTN2_COFB1_CLKEN_LPSPI5 (1 << 16) /* Bit 16: LPSPI5 clock enable (REQ48) */
/* Bits 17-18: Reserved */
#define MC_ME_PRTN2_COFB1_CLKEN_QSPI (1 << 19) /* Bit 19: QuadSPI clock enable (REQ51) */
/* Bit 20-22: Reserved */
#define MC_ME_PRTN2_COFB1_CLKEN_SAI1 (1 << 23) /* Bit 23: SAI1 clock enable (REQ55) */
/* Bits 24-25: Reserved */
#define MC_ME_PRTN2_COFB1_CLKEN_LCMP2 (1 << 26) /* Bit 26: LPCMP2 clock enable (REQ58) */
/* Bit 27-29: Reserved */
#define MC_ME_PRTN2_COFB1_CLKEN_CM7_0_TCM (1 << 30) /* Bit 30: CM7_0_TCM clock enable (REQ62) */
#define MC_ME_PRTN2_COFB1_CLKEN_CM7_1_TCM (1 << 31) /* Bit 31: CM7_1_TCM clock enable (REQ63) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_ME_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_RGM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_RGM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MC_RGM Register Offsets **************************************************/
#define S32K3XX_MC_RGM_DES_OFFSET (0x00) /* Destructive Event Status Register (DES) */
#define S32K3XX_MC_RGM_FES_OFFSET (0x08) /* Functional/External Reset Status Register (FES) */
#define S32K3XX_MC_RGM_FERD_OFFSET (0x0c) /* Functional Event Reset Disable Register (FERD) */
#define S32K3XX_MC_RGM_FBRE_OFFSET (0x10) /* Functional Bidirectional Reset Enable Register (FBRE) */
#define S32K3XX_MC_RGM_FREC_OFFSET (0x14) /* Functional Reset Escalation Counter Register (FREC) */
#define S32K3XX_MC_RGM_FRET_OFFSET (0x18) /* Functional Reset Escalation Threshold Register (FRET) */
#define S32K3XX_MC_RGM_DRET_OFFSET (0x1c) /* Destructive Reset Escalation Threshold Register (DRET) */
#define S32K3XX_MC_RGM_ERCTRL_OFFSET (0x20) /* External Reset Control Register (ERCTRL) */
#define S32K3XX_MC_RGM_RDSS_OFFSET (0x24) /* Reset During Standby Status Register (RDSS) */
#define S32K3XX_MC_RGM_FRENTC_OFFSET (0x28) /* Functional Reset Entry Timeout Control Register (FRENTC) */
#define S32K3XX_MC_RGM_LPDEBUG_OFFSET (0x2c) /* Low Power Debug Control Reguster (LPDEBUG) */
/* MC_RGM Register Addresses ************************************************/
#define S32K3XX_MC_RGM_DES (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_DES_OFFSET)
#define S32K3XX_MC_RGM_FES (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_FES_OFFSET)
#define S32K3XX_MC_RGM_FERD (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_FERD_OFFSET)
#define S32K3XX_MC_RGM_FBRE (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_FBRE_OFFSET)
#define S32K3XX_MC_RGM_FREC (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_FREC_OFFSET)
#define S32K3XX_MC_RGM_FRET (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_FRET_OFFSET)
#define S32K3XX_MC_RGM_DRET (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_DRET_OFFSET)
#define S32K3XX_MC_RGM_ERCTRL (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_ERCTRL_OFFSET)
#define S32K3XX_MC_RGM_RDSS (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_RDSS_OFFSET)
#define S32K3XX_MC_RGM_FRENTC (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_FRENTC_OFFSET)
#define S32K3XX_MC_RGM_LPDEBUG (S32K3XX_MC_RGM_BASE + S32K3XX_MC_RGM_LPDEBUG_OFFSET)
/* MC_RGM Register Bitfield Definitions *************************************/
/* Destructive Event Status Register (DES) */
#define MC_RGM_DES_F_POR (1 << 0) /* Bit 0: Flag for power-on reset (F_POR) */
/* Bits 1-2: Reserved */
#define MC_RGM_DES_FCCU_FTR (1 << 3) /* Bit 3: Flag for 'Destructive' Reset FCCU_FTR */
#define MC_RGM_DES_STCU_URF (1 << 4) /* Bit 4: Flag for 'Destructive' Reset STCU_URF */
/* Bit 5: Reserved */
#define MC_RGM_DES_MC_RGM_FRE (1 << 6) /* Bit 6: Flag for 'Destructive' Reset MC_RGM_FRE */
/* Bit 7: Reserved */
#define MC_RGM_DES_FXOSC_FAIL (1 << 8) /* Bit 8: Flag for 'Destructive' Reset FXOSC_FAIL */
#define MC_RGM_DES_PLL_LOL (1 << 9) /* Bit 9: Flag for 'Destructive' Reset PLL_LOL */
#define MC_RGM_DES_CORE_CLK_FAIL (1 << 10) /* Bit 10: Flag for 'Destructive' Reset CORE_CLK_FAIL */
/* Bit 11: Reserved */
#define MC_RGM_DES_AIPS_PLAT_CLK_FAIL (1 << 12) /* Bit 12: Flag for 'Destructive' Reset AIPS_PLAT_CLK_FAIL */
/* Bit 13: Reserved */
#define MC_RGM_DES_HSE_CLK_FAIL (1 << 14) /* Bit 14: Flag for 'Destructive' Reset HSE_CLK_FAIL */
#define MC_RGM_DES_SYS_DIV_FAIL (1 << 15) /* Bit 15: Flag for 'Destructive' Reset SYS_DIV_FAIL */
/* Bit 16: Reserved */
#define MC_RGM_DES_HSE_TMPR_RST (1 << 17) /* Bit 17: Flag for 'Destructive' Reset HSE_TMPR_RST */
#define MC_RGM_DES_HSE_SNVS_RST (1 << 18) /* Bit 18: Flag for 'Destructive' Reset HSE_SNVS_RST */
/* Bits 19-28: Reserved */
#define MC_RGM_DES_SW_DEST (1 << 29) /* Bit 29: Flag for 'Destructive' Reset SW_DEST */
#define MC_RGM_DES_DEBUG_DEST (1 << 30) /* Bit 30: Flag for 'Destructive' Reset DEBUG_DEST */
/* Bit 31: Reserved */
/* Functional/External Reset Status Register (FES) */
#define MC_RGM_FES_F_EXR (1 << 0) /* Bit 0: Flag for External Rest (F_EXR) */
/* Bits 1-2: Reserved */
#define MC_RGM_FES_FCCU_RST (1 << 3) /* Bit 3: Flag for 'Functional' Reset FCCU_RST */
#define MC_RGM_FES_ST_DONE (1 << 4) /* Bit 4: Flag for 'Functional' Reset ST_DONE */
/* Bit 5: Reserved */
#define MC_RGM_FES_SWT0_RST (1 << 6) /* Bit 6: Flag for 'Functional' Reset SWT0_RST */
#define MC_RGM_FES_SWT1_RST (1 << 7) /* Bit 7: Flag for 'Functional' Reset SWT1_RST */
/* Bit 8: Reserved */
#define MC_RGM_FES_JTAG_RST (1 << 9) /* Bit 9: Flag for 'Functional' Reset JTAG_RST */
/* Bits 10-15: Reserved */
#define MC_RGM_FES_HSE_SWT_RST (1 << 16) /* Bit 16: Flag for 'Functional' Reset HSE_SWT_RST */
/* Bits 17-19: Reserved */
#define MC_RGM_FES_HSE_BOOT_RST (1 << 20) /* Bit 20: Flag for 'Functional' Reset HSE_BOOT_RST */
/* Bits 21-28: Reserved */
#define MC_RGM_FES_SW_FUNC (1 << 29) /* Bit 29: Flag for 'Functional' Reset SW_FUNC */
#define MC_RGM_FES_DEBUG_FUNC (1 << 30) /* Bit 30: Flag for 'Functional' Reset DEBUG_FUNC */
/* Bit 31: Reserved */
/* Functional Event Reset Disable Register (FERD) */
/* Bits 0-2: Reserved */
#define MC_RGM_FERD_D_FCCU_RST (1 << 3) /* Bit 3: FCCU_RST Disable Control (D_FCCU_RST) */
/* Bits 4-5: Reserved */
#define MC_RGM_FERD_D_SWT0_RST (1 << 6) /* Bit 6: SWT0_RST Disable Control (D_SWT0_RST) */
#define MC_RGM_FERD_D_SWT1_RST (1 << 7) /* Bit 7: SWT1_RST Disable Control (D_SWT1_RST) */
/* Bit 8: Reserved */
#define MC_RGM_FERD_D_JTAG_RST (1 << 9) /* Bit 9: JTAG_RST Disable Control (D_JTAG_RST) */
/* Bits 10-29: Reserved */
#define MC_RGM_FERD_D_DEBUG_FUNC (1 << 30) /* Bit 30: DEBUG_FUNC Disable Control (D_DEBUG_FUNC) */
/* Bit 31: Reserved */
/* Functional Bidirectional Reset Enable Register (FBRE) */
/* Bits 0-2: Reserved */
#define MC_RGM_FBRE_BE_FCCU_RST (1 << 3) /* Bit 3: Bidirectional Reset Enable for 'Functional' Reset FCCU_RST (BE_FCCU_RST) */
#define MC_RGM_FBRE_BE_ST_DONE (1 << 4) /* Bit 4: Bidirectional Reset Enable for 'Functional' Reset ST_DONE (BE_ST_DONE) */
/* Bit 5: Reserved */
#define MC_RGM_FBRE_BE_SWT0_RST (1 << 6) /* Bit 6: Bidirectional Reset Enable for 'Functional' Reset SWT0_RST (BE_SWT0_RST) */
#define MC_RGM_FBRE_BE_SWT1_RST (1 << 7) /* Bit 7: Bidirectional Reset Enable for 'Functional' Reset SWT1_RST (BE_SWT1_RST) */
/* Bit 8: Reserved */
#define MC_RGM_FBRE_BE_JTAG_RST (1 << 9) /* Bit 9: Bidirectional Reset Enable for 'Functional' Reset JTAG_RST (BE_JTAG_RST) */
/* Bits 10-15: Reserved */
#define MC_RGM_FBRE_BE_HSE_SWT_RST (1 << 16) /* Bit 16: Bidirectional Reset Enable for 'Functional' Reset HSE_SWT_RST (BE_HSE_SWT_RST) */
/* Bits 17-19: Reserved */
#define MC_RGM_FBRE_BE_HSE_BOOT_RST (1 << 20) /* Bit 20: Bidirectional Rest Enable for 'Functional' Reset HSE_BOOT_RST (BE_HSE_BOOT_RST) */
/* Bits 21-28: Reserved */
#define MC_RGM_FBRE_BE_SW_FUNC (1 << 29) /* Bit 29: Bidirectional Rest Enable for 'Functional' Reset SW_FUNC (BE_SW_FUNC) */
#define MC_RGM_FBRE_BE_DEBUG_FUNC (1 << 30) /* Bit 30: Bidirectional Rest Enable for 'Functional' Reset DEBUG_FUNC (BE_DEBUG_FUNC) */
/* Bit 31: Reserved */
/* Functional Reset Escalation Counter Register (FREC) */
#define MC_RGM_FREC_SHIFT (0) /* Bits 0-3: 'Functional' Reset Escalation Counter (FREC) */
#define MC_RGM_FREC_MASK (0x0f << MC_RGM_FREC_SHIFT)
/* Bits 4-31: Reserved */
/* Functional Reset Escalation Threshold Register (FRET) */
#define MC_RGM_FRET_SHIFT (0) /* Bits 0-3: 'Functional' Reset Escalation Threshold (FRET) */
#define MC_RGM_FRET_MASK (0x0f << MC_RGM_FRET_SHIFT)
/* Bits 4-31: Reserved */
/* Destructive Reset Escalation Threshold Register (DRET) */
#define MC_RGM_DRET_SHIFT (0) /* Bits 0-3: 'Destructive' Reset Escalation Threshold (DRET) */
#define MC_RGM_DRET_MASK (0x0f << MC_RGM_DRET_SHIFT)
/* Bits 4-31: Reserved */
/* External Reset Control Register (ERCTRL) */
#define MC_RGM_ERCTRL_ERASSERT (1 << 0) /* Bit 0: External reset is asserted (ERASSERT) */
/* Bits 1-31: Reserved */
/* Reset During Standby Status Register (RDSS) */
#define MC_RGM_RDSS_DES_RES (1 << 0) /* Bit 0: Destructive reset event occured during standby mode (DES_RES) */
#define MC_RGM_RDSS_FES_RES (1 << 1) /* Bit 1: Functional reset event occured during standby mode (FES_RES) */
/* Bits 2-31: Reserved */
/* Functional Reset Entry Timeout Control Register (FRENTC) */
#define MC_RGM_FRENTC_FRET_EN (1 << 0) /* Bit 0: Functional Reset Entry Timer Enable (FRET_EN) */
#define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1) /* Bits 1-31: Functional Reset Entry Timer Value (FRET_TIMEOUT) */
#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)
/* Low Power Debug Control Reguster (LPDEBUG) */
#define MC_RGM_LPDEBUG_LP_DBG_EN (1 << 0) /* Bit 0: Low-Power Debug Enable (LP_DBG_EN) */
/* Bits 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MC_RGM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_mcm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MCM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MCM Register Offsets *****************************************************/
#define S32K3XX_MCM_PLREV_OFFSET (0x0000) /* SoC-defined Platform Revision Register (PLREV) */
#define S32K3XX_MCM_PCT_OFFSET (0x0002) /* Processor Core Type Register (PCT) */
#define S32K3XX_MCM_CPCR_OFFSET (0x000c) /* Core Platform Control Register (CPCR) */
#define S32K3XX_MCM_ISCR_OFFSET (0x0010) /* Interrupt Status and Control Register (ISCR) */
#define S32K3XX_MCM_LMEMDESC0_OFFSET (0x0400) /* Local Memory Descriptor 0 Register (LMEM_DESC_0) */
#define S32K3XX_MCM_LMEMDESC1_OFFSET (0x0404) /* Local Memory Descriptor 1 Register (LMEM_DESC_1) */
#define S32K3XX_MCM_LMEMDESC2_OFFSET (0x0408) /* Local Memory Descriptor 2 Register (LMEM_DESC_2) */
#define S32K3XX_MCM_LMEMDESC3_OFFSET (0x040c) /* Local Memory Descriptor 3 Register (LMEM_DESC_3) */
#define S32K3XX_MCM_LMEMDESC4_OFFSET (0x0410) /* Local Memory Descriptor 4 Register (LMEM_DESC_4) */
/* MCM Register Addresses ***************************************************/
#define S32K3XX_MCM_PLREV (S32K3XX_MCM_BASE + S32K3XX_MCM_PLREV_OFFSET)
#define S32K3XX_MCM_PCT (S32K3XX_MCM_BASE + S32K3XX_MCM_PCT_OFFSET)
#define S32K3XX_MCM_CPCR (S32K3XX_MCM_BASE + S32K3XX_MCM_CPCR_OFFSET)
#define S32K3XX_MCM_ISCR (S32K3XX_MCM_BASE + S32K3XX_MCM_ISCR_OFFSET)
#define S32K3XX_MCM_LMEMDESC0 (S32K3XX_MCM_BASE + S32K3XX_MCM_LMEMDESC0_OFFSET)
#define S32K3XX_MCM_LMEMDESC1 (S32K3XX_MCM_BASE + S32K3XX_MCM_LMEMDESC1_OFFSET)
#define S32K3XX_MCM_LMEMDESC2 (S32K3XX_MCM_BASE + S32K3XX_MCM_LMEMDESC2_OFFSET)
#define S32K3XX_MCM_LMEMDESC3 (S32K3XX_MCM_BASE + S32K3XX_MCM_LMEMDESC3_OFFSET)
#define S32K3XX_MCM_LMEMDESC4 (S32K3XX_MCM_BASE + S32K3XX_MCM_LMEMDESC4_OFFSET)
/* MCM Register Bitfield Definitions ****************************************/
/* SoC-defined Platform Revision Register (PLREV) */
#define MCM_PLREV_SHIFT (0) /* Bits 0-15: SoC-defined Platform Revision (PLREV) */
#define MCM_PLREV_MASK (0xffff << MCM_PLREV_SHIFT)
/* Processor Core Type Register (PCT) */
#define MCM_PCT_SHIFT (0) /* Bits 0-15: Processor Core Type (PCT) */
#define MCM_PCT_MASK (0xffff << MCM_PCT_SHIFT)
# define MCM_PCT_CM7 (0xac70 << MCM_PCT_SHIFT) /* Cortex-M7 */
/* Core Platform Control Register (CPCR) */
/* Bits 0-26: Reserved */
#define MCM_CPCR_CM7_AHBSPRI (1 << 27) /* Bit 27: AHB Slave Priority (CM7_AHBSPRI) */
/* Bits 28-31: Reserved */
/* Interrupt Status and Control Register (ISCR) */
/* Bits 0-4: Reserved */
#define MCM_ISCR_WABS (1 << 5) /* Bit 5: Write Abort on Slave (WABS) */
#define MCM_ISCR_WABSO (1 << 6) /* Bit 6: Write Abort on Slave Overrun (WABSO) */
/* Bit 7: Reserved */
#define MCM_ISCR_FIOC (1 << 8) /* Bit 8: FPU Invalid Operation Interrupt Status (FIOC) */
#define MCM_ISCR_FDZC (1 << 9) /* Bit 9: FPU Divide-by-Zero Interrupt Status (FDZC) */
#define MCM_ISCR_FOFC (1 << 10) /* Bit 10: FPU Overflow Interrupt Status (FOFC) */
#define MCM_ISCR_FUFC (1 << 11) /* Bit 11: FPU Underflow Interrupt Status (FUFC) */
#define MCM_ISCR_FIXC (1 << 12) /* Bit 12: FPU Inexact Interrupt Status (FIXC) */
/* Bits 13-14: Reserved */
#define MCM_ISCR_FIDC (1 << 15) /* Bit 15: FPU Input Denormal Interrupt Status (FIDC) */
/* Bits 16-20: Reserved */
#define MCM_ISCR_WABE (1 << 21) /* Bit 21: TCM Write Abort Interrupt Enable (WABE) */
/* Bits 22-23: Reserved */
#define MCM_ISCR_FIOCE (1 << 24) /* Bit 24: FPU Invalid Operation Interrupt Enable (FIOCE) */
#define MCM_ISCR_FDZCE (1 << 25) /* Bit 25: FPU Divide-by-Zero Interrupt Enable (FDZCE) */
#define MCM_ISCR_FOFCE (1 << 26) /* Bit 26: FPU Overflow Interrupt Enable (FOFCE) */
#define MCM_ISCR_FUFCE (1 << 27) /* Bit 27: FPU Underflow Interrupt Enable (FUFCE) */
#define MCM_ISCR_FIXCE (1 << 28) /* Bit 28: FPU Inexact Interrupt Enable (FIXCE) */
/* Bits 29-30: Reserved */
#define MCM_ISCR_FIDCE (1 << 31) /* Bit 31: FPU Input Denormal Interrupt Enable (FIDCE) */
/* Local Memory Descriptor n Register (LMEM_DESC_n) */
/* Bits 0-12: Reserved */
#define MCM_LMEMDESC_MT_SHIFT (13) /* Bits 13-15: Memory Type (MT) */
#define MCM_LMEMDESC_MT_MASK (0x07 << MCM_LMEMDESC_MT_SHIFT)
# define MCM_LMEMDESC_MT_ITCM (0x00 << MCM_LMEMDESC_MT_SHIFT) /* ITCM */
# define MCM_LMEMDESC_MT_DTCM (0x01 << MCM_LMEMDESC_MT_SHIFT) /* DTCM */
# define MCM_LMEMDESC_MT_ICACHE (0x02 << MCM_LMEMDESC_MT_SHIFT) /* ICACHE */
# define MCM_LMEMDESC_MT_DCACHE (0x03 << MCM_LMEMDESC_MT_SHIFT) /* DCACHE */
/* Bits 16: Reserved */
#define MCM_LMEMDESC_DPW_SHIFT (17) /* Bits 17-19: Data Path Width (DPW) */
#define MCM_LMEMDESC_DPW_MASK (0x07 << MCM_LMEMDESC_DPW_SHIFT)
# define MCM_LMEMDESC_DPW_32 (0x02 << MCM_LMEMDESC_DPW_SHIFT) /* LMEM0 is 32-bits wide */
# define MCM_LMEMDESC_DPW_64 (0x03 << MCM_LMEMDESC_DPW_SHIFT) /* LMEM0 is 64-bits wide */
#define MCM_LMEMDESC_WY_SHIFT (20) /* Bits 20-23: Level 1 Cache Ways (WY) */
#define MCM_LMEMDESC_WY_MASK (0x0f << MCM_LMEMDESC_WY_SHIFT)
# define MCM_LMEMDESC_WY_NOCACHE (0x00 << MCM_LMEMDESC_WY_SHIFT) /* No cache */
# define MCM_LMEMDESC_WY_2WAYSA (0x02 << MCM_LMEMDESC_WY_SHIFT) /* 2-way set associative */
# define MCM_LMEMDESC_WY_4WAYSA (0x04 << MCM_LMEMDESC_WY_SHIFT) /* 4-way set associative */
#define MCM_LMEMDESC_LMSZ_SHIFT (24) /* Bits 24-27: Local Memory Size (LMSZ) */
#define MCM_LMEMDESC_LMSZ_MASK (0x0f << MCM_LMEMDESC_LMSZ_SHIFT)
# define MCM_LMEMDESC_LMSZ_0K (0x00 << MCM_LMEMDESC_LMSZ_SHIFT) /* 0 KB */
# define MCM_LMEMDESC_LMSZ_1K (0x01 << MCM_LMEMDESC_LMSZ_SHIFT) /* 1 KB */
# define MCM_LMEMDESC_LMSZ_2K (0x02 << MCM_LMEMDESC_LMSZ_SHIFT) /* 2 KB */
# define MCM_LMEMDESC_LMSZ_4K (0x03 << MCM_LMEMDESC_LMSZ_SHIFT) /* 4 KB */
# define MCM_LMEMDESC_LMSZ_8K (0x04 << MCM_LMEMDESC_LMSZ_SHIFT) /* 8 KB */
# define MCM_LMEMDESC_LMSZ_16K (0x05 << MCM_LMEMDESC_LMSZ_SHIFT) /* 16 KB */
# define MCM_LMEMDESC_LMSZ_32K (0x06 << MCM_LMEMDESC_LMSZ_SHIFT) /* 32 KB */
# define MCM_LMEMDESC_LMSZ_64K (0x07 << MCM_LMEMDESC_LMSZ_SHIFT) /* 64 KB */
# define MCM_LMEMDESC_LMSZ_128K (0x08 << MCM_LMEMDESC_LMSZ_SHIFT) /* 128 KB */
# define MCM_LMEMDESC_LMSZ_256K (0x09 << MCM_LMEMDESC_LMSZ_SHIFT) /* 256 KB */
# define MCM_LMEMDESC_LMSZ_512K (0x0a << MCM_LMEMDESC_LMSZ_SHIFT) /* 512 KB */
# define MCM_LMEMDESC_LMSZ_1024K (0x0b << MCM_LMEMDESC_LMSZ_SHIFT) /* 1024 KB */
# define MCM_LMEMDESC_LMSZ_2048K (0x0c << MCM_LMEMDESC_LMSZ_SHIFT) /* 2048 KB */
# define MCM_LMEMDESC_LMSZ_4096K (0x0d << MCM_LMEMDESC_LMSZ_SHIFT) /* 4096 KB */
# define MCM_LMEMDESC_LMSZ_8192K (0x0e << MCM_LMEMDESC_LMSZ_SHIFT) /* 8192 KB */
# define MCM_LMEMDESC_LMSZ_16384K (0x0f << MCM_LMEMDESC_LMSZ_SHIFT) /* 16384 KB */
#define MCM_LMEMDESC_LMSZH (1 << 28) /* Bit 28: LMEM Size Hole (LMSZH) */
/* Bits 29-30: Reserved */
#define MCM_LMEMDESC_LMV (1 << 31) /* Bit 31: Local Memory Valid (LMV) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MCM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MEMORYMAP_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* AIPS-Lite Peripheral Bridges */
#define S32K3XX_AIPS0_BASE (0x40000000) /* AIPS-Lite Peripheral Bridge 0 */
#define S32K3XX_AIPS1_BASE (0x40200000) /* AIPS-Lite Peripheral Bridge 1 */
#define S32K3XX_AIPS2_BASE (0x40400000) /* AIPS-Lite Peripheral Bridge 2 */
/* Peripheral Bridge 0 (AIPS0) **********************************************/
#define S32K3XX_TRGMUX_BASE (0x40080000) /* Trigger Multiplexer */
#define S32K3XX_BCTU_BASE (0x40084000) /* Body Cross-Triggering Unit */
#define S32K3XX_EMIOS0_BASE (0x40088000) /* Enhanced Modular I/O Subsystem 0 */
#define S32K3XX_EMIOS1_BASE (0x4008c000) /* Enhanced Modular I/O Subsystem 1 */
#define S32K3XX_EMIOS2_BASE (0x40090000) /* Enhanced Modular I/O Subsystem 2 */
/* 0x40094000-0x40097fff Reserved */
#define S32K3XX_LCU0_BASE (0x40098000) /* Logic Control Unit 0 */
#define S32K3XX_LCU1_BASE (0x4009c000) /* Logic Control Unit 1 */
#define S32K3XX_ADC0_BASE (0x400a0000) /* Analog-to-Digital Converter 0 */
#define S32K3XX_ADC1_BASE (0x400a4000) /* Analog-to-Digital Converter 1 */
#define S32K3XX_ADC2_BASE (0x400a8000) /* Analog-to-Digital Converter 2 */
/* 0x400ac000-0x400afff Reserved */
#define S32K3XX_PIT0_BASE (0x400b0000) /* Periodic Interrupt Timer 0 */
#define S32K3XX_PIT1_BASE (0x400b4000) /* Periodic Interrupt Timer 1 */
#define S32K3XX_MU2_MUA_BASE (0x400b8000) /* Messaging Unit 2, Interface A */
#define S32K3XX_MU2_MUB_BASE (0x400bc000) /* Messaging Unit 2, Interface B */
#define S32K3XX_I3C_BASE (0x400c0000) /* Improved Inter-Integrated Circuit */
/* Peripheral Bridge 1 (AIPS1) **********************************************/
#define S32K3XX_AXBS_BASE (0x40200000) /* Crossbar Switch */
#define S32K3XX_XBIC0_BASE (0x40204000) /* Crossbar Integrity Checker 0 */
#define S32K3XX_XBIC1_BASE (0x40208000) /* Crossbar Integrity Checker 1 */
#define S32K3XX_EDMA_BASE (0x4020c000) /* Enhanced Direct Memory Access */
#define S32K3XX_EDMA_TCD_BASE (0x40210000) /* eDMA Transfer Control Descriptor */
/* 0x40240000-0x40257fff Debug */
#define S32K3XX_EIM_BASE (0x40258000) /* Error Injection Module */
#define S32K3XX_ERM_BASE (0x4025c000) /* Error Reporting Module */
#define S32K3XX_MSCM_BASE (0x40260000) /* Miscellaneous System Control Module */
#define S32K3XX_PRAMC0_BASE (0x40264000) /* Platform RAM Controller 0 */
#define S32K3XX_PFLASH_BASE (0x40268000) /* Platform Flash Memory Controller */
/* 0x4026c000-0x4026ffff PFLASH Alt. */
#define S32K3XX_SWT0_BASE (0x40270000) /* Software Watchdog Timer 0 */
#define S32K3XX_STM0_BASE (0x40274000) /* System Timer Module 0 */
#define S32K3XX_XRDC_BASE (0x40278000) /* Extended Resource Domain Controller */
#define S32K3XX_INTM_BASE (0x4027c000) /* Interrupt Monitor */
#define S32K3XX_DMAMUX0_BASE (0x40280000) /* Direct Memory Access Multiplexer 0 */
#define S32K3XX_DMAMUX1_BASE (0x40284000) /* Direct Memory Access Multiplexer 1 */
#define S32K3XX_RTC_BASE (0x40288000) /* Real Time Clock */
#define S32K3XX_MC_RGM_BASE (0x4028c000) /* Reset Generation Module */
#define S32K3XX_SIUL2_BASE (0x40290000) /* System Integration Unit Lite */
/* 0x40294000-0x402a7fff SIUL2 */
#define S32K3XX_VIRTWRAPPER_BASE (0x402a8000) /* Virtualization Wrapper */
#define S32K3XX_DCM_BASE (0x402ac000) /* Device Configuration Module */
/* 0x402b0000-0x402b3fff Reserved */
#define S32K3XX_WKPU_BASE (0x402b4000) /* Wakeup Unit */
/* 0x402b8000-0x402bbfff Reserved */
#define S32K3XX_CMU0_BASE (0x402bc000) /* Clock Monitoring Unit 0 */
#define S32K3XX_CMU1_BASE (0x402bc020) /* Clock Monitoring Unit 1 */
#define S32K3XX_CMU2_BASE (0x402bc040) /* Clock Monitoring Unit 2 */
#define S32K3XX_CMU3_BASE (0x402bc060) /* Clock Monitoring Unit 3 */
#define S32K3XX_CMU4_BASE (0x402bc080) /* Clock Monitoring Unit 4 */
#define S32K3XX_CMU5_BASE (0x402bc0a0) /* Clock Monitoring Unit 5 */
/* 0x402c0000-0x402c3fff Reserved */
#define S32K3XX_TSPC_BASE (0x402c4000) /* Touch Sensing Pin Coupling */
#define S32K3XX_SIRC_BASE (0x402c8000) /* Slow Internal RC Oscillator */
#define S32K3XX_SXOSC_BASE (0x402cc000) /* Slow Crystal Oscillator */
#define S32K3XX_FIRC_BASE (0x402d0000) /* Fast Internal RC Oscillator */
#define S32K3XX_FXOSC_BASE (0x402d4000) /* Fast Crystal Oscillator */
#define S32K3XX_MC_CGM_BASE (0x402d8000) /* Clock Generation Module */
#define S32K3XX_MC_ME_BASE (0x402dc000) /* Mode Entry Module */
#define S32K3XX_PLL_BASE (0x402e0000) /* Phase-Locked Loop */
/* 0x402e4000-0x402e7fff Reserved */
#define S32K3XX_PMC_BASE (0x402e8000) /* Power Management Controller */
#define S32K3XX_FMU_BASE (0x402ec000) /* Flash Management Unit */
/* 0x402f0000-0x402f3fff FMU Alt. */
/* 0x402f4000-0x402fbfff Reserved */
#define S32K3XX_PIT2_BASE (0x402fc000) /* Periodic Interrupt Timer 2 */
/* 0x40300000-0x40303fff Reserved */
#define S32K3XX_FLEXCAN0_BASE (0x40304000) /* FlexCAN 0 */
#define S32K3XX_FLEXCAN1_BASE (0x40308000) /* FlexCAN 1 */
#define S32K3XX_FLEXCAN2_BASE (0x4030c000) /* FlexCAN 2 */
#define S32K3XX_FLEXCAN3_BASE (0x40310000) /* FlexCAN 3 */
#define S32K3XX_FLEXCAN4_BASE (0x40314000) /* FlexCAN 4 */
#define S32K3XX_FLEXCAN5_BASE (0x40318000) /* FlexCAN 5 */
/* 0x4031c000-0x40323fff Reserved */
#define S32K3XX_FLEXIO_BASE (0x40324000) /* Flexible I/O */
#define S32K3XX_LPUART0_BASE (0x40328000) /* Low Power Universal Asynchronous Receiver/Transmitter 0 */
#define S32K3XX_LPUART1_BASE (0x4032c000) /* Low Power Universal Asynchronous Receiver/Transmitter 1 */
#define S32K3XX_LPUART2_BASE (0x40330000) /* Low Power Universal Asynchronous Receiver/Transmitter 2 */
#define S32K3XX_LPUART3_BASE (0x40334000) /* Low Power Universal Asynchronous Receiver/Transmitter 3 */
#define S32K3XX_LPUART4_BASE (0x40338000) /* Low Power Universal Asynchronous Receiver/Transmitter 4 */
#define S32K3XX_LPUART5_BASE (0x4033c000) /* Low Power Universal Asynchronous Receiver/Transmitter 5 */
#define S32K3XX_LPUART6_BASE (0x40340000) /* Low Power Universal Asynchronous Receiver/Transmitter 6 */
#define S32K3XX_LPUART7_BASE (0x40344000) /* Low Power Universal Asynchronous Receiver/Transmitter 7 */
/* 0x40348000-0x4034ffff Reserved */
#define S32K3XX_LPI2C0_BASE (0x40350000) /* Low Power Inter-Integrated Circuit 0 */
#define S32K3XX_LPI2C1_BASE (0x40354000) /* Low Power Inter-Integrated Circuit 1 */
#define S32K3XX_LPSPI0_BASE (0x40358000) /* Low Power Serial Peripheral Interface 0 */
#define S32K3XX_LPSPI1_BASE (0x4035c000) /* Low Power Serial Peripheral Interface 1 */
#define S32K3XX_LPSPI2_BASE (0x40360000) /* Low Power Serial Peripheral Interface 2 */
#define S32K3XX_LPSPI3_BASE (0x40364000) /* Low Power Serial Peripheral Interface 3 */
/* 0x40368000-0x4036bfff Reserved */
#define S32K3XX_SAI0_BASE (0x4036c000) /* Synchronous Audio Interface 0 */
#define S32K3XX_LPCMP0_BASE (0x40370000) /* Low Power Comparator 0 */
#define S32K3XX_LPCMP1_BASE (0x40374000) /* Low Power Comparator 1 */
/* 0x40378000-0x4037bfff Reserved */
#define S32K3XX_TMU_BASE (0x4037c000) /* Temperature Sensor Unit */
#define S32K3XX_CRC_BASE (0x40380000) /* Cyclic Redundancy Check */
#define S32K3XX_FCCU_BASE (0x40384000) /* Fault Collection and Control Unit */
/* 0x40388000-0x4038bfff Self-test */
#define S32K3XX_MU0_MUB_BASE (0x4038c000) /* Messaging Unit 0, Interface B */
#if defined(CONFIG_ARCH_CHIP_S32K312) || defined(CONFIG_ARCH_CHIP_S32K311)
# define S32K3XX_MU1_MUB_BASE (0x40390000) /* Messaging Unit 1, Interface B (S32K312/S32K311) */
#endif
#define S32K3XX_JDC_BASE (0x40394000) /* JTAG Data Communication */
#define S32K3XX_HSE_BASE (0x4039c000) /* HSE_B Configuration_GPR */
/* Peripheral Bridge 2 (AIPS2) **********************************************/
#define S32K3XX_XBIC2_BASE (0x40400000) /* Crossbar Integrity Checker 2 */
#define S32K3XX_XBIC3_BASE (0x40404000) /* Crossbar Integrity Checker 3 */
/* 0x40408000-0x4040ffff Reserved */
/* 0x40410000-0x4045ffff EDMA TCD */
#define S32K3XX_SEMA42_BASE (0x40460000) /* Semaphores */
#define S32K3XX_PRAMC1_BASE (0x40464000) /* Platform RAM Controller 1 */
/* 0x40468000-0x4046bfff Reserved */
#define S32K3XX_SWT1_BASE (0x4046c000) /* Software Watchdog Timer 1 */
/* 0x40470000-0x40473fff Reserved */
#define S32K3XX_STM1_BASE (0x40474000) /* System Timer Module 1 */
/* 0x40478000-0x4047ffff Reserved */
#define S32K3XX_EMAC_BASE (0x40480000) /* Ethernet Media Access Controller */
/* 0x40484000-0x4048bfff Reserved */
#define S32K3XX_LPUART8_BASE (0x4048c000) /* Low Power Universal Asynchronous Receiver/Transmitter 8 */
#define S32K3XX_LPUART9_BASE (0x40490000) /* Low Power Universal Asynchronous Receiver/Transmitter 9 */
#define S32K3XX_LPUART10_BASE (0x40494000) /* Low Power Universal Asynchronous Receiver/Transmitter 10 */
#define S32K3XX_LPUART11_BASE (0x40498000) /* Low Power Universal Asynchronous Receiver/Transmitter 11 */
#define S32K3XX_LPUART12_BASE (0x4049c000) /* Low Power Universal Asynchronous Receiver/Transmitter 12 */
#define S32K3XX_LPUART13_BASE (0x404a0000) /* Low Power Universal Asynchronous Receiver/Transmitter 13 */
#define S32K3XX_LPUART14_BASE (0x404a4000) /* Low Power Universal Asynchronous Receiver/Transmitter 14 */
#define S32K3XX_LPUART15_BASE (0x404a8000) /* Low Power Universal Asynchronous Receiver/Transmitter 15 */
/* 0x404ac000-0x404bbfff Reserved */
#define S32K3XX_LPSPI4_BASE (0x404bc000) /* Low Power Serial Peripheral Interface 4 */
#define S32K3XX_LPSPI5_BASE (0x404c0000) /* Low Power Serial Peripheral Interface 5 */
/* 0x404c4000-0x404cbfff Reserved */
#define S32K3XX_QSPI_BASE (0x404cc000) /* Quad Serial Peripheral Interface */
/* 0x404d0000-0x404dbfff Reserved */
#define S32K3XX_SAI1_BASE (0x404dc000) /* Synchronous Audio Interface 1 */
/* 0x404e0000-0x404e7fff Reserved */
#define S32K3XX_LPCMP2_BASE (0x404e8000) /* Low Power Comparator 2 */
#if !defined(CONFIG_ARCH_CHIP_S32K312) && !defined(CONFIG_ARCH_CHIP_S32K311)
# define S32K3XX_MU1_MUB_BASE (0x404ec000) /* Messaging Unit 1, Interface B (S32K344/S32K342/S32K324/S32K322/S32K314) */
#endif
/* Private Peripheral Bus (PPB) *********************************************/
#define S32K3XX_ITM_BASE (0xe0000000) /* Instrumentation Trace Macrocell */
#define S32K3XX_DWT_BASE (0xe0001000) /* Data Watchpoint and Trace */
#define S32K3XX_FPB_BASE (0xe0002000) /* Flash Patch and Breakpoint */
#define S32K3XX_SCS_BASE (0xe000e000) /* System Control Space */
#define S32K3XX_TPIU_BASE (0xe0040000) /* Trace Port Interface Unit */
#define S32K3XX_ETM_BASE (0xe0041000) /* Embedded Trace Macrocell */
#define S32K3XX_CTI_BASE (0xe0042000) /* Cross Trigger Interface */
#define S32K3XX_MCM_BASE (0xe0080000) /* Miscellaneous Control Module */
#define S32K3XX_ROMTABLE_BASE (0xe00ff000) /* Cortex-M7 PPB ROM Table */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MSCM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MSCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MSCM Register Offsets ****************************************************/
#define S32K3XX_MSCM_CPXTYPE_OFFSET (0x0000) /* Processor X Type Register (CPXTYPE) */
#define S32K3XX_MSCM_CPXNUM_OFFSET (0x0004) /* Processor X Number Register (CPXNUM) */
#define S32K3XX_MSCM_CPXREV_OFFSET (0x0008) /* Processor X Revision Register (CPXREV) */
#define S32K3XX_MSCM_CPXCFG0_OFFSET (0x000c) /* Processor X Configuration 0 Register (CPXCFG0) */
#define S32K3XX_MSCM_CPXCFG1_OFFSET (0x0010) /* Processor X Configuration 1 Register (CPXCFG1) */
#define S32K3XX_MSCM_CPXCFG2_OFFSET (0x0014) /* Processor X Configuration 2 Register (CPXCFG2) */
#define S32K3XX_MSCM_CPXCFG3_OFFSET (0x0018) /* Processor X Configuration 3 Register (CPXCFG3) */
#define S32K3XX_MSCM_CP0TYPE_OFFSET (0x0020) /* Processor 0 Type Register (CP0TYPE) */
#define S32K3XX_MSCM_CP0NUM_OFFSET (0x0024) /* Processor 0 Number Register (CP0NUM) */
#define S32K3XX_MSCM_CP0REV_OFFSET (0x0028) /* Processor 0 Revision Register (CP0REV) */
#define S32K3XX_MSCM_CP0CFG0_OFFSET (0x002c) /* Processor 0 Configuration 0 Register (CP0CFG0) */
#define S32K3XX_MSCM_CP0CFG1_OFFSET (0x0030) /* Processor 0 Configuration 1 Register (CP0CFG1) */
#define S32K3XX_MSCM_CP0CFG2_OFFSET (0x0034) /* Processor 0 Configuration 2 Register (CP0CFG2) */
#define S32K3XX_MSCM_CP0CFG3_OFFSET (0x0038) /* Processor 0 Configuration 3 Register (CP0CFG3) */
#define S32K3XX_MSCM_CP1TYPE_OFFSET (0x0040) /* Processor 1 Type Register (CP1TYPE) */
#define S32K3XX_MSCM_CP1NUM_OFFSET (0x0044) /* Processor 1 Number Register (CP1NUM) */
#define S32K3XX_MSCM_CP1REV_OFFSET (0x0048) /* Processor 1 Revision Register (CP1REV) */
#define S32K3XX_MSCM_CP1CFG0_OFFSET (0x004c) /* Processor 1 Configuration 0 Register (CP1CFG0) */
#define S32K3XX_MSCM_CP1CFG1_OFFSET (0x0050) /* Processor 1 Configuration 1 Register (CP1CFG1) */
#define S32K3XX_MSCM_CP1CFG2_OFFSET (0x0054) /* Processor 1 Configuration 2 Register (CP1CFG2) */
#define S32K3XX_MSCM_CP1CFG3_OFFSET (0x0058) /* Processor 1 Configuration 3 Register (CP1CFG3) */
#define S32K3XX_MSCM_IRCP0ISR0_OFFSET (0x0200) /* Interrupt Router CP0 Interrupt Status Register 0 (IRCP0ISR0) */
#define S32K3XX_MSCM_IRCP0IGR0_OFFSET (0x0204) /* Interrupt Router CP0 Interrupt Generation Register 0 (IRCP0IGR0) */
#define S32K3XX_MSCM_IRCP0ISR1_OFFSET (0x0208) /* Interrupt Router CP0 Interrupt Status Register 1 (IRCP0ISR1) */
#define S32K3XX_MSCM_IRCP0IGR1_OFFSET (0x020c) /* Interrupt Router CP0 Interrupt Generation Register 1 (IRCP0IGR1) */
#define S32K3XX_MSCM_IRCP0ISR2_OFFSET (0x0210) /* Interrupt Router CP0 Interrupt Status Register 2 (IRCP0ISR2) */
#define S32K3XX_MSCM_IRCP0IGR2_OFFSET (0x0214) /* Interrupt Router CP0 Interrupt Generation Register 2 (IRCP0IGR2) */
#define S32K3XX_MSCM_IRCP0ISR3_OFFSET (0x0218) /* Interrupt Router CP0 Interrupt Status Register 3 (IRCP0ISR3) */
#define S32K3XX_MSCM_IRCP0IGR3_OFFSET (0x021c) /* Interrupt Router CP0 Interrupt Generation Register 3 (IRCP0IGR3) */
#define S32K3XX_MSCM_IRCP1ISR0_OFFSET (0x0220) /* Interrupt Router CP1 Interrupt Status Register 0 (IRCP1ISR0) */
#define S32K3XX_MSCM_IRCP1IGR0_OFFSET (0x0224) /* Interrupt Router CP1 Interrupt Generation Register 0 (IRCP1IGR0) */
#define S32K3XX_MSCM_IRCP1ISR1_OFFSET (0x0228) /* Interrupt Router CP1 Interrupt Status Register 1 (IRCP1ISR1) */
#define S32K3XX_MSCM_IRCP1IGR1_OFFSET (0x022c) /* Interrupt Router CP1 Interrupt Generation Register 1 (IRCP1IGR1) */
#define S32K3XX_MSCM_IRCP1ISR2_OFFSET (0x0230) /* Interrupt Router CP1 Interrupt Status Register 2 (IRCP1ISR2) */
#define S32K3XX_MSCM_IRCP1IGR2_OFFSET (0x0234) /* Interrupt Router CP1 Interrupt Generation Register 2 (IRCP1IGR2) */
#define S32K3XX_MSCM_IRCP1ISR3_OFFSET (0x0238) /* Interrupt Router CP1 Interrupt Status Register 3 (IRCP1ISR3) */
#define S32K3XX_MSCM_IRCP1IGR3_OFFSET (0x023c) /* Interrupt Router CP1 Interrupt Generation Register 3 (IRCP1IGR3) */
#define S32K3XX_MSCM_IRCPCFG_OFFSET (0x0400) /* Interrupt Router Configuration Register (IRCPCFG) */
#define S32K3XX_MSCM_ENEDC_OFFSET (0x0600) /* Enable Interconnect Error Detection Register (ENEDC) */
#define S32K3XX_MSCM_IAHBCFGREG_OFFSET (0x0700) /* AHB Gasket Configuration Register (IAHBCFGREG) */
#define S32K3XX_MSCM_IRSPRC_OFFSET(n) (0x0880 + ((n) << 1)) /* Interrupt Router Shared Peripheral Routing Control n=0..239 Register (IRSPRCn) */
/* MSCM Register Addresses **************************************************/
#define S32K3XX_MSCM_CPXTYPE (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXTYPE_OFFSET)
#define S32K3XX_MSCM_CPXNUM (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXNUM_OFFSET)
#define S32K3XX_MSCM_CPXREV (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXREV_OFFSET)
#define S32K3XX_MSCM_CPXCFG0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXCFG0_OFFSET)
#define S32K3XX_MSCM_CPXCFG1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXCFG1_OFFSET)
#define S32K3XX_MSCM_CPXCFG2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXCFG2_OFFSET)
#define S32K3XX_MSCM_CPXCFG3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CPXCFG3_OFFSET)
#define S32K3XX_MSCM_CP0TYPE (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0TYPE_OFFSET)
#define S32K3XX_MSCM_CP0NUM (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0NUM_OFFSET)
#define S32K3XX_MSCM_CP0REV (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0REV_OFFSET)
#define S32K3XX_MSCM_CP0CFG0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0CFG0_OFFSET)
#define S32K3XX_MSCM_CP0CFG1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0CFG1_OFFSET)
#define S32K3XX_MSCM_CP0CFG2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0CFG2_OFFSET)
#define S32K3XX_MSCM_CP0CFG3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP0CFG3_OFFSET)
#define S32K3XX_MSCM_CP1TYPE (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1TYPE_OFFSET)
#define S32K3XX_MSCM_CP1NUM (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1NUM_OFFSET)
#define S32K3XX_MSCM_CP1REV (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1REV_OFFSET)
#define S32K3XX_MSCM_CP1CFG0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1CFG0_OFFSET)
#define S32K3XX_MSCM_CP1CFG1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1CFG1_OFFSET)
#define S32K3XX_MSCM_CP1CFG2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1CFG2_OFFSET)
#define S32K3XX_MSCM_CP1CFG3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_CP1CFG3_OFFSET)
#define S32K3XX_MSCM_IRCP0ISR0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0ISR0_OFFSET)
#define S32K3XX_MSCM_IRCP0IGR0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0IGR0_OFFSET)
#define S32K3XX_MSCM_IRCP0ISR1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0ISR1_OFFSET)
#define S32K3XX_MSCM_IRCP0IGR1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0IGR1_OFFSET)
#define S32K3XX_MSCM_IRCP0ISR2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0ISR2_OFFSET)
#define S32K3XX_MSCM_IRCP0IGR2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0IGR2_OFFSET)
#define S32K3XX_MSCM_IRCP0ISR3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0ISR3_OFFSET)
#define S32K3XX_MSCM_IRCP0IGR3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP0IGR3_OFFSET)
#define S32K3XX_MSCM_IRCP1ISR0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1ISR0_OFFSET)
#define S32K3XX_MSCM_IRCP1IGR0 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1IGR0_OFFSET)
#define S32K3XX_MSCM_IRCP1ISR1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1ISR1_OFFSET)
#define S32K3XX_MSCM_IRCP1IGR1 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1IGR1_OFFSET)
#define S32K3XX_MSCM_IRCP1ISR2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1ISR2_OFFSET)
#define S32K3XX_MSCM_IRCP1IGR2 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1IGR2_OFFSET)
#define S32K3XX_MSCM_IRCP1ISR3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1ISR3_OFFSET)
#define S32K3XX_MSCM_IRCP1IGR3 (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCP1IGR3_OFFSET)
#define S32K3XX_MSCM_IRCPCFG (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRCPCFG_OFFSET)
#define S32K3XX_MSCM_ENEDC (S32K3XX_MSCM_BASE + S32K3XX_MSCM_ENEDC_OFFSET)
#define S32K3XX_MSCM_IAHBCFGREG (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IAHBCFGREG_OFFSET)
#define S32K3XX_MSCM_IRSPRC(n) (S32K3XX_MSCM_BASE + S32K3XX_MSCM_IRSPRC_OFFSET(n))
/* MSCM Register Bitfield Definitions ***************************************/
/* Processor x Type Register (CPXTYPE) */
#define MSCM_CPXTYPE_PERSONALITY_SHIFT (0) /* Bits 0-31: Personality of CPx (PERSONALITY) */
#define MSCM_CPXTYPE_PERSONALITY_MASK (0xffffffff << MSCM_CPXTYPE_PERSONALITY_SHIFT)
# define MSCM_CPXTYPE_PERSONALITY_M7_0 (0x434d3730 << MSCM_CPXTYPE_PERSONALITY_SHIFT) /* Cortex-M7 core 0 */
# define MSCM_CPXTYPE_PERSONALITY_M7_1 (0x434d3731 << MSCM_CPXTYPE_PERSONALITY_SHIFT) /* Cortex-M7 core 1 */
/* Processor x Number Register (CPXNUM) */
#define MSCM_CPXNUM_CPN_SHIFT (0) /* Bits 0-1: Processor Number (CPN) */
#define MSCM_CPXNUM_CPN_MASK (0x03 << MSCM_CPXNUM_CPN_SHIFT)
# define MSCM_CPXNUM_CPN_M7_0 (0x00 << MSCM_CPXNUM_CPN_SHIFT) /* Cortex-M7 core 0 */
# define MSCM_CPXNUM_CPN_M7_1 (0x01 << MSCM_CPXNUM_CPN_SHIFT) /* Cortex-M7 core 1 */
/* Bits 2-31: Reserved */
/* Processor x Revision Register (CPXREV) */
#define MSCM_CPXREV_RYPZ_SHIFT (0) /* Bits 0-7: Processor Revision (RYPZ) */
#define MSCM_CPXREV_RYPZ_MASK (0xff << MSCM_CPXREV_RYPZ_SHIFT)
/* Bits 8-31: Reserved */
/* Processor x Configuration 0 Register (CPXCFG0) */
#define MSCM_CPXCFG0_DCWY_SHIFT (0) /* Bits 0-7: L1 Data Cache Ways (DCWY) */
#define MSCM_CPXCFG0_DCWY_MASK (0xff << MSCM_CPXCFG0_DCWY_SHIFT)
#define MSCM_CPXCFG0_DCSZ_SHIFT (8) /* Bits 8-15: L1 Data Cache Size (DCSZ) */
#define MSCM_CPXCFG0_DCSZ_MASK (0xff << MSCM_CPXCFG0_DCSZ_SHIFT)
#define MSCM_CPXCFG0_ICWY_SHIFT (16) /* Bits 16-23: L1 Instruction Cache Ways (ICWY) */
#define MSCM_CPXCFG0_ICWY_MASK (0xff << MSCM_CPXCFG0_ICWY_SHIFT)
#define MSCM_CPXCFG0_ICSZ_SHIFT (24) /* Bits 24-31: L1 Instruction Cache Size (ICSZ) */
#define MSCM_CPXCFG0_ICSZ_MASK (0xff << MSCM_CPXCFG0_ICSZ_SHIFT)
/* Processor x Configuration 1 Register (CPXCFG1) */
/* Bits 0-15: Reserved */
#define MSCM_CPXCFG1_L2WY_SHIFT (16) /* Bits 16-23: L2 Cache Ways (L2WY) */
#define MSCM_CPXCFG1_L2WY_MASK (0xff << MSCM_CPXCFG1_L2WY_SHIFT)
#define MSCM_CPXCFG1_L2SZ_SHIFT (24) /* Bits 24-31: L2 Cache Size (L2SZ) */
#define MSCM_CPXCFG1_L2SZ_MASK (0xff << MSCM_CPXCFG1_L2SZ_SHIFT)
/* Processor x Configuration 2 Register (CPXCFG2) */
/* Bits 0-15: Reserved */
#define MSCM_CPXCFG2_ITCMSZ_SHIFT (16) /* Bits 16-23: Instruction Tightly Coupled Memory Size (ITCMSZ) */
#define MSCM_CPXCFG2_ITCMSZ_MASK (0xff << MSCM_CPXCFG2_ITCMSZ_SHIFT)
#define MSCM_CPXCFG2_DTCMSZ_SHIFT (24) /* Bits 24-31: Data Tightly Coupled Memory Size (DTCMSZ) */
#define MSCM_CPXCFG2_DTCMSZ_MASK (0xff << MSCM_CPXCFG2_DTCMSZ_SHIFT)
/* Processor x Configuration 3 Register (CPXCFG3) */
#define MSCM_CPXCFG3_FPU (1 << 0) /* Bit 0: Floating Point Unit (FPU) */
#define MSCM_CPXCFG3_SIMD (1 << 1) /* Bit 1: SIMD/NEON Instruction Support (SIMD) */
#define MSCM_CPXCFG3_MMU (1 << 2) /* Bit 2: Memory Mangement Unit (MMU) */
#define MSCM_CPXCFG3_CMP (1 << 3) /* Bit 3: Core Memory Protection Unit (CMP) */
#define MSCM_CPXCFG3_CPY (1 << 4) /* Bit 4: Cryptography (CPY) */
/* Bits 5-31: Reserved */
/* Interrupt Router CPn Interrupt Status Register m (IRCPnISRm) */
#define MSCM_IRCPISR_CP0_INT (1 << 0) /* Bit 0: CP0-to-CPn Interrupt (CP0_INT) */
#define MSCM_IRCPISR_CP1_INT (1 << 1) /* Bit 1: CP1-to-CPn Interrupt (CP1_INT) */
/* Bit 2-31: Reserved */
/* Interrupt Router CPn Interrupt Generation Register m (IRCPnIGRm) */
#define MSCM_IRCPIGR_INT_EN (1 << 0) /* Bit 0: Interrupt Enable (INT_EN) */
/* Bit 1-31: Reserved */
/* Interrupt Router Configuration Register (IRCPCFG) */
#define MSCM_IRCPCFG_CP0_TR (1 << 0) /* Bit 0: CP0 as Trusted Core (CP0_TR) */
#define MSCM_IRCPCFG_CP1_TR (1 << 1) /* Bit 1: CP1 as Trusted Core (CP1_TR) */
/* Bits 2-30: Reserved */
#define MSCM_IRCPCFG_LOCK (1 << 31) /* Bit 31: Lock (LOCK) */
/* Enable Interconnect Error Detection Register (ENEDC) */
#define MSCM_ENEDC_EN_RD_CM7_0_AHBM (1 << 0) /* Bit 0: Enable Read Data Check Cortex-M7_0_AHBM (EN_RD_CM7_0_AHBM) */
#define MSCM_ENEDC_EN_RD_CM7_0_AHBP (1 << 1) /* Bit 1: Enable Read Data Check Cortex-M7_0_AHBP (EN_RD_CM7_0_AHBP) */
#define MSCM_ENEDC_EN_RD_EDMA (1 << 2) /* Bit 2: Enable Read Data Check eDMA (EN_RD_EDMA) */
/* Bit 3: Reserved */
#define MSCM_ENEDC_EN_RD_HSE (1 << 4) /* Bit 4: Enable Read Data Check HSE (EN_RD_HSE) */
#define MSCM_ENEDC_EN_RD_EMAC (1 << 5) /* Bit 5: Enable Read Data Check EMAC (EN_RD_EMAC) */
#define MSCM_ENEDC_EN_RD_CM7_1_AHBM (1 << 6) /* Bit 6: Enable Read Data Check Cortex-M7_1_AHBM (EN_RD_CM7_1_AHBM) */
#define MSCM_ENEDC_EN_RD_CM7_1_AHBP (1 << 7) /* Bit 7: Enable Read Data Check Cortex-M7_1_AHBP (EN_RD_CM7_1_AHBP) */
#define MSCM_ENEDC_EN_RD_TCM (1 << 8) /* Bit 8: Enable Read Data Check TCM (EN_RD_TCM) */
#define MSCM_ENEDC_EN_ADD_PFLASH_PORT0 (1 << 9) /* Bit 9: Enable Address Check P_FLASH_PORT0 (EN_ADD_PFLASH_PORT0) */
#define MSCM_ENEDC_EN_ADD_PFLASH_PORT1 (1 << 10) /* Bit 10: Enable Address Check P_FLASH_PORT1 (EN_ADD_PFLASH_PORT1) */
#define MSCM_ENEDC_EN_ADD_PFLASH_PORT2 (1 << 11) /* Bit 11: Enable Address Check P_FLASH_PORT2 (EN_ADD_PFLASH_PORT2) */
#define MSCM_ENEDC_EN_WR_PRAM0 (1 << 12) /* Bit 12: Enable Write Data Check PRAM0 (EN_WR_PRAM0) */
#define MSCM_ENEDC_EN_ADD_PRAM0 (1 << 13) /* Bit 13: Enable Address Check PRAM0 (EN_ADD_PRAM0) */
#define MSCM_ENEDC_EN_WR_PRAM1 (1 << 14) /* Bit 14: Enable Write Data Check PRAM1 (EN_WR_PRAM1) */
#define MSCM_ENEDC_EN_ADD_PRAM1 (1 << 15) /* Bit 15: Enable Address Check PRAM1 (EN_ADD_PRAM1) */
#define MSCM_ENEDC_EN_WR_TCM (1 << 16) /* Bit 16: Enable Write Data Check TCM (EN_WR_TCM) */
#define MSCM_ENEDC_EN_ADD_TCM (1 << 17) /* Bit 17: Enable Address Check TCM (EN_ADD_TCM) */
/* Bit 18: Reserved */
#define MSCM_ENEDC_EN_ADD_QSPI (1 << 19) /* Bit 19: Enable Address Check QuadSPI (EN_ADD_QSPI) */
#define MSCM_ENEDC_EN_WR_AIPS0 (1 << 20) /* Bit 20: Enable Write Data Check AIPS0 (EN_WR_AIPS0) */
#define MSCM_ENEDC_EN_ADD_AIPS0 (1 << 21) /* Bit 21: Enable Address Check AIPS0 (EN_ADD_AIPS0) */
#define MSCM_ENEDC_EN_WR_AIPS1 (1 << 22) /* Bit 22: Enable Write Data Check AIPS1 (EN_WR_AIPS1) */
#define MSCM_ENEDC_EN_ADD_AIPS1 (1 << 23) /* Bit 23: Enable Address Check AIPS1 (EN_ADD_AIPS1) */
#define MSCM_ENEDC_EN_WR_AIPS2 (1 << 24) /* Bit 24: Enable Write Data Check AIPS2 (EN_WR_AIPS2) */
#define MSCM_ENEDC_EN_ADD_AIPS2 (1 << 25) /* Bit 25: Enable Address Check AIPS2 (EN_ADD_AIPS2) */
#define MSCM_ENEDC_EN_WR_CM7_0_TCM (1 << 26) /* Bit 26: Enable Write Data Check Cortex-M7_0_TCM (EN_WR_CM7_0_TCM) */
#define MSCM_ENEDC_EN_ADD_CM7_0_TCM (1 << 27) /* Bit 27: Enable Address Check Cortex-M7_0_TCM (EN_ADD_CM7_0_TCM) */
#define MSCM_ENEDC_EN_WR_CM7_1_TCM (1 << 28) /* Bit 28: Enable Write Data Check Cortex-M7_1_TCM (EN_WR_CM7_1_TCM) */
#define MSCM_ENEDC_EN_ADD_CM7_1_TCM (1 << 29) /* Bit 29: Enable Address Check Cortex-M7_1_TCM (EN_ADD_CM7_1_TCM) */
/* Bits 30-31: Reserved */
/* AHB Gasket Configuration Register (IAHBCFGREG) */
#define MSCM_IAHBCFG_EMAC_DIS_WR_OPT (1 << 0) /* Bit 0: EMAC AHB gasket write burst optimizations disabled (EMAC_DIS_WR_OPT) */
/* Bits 1-3: Reserved */
#define MSCM_IAHBCFG_DMA_AXBS_S0_DIS_WR_OPT (1 << 4) /* Bit 4: DMA AXBS S0 AHB gasket write burst optimizations disabled (DMA_AXBS_S0_DIS_WR_OPT) */
/* Bits 5-7: Reserved */
#define MSCM_IAHBCFG_DMA_AXBS_S1_DIS_WR_OPT (1 << 8) /* Bit 8: DMA AXBS S1 AHB gasket write burst optimizations disabled (DMA_AXBS_S1_DIS_WR_OPT) */
/* Bits 9-11: Reserved */
#define MSCM_IAHBCFG_DMA_AXBS_S2_DIS_WR_OPT (1 << 12) /* Bit 12: DMA AXBS S2 AHB gasket write burst optimizations disabled (DMA_AXBS_S2_DIS_WR_OPT) */
/* Bits 13-15: Reserved */
#define MSCM_IAHBCFG_TCM_DIS_WR_OPT (1 << 16) /* Bit 16: TCM AHB gasket write burst optimizations disabled (TCM_DIS_WR_OPT) */
/* Bits 17-19: Reserved */
#define MSCM_IAHBCFG_QSPI_DIS_WR_OPT (1 << 20) /* Bit 20: QuadSPI AHB gasket write burst optimizations disabled (QSPI_DIS_WR_OPT) */
/* Bits 21-23: Reserved */
#define MSCM_IAHBCFG_AIPS1_DIS_WR_OPT (1 << 24) /* Bit 24: AIPS1 AHB gasket write burst optimizations disabled (AIPS1_DIS_WR_OPT) */
/* Bits 25-27: Reserved */
#define MSCM_IAHBCFG_AIPS2_DIS_WR_OPT (1 << 28) /* Bit 28: AIPS2 AHB gasket write burst optimizations disabled (AIPS2_DIS_WR_OPT) */
/* Bits 29-31: Reserved */
/* Interrupt Router Shared Peripheral Routing Control n=0..239 (IRSPRCn) */
#define MSCM_IRSPRC_M7_0 (1 << 0) /* Bit 0: Enable Cortex-M7_0 Interrupt Steering (M7_0) */
#define MSCM_IRSPRC_M7_1 (1 << 1) /* Bit 1: Enable Cortex-M7_1 Interrupt Steering (M7_1) */
/* Bits 2-14: Reserved */
#define MSCM_IRSPRC_LOCK (1 << 15) /* Bit 15: Lock (LOCK) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MSCM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_mu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MU_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MU Register Offsets ******************************************************/
#define S32K3XX_MU_VER_OFFSET (0x0000) /* Version ID Register (VER) */
#define S32K3XX_MU_PAR_OFFSET (0x0004) /* Parameter Register (PAR) */
#define S32K3XX_MU_CR_OFFSET (0x0008) /* Control Register (CR) */
#define S32K3XX_MU_SR_OFFSET (0x000c) /* Status Register (SR) */
#define S32K3XX_MU_CCR0_OFFSET (0x0010) /* Core Control Register 0 (CCR0) */
#define S32K3XX_MU_CSSR0_OFFSET (0x0018) /* Core Sticky Status Register 0 (CSSR0) */
#define S32K3XX_MU_FCR_OFFSET (0x0100) /* Flag Control Register (FCR) */
#define S32K3XX_MU_FSR_OFFSET (0x0104) /* Flag Status Register (FSR) */
#define S32K3XX_MU_GIER_OFFSET (0x0110) /* General Interrupt Enable Register (GIER) */
#define S32K3XX_MU_GCR_OFFSET (0x0114) /* General Control Register (GCR) */
#define S32K3XX_MU_GSR_OFFSET (0x0118) /* General Status Register (GSR) */
#define S32K3XX_MU_TCR_OFFSET (0x0120) /* Transmit Control Register (TCR) */
#define S32K3XX_MU_TSR_OFFSET (0x0124) /* Transmit Status Register (TSR) */
#define S32K3XX_MU_RCR_OFFSET (0x0128) /* Receive Control Register (RCR) */
#define S32K3XX_MU_RSR_OFFSET (0x012c) /* Receive Status Register (RSR) */
#define S32K3XX_MU_TR0_OFFSET (0x0200) /* Transmit Register 0 (TR0) */
#define S32K3XX_MU_TR1_OFFSET (0x0204) /* Transmit Register 1 (TR1) */
#define S32K3XX_MU_TR2_OFFSET (0x0208) /* Transmit Register 2 (TR2) */
#define S32K3XX_MU_TR3_OFFSET (0x020c) /* Transmit Register 3 (TR3) */
#define S32K3XX_MU_RR0_OFFSET (0x0280) /* Receive Register 0 (RR0) */
#define S32K3XX_MU_RR1_OFFSET (0x0284) /* Receive Register 1 (RR1) */
#define S32K3XX_MU_RR2_OFFSET (0x0288) /* Receive Register 2 (RR2) */
#define S32K3XX_MU_RR3_OFFSET (0x028c) /* Receive Register 3 (RR3) */
/* MU Register Addresses ****************************************************/
#define S32K3XX_MU0_MUB_VER (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_VER_OFFSET)
#define S32K3XX_MU0_MUB_PAR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_PAR_OFFSET)
#define S32K3XX_MU0_MUB_CR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_CR_OFFSET)
#define S32K3XX_MU0_MUB_SR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_SR_OFFSET)
#define S32K3XX_MU0_MUB_CCR0 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_CCR0_OFFSET)
#define S32K3XX_MU0_MUB_CSSR0 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_CSSR0_OFFSET)
#define S32K3XX_MU0_MUB_FCR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_FCR_OFFSET)
#define S32K3XX_MU0_MUB_FSR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_FSR_OFFSET)
#define S32K3XX_MU0_MUB_GIER (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_GIER_OFFSET)
#define S32K3XX_MU0_MUB_GCR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_GCR_OFFSET)
#define S32K3XX_MU0_MUB_GSR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_GSR_OFFSET)
#define S32K3XX_MU0_MUB_TCR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_TCR_OFFSET)
#define S32K3XX_MU0_MUB_TSR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_TSR_OFFSET)
#define S32K3XX_MU0_MUB_RCR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_RCR_OFFSET)
#define S32K3XX_MU0_MUB_RSR (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_RSR_OFFSET)
#define S32K3XX_MU0_MUB_TR0 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_TR0_OFFSET)
#define S32K3XX_MU0_MUB_TR1 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_TR1_OFFSET)
#define S32K3XX_MU0_MUB_TR2 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_TR2_OFFSET)
#define S32K3XX_MU0_MUB_TR3 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_TR3_OFFSET)
#define S32K3XX_MU0_MUB_RR0 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_RR0_OFFSET)
#define S32K3XX_MU0_MUB_RR1 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_RR1_OFFSET)
#define S32K3XX_MU0_MUB_RR2 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_RR2_OFFSET)
#define S32K3XX_MU0_MUB_RR3 (S32K3XX_MU0_MUB_BASE + S32K3XX_MU_RR3_OFFSET)
#define S32K3XX_MU1_MUB_VER (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_VER_OFFSET)
#define S32K3XX_MU1_MUB_PAR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_PAR_OFFSET)
#define S32K3XX_MU1_MUB_CR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_CR_OFFSET)
#define S32K3XX_MU1_MUB_SR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_SR_OFFSET)
#define S32K3XX_MU1_MUB_CCR0 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_CCR0_OFFSET)
#define S32K3XX_MU1_MUB_CSSR0 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_CSSR0_OFFSET)
#define S32K3XX_MU1_MUB_FCR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_FCR_OFFSET)
#define S32K3XX_MU1_MUB_FSR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_FSR_OFFSET)
#define S32K3XX_MU1_MUB_GIER (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_GIER_OFFSET)
#define S32K3XX_MU1_MUB_GCR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_GCR_OFFSET)
#define S32K3XX_MU1_MUB_GSR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_GSR_OFFSET)
#define S32K3XX_MU1_MUB_TCR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_TCR_OFFSET)
#define S32K3XX_MU1_MUB_TSR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_TSR_OFFSET)
#define S32K3XX_MU1_MUB_RCR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_RCR_OFFSET)
#define S32K3XX_MU1_MUB_RSR (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_RSR_OFFSET)
#define S32K3XX_MU1_MUB_TR0 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_TR0_OFFSET)
#define S32K3XX_MU1_MUB_TR1 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_TR1_OFFSET)
#define S32K3XX_MU1_MUB_TR2 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_TR2_OFFSET)
#define S32K3XX_MU1_MUB_TR3 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_TR3_OFFSET)
#define S32K3XX_MU1_MUB_RR0 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_RR0_OFFSET)
#define S32K3XX_MU1_MUB_RR1 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_RR1_OFFSET)
#define S32K3XX_MU1_MUB_RR2 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_RR2_OFFSET)
#define S32K3XX_MU1_MUB_RR3 (S32K3XX_MU1_MUB_BASE + S32K3XX_MU_RR3_OFFSET)
#define S32K3XX_MU2_MUA_VER (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_VER_OFFSET)
#define S32K3XX_MU2_MUA_PAR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_PAR_OFFSET)
#define S32K3XX_MU2_MUA_CR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_CR_OFFSET)
#define S32K3XX_MU2_MUA_SR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_SR_OFFSET)
#define S32K3XX_MU2_MUA_FCR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_FCR_OFFSET)
#define S32K3XX_MU2_MUA_FSR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_FSR_OFFSET)
#define S32K3XX_MU2_MUA_GIER (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_GIER_OFFSET)
#define S32K3XX_MU2_MUA_GCR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_GCR_OFFSET)
#define S32K3XX_MU2_MUA_GSR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_GSR_OFFSET)
#define S32K3XX_MU2_MUA_TCR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_TCR_OFFSET)
#define S32K3XX_MU2_MUA_TSR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_TSR_OFFSET)
#define S32K3XX_MU2_MUA_RCR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_RCR_OFFSET)
#define S32K3XX_MU2_MUA_RSR (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_RSR_OFFSET)
#define S32K3XX_MU2_MUA_TR0 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_TR0_OFFSET)
#define S32K3XX_MU2_MUA_TR1 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_TR1_OFFSET)
#define S32K3XX_MU2_MUA_TR2 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_TR2_OFFSET)
#define S32K3XX_MU2_MUA_TR3 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_TR3_OFFSET)
#define S32K3XX_MU2_MUA_RR0 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_RR0_OFFSET)
#define S32K3XX_MU2_MUA_RR1 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_RR1_OFFSET)
#define S32K3XX_MU2_MUA_RR2 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_RR2_OFFSET)
#define S32K3XX_MU2_MUA_RR3 (S32K3XX_MU2_MUA_BASE + S32K3XX_MU_RR3_OFFSET)
#define S32K3XX_MU2_MUB_VER (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_VER_OFFSET)
#define S32K3XX_MU2_MUB_PAR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_PAR_OFFSET)
#define S32K3XX_MU2_MUB_CR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_CR_OFFSET)
#define S32K3XX_MU2_MUB_SR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_SR_OFFSET)
#define S32K3XX_MU2_MUB_CCR0 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_CCR0_OFFSET)
#define S32K3XX_MU2_MUB_CSSR0 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_CSSR0_OFFSET)
#define S32K3XX_MU2_MUB_FCR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_FCR_OFFSET)
#define S32K3XX_MU2_MUB_FSR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_FSR_OFFSET)
#define S32K3XX_MU2_MUB_GIER (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_GIER_OFFSET)
#define S32K3XX_MU2_MUB_GCR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_GCR_OFFSET)
#define S32K3XX_MU2_MUB_GSR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_GSR_OFFSET)
#define S32K3XX_MU2_MUB_TCR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_TCR_OFFSET)
#define S32K3XX_MU2_MUB_TSR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_TSR_OFFSET)
#define S32K3XX_MU2_MUB_RCR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_RCR_OFFSET)
#define S32K3XX_MU2_MUB_RSR (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_RSR_OFFSET)
#define S32K3XX_MU2_MUB_TR0 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_TR0_OFFSET)
#define S32K3XX_MU2_MUB_TR1 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_TR1_OFFSET)
#define S32K3XX_MU2_MUB_TR2 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_TR2_OFFSET)
#define S32K3XX_MU2_MUB_TR3 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_TR3_OFFSET)
#define S32K3XX_MU2_MUB_RR0 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_RR0_OFFSET)
#define S32K3XX_MU2_MUB_RR1 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_RR1_OFFSET)
#define S32K3XX_MU2_MUB_RR2 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_RR2_OFFSET)
#define S32K3XX_MU2_MUB_RR3 (S32K3XX_MU2_MUB_BASE + S32K3XX_MU_RR3_OFFSET)
/* MU Register Bitfield Definitions *****************************************/
/* Version ID Register (VER) */
#define MU_FEATURE_SHIFT (0) /* Bits 0-15: Feature Set Number (FEATURE) */
#define MU_FEATURE_MASK (0xffff << MU_FEATURE_SHIFT)
# define MU_FEATURE_STANDARD (1 << 0) /* Bit 0: Standard features are implemented */
# define MU_FEATURE_RAIP_RAIE (1 << 1) /* Bit 1: RAIP/RAIE register bits are implemented */
# define MU_FEATURE_CCR_CSSR (1 << 2) /* Bit 2: Core Control and Status Registers are implemented in both MUA and MUB */
# define MU_FEATURE_EXPAND (1 << 3) /* Bit 3: Expand TRn/RRn registers number */
#define MU_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define MU_MINOR_MASK (0xff << MU_MINOR_SHIFT)
#define MU_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define MU_MAJOR_MASK (0xff << MU_MAJOR_SHIFT)
/* Parameter Register (PAR) */
#define MU_PAR_TR_NUM_SHIFT (0) /* Bits 0-7: Transmit Register Number (TR_NUM) */
#define MU_PAR_TR_NUM_MASK (0xff << MU_PAR_TR_NUM_SHIFT)
#define MU_PAR_RR_NUM_SHIFT (8) /* Bits 8-15: Receive Register Number (RR_NUM) */
#define MU_PAR_RR_NUM_MASK (0xff << MU_PAR_RR_NUM_SHIFT)
#define MU_PAR_GIR_NUM_SHIFT (16) /* Bits 16-23: General Interrupt Request Number (GIR_NUM) */
#define MU_PAR_GIR_NUM_MASK (0xff << MU_PAR_GIR_NUM_SHIFT)
#define MU_PAR_FLAG_WIDTH_SHIFT (24) /* Bits 24-31: Flag Width (FLAG_WIDTH) */
#define MU_PAR_FLAG_WIDTH_MASK (0xff << MU_PAR_FLAG_WIDTH_SHIFT)
/* Control Register (CR) */
#define MU_CR_MUR (1 << 0) /* Bit 0: MUA and MUB Reset (MUR) */
#define MU_CR_MURIE (1 << 1) /* Bit 1: MU Reset Interrupt Enable (MURIE) */
/* Bits 2-31: Reserved */
/* Status Register (SR) */
#define MU_SR_MURS (1 << 0) /* Bit 0: MUA and MUB Reset State (MURS) */
#define MU_SR_MURIP (1 << 1) /* Bit 1: MU Reset Interrupt Pending (MURIP) */
#define MU_SR_EP (1 << 2) /* Bit 2: MU Side Event Pending (EP) */
#define MU_SR_FUP (1 << 3) /* Bit 3: MU Flags Update Pending (FUP) */
#define MU_SR_GIRP (1 << 4) /* Bit 4: MU General Interrupt Pending (GIRP) */
#define MU_SR_TEP (1 << 5) /* Bit 5: MU Transmit Empty Pending (TEP) */
#define MU_SR_RFP (1 << 6) /* Bit 6: MU Receive Full Pending Flag (RFP) */
/* Bits 7-31: Reserved */
/* Core Control Register 0 (CCR0) */
#define MU_CCR0_NMI (1 << 0) /* Bit 0: MUA Non-maskable Interrupt Request */
/* Bits 1-31: Reserved */
/* Core Sticky Status Register 0 (CSSR0) */
#define MU_CSSR0_NMIC (1 << 0) /* Bit 0: Processor B Non-Maskable-Interrupt Clear */
/* Bits 1-31: Reserved */
/* Flag Control Register (FCR) */
#define MU_FCR_F(n) (1 << (n)) /* Bit n: MUA/MUB to MUB/MUA Flag n (Fn) */
#define MU_FCR_F0 (1 << 0) /* Bit 0: MUA/MUB to MUB/MUA Flag 0 (F0) */
#define MU_FCR_F1 (1 << 1) /* Bit 1: MUA/MUB to MUB/MUA Flag 1 (F1) */
#define MU_FCR_F2 (1 << 2) /* Bit 2: MUA/MUB to MUB/MUA Flag 2 (F2) */
#define MU_FCR_F3 (1 << 3) /* Bit 3: MUB to MUA Flag 3 (F3) */
#define MU_FCR_F4 (1 << 4) /* Bit 4: MUB to MUA Flag 4 (F4) */
#define MU_FCR_F5 (1 << 5) /* Bit 5: MUB to MUA Flag 5 (F5) */
#define MU_FCR_F6 (1 << 6) /* Bit 6: MUB to MUA Flag 6 (F6) */
#define MU_FCR_F7 (1 << 7) /* Bit 7: MUB to MUA Flag 7 (F7) */
#define MU_FCR_F8 (1 << 8) /* Bit 8: MUB to MUA Flag 8 (F8) */
#define MU_FCR_F9 (1 << 9) /* Bit 9: MUB to MUA Flag 9 (F9) */
#define MU_FCR_F10 (1 << 10) /* Bit 10: MUB to MUA Flag 10 (F10) */
#define MU_FCR_F11 (1 << 11) /* Bit 11: MUB to MUA Flag 11 (F11) */
#define MU_FCR_F12 (1 << 12) /* Bit 12: MUB to MUA Flag 12 (F12) */
#define MU_FCR_F13 (1 << 13) /* Bit 13: MUB to MUA Flag 13 (F13) */
#define MU_FCR_F14 (1 << 14) /* Bit 14: MUB to MUA Flag 14 (F14) */
#define MU_FCR_F15 (1 << 15) /* Bit 15: MUB to MUA Flag 15 (F15) */
#define MU_FCR_F16 (1 << 16) /* Bit 16: MUB to MUA Flag 16 (F16) */
#define MU_FCR_F17 (1 << 17) /* Bit 17: MUB to MUA Flag 17 (F17) */
#define MU_FCR_F18 (1 << 18) /* Bit 18: MUB to MUA Flag 18 (F18) */
#define MU_FCR_F19 (1 << 19) /* Bit 19: MUB to MUA Flag 19 (F19) */
#define MU_FCR_F20 (1 << 20) /* Bit 20: MUB to MUA Flag 20 (F20) */
#define MU_FCR_F21 (1 << 21) /* Bit 21: MUB to MUA Flag 21 (F21) */
#define MU_FCR_F22 (1 << 22) /* Bit 22: MUB to MUA Flag 22 (F22) */
#define MU_FCR_F23 (1 << 23) /* Bit 23: MUB to MUA Flag 23 (F23) */
#define MU_FCR_F24 (1 << 24) /* Bit 24: MUB to MUA Flag 24 (F24) */
#define MU_FCR_F25 (1 << 25) /* Bit 25: MUB to MUA Flag 25 (F25) */
#define MU_FCR_F26 (1 << 26) /* Bit 26: MUB to MUA Flag 26 (F26) */
#define MU_FCR_F27 (1 << 27) /* Bit 27: MUB to MUA Flag 27 (F27) */
#define MU_FCR_F28 (1 << 28) /* Bit 28: MUB to MUA Flag 28 (F28) */
#define MU_FCR_F29 (1 << 29) /* Bit 29: MUB to MUA Flag 29 (F29) */
#define MU_FCR_F30 (1 << 30) /* Bit 30: MUB to MUA Flag 30 (F30) */
#define MU_FCR_F31 (1 << 31) /* Bit 31: MUB to MUA Flag 31 (F31) */
/* Flag Status Register (FSR) */
#define MU_FSR_F(n) (1 << (n)) /* Bit n: MUB/MUA to MUA/MUB Side Flag n (Fn) */
#define MU_FSR_F0 (1 << 0) /* Bit 0: MUB/MUA to MUA/MUB Side Flag 0 (F0) */
#define MU_FSR_F1 (1 << 1) /* Bit 1: MUB/MUA to MUA/MUB Side Flag 1 (F1) */
#define MU_FSR_F2 (1 << 2) /* Bit 2: MUB/MUA to MUA/MUB Side Flag 2 (F2) */
#define MU_FSR_F3 (1 << 3) /* Bit 3: MUA to MUB Side Flag 3 (F3) */
#define MU_FSR_F4 (1 << 4) /* Bit 4: MUA to MUB Side Flag 4 (F4) */
#define MU_FSR_F5 (1 << 5) /* Bit 5: MUA to MUB Side Flag 5 (F5) */
#define MU_FSR_F6 (1 << 6) /* Bit 6: MUA to MUB Side Flag 6 (F6) */
#define MU_FSR_F7 (1 << 7) /* Bit 7: MUA to MUB Side Flag 7 (F7) */
#define MU_FSR_F8 (1 << 8) /* Bit 8: MUA to MUB Side Flag 8 (F8) */
#define MU_FSR_F9 (1 << 9) /* Bit 9: MUA to MUB Side Flag 9 (F9) */
#define MU_FSR_F10 (1 << 10) /* Bit 10: MUA to MUB Side Flag 10 (F10) */
#define MU_FSR_F11 (1 << 11) /* Bit 11: MUA to MUB Side Flag 11 (F11) */
#define MU_FSR_F12 (1 << 12) /* Bit 12: MUA to MUB Side Flag 12 (F12) */
#define MU_FSR_F13 (1 << 13) /* Bit 13: MUA to MUB Side Flag 13 (F13) */
#define MU_FSR_F14 (1 << 14) /* Bit 14: MUA to MUB Side Flag 14 (F14) */
#define MU_FSR_F15 (1 << 15) /* Bit 15: MUA to MUB Side Flag 15 (F15) */
#define MU_FSR_F16 (1 << 16) /* Bit 16: MUA to MUB Side Flag 16 (F16) */
#define MU_FSR_F17 (1 << 17) /* Bit 17: MUA to MUB Side Flag 17 (F17) */
#define MU_FSR_F18 (1 << 18) /* Bit 18: MUA to MUB Side Flag 18 (F18) */
#define MU_FSR_F19 (1 << 19) /* Bit 19: MUA to MUB Side Flag 19 (F19) */
#define MU_FSR_F20 (1 << 20) /* Bit 20: MUA to MUB Side Flag 20 (F20) */
#define MU_FSR_F21 (1 << 21) /* Bit 21: MUA to MUB Side Flag 21 (F21) */
#define MU_FSR_F22 (1 << 22) /* Bit 22: MUA to MUB Side Flag 22 (F22) */
#define MU_FSR_F23 (1 << 23) /* Bit 23: MUA to MUB Side Flag 23 (F23) */
#define MU_FSR_F24 (1 << 24) /* Bit 24: MUA to MUB Side Flag 24 (F24) */
#define MU_FSR_F25 (1 << 25) /* Bit 25: MUA to MUB Side Flag 25 (F25) */
#define MU_FSR_F26 (1 << 26) /* Bit 26: MUA to MUB Side Flag 26 (F26) */
#define MU_FSR_F27 (1 << 27) /* Bit 27: MUA to MUB Side Flag 27 (F27) */
#define MU_FSR_F28 (1 << 28) /* Bit 28: MUA to MUB Side Flag 28 (F28) */
#define MU_FSR_F29 (1 << 29) /* Bit 29: MUA to MUB Side Flag 29 (F29) */
#define MU_FSR_F30 (1 << 30) /* Bit 30: MUA to MUB Side Flag 30 (F30) */
#define MU_FSR_F31 (1 << 31) /* Bit 31: MUA to MUB Side Flag 31 (F31) */
/* General Interrupt Enable Register (GIER) */
#define MU_GIER_GIE(n) (1 << (n)) /* Bit n: MUA/MUB General Purpose Interrupt Enable n (GIEn) */
#define MU_GIER_GIE0 (1 << 0) /* Bit 0: MUA/MUB General Purpose Interrupt Enable 0 (GIE0) */
#define MU_GIER_GIE1 (1 << 1) /* Bit 1: MUB General Purpose Interrupt Enable 1 (GIE1) */
#define MU_GIER_GIE2 (1 << 2) /* Bit 2: MUB General Purpose Interrupt Enable 2 (GIE2) */
#define MU_GIER_GIE3 (1 << 3) /* Bit 3: MUB General Purpose Interrupt Enable 3 (GIE3) */
#define MU_GIER_GIE4 (1 << 4) /* Bit 4: MUB General Purpose Interrupt Enable 4 (GIE4) */
#define MU_GIER_GIE5 (1 << 5) /* Bit 5: MUB General Purpose Interrupt Enable 5 (GIE5) */
#define MU_GIER_GIE6 (1 << 6) /* Bit 6: MUB General Purpose Interrupt Enable 6 (GIE6) */
#define MU_GIER_GIE7 (1 << 7) /* Bit 7: MUB General Purpose Interrupt Enable 7 (GIE7) */
#define MU_GIER_GIE8 (1 << 8) /* Bit 8: MUB General Purpose Interrupt Enable 8 (GIE8) */
#define MU_GIER_GIE9 (1 << 9) /* Bit 9: MUB General Purpose Interrupt Enable 9 (GIE9) */
#define MU_GIER_GIE10 (1 << 10) /* Bit 10: MUB General Purpose Interrupt Enable 10 (GIE10) */
#define MU_GIER_GIE11 (1 << 11) /* Bit 11: MUB General Purpose Interrupt Enable 11 (GIE11) */
#define MU_GIER_GIE12 (1 << 12) /* Bit 12: MUB General Purpose Interrupt Enable 12 (GIE12) */
#define MU_GIER_GIE13 (1 << 13) /* Bit 13: MUB General Purpose Interrupt Enable 13 (GIE13) */
#define MU_GIER_GIE14 (1 << 14) /* Bit 14: MUB General Purpose Interrupt Enable 14 (GIE14) */
#define MU_GIER_GIE15 (1 << 15) /* Bit 15: MUB General Purpose Interrupt Enable 15 (GIE15) */
#define MU_GIER_GIE16 (1 << 16) /* Bit 16: MUB General Purpose Interrupt Enable 16 (GIE16) */
#define MU_GIER_GIE17 (1 << 17) /* Bit 17: MUB General Purpose Interrupt Enable 17 (GIE17) */
#define MU_GIER_GIE18 (1 << 18) /* Bit 18: MUB General Purpose Interrupt Enable 18 (GIE18) */
#define MU_GIER_GIE19 (1 << 19) /* Bit 19: MUB General Purpose Interrupt Enable 19 (GIE19) */
#define MU_GIER_GIE20 (1 << 20) /* Bit 20: MUB General Purpose Interrupt Enable 20 (GIE20) */
#define MU_GIER_GIE21 (1 << 21) /* Bit 21: MUB General Purpose Interrupt Enable 21 (GIE21) */
#define MU_GIER_GIE22 (1 << 22) /* Bit 22: MUB General Purpose Interrupt Enable 22 (GIE22) */
#define MU_GIER_GIE23 (1 << 23) /* Bit 23: MUB General Purpose Interrupt Enable 23 (GIE23) */
#define MU_GIER_GIE24 (1 << 24) /* Bit 24: MUB General Purpose Interrupt Enable 24 (GIE24) */
#define MU_GIER_GIE25 (1 << 25) /* Bit 25: MUB General Purpose Interrupt Enable 25 (GIE25) */
#define MU_GIER_GIE26 (1 << 26) /* Bit 26: MUB General Purpose Interrupt Enable 26 (GIE26) */
#define MU_GIER_GIE27 (1 << 27) /* Bit 27: MUB General Purpose Interrupt Enable 27 (GIE27) */
#define MU_GIER_GIE28 (1 << 28) /* Bit 28: MUB General Purpose Interrupt Enable 28 (GIE28) */
#define MU_GIER_GIE29 (1 << 29) /* Bit 29: MUB General Purpose Interrupt Enable 29 (GIE29) */
#define MU_GIER_GIE30 (1 << 30) /* Bit 30: MUB General Purpose Interrupt Enable 30 (GIE30) */
#define MU_GIER_GIE31 (1 << 31) /* Bit 31: MUB General Purpose Interrupt Enable 31 (GIE31) */
/* General Control Register (GCR) */
#define MU_GCR_GIR(n) (1 << (n)) /* Bit n: MUA/MUB General Purpose Interrupt Request n (GIRn) */
#define MU_GCR_GIR0 (1 << 0) /* Bit 0: MUA/MUB General Purpose Interrupt Request 0 (GIR0) */
#define MU_GCR_GIR1 (1 << 1) /* Bit 1: MUB General Purpose Interrupt Request 1 (GIR1) */
#define MU_GCR_GIR2 (1 << 2) /* Bit 2: MUB General Purpose Interrupt Request 2 (GIR2) */
#define MU_GCR_GIR3 (1 << 3) /* Bit 3: MUB General Purpose Interrupt Request 3 (GIR3) */
#define MU_GCR_GIR4 (1 << 4) /* Bit 4: MUB General Purpose Interrupt Request 4 (GIR4) */
#define MU_GCR_GIR5 (1 << 5) /* Bit 5: MUB General Purpose Interrupt Request 5 (GIR5) */
#define MU_GCR_GIR6 (1 << 6) /* Bit 6: MUB General Purpose Interrupt Request 6 (GIR6) */
#define MU_GCR_GIR7 (1 << 7) /* Bit 7: MUB General Purpose Interrupt Request 7 (GIR7) */
#define MU_GCR_GIR8 (1 << 8) /* Bit 8: MUB General Purpose Interrupt Request 8 (GIR8) */
#define MU_GCR_GIR9 (1 << 9) /* Bit 9: MUB General Purpose Interrupt Request 9 (GIR9) */
#define MU_GCR_GIR10 (1 << 10) /* Bit 10: MUB General Purpose Interrupt Request 10 (GIR10) */
#define MU_GCR_GIR11 (1 << 11) /* Bit 11: MUB General Purpose Interrupt Request 11 (GIR11) */
#define MU_GCR_GIR12 (1 << 12) /* Bit 12: MUB General Purpose Interrupt Request 12 (GIR12) */
#define MU_GCR_GIR13 (1 << 13) /* Bit 13: MUB General Purpose Interrupt Request 13 (GIR13) */
#define MU_GCR_GIR14 (1 << 14) /* Bit 14: MUB General Purpose Interrupt Request 14 (GIR14) */
#define MU_GCR_GIR15 (1 << 15) /* Bit 15: MUB General Purpose Interrupt Request 15 (GIR15) */
#define MU_GCR_GIR16 (1 << 16) /* Bit 16: MUB General Purpose Interrupt Request 16 (GIR16) */
#define MU_GCR_GIR17 (1 << 17) /* Bit 17: MUB General Purpose Interrupt Request 17 (GIR17) */
#define MU_GCR_GIR18 (1 << 18) /* Bit 18: MUB General Purpose Interrupt Request 18 (GIR18) */
#define MU_GCR_GIR19 (1 << 19) /* Bit 19: MUB General Purpose Interrupt Request 19 (GIR19) */
#define MU_GCR_GIR20 (1 << 20) /* Bit 20: MUB General Purpose Interrupt Request 20 (GIR20) */
#define MU_GCR_GIR21 (1 << 21) /* Bit 21: MUB General Purpose Interrupt Request 21 (GIR21) */
#define MU_GCR_GIR22 (1 << 22) /* Bit 22: MUB General Purpose Interrupt Request 22 (GIR22) */
#define MU_GCR_GIR23 (1 << 23) /* Bit 23: MUB General Purpose Interrupt Request 23 (GIR23) */
#define MU_GCR_GIR24 (1 << 24) /* Bit 24: MUB General Purpose Interrupt Request 24 (GIR24) */
#define MU_GCR_GIR25 (1 << 25) /* Bit 25: MUB General Purpose Interrupt Request 25 (GIR25) */
#define MU_GCR_GIR26 (1 << 26) /* Bit 26: MUB General Purpose Interrupt Request 26 (GIR26) */
#define MU_GCR_GIR27 (1 << 27) /* Bit 27: MUB General Purpose Interrupt Request 27 (GIR27) */
#define MU_GCR_GIR28 (1 << 28) /* Bit 28: MUB General Purpose Interrupt Request 28 (GIR28) */
#define MU_GCR_GIR29 (1 << 29) /* Bit 29: MUB General Purpose Interrupt Request 29 (GIR29) */
#define MU_GCR_GIR30 (1 << 30) /* Bit 30: MUB General Purpose Interrupt Request 30 (GIR30) */
#define MU_GCR_GIR31 (1 << 31) /* Bit 31: MUB General Purpose Interrupt Request 31 (GIR31) */
/* General Status Register (GSR) */
#define MU_GSR_GIP(n) (1 << (n)) /* Bit n: MUA/MUB General Interrupt Request Pending n (GIPn) */
#define MU_GSR_GIP0 (1 << 0) /* Bit 0: MUA/MUB General Interrupt Request Pending 0 (GIP0) */
#define MU_GSR_GIP1 (1 << 1) /* Bit 1: MUB General Interrupt Request Pending 1 (GIP1) */
#define MU_GSR_GIP2 (1 << 2) /* Bit 2: MUB General Interrupt Request Pending 2 (GIP2) */
#define MU_GSR_GIP3 (1 << 3) /* Bit 3: MUB General Interrupt Request Pending 3 (GIP3) */
#define MU_GSR_GIP4 (1 << 4) /* Bit 4: MUB General Interrupt Request Pending 4 (GIP4) */
#define MU_GSR_GIP5 (1 << 5) /* Bit 5: MUB General Interrupt Request Pending 5 (GIP5) */
#define MU_GSR_GIP6 (1 << 6) /* Bit 6: MUB General Interrupt Request Pending 6 (GIP6) */
#define MU_GSR_GIP7 (1 << 7) /* Bit 7: MUB General Interrupt Request Pending 7 (GIP7) */
#define MU_GSR_GIP8 (1 << 8) /* Bit 8: MUB General Interrupt Request Pending 8 (GIP8) */
#define MU_GSR_GIP9 (1 << 9) /* Bit 9: MUB General Interrupt Request Pending 9 (GIP9) */
#define MU_GSR_GIP10 (1 << 10) /* Bit 10: MUB General Interrupt Request Pending 10 (GIP10) */
#define MU_GSR_GIP11 (1 << 11) /* Bit 11: MUB General Interrupt Request Pending 11 (GIP11) */
#define MU_GSR_GIP12 (1 << 12) /* Bit 12: MUB General Interrupt Request Pending 12 (GIP12) */
#define MU_GSR_GIP13 (1 << 13) /* Bit 13: MUB General Interrupt Request Pending 13 (GIP13) */
#define MU_GSR_GIP14 (1 << 14) /* Bit 14: MUB General Interrupt Request Pending 14 (GIP14) */
#define MU_GSR_GIP15 (1 << 15) /* Bit 15: MUB General Interrupt Request Pending 15 (GIP15) */
#define MU_GSR_GIP16 (1 << 16) /* Bit 16: MUB General Interrupt Request Pending 16 (GIP16) */
#define MU_GSR_GIP17 (1 << 17) /* Bit 17: MUB General Interrupt Request Pending 17 (GIP17) */
#define MU_GSR_GIP18 (1 << 18) /* Bit 18: MUB General Interrupt Request Pending 18 (GIP18) */
#define MU_GSR_GIP19 (1 << 19) /* Bit 19: MUB General Interrupt Request Pending 19 (GIP19) */
#define MU_GSR_GIP20 (1 << 20) /* Bit 20: MUB General Interrupt Request Pending 20 (GIP20) */
#define MU_GSR_GIP21 (1 << 21) /* Bit 21: MUB General Interrupt Request Pending 21 (GIP21) */
#define MU_GSR_GIP22 (1 << 22) /* Bit 22: MUB General Interrupt Request Pending 22 (GIP22) */
#define MU_GSR_GIP23 (1 << 23) /* Bit 23: MUB General Interrupt Request Pending 23 (GIP23) */
#define MU_GSR_GIP24 (1 << 24) /* Bit 24: MUB General Interrupt Request Pending 24 (GIP24) */
#define MU_GSR_GIP25 (1 << 25) /* Bit 25: MUB General Interrupt Request Pending 25 (GIP25) */
#define MU_GSR_GIP26 (1 << 26) /* Bit 26: MUB General Interrupt Request Pending 26 (GIP26) */
#define MU_GSR_GIP27 (1 << 27) /* Bit 27: MUB General Interrupt Request Pending 27 (GIP27) */
#define MU_GSR_GIP28 (1 << 28) /* Bit 28: MUB General Interrupt Request Pending 28 (GIP28) */
#define MU_GSR_GIP29 (1 << 29) /* Bit 29: MUB General Interrupt Request Pending 29 (GIP29) */
#define MU_GSR_GIP30 (1 << 30) /* Bit 30: MUB General Interrupt Request Pending 30 (GIP30) */
#define MU_GSR_GIP31 (1 << 31) /* Bit 31: MUB General Interrupt Request Pending 31 (GIP31) */
/* Transmit Control Register (TCR) */
#define MU_TCR_TIE_SHIFT (0) /* Bits 0-3: MU Transmit Interrupt Enable n (TIEn) */
#define MU_TCR_TIE_MASK (0x0f << MU_TCR_TIE_SHIFT)
# define MU_TCR_TIE0 (1 << 0) /* Bit 0: MU Transmit Interrupt Enable 0 (TIE0) */
# define MU_TCR_TIE1 (1 << 1) /* Bit 1: MU Transmit Interrupt Enable 1 (TIE1) */
# define MU_TCR_TIE2 (1 << 2) /* Bit 2: MU Transmit Interrupt Enable 2 (TIE2) */
# define MU_TCR_TIE3 (1 << 3) /* Bit 3: MU Transmit Interrupt Enable 3 (TIE3) */
/* Bits 4-31: Reserved */
/* Transmit Status Register (TSR) */
#define MU_TSR_TE_SHIFT (0) /* Bits 0-3: MU Transmit Register n Empty (TEn) */
#define MU_TSR_TE_MASK (0x0f << MU_TSR_TE_SHIFT)
# define MU_TSR_TE0 (1 << 0) /* Bit 0: MU Transmit Register 0 Empty (TE0) */
# define MU_TSR_TE1 (1 << 1) /* Bit 1: MU Transmit Register 1 Empty (TE1) */
# define MU_TSR_TE2 (1 << 2) /* Bit 2: MU Transmit Register 2 Empty (TE2) */
# define MU_TSR_TE3 (1 << 3) /* Bit 3: MU Transmit Register 3 Empty (TE3) */
/* Bits 4-31: Reserved */
/* Receive Control Register (RCR) */
#define MU_RCR_RIE_SHIFT (0) /* Bits 0-3: MU Receive Interrupt Enable n (RIEn) */
#define MU_RCR_RIE_MASK (0x0f << MU_RCR_RIE_SHIFT)
# define MU_RCR_RIE0 (1 << 0) /* Bit 0: MUA Receive Interrupt Enable 0 (RIE0) */
# define MU_RCR_RIE1 (1 << 1) /* Bit 1: MUA Receive Interrupt Enable 1 (RIE1) */
# define MU_RCR_RIE2 (1 << 2) /* Bit 2: MUA Receive Interrupt Enable 2 (RIE2) */
# define MU_RCR_RIE3 (1 << 3) /* Bit 3: MUA Receive Interrupt Enable 3 (RIE3) */
/* Bits 4-31: Reserved */
/* Receive Status Register (RSR) */
#define MU_RSR_RF_SHIFT (0) /* Bits 0-3: MU Receive Register n Full (RFn) */
#define MU_RSR_RF_MASK (0x0f << MU_RSR_RF_SHIFT)
# define MU_RSR_RF0 (1 << 0) /* Bit 0: MUA Receive Register 0 Full (RF0) */
# define MU_RSR_RF1 (1 << 1) /* Bit 1: MUA Receive Register 1 Full (RF1) */
# define MU_RSR_RF2 (1 << 2) /* Bit 2: MUA Receive Register 2 Full (RF2) */
# define MU_RSR_RF3 (1 << 3) /* Bit 3: MUA Receive Register 3 Full (RF3) */
/* Bits 4-31: Reserved */
/* Transmit Register (TRn) */
#define MU_TR_DATA_SHIFT (0) /* Bits 0-31: MU Transmit Data (TR_DATA) */
#define MU_TR_DATA_MASK (0xffffffff << MU_TR_DATA_SHIFT)
/* Receive Register (RRn) */
#define MU_RR_DATA_SHIFT (0) /* Bits 0-31: MU Receive Data (RR_DATA) */
#define MU_RR_DATA_MASK (0xffffffff << MU_RR_DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_MU_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_pflash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PFLASH_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PFLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PFLASH Register Offsets **************************************************/
#define S32K3XX_PFLASH_PFCR0_OFFSET (0x0000) /* Platform Flash Memory Configuration Register 0 (PFCR0) */
#define S32K3XX_PFLASH_PFCR1_OFFSET (0x0004) /* Platform Flash Memory Configuration Register 1 (PFCR1) */
#define S32K3XX_PFLASH_PFCR2_OFFSET (0x0008) /* Platform Flash Memory Configuration Register 2 (PFCR2) */
#define S32K3XX_PFLASH_PFCR4_OFFSET (0x0010) /* Platform Flash Memory Configuration Register 4 (PFCR4) */
#define S32K3XX_PFLASH_PFAPR_OFFSET (0x0014) /* Platform Flash Memory Access Protection Register (PFAPR) */
#define S32K3XX_PFLASH_PFCPGM_PEADR_L_OFFSET (0x0300) /* Platform Flash Memory Program Erase Address Logical (PFCPGM_PEADR_L) */
#define S32K3XX_PFLASH_PFCPGM_PEADR_P_OFFSET (0x0304) /* Platform Flash Memory Program Erase Address Physical (PFCPGM_PEADR_P) */
#define S32K3XX_PFLASH_PFCPGM_XPEADR_L_OFFSET (0x0308) /* Platform Flash Memory Express Program Erase Address Logical (PFCPGM_XPEADR_L) */
#define S32K3XX_PFLASH_PFCPGM_XPEADR_P_OFFSET (0x030c) /* Platform Flash Memory Express Program Erase Address Physical (PFCPGM_XPEADR_P) */
#define S32K3XX_PFLASH_PFCBLK0_SPELOCK_OFFSET (0x0340) /* Block 0 Sector Program Erase Lock (PFCBLK0_SPELOCK) */
#define S32K3XX_PFLASH_PFCBLK1_SPELOCK_OFFSET (0x0344) /* Block 1 Sector Program Erase Lock (PFCBLK1_SPELOCK) */
#define S32K3XX_PFLASH_PFCBLK2_SPELOCK_OFFSET (0x0348) /* Block 2 Sector Program Erase Lock (PFCBLK2_SPELOCK) */
#define S32K3XX_PFLASH_PFCBLK3_SPELOCK_OFFSET (0x034c) /* Block 3 Sector Program Erase Lock (PFCBLK3_SPELOCK) */
#define S32K3XX_PFLASH_PFCBLK4_SPELOCK_OFFSET (0x0350) /* Block 4 Sector Program Erase Lock (PFCBLK4_SPELOCK) */
#define S32K3XX_PFLASH_PFCBLKU_SPELOCK_OFFSET (0x0358) /* Block UTEST Sector Program Erase Lock (PFCBLKU_SPELOCK) */
#define S32K3XX_PFLASH_PFCBLK0_SSPELOCK_OFFSET (0x035c) /* Block 0 Super Sector Program Erase Lock (PFCBLK0_SSPELOCK) */
#define S32K3XX_PFLASH_PFCBLK1_SSPELOCK_OFFSET (0x0360) /* Block 1 Super Sector Program Erase Lock (PFCBLK1_SSPELOCK) */
#define S32K3XX_PFLASH_PFCBLK2_SSPELOCK_OFFSET (0x0364) /* Block 2 Super Sector Program Erase Lock (PFCBLK2_SSPELOCK) */
#define S32K3XX_PFLASH_PFCBLK3_SSPELOCK_OFFSET (0x0368) /* Block 3 Super Sector Program Erase Lock (PFCBLK3_SSPELOCK) */
#define S32K3XX_PFLASH_PFCBLK0_SETSLOCK_OFFSET (0x0380) /* Block 0 Set Sector Lock (PFCBLK0_SETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK1_SETSLOCK_OFFSET (0x0384) /* Block 1 Set Sector Lock (PFCBLK1_SETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK2_SETSLOCK_OFFSET (0x0388) /* Block 2 Set Sector Lock (PFCBLK2_SETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK3_SETSLOCK_OFFSET (0x038c) /* Block 3 Set Sector Lock (PFCBLK3_SETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK4_SETSLOCK_OFFSET (0x0390) /* Block 4 Set Sector Lock (PFCBLK4_SETSLOCK) */
#define S32K3XX_PFLASH_PFCBLKU_SETSLOCK_OFFSET (0x0398) /* Block UTEST Set Sector Lock (PFCBLKU_SETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK0_SSETSLOCK_OFFSET (0x039c) /* Block 0 Set Super Sector Lock (PFCBLK0_SSETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK1_SSETSLOCK_OFFSET (0x03a0) /* Block 1 Set Super Sector Lock (PFCBLK1_SSETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK2_SSETSLOCK_OFFSET (0x03a4) /* Block 2 Set Super Sector Lock (PFCBLK2_SSETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK3_SSETSLOCK_OFFSET (0x03a8) /* Block 3 Set Super Sector Lock (PFCBLK3_SSETSLOCK) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S0_OFFSET (0x03c0) /* Block 0 Lock Master Sector 0 (PFCBLK0_LOCKMASTER_S0) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S1_OFFSET (0x03c4) /* Block 0 Lock Master Sector 1 (PFCBLK0_LOCKMASTER_S1) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S2_OFFSET (0x03c8) /* Block 0 Lock Master Sector 2 (PFCBLK0_LOCKMASTER_S2) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S3_OFFSET (0x03cc) /* Block 0 Lock Master Sector 3 (PFCBLK0_LOCKMASTER_S3) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S4_OFFSET (0x03d0) /* Block 0 Lock Master Sector 4 (PFCBLK0_LOCKMASTER_S4) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S5_OFFSET (0x03d4) /* Block 0 Lock Master Sector 5 (PFCBLK0_LOCKMASTER_S5) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S6_OFFSET (0x03d8) /* Block 0 Lock Master Sector 6 (PFCBLK0_LOCKMASTER_S6) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S7_OFFSET (0x03dc) /* Block 0 Lock Master Sector 7 (PFCBLK0_LOCKMASTER_S7) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S0_OFFSET (0x03e0) /* Block 1 Lock Master Sector 0 (PFCBLK1_LOCKMASTER_S0) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S1_OFFSET (0x03e4) /* Block 1 Lock Master Sector 1 (PFCBLK1_LOCKMASTER_S1) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S2_OFFSET (0x03e8) /* Block 1 Lock Master Sector 2 (PFCBLK1_LOCKMASTER_S2) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S3_OFFSET (0x03ec) /* Block 1 Lock Master Sector 3 (PFCBLK1_LOCKMASTER_S3) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S4_OFFSET (0x03f0) /* Block 1 Lock Master Sector 4 (PFCBLK1_LOCKMASTER_S4) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S5_OFFSET (0x03f4) /* Block 1 Lock Master Sector 5 (PFCBLK1_LOCKMASTER_S5) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S6_OFFSET (0x03f8) /* Block 1 Lock Master Sector 6 (PFCBLK1_LOCKMASTER_S6) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S7_OFFSET (0x03fc) /* Block 1 Lock Master Sector 7 (PFCBLK1_LOCKMASTER_S7) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S0_OFFSET (0x0400) /* Block 2 Lock Master Sector 0 (PFCBLK2_LOCKMASTER_S0) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S1_OFFSET (0x0404) /* Block 2 Lock Master Sector 1 (PFCBLK2_LOCKMASTER_S1) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S2_OFFSET (0x0408) /* Block 2 Lock Master Sector 2 (PFCBLK2_LOCKMASTER_S2) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S3_OFFSET (0x040c) /* Block 2 Lock Master Sector 3 (PFCBLK2_LOCKMASTER_S3) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S4_OFFSET (0x0410) /* Block 2 Lock Master Sector 4 (PFCBLK2_LOCKMASTER_S4) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S5_OFFSET (0x0414) /* Block 2 Lock Master Sector 5 (PFCBLK2_LOCKMASTER_S5) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S6_OFFSET (0x0418) /* Block 2 Lock Master Sector 6 (PFCBLK2_LOCKMASTER_S6) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S7_OFFSET (0x041c) /* Block 2 Lock Master Sector 7 (PFCBLK2_LOCKMASTER_S7) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S0_OFFSET (0x0420) /* Block 3 Lock Master Sector 0 (PFCBLK3_LOCKMASTER_S0) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S1_OFFSET (0x0424) /* Block 3 Lock Master Sector 1 (PFCBLK3_LOCKMASTER_S1) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S2_OFFSET (0x0428) /* Block 3 Lock Master Sector 2 (PFCBLK3_LOCKMASTER_S2) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S3_OFFSET (0x042c) /* Block 3 Lock Master Sector 3 (PFCBLK3_LOCKMASTER_S3) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S4_OFFSET (0x0430) /* Block 3 Lock Master Sector 4 (PFCBLK3_LOCKMASTER_S4) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S5_OFFSET (0x0434) /* Block 3 Lock Master Sector 5 (PFCBLK3_LOCKMASTER_S5) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S6_OFFSET (0x0438) /* Block 3 Lock Master Sector 6 (PFCBLK3_LOCKMASTER_S6) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S7_OFFSET (0x043c) /* Block 3 Lock Master Sector 7 (PFCBLK3_LOCKMASTER_S7) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S0_OFFSET (0x0440) /* Block 4 Lock Master Sector 0 (PFCBLK4_LOCKMASTER_S0) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S1_OFFSET (0x0444) /* Block 4 Lock Master Sector 1 (PFCBLK4_LOCKMASTER_S1) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S2_OFFSET (0x0448) /* Block 4 Lock Master Sector 2 (PFCBLK4_LOCKMASTER_S2) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S3_OFFSET (0x044c) /* Block 4 Lock Master Sector 3 (PFCBLK4_LOCKMASTER_S3) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S4_OFFSET (0x0450) /* Block 4 Lock Master Sector 4 (PFCBLK4_LOCKMASTER_S4) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S5_OFFSET (0x0454) /* Block 4 Lock Master Sector 5 (PFCBLK4_LOCKMASTER_S5) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S6_OFFSET (0x0458) /* Block 4 Lock Master Sector 6 (PFCBLK4_LOCKMASTER_S6) */
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S7_OFFSET (0x045c) /* Block 4 Lock Master Sector 7 (PFCBLK4_LOCKMASTER_S7) */
#define S32K3XX_PFLASH_PFCBLKU_LOCKMASTER_S_OFFSET (0x0480) /* Block UTEST Lock Master Sector (PFCBLKU_LOCKMASTER_S) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS0_OFFSET (0x0484) /* Block 0 Lock Master Super Sector 0 (PFCBLK0_LOCKMASTER_SS0) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS1_OFFSET (0x0488) /* Block 0 Lock Master Super Sector 1 (PFCBLK0_LOCKMASTER_SS1) */
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS2_OFFSET (0x048c) /* Block 0 Lock Master Super Sector 2 (PFCBLK0_LOCKMASTER_SS2) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS0_OFFSET (0x0494) /* Block 1 Lock Master Super Sector 0 (PFCBLK1_LOCKMASTER_SS0) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS1_OFFSET (0x0498) /* Block 1 Lock Master Super Sector 1 (PFCBLK1_LOCKMASTER_SS1) */
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS2_OFFSET (0x049c) /* Block 1 Lock Master Super Sector 2 (PFCBLK1_LOCKMASTER_SS2) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS0_OFFSET (0x04a4) /* Block 2 Lock Master Super Sector 0 (PFCBLK2_LOCKMASTER_SS0) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS1_OFFSET (0x04a8) /* Block 2 Lock Master Super Sector 1 (PFCBLK2_LOCKMASTER_SS1) */
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS2_OFFSET (0x04ac) /* Block 2 Lock Master Super Sector 2 (PFCBLK2_LOCKMASTER_SS2) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS0_OFFSET (0x04b4) /* Block 3 Lock Master Super Sector 0 (PFCBLK3_LOCKMASTER_SS0) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS1_OFFSET (0x04b8) /* Block 3 Lock Master Super Sector 1 (PFCBLK3_LOCKMASTER_SS1) */
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS2_OFFSET (0x04bc) /* Block 3 Lock Master Super Sector 2 (PFCBLK3_LOCKMASTER_SS2) */
/* PFLASH Register Addresses ************************************************/
#define S32K3XX_PFLASH_PFCR0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCR0_OFFSET)
#define S32K3XX_PFLASH_PFCR1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCR1_OFFSET)
#define S32K3XX_PFLASH_PFCR2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCR2_OFFSET)
#define S32K3XX_PFLASH_PFCR4 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCR4_OFFSET)
#define S32K3XX_PFLASH_PFAPR (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFAPR_OFFSET)
#define S32K3XX_PFLASH_PFCPGM_PEADR_L (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCPGM_PEADR_L_OFFSET)
#define S32K3XX_PFLASH_PFCPGM_PEADR_P (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCPGM_PEADR_P_OFFSET)
#define S32K3XX_PFLASH_PFCPGM_XPEADR_L (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCPGM_XPEADR_L_OFFSET)
#define S32K3XX_PFLASH_PFCPGM_XPEADR_P (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCPGM_XPEADR_P_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_SPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_SPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_SPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_SPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_SPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_SPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_SPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_SPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_SPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_SPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLKU_SPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLKU_SPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_SSPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_SSPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_SSPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_SSPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_SSPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_SSPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_SSPELOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_SSPELOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_SETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_SETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_SETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_SETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_SETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_SETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_SETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_SETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_SETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_SETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLKU_SETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLKU_SETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_SSETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_SSETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_SSETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_SSETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_SSETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_SSETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_SSETSLOCK (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_SSETSLOCK_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S3 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S3_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S4 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S4_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S5 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S5_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S6 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S6_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S7 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_S7_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S3 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S3_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S4 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S4_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S5 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S5_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S6 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S6_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S7 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_S7_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S3 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S3_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S4 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S4_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S5 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S5_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S6 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S6_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S7 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_S7_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S3 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S3_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S4 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S4_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S5 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S5_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S6 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S6_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S7 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_S7_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S3 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S3_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S4 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S4_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S5 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S5_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S6 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S6_OFFSET)
#define S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S7 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK4_LOCKMASTER_S7_OFFSET)
#define S32K3XX_PFLASH_PFCBLKU_LOCKMASTER_S (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLKU_LOCKMASTER_S_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK0_LOCKMASTER_SS2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK1_LOCKMASTER_SS2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK2_LOCKMASTER_SS2_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS0 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS0_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS1 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS1_OFFSET)
#define S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS2 (S32K3XX_PFLASH_BASE + S32K3XX_PFLASH_PFCBLK3_LOCKMASTER_SS2_OFFSET)
/* PFLASH Register Bitfield Definitions *************************************/
/* Platform Flash Memory Configuration Register 0 (PFCR0) */
#define PFLASH_PFCR0_P0_CBFEN (1 << 0) /* Bit 0: Port 0 PFLASH Line Read Code Buffers Enable (P0_CBFEN) */
#define PFLASH_PFCR0_P0_DBFEN (1 << 1) /* Bit 1: Port 0 PFLASH Line Read Data Buffers Enable (P0_DBFEN) */
/* Bit 2-3: Reserved */
#define PFLASH_PFCR0_P0_CPFEN (1 << 4) /* Bit 4: Port 0 Code Prefetch Enable (P0_CPFEN) */
#define PFLASH_PFCR0_P0_DPFEN (1 << 5) /* Bit 5: Port 0 Data Prefetch Enable (P0_DPFEN) */
/* Bits 6-31: Reserved */
/* Platform Flash Memory Configuration Register 1 (PFCR1) */
#define PFLASH_PFCR1_P1_CBFEN (1 << 0) /* Bit 0: Port 1 PFLASH Line Read Code Buffers Enable (P1_CBFEN) */
#define PFLASH_PFCR1_P1_DBFEN (1 << 1) /* Bit 1: Port 1 PFLASH Line Read Data Buffers Enable (P1_DBFEN) */
/* Bit 2-3: Reserved */
#define PFLASH_PFCR1_P1_CPFEN (1 << 4) /* Bit 4: Port 1 Code Prefetch Enable (P1_CPFEN) */
#define PFLASH_PFCR1_P1_DPFEN (1 << 5) /* Bit 5: Port 1 Data Prefetch Enable (P1_DPFEN) */
/* Bits 6-31: Reserved */
/* Platform Flash Memory Configuration Register 2 (PFCR2) */
#define PFLASH_PFCR2_P2_CBFEN (1 << 0) /* Bit 0: Port 2 PFLASH Line Read Code Buffers Enable (P2_CBFEN) */
#define PFLASH_PFCR2_P2_DBFEN (1 << 1) /* Bit 1: Port 2 PFLASH Line Read Data Buffers Enable (P2_DBFEN) */
/* Bit 2-3: Reserved */
#define PFLASH_PFCR2_P2_CPFEN (1 << 4) /* Bit 4: Port 2 Code Prefetch Enable (P2_CPFEN) */
#define PFLASH_PFCR2_P2_DPFEN (1 << 5) /* Bit 5: Port 2 Data Prefetch Enable (P2_DPFEN) */
/* Bits 6-31: Reserved */
/* Platform Flash Memory Configuration Register 4 (PFCR4) */
#define PFLASH_PFCR4_DERR_SUP (1 << 0) /* Bit 0: Data Error Suppression (DERR_SUP) */
#define PFLASH_PFCR4_BLK4_PS_SHIFT (1) /* Bits 1-3: Block 4 Pipe Select (BLK4_PS) */
#define PFLASH_PFCR4_BLK4_PS_MASK (0x07 << PFLASH_PFCR4_BLK4_PS_SHIFT)
/* Bits 4-6: Reserved */
#define PFLASH_PFCR4_DMEEE (1 << 7) /* Bit 7: Disable Multi-Bit ECC Error Exception (DMEEE) */
/* Bits 8-31: Reserved */
/* Platform Flash Memory Access Protection Register (PFAPR) */
#define PFLASH_PFAPR_M15AP_SHIFT (0) /* Bits 0-1: Master 15 Access Protection (M15AP) */
#define PFLASH_PFAPR_M15AP_MASK (0x03 << PFLASH_PFAPR_M15AP_SHIFT)
#define PFLASH_PFAPR_M14AP_SHIFT (2) /* Bits 2-3: Master 14 Access Protection (M14AP) */
#define PFLASH_PFAPR_M14AP_MASK (0x03 << PFLASH_PFAPR_M14AP_SHIFT)
#define PFLASH_PFAPR_M13AP_SHIFT (4) /* Bits 4-5: Master 13 Access Protection (M13AP) */
#define PFLASH_PFAPR_M13AP_MASK (0x03 << PFLASH_PFAPR_M13AP_SHIFT)
#define PFLASH_PFAPR_M12AP_SHIFT (6) /* Bits 6-7: Master 12 Access Protection (M12AP) */
#define PFLASH_PFAPR_M12AP_MASK (0x03 << PFLASH_PFAPR_M12AP_SHIFT)
#define PFLASH_PFAPR_M11AP_SHIFT (8) /* Bits 8-9: Master 11 Access Protection (M11AP) */
#define PFLASH_PFAPR_M11AP_MASK (0x03 << PFLASH_PFAPR_M11AP_SHIFT)
#define PFLASH_PFAPR_M10AP_SHIFT (10) /* Bits 10-11: Master 10 Access Protection (M10AP) */
#define PFLASH_PFAPR_M10AP_MASK (0x03 << PFLASH_PFAPR_M10AP_SHIFT)
#define PFLASH_PFAPR_M9AP_SHIFT (12) /* Bits 12-13: Master 9 Access Protection (M9AP) */
#define PFLASH_PFAPR_M9AP_MASK (0x03 << PFLASH_PFAPR_M9AP_SHIFT)
#define PFLASH_PFAPR_M8AP_SHIFT (14) /* Bits 14-15: Master 8 Access Protection (M8AP) */
#define PFLASH_PFAPR_M8AP_MASK (0x03 << PFLASH_PFAPR_M8AP_SHIFT)
#define PFLASH_PFAPR_M7AP_SHIFT (16) /* Bits 16-17: Master 7 Access Protection (M7AP) */
#define PFLASH_PFAPR_M7AP_MASK (0x03 << PFLASH_PFAPR_M7AP_SHIFT)
#define PFLASH_PFAPR_M6AP_SHIFT (18) /* Bits 18-19: Master 6 Access Protection (M6AP) */
#define PFLASH_PFAPR_M6AP_MASK (0x03 << PFLASH_PFAPR_M6AP_SHIFT)
#define PFLASH_PFAPR_M5AP_SHIFT (20) /* Bits 20-21: Master 5 Access Protection (M5AP) */
#define PFLASH_PFAPR_M5AP_MASK (0x03 << PFLASH_PFAPR_M5AP_SHIFT)
#define PFLASH_PFAPR_M4AP_SHIFT (22) /* Bits 22-23: Master 4 Access Protection (M4AP) */
#define PFLASH_PFAPR_M4AP_MASK (0x03 << PFLASH_PFAPR_M4AP_SHIFT)
/* Bits 24-25: Reserved */
#define PFLASH_PFAPR_M2AP_SHIFT (26) /* Bits 26-27: Master 2 Access Protection (M2AP) */
#define PFLASH_PFAPR_M2AP_MASK (0x03 << PFLASH_PFAPR_M2AP_SHIFT)
#define PFLASH_PFAPR_M1AP_SHIFT (28) /* Bits 28-29: Master 1 Access Protection (M1AP) */
#define PFLASH_PFAPR_M1AP_MASK (0x03 << PFLASH_PFAPR_M1AP_SHIFT)
#define PFLASH_PFAPR_M0AP_SHIFT (30) /* Bits 30-31: Master 0 Access Protection (M0AP) */
#define PFLASH_PFAPR_M0AP_MASK (0x03 << PFLASH_PFAPR_M0AP_SHIFT)
/* Platform Flash Memory Program Erase Address Logical (PFCPGM_PEADR_L) */
#define PFLASH_PFCPGM_PEADR_L_SHIFT (0) /* Bits 0-31: Program Erase Address Logical (PEADR_L) */
#define PFLASH_PFCPGM_PEADR_L_MASK (0xffffffff << PFLASH_PFCPGM_PEADR_L_SHIFT)
/* Platform Flash Memory Program Erase Address Physical (PFCPGM_PEADR_P) */
#define PFLASH_PFCPGM_PEADR_P_SHIFT (0) /* Bits 0-31: Program Erase Address Physical (PEADR_P) */
#define PFLASH_PFCPGM_PEADR_P_MASK (0xffffffff << PFLASH_PFCPGM_PEADR_P_SHIFT)
/* Platform Flash Memory Express Program Erase Address Logica
* (PFCPGM_XPEADR_L)
*/
#define PFLASH_PFCPGM_XPEADR_L_SHIFT (0) /* Bits 0-31: Express Program Erase Address Logical (XPEADR_L) */
#define PFLASH_PFCPGM_XPEADR_L_MASK (0xffffffff << PFLASH_PFCPGM_XPEADR_L_SHIFT)
/* Platform Flash Memory Express Program Erase Address Physical
* (PFCPGM_XPEADR_P)
*/
#define PFLASH_PFCPGM_XPEADR_P_SHIFT (0) /* Bits 0-31: Express Program Erase Address Physical (XPEADR_P) */
#define PFLASH_PFCPGM_XPEADR_P_MASK (0xffffffff << PFLASH_PFCPGM_XPEADR_P_SHIFT)
/* Block n Sector Program Erase Lock (PFCBLKn_SPELOCK) */
#define PFLASH_PFCBLK_SPELOCK_SHIFT (0) /* Bits 0-31: Sector Lock (SLCK) */
#define PFLASH_PFCBLK_SPELOCK_MASK (0xffffffff << PFLASH_PFCBLK_SPELOCK_SLCK_SHIFT)
/* Block UTEST Sector Program Erase Lock (PFCBLKU_SPELOCK) */
#define PFLASH_PFCBLKU_SPELOCK_SLCK (1 << 0) /* Bit 0: Sector Lock (SLCK) */
/* Bits 1-31: Reserved */
/* Block n Super Sector Program Erase Lock (PFCBLKn_SSPELOCK) */
#define PFLASH_PFCBLK_SSPELOCK_SHIFT (0) /* Bits 0-11: Super Sector Lock (SSLCK) */
#define PFLASH_PFCBLK_SSPELOCK_MASK (0x0fff << PFLASH_PFCBLK_SSPELOCK_SSLCK_SHIFT)
/* Bits 12-31: Reserved */
/* Block n Set Sector Lock (PFCBLKn_SETSLOCK) */
#define PFLASH_PFCBLK_SETSLOCK_SHIFT (0) /* Bits 0-31: Set Sector Lock (SETSLCK) */
#define PFLASH_PFCBLK_SETSLOCK_MASK (0xffffffff << PFLASH_PFCBLK_SETSLOCK_SHIFT)
/* Block UTEST Set Sector Lock (PFCBLKU_SETSLOCK) */
#define PFLASH_PFCBLKU_SETSLOCK (1 << 0) /* Bit 0: Set Sector Lock (SETSLCK) */
/* Bits 1-31: Reserved */
/* Block n Set Super Sector Lock (PFCBLKn_SSETSLOCK) */
#define PFLASH_PFCBLK_SSETSLOCK_SHIFT (0) /* Bits 0-11: Set Super Sector Lock (SSETSLCK) */
#define PFLASH_PFCBLK_SSETSLOCK_MASK (0x0fff << PFLASH_FCBLK_SSETSLOCK_SHIFT)
/* Bits 12-31: Reserved */
/* Block n Lock Master Sector m (PFCBLKn_LOCKMASTER_Sm) */
#define PFLASH_PFCBLK_LOCKMASTER_S_SHIFT (0) /* Bits 0-31: Block n Lock Master Sector m (LOCKMASTER_S) */
#define PFLASH_PFCBLK_LOCKMASTER_S_MASK (0xffffffff << PFLASH_PFCBLK_LOCKMASTER_S_SHIFT)
/* Block UTEST Lock Master Sector (PFCBLKU_LOCKMASTER_S) */
#define PFLASH_PFCBLKU_LOCKMASTER_S_SHIFT (0) /* Bits 0-7: Block n Lock Master Sector m (LOCKMASTER_S) */
#define PFLASH_PFCBLKU_LOCKMASTER_S_MASK (0xff << PFLASH_PFCBLKU_LOCKMASTER_S_SHIFT)
/* Bits 8-31: Reserved */
/* Block n Lock Master Super Sector m (PFCBLKn_LOCKMASTER_SSm) */
#define PFLASH_PFCBLK_LOCKMASTER_SS_SHIFT (0) /* Bits 0-31: Block n Lock Master Super Sector m (LOCKMASTER_SS) */
#define PFLASH_PFCBLK_LOCKMASTER_SS_MASK (0xffffffff << PFLASH_PFCBLK_LOCKMASTER_SS_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PFLASH_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PINMUX_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PINMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around pin muxing header files for the select
* S32K3xx family.
*/
#if defined(CONFIG_ARCH_CHIP_S32K344)
# include "hardware/s32k344_pinmux.h"
#else
# error "No pin multiplexing for this S32K3xx part"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PINMUX_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_pit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PIT_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PIT Register Offsets *****************************************************/
#define S32K3XX_PIT_MCR_OFFSET (0x0000) /* PIT Module Control Register (MCR) */
#define S32K3XX_PIT_LTMR64H_OFFSET (0x00e0) /* PIT Upper Lifetime Timer Register (LTMR64H) */
#define S32K3XX_PIT_LTMR64L_OFFSET (0x00e4) /* PIT Lower Lifetime Timer Register (LTMR64L) */
#define S32K3XX_PIT_RTI_LDVAL_STAT_OFFSET (0x00ec) /* RTI Timer Load Value Sync Status Register (RTI_LDVAL_STAT) */
#define S32K3XX_PIT_RTI_LDVAL_OFFSET (0x00f0) /* Timer Load Value Register (RTI_LDVAL) */
#define S32K3XX_PIT_RTI_CVAL_OFFSET (0x00f4) /* Current Timer Value Register (RTI_CVAL) */
#define S32K3XX_PIT_RTI_TCTRL_OFFSET (0x00f8) /* Timer Control Register (RTI_TCTRL) */
#define S32K3XX_PIT_RTI_TFLG_OFFSET (0x00fc) /* Timer Flag Register (RTI_TFLG) */
#define S32K3XX_PIT_LDVAL0_OFFSET (0x0100) /* Timer Load Value Register 0 (LDVAL0) */
#define S32K3XX_PIT_CVAL0_OFFSET (0x0104) /* Current Timer Value Register 0 (CVAL0) */
#define S32K3XX_PIT_TCTRL0_OFFSET (0x0108) /* Timer Control Register 0 (TCTRL0) */
#define S32K3XX_PIT_TFLG0_OFFSET (0x010c) /* Timer Flag Register 0 (TFLG0) */
#define S32K3XX_PIT_LDVAL1_OFFSET (0x0110) /* Timer Load Value Register 1 (LDVAL1) */
#define S32K3XX_PIT_CVAL1_OFFSET (0x0114) /* Current Timer Value Register 1 (CVAL1) */
#define S32K3XX_PIT_TCTRL1_OFFSET (0x0118) /* Timer Control Register 1 (TCTRL1) */
#define S32K3XX_PIT_TFLG1_OFFSET (0x011c) /* Timer Flag Register 1 (TFLG1) */
#define S32K3XX_PIT_LDVAL2_OFFSET (0x0120) /* Timer Load Value Register 2 (LDVAL2) */
#define S32K3XX_PIT_CVAL2_OFFSET (0x0124) /* Current Timer Value Register 2 (CVAL2) */
#define S32K3XX_PIT_TCTRL2_OFFSET (0x0128) /* Timer Control Register 2 (TCTRL2) */
#define S32K3XX_PIT_TFLG2_OFFSET (0x012c) /* Timer Flag Register 2 (TFLG2) */
#define S32K3XX_PIT_LDVAL3_OFFSET (0x0130) /* Timer Load Value Register 3 (LDVAL3) */
#define S32K3XX_PIT_CVAL3_OFFSET (0x0134) /* Current Timer Value Register 3 (CVAL3) */
#define S32K3XX_PIT_TCTRL3_OFFSET (0x0138) /* Timer Control Register 3 (TCTRL3) */
#define S32K3XX_PIT_TFLG3_OFFSET (0x013c) /* Timer Flag Register 3 (TFLG3) */
/* PIT Register Addresses ***************************************************/
#define S32K3XX_PIT0_MCR (S32K3XX_PIT0_BASE + S32K3XX_PIT_MCR_OFFSET)
#define S32K3XX_PIT0_LTMR64H (S32K3XX_PIT0_BASE + S32K3XX_PIT_LTMR64H_OFFSET)
#define S32K3XX_PIT0_LTMR64L (S32K3XX_PIT0_BASE + S32K3XX_PIT_LTMR64L_OFFSET)
#define S32K3XX_PIT0_RTI_LDVAL_STAT (S32K3XX_PIT0_BASE + S32K3XX_PIT_RTI_LDVAL_STAT_OFFSET)
#define S32K3XX_PIT0_RTI_LDVAL (S32K3XX_PIT0_BASE + S32K3XX_PIT_RTI_LDVAL_OFFSET)
#define S32K3XX_PIT0_RTI_CVAL (S32K3XX_PIT0_BASE + S32K3XX_PIT_RTI_CVAL_OFFSET)
#define S32K3XX_PIT0_RTI_TCTRL (S32K3XX_PIT0_BASE + S32K3XX_PIT_RTI_TCTRL_OFFSET)
#define S32K3XX_PIT0_RTI_TFLG (S32K3XX_PIT0_BASE + S32K3XX_PIT_RTI_TFLG_OFFSET)
#define S32K3XX_PIT0_LDVAL0 (S32K3XX_PIT0_BASE + S32K3XX_PIT_LDVAL0_OFFSET)
#define S32K3XX_PIT0_CVAL0 (S32K3XX_PIT0_BASE + S32K3XX_PIT_CVAL0_OFFSET)
#define S32K3XX_PIT0_TCTRL0 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TCTRL0_OFFSET)
#define S32K3XX_PIT0_TFLG0 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TFLG0_OFFSET)
#define S32K3XX_PIT0_LDVAL1 (S32K3XX_PIT0_BASE + S32K3XX_PIT_LDVAL1_OFFSET)
#define S32K3XX_PIT0_CVAL1 (S32K3XX_PIT0_BASE + S32K3XX_PIT_CVAL1_OFFSET)
#define S32K3XX_PIT0_TCTRL1 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TCTRL1_OFFSET)
#define S32K3XX_PIT0_TFLG1 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TFLG1_OFFSET)
#define S32K3XX_PIT0_LDVAL2 (S32K3XX_PIT0_BASE + S32K3XX_PIT_LDVAL2_OFFSET)
#define S32K3XX_PIT0_CVAL2 (S32K3XX_PIT0_BASE + S32K3XX_PIT_CVAL2_OFFSET)
#define S32K3XX_PIT0_TCTRL2 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TCTRL2_OFFSET)
#define S32K3XX_PIT0_TFLG2 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TFLG2_OFFSET)
#define S32K3XX_PIT0_LDVAL3 (S32K3XX_PIT0_BASE + S32K3XX_PIT_LDVAL3_OFFSET)
#define S32K3XX_PIT0_CVAL3 (S32K3XX_PIT0_BASE + S32K3XX_PIT_CVAL3_OFFSET)
#define S32K3XX_PIT0_TCTRL3 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TCTRL3_OFFSET)
#define S32K3XX_PIT0_TFLG3 (S32K3XX_PIT0_BASE + S32K3XX_PIT_TFLG3_OFFSET)
#define S32K3XX_PIT1_MCR (S32K3XX_PIT1_BASE + S32K3XX_PIT_MCR_OFFSET)
#define S32K3XX_PIT1_LTMR64H (S32K3XX_PIT1_BASE + S32K3XX_PIT_LTMR64H_OFFSET)
#define S32K3XX_PIT1_LTMR64L (S32K3XX_PIT1_BASE + S32K3XX_PIT_LTMR64L_OFFSET)
#define S32K3XX_PIT1_RTI_LDVAL_STAT (S32K3XX_PIT1_BASE + S32K3XX_PIT_RTI_LDVAL_STAT_OFFSET)
#define S32K3XX_PIT1_RTI_LDVAL (S32K3XX_PIT1_BASE + S32K3XX_PIT_RTI_LDVAL_OFFSET)
#define S32K3XX_PIT1_RTI_CVAL (S32K3XX_PIT1_BASE + S32K3XX_PIT_RTI_CVAL_OFFSET)
#define S32K3XX_PIT1_RTI_TCTRL (S32K3XX_PIT1_BASE + S32K3XX_PIT_RTI_TCTRL_OFFSET)
#define S32K3XX_PIT1_RTI_TFLG (S32K3XX_PIT1_BASE + S32K3XX_PIT_RTI_TFLG_OFFSET)
#define S32K3XX_PIT1_LDVAL0 (S32K3XX_PIT1_BASE + S32K3XX_PIT_LDVAL0_OFFSET)
#define S32K3XX_PIT1_CVAL0 (S32K3XX_PIT1_BASE + S32K3XX_PIT_CVAL0_OFFSET)
#define S32K3XX_PIT1_TCTRL0 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TCTRL0_OFFSET)
#define S32K3XX_PIT1_TFLG0 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TFLG0_OFFSET)
#define S32K3XX_PIT1_LDVAL1 (S32K3XX_PIT1_BASE + S32K3XX_PIT_LDVAL1_OFFSET)
#define S32K3XX_PIT1_CVAL1 (S32K3XX_PIT1_BASE + S32K3XX_PIT_CVAL1_OFFSET)
#define S32K3XX_PIT1_TCTRL1 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TCTRL1_OFFSET)
#define S32K3XX_PIT1_TFLG1 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TFLG1_OFFSET)
#define S32K3XX_PIT1_LDVAL2 (S32K3XX_PIT1_BASE + S32K3XX_PIT_LDVAL2_OFFSET)
#define S32K3XX_PIT1_CVAL2 (S32K3XX_PIT1_BASE + S32K3XX_PIT_CVAL2_OFFSET)
#define S32K3XX_PIT1_TCTRL2 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TCTRL2_OFFSET)
#define S32K3XX_PIT1_TFLG2 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TFLG2_OFFSET)
#define S32K3XX_PIT1_LDVAL3 (S32K3XX_PIT1_BASE + S32K3XX_PIT_LDVAL3_OFFSET)
#define S32K3XX_PIT1_CVAL3 (S32K3XX_PIT1_BASE + S32K3XX_PIT_CVAL3_OFFSET)
#define S32K3XX_PIT1_TCTRL3 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TCTRL3_OFFSET)
#define S32K3XX_PIT1_TFLG3 (S32K3XX_PIT1_BASE + S32K3XX_PIT_TFLG3_OFFSET)
#define S32K3XX_PIT2_MCR (S32K3XX_PIT2_BASE + S32K3XX_PIT_MCR_OFFSET)
#define S32K3XX_PIT2_LTMR64H (S32K3XX_PIT2_BASE + S32K3XX_PIT_LTMR64H_OFFSET)
#define S32K3XX_PIT2_LTMR64L (S32K3XX_PIT2_BASE + S32K3XX_PIT_LTMR64L_OFFSET)
#define S32K3XX_PIT2_RTI_LDVAL_STAT (S32K3XX_PIT2_BASE + S32K3XX_PIT_RTI_LDVAL_STAT_OFFSET)
#define S32K3XX_PIT2_RTI_LDVAL (S32K3XX_PIT2_BASE + S32K3XX_PIT_RTI_LDVAL_OFFSET)
#define S32K3XX_PIT2_RTI_CVAL (S32K3XX_PIT2_BASE + S32K3XX_PIT_RTI_CVAL_OFFSET)
#define S32K3XX_PIT2_RTI_TCTRL (S32K3XX_PIT2_BASE + S32K3XX_PIT_RTI_TCTRL_OFFSET)
#define S32K3XX_PIT2_RTI_TFLG (S32K3XX_PIT2_BASE + S32K3XX_PIT_RTI_TFLG_OFFSET)
#define S32K3XX_PIT2_LDVAL0 (S32K3XX_PIT2_BASE + S32K3XX_PIT_LDVAL0_OFFSET)
#define S32K3XX_PIT2_CVAL0 (S32K3XX_PIT2_BASE + S32K3XX_PIT_CVAL0_OFFSET)
#define S32K3XX_PIT2_TCTRL0 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TCTRL0_OFFSET)
#define S32K3XX_PIT2_TFLG0 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TFLG0_OFFSET)
#define S32K3XX_PIT2_LDVAL1 (S32K3XX_PIT2_BASE + S32K3XX_PIT_LDVAL1_OFFSET)
#define S32K3XX_PIT2_CVAL1 (S32K3XX_PIT2_BASE + S32K3XX_PIT_CVAL1_OFFSET)
#define S32K3XX_PIT2_TCTRL1 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TCTRL1_OFFSET)
#define S32K3XX_PIT2_TFLG1 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TFLG1_OFFSET)
#define S32K3XX_PIT2_LDVAL2 (S32K3XX_PIT2_BASE + S32K3XX_PIT_LDVAL2_OFFSET)
#define S32K3XX_PIT2_CVAL2 (S32K3XX_PIT2_BASE + S32K3XX_PIT_CVAL2_OFFSET)
#define S32K3XX_PIT2_TCTRL2 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TCTRL2_OFFSET)
#define S32K3XX_PIT2_TFLG2 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TFLG2_OFFSET)
#define S32K3XX_PIT2_LDVAL3 (S32K3XX_PIT2_BASE + S32K3XX_PIT_LDVAL3_OFFSET)
#define S32K3XX_PIT2_CVAL3 (S32K3XX_PIT2_BASE + S32K3XX_PIT_CVAL3_OFFSET)
#define S32K3XX_PIT2_TCTRL3 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TCTRL3_OFFSET)
#define S32K3XX_PIT2_TFLG3 (S32K3XX_PIT2_BASE + S32K3XX_PIT_TFLG3_OFFSET)
/* PIT Register Bitfield Definitions ****************************************/
/* PIT Module Control Register (MCR) */
#define PIT_MCR_FRZ (1 << 0) /* Bit 0: Freeze (FRZ) */
#define PIT_MCR_MDIS (1 << 1) /* Bit 1: Module Disable for PIT (MDIS) */
#define PIT_MCR_MDIS_RTI (1 << 2) /* Bit 2: Module Disable for RTI (MDIS_RTI) */
/* Bits 3-31: Reserved */
/* PIT Upper Lifetime Timer Register (LTMR64H) */
#define PIT_LTMR64H_LTH_SHIFT (0) /* Bits 0-31: Life Timer Value (LTH) */
#define PIT_LTMR64H_LTH_MASK (0xffffffff << PIT_LTMR64H_LTH_SHIFT)
/* PIT Lower Lifetime Timer Register (LTMR64L) */
#define PIT_LTMR64L_LTL_SHIFT (0) /* Bits 0-31: Life Timer Value (LTL) */
#define PIT_LTMR64L_LTL_MASK (0xffffffff << PIT_LTMR64L_LTL_SHIFT)
/* RTI Timer Load Value Sync Status Register (RTI_LDVAL_STAT) */
#define PIT_RTI_LDVAL_STAT_RT_STAT (1 << 0) /* Bit 0: RTI Timer Load Value Sync Status (RT_STAT) */
/* Bits 1-31: Reserved */
/* Timer Load Value Register (RTI_LDVAL / LDVALn) */
#define PIT_LDVAL_TSV_SHIFT (0) /* Bits 0-31: Timer Start Value (TSV) */
#define PIT_LDVAL_TSV_MASK (0xffffffff << PIT_LDVAL_TSV_SHIFT)
/* Current Timer Value Register (RTI_CVAL / CVALn) */
#define PIT_CVAL_TVL_SHIFT (0) /* Bits 0-31: Current Timer Value (TVL) */
#define PIT_CVAL_TVL_MASK (0xffffffff << PIT_CVAL_TVL_SHIFT)
/* Timer Control Register (RTI_TCTRL / TCTRLn) */
#define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable (TEN) */
#define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable (TIE) */
#define PIT_TCTRL_CHN (1 << 2) /* Bit 2: Chain Mode (CHN) */
/* Bits 3-31: Reserved */
/* Timer Flag Register (RTI_TFLG / TFLGn) */
#define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag (TIF) */
/* Bits 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PIT_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_pll.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PLL_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PLL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PLL Register Offsets *****************************************************/
#define S32K3XX_PLL_CR_OFFSET (0x00) /* PLL Control Register (PLLCR) */
#define S32K3XX_PLL_SR_OFFSET (0x04) /* PLL Status Register (PLLSR) */
#define S32K3XX_PLL_DV_OFFSET (0x08) /* PLL Divider Register (PLLDV) */
#define S32K3XX_PLL_FM_OFFSET (0x0c) /* PLL Frequency Modulation Register (PLLFM) */
#define S32K3XX_PLL_FD_OFFSET (0x10) /* PLL Fractional Divider Register (PLLFD) */
#define S32K3XX_PLL_CAL2_OFFSET (0x18) /* PLL Calibration Register 2 (PLLCAL2) */
#define S32K3XX_PLL_ODIV0_OFFSET (0x80) /* PLL Output Divider 0 Register (PLLODIV0) */
#define S32K3XX_PLL_ODIV1_OFFSET (0x84) /* PLL Output Divider 1 Register (PLLODIV1) */
/* PLL Register Addresses ***************************************************/
#define S32K3XX_PLL_CR (S32K3XX_PLL_BASE + S32K3XX_PLL_CR_OFFSET)
#define S32K3XX_PLL_SR (S32K3XX_PLL_BASE + S32K3XX_PLL_SR_OFFSET)
#define S32K3XX_PLL_DV (S32K3XX_PLL_BASE + S32K3XX_PLL_DV_OFFSET)
#define S32K3XX_PLL_FM (S32K3XX_PLL_BASE + S32K3XX_PLL_FM_OFFSET)
#define S32K3XX_PLL_FD (S32K3XX_PLL_BASE + S32K3XX_PLL_FD_OFFSET)
#define S32K3XX_PLL_CAL2 (S32K3XX_PLL_BASE + S32K3XX_PLL_CAL2_OFFSET)
#define S32K3XX_PLL_ODIV0 (S32K3XX_PLL_BASE + S32K3XX_PLL_ODIV0_OFFSET)
#define S32K3XX_PLL_ODIV1 (S32K3XX_PLL_BASE + S32K3XX_PLL_ODIV1_OFFSET)
/* PLL Register Bitfield Definitions ****************************************/
/* PLL Control Register (PLLCR) */
/* Bits 0-30: Reserved */
#define PLL_CR_PLLPD (1 << 31) /* Bit 31: PLL Power Down (PLLPD) */
# define PLL_CR_PLLPU (0 << 31) /* PLL Power Up */
/* PLL Status Register (PLLSR) */
/* Bits 0-1: Reserved */
#define PLL_SR_LOCK (1 << 2) /* Bit 2: Lock Status (LOCK) */
#define PLL_SR_LOL (1 << 3) /* Bit 3: Loss-Of-Lock Flag (LOL) */
/* Bits 4-31: Reserved */
/* PLL Divider Register (PLLDV) */
#define PLL_DV_MFI_SHIFT (0) /* Bits 0-7: PLL feedback loop divider (MFI) */
#define PLL_DV_MFI_MASK (0xff << PLL_DV_MFI_SHIFT)
#define PLL_DV_MFI(n) (((n) << PLL_DV_MFI_SHIFT) & PLL_DV_MFI_MASK)
/* Bits 8-11: Reserved */
#define PLL_DV_RDIV_SHIFT (12) /* Bits 12-14: Input clock predivider (RDIV) */
#define PLL_DV_RDIV_MASK (0x07 << PLL_DV_RDIV_SHIFT)
# define PLL_DV_RDIV_DIV(n) ((n) << PLL_DV_RDIV_SHIFT) /* Divide by n=1..7 */
/* Bits 15-24: Reserved */
#define PLL_DV_ODIV2_SHIFT (25) /* Bits 25-30: Output frequency divider for raw PLL clock (ODIV2) */
#define PLL_DV_ODIV2_MASK (0x3f << PLL_DV_ODIV2_SHIFT)
# define PLL_DV_ODIV2_DIV(n) ((n) << PLL_DV_ODIV2_SHIFT) /* Divide by n=1..63 */
/* Bit 31: Reserved */
/* PLL Frequency Modulation Register (PLLFM) */
#define PLL_FM_STEPNO_SHIFT (0) /* Bits 0-10: Number of steps of modulation period or frequency modulation (STEPNO) */
#define PLL_FM_STEPNO_MASK (0x07ff << PLL_FM_STEPNO_SHIFT)
/* Bits 11-15: Reserved */
#define PLL_FM_STEPSIZE_SHIFT (16) /* Bits 16-25: Frequency modulation step size (STEPSIZE) */
#define PLL_FM_STEPSIZE_MASK (0x03ff << PLL_FM_STEPSIZE_SHIFT)
/* Bits 26-28: Reserved */
#define PLL_FM_SPREADCTL (1 << 29) /* Bit 29: Modulation Type Selection (SPREADCTL) */
#define PLL_FM_SSCGBYP (1 << 30) /* Bit 30: Frequency Modulation (Spread Spectrum Clock Generation) Bypass (SSCGBYP) */
/* Bit 31: Reserved */
/* PLL Fractional Divider Register (PLLFD) */
#define PLL_FD_MFN_SHIFT (0) /* Bits 0-14: Numerator of fractional loop division factor (MFN) */
#define PLL_FD_MFN_MASK (0x7fff << PLL_FD_MFN_SHIFT)
/* Bits 15-27: Reserved */
#define PLL_FD_SDM3 (1 << 28) /* Bit 28: Fractional Mode Configuration (SDM3) */
#define PLL_FD_SDM2 (1 << 29) /* Bit 29: Fractional Mode Configuration (SDM2) */
#define PLL_FD_SDMEN (1 << 30) /* Bit 30: Fractional Mode Enable (SDMEN) */
/* Bit 31: Reserved */
/* PLL Calibration Register 2 (PLLCAL2) */
/* Bits 0-6: Reserved */
#define PLL_CAL2_ULKCTL_SHIFT (7) /* Bits 7-8: Unlock Control Accuracy (ULKCTL) */
#define PLL_CAL2_ULKCTL_MASK (0x03 << PLL_CAL2_ULKCTL_SHIFT)
# define PLL_CAL2_ULKCTL_EV9 (0x00 << PLL_CAL2_ULKCTL_SHIFT) /* Expected value +- 9 */
# define PLL_CAL2_ULKCTL_EV17 (0x01 << PLL_CAL2_ULKCTL_SHIFT) /* Expected value +- 17 */
# define PLL_CAL2_ULKCTL_EV33 (0x02 << PLL_CAL2_ULKCTL_SHIFT) /* Expected value +- 33 */
# define PLL_CAL2_ULKCTL_EV5 (0x03 << PLL_CAL2_ULKCTL_SHIFT) /* Expected value +- 5 */
/* Bits 9-31: Reserved */
/* PLL Output Divider n=0..1 Register (PLLODIVn) */
/* Bits 0-15: Reserved */
#define PLL_ODIV_DIV_SHIFT (16) /* Bits 16-19: Division Value (DIV) */
#define PLL_ODIV_DIV_MASK (0x0f << PLL_ODIV_DIV_SHIFT)
#define PLL_ODIV_DIV(n) (((n-1) << PLL_ODIV_DIV_SHIFT) & PLL_ODIV_DIV_MASK)
/* DIV + 1 times the time period of the divider input clock */
/* Bits 20-30: Reserved */
#define PLL_ODIV_DE (1 << 31) /* Bit 31: Divider Enable (DE) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PLL_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_pmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PMC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PMC Register Offsets *****************************************************/
#define S32K3XX_PMC_LVSC_OFFSET (0x00) /* Low Voltage Status and Control Register (LVSC) */
#define S32K3XX_PMC_CONFIG_OFFSET (0x04) /* PMC Configuration Register (CONFIG) */
#define S32K3XX_PMC_VERID_OFFSET (0x0c) /* Version ID Register (VERID) */
/* PMC Register Addresses ***************************************************/
#define S32K3XX_PMC_LVSC (S32K3XX_PMC_BASE + S32K3XX_PMC_LVSC_OFFSET)
#define S32K3XX_PMC_CONFIG (S32K3XX_PMC_BASE + S32K3XX_PMC_CONFIG_OFFSET)
#define S32K3XX_PMC_VERID (S32K3XX_PMC_BASE + S32K3XX_PMC_VERID_OFFSET)
/* PMC Register Bitfield Definitions ****************************************/
/* Low Voltage Status and Control Register (LVSC) */
#define PMC_LVSC_HVDAF (1 << 0) /* Bit 0: HVDA flag on VDD_HV_A domain in FPM (HVDAF) */
#define PMC_LVSC_HVDBF (1 << 1) /* Bit 1: HVDB flag on VDD_HV_B domain in FPM (HVDBF) */
#define PMC_LVSC_HVD25F (1 << 2) /* Bit 2: HVD25 flag on V25 domain in FPM (HVD25F) */
#define PMC_LVSC_HVD11F (1 << 3) /* Bit 3: HVD11 flag on V11 domain in FPM (HVD11F) */
#define PMC_LVSC_LVD5AF (1 << 4) /* Bit 4: LVD5A flag on VDD_HV_A domain in FPM (LVD5AF) */
#define PMC_LVSC_LVD15F (1 << 5) /* Bit 5: LVD15 flag on V15 domain in FPM (LVD15F) */
/* Bits 6-7: Reserved */
#define PMC_LVSC_HVDAS (1 << 8) /* Bit 8: HVDA status on VDD_HV_A domain in FPM (HVDAS) */
#define PMC_LVSC_HVDBS (1 << 9) /* Bit 9: HVDB status on VDD_HV_B domain in FPM (HVDBS) */
#define PMC_LVSC_HVD25S (1 << 10) /* Bit 10: HVD25 status on V25 domain in FPM (HVD25S) */
#define PMC_LVSC_HVD11S (1 << 11) /* Bit 11: HVD11 status on V11 domain in FPM (HVD11S) */
#define PMC_LVSC_LVD5AS (1 << 12) /* Bit 12: LVD5A status on VDD_HV_A domain in FPM (LVD5AS) */
#define PMC_LVSC_LVD15S (1 << 13) /* Bit 13: LVD15 status on V15 domain in FPM (LVD15S) */
/* Bits 14-15: Reserved */
#define PMC_LVSC_LVRAF (1 << 16) /* Bit 16: LVRA flag on VDD_HV_A domain in FPM (LVRAF) */
#define PMC_LVSC_LVRALPF (1 << 17) /* Bit 17: LVRALP flag on VDD_HV_A domain (LVRALPF) */
#define PMC_LVSC_LVRBF (1 << 18) /* Bit 18: LVRB flag on VDD_HV_B domain in FPM (LVRBF) */
#define PMC_LVSC_LVRBLPF (1 << 19) /* Bit 19: LVRBLP flag on VDD_HV_B domain (LVRBLPF) */
#define PMC_LVSC_LVR25F (1 << 20) /* Bit 20: LVR25 flag on V25 domain in FPM (LVR25F) */
#define PMC_LVSC_LVR25LPF (1 << 21) /* Bit 21: LVR25LP flag on V25 domain (LVR25LPF) */
#define PMC_LVSC_LVR11F (1 << 22) /* Bit 22: LVR11 flag on V11 domain in FPM (LVR11F) */
#define PMC_LVSC_LVR11LPF (1 << 23) /* Bit 23: LVR11LP flag on V11 domain (LVR11LPF) */
#define PMC_LVSC_GNG25OSCF (1 << 24) /* Bit 24: GO/NoGo detect flag on Osc part of V25 domain (GNG25OSCF) */
#define PMC_LVSC_GNG11OSCF (1 << 25) /* Bit 25: GO/NoGo detect flag on Osc part of V11 domain (GNG11OSCF) */
/* Bits 26-30: Reserved */
#define PMC_LVSC_PORF (1 << 31) /* Bit 31: POR flag (PORF) */
/* PMC Configuration Register (CONFIG) */
#define PMC_CONFIG_LMEN (1 << 0) /* Bit 0: Last Mile regulator enable bit (LMEN) */
#define PMC_CONFIG_LMBCTLEN (1 << 1) /* Bit 1: Last Mile regulator base control enable bit (LMBCTLEN) */
#define PMC_CONFIG_FASTREC (1 << 2) /* Bit 2: Fast recovery from LPM enable bit (FASTREC) */
#define PMC_CONFIG_LPM25EN (1 << 3) /* Bit 3: V25 domain enable bit during LPM (LPM25EN) */
#define PMC_CONFIG_LVRBLPEN (1 << 4) /* Bit 4: LVRBLP enable bit during LPM (LVRBLPEN) */
/* Bits 5-7: Reserved */
#define PMC_CONFIG_HVDIE (1 << 8) /* Bit 8: High voltage detect interrupt enable (HVDIE) */
#define PMC_CONFIG_LVDIE (1 << 9) /* Bit 9: Low voltage detect interrupt enable (LVDIE) */
/* Bit 10-15: Reserved */
#define PMC_CONFIG_LMAUTOEN (1 << 16) /* Bit 16: Last Mile regulator auto turn over bit (LMAUTOEN) */
#define PMC_CONFIG_LMSTAT (1 << 17) /* Bit 17: Last Mile regulator status bit (LMSTAT) */
/* Bits 18-31: Reserved */
/* Version ID Register (VERID) */
#define PMC_VERID_LMFEAT (1 << 0) /* Bit 0: Last Mile Regulator Feature (LMFEAT) */
/* Bits 1-15: Reserved */
#define PMC_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor version number (MINOR) */
#define PMC_VERID_MINOR_MASK (0xff << PMC_VERID_MINOR_SHIFT)
#define PMC_VERID_MAJOR_SHIFT (24) /* Bits 14-31: Major version number (MAJOR) */
#define PMC_VERID_MAJOR_MASK (0xff << PMC_VERID_MAJOR_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PMC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_pramc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PRAMC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PRAMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PRAMC Register Offsets ***************************************************/
#define S32K3XX_PRAMC_PRCR1_OFFSET (0x00) /* Platform RAM Configuration Register 1 (PRCR1) */
/* PRAMC Register Addresses *************************************************/
#define S32K3XX_PRAMC0_PRCR1 (S32K3XX_PRAMC0_BASE + S32K3XX_PRAMC_PRCR1_OFFSET)
#define S32K3XX_PRAMC1_PRCR1 (S32K3XX_PRAMC1_BASE + S32K3XX_PRAMC_PRCR1_OFFSET)
/* PRAMC Register Bitfield Definitions **************************************/
/* Platform RAM Configuration Register 1 (PRCR1) */
#define PRAMC_FT_DIS (1 << 0) /* Bit 0: Flow-through disabled (FT_DIS) */
/* Bits 1-5: Reserved */
#define PRAMC_P0_BO_DIS (1 << 6) /* Bit 6: Port 0 read burst optimization disable (P0_BO_DIS) */
/* Bit 7-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_PRAMC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* QSPI Register Offsets ****************************************************/
#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
/* QSPI Register Addresses **************************************************/
#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
#define S32K3XX_QSPI_LUT_COUNT 20
/* QSPI Register Bitfield Definitions ***************************************/
/* Module Configuration Register (MCR) */
#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
/* Bits 2-9: Reserved */
#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
/* Bits 12-13: Reserved */
#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
/* Bits 15-23: Reserved */
#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
/* Bits 26-31: Reserved */
/* IP Configuration Register (IPCR) */
#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
/* Bits 16-23: Reserved */
#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
/* Bits 28-31: Reserved */
/* Flash Memory Configuration Register (FLSHCR) */
#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
/* Bits 12-31: Reserved */
/* Buffer n Configuration Register (BUFnCR) */
#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
/* Bits 4-7: Reserved */
#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
/* Bits 14-31: Reserved */
#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
/* Buffer Generic Configuration Register (BFGENCR) */
/* Bits 0-11: Reserved */
#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
/* Bits 16-31: Reserved */
/* SOC Configuration Register (SOCCR) */
#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
/* Buffer n Top Index Register (BUFnIND) */
/* Bits 0-2: Reserved */
#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
/* Bits 9-31: Reserved */
/* DLL Flash Memory A Configuration Register (DLLCRA) */
#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
/* Bits 3-7: Reserved */
#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
/* Bit 15: Reserved */
#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
/* Bits 20-29: Reserved */
#define QSPI_DLLCRA_FREQEN (1 << 30) /* Bit 30: Frequency enable (FREQEN) */
/* Bit 31: Reserved */
/* Serial Flash Memory Address Register (SFAR) */
#define QSPI_SFAR_SFADR_SHIFT (0) /* Bits 0-31: Serial flash memory address (SFADR) */
#define QSPI_SFAR_SFADR_MASK (0xffffffff << QSPI_SFAR_SFADR_SHIFT)
/* Sampling Register (SMPR) */
/* Bits 0-4: Reserved */
#define QSPI_SMPR_FSPHS (1 << 5) /* Bit 5: Full speed phase selection for SDR instructions (FSPHS) */
#define QSPI_SMPR_FSDLY (1 << 6) /* Bit 6: Full speed delay section for SDR instructions (FSDLY) */
/* Bits 7-23: Reserved */
#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
/* Bits 27-31: Reserved */
/* RX Buffer Status Register (RBSR) */
#define QSPI_RBSR_RDBFL_SHIFT (0) /* Bits 0-7: RX buffer fill level (RDBFL) */
#define QSPI_RBSR_RDBFL_MASK (0xff << QSPI_RBSR_RDBFL_SHIFT)
/* Bits 8-15: Reserved */
#define QSPI_RBSR_RDCTR_SHIFT (16) /* Bits 16-31: Read counter (RDCTR) */
#define QSPI_RBSR_RDCTR_MASK (0xffff << QSPI_RBSR_RDCTR_SHIFT)
/* RX Buffer Control Register (RBCT) */
#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
/* Bit 7: Reserved */
#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
# define QSPI_RBCT_RXBRD_IP (1 << 8) /* RX buffer content is read using the IP bus registers */
/* Bits 9-31: Reserved */
/* Data Learning Status Flash Memory A Register (DLSR_FA) */
#define QSPI_DLSR_FA_NEG_EDGE_SHIFT (0) /* Bits 0-7: DLP negative edge match signature for flash memory A (NEG_EDGE) */
#define QSPI_DLSR_FA_NEG_EDGE_MASK (0xff << QSPI_DLSR_FA_NEG_EDGE_SHIFT)
#define QSPI_DLSR_FA_POS_EDGE_SHIFT (8) /* Bits 8-15: DLP positive edge match signature for flash memory A (POS_EDGE) */
#define QSPI_DLSR_FA_POS_EDGE_MASK (0xff << QSPI_DLSR_FA_POS_EDGE_SHIFT)
/* Bits 16-30: Reserved */
#define QSPI_DLSR_FA_DLPFFA (1 << 31) /* Bit 31: Data learning pattern fail (DLPFFA) */
/* TX Buffer Status Register (TBSR) */
#define QSPI_TBSR_TRBLF_SHIFT (0) /* Bits 0-5: TX buffer fill level (TRBFL) */
#define QSPI_TBSR_TRBLF_MASK (0x3f << QSPI_TBSR_TRBLF_SHIFT)
/* Bits 6-15: Reserved */
#define QSPI_TBSR_TRCTR_SHIFT (16) /* Bits 16-31: Transmit counter (TRCTR) */
#define QSPI_TBSR_TRCTR_MASK (0xffff << QSPI_TBSR_TRCTR_SHIFT)
/* TX Buffer Data Register (TBDR) */
#define QSPI_TBDR_TXDATA_SHIFT (0) /* Bits 0-31: TX data (TXDATA) */
#define QSPI_TBDR_TXDATA_MASK (0xffffffff << QSPI_TBDR_TXDATA_SHIFT)
/* TX Buffer Control Register (TBCT) */
#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
/* Bits 5-31: Reserved */
/* Status Register (SR) */
#define QSPI_SR_BUSY (1 << 0) /* Bit 0: Module busy (BUSY) */
#define QSPI_SR_IP_ACC (1 << 1) /* Bit 1: IP access (IP_ACC) */
#define QSPI_SR_AHB_ACC (1 << 2) /* Bit 2: AHB read access (AHB_ACC) */
/* Bits 3-5: Reserved */
#define QSPI_SR_AHBTRN (1 << 6) /* Bit 6: AHB access transaction pending (AHBTRN) */
#define QSPI_SR_AHB0NE (1 << 7) /* Bit 7: AHB 0 buffer not empty (AHB0NE) */
#define QSPI_SR_AHB1NE (1 << 8) /* Bit 8: AHB 1 buffer not empty (AHB1NE) */
#define QSPI_SR_AHB2NE (1 << 9) /* Bit 9: AHB 2 buffer not empty (AHB2NE) */
#define QSPI_SR_AHB3NE (1 << 10) /* Bit 10: AHB 3 buffer not empty (AHB3NE) */
#define QSPI_SR_AHB0FUL (1 << 11) /* Bit 11: AHB 0 buffer full (AHB0FUL) */
#define QSPI_SR_AHB1FUL (1 << 12) /* Bit 12: AHB 1 buffer full (AHB1FUL) */
#define QSPI_SR_AHB2FUL (1 << 13) /* Bit 13: AHB 2 buffer full (AHB2FUL) */
#define QSPI_SR_AHB3FUL (1 << 14) /* Bit 14: AHB 3 buffer full (AHB3FUL) */
/* Bit 15: Reserved */
#define QSPI_SR_RXWE (1 << 16) /* Bit 16: RX buffer watermark exceeded (RXWE) */
/* Bits 17-18: Reserved */
#define QSPI_SR_RXFULL (1 << 19) /* Bit 19: RX buffer full (RXFULL) */
/* Bits 20-22: Reserved */
#define QSPI_SR_RXDMA (1 << 23) /* Bit 23: RX buffer DMA (RXDMA) */
#define QSPI_SR_TXNE (1 << 24) /* Bit 24: TX buffer not empty (TXNE) */
#define QSPI_SR_TXWA (1 << 25) /* Bit 25: TX buffer watermark available (TXWA) */
#define QSPI_SR_TXDMA (1 << 26) /* Bit 26: TX buffer DMA (TXDMA) */
#define QSPI_SR_TXFUL (1 << 27) /* Bit 27: TX buffer full (TXFULL) */
/* Bits 28-31: Reserved */
/* Flag Register (FR) */
#define QSPI_FR_TFF (1 << 0) /* Bit 0: IP command transaction finished flag (TFF) */
/* Bits 1-5: Reserved */
#define QSPI_FR_IPIEF (1 << 6) /* Bit 6: IP command trigger could not be executed error flag (IPIEF) */
#define QSPI_FR_IPAEF (1 << 7) /* Bit 7: IP command trigger during AHB access error flag (IPAEF) */
/* Bits 8-11: Reserved */
#define QSPI_FR_ABOF (1 << 12) /* Bit 12: AHB buffer overflow flag (ABOF) */
#define QSPI_FR_AIBSEF (1 << 13) /* Bit 13: AHB illegal burst size error flag (AIBSEF) */
#define QSPI_FR_AITEF (1 << 14) /* Bit 14: AHB illegal transaction error flag (AITEF) */
/* Bit 15: Reserved */
#define QSPI_FR_RBDF (1 << 16) /* Bit 16: RX buffer drain flag (RBDF) */
#define QSPI_FR_RBOF (1 << 17) /* Bit 17: RX buffer overflow flag (RBOF) */
/* Bits 18-22: Reserved */
#define QSPI_FR_ILLINE (1 << 23) /* Bit 23: Illegal instruction error flag (ILLINE) */
/* Bits 24-25: Reserved */
#define QSPI_FR_TBUF (1 << 26) /* Bit 26: TX buffer underrun flag (TBUF) */
#define QSPI_FR_TBFF (1 << 27) /* Bit 27: TX buffer fill flag (TBFF) */
/* Bits 28-31: Reserved */
/* Interrupt and DMA Request Select and Enable Register (RSER) */
#define QSPI_RSER_TFIE (1 << 0) /* Bit 0: Transaction finished interrupt enable flag (TFIE) */
/* Bits 1-5: Reserved */
#define QSPI_RSER_IPIEIE (1 << 6) /* Bit 6: IP command trigger during IP access error interrupt enable flag (IPIEIE) */
#define QSPI_RSER_IPAEIE (1 << 7) /* Bit 7: IP command trigger during AHB read access error interrupt enable flag (IPAEIE) */
/* Bits 8-11: Reserved */
#define QSPI_RSER_ABOIE (1 << 12) /* Bit 12: AHB buffer overflow interrupt enable flag (ABOIE) */
#define QSPI_RSER_AIBSIE (1 << 13) /* Bit 13: AHB illegal burst size interrupt enable flag (AIBSIE) */
#define QSPI_RSER_AITIE (1 << 14) /* Bit 14: AHB illegal transaction interrupt enable flag (AITIE) */
/* Bit 15: Reserved */
#define QSPI_RSER_RBDIE (1 << 16) /* Bit 16: RX buffer drain interrupt enable (RBDIE) */
#define QSPI_RSER_RBOIE (1 << 17) /* Bit 17: RX buffer overflow interrupt enable (RBOIE) */
/* Bits 18-20: Reserved */
#define QSPI_RSER_RBDDE (1 << 21) /* Bit 21: RX buffer drain DMA enable (RBDDE) */
/* Bit 22: Reserved */
#define QSPI_RSER_ILLINIE (1 << 23) /* Bit 23: Illegal instruction error interrupt enable (ILLINIE) */
/* Bit 24: Reserved */
#define QSPI_RSER_TBFDE (1 << 25) /* Bit 25: TX buffer fill DMA enable (TBFDE) */
#define QSPI_RSER_TBUIE (1 << 26) /* Bit 26: TX buffer underrun interrupt enable flag (TBUIE) */
#define QSPI_RSER_TBFIE (1 << 27) /* Bit 27: TX buffer fill interrupt enable flag (TBFIE) */
/* Bits 28-31: Reserved */
/* Sequence Pointer Clear Register (SPTRCLR) */
#define QSPI_SPTRCLR_BFPTRC (1 << 0) /* Bit 0: Buffer pointer clear (BFPTRC) */
/* Bits 1-7: Reserved */
#define QSPI_SPTRCLR_IPPTRC (1 << 8) /* Bit 8: IP pointer clear (IPPTRC) */
/* Bits 9-31: Reserved */
/* Serial Flash Memory An/Bn Top Address Register (SFAnAD/SFBnAD) */
/* Bits 0-9: Reserved */
#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
/* RX Buffer Data Register (RBDRn, n=0,...,63) */
#define QSPI_RBDR_RXDATA_SHIFT (0) /* Bits 0-31: RX data (RXDATA) */
#define QSPI_RBDR_RXDATA_MASK (0xffffffff << QSPI_RBDR_RXDATA_SHIFT)
/* LUT Key Register (LUTKEY) */
#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
/* LUT Lock Configuration Register (LKCR) */
#define QSPI_LKCR_LOCK (1 << 0) /* Bit 0: Lock LUT (LOCK) */
#define QSPI_LKCR_UNLOCK (1 << 1) /* Bit 1: Unlock LUT (UNLOCK) */
/* Bits 2-31: Reserved */
/* LUT Register (LUTn) */
#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
/* External Memory Base Address */
#define QSPI_AMBA_BASE 0x68000000
/* flash connection to the QSPI module */
typedef enum
{
QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
} s32k3xx_qspi_connectiontype;
/* flash operation type */
typedef enum
{
QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
} s32k3xx_qspi_optype;
/* Lut commands */
typedef enum
{
QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */
QSPI_LUT_INSTR_CMD = (1U << 10U), /* Command */
QSPI_LUT_INSTR_ADDR = (2U << 10U), /* Address */
QSPI_LUT_INSTR_DUMMY = (3U << 10U), /* Dummy cycles */
QSPI_LUT_INSTR_MODE = (4U << 10U), /* 8-bit mode */
QSPI_LUT_INSTR_MODE2 = (5U << 10U), /* 2-bit mode */
QSPI_LUT_INSTR_MODE4 = (6U << 10U), /* 4-bit mode */
QSPI_LUT_INSTR_READ = (7U << 10U), /* Read data */
QSPI_LUT_INSTR_WRITE = (8U << 10U), /* Write data */
QSPI_LUT_INSTR_JMP_ON_CS = (9U << 10U), /* Jump on chip select deassert and stop */
QSPI_LUT_INSTR_ADDR_DDR = (10U << 10U), /* Address - DDR mode */
QSPI_LUT_INSTR_MODE_DDR = (11U << 10U), /* 8-bit mode - DDR mode */
QSPI_LUT_INSTR_MODE2_DDR = (12U << 10U), /* 2-bit mode - DDR mode */
QSPI_LUT_INSTR_MODE4_DDR = (13U << 10U), /* 4-bit mode - DDR mode */
QSPI_LUT_INSTR_READ_DDR = (14U << 10U), /* Read data - DDR mode */
QSPI_LUT_INSTR_WRITE_DDR = (15U << 10U), /* Write data - DDR mode */
QSPI_LUT_INSTR_DATA_LEARN = (16U << 10U), /* Data learning pattern */
QSPI_LUT_INSTR_CMD_DDR = (17U << 10U), /* Command - DDR mode */
QSPI_LUT_INSTR_CADDR = (18U << 10U), /* Column address */
QSPI_LUT_INSTR_CADDR_DDR = (19U << 10U), /* Column address - DDR mode */
QSPI_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /* Jump on chip select deassert and continue */
} s32k3xx_qspi_lutcommandstype;
/* Lut pad options */
typedef enum
{
QSPI_LUT_PADS_1 = (0U << 8U), /* 1 Pad */
QSPI_LUT_PADS_2 = (1U << 8U), /* 2 Pads */
QSPI_LUT_PADS_4 = (2U << 8U), /* 4 Pads */
QSPI_LUT_PADS_8 = (3U << 8U), /* 8 Pads */
} s32k3xx_qspi_lutpadstype;
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_RTC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* RTC Register Offsets *****************************************************/
#define S32K3XX_RTC_RTCSUPV_OFFSET (0x00) /* RTC Supervisor Control Register (RTCSUPV) */
#define S32K3XX_RTC_RTCC_OFFSET (0x04) /* RTC Control Register (RTCC) */
#define S32K3XX_RTC_RTCS_OFFSET (0x08) /* RTC Status Register (RTCS) */
#define S32K3XX_RTC_RTCCNT_OFFSET (0x0c) /* RTC Counter Register (RTCCNT) */
#define S32K3XX_RTC_APIVAL_OFFSET (0x10) /* API Compare Value Register (APIVAL) */
#define S32K3XX_RTC_RTCVAL_OFFSET (0x14) /* RTC Compare Value Register (RTCVAL) */
/* RTC Register Addresses ***************************************************/
#define S32K3XX_RTC_RTCSUPV (S32K3XX_RTC_BASE + S32K3XX_RTC_RTCSUPV_OFFSET)
#define S32K3XX_RTC_RTCC (S32K3XX_RTC_BASE + S32K3XX_RTC_RTCC_OFFSET)
#define S32K3XX_RTC_RTCS (S32K3XX_RTC_BASE + S32K3XX_RTC_RTCS_OFFSET)
#define S32K3XX_RTC_RTCCNT (S32K3XX_RTC_BASE + S32K3XX_RTC_RTCCNT_OFFSET)
#define S32K3XX_RTC_APIVAL (S32K3XX_RTC_BASE + S32K3XX_RTC_APIVAL_OFFSET)
#define S32K3XX_RTC_RTCVAL (S32K3XX_RTC_BASE + S32K3XX_RTC_RTCVAL_OFFSET)
/* RTC Register Bitfield Definitions ****************************************/
/* RTC Supervisor Control Register (RTCSUPV) */
/* Bits 0-30: Reserved */
#define RTC_RTCSUPV_SUPV (1 << 31) /* Bit 31: RTC Supervisor Bit (SUPV) */
/* RTC Control Register (RTCC) */
#define RTC_RTCC_TRIG_EN (1 << 0) /* Bit 0: Trigger enable for Analog Comparator (TRIG_EN) */
/* Bit 1-9: Reserved */
#define RTC_RTCC_DIV32EN (1 << 10) /* Bit 10: Divide by 32 enable (DIV32EN) */
#define RTC_RTCC_DIV512EN (1 << 11) /* Bit 11: Divide by 512 enable (DIV512EN) */
#define RTC_RTCC_CLKSEL_SHIFT (12) /* Bits 12-13: Clock select (CLKSEL) */
#define RTC_RTCC_CLKSEL_MASK (0x03 << RTC_RTCC_CLKSEL_SHIFT)
#define RTC_RTCC_CLKSEL0 (0x00 << RTC_RTCC_CLKSEL_SHIFT) /* Clock source 0 */
#define RTC_RTCC_CLKSEL1 (0x01 << RTC_RTCC_CLKSEL_SHIFT) /* Clock source 1 */
#define RTC_RTCC_CLKSEL2 (0x02 << RTC_RTCC_CLKSEL_SHIFT) /* Clock source 2 */
#define RTC_RTCC_CLKSEL3 (0x03 << RTC_RTCC_CLKSEL_SHIFT) /* Clock source 3 */
#define RTC_RTCC_APIIE (1 << 14) /* Bit 14: API Interrupt Enable (APIIE) */
#define RTC_RTCC_APIEN (1 << 15) /* Bit 15: Autonomous Periodic Interrupt Enable (APIEN) */
/* Bits 16-27: Reserved */
#define RTC_RTCC_ROVREN (1 << 28) /* Bit 28: Counter Roll Over Wakeup/Interrupt Enable (ROVREN) */
#define RTC_RTCC_FRZEN (1 << 29) /* Bit 29: Freeze Enable Bit (FRZEN) */
#define RTC_RTCC_RTCIE (1 << 30) /* Bit 30: RTC Interrupt Enable (RTCIE) */
#define RTC_RTCC_CNTEN (1 << 31) /* Bit 31: Counter Enable (CNTEN) */
/* RTC Status Register (RTCS) */
/* Bits 0-9: Reserved */
#define RTC_RTCS_ROVRF (1 << 10) /* Bit 10: Counter Roll Over Interrupt Flag (ROVRF) */
/* Bits 11-12: Reserved */
#define RTC_RTCS_APIF (1 << 13) /* Bit 13: API Interrupt Flag (APIF) */
/* Bits 14-16: Reserved */
#define RTC_RTCS_INV_API (1 << 17) /* Bit 17: Invalid APIVAL write (INV_API) */
#define RTC_RTCS_INV_RTC (1 << 18) /* Bit 18: Invalid RTC write (INV_RTC) */
/* Bits 19-28: Reserved */
#define RTC_RTCS_RTCF (1 << 29) /* Bit 29: RTC Interrupt Flag (RTCF) */
/* Bits 30-31: Reserved */
/* RTC Counter Register (RTCCNT) */
#define RTC_RTCCNT_SHIFT (0) /* Bits 0-31: RTC Counter Value (RTCCNT) */
#define RTC_RTCCNT_MASK (0xffffffff << RTC_RTCCNT_SHIFT)
/* API Compare Value Register (APIVAL) */
#define RTC_APIVAL_SHIFT (0) /* Bits 0-31: API Compare Value (APIVAL) */
#define RTC_APIVAL_MASK (0xffffffff << RTC_APIVAL_SHIFT)
/* RTC Compare Value Register (RTCVAL) */
#define RTC_RTCVAL_SHIFT (0) /* Bits 0-31: RTC Compare Value (RTCVAL) */
#define RTC_RTCVAL_MASK (0xffffffff << RTC_RTCVAL_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_RTC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_sema42.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SEMA42_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SEMA42_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SEMA42 Register Offsets **************************************************/
#define S32K3XX_SEMA42_GATE3_OFFSET (0x00) /* Gate Register 3 (GATE3) */
#define S32K3XX_SEMA42_GATE2_OFFSET (0x01) /* Gate Register 2 (GATE2) */
#define S32K3XX_SEMA42_GATE1_OFFSET (0x02) /* Gate Register 1 (GATE1) */
#define S32K3XX_SEMA42_GATE0_OFFSET (0x03) /* Gate Register 0 (GATE0) */
#define S32K3XX_SEMA42_GATE7_OFFSET (0x04) /* Gate Register 7 (GATE7) */
#define S32K3XX_SEMA42_GATE6_OFFSET (0x05) /* Gate Register 6 (GATE6) */
#define S32K3XX_SEMA42_GATE5_OFFSET (0x06) /* Gate Register 5 (GATE5) */
#define S32K3XX_SEMA42_GATE4_OFFSET (0x07) /* Gate Register 4 (GATE4) */
#define S32K3XX_SEMA42_GATE11_OFFSET (0x08) /* Gate Register 11 (GATE11) */
#define S32K3XX_SEMA42_GATE10_OFFSET (0x09) /* Gate Register 10 (GATE19) */
#define S32K3XX_SEMA42_GATE9_OFFSET (0x0a) /* Gate Register 9 (GATE9) */
#define S32K3XX_SEMA42_GATE8_OFFSET (0x0b) /* Gate Register 8 (GATE8) */
#define S32K3XX_SEMA42_GATE15_OFFSET (0x0c) /* Gate Register 15 (GATE15) */
#define S32K3XX_SEMA42_GATE14_OFFSET (0x0d) /* Gate Register 14 (GATE14) */
#define S32K3XX_SEMA42_GATE13_OFFSET (0x0e) /* Gate Register 13 (GATE13) */
#define S32K3XX_SEMA42_GATE12_OFFSET (0x0f) /* Gate Register 12 (GATE12) */
#define S32K3XX_SEMA42_RSTGT_OFFSET (0x42) /* Reset Gate Register (RSTGT) */
/* SEMA42 Register Addresses ************************************************/
#define S32K3XX_SEMA42_GATE3 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE3)
#define S32K3XX_SEMA42_GATE2 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE2)
#define S32K3XX_SEMA42_GATE1 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE1)
#define S32K3XX_SEMA42_GATE0 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE0)
#define S32K3XX_SEMA42_GATE7 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE7)
#define S32K3XX_SEMA42_GATE6 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE6)
#define S32K3XX_SEMA42_GATE5 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE5)
#define S32K3XX_SEMA42_GATE4 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE4)
#define S32K3XX_SEMA42_GATE11 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE11)
#define S32K3XX_SEMA42_GATE10 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE10)
#define S32K3XX_SEMA42_GATE9 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE9)
#define S32K3XX_SEMA42_GATE8 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE8)
#define S32K3XX_SEMA42_GATE15 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE15)
#define S32K3XX_SEMA42_GATE14 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE14)
#define S32K3XX_SEMA42_GATE13 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE13)
#define S32K3XX_SEMA42_GATE12 (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_GATE12)
#define S32K3XX_SEMA42_RSTGT (S32K3XX_SEMA42_BASE + S32K3XX_SEMA42_RSTGT)
/* SEMA42 Register Bitfield Definitions *************************************/
/* Gate Register n (GATEn) */
#define SEMA42_GATE_GTFSM_SHIFT (0) /* Bits 0-3: Gate finite state machine (GTFSM) */
#define SEMA42_GATE_GTFSM_MASK (0x0f << SEMA42_GATE_GTFSM_SHIFT)
#define SEMA42_GATE_GTFSM_FREE (0x00 << SEMA42_GATE_GTFSM_SHIFT) /* Gate is unlocked (free) */
#define SEMA42_GATE_GTFSM_DOM0 (0x01 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 0 locked the gate */
#define SEMA42_GATE_GTFSM_DOM1 (0x02 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 1 locked the gate */
#define SEMA42_GATE_GTFSM_DOM2 (0x03 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 2 locked the gate */
#define SEMA42_GATE_GTFSM_DOM3 (0x04 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 3 locked the gate */
#define SEMA42_GATE_GTFSM_DOM4 (0x05 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 4 locked the gate */
#define SEMA42_GATE_GTFSM_DOM5 (0x06 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 5 locked the gate */
#define SEMA42_GATE_GTFSM_DOM6 (0x07 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 6 locked the gate */
#define SEMA42_GATE_GTFSM_DOM7 (0x08 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 7 locked the gate */
#define SEMA42_GATE_GTFSM_DOM8 (0x09 << SEMA42_GATE_GTFSM_SHIFT) /* Domain 8 locked the gate */
#define SEMA42_GATE_GTFSM_DOM9 (0x0a << SEMA42_GATE_GTFSM_SHIFT) /* Domain 9 locked the gate */
#define SEMA42_GATE_GTFSM_DOM10 (0x0b << SEMA42_GATE_GTFSM_SHIFT) /* Domain 10 locked the gate */
#define SEMA42_GATE_GTFSM_DOM11 (0x0c << SEMA42_GATE_GTFSM_SHIFT) /* Domain 11 locked the gate */
#define SEMA42_GATE_GTFSM_DOM12 (0x0d << SEMA42_GATE_GTFSM_SHIFT) /* Domain 12 locked the gate */
#define SEMA42_GATE_GTFSM_DOM13 (0x0e << SEMA42_GATE_GTFSM_SHIFT) /* Domain 13 locked the gate */
#define SEMA42_GATE_GTFSM_DOM14 (0x0f << SEMA42_GATE_GTFSM_SHIFT) /* Domain 14 locked the gate */
/* Bits 4-7: Reserved */
/* Reset Gate Register (RSTGT) */
#define SEMA42_RSTGT_RSTGTN_SHIFT (0) /* Bits 0-7: Reset Gate Number (RSTGTN) */
#define SEMA42_RSTGT_RSTGTN_MASK (0xff << SEMA42_RSTGT_RSTGTN_SHIFT)
#define SEMA42_RSTGT_RSTGDP_SHIFT (8) /* Bits 8-15: Reset Gate Data Pattern (RSTGDP) */
#define SEMA42_RSTGT_RSTGDP_MASK (0xff << SEMA42_RSTGT_RSTGDP_SHIFT)
#define SEMA42_RSTGT_RSTGMS_SHIFT (8) /* Bits 8-11: Reset Gate Domain (RSTGMS) */
#define SEMA42_RSTGT_RSTGMS_MASK (0x0f << SEMA42_RSTGT_RSTGMS_SHIFT)
#define SEMA42_RSTGT_RSTGSM_SHIFT (12) /* Bits 12-13: Reset Gate Finite State Machine (RSTGSM) */
#define SEMA42_RSTGT_RSTGSM_MASK (0x03 << SEMA42_RSTGT_RSTGSM_SHIFT)
#define SEMA42_RSTGT_RSTGSM_FIRST (0x03 << SEMA42_RSTGT_RSTGSM_SHIFT) /* Idle, waiting for the first data pattern write */
#define SEMA42_RSTGT_RSTGSM_SECOND (0x03 << SEMA42_RSTGT_RSTGSM_SHIFT) /* Waiting for the second data pattern write */
#define SEMA42_RSTGT_RSTGSM_COMPLETE (0x03 << SEMA42_RSTGT_RSTGSM_SHIFT) /* The 2-write sequence has completed */
#define SEMA42_RSTGT_ROZ_SHIFT (14) /* Bits 14-15: ROZ */
#define SEMA42_RSTGT_ROZ_MASK (0x03 << SEMA42_RSTGT_ROZ_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SEMA42_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_sirc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SIRC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SIRC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SIRC Register Offsets ****************************************************/
#define S32K3XX_SIRC_SR_OFFSET (0x04) /* Status Register (SR) */
#define S32K3XX_SIRC_MISCELLANEOUS_IN_OFFSET (0x0c) /* Miscellaneous Input Register (MISCELLANEOUS_IN) */
/* SIRC Register Addresses **************************************************/
#define S32K3XX_SIRC_SR (S32K3XX_SIRC_BASE + S32K3XX_SIRC_SR_OFFSET)
#define S32K3XX_SIRC_MISCELLANEOUS_IN (S32K3XX_SIRC_BASE + S32K3XX_SIRC_MISCELLANEOUS_IN_OFFSET)
/* SIRC Register Bitfield Definitions ***************************************/
/* Status Register (SR) */
#define SIRC_SR_STATUS (1 << 0) /* Bit 0: Status bit for SIRC (STATUS) */
# define SIRC_SR_STATUS_OFF (0 << 0) /* SIRC is off or unstable */
# define SIRC_SR_STATUS_ON (1 << 0) /* SIRC is on and stable */
/* Bits 1-31: Reserved */
/* Miscellaneous Input Register (MISCELLANEOUS_IN) */
/* Bits 0-7: Reserved */
#define SIRC_MISCELLANEOUS_IN_STANDBY_ENABLE (1 << 8) /* Bit 8: SIRC enabled in standby mode (STANDBY_ENABLE) */
# define SIRC_MISCELLANEOUS_IN_STANDBY_DISABLE (0 << 8) /* SIRC disabled in standby mode */
/* Bit 9-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SIRC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_siul2.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SIUL2_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SIUL2_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define S32K3XX_PORTA (0)
#define S32K3XX_PORTB (1)
#define S32K3XX_PORTC (2)
#define S32K3XX_PORTD (3)
#define S32K3XX_PORTE (4)
#define S32K3XX_PORTF (5)
#define S32K3XX_PORTG (6)
#define S32K3XX_NPORTS (7) /* Number of available ports */
#define S32K3XX_NPINS (32) /* Maximum amount of pins per port */
/* SIUL2 Register Offsets ***************************************************/
#define S32K3XX_SIUL2_MIDR1_OFFSET (0x0004) /* SIUL2 MCU ID Register #1 (MIDR1) */
#define S32K3XX_SIUL2_MIDR2_OFFSET (0x0008) /* SIUL2 MCU ID Register #2 (MIDR2) */
#define S32K3XX_SIUL2_DISR0_OFFSET (0x0010) /* SIUL2 DMA/Interrupt Status Flag Register 0 (DISR0) */
#define S32K3XX_SIUL2_DIRER0_OFFSET (0x0018) /* SIUL2 DMA/Interrupt Request Enable Register 0 (DIRER0) */
#define S32K3XX_SIUL2_DIRSR0_OFFSET (0x0020) /* SIUL2 DMA/Interrupt Request Select Register 0 (DIRSR0) */
#define S32K3XX_SIUL2_IREER0_OFFSET (0x0028) /* SIUL2 Interrupt Rising-Edge Event Enable Register 0 (IREER0) */
#define S32K3XX_SIUL2_IFEER0_OFFSET (0x0030) /* SIUL2 Interrupt Falling-Edge Event Enable Register 0 (IFEER0) */
#define S32K3XX_SIUL2_IFER0_OFFSET (0x0038) /* SIUL2 Interrupt Filter Enable Register 0 (IFER0) */
#define S32K3XX_SIUL2_IFMCR_OFFSET(n) (0x0040 + ((n) << 2)) /* SIUL2 Interrupt Filter Maximum Counter Register n=0..31 (IFMCRn) */
#define S32K3XX_SIUL2_IFCPR_OFFSET (0x00c0) /* SIUL2 Interrupt Filter Clock Prescaler Register */
#define S32K3XX_SIUL2_MIDR3_OFFSET (0x0200) /* SIUL2 MCU ID Register #3 (MIDR3) */
#define S32K3XX_SIUL2_MIDR4_OFFSET (0x0204) /* SIUL2 MCU ID Register #4 (MIDR4) */
#define S32K3XX_SIUL2_MSCR_OFFSET(n) (0x0240 + ((n) << 2)) /* SIUL2 Multiplexed Signal Configuration Register n=0..219 (MSCRn) */
#define S32K3XX_SIUL2_IMCR_OFFSET(n) (0x0a40 + ((n) << 2)) /* SIUL2 Input Multiplexed Signal Configuration Register n=0..378 (IMCRn) */
#define S32K3XX_SIUL2_GPDO_OFFSET(n) (0x1300 + ((n) + 3 - 2 * ((n) % 4))) /* SIUL2 GPIO Pad Data Output Register n=0..219 (GPDOn) */
#define S32K3XX_SIUL2_GPDI_OFFSET(n) (0x1500 + ((n) + 3 - 2 * ((n) % 4))) /* SIUL2 GPIO Pad Data Input Register n=0..219 (GPDIn) */
#define S32K3XX_SIUL2_PGPDO1_OFFSET (0x1700) /* SIUL2 Parallel GPIO Pad Data Out Register 1 (PGPDO1) */
#define S32K3XX_SIUL2_PGPDO0_OFFSET (0x1702) /* SIUL2 Parallel GPIO Pad Data Out Register 0 (PGPDO0) */
#define S32K3XX_SIUL2_PGPDO3_OFFSET (0x1704) /* SIUL2 Parallel GPIO Pad Data Out Register 3 (PGPDO3) */
#define S32K3XX_SIUL2_PGPDO2_OFFSET (0x1706) /* SIUL2 Parallel GPIO Pad Data Out Register 2 (PGPDO2) */
#define S32K3XX_SIUL2_PGPDO5_OFFSET (0x1708) /* SIUL2 Parallel GPIO Pad Data Out Register 5 (PGPDO5) */
#define S32K3XX_SIUL2_PGPDO4_OFFSET (0x170a) /* SIUL2 Parallel GPIO Pad Data Out Register 4 (PGPDO4) */
#define S32K3XX_SIUL2_PGPDO7_OFFSET (0x170c) /* SIUL2 Parallel GPIO Pad Data Out Register 7 (PGPDO7) */
#define S32K3XX_SIUL2_PGPDO6_OFFSET (0x170e) /* SIUL2 Parallel GPIO Pad Data Out Register 6 (PGPDO6) */
#define S32K3XX_SIUL2_PGPDO9_OFFSET (0x1710) /* SIUL2 Parallel GPIO Pad Data Out Register 9 (PGPDO9) */
#define S32K3XX_SIUL2_PGPDO8_OFFSET (0x1712) /* SIUL2 Parallel GPIO Pad Data Out Register 8 (PGPDO8) */
#define S32K3XX_SIUL2_PGPDO11_OFFSET (0x1714) /* SIUL2 Parallel GPIO Pad Data Out Register 11 (PGPDO11) */
#define S32K3XX_SIUL2_PGPDO10_OFFSET (0x1716) /* SIUL2 Parallel GPIO Pad Data Out Register 10 (PGPDO10) */
#define S32K3XX_SIUL2_PGPDO13_OFFSET (0x1718) /* SIUL2 Parallel GPIO Pad Data Out Register 13 (PGPDO13) */
#define S32K3XX_SIUL2_PGPDO12_OFFSET (0x171a) /* SIUL2 Parallel GPIO Pad Data Out Register 12 (PGPDO12) */
#define S32K3XX_SIUL2_PGPDI1_OFFSET (0x1740) /* SIUL2 Parallel GPIO Pad Data In Register 1 (PGPDI1) */
#define S32K3XX_SIUL2_PGPDI0_OFFSET (0x1742) /* SIUL2 Parallel GPIO Pad Data In Register 0 (PGPDI0) */
#define S32K3XX_SIUL2_PGPDI3_OFFSET (0x1744) /* SIUL2 Parallel GPIO Pad Data In Register 3 (PGPDI3) */
#define S32K3XX_SIUL2_PGPDI2_OFFSET (0x1746) /* SIUL2 Parallel GPIO Pad Data In Register 2 (PGPDI2) */
#define S32K3XX_SIUL2_PGPDI5_OFFSET (0x1748) /* SIUL2 Parallel GPIO Pad Data In Register 5 (PGPDI5) */
#define S32K3XX_SIUL2_PGPDI4_OFFSET (0x174a) /* SIUL2 Parallel GPIO Pad Data In Register 4 (PGPDI4) */
#define S32K3XX_SIUL2_PGPDI7_OFFSET (0x174c) /* SIUL2 Parallel GPIO Pad Data In Register 7 (PGPDI7) */
#define S32K3XX_SIUL2_PGPDI6_OFFSET (0x174e) /* SIUL2 Parallel GPIO Pad Data In Register 6 (PGPDI6) */
#define S32K3XX_SIUL2_PGPDI9_OFFSET (0x1750) /* SIUL2 Parallel GPIO Pad Data In Register 9 (PGPDI9) */
#define S32K3XX_SIUL2_PGPDI8_OFFSET (0x1752) /* SIUL2 Parallel GPIO Pad Data In Register 8 (PGPDI8) */
#define S32K3XX_SIUL2_PGPDI11_OFFSET (0x1754) /* SIUL2 Parallel GPIO Pad Data In Register 11 (PGPDI11) */
#define S32K3XX_SIUL2_PGPDI10_OFFSET (0x1756) /* SIUL2 Parallel GPIO Pad Data In Register 10 (PGPDI10) */
#define S32K3XX_SIUL2_PGPDI13_OFFSET (0x1758) /* SIUL2 Parallel GPIO Pad Data In Register 13 (PGPDI13) */
#define S32K3XX_SIUL2_PGPDI12_OFFSET (0x175a) /* SIUL2 Parallel GPIO Pad Data In Register 12 (PGPDI12) */
#define S32K3XX_SIUL2_MPGPDO_OFFSET(n) (0x1780 + ((n) << 2)) /* SIUL2 Masked Parallel GPIO Pad Data Out Register n=0..13 (MPGPDOn) */
/* SIUL2 Register Addresses *************************************************/
#define S32K3XX_SIUL2_MIDR1 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_MIDR1_OFFSET)
#define S32K3XX_SIUL2_MIDR2 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_MIDR2_OFFSET)
#define S32K3XX_SIUL2_DISR0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DISR0_OFFSET)
# define S32K3XX_SIUL2_DISR0_IRQ0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DISR0_OFFSET + 0x00)
# define S32K3XX_SIUL2_DISR0_IRQ1 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DISR0_OFFSET + 0x01)
# define S32K3XX_SIUL2_DISR0_IRQ2 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DISR0_OFFSET + 0x02)
# define S32K3XX_SIUL2_DISR0_IRQ3 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DISR0_OFFSET + 0x03)
#define S32K3XX_SIUL2_DIRER0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DIRER0_OFFSET)
#define S32K3XX_SIUL2_DIRSR0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_DIRSR0_OFFSET)
#define S32K3XX_SIUL2_IREER0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_IREER0_OFFSET)
#define S32K3XX_SIUL2_IFEER0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_IFEER0_OFFSET)
#define S32K3XX_SIUL2_IFER0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_IFER0_OFFSET)
#define S32K3XX_SIUL2_IFMCR(n) (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_IFMCR_OFFSET(n))
#define S32K3XX_SIUL2_IFCPR (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_IFCPR_OFFSET)
#define S32K3XX_SIUL2_MIDR3 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_MIDR3_OFFSET)
#define S32K3XX_SIUL2_MIDR4 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_MIDR4_OFFSET)
#define S32K3XX_SIUL2_MSCR(n) (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_MSCR_OFFSET(n))
#define S32K3XX_SIUL2_IMCR(n) (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_IMCR_OFFSET(n))
#define S32K3XX_SIUL2_GPDO(n) (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_GPDO_OFFSET(n))
#define S32K3XX_SIUL2_GPDI(n) (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_GPDI_OFFSET(n))
#define S32K3XX_SIUL2_PGPDO1 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO1_OFFSET)
#define S32K3XX_SIUL2_PGPDO0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO0_OFFSET)
#define S32K3XX_SIUL2_PGPDO3 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO3_OFFSET)
#define S32K3XX_SIUL2_PGPDO2 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO2_OFFSET)
#define S32K3XX_SIUL2_PGPDO5 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO5_OFFSET)
#define S32K3XX_SIUL2_PGPDO4 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO4_OFFSET)
#define S32K3XX_SIUL2_PGPDO7 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO7_OFFSET)
#define S32K3XX_SIUL2_PGPDO6 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO6_OFFSET)
#define S32K3XX_SIUL2_PGPDO9 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO9_OFFSET)
#define S32K3XX_SIUL2_PGPDO8 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO8_OFFSET)
#define S32K3XX_SIUL2_PGPDO11 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO11_OFFSET)
#define S32K3XX_SIUL2_PGPDO10 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO10_OFFSET)
#define S32K3XX_SIUL2_PGPDO13 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO13_OFFSET)
#define S32K3XX_SIUL2_PGPDO12 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDO12_OFFSET)
#define S32K3XX_SIUL2_PGPDI1 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI1_OFFSET)
#define S32K3XX_SIUL2_PGPDI0 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI0_OFFSET)
#define S32K3XX_SIUL2_PGPDI3 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI3_OFFSET)
#define S32K3XX_SIUL2_PGPDI2 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI2_OFFSET)
#define S32K3XX_SIUL2_PGPDI5 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI5_OFFSET)
#define S32K3XX_SIUL2_PGPDI4 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI4_OFFSET)
#define S32K3XX_SIUL2_PGPDI7 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI7_OFFSET)
#define S32K3XX_SIUL2_PGPDI6 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI6_OFFSET)
#define S32K3XX_SIUL2_PGPDI9 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI9_OFFSET)
#define S32K3XX_SIUL2_PGPDI8 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI8_OFFSET)
#define S32K3XX_SIUL2_PGPDI11 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI11_OFFSET)
#define S32K3XX_SIUL2_PGPDI10 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI10_OFFSET)
#define S32K3XX_SIUL2_PGPDI13 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI13_OFFSET)
#define S32K3XX_SIUL2_PGPDI12 (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_PGPDI12_OFFSET)
#define S32K3XX_SIUL2_MPGPDO(n) (S32K3XX_SIUL2_BASE + S32K3XX_SIUL2_MPGPDO_OFFSET(n))
/* SIUL2 Register Bitfield Definitions **************************************/
/* SIUL2 MCU ID Register #1 (MIDR1) */
#define SIUL2_MIDR1_MINOR_SHIFT (0) /* Bits 0-3: Minor Mask Revision (MINOR_MASK) */
#define SIUL2_MIDR1_MINOR_MASK (0x0f << SIUL2_MIDR1_MINOR_SHIFT)
#define SIUL2_MIDR1_MAJOR_SHIFT (4) /* Bits 4-7: Major Mask Revision (MAJOR_MASK) */
#define SIUL2_MIDR1_MAJOR_MASK (0x0f << SIUL2_MIDR1_MAJOR_SHIFT)
/* Bits 8-15: Reserved */
#define SIUL2_MIDR1_PART_NO_SHIFT (16) /* Bits 16-25: MCU Part Number (PART_NO) */
#define SIUL2_MIDR1_PART_NO_MASK (0x03ff << SIUL2_MIDR1_PART_NO_SHIFT)
# define SIUL2_MIDR1_PART_NO_S32K311 (0x0137 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K311 */
# define SIUL2_MIDR1_PART_NO_S32K312 (0x0138 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K312 */
# define SIUL2_MIDR1_PART_NO_S32K314 (0x013a << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K314 */
# define SIUL2_MIDR1_PART_NO_S32K322 (0x0142 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K322 */
# define SIUL2_MIDR1_PART_NO_S32K324 (0x0144 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K324 */
# define SIUL2_MIDR1_PART_NO_S32K328 (0x0148 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K328 */
# define SIUL2_MIDR1_PART_NO_S32K338 (0x0152 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K338 */
# define SIUL2_MIDR1_PART_NO_S32K342 (0x0156 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K342 */
# define SIUL2_MIDR1_PART_NO_S32K344 (0x0158 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K344 */
# define SIUL2_MIDR1_PART_NO_S32K348 (0x015c << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K348 */
# define SIUL2_MIDR1_PART_NO_S32K358 (0x0166 << SIUL2_MIDR1_PART_NO_SHIFT) /* S32K358 */
#define SIUL2_MIDR1_PRODUCT_LINE_LETTER_SHIFT (26) /* Bits 26-31: Product Line Letter (PRODUCT_LINE_LETTER) */
#define SIUL2_MIDR1_PRODUCT_LINE_LETTER_MASK (0x3f << SIUL2_MIDR1_PRODUCT_LINE_LETTER_SHIFT)
/* SIUL2 MCU ID Register #2 (MIDR2) */
#define SIUL2_MIDR2_FLASH_SIZE_CODE_SHIFT (0) /* Bits 0-7: Code Flash Size (FLASH_SIZE_CODE) */
#define SIUL2_MIDR2_FLASH_SIZE_CODE_MASK (0xff << SIUL2_MIDR2_FLASH_SIZE_CODE_SHIFT)
#define SIUL2_MIDR2_FLASH_SIZE_DATA_SHIFT (8) /* Bits 8-11: Data Flash Size (FLASH_SIZE_DATA) */
#define SIUL2_MIDR2_FLASH_SIZE_DATA_MASK (0x0f << SIUL2_MIDR2_FLASH_SIZE_DATA_SHIFT)
#define SIUL2_MIDR2_FLASH_DATA_SHIFT (12) /* Bits 12-13: Data Flash Location (FLASH_DATA) */
#define SIUL2_MIDR2_FLASH_DATA_MASK (0x03 << SIUL2_MIDR2_FLASH_DATA_SHIFT)
#define SIUL2_MIDR2_FLASH_CODE_SHIFT (14) /* Bits 14-15: Code Flash Location (FLASH_CODE) */
#define SIUL2_MIDR2_FLASH_CODE_MASK (0x03 << SIUL2_MIDR2_FLASH_CODE_SHIFT)
#define SIUL2_MIDR2_FREQUENCY_SHIFT (16) /* Bits 16-19: Maximum Core Frequency (FREQUENCY) */
#define SIUL2_MIDR2_FREQUENCY_MASK (0x0f << SIUL2_MIDR2_FREQUENCY_SHIFT)
#define SIUL2_MIDR2_PACKAGE_SHIFT (20) /* Bits 20-25: Package Type (PACKAGE) */
#define SIUL2_MIDR2_PACKAGE_MASK (0x3f << SIUL2_MIDR2_PACKAGE_SHIFT)
#define SIUL2_MIDR2_TEMPERATURE_SHIFT (26) /* Bits 26-28: Ambient Temperature Range (TEMPERATURE) */
#define SIUL2_MIDR2_TEMPERATURE_MASK (0x07 << SIUL2_MIDR2_TEMPERATURE_SHIFT)
#define SIUL2_MIDR2_TECHNOLOGY_SHIFT (29) /* Bits 29-31: Silicon Technology (TECHNOLOGY) */
#define SIUL2_MIDR2_TECHNOLOGY_MASK (0x07 << SIUL2_MIDR2_TECHNOLOGY_SHIFT)
/* SIUL2 DMA/Interrupt Status Flag Register 0 (DISR0) */
#define SIUL2_DISR0_EIF(b) (1 << (b)) /* Bits 0-31: External Interrupt Status Flag 0-31 (EIF0-EIF31) */
/* SIUL2 DMA/Interrupt Request Enable Register 0 (DIRER0) */
#define SIUL2_DIRER0_EIRE(b) (1 << (b)) /* Bits 0-31: External Interrupt Request Enable 0-31 (EIRE0-EIRE31) */
/* SIUL2 DMA/Interrupt Request Select Register 0 (DIRSR0) */
#define SIUL2_DIRSR0_DIRSR(b) (1 << (b)) /* Bits 0-31: DMA/Interrupt Request Select Register 0-31 (DIRSR0-DIRSR31) */
/* SIUL2 Interrupt Rising-Edge Event Enable Register 0 (IREER0) */
#define SIUL2_IREER0_IREE(b) (1 << (b)) /* Bits 0-31: Interrupt Rising-Edge Event Enable 0-31 (IREE0-IREE31) */
/* SIUL2 Interrupt Falling-Edge Event Enable Register 0 (IFEER0) */
#define SIUL2_IFEER0_IFEE(b) (1 << (b)) /* Bits 0-31: Interrupt Falling-Edge Event Enable 0-31 (IFEE0-IFEE31) */
/* SIUL2 Interrupt Filter Enable Register 0 (IFER0) */
#define SIUL2_IFER0_IFE(b) (1 << (b)) /* Bits 0-31: Interrupt Filter Enable 0-31 (IFE0-IFE31) */
/* SIUL2 Interrupt Filter Maximum Counter Register n=0..31 (IFMCRn) */
#define SIUL2_IFMCR_MAXCNT_SHIFT (0) /* Bits 0-3: Maximum Interrupt Filter Counter Setting (MAXCNT) */
#define SIUL2_IFMCR_MAXCNT_MASK (0x0f << SIUL2_IFMCR_MAXCNT_SHIFT)
/* Bits 4-31: Reserved */
/* SIUL2 Interrupt Filter Clock Prescaler Register */
#define SIUL2_IFCPR_IFCP_SHIFT (0) /* Bits 0-3: Interrupt Filter Clock Prescaler Setting (IFCP) */
#define SIUL2_IFCPR_IFCP_MASK (0x0f << SIUL2_IFCPR_IFCP_SHIFT)
/* Bits 4-31: Reserved */
/* SIUL2 MCU ID Register #3 (MIDR3) */
#define SIUL2_MIDR3_SYS_RAM_SIZE_SHIFT (0) /* Bits 0-5: System RAM Size (SYS_RAM_SIZE) */
#define SIUL2_MIDR3_SYS_RAM_SIZE_MASK (0x3f << SIUL2_MIDR3_SYS_RAM_SIZE_SHIFT)
/* Bits 6-9: Reserved */
#define SIUL2_MIDR3_PART_NO_SUF_SHIFT (10) /* Bits 10-15: Part Number Suffix (PART_NO_SUFFIX) */
#define SIUL2_MIDR3_PART_NO_SUF_MASK (0x3f << SIUL2_MIDR3_PART_NO_SUF_SHIFT)
#define SIUL2_MIDR3_PROD_FAM_NO_SHIFT (16) /* Bits 16-25: Product Family Number (PROD_FAM_NO) */
#define SIUL2_MIDR3_PROD_FAM_NO_MASK (0x03ff << SIUL2_MIDR3_PROD_FAM_NO_SHIFT)
#define SIUL2_MIDR3_PROD_FAM_LET_SHIFT (26) /* Bits 26-31: Product Family Letter (PROD_FAM_LET) */
#define SIUL2_MIDR3_PROD_FAM_LET_MASK (0x3f << SIUL2_MIDR3_PROD_FAM_LET_SHIFT)
/* SIUL2 MCU ID Register #4 (MIDR4) */
#define SIUL2_MIDR4_CORE_PLAT_FET_SHIFT (0) /* Bits 0-2: Core Platform Options Feature (CORE_PLAT_FET) */
#define SIUL2_MIDR4_CORE_PLAT_FET_MASK (0x07 << SIUL2_MIDR4_CORE_PLAT_FET_SHIFT)
#define SIUL2_MIDR4_EMAC_FET_SHIFT (3) /* Bits 3-4: Ethernet Feature (EMAC_FET) */
#define SIUL2_MIDR4_EMAC_FET_MASK (0x03 << SIUL2_MIDR4_EMAC_FET_SHIFT)
#define SIUL2_MIDR4_SEC_FET_SHIFT (5) /* Bits 5-6: Security Feature (SEC_FET) */
#define SIUL2_MIDR4_SEC_FET_MASK (0x03 << SIUL2_MIDR4_SEC_FET_SHIFT)
/* Bits 7-31: Reserved */
/* SIUL2 Multiplexed Signal Configuration Register n=0..219 (MSCRn) */
#define SIUL2_MSCR_SSS_SHIFT (0) /* Bit 0: Source Signal Select (SSS) */
#define SIUL2_MSCR_SSS_MASK (0x07 << SIUL2_MSCR_SSS_SHIFT)
# define SIUL2_MSCR_SSS(n) (((n) << SIUL2_MSCR_SSS_SHIFT) & SIUL2_MSCR_SSS_MASK)
/* Bits 3-4: Reserved */
#define SIUL2_MSCR_SMC (1 << 5) /* Bit 5: Safe Mode Control (SMC) */
#define SIUL2_MSCR_IFE (1 << 6) /* Bit 6: Input Filter Enable (IFE) */
/* Bit 7: Reserved */
#define SIUL2_MSCR_DSE (1 << 8) /* Bit 8: Drive Strength Enable (DSE) */
/* Bits 9-10: Reserved */
#define SIUL2_MSCR_PUS (1 << 11) /* Bit 11: Pull Select (PUS) */
/* Bit 12: Reserved */
#define SIUL2_MSCR_PUE (1 << 13) /* Bit 13: Pull Enable (PUE) */
#define SIUL2_MSCR_SRC (1 << 14) /* Bit 14: Slew Rate Control (SRC) */
/* Bit 15: Reserved */
#define SIUL2_MSCR_PKE (1 << 16) /* Bit 16: Pad Keeping Enable (PKE) */
#define SIUL2_MSCR_INV (1 << 17) /* Bit 17: Invert (INV) */
/* Bit 18: Reserved */
#define SIUL2_MSCR_IBE (1 << 19) /* Bit 19: Input Buffer Enable (IBE) */
/* Bit 20: Reserved */
#define SIUL2_MSCR_OBE (1 << 21) /* Bit 21: GPIO Output Buffer Enable (OBE) */
/* Bits 22-31: Reserved */
/* SIUL2 Input Multiplexed Signal Configuration Register n=0..378 (IMCRn) */
#define SIUL2_IMCR_SSS_SHIFT (0) /* Bits 0-3: Source Signal Select (SSS) */
#define SIUL2_IMCR_SSS_MASK (0x0f << SIUL2_IMCR_SSS_SHIFT)
# define SIUL2_IMCR_SSS(n) (((n) << SIUL2_IMCR_SSS_SHIFT) & SIUL2_IMCR_SSS_MASK)
/* Bits 4-31: Reserved */
/* SIUL2 GPIO Pad Data Output Register n=0..219 (GPDOn) */
#define SIUL2_GPDO_PDO (1 << 0) /* Bit 0: Pad Data Out (PDO) */
/* Bits 1-7: Reserved */
/* SIUL2 GPIO Pad Data Input Register n=0..219 (GPDIn) */
#define SIUL2_GPDI_PDI (1 << 0) /* Bit 0: Pad Data In (PDI) */
/* Bits 1-7: Reserved */
/* SIUL2 Parallel GPIO Pad Data Out Register n=0..13 (PGPDOn) */
#define SIUL2_PGPDO_PPDO(b) (1 << (b)) /* Bits 0-15: Parallel Pad Data Out 0-15 (PPDO0-PPDO15) */
/* SIUL2 Parallel GPIO Pad Data In Register n=0..13 (PGPDIn) */
#define SIUL2_PGPDI_PPDI(b) (1 << (b)) /* Bits 0-15: Parallel Pad Data In 0-15 (PPDI0-PPDI15) */
/* SIUL2 Masked Parallel GPIO Pad Data Out Register n=0..13 (MPGPDOn) */
#define SIUL2_MPGPDO_MPPDO(b) (1 << (b)) /* Bits 0-15: Masked Parallel Pad Data Out 0-15 (MPPDO0-MPPDO15) */
#define SIUL2_MPGPDO_MPPDO_SHIFT (0)
#define SIUL2_MPGPDO_MPPDO_MASK (0xffff << SIUL2_MPGPDO_MPPDO_SHIFT)
#define SIUL2_MPGPDO_MASK(b) (1 << (b)) /* Bits 16-31: Mask Field 0-15 (MASK0-MASK15) */
#define SIUL2_MPGPDO_MASK_SHIFT (16)
#define SIUL2_MPGPDO_MASK_MASK (0xffff << SIUL2_MPGPDO_MASK_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SIUL2_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_STM_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_STM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* STM Register Offsets *****************************************************/
#define S32K3XX_STM_CR_OFFSET (0x00) /* Control Register (CR) */
#define S32K3XX_STM_CNT_OFFSET (0x04) /* Count Register (CNT) */
#define S32K3XX_STM_CCR0_OFFSET (0x10) /* Channel Control Register 0 (CCR0) */
#define S32K3XX_STM_CIR0_OFFSET (0x14) /* Channel Interrupt Register 0 (CIR0) */
#define S32K3XX_STM_CMP0_OFFSET (0x18) /* Channel Compare Register 0 (CMP0) */
#define S32K3XX_STM_CCR1_OFFSET (0x20) /* Channel Control Register 1 (CCR1) */
#define S32K3XX_STM_CIR1_OFFSET (0x24) /* Channel Interrupt Register 1 (CIR1) */
#define S32K3XX_STM_CMP1_OFFSET (0x28) /* Channel Compare Register 1 (CMP1) */
#define S32K3XX_STM_CCR2_OFFSET (0x30) /* Channel Control Register 2 (CCR2) */
#define S32K3XX_STM_CIR2_OFFSET (0x34) /* Channel Interrupt Register 2 (CIR2) */
#define S32K3XX_STM_CMP2_OFFSET (0x38) /* Channel Compare Register 2 (CMP2) */
#define S32K3XX_STM_CCR3_OFFSET (0x40) /* Channel Control Register 3 (CCR3) */
#define S32K3XX_STM_CIR3_OFFSET (0x44) /* Channel Interrupt Register 3 (CIR3) */
#define S32K3XX_STM_CMP3_OFFSET (0x48) /* Channel Compare Register 3 (CMP3) */
/* STM Register Addresses ***************************************************/
#define S32K3XX_STM0_CR (S32K3XX_STM0_BASE + S32K3XX_STM_CR_OFFSET)
#define S32K3XX_STM0_CNT (S32K3XX_STM0_BASE + S32K3XX_STM_CNT_OFFSET)
#define S32K3XX_STM0_CCR0 (S32K3XX_STM0_BASE + S32K3XX_STM_CCR0_OFFSET)
#define S32K3XX_STM0_CIR0 (S32K3XX_STM0_BASE + S32K3XX_STM_CIR0_OFFSET)
#define S32K3XX_STM0_CMP0 (S32K3XX_STM0_BASE + S32K3XX_STM_CMP0_OFFSET)
#define S32K3XX_STM0_CCR1 (S32K3XX_STM0_BASE + S32K3XX_STM_CCR1_OFFSET)
#define S32K3XX_STM0_CIR1 (S32K3XX_STM0_BASE + S32K3XX_STM_CIR1_OFFSET)
#define S32K3XX_STM0_CMP1 (S32K3XX_STM0_BASE + S32K3XX_STM_CMP1_OFFSET)
#define S32K3XX_STM0_CCR2 (S32K3XX_STM0_BASE + S32K3XX_STM_CCR2_OFFSET)
#define S32K3XX_STM0_CIR2 (S32K3XX_STM0_BASE + S32K3XX_STM_CIR2_OFFSET)
#define S32K3XX_STM0_CMP2 (S32K3XX_STM0_BASE + S32K3XX_STM_CMP2_OFFSET)
#define S32K3XX_STM0_CCR3 (S32K3XX_STM0_BASE + S32K3XX_STM_CCR3_OFFSET)
#define S32K3XX_STM0_CIR3 (S32K3XX_STM0_BASE + S32K3XX_STM_CIR3_OFFSET)
#define S32K3XX_STM0_CMP3 (S32K3XX_STM0_BASE + S32K3XX_STM_CMP3_OFFSET)
#define S32K3XX_STM1_CR (S32K3XX_STM1_BASE + S32K3XX_STM_CR_OFFSET)
#define S32K3XX_STM1_CNT (S32K3XX_STM1_BASE + S32K3XX_STM_CNT_OFFSET)
#define S32K3XX_STM1_CCR0 (S32K3XX_STM1_BASE + S32K3XX_STM_CCR0_OFFSET)
#define S32K3XX_STM1_CIR0 (S32K3XX_STM1_BASE + S32K3XX_STM_CIR0_OFFSET)
#define S32K3XX_STM1_CMP0 (S32K3XX_STM1_BASE + S32K3XX_STM_CMP0_OFFSET)
#define S32K3XX_STM1_CCR1 (S32K3XX_STM1_BASE + S32K3XX_STM_CCR1_OFFSET)
#define S32K3XX_STM1_CIR1 (S32K3XX_STM1_BASE + S32K3XX_STM_CIR1_OFFSET)
#define S32K3XX_STM1_CMP1 (S32K3XX_STM1_BASE + S32K3XX_STM_CMP1_OFFSET)
#define S32K3XX_STM1_CCR2 (S32K3XX_STM1_BASE + S32K3XX_STM_CCR2_OFFSET)
#define S32K3XX_STM1_CIR2 (S32K3XX_STM1_BASE + S32K3XX_STM_CIR2_OFFSET)
#define S32K3XX_STM1_CMP2 (S32K3XX_STM1_BASE + S32K3XX_STM_CMP2_OFFSET)
#define S32K3XX_STM1_CCR3 (S32K3XX_STM1_BASE + S32K3XX_STM_CCR3_OFFSET)
#define S32K3XX_STM1_CIR3 (S32K3XX_STM1_BASE + S32K3XX_STM_CIR3_OFFSET)
#define S32K3XX_STM1_CMP3 (S32K3XX_STM1_BASE + S32K3XX_STM_CMP3_OFFSET)
/* STM Register Bitfield Definitions ****************************************/
/* Control Register (CR) */
#define STM_CR_TEN (1 << 0) /* Bit 0: Timer Enable (TEN) */
#define STM_CR_FRZ (1 << 1) /* Bit 1: Freeze (FRZ) */
/* Bits 2-7: Reserved */
#define STM_CR_CPS_SHIFT (8) /* Bits 8-15: Counter Prescaler (CPS) */
#define STM_CR_CPS_MASK (0xff << STM_CR_CPS_SHIFT)
#define STM_CR_CPS(n) ((n << STM_CR_CPS_SHIFT) & STM_CR_CPS_MASK)
/* Bits 16-31: Reserved */
/* Count Register (CNT) */
#define STM_CNT_SHIFT (0) /* Bits 0-31: Timer Count (CNT) */
#define STM_CNT_MASK (0xffffffff << STM_CNT_SHIFT)
/* Channel Control Register n (CCRn) */
#define STM_CCR_CEN (1 << 0) /* Bit 0: Channel Enable (CEN) */
/* Bits 1-31: Reserved */
/* Channel Interrupt Register n (CIRn) */
#define STM_CIR_CIF (1 << 0) /* Bit 0: Channel Interrupt Flag (CIF) */
/* Bits 1-31: Reserved */
/* Channel Compare Register n (CMPn) */
#define STM_CMP_SHIFT (0) /* Bits 0-31: Channel Compare (CMP) */
#define STM_CMP_MASK (0xffffffff << STM_CMP_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_STM_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_swt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SWT_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SWT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SWT Register Offsets *****************************************************/
#define S32K3XX_SWT_CR_OFFSET (0x00) /* Control Register (CR) */
#define S32K3XX_SWT_IR_OFFSET (0x04) /* Interrupt Register (IR) */
#define S32K3XX_SWT_TO_OFFSET (0x08) /* Timeout Register (TO) */
#define S32K3XX_SWT_WN_OFFSET (0x0c) /* Window Register (WN) */
#define S32K3XX_SWT_SR_OFFSET (0x10) /* Service Register (SR) */
#define S32K3XX_SWT_CO_OFFSET (0x14) /* Counter Output Register (CO) */
#define S32K3XX_SWT_SK_OFFSET (0x18) /* Service Key Register (SK) */
#define S32K3XX_SWT_RRR_OFFSET (0x1c) /* Event Request Register (RRR) */
/* SWT Register Addresses ***************************************************/
#define S32K3XX_SWT0_CR (S32K3XX_SWT0_BASE + S32K3XX_SWT_CR_OFFSET)
#define S32K3XX_SWT0_IR (S32K3XX_SWT0_BASE + S32K3XX_SWT_IR_OFFSET)
#define S32K3XX_SWT0_TO (S32K3XX_SWT0_BASE + S32K3XX_SWT_TO_OFFSET)
#define S32K3XX_SWT0_WN (S32K3XX_SWT0_BASE + S32K3XX_SWT_WN_OFFSET)
#define S32K3XX_SWT0_SR (S32K3XX_SWT0_BASE + S32K3XX_SWT_SR_OFFSET)
#define S32K3XX_SWT0_CO (S32K3XX_SWT0_BASE + S32K3XX_SWT_CO_OFFSET)
#define S32K3XX_SWT0_SK (S32K3XX_SWT0_BASE + S32K3XX_SWT_SK_OFFSET)
#define S32K3XX_SWT0_RRR (S32K3XX_SWT0_BASE + S32K3XX_SWT_RRR_OFFSET)
#define S32K3XX_SWT1_CR (S32K3XX_SWT1_BASE + S32K3XX_SWT_CR_OFFSET)
#define S32K3XX_SWT1_IR (S32K3XX_SWT1_BASE + S32K3XX_SWT_IR_OFFSET)
#define S32K3XX_SWT1_TO (S32K3XX_SWT1_BASE + S32K3XX_SWT_TO_OFFSET)
#define S32K3XX_SWT1_WN (S32K3XX_SWT1_BASE + S32K3XX_SWT_WN_OFFSET)
#define S32K3XX_SWT1_SR (S32K3XX_SWT1_BASE + S32K3XX_SWT_SR_OFFSET)
#define S32K3XX_SWT1_CO (S32K3XX_SWT1_BASE + S32K3XX_SWT_CO_OFFSET)
#define S32K3XX_SWT1_SK (S32K3XX_SWT1_BASE + S32K3XX_SWT_SK_OFFSET)
#define S32K3XX_SWT1_RRR (S32K3XX_SWT1_BASE + S32K3XX_SWT_RRR_OFFSET)
/* SWT Register Bitfield Definitions ****************************************/
/* Control Register (CR) */
#define SWT_CR_WEN (1 << 0) /* Bit 0: Watchdog Enable (WEN) */
#define SWT_CR_FRZ (1 << 1) /* Bit 1: Debug Mode Control (FRZ) */
#define SWT_CR_STP (1 << 2) /* Bit 2: Stop Mode Control (STP) */
/* Bit 3: Reserved */
#define SWT_CR_SLK (1 << 4) /* Bit 4: Soft Lock (SLK) */
#define SWT_CR_HLK (1 << 5) /* Bit 5: Hard Lock (HLK) */
#define SWT_CR_ITR (1 << 6) /* Bit 6: Interrupt Then Reset Request (ITR) */
#define SWT_CR_WND (1 << 7) /* Bit 7: Window Mode (WND) */
#define SWT_CR_RIA (1 << 8) /* Bit 8: Reset on Invalid Access (RIA) */
#define SWT_CR_SMD_SHIFT (9) /* Bits 9-10: Service Mode (SMD) */
#define SWT_CR_SMD_MASK (0x03 << SWT_CR_SMD_SHIFT)
# define SWT_CR_SMD_FIXED (0x00 << SWT_CR_SMD_SHIFT) /* Fixed Service Sequence */
# define SWT_CR_SMD_KEYED (0x01 << SWT_CR_SMD_SHIFT) /* Keyed Service Sequence */
/* Bits 11-23: Reserved */
#define SWT_CR_MAP7 (1 << 24) /* Bit 24: Master Access Protection 7 (MAP7) */
#define SWT_CR_MAP6 (1 << 25) /* Bit 25: Master Access Protection 6 (MAP6) */
#define SWT_CR_MAP5 (1 << 26) /* Bit 26: Master Access Protection 5 (MAP5) */
#define SWT_CR_MAP4 (1 << 27) /* Bit 27: Master Access Protection 4 (MAP4) */
#define SWT_CR_MAP3 (1 << 28) /* Bit 28: Master Access Protection 3 (MAP3) */
#define SWT_CR_MAP2 (1 << 29) /* Bit 29: Master Access Protection 2 (MAP2) */
#define SWT_CR_MAP1 (1 << 30) /* Bit 30: Master Access Protection 1 (MAP1) */
#define SWT_CR_MAP0 (1 << 31) /* Bit 31: Master Access Protection 0 (MAP0) */
/* Interrupt Register (IR) */
#define SWT_IR_TIF (1 << 0) /* Bit 0: Timeout Interrupt Flag (TIF) */
/* Bit 1-31: Reserved */
/* Timeout Register (TO) */
#define SWT_TO_WTO_SHIFT (0) /* Bits 0-31: Watchdog Timeout (WTO) */
#define SWT_TO_WTO_MASK (0xffffffff << SWT_TO_WTO_SHIFT)
/* Window Register (WN) */
#define SWT_WN_WST_SHIFT (0) /* Bits 0-31: Window Start Value (WSV) */
#define SWT_WN_WST_MASK (0xffffffff << SWT_WN_WST_SHIFT)
/* Service Register (SR) */
#define SWT_SR_WSC_SHIFT (0) /* Bits 0-15: Watchdog Service Code (WSC) */
#define SWT_SR_WSC_MASK (0xffff << SWT_SR_WSC_SHIFT)
/* Bits 16-31: Reserved */
/* Counter Output Register (CO) */
#define SWT_CO_CNT_SHIFT (0) /* Bits 0-31: Watchdog Count (CNT) */
#define SWT_CO_CNT_MASK (0xffffffff << SWT_CO_CNT_SHIFT)
/* Service Key Register (SK) */
#define SWT_SK_SHIFT (0) /* Bits 0-15: Service Key (SK) */
#define SWT_SK_MASK (0xffff << SWT_SK_SHIFT)
/* Bits 16-31: Reserved */
/* Event Request Register (RRR) */
#define SWT_RRR_RRF (1 << 0) /* Bit 0: Reset Request Flag (RRF) */
/* Bits 1-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SWT_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SXOSC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SXOSC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SXOSC Register Offsets ***************************************************/
#define S32K3XX_SXOSC_CTRL_OFFSET (0x00) /* Oscillator Control Register (CTRL) */
#define S32K3XX_SXOSC_STAT_OFFSET (0x04) /* Oscillator Status Register (STAT) */
/* SXOSC Register Addresses *************************************************/
#define S32K3XX_SXOSC_CTRL (S32K3XX_SXOSC_BASE + S32K3XX_SXOSC_CTRL_OFFSET)
#define S32K3XX_SXOSC_STAT (S32K3XX_SXOSC_BASE + S32K3XX_SXOSC_STAT_OFFSET)
/* SXOSC Register Bitfield Definitions **************************************/
/* SXOSC Control Register (CTRL) */
#define SXOSC_CTRL_OSCON (1 << 0) /* Bit 0: Enables SXOSC (OSCON) */
# define SXOSC_CTRL_OSCOFF (0 << 0) /* Disables SXOSC */
/* Bits 1-15: Reserved */
#define SXOSC_CTRL_EOCV_SHIFT (16) /* Bits 16-23: End of count value (EOCV) */
#define SXOSC_CTRL_EOCV_MASK (0xff << SXOSC_CTRL_EOCV_SHIFT)
/* Bits 24-31: Reserved */
/* SXOSC Status Register (STAT) */
/* Bits 0-30: Reserved */
#define SXOSC_STAT_OSC_STAT (1 << 31) /* Bit 31: Crystal oscilator status (OSC_STAT) */
# define SXOSC_STAT_OSC_STAT_UNSTABLE (0 << 31) /* Crystal oscillator is unstable */
# define SXOSC_STAT_OSC_STAT_STABLE (1 << 31) /* Crystal oscillator is stable */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_SXOSC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_tspc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_TSPC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_TSPC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TSPC Register Offsets ****************************************************/
#define S32K3XX_TSPC_GRP_EN_OFFSET (0x00) /* Group Enable Register (GRP_EN) */
#define S32K3XX_TSPC_GRP1_OBE1_OFFSET (0x50) /* Group OBE (GRP1_OBE1) */
#define S32K3XX_TSPC_GRP1_OBE2_OFFSET (0x54) /* Group OBE (GRP1_OBE2) */
#define S32K3XX_TSPC_GRP2_OBE1_OFFSET (0xa0) /* Group OBE (GRP2_OBE1) */
#define S32K3XX_TSPC_GRP2_OBE2_OFFSET (0xa4) /* Group OBE (GRP2_OBE2) */
/* TSPC Register Addresses **************************************************/
#define S32K3XX_TSPC_GRP_EN (S32K3XX_TSPC_BASE + S32K3XX_TSPC_GRP_EN_OFFSET)
#define S32K3XX_TSPC_GRP1_OBE1 (S32K3XX_TSPC_BASE + S32K3XX_TSPC_GRP1_OBE1_OFFSET)
#define S32K3XX_TSPC_GRP1_OBE2 (S32K3XX_TSPC_BASE + S32K3XX_TSPC_GRP1_OBE2_OFFSET)
#define S32K3XX_TSPC_GRP2_OBE1 (S32K3XX_TSPC_BASE + S32K3XX_TSPC_GRP2_OBE1_OFFSET)
#define S32K3XX_TSPC_GRP2_OBE2 (S32K3XX_TSPC_BASE + S32K3XX_TSPC_GRP2_OBE2_OFFSET)
/* TSPC Register Bitfield Definitions ***************************************/
/* Group Enable Register (GRP_EN) */
#define S32K3XX_TSPC_GRP_EN_GRP1_EN (1 << 0) /* Bit 0: Enable for GRP1_OBEn Register (GRP1_EN) */
#define S32K3XX_TSPC_GRP_EN_GRP2_EN (1 << 1) /* Bit 1: Enable for GRP2_OBEn Register (GRP2_EN) */
/* Bits 2-31: Reserved */
/* Group OBE (GRPn_OBE1) */
#define S32K3XX_TSPC_GRP_OBE1_OBE(b) (1 << (b)) /* Bit b: Output Buffer Enable (OBE) */
/* Group OBE (GRPn_OBE2) */
#define S32K3XX_TSPC_GRP_OBE2_OBE(b) (1 << ((b) - 32)) /* Bit (b-32): Output Buffer Enable (OBE) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_TSPC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* VIRTWRAPPER Register Offsets *********************************************/
#define S32K3XX_VIRTWRAPPER_REG_A15_0_OFFSET (0x0000) /* Parameter_n Register (REG_A15_0) */
#define S32K3XX_VIRTWRAPPER_REG_A31_16_OFFSET (0x0004) /* Parameter_n Register (REG_A31_16) */
#define S32K3XX_VIRTWRAPPER_REG_A47_32_OFFSET (0x0008) /* Parameter_n Register (REG_A47_32) */
#define S32K3XX_VIRTWRAPPER_REG_A63_48_OFFSET (0x000c) /* Parameter_n Register (REG_A63_48) */
#define S32K3XX_VIRTWRAPPER_REG_A79_64_OFFSET (0x0010) /* Parameter_n Register (REG_A79_64) */
#define S32K3XX_VIRTWRAPPER_REG_A95_80_OFFSET (0x0014) /* Parameter_n Register (REG_A95_80) */
#define S32K3XX_VIRTWRAPPER_REG_A111_96_OFFSET (0x0018) /* Parameter_n Register (REG_A111_96) */
#define S32K3XX_VIRTWRAPPER_REG_A127_112_OFFSET (0x001c) /* Parameter_n Register (REG_A127_112) */
#define S32K3XX_VIRTWRAPPER_REG_A143_128_OFFSET (0x0020) /* Parameter_n Register (REG_A143_128) */
#define S32K3XX_VIRTWRAPPER_REG_A159_144_OFFSET (0x0024) /* Parameter_n Register (REG_A159_144) */
#define S32K3XX_VIRTWRAPPER_REG_A175_160_OFFSET (0x0028) /* Parameter_n Register (REG_A175_160) */
#define S32K3XX_VIRTWRAPPER_REG_A191_176_OFFSET (0x002c) /* Parameter_n Register (REG_A191_176) */
#define S32K3XX_VIRTWRAPPER_REG_A207_192_OFFSET (0x0030) /* Parameter_n Register (REG_A207_192) */
#define S32K3XX_VIRTWRAPPER_REG_A223_208_OFFSET (0x0034) /* Parameter_n Register (REG_A223_208) */
#define S32K3XX_VIRTWRAPPER_REG_A239_224_OFFSET (0x0038) /* Parameter_n Register (REG_A239_224) */
#define S32K3XX_VIRTWRAPPER_REG_A255_240_OFFSET (0x003c) /* Parameter_n Register (REG_A255_240) */
#define S32K3XX_VIRTWRAPPER_REG_A271_256_OFFSET (0x0040) /* Parameter_n Register (REG_A271_256) */
#define S32K3XX_VIRTWRAPPER_REG_A287_272_OFFSET (0x0044) /* Parameter_n Register (REG_A287_272) */
#define S32K3XX_VIRTWRAPPER_REG_A303_288_OFFSET (0x0048) /* Parameter_n Register (REG_A303_288) */
#define S32K3XX_VIRTWRAPPER_REG_A319_304_OFFSET (0x004c) /* Parameter_n Register (REG_A319_304) */
#define S32K3XX_VIRTWRAPPER_REG_A335_320_OFFSET (0x0050) /* Parameter_n Register (REG_A335_320) */
#define S32K3XX_VIRTWRAPPER_REG_A351_336_OFFSET (0x0054) /* Parameter_n Register (REG_A351_336) */
#define S32K3XX_VIRTWRAPPER_REG_A367_352_OFFSET (0x0058) /* Parameter_n Register (REG_A367_352) */
#define S32K3XX_VIRTWRAPPER_REG_A383_368_OFFSET (0x005c) /* Parameter_n Register (REG_A383_368) */
#define S32K3XX_VIRTWRAPPER_REG_A399_384_OFFSET (0x0060) /* Parameter_n Register (REG_A399_384) */
#define S32K3XX_VIRTWRAPPER_REG_A415_400_OFFSET (0x0064) /* Parameter_n Register (REG_A415_400) */
#define S32K3XX_VIRTWRAPPER_REG_A431_416_OFFSET (0x0068) /* Parameter_n Register (REG_A431_416) */
#define S32K3XX_VIRTWRAPPER_REG_A447_432_OFFSET (0x006c) /* Parameter_n Register (REG_A447_432) */
#define S32K3XX_VIRTWRAPPER_REG_A463_448_OFFSET (0x0070) /* Parameter_n Register (REG_A463_448) */
#define S32K3XX_VIRTWRAPPER_REG_A479_464_OFFSET (0x0074) /* Parameter_n Register (REG_A479_464) */
#define S32K3XX_VIRTWRAPPER_REG_A495_480_OFFSET (0x0078) /* Parameter_n Register (REG_A495_480) */
#define S32K3XX_VIRTWRAPPER_REG_A511_496_OFFSET (0x007c) /* Parameter_n Register (REG_A511_496) */
#define S32K3XX_VIRTWRAPPER_REG_B527_512_OFFSET (0x0080) /* Parameter_n Register (REG_B527_512) */
#define S32K3XX_VIRTWRAPPER_REG_B543_528_OFFSET (0x0084) /* Parameter_n Register (REG_B543_528) */
#define S32K3XX_VIRTWRAPPER_REG_B559_544_OFFSET (0x0088) /* Parameter_n Register (REG_B559_544) */
#define S32K3XX_VIRTWRAPPER_REG_B575_560_OFFSET (0x008c) /* Parameter_n Register (REG_B575_560) */
#define S32K3XX_VIRTWRAPPER_REG_B591_576_OFFSET (0x0090) /* Parameter_n Register (REG_B591_576) */
#define S32K3XX_VIRTWRAPPER_REG_B607_592_OFFSET (0x0094) /* Parameter_n Register (REG_B607_592) */
#define S32K3XX_VIRTWRAPPER_REG_B623_608_OFFSET (0x0098) /* Parameter_n Register (REG_B623_608) */
#define S32K3XX_VIRTWRAPPER_REG_B639_624_OFFSET (0x009c) /* Parameter_n Register (REG_B639_624) */
#define S32K3XX_VIRTWRAPPER_REG_B655_640_OFFSET (0x00a0) /* Parameter_n Register (REG_B655_640) */
#define S32K3XX_VIRTWRAPPER_REG_B671_656_OFFSET (0x00a4) /* Parameter_n Register (REG_B671_656) */
#define S32K3XX_VIRTWRAPPER_REG_B687_672_OFFSET (0x00a8) /* Parameter_n Register (REG_B687_672) */
#define S32K3XX_VIRTWRAPPER_REG_B703_688_OFFSET (0x00ac) /* Parameter_n Register (REG_B703_688) */
#define S32K3XX_VIRTWRAPPER_REG_B719_704_OFFSET (0x00b0) /* Parameter_n Register (REG_B719_704) */
#define S32K3XX_VIRTWRAPPER_REG_B735_720_OFFSET (0x00b4) /* Parameter_n Register (REG_B735_720) */
#define S32K3XX_VIRTWRAPPER_REG_B751_736_OFFSET (0x00b8) /* Parameter_n Register (REG_B751_736) */
#define S32K3XX_VIRTWRAPPER_REG_B767_752_OFFSET (0x00bc) /* Parameter_n Register (REG_B767_752) */
#define S32K3XX_VIRTWRAPPER_REG_B783_768_OFFSET (0x00c0) /* Parameter_n Register (REG_B783_768) */
#define S32K3XX_VIRTWRAPPER_REG_B799_784_OFFSET (0x00c4) /* Parameter_n Register (REG_B799_784) */
#define S32K3XX_VIRTWRAPPER_REG_B815_800_OFFSET (0x00c8) /* Parameter_n Register (REG_B815_800) */
#define S32K3XX_VIRTWRAPPER_REG_B831_816_OFFSET (0x00cc) /* Parameter_n Register (REG_B831_816) */
#define S32K3XX_VIRTWRAPPER_REG_B847_832_OFFSET (0x00d0) /* Parameter_n Register (REG_B847_832) */
#define S32K3XX_VIRTWRAPPER_REG_B863_848_OFFSET (0x00d4) /* Parameter_n Register (REG_B863_848) */
#define S32K3XX_VIRTWRAPPER_REG_B879_864_OFFSET (0x00d8) /* Parameter_n Register (REG_B879_864) */
#define S32K3XX_VIRTWRAPPER_REG_B895_880_OFFSET (0x00dc) /* Parameter_n Register (REG_B895_880) */
#define S32K3XX_VIRTWRAPPER_REG_B911_896_OFFSET (0x00e0) /* Parameter_n Register (REG_B911_896) */
#define S32K3XX_VIRTWRAPPER_REG_B927_912_OFFSET (0x00e4) /* Parameter_n Register (REG_B927_912) */
#define S32K3XX_VIRTWRAPPER_REG_B943_928_OFFSET (0x00e8) /* Parameter_n Register (REG_B943_928) */
#define S32K3XX_VIRTWRAPPER_REG_B959_944_OFFSET (0x00ec) /* Parameter_n Register (REG_B959_944) */
#define S32K3XX_VIRTWRAPPER_REG_B975_960_OFFSET (0x00f0) /* Parameter_n Register (REG_B975_960) */
#define S32K3XX_VIRTWRAPPER_REG_B991_976_OFFSET (0x00f4) /* Parameter_n Register (REG_B991_976) */
#define S32K3XX_VIRTWRAPPER_REG_B1007_992_OFFSET (0x00f8) /* Parameter_n Register (REG_B1007_99) */
#define S32K3XX_VIRTWRAPPER_REG_B1023_1008_OFFSET (0x00fc) /* Parameter_n Register (REG_B1023_1008) */
#define S32K3XX_VIRTWRAPPER_REG_C1039_1024_OFFSET (0x0100) /* Parameter_n Register (REG_C1039_1024) */
#define S32K3XX_VIRTWRAPPER_REG_D1055_1040_OFFSET (0x0104) /* Parameter_n Register (REG_D1055_1040) */
/* VIRTWRAPPER Register Addresses *******************************************/
#define S32K3XX_VIRTWRAPPER_REG_A15_0 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A15_0_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A31_16 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A31_16_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A47_32 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A47_32_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A63_48 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A63_48_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A79_64 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A79_64_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A95_80 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A95_80_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A111_96 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A111_96_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A127_112 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A127_112_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A143_128 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A143_128_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A159_144 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A159_144_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A175_160 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A175_160_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A191_176 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A191_176_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A207_192 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A207_192_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A223_208 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A223_208_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A239_224 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A239_224_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A255_240 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A255_240_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A271_256 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A271_256_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A287_272 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A287_272_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A303_288 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A303_288_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A319_304 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A319_304_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A335_320 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A335_320_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A351_336 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A351_336_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A367_352 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A367_352_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A383_368 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A383_368_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A399_384 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A399_384_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A415_400 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A415_400_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A431_416 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A431_416_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A447_432 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A447_432_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A463_448 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A463_448_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A479_464 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A479_464_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A495_480 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A495_480_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A511_496 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A511_496_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B527_512 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B527_512_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B543_528 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B543_528_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B559_544 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B559_544_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B575_560 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B575_560_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B591_576 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B591_576_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B607_592 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B607_592_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B623_608 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B623_608_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B639_624 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B639_624_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B655_640 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B655_640_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B671_656 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B671_656_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B687_672 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B687_672_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B703_688 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B703_688_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B719_704 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B719_704_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B735_720 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B735_720_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_A751_736 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B751_736_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B767_752 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B767_752_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B783_768 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B783_768_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B799_784 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B799_784_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B815_800 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B815_800_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B831_816 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B831_816_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B847_832 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B847_832_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B863_848 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B863_848_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B879_864 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B879_864_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B895_880 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B895_880_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B911_896 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B911_896_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B927_912 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B927_912_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B943_928 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B943_928_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B959_944 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B959_944_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B975_960 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B975_960_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B991_976 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B991_976_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B1007_992 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B1007_992_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_B1023_1008 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B1023_1008_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_C1039_1024 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_C1039_1024_OFFSET)
#define S32K3XX_VIRTWRAPPER_REG_D1055_1040 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_D1055_1040_OFFSET)
/* VIRTWRAPPER Register Bitfield Definitions ********************************/
/* Parameter_n Register (REG_Annn_mmm) */
#define VIRTWRAPPER_REG_A_PAD_SHIFT(p) ((p) << 1) /* Bits (2*p)-(2*p+1): PAD_p, p=0..15 */
#define VIRTWRAPPER_REG_A_PAD_MASK(p) (0x03 << VIRTWRAPPER_REG_A_PAD_SHIFT(p))
# define VIRTWRAPPER_REG_A_PAD_CORE0(p) (0x00 << VIRTWRAPPER_REG_A_PAD_SHIFT(p)) /* SIUL2_VIRTWRAPPER_PDAC1 (Core 0) */
# define VIRTWRAPPER_REG_A_PAD_CORE1(p) (0x01 << VIRTWRAPPER_REG_A_PAD_SHIFT(p)) /* SIUL2_VIRTWRAPPER_PDAC2 (Core 1) */
# define VIRTWRAPPER_REG_A_PAD_SECCORE(p) (0x03 << VIRTWRAPPER_REG_A_PAD_SHIFT(p)) /* SIUL2_VIRTWRAPPER_PDAC0 (Secure Core) */
/* Parameter_n Register (REG_Bnnnn_mmmm) */
#define VIRTWRAPPER_REG_B_INMUX_SHIFT(i) ((i) << 1) /* Bits (2*i)-(2*i+1): INMUX_i, i=0..15 */
#define VIRTWRAPPER_REG_B_INMUX_MASK(i) (0x03 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i))
# define VIRTWRAPPER_REG_B_INMUX_CORE0(i) (0x00 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i)) /* SIUL2_VIRTWRAPPER_PDAC1 (Core 0) */
# define VIRTWRAPPER_REG_B_INMUX_CORE1(i) (0x01 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i)) /* SIUL2_VIRTWRAPPER_PDAC2 (Core 1) */
# define VIRTWRAPPER_REG_B_INMUX_SECCORE(i) (0x03 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i)) /* SIUL2_VIRTWRAPPER_PDAC0 (Secure Core) */
/* Parameter_n Register (REG_C1039_1024) */
#define VIRTWRAPPER_REG_C_INTC_CTRL_SHIFT (0) /* Bits 0-1: Interrupt register control (INTC_CTRL) */
#define VIRTWRAPPER_REG_C_INTC_CTRL_MASK (0x03 << VIRTWRAPPER_REG_C_INTC_CTRL_SHIFT)
/* Bits 2-31: Reserved */
/* Parameter_n Register (REG_D1055_1040) */
/* Bits 0-29: Reserved */
#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR REgister Of REG_PROT (REG_GCR) */
#define VIRTWRAPPER_REG_D_REG_GCR_MASK (0x03 << VIRTWRAPPER_REG_D_REG_GCR_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_WKPU_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_WKPU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* WKPU Register Offsets ****************************************************/
#define S32K3XX_WKPU_NSR_OFFSET (0x00) /* WKPU NMI Status Flag Register (NSR) */
#define S32K3XX_WKPU_NCR_OFFSET (0x08) /* WKPU NMI Configuration Register (NCR) */
#define S32K3XX_WKPU_WISR_OFFSET (0x14) /* WKPU Wakeup/Interrupt Status Flag Register (WISR) */
#define S32K3XX_WKPU_IRER_OFFSET (0x18) /* WKPU Interrupt Request Enable Register (IRER) */
#define S32K3XX_WKPU_WRER_OFFSET (0x1c) /* WKPU Wakeup Request Enable Register (WRER) */
#define S32K3XX_WKPU_WIREER_OFFSET (0x28) /* WKPU Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) */
#define S32K3XX_WKPU_WIFEER_OFFSET (0x2c) /* WKPU Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) */
#define S32K3XX_WKPU_WIFER_OFFSET (0x30) /* WKPU Wakeup/Interrupt Filter Enable Register (WIFER) */
#define S32K3XX_WKPU_WISR_64_OFFSET (0x54) /* WKPU Wakeup/Interrupt Status Flag Register (WISR_64) */
#define S32K3XX_WKPU_IRER_64_OFFSET (0x58) /* WKPU Interrupt Request Enable Register (IRER_64) */
#define S32K3XX_WKPU_WRER_64_OFFSET (0x5c) /* WKPU Wakeup Request Enable Register (WRER_64) */
#define S32K3XX_WKPU_WIREER_64_OFFSET (0x68) /* WKPU Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER_64) */
#define S32K3XX_WKPU_WIFEER_64_OFFSET (0x6c) /* WKPU Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER_64) */
#define S32K3XX_WKPU_WIFER_64_OFFSET (0x70) /* WKPU Wakeup/Interrupt Filter Enable Register (WIFER_64) */
/* WKPU Register Addresses **************************************************/
#define S32K3XX_WKPU_NSR (S32K3XX_WKPU_BASE + S32K3XX_WKPU_NSR_OFFSET)
#define S32K3XX_WKPU_NCR (S32K3XX_WKPU_BASE + S32K3XX_WKPU_NCR_OFFSET)
#define S32K3XX_WKPU_WISR (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WISR_OFFSET)
#define S32K3XX_WKPU_IRER (S32K3XX_WKPU_BASE + S32K3XX_WKPU_IRER_OFFSET)
#define S32K3XX_WKPU_WRER (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WRER_OFFSET)
#define S32K3XX_WKPU_WIREER (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WIREER_OFFSET)
#define S32K3XX_WKPU_WIFEER (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WIFEER_OFFSET)
#define S32K3XX_WKPU_WIFER (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WIFER_OFFSET)
#define S32K3XX_WKPU_WISR_64 (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WISR_64_OFFSET)
#define S32K3XX_WKPU_IRER_64 (S32K3XX_WKPU_BASE + S32K3XX_WKPU_IRER_64_OFFSET)
#define S32K3XX_WKPU_WRER_64 (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WRER_64_OFFSET)
#define S32K3XX_WKPU_WIREER_64 (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WIREER_64_OFFSET)
#define S32K3XX_WKPU_WIFEER_64 (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WIFEER_64_OFFSET)
#define S32K3XX_WKPU_WIFER_64 (S32K3XX_WKPU_BASE + S32K3XX_WKPU_WIFER_64_OFFSET)
/* WKPU Register Bitfield Definitions ***************************************/
/* WKPU NMI Status Flag Register (NSR) */
/* Bits 0-21: Reserved */
#define WKPU_NSR_NOVF1 (1 << 22) /* Bit 22: NMI Overrun Status Flag 1 (NOVF1) */
#define WKPU_NSR_NIF1 (1 << 23) /* Bit 23: NMI Status Flag 1 (NIF1) */
/* Bits 24-29: Reserved */
#define WKPU_NSR_NOVF0 (1 << 30) /* Bit 30: NMI Overrun Status Flag 0 (NOVF0) */
#define WKPU_NSR_NIF0 (1 << 31) /* Bit 31: NMI Status Flag 0 (NIF0) */
/* WKPU NMI Configuration Register (NCR) */
/* Bits 0-15: Reserved */
#define WKPU_NCR_NFE1 (1 << 16) /* Bit 16: NMI Filter Enable 1 (NFE1) */
#define WKPU_NCR_NFEE1 (1 << 17) /* Bit 17: NMI Falling-edge Events Enable 1 (NFEE1) */
#define WKPU_NCR_NREE1 (1 << 18) /* Bit 18: NMI Rising-Edge Events Enable 1 (NREE1) */
/* Bit 19: Reserved */
#define WKPU_NCR_NWRE1 (1 << 20) /* Bit 20: NMI Wakeup Request Enable 1 (NWRE1) */
#define WKPU_NCR_NDSS1_SHIFT (21) /* Bits 21-22: NMI Destination Source Select 1 (NDSS1) */
#define WKPU_NCR_NDSS1_MASK (0x03 << WKPU_NCR_NDSS1_SHIFT)
# define WKPU_NCR_NDSS1_NMI (0x00 << WKPU_NCR_NDSS1_SHIFT) /* Non-maskable interrupt */
#define WKPU_NCR_NLOCK1 (1 << 23) /* Bit 23: NMI Configuration Lock Register 1 (NLOCK1) */
#define WKPU_NCR_NFE0 (1 << 24) /* Bit 24: NMI Filter Enable 0 (NFE0) */
#define WKPU_NCR_NFEE0 (1 << 25) /* Bit 25: NMI Falling-edge Events Enable 0 (NFEE0) */
#define WKPU_NCR_NREE0 (1 << 26) /* Bit 26: NMI Rising-Edge Events Enable 0 (NREE0) */
/* Bit 27: Reserved */
#define WKPU_NCR_NWRE0 (1 << 28) /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */
#define WKPU_NCR_NDSS0_SHIFT (29) /* Bits 29-30: NMI Destination Source Select 0 (NDSS0) */
#define WKPU_NCR_NDSS0_MASK (0x03 << WKPU_NCR_NDSS0_SHIFT)
# define WKPU_NCR_NDSS0_NMI (0x00 << WKPU_NCR_NDSS0_SHIFT) /* Non-maskable interrupt */
#define WKPU_NCR_NLOCK0 (1 << 31) /* Bit 31: NMI Configuration Lock Register 0 (NLOCK0) */
/* WKPU Wakeup/Interrupt Status Flag Register (WISR, WISR_64) */
#define WKPU_WISR_EIF(n) (1 << (n)) /* Bit n: External Wakeup/Interrupt Status Flag n (EIFn) */
/* WKPU Interrupt Request Enable Register (IRER, IRER_64) */
#define WKPU_IRER_EIRE(n) (1 << (n)) /* Bit n: External Interrupt Request Enable n (EIREn) */
/* WKPU Wakeup Request Enable Register (WRER, WRER_64) */
#define WKPU_WRER_WRE(n) (1 << (n)) /* Bit n: External Wakeup Request Enable n (WREn) */
/* WKPU Wakeup/Interrupt Rising-Edge Event Enable Register
* (WIREER, WIREER_64)
*/
#define WKPU_WIREER_IREE(n) (1 << (n)) /* Bit n: External Interrupt Rising-edge Events Enable n (IREEn) */
/* WKPU Wakeup/Interrupt Falling-Edge Event Enable Register
* (WIFEER, WIFEER_64)
*/
#define WKPU_WIFEER_IFEE(n) (1 << (n)) /* Bit n: External Interrupt Falling-edge Events Enable n (IFEEn) */
/* WKPU Wakeup/Interrupt Filter Enable Register (WIFER, WIFER_64) */
#define WKPU_WIFER_IFE(n) (1 << (n)) /* Bit n: External Interrupt Filter Enable n (IFEn) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_WKPU_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_xbic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_XBIC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_XBIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* XBIC Register Offsets ****************************************************/
#define S32K3XX_XBIC_MCR_OFFSET (0x00) /* XBIC Module Control Register (MCR) */
#define S32K3XX_XBIC_EIR_OFFSET (0x04) /* XBIC Error Injection Register (EIR) */
#define S32K3XX_XBIC_ESR_OFFSET (0x08) /* XBIC Error Status Register (ESR) */
#define S32K3XX_XBIC_EAR_OFFSET (0x0c) /* XBIC Error Address (EAR) */
/* XBIC Register Addresses **************************************************/
#define S32K3XX_XBIC0_MCR (S32K3XX_XBIC0_BASE + S32K3XX_XBIC_MCR_OFFSET)
#define S32K3XX_XBIC0_EIR (S32K3XX_XBIC0_BASE + S32K3XX_XBIC_EIR_OFFSET)
#define S32K3XX_XBIC0_ESR (S32K3XX_XBIC0_BASE + S32K3XX_XBIC_ESR_OFFSET)
#define S32K3XX_XBIC0_EAR (S32K3XX_XBIC0_BASE + S32K3XX_XBIC_EAR_OFFSET)
#define S32K3XX_XBIC1_MCR (S32K3XX_XBIC1_BASE + S32K3XX_XBIC_MCR_OFFSET)
#define S32K3XX_XBIC1_EIR (S32K3XX_XBIC1_BASE + S32K3XX_XBIC_EIR_OFFSET)
#define S32K3XX_XBIC1_ESR (S32K3XX_XBIC1_BASE + S32K3XX_XBIC_ESR_OFFSET)
#define S32K3XX_XBIC1_EAR (S32K3XX_XBIC1_BASE + S32K3XX_XBIC_EAR_OFFSET)
#define S32K3XX_XBIC2_MCR (S32K3XX_XBIC2_BASE + S32K3XX_XBIC_MCR_OFFSET)
#define S32K3XX_XBIC2_EIR (S32K3XX_XBIC2_BASE + S32K3XX_XBIC_EIR_OFFSET)
#define S32K3XX_XBIC2_ESR (S32K3XX_XBIC2_BASE + S32K3XX_XBIC_ESR_OFFSET)
#define S32K3XX_XBIC2_EAR (S32K3XX_XBIC2_BASE + S32K3XX_XBIC_EAR_OFFSET)
#define S32K3XX_XBIC3_MCR (S32K3XX_XBIC3_BASE + S32K3XX_XBIC_MCR_OFFSET)
#define S32K3XX_XBIC3_EIR (S32K3XX_XBIC3_BASE + S32K3XX_XBIC_EIR_OFFSET)
#define S32K3XX_XBIC3_ESR (S32K3XX_XBIC3_BASE + S32K3XX_XBIC_ESR_OFFSET)
#define S32K3XX_XBIC3_EAR (S32K3XX_XBIC3_BASE + S32K3XX_XBIC_EAR_OFFSET)
/* XBIC Register Bitfield Definitions ***************************************/
/* XBIC Module Control Register (MCR) */
/* Bits 0-15: Reserved */
#define XBIC_MCR_ME7 (1 << 16) /* Bit 16: Master Port 7 Enable for Feedback Integrity Check (ME7) */
#define XBIC_MCR_ME6 (1 << 17) /* Bit 17: Master Port 6 Enable for Feedback Integrity Check (ME6) */
#define XBIC_MCR_ME5 (1 << 18) /* Bit 18: Master Port 5 Enable for Feedback Integrity Check (ME5) */
#define XBIC_MCR_ME4 (1 << 19) /* Bit 19: Master Port 4 Enable for Feedback Integrity Check (ME4) */
#define XBIC_MCR_ME3 (1 << 20) /* Bit 20: Master Port 3 Enable for Feedback Integrity Check (ME3) */
#define XBIC_MCR_ME2 (1 << 21) /* Bit 21: Master Port 2 Enable for Feedback Integrity Check (ME2) */
#define XBIC_MCR_ME1 (1 << 22) /* Bit 22: Master Port 1 Enable for Feedback Integrity Check (ME1) */
#define XBIC_MCR_ME0 (1 << 23) /* Bit 23: Master Port 0 Enable for Feedback Integrity Check (ME0) */
#define XBIC_MCR_SE7 (1 << 24) /* Bit 24: Slave Port 7 EDC Error Detection Enable (SE7) */
#define XBIC_MCR_SE6 (1 << 25) /* Bit 25: Slave Port 6 EDC Error Detection Enable (SE6) */
#define XBIC_MCR_SE5 (1 << 26) /* Bit 26: Slave Port 5 EDC Error Detection Enable (SE5) */
#define XBIC_MCR_SE4 (1 << 27) /* Bit 27: Slave Port 4 EDC Error Detection Enable (SE4) */
#define XBIC_MCR_SE3 (1 << 28) /* Bit 28: Slave Port 3 EDC Error Detection Enable (SE3) */
#define XBIC_MCR_SE2 (1 << 29) /* Bit 29: Slave Port 2 EDC Error Detection Enable (SE2) */
#define XBIC_MCR_SE1 (1 << 30) /* Bit 30: Slave Port 1 EDC Error Detection Enable (SE1) */
#define XBIC_MCR_SE0 (1 << 31) /* Bit 31: Slave Port 0 EDC Error Detection Enable (SE0) */
/* XBIC Error Injection Register (EIR) */
#define XBIC_EIR_SYN_SHIFT (0) /* Bits 0-7: Syndrome (SYN) */
#define XBIC_EIR_SYN_MASK (0xff << XBIC_EIR_SYN_SHIFT)
#define XBIC_EIR_MST_SHIFT (8) /* Bits 8-11: Target Master ID (MST) */
#define XBIC_EIR_MST_MASK (0x0f << XBIC_EIR_MST_SHIFT)
#define XBIC_EIR_SLV_SHIFT (12) /* Bits 12-14: Target Slave Port (SLV) */
#define XBIC_EIR_SLV_MASK (0x07 << XBIC_EIR_SLV_SHIFT)
/* Bits 15-30: Reserved */
#define XBIC_EIR_EIE (1 << 31) /* Bit 31: Errir Injection Enable (EIE) */
/* XBIC Error Status Register (ESR) */
#define XBIC_ESR_SYN_SHIFT (0) /* Bits 0-7: Syndrome (SYN) */
#define XBIC_ESR_SYN_MASK (0xff << XBIC_ESR_SYN_SHIFT)
#define XBIC_ESR_MST_SHIFT (8) /* Bits 8-11: Master ID (MST) */
#define XBIC_ESR_MST_MASK (0x0f << XBIC_ESR_MST_SHIFT)
#define XBIC_ESR_SLV_SHIFT (12) /* Bits 12-14: Slave Port (SLV) */
#define XBIC_ESR_SLV_MASK (0x07 << XBIC_ESR_SLV_SHIFT)
#define XBIC_ESR_DPME7 (1 << 15) /* Bit 15: Data Phase Master Port 7 Error (DPME7) */
#define XBIC_ESR_DPME6 (1 << 16) /* Bit 16: Data Phase Master Port 6 Error (DPME6) */
#define XBIC_ESR_DPME5 (1 << 17) /* Bit 17: Data Phase Master Port 5 Error (DPME5) */
#define XBIC_ESR_DPME4 (1 << 18) /* Bit 18: Data Phase Master Port 4 Error (DPME4) */
#define XBIC_ESR_DPME3 (1 << 19) /* Bit 19: Data Phase Master Port 3 Error (DPME3) */
#define XBIC_ESR_DPME2 (1 << 20) /* Bit 20: Data Phase Master Port 2 Error (DPME2) */
#define XBIC_ESR_DPME1 (1 << 21) /* Bit 21: Data Phase Master Port 1 Error (DPME1) */
#define XBIC_ESR_DPME0 (1 << 22) /* Bit 22: Data Phase Master Port 0 Error (DPME0) */
#define XBIC_ESR_DPSE7 (1 << 23) /* Bit 23: Data Phase Slave Port 7 Error (DPSE7) */
#define XBIC_ESR_DPSE6 (1 << 24) /* Bit 24: Data Phase Slave Port 6 Error (DPSE6) */
#define XBIC_ESR_DPSE5 (1 << 25) /* Bit 25: Data Phase Slave Port 5 Error (DPSE5) */
#define XBIC_ESR_DPSE4 (1 << 26) /* Bit 26: Data Phase Slave Port 4 Error (DPSE4) */
#define XBIC_ESR_DPSE3 (1 << 27) /* Bit 27: Data Phase Slave Port 3 Error (DPSE3) */
#define XBIC_ESR_DPSE2 (1 << 28) /* Bit 28: Data Phase Slave Port 2 Error (DPSE2) */
#define XBIC_ESR_DPSE1 (1 << 29) /* Bit 29: Data Phase Slave Port 1 Error (DPSE1) */
#define XBIC_ESR_DPSE0 (1 << 30) /* Bit 30: Data Phase Slave Port 0 Error (DPSE0) */
#define XBIC_ESR_VLD (1 << 31) /* Bit 31: Error Status Valid (VLD) */
/* XBIC Error Address (EAR) */
#define XBIC_EAR_ADDR_SHIFT (0) /* Bits 0-31: Error Address (ADDR) */
#define XBIC_EAR_ADDR_MASK (0xffffffff << XBIC_EAR_ADDR_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_XBIC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/hardware/s32k3xx_xrdc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_XRDC_H
#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_XRDC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/s32k3xx_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* XRDC Register Offsets ****************************************************/
#define S32K3XX_XRDC_CR_OFFSET (0x0000) /* Control Register (CR) */
#define S32K3XX_XRDC_HWCFG0_OFFSET (0x00f0) /* Hardware Configuration Register 0 (HWCFG0) */
#define S32K3XX_XRDC_HWCFG1_OFFSET (0x00f4) /* Hardware Configuration Register 1 (HWCFG1) */
#define S32K3XX_XRDC_HWCFG2_OFFSET (0x00f8) /* Hardware Configuration Register 2 (HWCFG2) */
#define S32K3XX_XRDC_MDACFG0_OFFSET (0x0100) /* Master Domain Assignment Configuration Register 0 (MDACFG0) */
#define S32K3XX_XRDC_MDACFG1_OFFSET (0x0101) /* Master Domain Assignment Configuration Register 1 (MDACFG1) */
#define S32K3XX_XRDC_MDACFG2_OFFSET (0x0102) /* Master Domain Assignment Configuration Register 2 (MDACFG2) */
#define S32K3XX_XRDC_MDACFG3_OFFSET (0x0103) /* Master Domain Assignment Configuration Register 3 (MDACFG3) */
#define S32K3XX_XRDC_MDACFG4_OFFSET (0x0104) /* Master Domain Assignment Configuration Register 4 (MDACFG4) */
#define S32K3XX_XRDC_MDACFG5_OFFSET (0x0105) /* Master Domain Assignment Configuration Register 5 (MDACFG5) */
#define S32K3XX_XRDC_MRCFG0_OFFSET (0x0140) /* Memory Region Configuration Register 0 (MRCFG0) */
#define S32K3XX_XRDC_MRCFG1_OFFSET (0x0141) /* Memory Region Configuration Register 1 (MRCFG1) */
#define S32K3XX_XRDC_MRCFG2_OFFSET (0x0142) /* Memory Region Configuration Register 2 (MRCFG2) */
#define S32K3XX_XRDC_DERRLOC0_OFFSET (0x0200) /* Domain Error Location Register 0 (DERRLOC0) */
#define S32K3XX_XRDC_DERRLOC1_OFFSET (0x0204) /* Domain Error Location Register 1 (DERRLOC1) */
#define S32K3XX_XRDC_DERRLOC2_OFFSET (0x0208) /* Domain Error Location Register 2 (DERRLOC2) */
#define S32K3XX_XRDC_DERR_W0_0_OFFSET (0x0400) /* Domain Error Word 0 (DERR_W0_0) */
#define S32K3XX_XRDC_DERR_W1_0_OFFSET (0x0404) /* Domain Error Word 1 (DERR_W1_0) */
#define S32K3XX_XRDC_DERR_W3_0_OFFSET (0x040c) /* Domain Error Word 3 (DERR_W3_0) */
#define S32K3XX_XRDC_DERR_W0_1_OFFSET (0x0410) /* Domain Error Word 0 (DERR_W0_1) */
#define S32K3XX_XRDC_DERR_W1_1_OFFSET (0x0414) /* Domain Error Word 1 (DERR_W1_1) */
#define S32K3XX_XRDC_DERR_W3_1_OFFSET (0x041c) /* Domain Error Word 3 (DERR_W3_1) */
#define S32K3XX_XRDC_DERR_W0_2_OFFSET (0x0420) /* Domain Error Word 0 (DERR_W0_2) */
#define S32K3XX_XRDC_DERR_W1_2_OFFSET (0x0424) /* Domain Error Word 1 (DERR_W1_2) */
#define S32K3XX_XRDC_DERR_W3_2_OFFSET (0x042c) /* Domain Error Word 3 (DERR_W3_2) */
#define S32K3XX_XRDC_DERR_W0_16_OFFSET (0x0500) /* Domain Error Word 0 (DERR_W0_16) */
#define S32K3XX_XRDC_DERR_W1_16_OFFSET (0x0504) /* Domain Error Word 1 (DERR_W1_16) */
#define S32K3XX_XRDC_DERR_W3_16_OFFSET (0x050c) /* Domain Error Word 3 (DERR_W3_16) */
#define S32K3XX_XRDC_DERR_W0_17_OFFSET (0x0510) /* Domain Error Word 0 (DERR_W0_17) */
#define S32K3XX_XRDC_DERR_W1_17_OFFSET (0x0514) /* Domain Error Word 1 (DERR_W1_17) */
#define S32K3XX_XRDC_DERR_W3_17_OFFSET (0x051c) /* Domain Error Word 3 (DERR_W3_17) */
#define S32K3XX_XRDC_DERR_W0_18_OFFSET (0x0520) /* Domain Error Word 0 (DERR_W0_18) */
#define S32K3XX_XRDC_DERR_W1_18_OFFSET (0x0524) /* Domain Error Word 1 (DERR_W1_18) */
#define S32K3XX_XRDC_DERR_W3_18_OFFSET (0x052c) /* Domain Error Word 3 (DERR_W3_18) */
#define S32K3XX_XRDC_PID0_OFFSET (0x0700) /* Process Identifier (PID0) */
#define S32K3XX_XRDC_PID3_OFFSET (0x070c) /* Process Identifier (PID3) */
#define S32K3XX_XRDC_PID4_OFFSET (0x0710) /* Process Identifier (PID4) */
#define S32K3XX_XRDC_MDA_W0_0_DFMT0_OFFSET (0x0800) /* Master Domain Assignment (MDA_W0_0_DFMT0) */
#define S32K3XX_XRDC_MDA_W0_1_DFMT1_OFFSET (0x0820) /* Master Domain Assignment (MDA_W0_1_DFMT1) */
#define S32K3XX_XRDC_MDA_W0_2_DFMT1_OFFSET (0x0840) /* Master Domain Assignment (MDA_W0_2_DFMT1) */
#define S32K3XX_XRDC_MDA_W0_3_DFMT0_OFFSET (0x0860) /* Master Domain Assignment (MDA_W0_3_DFMT0) */
#define S32K3XX_XRDC_MDA_W0_4_DFMT0_OFFSET (0x0870) /* Master Domain Assignment (MDA_W0_4_DFMT0) */
#define S32K3XX_XRDC_MDA_W0_5_DFMT1_OFFSET (0x08a0) /* Master Domain Assignment (MDA_W0_5_DFMT1) */
#define S32K3XX_XRDC_PDAC_W0_OFFSET(n) (0x1100 + (((n) - 32) << 3)) /* Peripheral Domain Access Control (PDAC_W0_n, n=32..315) */
#define S32K3XX_XRDC_PDAC_W1_OFFSET(n) (0x1104 + (((n) - 32) << 3)) /* Peripheral Domain Access Control (PDAC_W1_n, n=32..315) */
#define S32K3XX_XRDC_MRGD_W0_OFFSET(n) (0x2000 + ((n) << 5)) /* Memory Region Descriptor (MRGD_W0_n, n=0..35) */
#define S32K3XX_XRDC_MRGD_W1_OFFSET(n) (0x2004 + ((n) << 5)) /* Memory Region Descriptor (MRGD_W1_n, n=0..35) */
#define S32K3XX_XRDC_MRGD_W2_OFFSET(n) (0x2008 + ((n) << 5)) /* Memory Region Descriptor (MRGD_W2_n, n=0..35) */
#define S32K3XX_XRDC_MRGD_W3_OFFSET(n) (0x200c + ((n) << 5)) /* Memory Region Descriptor (MRGD_W3_n, n=0..35) */
/* XRDC Register Addresses **************************************************/
#define S32K3XX_XRDC_CR (S32K3XX_XRDC_BASE + S32K3XX_XRDC_CR_OFFSET)
#define S32K3XX_XRDC_HWCFG0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_HWCFG0_OFFSET)
#define S32K3XX_XRDC_HWCFG1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_HWCFG1_OFFSET)
#define S32K3XX_XRDC_HWCFG2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_HWCFG2_OFFSET)
#define S32K3XX_XRDC_MDACFG0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDACFG0_OFFSET)
#define S32K3XX_XRDC_MDACFG1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDACFG0_OFFSET)
#define S32K3XX_XRDC_MDACFG2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDACFG0_OFFSET)
#define S32K3XX_XRDC_MDACFG3 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDACFG0_OFFSET)
#define S32K3XX_XRDC_MDACFG4 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDACFG0_OFFSET)
#define S32K3XX_XRDC_MDACFG5 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDACFG0_OFFSET)
#define S32K3XX_XRDC_MRCFG0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRCFG0_OFFSET)
#define S32K3XX_XRDC_MRCFG1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRCFG1_OFFSET)
#define S32K3XX_XRDC_MRCFG2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRCFG2_OFFSET)
#define S32K3XX_XRDC_DERRLOC0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERRLOC0_OFFSET)
#define S32K3XX_XRDC_DERRLOC1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERRLOC1_OFFSET)
#define S32K3XX_XRDC_DERRLOC2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERRLOC2_OFFSET)
#define S32K3XX_XRDC_DERR_W0_0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W0_0_OFFSET)
#define S32K3XX_XRDC_DERR_W1_0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W1_0_OFFSET)
#define S32K3XX_XRDC_DERR_W3_0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W3_0_OFFSET)
#define S32K3XX_XRDC_DERR_W0_1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W0_1_OFFSET)
#define S32K3XX_XRDC_DERR_W1_1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W1_1_OFFSET)
#define S32K3XX_XRDC_DERR_W3_1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W3_1_OFFSET)
#define S32K3XX_XRDC_DERR_W0_2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W0_2_OFFSET)
#define S32K3XX_XRDC_DERR_W1_2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W1_2_OFFSET)
#define S32K3XX_XRDC_DERR_W3_2 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W3_2_OFFSET)
#define S32K3XX_XRDC_DERR_W0_16 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W0_16_OFFSET)
#define S32K3XX_XRDC_DERR_W1_16 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W1_16_OFFSET)
#define S32K3XX_XRDC_DERR_W3_16 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W3_16_OFFSET)
#define S32K3XX_XRDC_DERR_W0_17 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W0_17_OFFSET)
#define S32K3XX_XRDC_DERR_W1_17 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W1_17_OFFSET)
#define S32K3XX_XRDC_DERR_W3_17 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W3_17_OFFSET)
#define S32K3XX_XRDC_DERR_W0_18 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W0_18_OFFSET)
#define S32K3XX_XRDC_DERR_W1_18 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W1_18_OFFSET)
#define S32K3XX_XRDC_DERR_W3_18 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_DERR_W3_18_OFFSET)
#define S32K3XX_XRDC_PID0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_PID0_OFFSET)
#define S32K3XX_XRDC_PID3 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_PID3_OFFSET)
#define S32K3XX_XRDC_PID4 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_PID4_OFFSET)
#define S32K3XX_XRDC_MDA_W0_0_DFMT0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDA_W0_0_DFMT0_OFFSET)
#define S32K3XX_XRDC_MDA_W0_1_DFMT1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDA_W0_1_DFMT1_OFFSET)
#define S32K3XX_XRDC_MDA_W0_2_DFMT1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDA_W0_2_DFMT1_OFFSET)
#define S32K3XX_XRDC_MDA_W0_3_DFMT0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDA_W0_3_DFMT0_OFFSET)
#define S32K3XX_XRDC_MDA_W0_4_DFMT0 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDA_W0_4_DFMT0_OFFSET)
#define S32K3XX_XRDC_MDA_W0_5_DFMT1 (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MDA_W0_5_DFMT1_OFFSET)
#define S32K3XX_XRDC_PDAC_W0(n) (S32K3XX_XRDC_BASE + S32K3XX_XRDC_PDAC_W0_OFFSET(n))
#define S32K3XX_XRDC_PDAC_W1(n) (S32K3XX_XRDC_BASE + S32K3XX_XRDC_PDAC_W1_OFFSET(n))
#define S32K3XX_XRDC_MRGD_W0(n) (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRGD_W0_OFFSET(n))
#define S32K3XX_XRDC_MRGD_W1(n) (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRGD_W1_OFFSET(n))
#define S32K3XX_XRDC_MRGD_W2(n) (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRGD_W2_OFFSET(n))
#define S32K3XX_XRDC_MRGD_W3(n) (S32K3XX_XRDC_BASE + S32K3XX_XRDC_MRGD_W3_OFFSET(n))
/* XRDC Register Bitfield Definitions ***************************************/
/* Control Register (CR) */
#define XRDC_CR_GVLD (1 << 0) /* Bit 0: Global Valid (XRDC Global Enable/Disable) (GLVD) */
#define XRDC_CR_HRL_SHIFT (1) /* Bits 1-4: Hardware Revision Level (HRL) */
#define XRDC_CR_HRL_MASK (0x0f << XRDC_CR_HRL_SHIFT)
/* Bits 5-6: Reserved */
#define XRDC_CR_MRF (1 << 7) /* Bit 7: Memory Region Format (MRF) */
#define XRDC_CR_VAW (1 << 8) /* Bit 8: Virtualization Aware (VAW) */
/* Bit 9-29: Reserved */
#define XRDC_CR_LK1 (1 << 30) /* Bit 30: Lock (LK1) */
/* Bit 31: Reserved */
/* Hardware Configuration Register 0 (HWCFG0) */
#define XRDC_HWCFG0_NDID_SHIFT (0) /* Bits 0-7: Number Of Domains (NDID) */
#define XRDC_HWCFG0_NDID_MASK (0xff << XRDC_HWCFG0_NDID_SHIFT)
#define XRDC_HWCFG0_NMSTR_SHIFT (8) /* Bits 8-15: Number Of Bus Masters (NMSTR) */
#define XRDC_HWCFG0_NMSTR_MASK (0xff << XRDC_HWCFG0_NMSTR_SHIFT)
#define XRDC_HWCFG0_NMRC_SHIFT (16) /* Bits 16-23: Number Of MRCs (NMRC) */
#define XRDC_HWCFG0_NMRC_MASK (0xff << XRDC_HWCFG0_NMRC_SHIFT)
#define XRDC_HWCFG0_NPAC_SHIFT (24) /* Bits 24-27: Number of PACs (NPAC) */
#define XRDC_HWCFG0_NPAC_MASK (0x0f << XRDC_HWCFG0_NPAC_SHIFT)
#define XRDC_HWCFG0_MID_SHIFT (28) /* Bits 28-31: Module ID (MID) */
#define XRDC_HWCFG0_MID_MASK (0x0f << XRDC_HWCFG0_MID_SHIFT)
/* Hardware Configuration Register 1 (HWCFG1) */
#define XRDC_HWCFG1_DID_SHIFT (0) /* Bits 0-3: Domain Identifier Number (DID) */
#define XRDC_HWCFG1_DID_MASK (0x0f << XRDC_HWCFG1_DID_SHIFT)
/* Bits 4-31: Reserved */
/* Hardware Configuration Register 2 (HWCFG2) */
#define XRDC_HWCFG2_PIDP(n) (1 << (n)) /* Bit n: Process Identifier n Present (PIDPn) */
/* Master Domain Assignment Configuration Register n (MDACFGn) */
#define XRDC_MDACFG_NMDAR_SHIFT (0) /* Bits 0-3: Number Of Master Domain Assignment Registers for Bus Master n (NMDAR) */
#define XRDC_MDACFG_NMDAR_MASK (0x0f << XRDC_MDACFG_NMDAR_SHIFT)
/* Bits 4-6: Reserved */
#define XRDC_MDACFG_NCM (1 << 7) /* Bit 7: Non-CPU Master (NCM) */
/* Memory Region Configuration Register n (MRCFGn) */
#define XRDC_MRCFG_NMRGD_SHIFT (0) /* Bits 0-4: Number Of Memory Region Descriptor For Memory Region Controller n (NMRGD) */
#define XRDC_MRCFG_NMRGD_MASK (0x1f << XRDC_MRCFG_NMRGD_SHIFT)
/* Bits 5-7: Reserved */
/* Domain Error Location Register n (DERRLOCn) */
#define XRDC_DERRLOC_MRCINST_SHIFT (0) /* Bits 0-15: MRC Instance (MCRINST) */
#define XRDC_DERRLOC_MRCINST_MASK (0xffff << XRDC_DERRLOC_MRCINST_SHIFT)
#define XRDC_DERRLOC_PACINST_SHIFT (16) /* Bits 16-19: PAC Instance (PACINST) */
#define XRDC_DERRLOC_PACINST_MASK (0x0f << XRDC_DERRLOC_PACINST_SHIFT)
/* Bits 20-31: Reserved */
/* Domain Error Word 0 (DERR_W0_n) */
#define XRDC_DERR_W0_EADDR_SHIFT (0) /* Bits 0-31: Error Address (EADDR) */
#define XRDC_DERR_W0_EADDR_MASK (0xffffffff << XRDC_DERR_W0_EADDR_SHIFT)
/* Domain Error Word 1 (DERR_W1_n) */
#define XRDC_DERR_W1_EDID_SHIFT (0) /* Bits 0-3: Error Domain Identifier (EDID) */
#define XRDC_DERR_W1_EDID_MASK (0x0f << XRDC_DERR_W1_EDID_SHIFT)
/* Bits 4-7: Reserved */
#define XRDC_DERR_W1_EATR_SHIFT (8) /* Bits 8-10: Error Attributes (EATR) */
#define XRDC_DERR_W1_EATR_MASK (0x07 << XRDC_DERR_W1_EATR_SHIFT)
# define XRDC_DERR_W1_EATR_SUM_IFA (0x00 << XRDC_DERR_W1_EATR_SHIFT) /* Secure user mode, instruction fetch access */
# define XRDC_DERR_W1_EATR_SUM_DA (0x01 << XRDC_DERR_W1_EATR_SHIFT) /* Secure user mode, data access */
# define XRDC_DERR_W1_EATR_SPM_IFA (0x02 << XRDC_DERR_W1_EATR_SHIFT) /* Secure privileged mode, instruction fetch access */
# define XRDC_DERR_W1_EATR_SPM_DA (0x03 << XRDC_DERR_W1_EATR_SHIFT) /* Secure privileged mode, data access */
# define XRDC_DERR_W1_EATR_NSUM_IFA (0x04 << XRDC_DERR_W1_EATR_SHIFT) /* Nonsecure user mode, instruction fetch access */
# define XRDC_DERR_W1_EATR_NSUM_DA (0x05 << XRDC_DERR_W1_EATR_SHIFT) /* Nonsecure user mode, data access */
# define XRDC_DERR_W1_EATR_NSPM_IFA (0x06 << XRDC_DERR_W1_EATR_SHIFT) /* Nonsecure privileged mode, instruction fetch access */
# define XRDC_DERR_W1_EATR_NSPM_DA (0x07 << XRDC_DERR_W1_EATR_SHIFT) /* Nonsecure privileged mode, data access */
#define XRDC_DERR_W1_ERW (1 << 11) /* Bit 11: Error Read/Write (ERW) */
/* Bits 12-23: Reserved */
#define XRDC_DERR_W1_EPORT_SHIFT (24) /* Bits 24-26: Error Port (EPORT) */
#define XRDC_DERR_W1_EPORT_MASK (0x07 << XRDC_DERR_W1_EPORT_SHIFT)
/* Bits 27-29: Reserved */
#define XRDC_DERR_W1_EST_SHIFT (30) /* Bits 30-31: Error State (EST) */
#define XRDC_DERR_W1_EST_MASK (0x03 << XRDC_DERR_W1_EST_SHIFT)
/* Domain Error Word 3 (DERR_W3_n) */
/* Bits 0-29: Reserved */
#define XRDC_DERR_W3_RECR_SHIFT (30) /* Bits 30-31: Rearm Error Capture Registers (RECR) */
#define XRDC_DERR_W3_RECR_MASK (0x03 << XRDC_DERR_W3_RECR_SHIFT)
#define XRDC_DERR_W3_RECR_REARM (0x01 << XRDC_DERR_W3_RECR_SHIFT) /* Rearm the error capture mechanism and clear registers DERR_W0_n and DERR_W1_n */
/* Process Identifier (PIDn) */
#define XRDC_PID_PID_SHIFT (0) /* Bits 0-5: Process Identifier (PID) */
#define XRDC_PID_PID_MASK (0x3f << XRDC_PID_PID_SHIFT)
/* Bits 6-15: Reserved */
#define XRDC_PID_LMNUM_SHIFT (16) /* Bits 16-21: Locked Master Number (LMNUM) */
#define XRDC_PID_LMNUM_MASK (0x03f << XRDC_PID_LMNUM_SHIFT)
/* Bits 22-23: Reserved */
#define XRDC_PID_ELK22H (1 << 24) /* Bit 24: Enable (LK2 = 2) Special Handling (ELK22H) */
/* Bits 25-27: Reserved */
#define XRDC_PID_TSM (1 << 28) /* Bit 28: Three-State Model (TSM) */
#define XRDC_PID_LK2_SHIFT (29) /* Bits 29-30: Lock (LK2) */
#define XRDC_PID_LK2_MASK (0x03 << XRDC_PID_LK2_SHIFT)
# define XRDC_PID_LK2_ANY (0x00 << XRDC_PID_LK2_SHIFT) /* Register can be written to by any secure privileged write */
# define XRDC_PID_LK2_MASTER (0x02 << XRDC_PID_LK2_SHIFT) /* Register can only be written by a secure privileged write from bus master n */
# define XRDC_PID_LK2_LOCKED (0x03 << XRDC_PID_LK2_SHIFT) /* Register locked (read-only) until the next reset */
/* Bit 31: Reserved */
/* Master Domain Assignment (MDA_W0_n_DFMT0, n=0,3,4) */
#define XRDC_MDA_W0_DFMT0_DID_SHIFT (0) /* Bits 0-1: Domain Identifier (DID) */
#define XRDC_MDA_W0_DFMT0_DID_MASK (0x03 << XRDC_MDA_W0_DFMT0_DID_SHIFT)
/* Bits 2-3: Reserved */
#define XRDC_MDA_W0_DFMT0_DIDS_SHIFT (4) /* Bits 4-5: DID Select (DIDS) */
#define XRDC_MDA_W0_DFMT0_DIDS_MASK (0x03 << XRDC_MDA_W0_DFMT0_DIDS_SHIFT)
# define XRDC_MDA_W0_DFMT0_DIDS_REGISTER (0x00 << XRDC_MDA_W0_DFMT0_DIDS_SHIFT) /* Use the DID field of this register as the domain identifier */
# define XRDC_MDA_W0_DFMT0_DIDS_INPUT (0x01 << XRDC_MDA_W0_DFMT0_DIDS_SHIFT) /* Use the input DID sa the domain identifier */
# define XRDC_MDA_W0_DFMT0_DIDS_COMBINED (0x02 << XRDC_MDA_W0_DFMT0_DIDS_SHIFT) /* Use bits [3:2] of this register concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier */
#define XRDC_MDA_W0_DFMT0_PE_SHIFT (6) /* Bits 6-7: Process Identifier Enable (PE) */
#define XRDC_MDA_W0_DFMT0_PE_MASK (0x03 << XRDC_MDA_W0_DFMT0_PE_SHIFT)
# define XRDC_MDA_W0_DFMT0_PE_NOPID (0x00 << XRDC_MDA_W0_DFMT0_PE_SHIFT) /* No process identifier is included in the domain hit evaluation */
# define XRDC_MDA_W0_DFMT0_PE2 (0x02 << XRDC_MDA_W0_DFMT0_PE_SHIFT) /* The process identifier is included in the domain hit evaluation (see reference manual) */
# define XRDC_MDA_W0_DFMT0_PE3 (0x03 << XRDC_MDA_W0_DFMT0_PE_SHIFT) /* The process identifier is included in the domain hit evaluation (see reference manual) */
#define XRDC_MDA_W0_DFMT0_PIDM_SHIFT (8) /* Bits 8-13: Process Identifier Mask (PIDM) */
#define XRDC_MDA_W0_DFMT0_PIDM_MASK (0x3f << XRDC_MDA_W0_DFMT0_PIDM_SHIFT)
/* Bits 14-15: Reserved */
#define XRDC_MDA_W0_DFMT0_PID_SHIFT (16) /* Bits 16-21: Process Identifier (PID) */
#define XRDC_MDA_W0_DFMT0_PID_MASK (0x3f << XRDC_MDA_W0_DFMT0_PID_SHIFT)
/* Bits 22-28: Reserved */
#define XRDC_MDA_W0_DFMT0_DFMT (1 << 29) /* Bit 29: Domain Format (DFMT) */
#define XRDC_MDA_W0_DFMT0_LK1 (1 << 30) /* Bit 30: Lock (LK1) */
#define XRDC_MDA_W0_DFMT0_VLD (1 << 31) /* Bit 31: Valid (VLD) */
/* Master Domain Assignment (MDA_W0_n_DFMT1, n=1,2,5) */
#define XRDC_MDA_W0_DFMT1_DID_SHIFT (0) /* Bits 0-1: Domain Identifier (DID) */
#define XRDC_MDA_W0_DFMT1_DID_MASK (0x03 << XRDC_MDA_W0_DFMT0_DID_SHIFT)
/* Bits 2-3: Reserved */
#define XRDC_MDA_W0_DFMT1_PA_SHIFT (4) /* Bits 4-5: Privileged Attribute (PA) */
#define XRDC_MDA_W0_DFMT1_PA_MASK (0x03 << XRDC_MDA_W0_DFMT1_PA_SHIFT)
#define XRDC_MDA_W0_DFMT1_SA_SHIFT (6) /* Bits 6-7: Secure Attribute (SA) */
#define XRDC_MDA_W0_DFMT1_SA_MASK (0x03 << XRDC_MDA_W0_DFMT1_SA_SHIFT)
#define XRDC_MDA_W0_DFMT1_DIDB (1 << 8) /* Bit 8: DID Bypass (DIDB) */
/* Bits 9-28: Reserved */
#define XRDC_MDA_W0_DFMT1_DFMT (1 << 29) /* Bit 29: Domain Format (DFMT) */
#define XRDC_MDA_W0_DFMT1_LK1 (1 << 30) /* Bit 30: Lock (LK1) */
#define XRDC_MDA_W0_DFMT1_VLD (1 << 31) /* Bit 31: Valid (VLD) */
/* Peripheral Domain Access Control (PDAC_W0_n, n=32..315) */
#define XRDC_PDAC_W0_D0ACP_SHIFT (0) /* Bits 0-2: Domain 0 Access Control Policy (D0ACP) */
#define XRDC_PDAC_W0_D0ACP_MASK (0x07 << XRDC_PDAC_W0_D0ACP_SHIFT)
#define XRDC_PDAC_W0_D1ACP_SHIFT (3) /* Bits 3-5: Domain 1 Access Control Policy (D1ACP) */
#define XRDC_PDAC_W0_D1ACP_MASK (0x07 << XRDC_PDAC_W0_D1ACP_SHIFT)
#define XRDC_PDAC_W0_D2ACP_SHIFT (6) /* Bits 6-8: Domain 2 Access Control Policy (D2ACP) */
#define XRDC_PDAC_W0_D2ACP_MASK (0x07 << XRDC_PDAC_W0_D2ACP_SHIFT)
/* Bits 9-23: Reserved */
#define XRDC_PDAC_W0_SNUM_SHIFT (24) /* Bits 24-27: Semaphore Number (SNUM) */
#define XRDC_PDAC_W0_SNUM_MASK (0x0f << XRDC_PDAC_W0_SNUM_SHIFT)
/* Bits 28-29: Reserved */
#define XRDC_PDAC_W0_SE (1 << 30) /* Bit 30: Semaphore Enable (SE) */
/* Bit 31: Reserved */
/* Peripheral Domain Access Control (PDAC_W1_n, n=32..315) */
/* Bits 0-28: Reserved */
#define XRDC_PDAC_W1_LK2_SHIFT (29) /* Bits 29-30: Lock (LK2) */
#define XRDC_PDAC_W1_LK2_MASK (0x03 << XRDC_PDAC_W1_LK2_SHIFT)
#define XRDC_PDAC_W1_VLD (1 << 31) /* Bit 31: Valid (VLD) */
/* Memory Region Descriptor (MRGD_WD0_n, n=0..35) */
/* Bits 0-4: Reserved */
#define XRDC_MRGD_W0_SRTADDR_SHIFT (5) /* Bits 5-31: Start Address (SRTADDR) */
#define XRDC_MRGD_W0_SRTADDR_MASK (0x07ffffff << XRDC_MRGD_W0_SRTADDR_SHIFT)
/* Memory Region Descriptor (MRGD_W1_n, n=0..35) */
/* Bits 0-4: Reserved */
#define XRDC_MRGD_W1_ENDADDR_SHIFT (5) /* Bits 5-31: End Address (ENDADDR) */
#define XRDC_MRGD_W1_ENDADDR_MASK (0x07ffffff << XRDC_MRGD_W1_ENDADDR_SHIFT)
/* Memory Region Descriptor (MRGD_WD2_n, n=0..35) */
#define XRDC_MRGD_W2_D0ACP_SHIFT (0) /* Bits 0-2: Domain 0 Access Control Policy (D0ACP) */
#define XRDC_MRGD_W2_D0ACP_MASK (0x07 << XRDC_MRGD_W2_D0ACP_SHIFT)
#define XRDC_MRGD_W2_D1ACP_SHIFT (3) /* Bits 3-5: Domain 1 Access Control Policy (D1ACP) */
#define XRDC_MRGD_W2_D1ACP_MASK (0x07 << XRDC_MRGD_W2_D1ACP_SHIFT)
#define XRDC_MRGD_W2_D2ACP_SHIFT (6) /* Bits 6-8: Domain 2 Access Control Policy (D2ACP) */
#define XRDC_MRGD_W2_D2ACP_MASK (0x07 << XRDC_MRGD_W2_D2ACP_SHIFT)
/* Bits 9-23: Reserved */
#define XRDC_MRGD_W2_SNUM_SHIFT (24) /* Bits 24-27: Semaphore Number (SNUM) */
#define XRDC_MRGD_W2_SNUM_MASK (0x0f << XRDC_MRGD_W2_SNUM_SHIFT)
/* Bits 28-29: Reserved */
#define XRDC_MRGD_W2_SE (1 << 30) /* Bit 30: Semaphore Enable (SE) */
/* Bit 31: Reserved */
/* Memory Region Descriptor (MRGD_WD3_n, n=0..35) */
/* Bits 0-28: Reserved */
#define XRDC_MRGD_W3_LK2_SHIFT (29) /* Bits 29-30: Lock (LK2) */
#define XRDC_MRGD_W3_LK2_MASK (0x03 << XRDC_MRGD_W3_LK2_SHIFT)
#define XRDC_MRGD_W3_VLD (1 << 31) /* Bit 31: Valid (VLD) */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_XRDC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/s32k3xx/chip.h>
#include "arm_internal.h"
#include "hardware/s32k3xx_memorymap.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a
* single heap access with the standard allocations (malloc/free). This
* heap is referred to as the user heap. In the protected build
* (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of
* otherwise flat memory, there will be two allocators: One that allocates
* protected (kernel) memory and one that allocates unprotected (user)
* memory. These are referred to as the kernel and user heaps,
* respectively.
*
* The ARMv7 has no MPU but does have an MMU. Without an MMU, it cannot
* support the kernel build (CONFIG_BUILD_KERNEL=y). In that configuration,
* there would is one kernel heap but multiple user heaps: One per task
* group. However, in this case, we need only be concerned about
* initializing the single kernel heap here.
*
* Primary RAM: The Linker script positions the system BLOB's .data and
* .bss in some RAM. We refer to that RAM as the primary RAM. It also
* holds the IDLE threads stack and any remaining portion of the primary
* OCRAM is automatically added to the heap. The linker provided address,
* ... .sbss, .ebss, .sdat, etc. ... are expected to lie in the the region
* defined by the OCRAM configuration settings.
*
* Other RAM regions must be selected use configuration options and the
* start and end of those RAM regions must also be provided in the
* configuration. CONFIG_MM_REGIONS must also be set to determined the
* number of regions to be added to the heap.
*
*
* SOC with 512KiB
*
* DTCM_BASE_ADDR 0x20000000 128K DTCM
* ITCM_BASE_ADDR 0x20000000 64K ITCM
* SRAM_BASE_ADDR 0x20400000 512KB OCRAM
*/
/* There there then several memory configurations with a one primary memory
* region and up to two additional memory regions which may be OCRAM, DTCM
* external SDRAM, or external SRAM.
*/
#undef S32K3XX_ITCM_ASSIGNED
#undef S32K3XX_DCTM_ASSIGNED
#undef S32K3XX_SRAM_ASSIGNED
#if CONFIG_MM_REGIONS > 1
/* Pick the first region to add to the heap could be any one of OCRAM, DTCM,
* SDRAM, or SRAM depending upon which are enabled and which has not
* already been assigned as the primary RAM.
*/
#if defined(CONFIG_S32K3XX_DTCM_HEAP) && !defined(S32K3XX_DCTM_ASSIGNED)
# define REGION1_RAM_START &DTCM_BASE_ADDR
# define REGION1_RAM_SIZE ((size_t)(&DTCM_END_ADDR) - (size_t)(&DTCM_BASE_ADDR))
# define S32K3XX_DCTM_ASSIGNED 1
#else
# warning CONFIG_MM_REGIONS > 1 but no available memory region
#endif
#define REGION1_RAM_END (REGION1_RAM_START + REGION1_RAM_SIZE)
#endif
/****************************************************************************
* Private Types
****************************************************************************/
extern const uint32_t SRAM_BASE_ADDR;
extern const uint32_t SRAM_END_ADDR;
extern const uint32_t SRAM_STDBY_BASE_ADDR;
extern const uint32_t SRAM_STDBY_END_ADDR;
extern const uint32_t ITCM_BASE_ADDR;
extern const uint32_t ITCM_END_ADDR;
extern const uint32_t DTCM_BASE_ADDR;
extern const uint32_t DTCM_END_ADDR;
/****************************************************************************
* Public Data
****************************************************************************/
/* _sbss is the start of the BSS region (see the linker script) _ebss is the
* end of the BSS regions (see the linker script). The idle task stack starts
* at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE
* thread is the thread that the system boots on and, eventually, becomes the
* idle, do nothing task that runs only when there is nothing else to run.
* The heap continues from there until the configured end of memory.
* g_idle_topstack is the beginning of this heap region (not necessarily
* aligned).
*/
const uintptr_t g_idle_topstack = (uintptr_t)&_ebss +
CONFIG_IDLETHREAD_STACKSIZE;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap/up_allocate_kheap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* - For the normal "flat" build, this function returns the size of the
* single heap.
* - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel-
* and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function
* provides the size of the unprotected, user-space heap.
* - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides
* the size of the protected, kernel-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated by an analogous up_allocate_kheap(). A custom version of this
* file is needed if memory protection of the kernel heap is required.
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. (size determined by
* CONFIG_IDLETHREAD_STACKSIZE).
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
#ifdef CONFIG_BUILD_KERNEL
void up_allocate_kheap(void **heap_start, size_t *heap_size)
#else
void up_allocate_heap(void **heap_start, size_t *heap_size)
#endif
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM_END_ADDR - ubase;
DEBUGASSERT(ubase < (uintptr_t)SRAM_END_ADDR);
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)ubase;
*heap_size = usize;
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)g_idle_topstack;
*heap_size = (size_t)(&SRAM_END_ADDR) -
(((size_t)&_ebss) + CONFIG_IDLETHREAD_STACKSIZE);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel-
* and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* the kernel-space heap. A custom version of this function is needed if
* memory protection of the kernel heap is required.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
DEBUGASSERT(ubase < (uintptr_t)SRAM_END_ADDR);
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
/* Add region 1 to the user heap */
kumm_addregion((void *)REGION1_RAM_START, REGION1_RAM_SIZE);
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to region 1 */
s32k3xx_mpu_uheap((uintptr_t)REGION1_RAM_START, REGION1_RAM_SIZE);
#endif
#if CONFIG_MM_REGIONS > 2
/* Add region 2 to the user heap */
kumm_addregion((void *)REGION2_RAM_START, REGION2_RAM_SIZE);
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to region 2 */
s32k3xx_mpu_uheap((uintptr_t)REGION2_RAM_START, REGION2_RAM_SIZE);
#endif
#endif /* CONFIG_MM_REGIONS > 2 */
}
#endif /* CONFIG_MM_REGIONS > 1 */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_CLKCONFIG_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_CLKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "s32k3xx_clocknames.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Nominal frequencies of internal clocks */
#define CGM_FIRC_LOWRANGE_FREQUENCY 3000000 /* 3MHz */
/* Only possible using HSE_B.CONFIG_REG_GPR[FIRC_DIV_SEL] */
#define CGM_FIRC_HIGHRANGE_FREQUENCY 48000000 /* 48MHz */
#define CGM_SIRC_FREQUENCY0 32000 /* 32kHz */
#define NUMBER_OF_TCLK_INPUTS 3
/****************************************************************************
* Public Types
****************************************************************************/
/* Clock Configuration ******************************************************/
enum cgm_system_clock_type_e
{
CGM_SYSTEM_CLOCK_CORE, /* Core clock */
CGM_SYSTEM_CLOCK_AIPS_PLAT_CLK, /* medium-speed peripheral clock */
CGM_SYSTEM_CLOCK_AIPS_SLOW_CLK, /* slow-speed peripheral clock */
CGM_SYSTEM_CLOCK_HSE_CLK, /* HSE clock */
CGM_SYSTEM_CLOCK_DCM_CLK, /* DCM clock */
CGM_SYSTEM_CLOCK_LBIST_CLK, /* LBIST clock */
CGM_SYSTEM_CLOCK_QSPI_MEM_CLK, /* QSPI clock */
};
enum cgm_csc_src_e
{
CGM_CLK_SRC_FIRC = 0,
CGM_CLK_SRC_SIRC = 1,
CGM_CLK_SRC_FXOSC = 2,
CGM_CLK_SRC_SXOSC = 4,
CGM_CLK_SRC_PLL_PHI0_CLK = 8,
CGM_CLK_SRC_PLL_PHI1_CLK = 9,
CGM_CLK_SRC_CORE_CLK = 16,
CGM_CLK_SRC_HSE_CLK = 19,
CGM_CLK_SRC_AIPS_PLAT_CLK = 22,
CGM_CLK_SRC_AIPS_SLOW_CLK = 23,
CGM_CLK_SRC_EMAC_RMII_TX_CLK = 24,
CGM_CLK_SRC_EMAC_RX_CLK = 25
};
/* These structure are used to define the clock configuration. */
/* CGM SIRC clock configuration */
enum cgm_sirc_range_e
{
CGM_FIRC_RANGE_32K = 1, /* Slow IRC is trimmed to 32kHz */
};
struct cgm_sirc_config_s
{
enum cgm_sirc_range_e range; /* Slow IRC frequency range */
};
/* CGM FIRC clock configuration */
enum cgm_firc_range_e
{
CGM_FIRC_RANGE_HIGH = 0, /* Slow IRC high range clock (48 MHz). */
};
enum cgm_firc_clock_div_e
{
CGM_CLOCK_DISABLE = 0, /* Clock output is disabled */
CGM_CLOCK_DIV_BY_1 = 1, /* Divided by 1 */
CGM_CLOCK_DIV_BY_2 = 2, /* Divided by 2 */
CGN_CLOCK_DIV_BY_16 = 5, /* Divided by 16 */
};
struct cgm_firc_config_s
{
enum cgm_firc_range_e range; /* Fast IRC frequency range */
enum cgm_firc_clock_div_e div; /* HSE FIRC DIV SEL */
};
/* CGM SOSC Clock Configuration */
enum cgm_mux_div_e
{
CGM_MUX_DISABLE = 0, /* Clock output is disabled */
CGM_MUX_DIV_BY_1 = 1, /* Divided by 1 */
CGM_MUX_DIV_BY_2 = 2, /* Divided by 2 */
CGM_MUX_DIV_BY_3 = 3, /* Divided by 3 */
CGM_MUX_DIV_BY_4 = 4, /* Divided by 4 */
CGM_MUX_DIV_BY_5 = 5, /* Divided by 5 */
CGM_MUX_DIV_BY_6 = 6, /* Divided by 6 */
CGM_MUX_DIV_BY_7 = 7, /* Divided by 7 */
CGM_MUX_DIV_BY_8 = 8, /* Divided by 8 */
};
enum cgm_mux_div_slow_e
{
CGM_MUX_SLOW_DISABLE = 0, /* Clock output is disabled */
CGM_MUX_DIV_SLOW_BY_1 = 1, /* Divided by 1 */
CGM_MUX_DIV_SLOW_BY_2 = 2, /* Divided by 2 */
CGM_MUX_DIV_SLOW_BY_3 = 3, /* Divided by 3 */
CGM_MUX_DIV_SLOW_BY_4 = 4, /* Divided by 4 */
CGM_MUX_DIV_SLOW_BY_5 = 5, /* Divided by 5 */
CGM_MUX_DIV_SLOW_BY_6 = 6, /* Divided by 6 */
CGM_MUX_DIV_SLOW_BY_7 = 7, /* Divided by 7 */
CGM_MUX_DIV_SLOW_BY_8 = 8, /* Divided by 8 */
CGM_MUX_DIV_SLOW_BY_9 = 8, /* Divided by 9 */
CGM_MUX_DIV_SLOW_BY_10 = 8, /* Divided by 10 */
CGM_MUX_DIV_SLOW_BY_11 = 8, /* Divided by 11 */
CGM_MUX_DIV_SLOW_BY_12 = 8, /* Divided by 12 */
};
enum cgm_scs_source_e
{
CGM_SCS_SOURCE_FIRC = 0,
CGM_SCS_SOURCE_PLL_PHI0 = 1
};
struct cgm_mux_config_s
{
enum cgm_mux_div_e div; /* Asynchronous peripheral source */
bool trigger; /* true: Common Trigger Divider update */
};
struct cgm_mux_slow_config_s
{
enum cgm_mux_div_slow_e div; /* Asynchronous peripheral source */
bool trigger; /* true: Common Trigger Divider update */
};
struct cgm_mux_src_config_s
{
enum cgm_csc_src_e source; /* MUX_X Clock src */
enum cgm_mux_div_e div; /* Note div ranges from 1..4 */
};
struct cgm_scs_config_s
{
enum cgm_scs_source_e scs_source;
struct cgm_mux_config_s core_clk;
struct cgm_mux_config_s aips_plat_clk;
struct cgm_mux_slow_config_s aips_slow_clk;
struct cgm_mux_config_s hse_clk;
struct cgm_mux_config_s dcm_clk;
struct cgm_mux_config_s lbist_clk;
#ifdef CONFIG_S32K3XX_QSPI
struct cgm_mux_config_s qspi_mem_clk;
#endif
struct cgm_mux_src_config_s mux_1_stm0;
struct cgm_mux_src_config_s mux_3;
struct cgm_mux_src_config_s mux_4;
#ifdef CONFIG_S32K3XX_ENET
struct cgm_mux_src_config_s mux_7_emac_rx;
struct cgm_mux_src_config_s mux_8_emac_tx;
struct cgm_mux_src_config_s mux_9_emac_ts;
#endif
#ifdef CONFIG_S32K3XX_QSPI
struct cgm_mux_src_config_s mux_10_qspi_sfck;
#endif
};
/* CGM PLL Clock Configuration */
enum scg_spll_monitor_mode_e
{
CGM_SPLL_MONITOR_DISABLE = 0, /* Monitor disable */
CGM_SPLL_MONITOR_INT = 1, /* Interrupt when system PLL error detected */
CGM_SPLL_MONITOR_RESET = 2 /* Reset when system PLL error detected */
};
enum cgm_pll_core_mode_e
{
CGM_PLL_INTEGER_MODE = 0,
CGM_PLL_FRACTIONAL_MODE = 1,
CGM_PLL_SSCG_MODE = 2
};
enum cgm_pll_sigma_delta_e
{
CGM_PLL_SIGMA_DELTA = 0,
CGM_PLL_SIGMA_DELTA_ORDER_2 = 1,
CGM_PLL_SIGMA_DELTA_ORDER_3 = 2
};
enum cgm_pll_postdiv_e
{
CGM_PLL_POSTDIV_DISABLE = 0, /* Clock output is disabled */
CGM_PLL_POSTDIV_BY_1 = 1, /* Divided by 1 */
CGM_PLL_POSTDIV_BY_2 = 2, /* Divided by 2 */
CGM_PLL_POSTDIV_BY_3 = 3, /* Divided by 3 */
CGM_PLL_POSTDIV_BY_4 = 4, /* Divided by 4 */
CGM_PLL_POSTDIV_BY_5 = 5, /* Divided by 5 */
CGM_PLL_POSTDIV_BY_6 = 6, /* Divided by 6 */
CGM_PLL_POSTDIV_BY_7 = 7, /* Divided by 7 */
CGM_PLL_POSTDIV_BY_8 = 8, /* Divided by 8 */
CGM_PLL_POSTDIV_BY_9 = 9, /* Divided by 9 */
CGM_PLL_POSTDIV_BY_10 = 10, /* Divided by 10 */
CGM_PLL_POSTDIV_BY_11 = 11, /* Divided by 11 */
};
enum cgm_pll_phi_div_e
{
CGM_PLL_PHI_DIV_DISABLE = 0, /* Clock output is disabled */
CGM_PLL_PHI_DIV_BY_1 = 1, /* Divided by 1 */
CGM_PLL_PHI_DIV_BY_2 = 2, /* Divided by 2 */
CGM_PLL_PHI_DIV_BY_3 = 3, /* Divided by 3 */
CGM_PLL_PHI_DIV_BY_4 = 4, /* Divided by 4 */
CGM_PLL_PHI_DIV_BY_5 = 5, /* Divided by 5 */
CGM_PLL_PHI_DIV_BY_6 = 6, /* Divided by 6 */
CGM_PLL_PHI_DIV_BY_7 = 7, /* Divided by 7 */
CGM_PLL_PHI_DIV_BY_8 = 8, /* Divided by 8 */
CGM_PLL_PHI_DIV_BY_9 = 9, /* Divided by 9 */
CGM_PLL_PHI_DIV_BY_10 = 10, /* Divided by 10 */
CGM_PLL_PHI_DIV_BY_11 = 11, /* Divided by 11 */
CGM_PLL_PHI_DIV_BY_12 = 12, /* Divided by 12 */
};
struct cgm_pll_config_s
{
uint32_t modul_freq;
uint32_t modul_depth;
bool core_pll_power;
bool modulation_type; /* true: modulation spread below */
enum cgm_pll_sigma_delta_e sigma_delta;
bool enable_dither;
enum cgm_pll_core_mode_e mode; /* Core PLL mode */
uint8_t prediv; /* PLL reference clock divider */
uint8_t mult; /* PLL multiplier */
enum cgm_pll_postdiv_e postdiv;
enum cgm_pll_phi_div_e phi0;
enum cgm_pll_phi_div_e phi1;
};
enum cgm_clkout_div_e
{
CGM_CLKOUT_DIV_DISABLE = 0, /* Clock output is disabled */
CGM_CLKOUT_DIV_BY_1 = 1, /* Divided by 1 */
CGM_CLKOUT_DIV_BY_2 = 2, /* Divided by 2 */
CGM_CLKOUT_DIV_BY_3 = 3, /* Divided by 3 */
CGM_CLKOUT_DIV_BY_4 = 4, /* Divided by 4 */
CGM_CLKOUT_DIV_BY_5 = 5, /* Divided by 5 */
CGM_CLKOUT_DIV_BY_6 = 6, /* Divided by 6 */
CGM_CLKOUT_DIV_BY_7 = 7, /* Divided by 7 */
CGM_CLKOUT_DIV_BY_8 = 8, /* Divided by 8 */
CGM_CLKOUT_DIV_BY_9 = 9, /* Divided by 9 */
CGM_CLKOUT_DIV_BY_10 = 10, /* Divided by 10 */
CGM_CLKOUT_DIV_BY_11 = 11, /* Divided by 11 */
CGM_CLKOUT_DIV_BY_12 = 12, /* Divided by 12 */
};
struct cgm_clkout_config_s
{
enum cgm_csc_src_e source;
enum cgm_clkout_div_e div;
};
/* Overall CGM Configuration */
struct cgm_config_s
{
struct cgm_sirc_config_s sirc; /* Slow internal reference clock configuration */
struct cgm_firc_config_s firc; /* Fast internal reference clock configuration */
struct cgm_scs_config_s scs; /* System oscillator configuration */
struct cgm_pll_config_s pll; /* Phase locked loop configuration */
struct cgm_clkout_config_s clkout; /* Phase locked loop configuration */
};
/* PCC clock configuration */
struct peripheral_clock_config_s; /* Forward reference */
struct pcc_config_s
{
unsigned int count; /* Number of peripherals to be configured */
const struct peripheral_clock_config_s *pclks; /* The peripheral clock configuration array */
};
/* Overall clock configuration */
struct clock_configuration_s
{
struct cgm_config_s cgm; /* CGM Clock configuration */
struct pcc_config_s pcc; /* PCC Clock configuration */
};
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_clockconfig
*
* Description:
* Called to initialize the S32K3XX. This does whatever setup is needed
* to put the MCU in a usable state. This includes the initialization of
* clocking using the settings in board.h. This function also performs
* other low-level chip as necessary.
*
* Input Parameters:
* clkcfg - Describes the new clock configuration
*
* Returned Value:
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
int s32k3xx_clockconfig(const struct clock_configuration_s *clkcfg);
/****************************************************************************
* Name: s32k3xx_get_coreclk
*
* Description:
* Return the current value of the CORE clock frequency.
*
* Input Parameters:
* None
*
* Returned Values:
* The current value of the CORE clock frequency. Zero is returned on any
* failure.
*
****************************************************************************/
uint32_t s32k3xx_get_coreclk(void);
/****************************************************************************
* Name: s32k3xx_get_sysclk
*
* Description:
* Return the current value of an CGM system clock frequency, these clocks
* are used for core, platform, external and bus clock domains..
*
* Input Parameters:
* type - Identifies the system clock of interest
*
* Returned Values:
* The current value of the system clock frequency. Zero is returned on
* any failure.
*
****************************************************************************/
uint32_t s32k3xx_get_sysclk(enum cgm_system_clock_type_e type);
/****************************************************************************
* Name: s32k3xx_get_freq
*
* Description:
* clock frequency from a clock source.
*
* Input Parameters:
* clksrc - The requested clock source.
*
* Returned Value:
* The frequency of the requested clock source.
*
****************************************************************************/
uint32_t s32k3xx_get_freq(enum clock_names_e clksrc);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_CLKCONFIG_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_clocknames.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_CLOCKNAMES_H
#define __ARCH_ARM_SRC_S32K3XX_CLOCKNAMES_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Types
****************************************************************************/
enum clock_names_e
{
/* Main clocks */
CORE_CLK = 0, /* Core clock */
AIPS_PLAT_CLK = 1, /* Bus clock */
AIPS_SLOW_CLK = 2, /* Slow clock */
HSE_CLK = 2, /* Slow clock */
DCM_CLK = 2, /* Slow clock */
LBIST_CLK = 2, /* Slow clock */
QSPI_MEM_CLK = 2, /* Slow clock */
SIRC_CLK = 3, /* CLKOUT clock */
FIRC_CLK = 4, /* CLKOUT clock */
PLL_PHI0_CLK = 7, /* CLKOUT clock */
PLL_PHI1_CLK = 8, /* CLKOUT clock */
SCS_CLK = 9, /* CLKOUT clock */
SCG_END_OF_CLOCKS = 18, /* End of SCG clocks */
/* MC_ME clocks */
TRGMUX_CLK = 32, /* Trigger Multiplexing Control */
BCTU_CLK = 33, /* Body Cross Triggering Unit */
EMIOS0_CLK = 34, /* eMIOS */
EMIOS1_CLK = 35, /* eMIOS */
EMIOS2_CLK = 36, /* eMIOS */
LCU0_CLK = 38, /* LCU */
LCU1_CLK = 39, /* LCU */
ADC0_CLK = 40, /* ADC */
ADC1_CLK = 41, /* ADC */
ADC2_CLK = 42, /* ADC */
PIT0_CLK = 44, /* Programmable Interrupt Timer 0 */
PIT1_CLK = 45, /* Programmable Interrupt Timer 1 */
MU_A_CLK = 46, /* MU_A */
MU_B_CLK = 47, /* MU_B */
EDMA_CLK = 131, /* eDMA */
EDMA_TCD0_CLK = 132, /* eDMA TCD0 */
EDMA_TCD1_CLK = 133, /* eDMA TCD1 */
EDMA_TCD2_CLK = 134, /* eDMA TCD2 */
EDMA_TCD3_CLK = 135, /* eDMA TCD3 */
EDMA_TCD4_CLK = 136, /* eDMA TCD4 */
EDMA_TCD5_CLK = 137, /* eDMA TCD5 */
EDMA_TCD6_CLK = 138, /* eDMA TCD6 */
EDMA_TCD7_CLK = 139, /* eDMA TCD7 */
EDMA_TCD8_CLK = 140, /* eDMA TCD8 */
EDMA_TCD9_CLK = 141, /* eDMA TCD9 */
EDMA_TCD10_CLK = 142, /* eDMA TCD10 */
EDMA_TCD11_CLK = 143, /* eDMA TCD11 */
SDA_AP_CLK = 149, /* SDA-AP */
EIM_CLK = 150, /* EIM */
ERM_CLK = 151, /* ERM */
MSCM_CLK = 152, /* MSCM */
SWT0_CLK = 156, /* Software Watchdog 0 */
STM0_CLK = 157, /* System Timer Module 0 */
INTM_CLK = 159, /* Interrupt Monitor */
DMAMUX0_CLK = 160, /* DMA Channel Multiplexer 0 */
DMAMUX1_CLK = 161, /* DMA Channel Multiplexer 1 */
RTC_CLK = 162, /* Real-time clock */
WKPU_CLK = 173, /* Wakeup Unit */
CMU_CLK = 175, /* CMU 0-5 */
TSPC_CLK = 177, /* Touch Sensing Pin Coupling Controller */
SXOSC_CLK = 178, /* 32 kHz Slow Internal RC Oscillator */
FXOSC_CLK = 181, /* 8-40 MHz Fast External Crystal Oscillator */
PLL_CLK = 184, /* Frequency Modulated Phase-Locked Loop */
PIT2_CLK = 191, /* Programmable Interrupt Timer 2 */
FLEXCAN0_CLK = 193, /* FlexCAN */
FLEXCAN1_CLK = 194, /* FlexCAN */
FLEXCAN2_CLK = 195, /* FlexCAN */
FLEXCAN3_CLK = 196, /* FlexCAN */
FLEXCAN4_CLK = 197, /* FlexCAN */
FLEXCAN5_CLK = 198, /* FlexCAN */
FLEXIO_CLK = 201, /* FlexIO */
LPUART0_CLK = 202, /* UART */
LPUART1_CLK = 203, /* UART */
LPUART2_CLK = 204, /* UART */
LPUART3_CLK = 205, /* UART */
LPUART4_CLK = 206, /* UART */
LPUART5_CLK = 207, /* UART */
LPUART6_CLK = 208, /* UART */
LPUART7_CLK = 209, /* UART */
LPI2C0_CLK = 212, /* I2C */
LPI2C1_CLK = 213, /* I2C */
LPSPI0_CLK = 214, /* SPI */
LPSPI1_CLK = 215, /* SPI */
LPSPI2_CLK = 216, /* SPI */
LPSPI3_CLK = 217, /* SPI */
SAI0_CLK = 219, /* Synchronous Audio Interface 0 */
LPCMP0_CLK = 220, /* Comparator 0 */
LPCMP1_CLK = 221, /* Comparator 1 */
TMU_CLK = 223, /* TempSense */
CRC_CLK = 224, /* CRC */
FCCU_CLK = 225, /* FCCU */
STCU2_CLK = 232, /* Self-Test Control Unit */
EDMA_TCD12_CLK = 260, /* eDMA TCD12 */
EDMA_TCD13_CLK = 261, /* eDMA TCD13 */
EDMA_TCD14_CLK = 262, /* eDMA TCD14 */
EDMA_TCD15_CLK = 263, /* eDMA TCD15 */
EDMA_TCD16_CLK = 264, /* eDMA TCD16 */
EDMA_TCD17_CLK = 265, /* eDMA TCD17 */
EDMA_TCD18_CLK = 266, /* eDMA TCD18 */
EDMA_TCD19_CLK = 267, /* eDMA TCD19 */
EDMA_TCD20_CLK = 268, /* eDMA TCD20 */
EDMA_TCD21_CLK = 269, /* eDMA TCD21 */
EDMA_TCD22_CLK = 270, /* eDMA TCD22 */
EDMA_TCD23_CLK = 271, /* eDMA TCD23 */
EDMA_TCD24_CLK = 272, /* eDMA TCD24 */
EDMA_TCD25_CLK = 273, /* eDMA TCD25 */
EDMA_TCD26_CLK = 274, /* eDMA TCD26 */
EDMA_TCD27_CLK = 275, /* eDMA TCD27 */
EDMA_TCD28_CLK = 276, /* eDMA TCD28 */
EDMA_TCD29_CLK = 277, /* eDMA TCD29 */
EDMA_TCD30_CLK = 278, /* eDMA TCD30 */
EDMA_TCD31_CLK = 279, /* eDMA TCD31 */
SEMA42_CLK = 280, /* Semaphores2 */
SWT1_CLK = 283, /* Software Watchdog 1 */
STM1_CLK = 285, /* System Timer Module 1 */
EMAC_CLK = 288, /* EMAC */
LPUART8_CLK = 291, /* UART */
LPUART9_CLK = 292, /* UART */
LPUART10_CLK = 293, /* UART */
LPUART11_CLK = 294, /* UART */
LPUART12_CLK = 295, /* UART */
LPUART13_CLK = 296, /* UART */
LPUART14_CLK = 297, /* UART */
LPUART15_CLK = 298, /* UART */
LPSPI4_CLK = 303, /* SPI */
LPSPI5_CLK = 304, /* SPI */
QSPI_CLK = 307, /* QSPI */
SAI1_CLK = 311, /* Synchronous Audio Interface 1 */
LPCMP2_CLK = 314, /* Comparator 2 */
CM7_0_TCM_CLK = 318, /* CM7_0_TCM */
CM7_1_TCM_CLK = 319, /* CM7_1_TCM */
CLOCK_NAME_COUNT = 92, /* The total number of entries */
};
#endif /* __ARCH_ARM_SRC_S32K3XX_CLOCKNAMES_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_clrpend.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include "nvic.h"
#include "arm_internal.h"
#include "s32k3xx_irq.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC. This does not seem to be
* required for most interrupts. Don't know why...
* but the S32K3xx Ethernet EMAC interrupt definitely needs it!
*
* This function is logically a part of s32k14x_irq.c, but I will keep it
* in a separate file so that it will not increase the footprint on S32K14x
* platforms that do not need this function.
*
****************************************************************************/
void s32k3xx_clrpend(int irq)
{
/* Check for external interrupt */
if (irq >= S32K3XX_IRQ_EXTINT)
{
irq -= S32K3XX_IRQ_EXTINT;
if (irq < 32)
{
putreg32(1 << irq , NVIC_IRQ0_31_CLRPEND);
}
else if (irq < 64)
{
putreg32(1 << (irq - 32), NVIC_IRQ32_63_CLRPEND);
}
else if (irq < 96)
{
putreg32(1 << (irq - 64), NVIC_IRQ64_95_CLRPEND);
}
else if (irq < 128)
{
putreg32(1 << (irq - 96), NVIC_IRQ96_127_CLRPEND);
}
else if (irq < S32K3XX_IRQ_NIRQS)
{
putreg32(1 << (irq - 128), NVIC_IRQ128_159_CLRPEND);
}
}
}

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_CONFIG_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_CONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#undef HAVE_LPUART0
#undef HAVE_LPUART1
#undef HAVE_LPUART2
#undef HAVE_LPUART3
#undef HAVE_LPUART4
#undef HAVE_LPUART5
#undef HAVE_LPUART6
#undef HAVE_LPUART7
#undef HAVE_LPUART8
#undef HAVE_LPUART9
#undef HAVE_LPUART10
#undef HAVE_LPUART11
#undef HAVE_LPUART12
#undef HAVE_LPUART13
#undef HAVE_LPUART14
#undef HAVE_LPUART15
#ifdef CONFIG_S32K3XX_LPUART0
# define HAVE_LPUART0 1
#endif
#ifdef CONFIG_S32K3XX_LPUART1
# define HAVE_LPUART1 1
#endif
#ifdef CONFIG_S32K3XX_LPUART2
# define HAVE_LPUART2 1
#endif
#ifdef CONFIG_S32K3XX_LPUART3
# define HAVE_LPUART3 1
#endif
#ifdef CONFIG_S32K3XX_LPUART4
# define HAVE_LPUART4 1
#endif
#ifdef CONFIG_S32K3XX_LPUART5
# define HAVE_LPUART5 1
#endif
#ifdef CONFIG_S32K3XX_LPUART6
# define HAVE_LPUART6 1
#endif
#ifdef CONFIG_S32K3XX_LPUART7
# define HAVE_LPUART7 1
#endif
#ifdef CONFIG_S32K3XX_LPUART8
# define HAVE_LPUART8 1
#endif
#ifdef CONFIG_S32K3XX_LPUART9
# define HAVE_LPUART9 1
#endif
#ifdef CONFIG_S32K3XX_LPUART10
# define HAVE_LPUART10 1
#endif
#ifdef CONFIG_S32K3XX_LPUART11
# define HAVE_LPUART11 1
#endif
#ifdef CONFIG_S32K3XX_LPUART12
# define HAVE_LPUART12 1
#endif
#ifdef CONFIG_S32K3XX_LPUART13
# define HAVE_LPUART13 1
#endif
#ifdef CONFIG_S32K3XX_LPUART14
# define HAVE_LPUART14 1
#endif
#ifdef CONFIG_S32K3XX_LPUART15
# define HAVE_LPUART15 1
#endif
/* Check if we have a LPUART device */
#undef CONFIG_S32K3XX_HAVE_LPUART
#undef HAVE_LPUART_DEVICE
#if defined(HAVE_LPUART0) || defined(HAVE_LPUART1) || \
defined(HAVE_LPUART2) || defined(HAVE_LPUART3) || \
defined(HAVE_LPUART4) || defined(HAVE_LPUART5) || \
defined(HAVE_LPUART6) || defined(HAVE_LPUART7) || \
defined(HAVE_LPUART8) || defined(HAVE_LPUART9) || \
defined(HAVE_LPUART10) || defined(HAVE_LPUART11) || \
defined(HAVE_LPUART12) || defined(HAVE_LPUART13) || \
defined(HAVE_LPUART14) || defined(HAVE_LPUART15)
# define HAVE_LPUART_DEVICE 1
#endif
/* Is there a serial console? There should be at most one defined.
* It could be on any LPUARTn, n=0,1,2,3
*/
#undef HAVE_LPUART_CONSOLE
#if defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(HAVE_LPUART0)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(HAVE_LPUART1)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) && defined(HAVE_LPUART2)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) && defined(HAVE_LPUART3)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) && defined(HAVE_LPUART4)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) && defined(HAVE_LPUART5)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) && defined(HAVE_LPUART6)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) && defined(HAVE_LPUART7)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) && defined(HAVE_LPUART8)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART9_SERIAL_CONSOLE) && defined(HAVE_LPUART9)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART10_SERIAL_CONSOLE) && defined(HAVE_LPUART10)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART11_SERIAL_CONSOLE) && defined(HAVE_LPUART11)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART12_SERIAL_CONSOLE) && defined(HAVE_LPUART12)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART13_SERIAL_CONSOLE) && defined(HAVE_LPUART13)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART14_SERIAL_CONSOLE) && defined(HAVE_LPUART14)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#elif defined(CONFIG_LPUART15_SERIAL_CONSOLE) && defined(HAVE_LPUART15)
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
#else
# ifdef CONFIG_DEV_CONSOLE
# warning "No valid CONFIG_LPUART[n]_SERIAL_CONSOLE Setting"
# endif
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_LPUART2_SERIAL_CONSOLE
# undef CONFIG_LPUART3_SERIAL_CONSOLE
# undef CONFIG_LPUART4_SERIAL_CONSOLE
# undef CONFIG_LPUART5_SERIAL_CONSOLE
# undef CONFIG_LPUART6_SERIAL_CONSOLE
# undef CONFIG_LPUART7_SERIAL_CONSOLE
# undef CONFIG_LPUART8_SERIAL_CONSOLE
# undef CONFIG_LPUART9_SERIAL_CONSOLE
# undef CONFIG_LPUART10_SERIAL_CONSOLE
# undef CONFIG_LPUART11_SERIAL_CONSOLE
# undef CONFIG_LPUART12_SERIAL_CONSOLE
# undef CONFIG_LPUART13_SERIAL_CONSOLE
# undef CONFIG_LPUART14_SERIAL_CONSOLE
# undef CONFIG_LPUART15_SERIAL_CONSOLE
#endif
/* Check LPUART flow control (Not yet supported) */
# undef CONFIG_LPUART0_FLOWCONTROL
# undef CONFIG_LPUART1_FLOWCONTROL
# undef CONFIG_LPUART2_FLOWCONTROL
# undef CONFIG_LPUART3_FLOWCONTROL
# undef CONFIG_LPUART4_FLOWCONTROL
# undef CONFIG_LPUART5_FLOWCONTROL
# undef CONFIG_LPUART6_FLOWCONTROL
# undef CONFIG_LPUART7_FLOWCONTROL
# undef CONFIG_LPUART8_FLOWCONTROL
# undef CONFIG_LPUART9_FLOWCONTROL
# undef CONFIG_LPUART10_FLOWCONTROL
# undef CONFIG_LPUART11_FLOWCONTROL
# undef CONFIG_LPUART12_FLOWCONTROL
# undef CONFIG_LPUART13_FLOWCONTROL
# undef CONFIG_LPUART14_FLOWCONTROL
# undef CONFIG_LPUART15_FLOWCONTROL
/* Ethernet controller configuration */
#ifndef CONFIG_S32K3XX_ENET_NRXBUFFERS
# define CONFIG_S32K3XX_ENET_NRXBUFFERS 6
#endif
#ifndef CONFIG_S32K3XX_ENET_NTXBUFFERS
# define CONFIG_S32K3XX_ENET_NTXBUFFERS 2
#endif
#ifndef CONFIG_S32K3XX_ENET_NETHIFS
# define CONFIG_S32K3XX_ENET_NETHIFS 1
#endif
#define S32K3XX_ENET_HAS_DBSWAP 1
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_CONFIG_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_edma.h
*
* Copyright (C) 2019, 2021 Gregory Nutt. All rights reserved.
* Copyright 2022 NXP
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david.sidrane@nscdg.com>
* Peter van der Perk <peter.vanderperk@nxp.com>
*
* This file was leveraged from the NuttX S32K1 port. Portions of that eDMA
* logic derived from NXP sample code which has a compatible BSD 3-clause
* license:
*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_EDMAC_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_EDMAC_H
/* General Usage:
*
* 1. Allocate a DMA channel
*
* DMACH_HANDLE handle;
* handle = edma_dmach_alloc(dmamux, dchpri);
*
* Where 'dmamux' is the channel DMAMUX configuration register setting and
* 'dchpri' is the channel DCHPRIO priority register setting.
*
* 2. Create the transfer configuration:
*
* struct s32k3xx_edma_xfrconfig_s config;
* config.saddr = ..;
* config.daddr = ..;
* etc.
*
* 3. Setup the transfer in hardware:
*
* int ret;
* ret = s32k3xx_dmach_xfrsetup(handle, &config);
*
* 4. If you are setting up a scatter gather DMA
* (with CONFIG_S32K3XX_EDMA_NTCD > 0), then repeat steps 2 and 3 for
* each segment of the transfer.
*
* 5. Start the DMA:
*
* ret = s32k3xx_dmach_start(handle, my_callback_func, priv);
*
* Where my_callback_func() is called when the DMA completes or an error
* occurs. 'priv' represents some internal driver state that will be
* provided with the callback.
*
* 6. If you need to stop the DMA and free resources (such as if a timeout
* occurs), then:
*
* i mxrt_dmach_stop(handle);
*
* 7. The callback will be received when the DMA completes (or an error
* occurs). After that, you may free the DMA channel, or re-use it on
* subsequent DMAs.
*
* s32k3xx_dmach_free(handle);
*
* Almost non-invasive debug instrumentation is available. You may call
* s32k3xx_dmasample() to save the current state of the eDMA registers at
* any given point in time. At some later, postmortem analysis, you can
* dump the content of the buffered registers with s32k3xx_dmadump().
* s32k3xx_dmasample() is also available for monitoring DMA progress.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration flags.
*
* REVISIT: Many missing options that should be represented as flags:
* 1. Bandwidth
* 2. Source/Destination modulo
*/
#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */
#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT)
# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */
# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */
# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */
#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */
#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT)
# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */
# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */
# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */
#define EDMA_CONFIG_INTHALF (1 << 3) /* Bits 3: Int on HALF */
/****************************************************************************
* Public Types
****************************************************************************/
typedef void *DMACH_HANDLE;
typedef void (*edma_callback_t)(DMACH_HANDLE handle,
void *arg, bool done, int result);
/* eDMA transfer type */
enum s32k3xx_edma_xfrtype_e
{
EDMA_MEM2MEM = 0, /* Transfer from memory to memory */
EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */
EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */
};
/* eDMA transfer sises */
enum s32k3xx_edma_sizes_e
{
EDMA_8BIT = 0, /* Transfer data size 8 */
EDMA_16BIT = 1, /* Transfer data size 16 */
EDMA_32BIT = 2, /* Transfer data size 32 */
EDMA_64BIT = 3, /* Transfer data size 64 */
EDMA_16BYTE = 4, /* Transfer data size 16-byte */
EDMA_32BYTE = 5, /* Transfer data size 32-byte */
EDMA_64BYTE = 6, /* Transfer data size 64-byte */
};
/* This structure holds the source/destination transfer attribute
* configuration.
*/
struct s32k3xx_edma_xfrconfig_s
{
uint32_t saddr; /* Source data address. */
uint32_t daddr; /* Destination data address. */
int16_t soff; /* Sign-extended offset for current source address. */
int16_t doff; /* Sign-extended offset for current destination address. */
uint16_t iter; /* Major loop iteration count. */
uint8_t flags; /* See EDMA_CONFIG_* definitions */
uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */
uint8_t dsize; /* Destination data transfer size. */
uint8_t ttype; /* Transfer type (see enum s32k3xx_edma_xfrtype_e). */
#ifdef CONFIG_S32K3XX_EDMA_EMLIM
uint16_t nbytes; /* Bytes to transfer in a minor loop */
#else
uint32_t nbytes; /* Bytes to transfer in a minor loop */
#endif
#ifdef CONFIG_S32K3XX_EDMA_MOD
uint8_t smod;
uint8_t dmod;
#endif
#ifdef CONFIG_S32K3XX_EDMA_BWC
uint8_t bwc;
#endif
#ifdef CONFIG_S32K3XX_EDMA_ELINK
DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */
#endif
};
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA
* is selected
*/
#ifdef CONFIG_DEBUG_DMA
struct s32k3xx_dmaregs_s
{
uint8_t chan; /* Sampled channel */
/* eDMA Global Registers */
uint32_t cr; /* Control */
uint32_t es; /* Error Status */
uint32_t req; /* Interrupt Request */
uint32_t hrs; /* Hardware Request Status */
/* eDMA Channel registers */
uint8_t dchpri; /* Channel priority */
/* eDMA TCD */
uint32_t saddr; /* TCD Source Address */
uint16_t soff; /* TCD Signed Source Address Offset */
uint16_t attr; /* TCD Transfer Attributes */
uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* TCD Last Source Address Adjustment */
uint32_t daddr; /* TCD Destination Address */
uint16_t doff; /* TCD Signed Destination Address Offset */
uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* TCD Control and Status */
uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */
/* DMAMUX registers */
uint32_t dmamux; /* Channel configuration */
};
#endif /* CONFIG_DEBUG_DMA */
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_dmach_alloc
*
* Allocate a DMA channel. This function sets aside a DMA channel,
* initializes the DMAMUX for the channel, then gives the caller exclusive
* access to the DMA channel.
*
* Input Parameters:
* dmamux - DMAMUX configuration see DMAMUX channel configuration register
* bit-field definitions in hardware/s32k3xx_dmamux.h.
* Settings include:
*
* DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required)
* DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional)
* DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required)
*
* A value of zero will disable the DMAMUX channel.
* dchpri - DCHPRI channel priority configuration. See DCHPRI channel
* configuration register bit-field definitions in
* hardware/s32k3xx_edma.h. Meaningful settings include:
*
* EDMA_DCHPRI_CHPRI Channel Arbitration Priority
* DCHPRI_DPA Disable Preempt Ability
* DCHPRI_ECP Enable Channel Preemption
*
* The power-on default, 0x05, is a reasonable choice.
*
* Returned Value:
* If a DMA channel is available, this function returns a non-NULL, void*
* DMA channel handle. NULL is returned on any failure.
*
****************************************************************************/
DMACH_HANDLE s32k3xx_dmach_alloc(uint16_t dmamux, uint8_t dchpri);
/****************************************************************************
* Name: s32k3xx_dmach_free
*
* Description:
* Release a DMA channel.
* NOTE: The 'handle' used in this argument must NEVER be used again
* until s32k3xx_dmach_alloc() is called again to re-gain a valid handle.
*
* Returned Value:
* None
*
****************************************************************************/
void s32k3xx_dmach_free(DMACH_HANDLE handle);
/****************************************************************************
* Name: s32k3xx_dmach_xfrsetup
*
* Description:
* This function adds the eDMA transfer to the DMA sequence. The request
* is setup according to the content of the transfer configuration
* structure. For "normal" DMA, s32k3xx_dmach_xfrsetup is called only
* once.
* Scatter/gather DMA is accomplished by calling this function repeatedly,
* once for each transfer in the sequence. Scatter/gather DMA processing
* is enabled automatically when the second transfer configuration is
* received.
*
* This function may be called multiple times to handle multiple,
* discontinuous transfers (scatter-gather)
*
* Input Parameters:
* handle - DMA channel handle created by s32k3xx_dmach_alloc()
* config - A DMA transfer configuration instance, populated by the
* The content of 'config' describes the transfer
*
* Returned Value
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
****************************************************************************/
int s32k3xx_dmach_xfrsetup(DMACH_HANDLE *handle,
const struct s32k3xx_edma_xfrconfig_s *config);
/****************************************************************************
* Name: s32k3xx_dmach_start
*
* Description:
* Start the DMA transfer by enabling the channel DMA request.
* This function should be called after the final call to
* s32k3xx_dmasetup() in order to avoid race conditions.
*
* At the conclusion of each major DMA loop, a callback to the
* user-provided function is made: |For "normal" DMAs, this will
* correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple
* interrupts will be generated with the final being the DONE interrupt.
*
* At the conclusion of the DMA, the DMA channel is reset, all TCDs are
* freed, and the callback function is called with the the success/fail
* result of the DMA.
*
* NOTE:
* On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary
* to invalidate the destination memory. That is not done automatically
* by the DMA module. Invalidation of the destination memory regions is
* the responsibility of the caller.
*
* Input Parameters:
* handle - DMA channel handle created by s32k3xx_dmach_alloc()
* callback - The callback to be invoked when the DMA is completes or is
* aborted.
* arg - An argument that accompanies the callback
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
****************************************************************************/
int s32k3xx_dmach_start(DMACH_HANDLE handle,
edma_callback_t callback, void *arg);
/****************************************************************************
* Name: s32k3xx_dmach_stop
*
* Description:
* Cancel the DMA. After s32k3xx_dmach_stop() is called, the DMA channel
* is reset, all TCDs are freed, and s32k3xx_dmarx/txsetup() must be called
* before s32k3xx_dmach_start() can be called again
*
* Input Parameters:
* handle - DMA channel handle created by s32k3xx_dmach_alloc()
*
* Returned Value:
* None.
*
****************************************************************************/
void s32k3xx_dmach_stop(DMACH_HANDLE handle);
/****************************************************************************
* Name: s32k3xx_dmach_getcount
*
* Description:
* This function checks the TCD (Task Control Descriptor) status for a
* specified eDMA channel and returns the the number of major loop counts
* that have not finished.
*
* NOTES:
* 1. This function can only be used to get unfinished major loop count of
* transfer without the next TCD, or it might be inaccuracy.
* 2. The unfinished/remaining transfer bytes cannot be obtained directly
* from registers while the channel is running.
*
* Because to calculate the remaining bytes, the initial NBYTES configured
* in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not
* support getting it while a channel is active. In another words, the
* NBYTES value reading is always the actual (decrementing) NBYTES value
* the dma_engine is working with while a channel is running.
* Consequently, to get the remaining transfer bytes, a software-saved
* initial value of NBYTES (for example copied before enabling the channel)
* is needed. The formula to calculate it is shown below:
*
* RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
*
* Input Parameters:
* handle - DMA channel handle created by s32k3xx_dmach_alloc()
*
* Returned Value:
* Major loop count which has not been transferred yet for the current TCD.
*
****************************************************************************/
unsigned int s32k3xx_dmach_getcount(DMACH_HANDLE *handle);
/****************************************************************************
* Name: s32k3xx_dmasample
*
* Description:
* Sample DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void s32k3xx_dmasample(DMACH_HANDLE handle, struct s32k3xx_dmaregs_s *regs);
#else
# define s32k3xx_dmasample(handle,regs)
#endif
/****************************************************************************
* Name: s32k3xx_dmadump
*
* Description:
* Dump previously sampled DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void s32k3xx_dmadump(const struct s32k3xx_dmaregs_s *regs, const char *msg);
#else
# define s32k3xx_dmadump(handle,regs,msg)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_EDMAC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_emac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_EMAC_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_EMAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/s32k3xx_emac.h"
#ifdef CONFIG_S32K3XX_ENET
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Definitions for use with s32k3xx_phy_boardinitialize */
#define EMAC_INTF 0
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: s32k3xx_netinitialize
*
* Description:
* Initialize the Ethernet controller and driver
*
* Input Parameters:
* intf - In the case where there are multiple EMACs, this value
* identifies which EMAC is to be initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NETDEV_LATEINIT
int s32k3xx_netinitialize(int intf);
#endif
/****************************************************************************
* Function: s32k3xx_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can
* be be used. This may include such things as configuring GPIOs,
* resetting the PHY, etc. If CONFIG_S32K3XX_EMAC_PHYINIT is defined in
* the configuration then the board specific logic must provide
* s32k3xx_phyinitialize(); The i.MX RT Ethernet driver will call this
* function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_ENET_PHYINIT
int s32k3xx_phy_boardinitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_S32K3XX_EMAC */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_EMAC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_flashboot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Public Data
****************************************************************************/
extern const uint32_t CM7_0_START_ADDRESS;
typedef const struct image_vector_table
{
uint32_t HEADER; /* Header of IVT Structure */
uint32_t BOOTCONFIG; /* Boot Configuration Word */
const uint32_t reserved1; /* Reserved */
const uint32_t * CM7_0_STARTADDRESS; /* Start Address of Application on CM7_0 Core */
const uint32_t reserved2; /* Reserved */
const uint32_t * CM7_1_STARTADDRESS; /* Start Address of Application on CM7_1 Core */
const uint64_t reserved3; /* Reserved */
const uint32_t reserved4; /* Reserved */
const uint32_t * LCCONFIG; /* Address of LC configuration Word */
const uint32_t reserved5; /* Reserved */
const uint32_t reserved6; /* Reserved */
uint8_t reserved7[192]; /* Reserved for future use */
uint8_t reserved8[16]; /* Reserved. */
}ivt_t;
const ivt_t boot_header locate_data(".boot_header") =
{
.HEADER = 0x5aa55aa5, /* Header of IVT Structure */
.BOOTCONFIG = 1, /* Boot Configuration Word: CM7_0_ENABLE */
.CM7_0_STARTADDRESS = (const void *)&CM7_0_START_ADDRESS,
.CM7_1_STARTADDRESS = 0, /* Application on CM7_1 Core */
.LCCONFIG = 0, /* Address of LC configuration Word */
};
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_flexcan.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_FLEXCAN_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_FLEXCAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/s32k3xx_flexcan.h"
#ifdef CONFIG_S32K3XX_FLEXCAN
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: s32k3xx_caninitialize
*
* Description:
* Initialize the CAN controller and driver
*
* Input Parameters:
* intf - In the case where there are multiple CAN devices, this value
* identifies which CAN device is to be initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NETDEV_LATEINIT
int s32k3xx_caninitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_S32K3XX_FLEXCAN */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_FLEXCAN_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_fs26.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP
* This FS26 driver is intended for ENGINEERING DEVELOPMENT OR EVALUATION
* PURPOSES ONLY. It is provided as an example to disable the FS26 watchdog
* functionality for development on the S32K3XX platform. Please refer to
* the datasheets and application hints provided on NXP.com to implement
* full functionality.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/semaphore.h>
#include <nuttx/spi/spi.h>
#include <nuttx/power/pm.h>
#include "arm_internal.h"
#include "chip.h"
#include "s32k3xx_pin.h"
#include "hardware/s32k3xx_pinmux.h"
#include "hardware/s32k3xx_lpspi.h"
#include "hardware/s32k3xx_fs26.h"
#include "s32k3xx_fs26.h"
#include "s32k3xx_clockconfig.h"
#include "s32k3xx_lpspi.h"
#include <arch/board/board.h>
#define SWAP_ENDIANESS
#if defined(CONFIG_S32K3XX_FS26)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CRC polynomial used for SPI communication. */
#define FS26_CRC_TBL_SIZE 256U /* Size of CRC table. */
#define FS26_COM_CRC_POLYNOM 0x1DU /* CRC polynom. */
#define FS26_COM_CRC_INIT 0xFFU /* CRC initial value. */
/****************************************************************************
* Private Types
****************************************************************************/
struct fs26_dev_s g_fs26;
/* CRC lookup table. */
static const uint8_t FS26_CRC_TABLE[FS26_CRC_TBL_SIZE] =
{
0x00u, 0x1du, 0x3au, 0x27u, 0x74u, 0x69u, 0x4eu, 0x53u, 0xe8u,
0xf5u, 0xd2u, 0xcfu, 0x9cu, 0x81u, 0xa6u, 0xbbu, 0xcdu, 0xd0u,
0xf7u, 0xeau, 0xb9u, 0xa4u, 0x83u, 0x9eu, 0x25u, 0x38u, 0x1fu,
0x02u, 0x51u, 0x4cu, 0x6bu, 0x76u, 0x87u, 0x9au, 0xbdu, 0xa0u,
0xf3u, 0xeeu, 0xc9u, 0xd4u, 0x6fu, 0x72u, 0x55u, 0x48u, 0x1bu,
0x06u, 0x21u, 0x3cu, 0x4au, 0x57u, 0x70u, 0x6du, 0x3eu, 0x23u,
0x04u, 0x19u, 0xa2u, 0xbfu, 0x98u, 0x85u, 0xd6u, 0xcbu, 0xecu,
0xf1u, 0x13u, 0x0eu, 0x29u, 0x34u, 0x67u, 0x7au, 0x5du, 0x40u,
0xfbu, 0xe6u, 0xc1u, 0xdcu, 0x8fu, 0x92u, 0xb5u, 0xa8u, 0xdeu,
0xc3u, 0xe4u, 0xf9u, 0xaau, 0xb7u, 0x90u, 0x8du, 0x36u, 0x2bu,
0x0cu, 0x11u, 0x42u, 0x5fu, 0x78u, 0x65u, 0x94u, 0x89u, 0xaeu,
0xb3u, 0xe0u, 0xfdu, 0xdau, 0xc7u, 0x7cu, 0x61u, 0x46u, 0x5bu,
0x08u, 0x15u, 0x32u, 0x2fu, 0x59u, 0x44u, 0x63u, 0x7eu, 0x2du,
0x30u, 0x17u, 0x0au, 0xb1u, 0xacu, 0x8bu, 0x96u, 0xc5u, 0xd8u,
0xffu, 0xe2u, 0x26u, 0x3bu, 0x1cu, 0x01u, 0x52u, 0x4fu, 0x68u,
0x75u, 0xceu, 0xd3u, 0xf4u, 0xe9u, 0xbau, 0xa7u, 0x80u, 0x9du,
0xebu, 0xf6u, 0xd1u, 0xccu, 0x9fu, 0x82u, 0xa5u, 0xb8u, 0x03u,
0x1eu, 0x39u, 0x24u, 0x77u, 0x6au, 0x4du, 0x50u, 0xa1u, 0xbcu,
0x9bu, 0x86u, 0xd5u, 0xc8u, 0xefu, 0xf2u, 0x49u, 0x54u, 0x73u,
0x6eu, 0x3du, 0x20u, 0x07u, 0x1au, 0x6cu, 0x71u, 0x56u, 0x4bu,
0x18u, 0x05u, 0x22u, 0x3fu, 0x84u, 0x99u, 0xbeu, 0xa3u, 0xf0u,
0xedu, 0xcau, 0xd7u, 0x35u, 0x28u, 0x0fu, 0x12u, 0x41u, 0x5cu,
0x7bu, 0x66u, 0xddu, 0xc0u, 0xe7u, 0xfau, 0xa9u, 0xb4u, 0x93u,
0x8eu, 0xf8u, 0xe5u, 0xc2u, 0xdfu, 0x8cu, 0x91u, 0xb6u, 0xabu,
0x10u, 0x0du, 0x2au, 0x37u, 0x64u, 0x79u, 0x5eu, 0x43u, 0xb2u,
0xafu, 0x88u, 0x95u, 0xc6u, 0xdbu, 0xfcu, 0xe1u, 0x5au, 0x47u,
0x60u, 0x7du, 0x2eu, 0x33u, 0x14u, 0x09u, 0x7fu, 0x62u, 0x45u,
0x58u, 0x0bu, 0x16u, 0x31u, 0x2cu, 0x97u, 0x8au, 0xadu, 0xb0u,
0xe3u, 0xfeu, 0xd9u, 0xc4u
};
fs26_watchdog_type wd_type = FS26_WD_CHALLENGER;
static uint16_t watchdog_token = 0x5ab2;
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Helpers */
static inline void fs26_configspi(struct spi_dev_s *spi)
{
/* Configure SPI for the ADXL345 */
SPI_SETMODE(spi, SPIDEV_MODE1); /* CPOL=0 CPHA=1 */
SPI_SETBITS(spi, 32);
SPI_SETFREQUENCY(spi, CONFIG_FS26_SPI_FREQUENCY);
}
static inline void fs26_print_general_device_status(uint32_t retval)
{
if (retval & FS26_M_AVAL)
{
spierr("Main State machine availability\n");
}
if (retval & FS26_FS_EN)
{
spierr("Fail Safe State machine status enabled\n");
}
spierr("IRQ:\n");
if (retval & FS26_FS_G)
{
spierr("FS26_FS_G\n");
}
if (retval & FS26_COM_G)
{
spierr("FS26_COM_G\n");
}
if (retval & FS26_WIO_G)
{
spierr("FS26_WIO_G\n");
}
if (retval & FS26_VSUP_G)
{
spierr("FS26_VSUP_G\n");
}
if (retval & FS26_REG_G)
{
spierr("FS26_REG_G\n");
}
if (retval & FS26_TSD_G)
{
spierr("FS26_TSD_G\n");
}
}
static inline void fs26_print_crc(uint8_t crc, uint8_t crc_received)
{
spierr("%02x<->%02x\n", crc, crc_received);
}
/* Computes Challenger Watchdog answer. */
static inline uint16_t fs26_wdcomputeanswer(uint16_t token)
{
uint32_t u32_mr = token; /* Monitoring result. */
/* Simulates ALU Checker on the MCU side. */
u32_mr *= 4U;
u32_mr += 6U;
u32_mr -= 4U;
u32_mr = ~u32_mr;
u32_mr /= 4U;
return (uint16_t)u32_mr;
}
static uint8_t fs26_calcrc(const uint8_t * data, uint8_t datalen)
{
uint8_t crc; /* Result. */
uint8_t tableidx; /* Index to the CRC table. */
uint8_t dataidx; /* Index to the data array (memory). */
DEBUGASSERT(data != NULL);
DEBUGASSERT(datalen > 0);
/* Set CRC token value. */
crc = FS26_COM_CRC_INIT;
for (dataidx = datalen; dataidx > 0; dataidx--)
{
tableidx = crc ^ data[dataidx];
crc = FS26_CRC_TABLE[tableidx];
}
return crc;
}
uint32_t fs26_setreg(struct fs26_dev_s *priv, uint8_t regaddr,
uint16_t regval)
{
uint32_t retval;
uint32_t spidata;
/* Send register address and set the value */
spidata = FS26_REG_ADDR(regaddr) | FS26_SET_DATA(regval) | FS26_RW;
spidata |= (uint32_t)fs26_calcrc((uint8_t *)&spidata, 3);
#ifdef SWAP_ENDIANESS
spidata = __builtin_bswap32(spidata);
#endif
/* If SPI bus is shared then lock and configure it */
SPI_LOCK(priv->spi, true);
fs26_configspi(priv->spi);
/* Select the FS26 */
SPI_SELECT(priv->spi, SPIDEV_NONE(0), true);
SPI_EXCHANGE(priv->spi, &spidata, &retval, 1);
#ifdef SWAP_ENDIANESS
retval = __builtin_bswap32(retval);
#endif
spiinfo("Received %08lx\n", retval);
if (fs26_calcrc((uint8_t *)&retval, 3) != ((uint8_t *)&retval)[0])
{
spierr("CRC error expected %02x got %02x\n",
fs26_calcrc((uint8_t *)&retval, 3),
((uint8_t *)&retval)[0]);
retval = 0x0;
}
/* Deselect the FS26 */
SPI_SELECT(priv->spi, SPIDEV_NONE(0), false);
/* Unlock bus */
SPI_LOCK(priv->spi, false);
return retval;
}
uint32_t fs26_getreg(struct fs26_dev_s *priv, uint8_t regaddr)
{
uint32_t retval;
uint32_t spidata;
/* Send register address and calc CRC */
spidata = FS26_REG_ADDR(regaddr);
spidata |= (uint32_t)fs26_calcrc((uint8_t *)&spidata, 3);
#ifdef SWAP_ENDIANESS
spidata = __builtin_bswap32(spidata);
#endif
/* If SPI bus is shared then lock and configure it */
SPI_LOCK(priv->spi, true);
fs26_configspi(priv->spi);
/* Select the FS26 */
SPI_SELECT(priv->spi, SPIDEV_NONE(0), true);
/* Send register to read and get the 32 bits */
SPI_EXCHANGE(priv->spi, &spidata, &retval, 1);
#ifdef SWAP_ENDIANESS
retval = __builtin_bswap32(retval);
#endif
if (fs26_calcrc((uint8_t *)&retval, 3) != ((uint8_t *)&retval)[0])
{
spierr("CRC error expected %02x got %02x\n",
fs26_calcrc((uint8_t *)&retval, 3),
((uint8_t *)&retval)[0]);
retval = 0x0;
}
/* Deselect the FS26 */
SPI_SELECT(priv->spi, SPIDEV_NONE(0), false);
/* Unlock bus */
SPI_LOCK(priv->spi, false);
/* DEBUG print */
spiinfo("%02x->%04lx\n", regaddr, retval);
return retval;
}
static uint32_t fs26_wdreadchallengetoken(uint16_t * token_ptr)
{
uint32_t retval;
retval = fs26_getreg(&g_fs26, FS26_FS_WD_TOKEN);
if (retval != 0)
{
*token_ptr = FS26_GET_DATA(retval);
retval = OK;
}
return retval;
}
int32_t fs26_wdrefresh(void)
{
int32_t retval = OK;
uint16_t u16_answer; /* Calculated monitoring result. */
irqstate_t flags;
if (FS26_WD_DISABLED == wd_type)
{
/* No need to refresh watchdog. */
retval = OK;
}
else if(FS26_WD_SIMPLE == wd_type)
{
if (fs26_setreg(&g_fs26, FS26_FS_WD_ANSWER, watchdog_token) != 0)
{
retval = OK;
}
else
{
retval = -1;
}
}
else if(FS26_WD_CHALLENGER == wd_type)
{
flags = enter_critical_section();
if (fs26_wdreadchallengetoken(&watchdog_token) == OK)
{
u16_answer = fs26_wdcomputeanswer(watchdog_token);
if (fs26_setreg(&g_fs26, FS26_FS_WD_ANSWER, u16_answer) != 0)
{
retval = OK;
}
else
{
retval = -1;
}
}
else
{
retval = -1;
}
leave_critical_section(flags);
}
/* Check if watchdog refresh was successful. */
if (((FS26_WD_SIMPLE == wd_type)
|| (FS26_WD_CHALLENGER == wd_type))
&& (OK == retval))
{
if ((FS26_GET_DATA(
fs26_getreg(&g_fs26, FS26_FS_GRL_FLAGS))
& FS_WD_G_MASK) == FS_WD_G)
{
retval = -1;
}
else
{
retval = OK;
}
}
return retval;
}
/****************************************************************************
* Public Functions
****************************************************************************/
void fs26_initialize(struct spi_dev_s *spi)
{
uint32_t retval;
uint16_t regval;
/* Assign spi controller */
g_fs26.spi = spi;
/* Check FS diag */
retval = fs26_getreg(&g_fs26, FS26_FS_DIAG_SAFETY1);
if ((FS26_GET_DATA(retval) & (ABIST1_PASS_MASK | LBIST_STATUS_MASK))
!= (ABIST1_PASS | LBIST_STATUS_OK))
{
spierr("FS26 DIAG failed %08lx\n", retval);
}
/* Get state machine state */
retval = fs26_getreg(&g_fs26, FS26_FS_STATES);
if ((FS26_GET_DATA(retval) & DBG_MODE_MASK) == DBG_MODE)
{
spierr("FS26 in DEBUG mode\n");
}
/* INIT_FS */
if ((FS26_GET_DATA(retval) & FS_STATES_MASK) == FS_STATES_INIT_FS)
{
/* Set all FS26_FS_I_XXX registers
* Note write data to both normal and not registers
*/
regval = VMON_PRE_OV_FS_REACTION_NO_EFFECT |
VMON_PRE_UV_FS_REACTION_NO_EFFECT |
VMON_CORE_OV_FS_REACTION_NO_EFFECT |
VMON_CORE_UV_FS_REACTION_NO_EFFECT |
VMON_LDO1_OV_FS_REACTION_NO_EFFECT |
VMON_LDO1_UV_FS_REACTION_NO_EFFECT |
VMON_LDO2_OV_FS_REACTION_NO_EFFECT |
VMON_LDO2_UV_FS_REACTION_NO_EFFECT;
fs26_setreg(&g_fs26, FS26_FS_I_OVUV_SAFE_REACTION1, regval);
fs26_setreg(&g_fs26, FS26_FS_I_NOT_OVUV_SAFE_REACTION1, ~regval);
regval = VMON_EXT_OV_FS_REACTION_NO_EFFECT |
VMON_EXT_UV_FS_REACTION_NO_EFFECT |
VMON_REF_OV_FS_REACTION_NO_EFFECT |
VMON_REF_UV_FS_REACTION_NO_EFFECT |
VMON_TRK2_OV_FS_REACTION_NO_EFFECT |
VMON_TRK2_UV_FS_REACTION_NO_EFFECT |
VMON_TRK1_OV_FS_REACTION_NO_EFFECT |
VMON_TRK1_UV_FS_REACTION_NO_EFFECT;
fs26_setreg(&g_fs26, FS26_FS_I_OVUV_SAFE_REACTION2, regval);
fs26_setreg(&g_fs26, FS26_FS_I_NOT_OVUV_SAFE_REACTION2, ~regval);
regval = WD_ERR_LIMIT_8 | WD_RFR_LIMIT_6 | WD_FS_REACTION_NO_ACTION;
fs26_setreg(&g_fs26, FS26_FS_I_WD_CFG, regval);
fs26_setreg(&g_fs26, FS26_FS_I_NOT_WD_CFG, ~regval);
regval = FCCU_CFG_NO_MONITORING | ERRMON_ACK_TIME_32MS;
fs26_setreg(&g_fs26, FS26_FS_I_SAFE_INPUTS, regval);
fs26_setreg(&g_fs26, FS26_FS_I_NOT_SAFE_INPUTS, ~regval);
regval = FLT_ERR_REACTION_NO_EFFECT | CLK_MON_DIS | DIS8S;
fs26_setreg(&g_fs26, FS26_FS_I_FSSM, regval);
fs26_setreg(&g_fs26, FS26_FS_I_NOT_FSSM, ~regval);
/* Disable watchdog */
regval = WDW_PERIOD_DISABLE | WDW_DC_62_37 | WDW_RECOVERY_DISABLE;
fs26_setreg(&g_fs26, FS26_FS_WDW_DURATION, regval);
fs26_setreg(&g_fs26, FS26_FS_NOT_WDW_DURATION, ~regval);
fs26_wdrefresh();
spierr("FS26 in INIT_FS mode\n");
}
else if ((FS26_GET_DATA(retval) & FS_STATES_MASK) == FS_STATES_DEBUG_ENTRY)
{
spierr("FS26 in DEBUG_ENTRY mode\n");
}
else if ((FS26_GET_DATA(retval) & FS_STATES_MASK) == FS_STATES_NORMAL)
{
spierr("FS26 in NORMAL mode\n");
}
else if ((FS26_GET_DATA(retval) & FS_STATES_MASK)
== FS_STATES_SAFETY_OUT_NOT)
{
spierr("FS26 in Safety Outputs not released\n");
}
}
#endif /* CONFIG_S32K3XX_FS26 */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_fs26.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP
* This FS26 driver is intended for ENGINEERING DEVELOPMENT OR EVALUATION
* PURPOSES ONLY. It is provided as an example to disable the FS26 watchdog
* functionality for development on the S32K3XX platform. Please refer to
* the datasheets and application hints provided on NXP.com to implement
* full functionality.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/semaphore.h>
#include <nuttx/spi/spi.h>
#include <nuttx/power/pm.h>
#include "arm_internal.h"
#include "chip.h"
#include "s32k3xx_pin.h"
#include "hardware/s32k3xx_pinmux.h"
#include "hardware/s32k3xx_lpspi.h"
#include "s32k3xx_clockconfig.h"
#include "s32k3xx_lpspi.h"
#include <arch/board/board.h>
#if defined(CONFIG_S32K3XX_FS26)
/****************************************************************************
* Data Types
****************************************************************************/
struct fs26_dev_s
{
struct spi_dev_s *spi; /* Saved SPI driver instance */
uint8_t device_status; /* Latest General device status */
};
typedef enum
{
FS26_WD_DISABLED = 0U, /* Watchdog refresh disabled */
FS26_WD_SIMPLE = 1U, /* Simple watchdog refresh */
FS26_WD_CHALLENGER = 2U /* Challenger watchdog refresh */
} fs26_watchdog_type;
void fs26_initialize(struct spi_dev_s *spi);
#endif /* CONFIG_S32K3XX_FS26 */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Sleep until an interrupt occurs to save power */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
#include <arch/chip/s32k3x4_irq.h>
#include "chip.h"
#include "nvic.h"
#include "ram_vectors.h"
#include "arm_internal.h"
#include "s32k3xx_irq.h"
#include "s32k3xx_pin.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void s32k3xx_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE),
getreg32(NVIC_IRQ96_127_ENABLE));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ128_159_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY),
getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY),
getreg32(NVIC_IRQ76_79_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY),
getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY),
getreg32(NVIC_IRQ92_95_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY),
getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY),
getreg32(NVIC_IRQ108_111_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY),
getreg32(NVIC_IRQ116_119_PRIORITY),
getreg32(NVIC_IRQ120_123_PRIORITY),
getreg32(NVIC_IRQ124_127_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ128_131_PRIORITY),
getreg32(NVIC_IRQ132_135_PRIORITY),
getreg32(NVIC_IRQ136_139_PRIORITY),
getreg32(NVIC_IRQ140_143_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ144_147_PRIORITY),
getreg32(NVIC_IRQ148_151_PRIORITY),
getreg32(NVIC_IRQ152_155_PRIORITY),
getreg32(NVIC_IRQ156_159_PRIORITY));
leave_critical_section(flags);
}
#else
# define s32k3xx_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: s32k3xx_nmi, s32k3xx_busfault, s32k3xx_usagefault, s32k3xx_pendsv,
* s32k3xx_dbgmonitor, s32k3xx_pendsv, s32k3xx_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int s32k3xx_nmi(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int s32k3xx_busfault(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
}
static int s32k3xx_usagefault(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
}
static int s32k3xx_pendsv(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int s32k3xx_dbgmonitor(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int s32k3xx_reserved(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: s32k3xx_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_USEBASEPRI
static inline void s32k3xx_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: s32k3xx_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int s32k3xx_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= S32K3XX_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= S32K3XX_IRQ_EXTINT)
{
n = irq - S32K3XX_IRQ_EXTINT;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == S32K3XX_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == S32K3XX_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == S32K3XX_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == S32K3XX_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
*
* Description:
* Complete initialization of the interrupt system and enable normal,
* interrupt processing.
*
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
uint32_t regval;
#endif
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < S32K3XX_IRQ_NEXTINT; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
arm_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(S32K3XX_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(S32K3XX_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(S32K3XX_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
s32k3xx_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
#ifdef CONFIG_ARM_MPU
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
irq_attach(S32K3XX_IRQ_MEMFAULT, arm_memfault, NULL);
up_enable_irq(S32K3XX_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(S32K3XX_IRQ_NMI, s32k3xx_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(S32K3XX_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(S32K3XX_IRQ_BUSFAULT, s32k3xx_busfault, NULL);
irq_attach(S32K3XX_IRQ_USAGEFAULT, s32k3xx_usagefault, NULL);
irq_attach(S32K3XX_IRQ_PENDSV, s32k3xx_pendsv, NULL);
irq_attach(S32K3XX_IRQ_DBGMONITOR, s32k3xx_dbgmonitor, NULL);
irq_attach(S32K3XX_IRQ_RESERVED, s32k3xx_reserved, NULL);
#endif
s32k3xx_dumpnvic("initial", S32K3XX_IRQ_NIRQS);
#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
/* If a debugger is connected, try to prevent it from catching hardfaults.
* If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
* operation.
*/
regval = getreg32(NVIC_DEMCR);
regval &= ~NVIC_DEMCR_VCHARDERR;
putreg32(regval, NVIC_DEMCR);
#endif
#ifdef CONFIG_S32K3XX_GPIOIRQ
/* Initialize GPIO PIN interrupts */
s32k3xx_pinirq_initialize();
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (s32k3xx_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= S32K3XX_IRQ_EXTINT)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
s32k3xx_dumpnvic("disable", irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (s32k3xx_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= S32K3XX_IRQ_EXTINT)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
s32k3xx_dumpnvic("enable", irq);
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
s32k3xx_clrpend(irq);
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= S32K3XX_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < S32K3XX_IRQ_EXTINT)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= S32K3XX_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
s32k3xx_dumpnvic("prioritize", irq);
return OK;
}
#endif

47
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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_IRQ_H
#define __ARCH_ARM_SRC_S32K3XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC. This does not seem to be
* required for most interrupts.
*
****************************************************************************/
void s32k3xx_clrpend(int irq);
#endif /* __ARCH_ARM_SRC_S32K3XX_IRQ_H */

718
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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <fixedmath.h>
#include <assert.h>
#include <errno.h>
#include "hardware/s32k3xx_pinmux.h"
#include "hardware/s32k3xx_lpuart.h"
#include "s32k3xx_config.h"
#include "s32k3xx_pin.h"
#include "s32k3xx_lowputc.h"
#include "s32k3xx_clockconfig.h"
#include "s32k3xx_periphclocks.h"
#include "arm_internal.h"
#include <arch/board/board.h> /* Include last: has dependencies */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifdef HAVE_LPUART_CONSOLE
# if defined(CONFIG_LPUART0_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART0_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART0_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART0_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART0_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART0_2STOP
# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART1_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART1_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART2_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART2_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART2_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART2_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART2_2STOP
# elif defined(CONFIG_LPUART3_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART3_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART3_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART3_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART3_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART3_2STOP
# elif defined(CONFIG_LPUART4_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART4_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART4_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART4_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART4_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART4_2STOP
# elif defined(CONFIG_LPUART5_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART5_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART5_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART5_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART5_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART5_2STOP
# elif defined(CONFIG_LPUART6_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART6_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART6_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART6_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART6_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART6_2STOP
# elif defined(CONFIG_LPUART7_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART7_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART7_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART7_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART7_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART7_2STOP
# elif defined(CONFIG_LPUART8_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART8_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART8_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART8_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART8_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART8_2STOP
# elif defined(CONFIG_LPUART9_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART9_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART9_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART9_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART9_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART9_2STOP
# elif defined(CONFIG_LPUART10_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART10_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART10_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART10_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART10_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART10_2STOP
# elif defined(CONFIG_LPUART11_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART11_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART11_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART11_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART11_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART11_2STOP
# elif defined(CONFIG_LPUART12_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART12_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART12_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART12_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART12_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART12_2STOP
# elif defined(CONFIG_LPUART13_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART13_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART13_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART13_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART13_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART13_2STOP
# elif defined(CONFIG_LPUART14_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART14_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART14_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART14_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART14_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART14_2STOP
# elif defined(CONFIG_LPUART15_SERIAL_CONSOLE)
# define S32K3XX_CONSOLE_BASE S32K3XX_LPUART15_BASE
# define S32K3XX_CONSOLE_BAUD CONFIG_LPUART15_BAUD
# define S32K3XX_CONSOLE_BITS CONFIG_LPUART15_BITS
# define S32K3XX_CONSOLE_PARITY CONFIG_LPUART15_PARITY
# define S32K3XX_CONSOLE_2STOP CONFIG_LPUART15_2STOP
# endif
#endif
/* Clocking *****************************************************************/
/* Functional clocking is provided via the PCC. The PCC clocking must
* be configured by board-specific logic prior to using the LPUART.
*/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_LPUART_CONSOLE
static const struct uart_config_s g_console_config =
{
.baud = S32K3XX_CONSOLE_BAUD, /* Configured baud */
.parity = S32K3XX_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */
.bits = S32K3XX_CONSOLE_BITS, /* Number of bits (5-9) */
.stopbits2 = S32K3XX_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */
};
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void s32k3xx_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
#ifdef HAVE_LPUART_DEVICE
#ifdef CONFIG_S32K3XX_LPUART0
/* Configure LPUART0 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART0_RX);
s32k3xx_pinconfig(PIN_LPUART0_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART0_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART0_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART1
/* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART1_RX);
s32k3xx_pinconfig(PIN_LPUART1_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART1_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART1_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART2
/* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART2_RX);
s32k3xx_pinconfig(PIN_LPUART2_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART2_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART2_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART3
/* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART3_RX);
s32k3xx_pinconfig(PIN_LPUART3_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART3_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART3_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART4
/* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART4_RX);
s32k3xx_pinconfig(PIN_LPUART4_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART4_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART4_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART5
/* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART5_RX);
s32k3xx_pinconfig(PIN_LPUART5_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART5_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART5_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART6
/* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART6_RX);
s32k3xx_pinconfig(PIN_LPUART6_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART6_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART6_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART7
/* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART7_RX);
s32k3xx_pinconfig(PIN_LPUART7_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART7_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART7_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART8
/* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART8_RX);
s32k3xx_pinconfig(PIN_LPUART8_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART8_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART8_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART9
/* Configure LPUART9 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART9_RX);
s32k3xx_pinconfig(PIN_LPUART9_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART9_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART9_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART10
/* Configure LPUART10 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART10_RX);
s32k3xx_pinconfig(PIN_LPUART10_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART10_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART10_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART11
/* Configure LPUART11 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART11_RX);
s32k3xx_pinconfig(PIN_LPUART11_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART11_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART11_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART12
/* Configure LPUART12 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART12_RX);
s32k3xx_pinconfig(PIN_LPUART12_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART12_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART12_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART13
/* Configure LPUART13 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART13_RX);
s32k3xx_pinconfig(PIN_LPUART13_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART13_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART13_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART14
/* Configure LPUART14 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART14_RX);
s32k3xx_pinconfig(PIN_LPUART14_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART14_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART14_RTS);
#endif
#endif
#ifdef CONFIG_S32K3XX_LPUART15
/* Configure LPUART15 pins: RXD and TXD.
* Also configure RTS and CTS if flow control is enabled.
*/
s32k3xx_pinconfig(PIN_LPUART15_RX);
s32k3xx_pinconfig(PIN_LPUART15_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
s32k3xx_pinconfig(PIN_LPUART15_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL)))
s32k3xx_pinconfig(PIN_LPUART15_RTS);
#endif
#endif
#ifdef HAVE_LPUART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
s32k3xx_lpuart_configure(S32K3XX_CONSOLE_BASE, &g_console_config);
#endif
#endif /* HAVE_LPUART_DEVICE */
#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */
}
/****************************************************************************
* Name: s32k3xx_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
int s32k3xx_lpuart_configure(uint32_t base,
const struct uart_config_s *config)
{
uint32_t lpuart_freq;
uint16_t sbr;
uint16_t temp_sbr;
uint32_t osr;
uint32_t temp_osr;
uint32_t temp_diff;
uint32_t calculated_baud;
uint32_t baud_diff;
uint32_t regval;
/* Functional clocking is provided via the PCC. The PCC clocking must
* be configured by board-specific logic prior to using the LPUART.
*/
/* Get the PCC source clock */
#ifdef CONFIG_S32K3XX_LPUART0
if (base == S32K3XX_LPUART0_BASE)
{
lpuart_freq = s32k3xx_get_freq(AIPS_PLAT_CLK);
}
else
#endif
#ifdef CONFIG_S32K3XX_LPUART8
if (base == S32K3XX_LPUART8_BASE)
{
lpuart_freq = s32k3xx_get_freq(AIPS_PLAT_CLK);
}
else
#endif
{
lpuart_freq = s32k3xx_get_freq(AIPS_SLOW_CLK);
}
DEBUGASSERT(lpuart_freq >= 0);
/* This LPUART instantiation uses a slightly different baud rate
* calculation. The idea is to use the best OSR (over-sampling rate)
* possible.
*
* NOTE: OSR is typically hard-set to 16 in other LPUART instantiations
* loop to find the best OSR value possible, one that generates minimum
* baud_diff iterate through the rest of the supported values of OSR
*/
baud_diff = config->baud;
osr = 0;
sbr = 0;
for (temp_osr = 4; temp_osr <= 32; temp_osr++)
{
/* Calculate the temporary sbr value */
temp_sbr = (lpuart_freq / (config->baud * temp_osr));
/* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the
* desired baud rate.
*/
if (temp_sbr == 0)
{
temp_sbr = 1;
}
/* Calculate the baud rate based on the temporary OSR and SBR values */
calculated_baud = (lpuart_freq / (temp_osr * temp_sbr));
temp_diff = calculated_baud - config->baud;
/* Select the better value between srb and (sbr + 1) */
if (temp_diff >
(config->baud - (lpuart_freq / (temp_osr * (temp_sbr + 1)))))
{
temp_diff = config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)));
temp_sbr++;
}
if (temp_diff <= baud_diff)
{
baud_diff = temp_diff;
osr = temp_osr;
sbr = temp_sbr;
}
}
if (baud_diff > ((config->baud / 100) * 3))
{
/* Unacceptable baud rate difference of more than 3% */
return ERROR;
}
/* Reset all internal logic and registers, except the Global Register */
regval = getreg32(base + S32K3XX_LPUART_GLOBAL_OFFSET);
regval |= LPUART_GLOBAL_RST;
putreg32(regval, base + S32K3XX_LPUART_GLOBAL_OFFSET);
regval &= ~LPUART_GLOBAL_RST;
putreg32(regval, base + S32K3XX_LPUART_GLOBAL_OFFSET);
/* Construct MODIR register */
regval = 0;
if (config->userts)
{
regval |= LPUART_MODIR_RXRTSE;
}
else if (config->users485)
{
/* Both TX and RX side can't control RTS, so this gives
* the RX side precedence. This should have been filtered
* in layers above anyway, but it's just a precaution.
*/
regval |= LPUART_MODIR_TXRTSE;
}
if (config->usects)
{
regval |= LPUART_MODIR_TXCTSE;
}
if (config->invrts)
{
regval |= LPUART_MODIR_TXRTSPOL;
}
putreg32(regval, base + S32K3XX_LPUART_MODIR_OFFSET);
regval = 0;
if ((osr > 3) && (osr < 8))
{
regval |= LPUART_BAUD_BOTHEDGE;
}
if (config->stopbits2)
{
regval |= LPUART_BAUD_SBNS;
}
regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr);
putreg32(regval, base + S32K3XX_LPUART_BAUD_OFFSET);
regval = 0;
if (config->parity == 1)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD;
}
else if (config->parity == 2)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN;
}
if (config->bits == 8)
{
regval &= ~LPUART_CTRL_M;
}
else if (config->bits == 9)
{
regval |= LPUART_CTRL_M;
}
else
{
/* REVISIT: Here should be added support of other bit modes. */
return -ENOSYS;
}
regval |= LPUART_CTRL_RE | LPUART_CTRL_TE;
putreg32(regval, base + S32K3XX_LPUART_CTRL_OFFSET);
return OK;
}
#endif /* HAVE_LPUART_DEVICE */
/****************************************************************************
* Name: s32k3xx_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from U-
* Boot (and the same UART is used for the console, of course.)
*
****************************************************************************/
#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
void s32k3xx_lowputc(int ch)
{
while ((getreg32(S32K3XX_CONSOLE_BASE + S32K3XX_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
/* If the character to output is a newline,
* then pre-pend a carriage return
*/
if (ch == '\n')
{
/* Send the carriage return by writing it into the UART_TXD register. */
putreg32((uint32_t)'\r',
S32K3XX_CONSOLE_BASE + S32K3XX_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(S32K3XX_CONSOLE_BASE + S32K3XX_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
}
/* Send the character by writing it into the UART_TXD register. */
putreg32((uint32_t)ch, S32K3XX_CONSOLE_BASE + S32K3XX_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(S32K3XX_CONSOLE_BASE + S32K3XX_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
}
#endif

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_LOWPUTC_H
#define __ARCH_ARM_SRC_S32K3XX_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "s32k3xx_config.h"
/****************************************************************************
* Public Types
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
/* This structure describes the configuration of an UART */
struct uart_config_s
{
uint32_t baud; /* Configured baud */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (5-9) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
bool userts; /* True: Assert RTS when there are data to be sent */
bool invrts; /* True: Invert sense of RTS pin (true=active high) */
bool usects; /* True: Condition transmission on CTS asserted */
bool users485; /* True: Assert RTS while transmission progresses */
};
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void s32k3xx_lowsetup(void);
/****************************************************************************
* Name: s32k3xx_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
int s32k3xx_lpuart_configure(uint32_t base,
const struct uart_config_s *config);
#endif
/****************************************************************************
* Name: s32k3xx_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from U-
* Boot (and the same UART is used for the console, of course.)
*
****************************************************************************/
#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
void s32k3xx_lowputc(int ch);
#else
# define s32k3xx_lowputc(ch)
#endif
#endif /* __ARCH_ARM_SRC_S32K3XX_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_lpi2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_LPI2C_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_LPI2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/i2c/i2c_master.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port and return a unique instance of struct
* i2c_master_s. This function may be called to obtain multiple instances
* of the interface.
*
* Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
struct i2c_master_s *s32k3xx_i2cbus_initialize(int port);
/****************************************************************************
* Name: s32k3xx_i2cbus_uninitialize
*
* Description:
* Uninitialize the selected I2C port and power down the device.
*
* Input Parameters:
* Device structure as returned by the s32k3xx_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR on internal reference count mismatch or dev points
* to invalid hardware device.
*
****************************************************************************/
int s32k3xx_i2cbus_uninitialize(struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_LPI2C_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_lpspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_LPSPI_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_LPSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/spi/spi.h>
#include "chip.h"
#include "hardware/s32k3xx_lpspi.h"
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
struct spi_dev_s; /* Forward reference */
/****************************************************************************
* Name: s32k3xx_lpspibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameters:
* bus number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct spi_dev_s *s32k3xx_lpspibus_initialize(int bus);
/****************************************************************************
* Name: s32k3xx_lpspi0/1/2/select and s32k3xx_lpspi0/1/2/status
*
* Description:
* The external functions, s32k3xx_lpspi001/2/select,
* s32k3xx_lpspi0/1/2/status, and s32k3xx_lpspi0/1/2/cmddata must be
* provided by board-specific logic. These are implementations of the
* select, status, and cmddata methods of the SPI interface defined by
* struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
* (including s32k3xx_lpspibus_initialize()) are provided by common
* S32K3XX logic. To use this common SPI logic on your board:
*
* 1. Provide logic in s32k3xx_boardinitialize() to configure SPI chip
* select pins.
* 2. Provide s32k3xx_lpspi0/1/2/select() and s32k3xx_lpspi0/1/2/status()
* functions in your board-specific logic. These functions will
* perform chip selection and status operations using GPIOs in the way
* your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
* then provide s32k3xx_lpspi0/1/2/cmddata() functions in your
* board-specific logic. These functions will perform cmd/data selection
* operations using GPIOs in the way your board is configured.
* 4. Add a calls to s32k3xx_lpspibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by s32k3xx_lpspibus_initialize() may then be
* used to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_LPSPI0
void s32k3xx_lpspi0select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t s32k3xx_lpspi0status(struct spi_dev_s *dev, uint32_t devid);
int s32k3xx_lpspi0cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_S32K3XX_LPSPI1
void s32k3xx_lpspi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t s32k3xx_lpspi1status(struct spi_dev_s *dev, uint32_t devid);
int s32k3xx_lpspi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_S32K3XX_LPSPI2
void s32k3xx_lpspi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t s32k3xx_lpspi2status(struct spi_dev_s *dev, uint32_t devid);
int s32k3xx_lpspi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_S32K3XX_LPSPI3
void s32k3xx_lpspi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t s32k3xx_lpspi3status(struct spi_dev_s *dev, uint32_t devid);
int s32k3xx_lpspi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_S32K3XX_LPSPI4
void s32k3xx_lpspi4select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t s32k3xx_lpspi4status(struct spi_dev_s *dev, uint32_t devid);
int s32k3xx_lpspi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_S32K3XX_LPSPI5
void s32k3xx_lpspi5select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t s32k3xx_lpspi5status(struct spi_dev_s *dev, uint32_t devid);
int s32k3xx_lpspi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/****************************************************************************
* Name: s32k3xx_lpspi0/1/2/register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s)
* must be implemented. These functions implements the registercallback
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_S32K3XX_LPSPI0
int s32k3xx_lpspi0register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_S32K3XX_LPSPI1
int s32k3xx_lpspi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_S32K3XX_LPSPI2
int s32k3xx_lpspi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_LPSPI_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_periphclocks.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <assert.h>
#include <debug.h>
#include "arm_internal.h"
#include "s32k3xx_clockconfig.h"
#include "s32k3xx_periphclocks.h"
#include "hardware/s32k3xx_mc_me.h"
/****************************************************************************
* Private Functions
****************************************************************************/
static inline uint32_t s32k3xx_get_cofb_clken(enum clock_names_e clkname)
{
if (clkname < 64)
{
return (uint32_t)(S32K3XX_MC_ME_PRTN0_COFB1_CLKEN);
}
else if(clkname < 160)
{
return (uint32_t)(S32K3XX_MC_ME_PRTN1_COFB0_CLKEN);
}
else if(clkname < 192)
{
return (uint32_t)(S32K3XX_MC_ME_PRTN1_COFB1_CLKEN);
}
else if(clkname < 224)
{
return (uint32_t)(S32K3XX_MC_ME_PRTN1_COFB2_CLKEN);
}
else if(clkname < 256)
{
return (uint32_t)(S32K3XX_MC_ME_PRTN1_COFB3_CLKEN);
}
else if(clkname < 288)
{
return (uint32_t)(S32K3XX_MC_ME_PRTN2_COFB0_CLKEN);
}
else
{
return (uint32_t)(S32K3XX_MC_ME_PRTN2_COFB1_CLKEN);
}
}
static inline uint32_t s32k3xx_get_cofb_clken_index(
enum clock_names_e clkname)
{
return (clkname - ((clkname / 128) * 128)) % 32;
}
/****************************************************************************
* Name: s32k3xx_set_pclkctrl
*
* Description:
* Sets PCC control register.
*
* Input Parameters:
* pclk - Describes the PCLK configuration.
*
* Returned Value:
* None
*
****************************************************************************/
static void
s32k3xx_cofb_clken(const struct peripheral_clock_config_s *pclk)
{
uint32_t regval;
uint32_t clken_reg = s32k3xx_get_cofb_clken(pclk->clkname);
uint32_t clken_index = s32k3xx_get_cofb_clken_index(pclk->clkname);
regval = getreg32(clken_reg);
if (pclk->clkgate)
{
regval |= (1 << clken_index);
}
else
{
regval &= ~(1 << clken_index);
}
putreg32(regval, clken_reg);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_periphclocks
*
* Description:
* This function configures peripheral clocks in the PCC block.
*
* Input Parameters:
* count - Number of peripheral clocks to be configured
* pclks - Pointer to an array of peripheral clock configurations
*
* Returned Value:
* None
*
****************************************************************************/
void s32k3xx_periphclocks(unsigned int count,
const struct peripheral_clock_config_s *pclks)
{
unsigned int i;
DEBUGASSERT(pclks != NULL);
for (i = 0; i < count; i++, pclks++)
{
/* Set peripheral clock control */
s32k3xx_cofb_clken(pclks);
}
/* Update Process update register */
putreg32(MC_ME_PRTN_PUPD_PCUD, S32K3XX_MC_ME_PRTN0_PUPD);
putreg32(MC_ME_PRTN_PUPD_PCUD, S32K3XX_MC_ME_PRTN1_PUPD);
putreg32(MC_ME_PRTN_PUPD_PCUD, S32K3XX_MC_ME_PRTN2_PUPD);
/* Control key register */
putreg32(MC_ME_CTL_KEY(0x5af0), S32K3XX_MC_ME_CTL_KEY);
putreg32(MC_ME_CTL_KEY(~0x5af0), S32K3XX_MC_ME_CTL_KEY);
}

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_periphclocks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_PERIPHCLOCKS_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_PERIPHCLOCKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
#include "s32k3xx_config.h"
#include "s32k3xx_clocknames.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Values for peripheral_clock_source_t. An enumeration is not appropriate
* because some of the values are duplicates.
*/
#define CLK_SRC_OFF 0 /* Clock is off */
#define CLK_SRC_SOSC 1 /* OSCCLK - System Oscillator Bus Clock */
#define CLK_SRC_SIRC 2 /* SCGIRCLK - Slow IRC Clock */
#define CLK_SRC_FIRC 3 /* SCGFIRCLK - Fast IRC Clock */
#define CLK_SRC_SPLL 6 /* SCGPCLK System PLL clock */
#define CLK_SRC_SOSC_DIV1 1 /* OSCCLK - System Oscillator Bus Clock */
#define CLK_SRC_SIRC_DIV1 2 /* SCGIRCLK - Slow IRC Clock */
#define CLK_SRC_FIRC_DIV1 3 /* SCGFIRCLK - Fast IRC Clock */
#define CLK_SRC_SPLL_DIV1 6 /* SCGPCLK System PLL clock */
#define CLK_SRC_SOSC_DIV2 1 /* OSCCLK - System Oscillator Bus Clock */
#define CLK_SRC_SIRC_DIV2 2 /* SCGIRCLK - Slow IRC Clock */
#define CLK_SRC_FIRC_DIV2 3 /* SCGFIRCLK - Fast IRC Clock */
#define CLK_SRC_SPLL_DIV2 6 /* SCGPCLK System PLL clock */
/* PCC index offsets (all S32K1xx families). These are used in in the
* family-specific mapping table g_clkname_mapping[] that is used to map a
* clock name to a PCC control register index.
*/
#define PCC_INVALID_INDEX 0
#define PCC_FTFC_INDEX 32
#define PCC_DMAMUX_INDEX 33
#define PCC_FLEXCAN0_INDEX 36
#define PCC_FLEXCAN1_INDEX 37
#define PCC_FTM3_INDEX 38
#define PCC_ADC1_INDEX 39
#define PCC_FLEXCAN2_INDEX 43
#define PCC_LPSPI0_INDEX 44
#define PCC_LPSPI1_INDEX 45
#define PCC_LPSPI2_INDEX 46
#define PCC_PDB1_INDEX 49
#define PCC_CRC_INDEX 50
#define PCC_PDB0_INDEX 54
#define PCC_LPIT_INDEX 55
#define PCC_FTM0_INDEX 56
#define PCC_FTM1_INDEX 57
#define PCC_FTM2_INDEX 58
#define PCC_ADC0_INDEX 59
#define PCC_RTC_INDEX 61
#define PCC_CMU0_INDEX 62
#define PCC_CMU1_INDEX 63
#define PCC_LPTMR0_INDEX 64
#define PCC_PORTA_INDEX 73
#define PCC_PORTB_INDEX 74
#define PCC_PORTC_INDEX 75
#define PCC_PORTD_INDEX 76
#define PCC_PORTE_INDEX 77
#define PCC_SAI0_INDEX 84
#define PCC_SAI1_INDEX 85
#define PCC_FLEXIO_INDEX 90
#define PCC_EWM_INDEX 97
#define PCC_LPI2C0_INDEX 102
#define PCC_LPI2C1_INDEX 103
#define PCC_LPUART0_INDEX 106
#define PCC_LPUART1_INDEX 107
#define PCC_LPUART2_INDEX 108
#define PCC_FTM4_INDEX 110
#define PCC_FTM5_INDEX 111
#define PCC_FTM6_INDEX 112
#define PCC_FTM7_INDEX 113
#define PCC_CMP0_INDEX 115
#define PCC_QSPI_INDEX 118
#define PCC_ENET_INDEX 121
/* Peripheral instance features. */
#define NO_PERIPHERAL_FEATURE (0) /* No peripheral feature */
#define HAS_CLOCK_GATING_IN_SIM (1 << 0) /* Clock gating implemented in SIM */
#define HAS_MULTIPLIER (1 << 1) /* Multiplier implemented in PCC */
#define HAS_DIVIDER (1 << 2) /* Divider implemented in PCC */
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1 << 3) /* Clock source provided by first asynch clock */
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1 << 4) /* Clock source iprovided by second asynch clock */
#define HAS_INT_CLOCK_FROM_BUS_CLOCK (1 << 5) /* Clock is provided by the bus clock */
#define HAS_INT_CLOCK_FROM_SYS_CLOCK (1 << 6) /* Clock is provided by the sys clock */
#define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1 << 7) /* Clock is provided by the slow clock */
/****************************************************************************
* Public Types
****************************************************************************/
typedef uint8_t peripheral_clock_source_t; /* See CLK_SRC_* definitions */
enum peripheral_clock_frac_e
{
MULTIPLY_BY_ONE = 0, /* Fractional value is zero */
MULTIPLY_BY_TWO = 1 /* Fractional value is one */
};
struct peripheral_clock_config_s
{
/* clkname is the name of the peripheral clock. It must be one of the
* values defined in the chip specific xxxxxx_configname.h header file.
*/
enum clock_names_e clkname; /* Peripheral clock name */
bool clkgate; /* Peripheral clock gate */
peripheral_clock_source_t clksrc; /* Peripheral clock source */
enum peripheral_clock_frac_e frac; /* Peripheral clock fractional value */
uint8_t divider; /* Peripheral clock divider, range 1..8 */
};
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Clock name mappings.
*
* Each S32K1xx architecture must provide this array. This is a constant
* array storing the mappings between clock names and peripheral clock
* control indexes. If there is no peripheral clock control index for a
* clock name, then the corresponding value is PCC_INVALID_INDEX.
*/
EXTERN const uint16_t g_clkname_mapping[];
/* Peripheral Features.
*
* Each S32K1xx architecture must provide this array. This is an array of
* bit-encoded peripheral clocking features. See the peripheral instance
* feature definitions above
*/
EXTERN const uint8_t g_periph_features[];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_periphclocks
*
* Description:
* This function configures peripheral clocks in the PCC block.
*
* Input Parameters:
* count - Number of peripheral clocks to be configured
* pclks - Pointer to an array of peripheral clock configurations
*
* Returned Value:
* None
*
****************************************************************************/
void s32k3xx_periphclocks(unsigned int count,
const struct peripheral_clock_config_s *pclks);
/****************************************************************************
* Name: s32k3xx_get_pclkfreq
*
* Description:
* This function returns the clock frequency of the specified peripheral
* functional clock.
*
* Input Parameters:
* clkname - Identifies the peripheral clock of interest
* frequency - The location where the peripheral clock frequency will be
* returned
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure. -ENODEV is returned if the clock is not enabled or is not
* being clocked.
*
****************************************************************************/
int s32k3xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_PERIPHCLOCKS_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_pin.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "s32k3xx_pin.h"
#include "hardware/s32k3xx_siul2.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_pinconfig
*
* Description:
* Configure a pin based on a bit-encoded description of the pin.
* NOTE that DMA/interrupts are disabled at the initial PIN configuration.
*
****************************************************************************/
int s32k3xx_pinconfig(uint32_t cfgset)
{
unsigned int port;
unsigned int pin;
unsigned int input_mode;
unsigned int imcr;
unsigned int output_mode;
uint32_t regval;
/* Get the port and pin number */
port = (cfgset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT;
pin = (cfgset & _PIN_MASK) >> _PIN_SHIFT;
DEBUGASSERT(port < S32K3XX_NPORTS);
DEBUGASSERT(pin < S32K3XX_NPINS);
if ((port >= S32K3XX_NPORTS) && (pin >= S32K3XX_NPINS))
{
return -EINVAL; /* Invalid port or pin number */
}
/* Get the desired input mode */
input_mode = (cfgset & _PIN_INPUT_MODE_MASK) >> _PIN_INPUT_MODE_SHIFT;
/* Get IMCR number (may also be the WKPU number) */
imcr = (cfgset & _IMCR_MASK) >> _IMCR_SHIFT;
/* Check if a valid input mode was defined */
if (input_mode <= _PIN_INPUT_MODE_ALT11)
{
/* The desired input mode should only be written to the IMCR register
* if it does not disable the input signal. Otherwise writing the SSS
* to the IMCR register could cause unwanted behavior (i.e. disable an
* input signal which might have been assigned to another pin).
*
* To completely disable the input signal and make sure it is not
* assigned to any pins, change the IMCR register directly.
*
* TO DO: Create a mapping of input signals to IMCR registers and
* maybe create a function to deassign and disable the signal.
*/
if (input_mode != _PIN_INPUT_MODE_DIS)
{
putreg32(SIUL2_IMCR_SSS(input_mode), S32K3XX_SIUL2_IMCR(imcr));
}
else
{
/* Else we just ignore the selection by doing nothing... */
}
}
else if (input_mode == _PIN_INPUT_MODE_WKPU)
{
/* WKPU interrupt mode */
/* WKPU number is stored in IMCR field */
}
else
{
return -EINVAL; /* Undefined input mode! */
}
/* Get the desired output mode */
output_mode = (cfgset & _PIN_OUTPUT_MODE_MASK) >> _PIN_OUTPUT_MODE_SHIFT;
/* Prepare the value that will be written to the MSCR register */
regval = 0;
/* Source Signal Select */
regval |= SIUL2_MSCR_SSS(output_mode);
/* Drive Strength Enable */
if ((cfgset & _PIN_OUTPUT_DRIVE_MASK) == PIN_OUTPUT_HIGHDRIVE)
{
regval |= SIUL2_MSCR_DSE;
}
/* Pull Enable & Pull Select */
if ((cfgset & _PIN_INPUT_PULLENABLE) == _PIN_INPUT_PULLENABLE)
{
if ((cfgset & _PIN_INPUT_PULL_MASK) == PIN_INPUT_PULLDOWN)
{
regval |= SIUL2_MSCR_PUE; /* Pull-Down */
}
else
{
regval |= (SIUL2_MSCR_PUE | SIUL2_MSCR_PUS); /* Pull-Up */
}
}
/* Slew Rate Control */
if ((cfgset & _PIN_OUTPUT_SLEW_MASK) == PIN_OUTPUT_SLOWSLEW)
{
regval |= SIUL2_MSCR_SRC;
}
/* Input Buffer Enable (IBE) */
regval |= SIUL2_MSCR_IBE;
/* Output Buffer Enable (OBE) */
if ((cfgset & _PIN_OUTPUT_BUFFER_MASK) == PIN_OUTPUT_BUFFERENA)
{
regval |= SIUL2_MSCR_OBE;
}
/* Write to the corresponding MSCR for this pin */
putreg32(regval, S32K3XX_SIUL2_MSCR((port << 5) + pin));
/* For GPIO outputs: Set the initial value */
if ((output_mode == _PIN_MODE_GPIO) &&
((cfgset & _PIN_OUTPUT_BUFFER_MASK) == PIN_OUTPUT_BUFFERENA))
{
s32k3xx_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_ONE) != 0));
}
return OK;
}

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_pin.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_PIN_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_PIN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <hardware/s32k3xx_siul2.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Bit-encoded input to s32k3xx_pinconfig() *********************************/
/* General form (32 bits):
*
* oooo oooo iiii iiii ittt tsss pppn nnnn
* | | | | | `--- n: Pin number (0-31)
* | | | | `--- p: Port (A-F)
* | | | `--- s: Output SSS (Source Signal Select)
* | | `--- t: Input SSS (Source Signal Select)
* | `--- i: IMCR (Input Multiplexing Config. Register)
* `--- o: Options (see below!)
*
* Note: IMCR field may instead contain the external WKPU source number, if
* Input SSS is set to 12.
*
* Options:
* - Bit 24: PUE (Pull Up Enable)
* - Bit 25: PUS (Pull Up Select)
* - Bit 26: OBE (Output Buffer Enable)
* - Bit 27: DSE (Drive Strength Enable)
* - Bit 28: SRC (Slew Rate Control)
* - Bit 29: GPIO Initial Value
* - Bit 30: EIRQ/WKPU Enable Interrupt on Rising Edge
* - Bit 31: EIRQ/WKPU Enable Interrupt on Falling Edge
*
* Not (yet) included/implemented:
* - IBE (Input Buffer Enable) --> IBE will be enabled for all configured
* pins. No option needed.
* - IFE (Input Filter Enable) --> Only available for RESET pin.
* - PKE (Pad Keeping Enable) --> Keep I/O configuration when switching
* between Run and Standby modes.
* - SMC (Safe Mode Control) --> Output buffer will be disabled by default
* when chip enters safe mode.
* - INV (Invert) --> Invert all pad output.
*
* - Selection between DMA or interrupt request (currently only interrupts
* are supported).
* - Configuration of interrupt glitch filter.
*/
/* Five bits are used to define the pin number:
*
* ---- ---- ---- ---- ---- ---- ---n nnnn
*/
#define _PIN_SHIFT (0) /* Bits 0-4: Pin number (0-31) */
#define _PIN_MASK (0x1f << _PIN_SHIFT)
#define PIN(n) ((n) << _PIN_SHIFT)
#define PIN0 (0 << _PIN_SHIFT)
#define PIN1 (1 << _PIN_SHIFT)
#define PIN2 (2 << _PIN_SHIFT)
#define PIN3 (3 << _PIN_SHIFT)
#define PIN4 (4 << _PIN_SHIFT)
#define PIN5 (5 << _PIN_SHIFT)
#define PIN6 (6 << _PIN_SHIFT)
#define PIN7 (7 << _PIN_SHIFT)
#define PIN8 (8 << _PIN_SHIFT)
#define PIN9 (9 << _PIN_SHIFT)
#define PIN10 (10 << _PIN_SHIFT)
#define PIN11 (11 << _PIN_SHIFT)
#define PIN12 (12 << _PIN_SHIFT)
#define PIN13 (13 << _PIN_SHIFT)
#define PIN14 (14 << _PIN_SHIFT)
#define PIN15 (15 << _PIN_SHIFT)
#define PIN16 (16 << _PIN_SHIFT)
#define PIN17 (17 << _PIN_SHIFT)
#define PIN18 (18 << _PIN_SHIFT)
#define PIN19 (19 << _PIN_SHIFT)
#define PIN20 (20 << _PIN_SHIFT)
#define PIN21 (21 << _PIN_SHIFT)
#define PIN22 (22 << _PIN_SHIFT)
#define PIN23 (23 << _PIN_SHIFT)
#define PIN24 (24 << _PIN_SHIFT)
#define PIN25 (25 << _PIN_SHIFT)
#define PIN26 (26 << _PIN_SHIFT)
#define PIN27 (27 << _PIN_SHIFT)
#define PIN28 (28 << _PIN_SHIFT)
#define PIN29 (29 << _PIN_SHIFT)
#define PIN30 (30 << _PIN_SHIFT)
#define PIN31 (31 << _PIN_SHIFT)
/* Three bits are used to define the port number:
*
* ---- ---- ---- ---- ---- ---- ppp- ----
*/
#define _PIN_PORT_SHIFT (5) /* Bits 5-7: Port (A-F) */
#define _PIN_PORT_MASK (0x07 << _PIN_PORT_SHIFT)
#define PIN_PORTA (S32K3XX_PORTA << _PIN_PORT_SHIFT)
#define PIN_PORTB (S32K3XX_PORTB << _PIN_PORT_SHIFT)
#define PIN_PORTC (S32K3XX_PORTC << _PIN_PORT_SHIFT)
#define PIN_PORTD (S32K3XX_PORTD << _PIN_PORT_SHIFT)
#define PIN_PORTE (S32K3XX_PORTE << _PIN_PORT_SHIFT)
#define PIN_PORTF (S32K3XX_PORTF << _PIN_PORT_SHIFT)
#define PIN_PORTG (S32K3XX_PORTG << _PIN_PORT_SHIFT)
/* Sixteen bits are used to define the input/output multiplexing:
*
* ---- ---- iiii iiii ittt tsss ---- ----
*/
#define _PIN_MODE_SHIFT (8) /* Bits 8-23: Pin Mode */
#define _PIN_MODE_MASK (0xffff << _PIN_MODE_SHIFT)
/* Of which three bits are used to define the output multiplexing:
*
* ---- ---- ---- ---- ---- -sss ---- ----
*/
#define _PIN_OUTPUT_MODE_SHIFT (8) /* Bits 8-10: Pin Output Mode */
#define _PIN_OUTPUT_MODE_MASK (0x07 << _PIN_OUTPUT_MODE_SHIFT)
#define _PIN_MODE_GPIO (0x00) /* 000 GPIO */
#define _PIN_OUTPUT_MODE_ALT0 _PIN_MODE_GPIO
#define _PIN_OUTPUT_MODE_ALT1 (0x01) /* 001 Output Alternative 1 */
#define _PIN_OUTPUT_MODE_ALT2 (0x02) /* 010 Output Alternative 2 */
#define _PIN_OUTPUT_MODE_ALT3 (0x03) /* 011 Output Alternative 3 */
#define _PIN_OUTPUT_MODE_ALT4 (0x04) /* 100 Output Alternative 4 */
#define _PIN_OUTPUT_MODE_ALT5 (0x05) /* 101 Output Alternative 5 */
#define _PIN_OUTPUT_MODE_ALT6 (0x06) /* 110 Output Alternative 6 */
#define _PIN_OUTPUT_MODE_ALT7 (0x07) /* 111 Output Alternative 7 */
#define PIN_MODE_GPIO (_PIN_MODE_GPIO << _PIN_OUTPUT_MODE_SHIFT) /* 000 GPIO */
#define PIN_OUTPUT_MODE_ALT0 PIN_MODE_GPIO
#define PIN_OUTPUT_MODE_ALT1 (_PIN_OUTPUT_MODE_ALT1 << _PIN_OUTPUT_MODE_SHIFT) /* 001 Output Alternative 1 */
#define PIN_OUTPUT_MODE_ALT2 (_PIN_OUTPUT_MODE_ALT2 << _PIN_OUTPUT_MODE_SHIFT) /* 010 Output Alternative 2 */
#define PIN_OUTPUT_MODE_ALT3 (_PIN_OUTPUT_MODE_ALT3 << _PIN_OUTPUT_MODE_SHIFT) /* 011 Output Alternative 3 */
#define PIN_OUTPUT_MODE_ALT4 (_PIN_OUTPUT_MODE_ALT4 << _PIN_OUTPUT_MODE_SHIFT) /* 100 Output Alternative 4 */
#define PIN_OUTPUT_MODE_ALT5 (_PIN_OUTPUT_MODE_ALT5 << _PIN_OUTPUT_MODE_SHIFT) /* 101 Output Alternative 5 */
#define PIN_OUTPUT_MODE_ALT6 (_PIN_OUTPUT_MODE_ALT6 << _PIN_OUTPUT_MODE_SHIFT) /* 110 Output Alternative 6 */
#define PIN_OUTPUT_MODE_ALT7 (_PIN_OUTPUT_MODE_ALT7 << _PIN_OUTPUT_MODE_SHIFT) /* 111 Output Alternative 7 */
/* Four bits define the input multiplexing (together with the IMCR field):
*
* ---- ---- ---- ---- -ttt t--- ---- ----
*/
#define _PIN_INPUT_MODE_SHIFT (11) /* Bits 11-14: Pin Input Mode */
#define _PIN_INPUT_MODE_MASK (0x0f << _PIN_INPUT_MODE_SHIFT)
#define _PIN_INPUT_MODE_DIS (0x00) /* 0000 Input Signal Disabled (- Does NOT disable the input buffer!) */
#define _PIN_INPUT_MODE_ALT0 _PIN_INPUT_MODE_DIS
#define _PIN_INPUT_MODE_ALT1 (0x01) /* 0001 Input Alternative 1 */
#define _PIN_INPUT_MODE_ALT2 (0x02) /* 0010 Input Alternative 2 */
#define _PIN_INPUT_MODE_ALT3 (0x03) /* 0011 Input Alternative 3 */
#define _PIN_INPUT_MODE_ALT4 (0x04) /* 0100 Input Alternative 4 */
#define _PIN_INPUT_MODE_ALT5 (0x05) /* 0101 Input Alternative 5 */
#define _PIN_INPUT_MODE_ALT6 (0x06) /* 0110 Input Alternative 6 */
#define _PIN_INPUT_MODE_ALT7 (0x07) /* 0111 Input Alternative 7 */
#define _PIN_INPUT_MODE_ALT8 (0x08) /* 1000 Input Alternative 8 */
#define _PIN_INPUT_MODE_ALT9 (0x09) /* 1001 Input Alternative 9 */
#define _PIN_INPUT_MODE_ALT10 (0x0a) /* 1010 Input Alternative 10 */
#define _PIN_INPUT_MODE_ALT11 (0x0b) /* 1011 Input Alternative 11 */
#define _PIN_INPUT_MODE_WKPU (0x0c) /* 1100 Use Wakeup Unit for external interrupt */
#define _PIN_INPUT_MODE_ALT13 (0x0d) /* 1101 Unused input mode */
#define _PIN_INPUT_MODE_ALT14 (0x0e) /* 1110 Unused input mode */
#define _PIN_INPUT_MODE_ALT15 (0x0f) /* 1111 Unused input mode */
#define PIN_INPUT_MODE_DIS (_PIN_INPUT_MODE_DIS << _PIN_INPUT_MODE_SHIFT) /* 0000 Input Signal Disabled (- Does NOT disable the input buffer!) */
#define PIN_INPUT_MODE_ALT0 PIN_INPUT_MODE_DIS
#define PIN_INPUT_MODE_ALT1 (_PIN_INPUT_MODE_ALT1 << _PIN_INPUT_MODE_SHIFT) /* 0001 Input Alternative 1 */
#define PIN_INPUT_MODE_ALT2 (_PIN_INPUT_MODE_ALT2 << _PIN_INPUT_MODE_SHIFT) /* 0010 Input Alternative 2 */
#define PIN_INPUT_MODE_ALT3 (_PIN_INPUT_MODE_ALT3 << _PIN_INPUT_MODE_SHIFT) /* 0011 Input Alternative 3 */
#define PIN_INPUT_MODE_ALT4 (_PIN_INPUT_MODE_ALT4 << _PIN_INPUT_MODE_SHIFT) /* 0100 Input Alternative 4 */
#define PIN_INPUT_MODE_ALT5 (_PIN_INPUT_MODE_ALT5 << _PIN_INPUT_MODE_SHIFT) /* 0101 Input Alternative 5 */
#define PIN_INPUT_MODE_ALT6 (_PIN_INPUT_MODE_ALT6 << _PIN_INPUT_MODE_SHIFT) /* 0110 Input Alternative 6 */
#define PIN_INPUT_MODE_ALT7 (_PIN_INPUT_MODE_ALT7 << _PIN_INPUT_MODE_SHIFT) /* 0111 Input Alternative 7 */
#define PIN_INPUT_MODE_ALT8 (_PIN_INPUT_MODE_ALT8 << _PIN_INPUT_MODE_SHIFT) /* 1000 Input Alternative 8 */
#define PIN_INPUT_MODE_ALT9 (_PIN_INPUT_MODE_ALT9 << _PIN_INPUT_MODE_SHIFT) /* 1001 Input Alternative 9 */
#define PIN_INPUT_MODE_ALT10 (_PIN_INPUT_MODE_ALT10 << _PIN_INPUT_MODE_SHIFT) /* 1010 Input Alternative 10 */
#define PIN_INPUT_MODE_ALT11 (_PIN_INPUT_MODE_ALT11 << _PIN_INPUT_MODE_SHIFT) /* 1011 Input Alternative 11 */
#define PIN_INPUT_MODE_WKPU (_PIN_INPUT_MODE_WKPU << _PIN_INPUT_MODE_SHIFT) /* 1100 Use Wakeup Unit for external interrupt */
#define PIN_INPUT_MODE_ALT13 (_PIN_INPUT_MODE_ALT13 << _PIN_INPUT_MODE_SHIFT) /* 1101 Unused input mode */
#define PIN_INPUT_MODE_ALT14 (_PIN_INPUT_MODE_ALT14 << _PIN_INPUT_MODE_SHIFT) /* 1110 Unused input mode */
#define PIN_INPUT_MODE_ALT15 (_PIN_INPUT_MODE_ALT15 << _PIN_INPUT_MODE_SHIFT) /* 1111 Unused input mode */
/* Nine bits specify the IMCR number for the input multiplexing:
*
* ---- ---- iiii iiii i--- ---- ---- ----
*/
#define _IMCR_SHIFT (15) /* Bits 15-23: IMCR */
#define _IMCR_MASK (0x01ff << _IMCR_SHIFT)
# define IMCR(n) ((((n) - 512) << _IMCR_SHIFT) & _IMCR_MASK)
#define _WKPU_SHIFT _IMCR_SHIFT /* WKPU number re-uses the IMCR field, only applicable if Input SSS = 12 */
#define _WKPU_MASK (0x3f << _WKPU_SHIFT)
# define WPKU(n) (((n) << _WKPU_SHIFT) & _WKPU_MASK)
/* Eight bits are used to define various pin options:
*
* oooo oooo ---- ---- ---- ---- ---- ----
*/
#define _PIN_OPTIONS_SHIFT (24) /* Bits 24-30: GPIO Pin Options */
#define _PIN_OPTIONS_MASK (0x7f << _PIN_OPTIONS_SHIFT)
/* Of which two bits are used to define pull-up/pull-down behavior:
*
* ---- --oo ---- ---- ---- ---- ---- ----
*/
#define _PIN_INPUT_PULL_SHIFT (24) /* Bits 24-25: Pull-Down/Pull-Up Behavior */
#define _PIN_INPUT_PULL_MASK (0x03 << _PIN_INPUT_PULL_SHIFT)
# define _PIN_INPUT_PULLENABLE (0x01 << _PIN_INPUT_PULL_SHIFT) /* Pull Enable (PUE) */
# define _PIN_INPUT_PULLSELECT (0x02 << _PIN_INPUT_PULL_SHIFT) /* Pull Select (PUS) */
# define PIN_INPUT_PULLDOWN (0x01 << _PIN_INPUT_PULL_SHIFT) /* Pull-Down */
# define PIN_INPUT_PULLUP (0x03 << _PIN_INPUT_PULL_SHIFT) /* Pull-Up */
/* One bit enables the output buffer:
*
* ---- -o-- ---- ---- ---- ---- ---- ----
*/
#define _PIN_OUTPUT_BUFFER_SHIFT (26) /* Bit 26: Output Buffer Enable */
#define _PIN_OUTPUT_BUFFER_MASK (1 << _PIN_OUTPUT_BUFFER_SHIFT)
# define PIN_OUTPUT_BUFFERDIS (0 << _PIN_OUTPUT_BUFFER_SHIFT)
# define PIN_OUTPUT_BUFFERENA (1 << _PIN_OUTPUT_BUFFER_SHIFT)
/* One bit defines the drive strength:
*
* ---- o--- ---- ---- ---- ---- ---- ----
*/
#define _PIN_OUTPUT_DRIVE_SHIFT (27) /* Bit 27: Drive Strength Enable */
#define _PIN_OUTPUT_DRIVE_MASK (1 << _PIN_OUTPUT_DRIVE_SHIFT)
# define PIN_OUTPUT_LOWDRIVE (0 << _PIN_OUTPUT_DRIVE_SHIFT)
# define PIN_OUTPUT_HIGHDRIVE (1 << _PIN_OUTPUT_DRIVE_SHIFT)
/* One bit defines the slew rate:
*
* ---o ---- ---- ---- ---- ---- ---- ----
*/
#define _PIN_OUTPUT_SLEW_SHIFT (28) /* Bit 28: Slew Rate Control */
#define _PIN_OUTPUT_SLEW_MASK (1 << _PIN_OUTPUT_SLEW_SHIFT)
# define PIN_OUTPUT_FASTSLEW (0 << _PIN_OUTPUT_SLEW_SHIFT) /* 0: Fast Slew Rate */
# define PIN_OUTPUT_SLOWSLEW (1 << _PIN_OUTPUT_SLEW_SHIFT) /* 1: Slow (Limited) Slew Rate */
/* The initial value for GPIO (Alternative 0 outputs):
*
* --o- ---- ---- ---- ---- ---- ---- ----
*/
#define _PIN_OUTPUT_INVAL_SHIFT (29) /* Bit 29: GPIO Inititial Value */
#define _PIN_OUTPUT_INVAL_MASK (1 << _PIN_OUTPUT_INVAL_SHIFT)
# define GPIO_OUTPUT_ZERO (0 << _PIN_OUTPUT_INVAL_SHIFT) /* 0: Initial output value is 0 */
# define GPIO_OUTPUT_ONE (1 << _PIN_OUTPUT_INVAL_SHIFT) /* 1: Initial output value is 1 */
/* Two bits are used to encode interrupt options:
*
* oo- ---- ---- ---- ---- ---- ---- ----
*
* TO DO: May be expanded to include DMA options by reusing bits that are
* only relevant for outputs.
*/
#define _PIN_INT_SHIFT (30)
#define _PIN_INT_MASK (0x03 << _PIN_INT_SHIFT)
# define PIN_INT_RISING (0x01 << _PIN_INT_SHIFT) /* 01: Interrupt on rising edge */
# define PIN_INT_FALLING (0x02 << _PIN_INT_SHIFT) /* 10: Interrupt on falling edge */
# define PIN_INT_BOTH (0x03 << _PIN_INT_SHIFT) /* 11: Interrupt on both edges */
/* End-user pin modes and configurations.
*
* Notes:
* (1) None of the digital options are available for analog functions, which
* are handled in parallel and are configured elsewhere.
* (2) Digital settings may be combined (OR'ed) provided that input-only
* and output-only options are not intermixed.
*/
/* GPIO pins */
#define GPIO_INPUT PIN_MODE_GPIO /* Note: Input Buffer will always be enabled for all configured pins! */
#define GPIO_PULLDOWN (PIN_MODE_GPIO | PIN_INPUT_PULLDOWN)
#define GPIO_PULLUP (PIN_MODE_GPIO | PIN_INPUT_PULLUP)
#define GPIO_OUTPUT (PIN_MODE_GPIO | PIN_OUTPUT_BUFFERENA)
#define GPIO_LOWDRIVE (PIN_MODE_GPIO | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define GPIO_HIGHDRIVE (PIN_MODE_GPIO | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define GPIO_FASTSLEW (PIN_MODE_GPIO | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define GPIO_SLOWSLEW (PIN_MODE_GPIO | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
/* Outputs */
#define PIN_OUTPUT_ALT0 (PIN_OUTPUT_MODE_ALT0 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT0_LOWDRIVE (PIN_OUTPUT_MODE_ALT0 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT0_HIGHDRIVE (PIN_OUTPUT_MODE_ALT0 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT0_FASTSLEW (PIN_OUTPUT_MODE_ALT0 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT0_SLOWSLEW (PIN_OUTPUT_MODE_ALT0 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT1 (PIN_OUTPUT_MODE_ALT1 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT1_LOWDRIVE (PIN_OUTPUT_MODE_ALT1 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT1_HIGHDRIVE (PIN_OUTPUT_MODE_ALT1 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT1_FASTSLEW (PIN_OUTPUT_MODE_ALT1 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT1_SLOWSLEW (PIN_OUTPUT_MODE_ALT1 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT2 (PIN_OUTPUT_MODE_ALT2 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT2_LOWDRIVE (PIN_OUTPUT_MODE_ALT2 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT2_HIGHDRIVE (PIN_OUTPUT_MODE_ALT2 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT2_FASTSLEW (PIN_OUTPUT_MODE_ALT2 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT2_SLOWSLEW (PIN_OUTPUT_MODE_ALT2 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT3 (PIN_OUTPUT_MODE_ALT3 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT3_LOWDRIVE (PIN_OUTPUT_MODE_ALT3 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT3_HIGHDRIVE (PIN_OUTPUT_MODE_ALT3 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT3_FASTSLEW (PIN_OUTPUT_MODE_ALT3 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT3_SLOWSLEW (PIN_OUTPUT_MODE_ALT3 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT4 (PIN_OUTPUT_MODE_ALT4 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT4_LOWDRIVE (PIN_OUTPUT_MODE_ALT4 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT4_HIGHDRIVE (PIN_OUTPUT_MODE_ALT4 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT4_FASTSLEW (PIN_OUTPUT_MODE_ALT4 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT4_SLOWSLEW (PIN_OUTPUT_MODE_ALT4 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT5 (PIN_OUTPUT_MODE_ALT5 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT5_LOWDRIVE (PIN_OUTPUT_MODE_ALT5 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT5_HIGHDRIVE (PIN_OUTPUT_MODE_ALT5 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT5_FASTSLEW (PIN_OUTPUT_MODE_ALT5 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT5_SLOWSLEW (PIN_OUTPUT_MODE_ALT5 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT6 (PIN_OUTPUT_MODE_ALT6 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT6_LOWDRIVE (PIN_OUTPUT_MODE_ALT6 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT6_HIGHDRIVE (PIN_OUTPUT_MODE_ALT6 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT6_FASTSLEW (PIN_OUTPUT_MODE_ALT6 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT6_SLOWSLEW (PIN_OUTPUT_MODE_ALT6 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
#define PIN_OUTPUT_ALT7 (PIN_OUTPUT_MODE_ALT7 | PIN_OUTPUT_BUFFERENA)
#define PIN_OUTPUT_ALT7_LOWDRIVE (PIN_OUTPUT_MODE_ALT7 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_LOWDRIVE)
#define PIN_OUTPUT_ALT7_HIGHDRIVE (PIN_OUTPUT_MODE_ALT7 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_HIGHDRIVE)
#define PIN_OUTPUT_ALT7_FASTSLEW (PIN_OUTPUT_MODE_ALT7 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_FASTSLEW)
#define PIN_OUTPUT_ALT7_SLOWSLEW (PIN_OUTPUT_MODE_ALT7 | PIN_OUTPUT_BUFFERENA | PIN_OUTPUT_SLOWSLEW)
/* Inputs */
#define PIN_INPUT_ALT1 PIN_INPUT_MODE_ALT1
#define PIN_INPUT_ALT1_PULLDOWN (PIN_INPUT_MODE_ALT1 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT1_PULLUP (PIN_INPUT_MODE_ALT1 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT2 PIN_INPUT_MODE_ALT2
#define PIN_INPUT_ALT2_PULLDOWN (PIN_INPUT_MODE_ALT2 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT2_PULLUP (PIN_INPUT_MODE_ALT2 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT3 PIN_INPUT_MODE_ALT3
#define PIN_INPUT_ALT3_PULLDOWN (PIN_INPUT_MODE_ALT3 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT3_PULLUP (PIN_INPUT_MODE_ALT3 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT4 PIN_INPUT_MODE_ALT4
#define PIN_INPUT_ALT4_PULLDOWN (PIN_INPUT_MODE_ALT4 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT4_PULLUP (PIN_INPUT_MODE_ALT4 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT5 PIN_INPUT_MODE_ALT5
#define PIN_INPUT_ALT5_PULLDOWN (PIN_INPUT_MODE_ALT5 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT5_PULLUP (PIN_INPUT_MODE_ALT5 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT6 PIN_INPUT_MODE_ALT6
#define PIN_INPUT_ALT6_PULLDOWN (PIN_INPUT_MODE_ALT6 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT6_PULLUP (PIN_INPUT_MODE_ALT6 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT7 PIN_INPUT_MODE_ALT7
#define PIN_INPUT_ALT7_PULLDOWN (PIN_INPUT_MODE_ALT7 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT7_PULLUP (PIN_INPUT_MODE_ALT7 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT8 PIN_INPUT_MODE_ALT8
#define PIN_INPUT_ALT8_PULLDOWN (PIN_INPUT_MODE_ALT8 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT8_PULLUP (PIN_INPUT_MODE_ALT8 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT9 PIN_INPUT_MODE_ALT9
#define PIN_INPUT_ALT9_PULLDOWN (PIN_INPUT_MODE_ALT9 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT9_PULLUP (PIN_INPUT_MODE_ALT9 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT10 PIN_INPUT_MODE_ALT10
#define PIN_INPUT_ALT10_PULLDOWN (PIN_INPUT_MODE_ALT10 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT10_PULLUP (PIN_INPUT_MODE_ALT10 | PIN_INPUT_PULLUP)
#define PIN_INPUT_ALT11 PIN_INPUT_MODE_ALT11
#define PIN_INPUT_ALT11_PULLDOWN (PIN_INPUT_MODE_ALT11 | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_ALT11_PULLUP (PIN_INPUT_MODE_ALT11 | PIN_INPUT_PULLUP)
#define PIN_INPUT_WKPU PIN_INPUT_MODE_WKPU
#define PIN_INPUT_WKPU_PULLDOWN (PIN_INPUT_MODE_WKPU | PIN_INPUT_PULLDOWN)
#define PIN_INPUT_WKPU_PULLUP (PIN_INPUT_MODE_WKPU | PIN_INPUT_PULLUP)
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_pinconfig
*
* Description:
* Configure a pin based on a bit-encoded description of the pin.
*
****************************************************************************/
int s32k3xx_pinconfig(uint32_t cfgset);
/****************************************************************************
* Name: s32k3xx_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void s32k3xx_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: s32k3xx_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool s32k3xx_gpioread(uint32_t pinset);
/****************************************************************************
* Name: s32k3xx_pinirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_GPIOIRQ
void s32k3xx_pinirq_initialize(void);
#else
# define s32k3xx_pinirq_initialize()
#endif
/****************************************************************************
* Name: s32k3xx_pinirqattach
*
* Description:
* Attach a pin interrupt handler. The normal initialization sequence is:
*
* 1. Call s32k3xx_pinconfig() to configure the interrupting pin
* (pin interrupts will be disabled.
* 2. Call s32k3xx_pinirqattach() to attach the pin interrupt handling
* function.
* 3. Call s32k3xx_pinirqenable() to enable interrupts on the pin.
*
* Input Parameters:
* pinset - Pin configuration
* pinisr - Pin interrupt service routine
* arg - An argument that will be provided to the interrupt service
* routine.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int s32k3xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg);
/****************************************************************************
* Name: s32k3xx_pinirqenable
*
* Description:
* Enable the interrupt for specified pin IRQ
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_GPIOIRQ
void s32k3xx_pinirqenable(uint32_t pinset);
#else
# define s32k3xx_pinirqenable(pinset)
#endif
/****************************************************************************
* Name: s32k3xx_pinirqdisable
*
* Description:
* Disable the interrupt for specified pin
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_GPIOIRQ
void s32k3xx_pinirqdisable(uint32_t pinset);
#else
# define s32k3xx_pinirqdisable(pinset)
#endif
/****************************************************************************
* Name: s32k3xx_pindmaenable
*
* Description:
* Enable DMA for specified pin
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_DMA
void s32k3xx_pindmaenable(uint32_t pinset);
#endif
/****************************************************************************
* Name: s32k3xx_pindmadisable
*
* Description:
* Disable DMA for specified pin
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_DMA
void s32k3xx_pindmadisable(uint32_t pinset);
#endif
/****************************************************************************
* Function: s32k3xx_pindump
*
* Description:
* Dump all GPIO registers associated with the base address of the provided
* pinset.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
void s32k3xx_pindump(uint32_t pinset, const char *msg);
#else
# define s32k3xx_pindump(p,m)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_PIN_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_pindma.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <arch/board/board.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
#include "s32k3xx_config.h"
#include "chip.h"
#ifdef CONFIG_S32K3XX_DMA
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_pindmaenable
*
* Description:
* Enable DMA for specified pin
*
****************************************************************************/
void s32k3xx_pindmaenable(uint32_t pinset)
{
#if 0
uintptr_t base;
uint32_t regval;
unsigned int port;
unsigned int pin;
/* Get the port number and pin number */
port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT;
pin = (pinset & _PIN_MASK) >> _PIN_SHIFT;
DEBUGASSERT(port < S32K3XX_NPORTS);
if (port < S32K3XX_NPORTS)
{
/* Get the base address of PORT block for this port */
base = S32K3XX_PORT_BASE(port);
/* Modify the IRQC field of the port PCR register in order to
* enable DMA.
*/
regval = getreg32(base + S32K3XX_PORT_PCR_OFFSET(pin));
regval &= ~PORT_PCR_IRQC_MASK;
switch (pinset & _PIN_INT_MASK)
{
case PIN_DMA_RISING : /* DMA Request on rising edge */
regval |= PORT_PCR_IRQC_DMARISING;
break;
case PIN_DMA_FALLING : /* DMA Request on falling edge */
regval |= PORT_PCR_IRQC_DMAFALLING;
break;
case PIN_DMA_BOTH : /* DMA Request on either edge */
regval |= PORT_PCR_IRQC_DMABOTH;
break;
default:
return;
}
putreg32(regval, base + S32K3XX_PORT_PCR_OFFSET(pin));
}
#endif
}
/****************************************************************************
* Name: s32k3xx_pindmadisable
*
* Description:
* Disable DMA for specified pin
*
****************************************************************************/
void s32k3xx_pindmadisable(uint32_t pinset)
{
#if 0
uintptr_t base;
uint32_t regval;
unsigned int port;
unsigned int pin;
/* Get the port number and pin number */
port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT;
pin = (pinset & _PIN_MASK) >> _PIN_SHIFT;
DEBUGASSERT(port < S32K3XX_NPORTS);
if (port < S32K3XX_NPORTS)
{
/* Get the base address of PORT block for this port */
base = S32K3XX_PORT_BASE(port);
/* Clear the IRQC field of the port PCR register in order to disable
* DMA.
*/
regval = getreg32(base + S32K3XX_PORT_PCR_OFFSET(pin));
regval &= ~PORT_PCR_IRQC_MASK;
putreg32(regval, base + S32K3XX_PORT_PCR_OFFSET(pin));
}
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_pingpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <errno.h>
#include "arm_internal.h"
#include "hardware/s32k3xx_siul2.h"
#include "s32k3xx_pin.h"
#include <arch/board/board.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void s32k3xx_gpiowrite(uint32_t pinset, bool value)
{
unsigned int port;
unsigned int pin;
DEBUGASSERT((pinset & _PIN_OUTPUT_MODE_MASK) == PIN_MODE_GPIO);
DEBUGASSERT((pinset & _PIN_OUTPUT_BUFFER_MASK) == PIN_OUTPUT_BUFFERENA);
/* Get the port and pin number */
port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT;
pin = (pinset & _PIN_MASK) >> _PIN_SHIFT;
DEBUGASSERT(port < S32K3XX_NPORTS);
DEBUGASSERT(pin < S32K3XX_NPINS);
if ((port < S32K3XX_NPORTS) && (pin < S32K3XX_NPINS))
{
/* Set or clear the output */
putreg8(value, S32K3XX_SIUL2_GPDO((port << 5) + pin));
}
}
/****************************************************************************
* Name: s32k3xx_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool s32k3xx_gpioread(uint32_t pinset)
{
unsigned int port;
unsigned int pin;
bool ret = false;
/* Get the port and pin number */
port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT;
pin = (pinset & _PIN_MASK) >> _PIN_SHIFT;
DEBUGASSERT(port < S32K3XX_NPORTS);
DEBUGASSERT(pin < S32K3XX_NPINS);
if ((port < S32K3XX_NPORTS) && (pin < S32K3XX_NPINS))
{
ret = getreg8(S32K3XX_SIUL2_GPDI((port << 5) + pin));
}
return ret;
}

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_pinirq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
#include <s32k3xx_pin.h>
#include <hardware/s32k3xx_siul2.h>
#include <hardware/s32k3xx_wkpu.h>
#ifdef CONFIG_S32K3XX_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define EIRQ_IMCR_FIRST 528 /* First EIRQ IMCR index */
#define EIRQ_IMCR_LAST 559 /* Last EIRQ IMCR index */
#define WKPU_SRC_OFFSET 4 /* Wakeup Source 0-3 are internal sources */
/****************************************************************************
* Private Types
****************************************************************************/
struct s32k3xx_pinirq_s
{
xcpt_t handler;
void *arg;
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt vectors. To keep the memory usage at a minimum, the logic may
* be configured per module.
*/
#ifdef CONFIG_S32K3XX_EIRQINTS
static struct s32k3xx_pinirq_s g_eirqisrs[32];
#endif
#ifdef CONFIG_S32K3XX_WKPUINTS
static struct s32k3xx_pinirq_s g_wkpuisrs[60];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_eirqinterrupt
*
* Description:
* External Interrupt (EIRQ) interrupt handling.
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_EIRQINTS
static int s32k3xx_eirqinterrupt(int irq, void *context, void *arg)
{
uint32_t disr0;
uint32_t direr0;
uint32_t eif;
int i;
/* Find interrupt flags for all enabled interrupts */
disr0 = getreg32(S32K3XX_SIUL2_DISR0);
direr0 = getreg32(S32K3XX_SIUL2_DIRER0);
eif = disr0 & direr0;
/* Examine each EIRQ channel */
for (i = 0; (i < 32) && (eif != 0); i++)
{
uint32_t bit = (1 << i);
if ((eif & bit) != 0)
{
if (g_eirqisrs[i].handler != NULL)
{
xcpt_t handler = g_eirqisrs[i].handler;
void *argument = g_eirqisrs[i].arg;
/* There is a registered interrupt handler... invoke it */
handler(irq, context, argument);
}
/* Writing a one to the DISR0 register will clear the pending
* interrupt.
*/
eif &= ~bit;
putreg32((1 << i), S32K3XX_SIUL2_DISR0);
}
}
return OK;
}
#endif /* CONFIG_S32K3XX_EIRQINTS */
/****************************************************************************
* Name: s32k3xx_wkpuinterrupt
*
* Description:
* Wakeup Unit (WKPU) interrupt handling.
*
****************************************************************************/
#ifdef CONFIG_S32K3XX_WKPUINTS
static int s32k3xx_wkpuinterrupt(int irq, void *context, void *arg)
{
uint32_t wisr;
uint32_t irer;
uint32_t wisr_64;
uint32_t irer_64;
uint64_t eif;
int i;
/* Find interrupt flags for all enabled interrupts */
wisr = getreg32(S32K3XX_WKPU_WISR);
irer = getreg32(S32K3XX_WKPU_IRER);
wisr_64 = getreg32(S32K3XX_WKPU_WISR_64);
irer_64 = getreg32(S32K3XX_WKPU_IRER_64);
eif = (wisr & irer) | (((uint64_t) (wisr_64 & irer_64)) << 32);
/* Examine each WKPU source */
for (i = WKPU_SRC_OFFSET; (i < 64) && (eif != 0); i++)
{
uint64_t bit = (1ULL << i);
if ((eif & bit) != 0)
{
unsigned int index = i - WKPU_SRC_OFFSET; /* g_wkpuisrs only contains IRQ handlers for external WKPU sources */
if (g_wkpuisrs[index].handler != NULL)
{
xcpt_t handler = g_wkpuisrs[index].handler;
void *argument = g_wkpuisrs[index].arg;
/* There is a registered interrupt handler... invoke it */
handler(irq, context, argument);
}
/* Writing a one to the WISR register will clear the pending
* interrupt.
*/
eif &= ~bit;
if (i < 32)
{
putreg32((1 << i), S32K3XX_WKPU_WISR);
}
else
{
putreg32((1 << (i - 32)), S32K3XX_WKPU_WISR_64);
}
}
}
return OK;
}
#endif /* CONFIG_S32K3XX_WKPUINTS */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_pinirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
void s32k3xx_pinirq_initialize(void)
{
#ifdef CONFIG_S32K3XX_EIRQINTS
irq_attach(S32K3XX_IRQ_SIUL2_VEC0, s32k3xx_eirqinterrupt, NULL);
putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ0);
up_enable_irq(S32K3XX_IRQ_SIUL2_VEC0);
irq_attach(S32K3XX_IRQ_SIUL2_VEC1, s32k3xx_eirqinterrupt, NULL);
putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ1);
up_enable_irq(S32K3XX_IRQ_SIUL2_VEC1);
irq_attach(S32K3XX_IRQ_SIUL2_VEC2, s32k3xx_eirqinterrupt, NULL);
putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ2);
up_enable_irq(S32K3XX_IRQ_SIUL2_VEC2);
irq_attach(S32K3XX_IRQ_SIUL2_VEC3, s32k3xx_eirqinterrupt, NULL);
putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ3);
up_enable_irq(S32K3XX_IRQ_SIUL2_VEC3);
#endif /* CONFIG_S32K3XX_EIRQINTS */
#ifdef CONFIG_S32K3XX_WKPUINTS
irq_attach(S32K3XX_IRQ_WKPU, s32k3xx_wkpuinterrupt, NULL);
putreg32(0xffffffff, S32K3XX_WKPU_WISR);
putreg32(0xffffffff, S32K3XX_WKPU_WISR_64);
up_enable_irq(S32K3XX_IRQ_WKPU);
#endif /* CONFIG_S32K3XX_WKPUINTS */
}
/****************************************************************************
* Name: s32k3xx_pinirqattach
*
* Description:
* Attach a pin interrupt handler. The normal initialization sequence is:
*
* 1. Call s32k3xx_pinconfig() to configure the interrupting pin (pin
* interrupts will be disabled).
* 2. Call s32k3xx_pinirqattach() to attach the pin interrupt handling
* function.
* 3. Call s32k3xx_pinirqenable() to enable interrupts on the pin.
*
* Input Parameters:
* pinset - Pin configuration
* pinisr - Pin interrupt service routine
* arg - An argument that will be provided to the interrupt service
* routine.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int s32k3xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
{
unsigned int index;
irqstate_t flags;
#ifdef CONFIG_S32K3XX_EIRQINTS
unsigned int imcr = (pinset & _IMCR_MASK) >> _IMCR_SHIFT;
if (((pinset & _PIN_INPUT_MODE_MASK) != PIN_INPUT_MODE_WKPU) && \
(imcr >= (EIRQ_IMCR_FIRST - 512)) && (imcr <= (EIRQ_IMCR_LAST - 512)))
{
/* Calculate the EIRQ index from the IMCR number */
index = imcr - (EIRQ_IMCR_FIRST - 512);
/* Attach the interrupt handler */
flags = enter_critical_section();
g_eirqisrs[index].handler = pinisr;
g_eirqisrs[index].arg = arg;
leave_critical_section(flags);
return OK;
}
#endif /* CONFIG_S32K3XX_EIRQINTS */
#ifdef CONFIG_S32K3XX_WKPUINTS
if ((pinset & _PIN_INPUT_MODE_MASK) == PIN_INPUT_MODE_WKPU)
{
/* Get the WPKU index based on pinset */
index = (pinset & _WKPU_MASK) >> _WKPU_SHIFT; /* Don't add offset */
/* Attach the interrupt handler */
flags = enter_critical_section();
g_wkpuisrs[index].handler = pinisr;
g_wkpuisrs[index].arg = arg;
leave_critical_section(flags);
return OK;
}
#endif /* CONFIG_S32K3XX_WKPUINTS */
return -EINVAL;
}
/****************************************************************************
* Name: s32k3xx_pinirqenable
*
* Description:
* Enable the interrupt for specified pin IRQ
*
****************************************************************************/
void s32k3xx_pinirqenable(uint32_t pinset)
{
unsigned int index;
#ifdef CONFIG_S32K3XX_EIRQINTS
unsigned int imcr = (pinset & _IMCR_MASK) >> _IMCR_SHIFT;
if (((pinset & _PIN_INPUT_MODE_MASK) != PIN_INPUT_MODE_WKPU) && \
(imcr >= (EIRQ_IMCR_FIRST - 512)) && (imcr <= (EIRQ_IMCR_LAST - 512)))
{
index = imcr - (EIRQ_IMCR_FIRST - 512);
switch (pinset & _PIN_INT_MASK)
{
case PIN_INT_RISING:
{
modifyreg32(S32K3XX_SIUL2_IREER0, 0, 1 << index); /* Enable rising-edge triggered events */
modifyreg32(S32K3XX_SIUL2_IFEER0, 1 << index, 0); /* Disable falling-edge triggered events */
}
break;
case PIN_INT_FALLING:
{
modifyreg32(S32K3XX_SIUL2_IREER0, 0, 1 << index); /* Enable falling-edge triggered events */
modifyreg32(S32K3XX_SIUL2_IFEER0, 1 << index, 0); /* Disable rising-edge triggered events */
}
break;
case PIN_INT_BOTH:
{
modifyreg32(S32K3XX_SIUL2_IREER0, 0, 1 << index); /* Enable rising-edge triggered events */
modifyreg32(S32K3XX_SIUL2_IFEER0, 0, 1 << index); /* Enable falling-edge triggered events */
}
break;
default:
break;
}
/* Enable interrupt requests */
modifyreg32(S32K3XX_SIUL2_DIRER0, 0, 1 << index);
}
#endif /* CONFIG_S32K3XX_EIRQINTS */
#ifdef CONFIG_S32K3XX_WKPUINTS
if ((pinset & _PIN_INPUT_MODE_MASK) == PIN_INPUT_MODE_WKPU)
{
/* Get the WPKU index based on pinset */
index = ((pinset & _WKPU_MASK) >> _WKPU_SHIFT) + WKPU_SRC_OFFSET;
if (index < 32)
{
switch (pinset & _PIN_INT_MASK)
{
case PIN_INT_RISING:
{
modifyreg32(S32K3XX_WKPU_WIREER, 0, 1 << index); /* Enable rising-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFEER, 1 << index, 0); /* Disable falling-edge triggered events */
}
break;
case PIN_INT_FALLING:
{
modifyreg32(S32K3XX_WKPU_WIFEER, 0, 1 << index); /* Enable falling-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIREER, 1 << index, 0); /* Disable rising-edge triggered events */
}
break;
case PIN_INT_BOTH:
{
modifyreg32(S32K3XX_WKPU_WIREER, 0, 1 << index); /* Enable rising-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFEER, 0, 1 << index); /* Enable falling-edge triggered events */
}
break;
default:
break;
}
/* Enable analog glitch filter */
modifyreg32(S32K3XX_WKPU_WIFER, 0, 1 << index);
/* Enable interrupt requests */
modifyreg32(S32K3XX_WKPU_IRER, 0, 1 << index);
}
else
{
switch (pinset & _PIN_INT_MASK)
{
case PIN_INT_RISING:
{
modifyreg32(S32K3XX_WKPU_WIREER_64, 0, 1 << (index - 32)); /* Enable rising-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFEER_64, 1 << (index - 32), 0); /* Disable falling-edge triggered events */
}
break;
case PIN_INT_FALLING:
{
modifyreg32(S32K3XX_WKPU_WIFEER_64, 0, 1 << (index - 32)); /* Enable falling-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIREER_64, 1 << (index - 32), 0); /* Disable rising-edge triggered events */
}
break;
case PIN_INT_BOTH:
{
modifyreg32(S32K3XX_WKPU_WIREER_64, 0, 1 << (index - 32)); /* Enable rising-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFEER_64, 0, 1 << (index - 32)); /* Enable falling-edge triggered events */
}
break;
default:
break;
}
/* Enable analog glitch filter */
modifyreg32(S32K3XX_WKPU_WIFER_64, 0, 1 << (index - 32));
/* Enable interrupt requests */
modifyreg32(S32K3XX_WKPU_IRER_64, 0, 1 << (index - 32));
}
}
#endif /* CONFIG_S32K3XX_WKPUINTS */
}
/****************************************************************************
* Name: s32k3xx_pinirqdisable
*
* Description:
* Disable the interrupt for specified pin
*
****************************************************************************/
void s32k3xx_pinirqdisable(uint32_t pinset)
{
unsigned int index;
#ifdef CONFIG_S32K3XX_EIRQINTS
unsigned int imcr = (pinset & _IMCR_MASK) >> _IMCR_SHIFT;
if (((pinset & _PIN_INPUT_MODE_MASK) != PIN_INPUT_MODE_WKPU) && \
(imcr >= (EIRQ_IMCR_FIRST - 512)) && (imcr <= (EIRQ_IMCR_LAST - 512)))
{
index = imcr - (EIRQ_IMCR_FIRST - 512);
modifyreg32(S32K3XX_SIUL2_DIRER0, 1 << index, 0); /* Disable interrupt requests */
modifyreg32(S32K3XX_SIUL2_IREER0, 1 << index, 0); /* Disable rising-edge triggered events */
modifyreg32(S32K3XX_SIUL2_IFEER0, 1 << index, 0); /* Disable falling-edge triggered events */
}
#endif /* CONFIG_S32K3XX_EIRQINTS */
#ifdef CONFIG_S32K3XX_WKPUINTS
if ((pinset & _PIN_INPUT_MODE_MASK) == PIN_INPUT_MODE_WKPU)
{
/* Get the WPKU index based on pinset */
index = ((pinset & _WKPU_MASK) >> _WKPU_SHIFT) + WKPU_SRC_OFFSET;
if (index < 32)
{
modifyreg32(S32K3XX_WKPU_IRER, 1 << index, 0); /* Disable interrupt requests */
modifyreg32(S32K3XX_WKPU_WIREER, 1 << index, 0); /* Disable rising-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFEER, 1 << index, 0); /* Disable falling-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFER, 1 << index, 0); /* Disable analog glitch filter */
}
else
{
modifyreg32(S32K3XX_WKPU_IRER_64, 1 << (index - 32), 0); /* Disable interrupt requests */
modifyreg32(S32K3XX_WKPU_WIREER_64, 1 << (index - 32), 0); /* Disable rising-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFEER_64, 1 << (index - 32), 0); /* Disable falling-edge triggered events */
modifyreg32(S32K3XX_WKPU_WIFER_64, 1 << (index - 32), 0); /* Disable analog glitch filter */
}
}
#endif /* CONFIG_S32K3XX_WKPUINTS */
}
#endif /* CONFIG_S32K3XX_GPIOIRQ */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_qspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_QSPI_H
#define __ARCH_ARM_SRC_S32K3XX_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi/qspi.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
#ifdef CONFIG_S32K3XX_QSPI
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_qspi_initialize
*
* Description:
* Initialize the selected QSPI port in master mode
*
* Input Parameters:
* intf - Interface number(must be zero)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct qspi_dev_s;
struct qspi_dev_s *s32k3xx_qspi_initialize(int intf);
/****************************************************************************
* Name: s32k3xx_qspi_enter_memorymapped
*
* Description:
* Put the QSPI device into memory mapped mode
*
* Input Parameters:
* dev - QSPI device
* meminfo - parameters like for a memory transfer used for reading
* lpto - number of cycles to wait to automatically de-assert CS
*
* Returned Value:
* None
*
****************************************************************************/
void s32k3xx_qspi_enter_memorymapped(struct qspi_dev_s *dev,
const struct qspi_meminfo_s *meminfo,
uint32_t lpto);
/****************************************************************************
* Name: s32k3xx_qspi_exit_memorymapped
*
* Description:
* Take the QSPI device out of memory mapped mode
*
* Input Parameters:
* dev - QSPI device
*
* Returned Value:
* None
*
****************************************************************************/
void s32k3xx_qspi_exit_memorymapped(struct qspi_dev_s *dev);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_S32K3XX_QSPI */
#endif /* __ARCH_ARM_SRC_S32K3XX_QSPI_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_serial.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_SERIAL_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_SERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "s32k3xx_config.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_earlyserialinit
*
* Description:
* Performs the low level UART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before arm_serialinit.
*
****************************************************************************/
#ifdef USE_EARLYSERIALINIT
void s32k3xx_earlyserialinit(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_SERIAL_H */

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/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include <arch/irq.h>
#include "arm_internal.h"
#include "nvic.h"
#ifdef CONFIG_BUILD_PROTECTED
# include "s32k3xx_userspace.h"
#endif
#include "hardware/s32k3xx_mcm.h"
#include "hardware/s32k3xx_mc_me.h"
#include "s32k3xx_clockconfig.h"
#include "s32k3xx_lowputc.h"
#include "s32k3xx_serial.h"
#include "s32k3xx_swt.h"
#include "s32k3xx_start.h"
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K3XX_ENET)
#include "hardware/s32k3xx_mpu.h"
#endif
#ifdef CONFIG_S32K3XX_PROGMEM
#include "s32k3xx_progmem.h"
#endif
#ifdef CONFIG_S32K3XX_EEEPROM
#include "s32k3xx_eeeprom.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory Map ***************************************************************/
/* 0x0040:1000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address CM7_0_START_ADDRESS at reset.
* 0x007d:0fff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2040:8000 - Start of internal SRAM and start of .data (_sdata)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U.
* The RAM is implemented such that the SRAM_L and SRAM_U
* ranges form a contiguous block in the memory map. Thus, the
* actual SRAM start address is SAM_L which some MCU-specific
* value in the range 0x1000:0000 and 0x1fff:ffff. SRAM_U
* then always starts at 0x2000:0000
* - End of .data (_edata) and start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
* start of heap. NOTE that the ARM uses a decrement before
* store stack so that the correct initial value is the end of
* the stack + 4;
* 0x2044:4000 - End of internal SRAM and end of heap. The actual end of
* SRAM_U will depend on the amount of memory supported by the
* MCU/
*
* NOTE: ARM EABI requires 64 bit stack alignment.
*/
#define STARTUP_ECC_INITVALUE 0
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) s32k3xx_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Private Types
****************************************************************************/
extern const uint32_t SRAM_BASE_ADDR;
extern const uint32_t SRAM_END_ADDR;
extern const uint32_t ITCM_BASE_ADDR;
extern const uint32_t ITCM_END_ADDR;
extern const uint32_t DTCM_BASE_ADDR;
extern const uint32_t DTCM_END_ADDR;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_mpu_config
*
* Description:
* Enable all bus masters.
*
****************************************************************************/
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K3XX_ENET)
static inline void s32k3xx_mpu_config(void)
{
uint32_t regval;
/* Bus masters 0-2 are already enabled r/w/x in supervisor and user modes
* after reset. Enable also bus master 3 (ENET) in S/U modes in default
* region 0: User=r+w+x, Supervisor=same as used.
*/
regval = (MPU_RGDAAC_M3UM_XACCESS | MPU_RGDAAC_M3UM_WACCESS |
MPU_RGDAAC_M3UM_RACCESS | MPU_RGDAAC_M3SM_M3UM);
putreg32(regval, S32K3XX_MPU_RGDAAC(0));
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
#define STR(x) #x
#define XSTR(s) STR(s)
void s32k3xx_start(void)
{
register uint64_t *src;
register uint64_t *dest;
/* Technically startup.S did initialize SRAM
* but if don't set init value here again
* then on a cold boot we go into a bootloop somehow
*/
dest = (uint64_t *)&SRAM_BASE_ADDR;
while (dest < (uint64_t *)&SRAM_END_ADDR)
{
*dest++ = STARTUP_ECC_INITVALUE;
}
/* ITCM */
dest = (uint64_t *)&ITCM_BASE_ADDR;
while (dest < (uint64_t *)&ITCM_END_ADDR)
{
*dest++ = STARTUP_ECC_INITVALUE;
}
/* DTCM */
dest = (uint64_t *)&DTCM_BASE_ADDR;
while (dest < (uint64_t *)&DTCM_END_ADDR)
{
*dest++ = STARTUP_ECC_INITVALUE;
}
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = (uint64_t *)&_sbss; dest < (uint64_t *)&_ebss; )
{
*dest++ = 0;
}
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = (uint64_t *)&_eronly, dest = (uint64_t *)&_sdata;
dest < (uint64_t *)&_edata;
)
{
*dest++ = *src++;
}
#endif
/* Copy any necessary code sections from FLASH to RAM. The correct
* destination in SRAM is given by _sramfuncs and _eramfuncs. The
* temporary location is in flash after the data initialization code
* at _framfuncs. This should be done before s32k3xx_clockconfig() is
* called (in case it has some dependency on initialized C variables).
*/
#ifdef CONFIG_ARCH_RAMFUNCS
for (src = (uint64_t *)&_framfuncs, dest = (uint64_t *)&_sramfuncs;
dest < (uint64_t *)&_eramfuncs;
)
{
*dest++ = *src++;
}
#endif
/* Configure the clocking and the console uart so that we can get debug
* output as soon as possible. NOTE: That this logic must not assume that
* .bss or .data have been initialized.
*/
DEBUGVERIFY(s32k3xx_clockconfig(&g_initial_clkconfig));
s32k3xx_lowsetup();
showprogress('B');
/* Initialize the FPU (if configured) */
arm_fpuconfig();
/* Enable I- and D-Caches */
up_enable_icache();
up_enable_dcache();
showprogress('C');
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K3XX_ENET)
/* Enable all MPU bus masters */
s32k3xx_mpu_config();
showprogress('D');
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
s32k3xx_earlyserialinit();
#endif
showprogress('E');
#ifdef CONFIG_S32K3XX_PROGMEM
s32k3xx_progmem_init();
#endif
#ifdef CONFIG_S32K3XX_EEEPROM
s32k3xx_eeeprom_init();
#endif
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
s32k3xx_userspace();
showprogress('F');
#endif
/* Initialize on-board resources */
showprogress('G');
s32k3xx_board_initialize();
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; );
}

70
arch/arm/src/s32k3xx/s32k3xx_start.h Normal file
View file

@ -0,0 +1,70 @@
/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_START_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* Each S32K1xx board must provide the following initialized structure.
* This is needed to establish the initial board clocking.
*/
extern const struct clock_configuration_s g_initial_clkconfig;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k3xx_board_initialize
*
* Description:
* All S32K3XX architectures must provide the following entry point.
* This entry point is called early in the initialization -- after
* clocking and memory have been configured but before caches have been
* enabled and before any devices have been initialized.
*
****************************************************************************/
void s32k3xx_board_initialize(void);
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_START_H */

104
arch/arm/src/s32k3xx/s32k3xx_swt.h Normal file
View file

@ -0,0 +1,104 @@
/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_swt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
#ifndef __ARCH_ARM_SRC_S32K3XX_S32K3XX_WDOG_H
#define __ARCH_ARM_SRC_S32K3XX_S32K3XX_WDOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "hardware/s32k3xx_swt.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Name: s32k3xx_swt_disable
*
* Description:
* Performs the low level UART initialization early in debug so that the
* serial console will be available during boot-up. This must be called
* before arm_serialinit.
*
* REVISIT: Hardcoded assumption that WDOG clock derives for LPO_CLK
*
****************************************************************************/
static inline void s32k3xx_swt_disable(void)
{
/* Unlock soft lock */
putreg32(0xc520, S32K3XX_SWT0_SR);
putreg32(0xd928, S32K3XX_SWT0_SR);
/* Enable access */
putreg32(SWT_CR_MAP0 |
SWT_CR_MAP1 |
SWT_CR_MAP2 |
SWT_CR_MAP3 |
SWT_CR_MAP4 |
SWT_CR_MAP5 |
SWT_CR_MAP6 |
SWT_CR_MAP7 |
SWT_CR_WND, S32K3XX_SWT0_CR);
}
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_S32K3XX_S32K3XX_WDOG_H */

133
arch/arm/src/s32k3xx/s32k3xx_timerisr.c Normal file
View file

@ -0,0 +1,133 @@
/****************************************************************************
* arch/arm/src/s32k3xx/s32k3xx_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "arm_internal.h"
#include "clock/clock.h"
#include "s32k3xx_clockconfig.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The SysTick clock input (Fsystick) is determined by the CLKSOURCE file of
* the SysTick CSR register: The CLKSOURCE field in SysTick Control and
* Status register selects either the core clock (when CLKSOURCE = 1) or a
* divide-by-16 of the core clock (when CLKSOURCE = 0).
*
* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* reload = (Fsystick / CLK_TICK) - 1
*/
#define SYSTICK_RELOAD(coreclk) (((coreclk) / CLK_TCK) - 1)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: s32k3xx_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int s32k3xx_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t coreclk;
uint32_t reload;
/* Make sure that the SYSTICK clock source is set to use the SysTick
* function clock (CLKSOURCE==1).
*/
putreg32(NVIC_SYSTICK_CTRL_CLKSOURCE, NVIC_SYSTICK_CTRL);
/* Get the reload value */
coreclk = s32k3xx_get_coreclk();
reload = SYSTICK_RELOAD(coreclk);
/* The size of the reload field is 24 bits. */
DEBUGASSERT(reload <= 0x00ffffff);
/* Configure SysTick to interrupt at the requested rate */
putreg32(reload, NVIC_SYSTICK_RELOAD);
putreg32(0, NVIC_SYSTICK_CURRENT);
/* Attach the timer interrupt vector */
irq_attach(S32K3XX_IRQ_SYSTICK, (xcpt_t)s32k3xx_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(S32K3XX_IRQ_SYSTICK);
}

57
arch/arm/src/s32k3xx/startup.S Normal file
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@ -0,0 +1,57 @@
/****************************************************************************
* arch/arm/src/s32k3xx/startup.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Copyright 2022 NXP */
.syntax unified
.arch armv7-m
.text
.global __start
.type __start, function
__start:
cpsid i
mov r0, #0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
/* Initialize SRAM ECC */
ldr r1, =SRAM_BASE_ADDR
ldr r2, =SRAM_END_ADDR
subs r2, r1
subs r2, #1
ble SRAM_LOOP_END
movs r0, 0
movs r3, 0
SRAM_LOOP:
stm r1!, {r0,r3}
subs r2, 8
bge SRAM_LOOP
SRAM_LOOP_END:
b s32k3xx_start
.align 4
.ltorg

35
drivers/serial/Kconfig
View file

@ -486,6 +486,41 @@ config LPUART8_SERIAL_CONSOLE
depends on LPUART8_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART9_SERIAL_CONSOLE
bool "LPUART9"
depends on LPUART9_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART10_SERIAL_CONSOLE
bool "LPUART10"
depends on LPUART10_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART11_SERIAL_CONSOLE
bool "LPUART11"
depends on LPUART11_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART12_SERIAL_CONSOLE
bool "LPUART12"
depends on LPUART12_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART13_SERIAL_CONSOLE
bool "LPUART13"
depends on LPUART13_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART14_SERIAL_CONSOLE
bool "LPUART14"
depends on LPUART14_SERIALDRIVER
select SERIAL_CONSOLE
config LPUART15_SERIAL_CONSOLE
bool "LPUART15"
depends on LPUART15_SERIALDRIVER
select SERIAL_CONSOLE
config SCI0_SERIAL_CONSOLE
bool "SCI0"
depends on SCI0_SERIALDRIVER

707
drivers/serial/Kconfig-lpuart
View file

@ -53,6 +53,41 @@ config LPUART8_SERIALDRIVER
default n
select MCU_SERIAL
config LPUART9_SERIALDRIVER
bool
default n
select MCU_SERIAL
config LPUART10_SERIALDRIVER
bool
default n
select MCU_SERIAL
config LPUART11_SERIALDRIVER
bool
default n
select MCU_SERIAL
config LPUART12_SERIALDRIVER
bool
default n
select MCU_SERIAL
config LPUART13_SERIALDRIVER
bool
default n
select MCU_SERIAL
config LPUART14_SERIALDRIVER
bool
default n
select MCU_SERIAL
config LPUART15_SERIALDRIVER
bool
default n
select MCU_SERIAL
#####################################################################################
menu "LPUART0 Configuration"
@ -918,3 +953,675 @@ config LPUART8_TXDMA
Enable Tx DMA transfers on LPUART8
endmenu
#####################################################################################
menu "LPUART9 Configuration"
depends on LPUART9_SERIALDRIVER
config LPUART9_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART9_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART9_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART9_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART9_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART9_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART9_NOIFLOWCONTROL
config LPUART9_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART9_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART9_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART9_INVERTIFLOWCONTROL
depends on LPUART9_RS485RTSCONTROL || LPUART9_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART9_OFLOWCONTROL
depends on !LPUART9_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART9_RXDMA
bool "LPUART9 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART9
config LPUART9_TXDMA
bool "LPUART9 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART9
endmenu
#####################################################################################
menu "LPUART10 Configuration"
depends on LPUART10_SERIALDRIVER
config LPUART10_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART10_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART10_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART10_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART10_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART10_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART10_NOIFLOWCONTROL
config LPUART10_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART10_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART10_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART10_INVERTIFLOWCONTROL
depends on LPUART10_RS485RTSCONTROL || LPUART10_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART10_OFLOWCONTROL
depends on !LPUART10_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART10_RXDMA
bool "LPUART10 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART10
config LPUART10_TXDMA
bool "LPUART10 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART10
endmenu
#####################################################################################
menu "LPUART11 Configuration"
depends on LPUART11_SERIALDRIVER
config LPUART11_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART11_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART11_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART11_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART11_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART11_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART11_NOIFLOWCONTROL
config LPUART11_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART11_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART11_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART11_INVERTIFLOWCONTROL
depends on LPUART11_RS485RTSCONTROL || LPUART11_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART11_OFLOWCONTROL
depends on !LPUART11_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART11_RXDMA
bool "LPUART11 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART11
config LPUART11_TXDMA
bool "LPUART11 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART11
endmenu
#####################################################################################
menu "LPUART12 Configuration"
depends on LPUART12_SERIALDRIVER
config LPUART12_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART12_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART12_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART12_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART12_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART12_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART12_NOIFLOWCONTROL
config LPUART12_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART12_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART12_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART12_INVERTIFLOWCONTROL
depends on LPUART12_RS485RTSCONTROL || LPUART12_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART12_OFLOWCONTROL
depends on !LPUART12_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART12_RXDMA
bool "LPUART12 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART12
config LPUART12_TXDMA
bool "LPUART12 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART12
endmenu
#####################################################################################
menu "LPUART13 Configuration"
depends on LPUART13_SERIALDRIVER
config LPUART13_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART13_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART13_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART13_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART13_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART13_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART13_NOIFLOWCONTROL
config LPUART13_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART13_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART13_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART13_INVERTIFLOWCONTROL
depends on LPUART13_RS485RTSCONTROL || LPUART13_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART13_OFLOWCONTROL
depends on !LPUART13_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART13_RXDMA
bool "LPUART13 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART13
config LPUART13_TXDMA
bool "LPUART13 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART13
endmenu
#####################################################################################
menu "LPUART14 Configuration"
depends on LPUART14_SERIALDRIVER
config LPUART14_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART14_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART14_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART14_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART14_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART14_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART14_NOIFLOWCONTROL
config LPUART14_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART14_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART14_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART14_INVERTIFLOWCONTROL
depends on LPUART14_RS485RTSCONTROL || LPUART14_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART14_OFLOWCONTROL
depends on !LPUART14_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART14_RXDMA
bool "LPUART14 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART14
config LPUART14_TXDMA
bool "LPUART14 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART14
endmenu
#####################################################################################
menu "LPUART15 Configuration"
depends on LPUART15_SERIALDRIVER
config LPUART15_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART15_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART15_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the LPUART.
config LPUART15_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART15_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART15_2STOP
int "Uses 2 stop bits"
default 0
---help---
1=Two stop bits
choice
prompt "IFLOW Control"
default LPUART15_NOIFLOWCONTROL
config LPUART15_NOIFLOWCONTROL
bool "No IFLOW control"
---help---
No IFLOW control
config LPUART15_RS485RTSCONTROL
bool "RTS for RS485 Direction"
select SERIAL_RS485CONTROL
---help---
Use RTS pin for RS485 direction switching
config LPUART15_IFLOWCONTROL
bool "RTS for IFLOW control"
select SERIAL_IFLOWCONTROL
---help---
Enable RTS flow control
endchoice
config LPUART15_INVERTIFLOWCONTROL
depends on LPUART15_RS485RTSCONTROL || LPUART15_IFLOWCONTROL
bool "Invert sense of RTS bit"
default n
---help---
Make RTS bit active high rather than active low
config LPUART15_OFLOWCONTROL
depends on !LPUART15_RS485RTSCONTROL
bool "CTS OFLOW control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable CTS flow control
config LPUART15_RXDMA
bool "LPUART15 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on LPUART15
config LPUART15_TXDMA
bool "LPUART15 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on LPUART15
endmenu