mirror of
https://github.com/apache/nuttx.git
synced 2025-01-13 09:49:21 +08:00
fix all remaining nxstyle errors
This commit is contained in:
Matias Nitsche
Alin Jerpelea
parent
2d8a534ef5
commit
e0d21275df
14 changed files with 438 additions and 384 deletions
|
|
@ -1,7 +1,8 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/stm32/common/src/stm32_ina219.c
|
||||
*
|
||||
* Copyright (C) 2018 Erle Robotics (Juan Flores Muñoz). All rights reserved.
|
||||
* Copyright (C) 2018 Erle Robotics (Juan Flores Muñoz). All rights
|
||||
* reserved.
|
||||
* Author: Erle Robotics (Juan Flores Muñoz) <juan@erlerobotics.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
|
|||
|
|
@ -218,68 +218,70 @@ int board_app_initialize(uintptr_t arg)
|
|||
" FLASH driver\n");
|
||||
|
||||
#ifdef CONFIG_MIKROE_FLASH_PART
|
||||
{
|
||||
int partno;
|
||||
int partsize;
|
||||
int partoffset;
|
||||
const char *partstring = CONFIG_MIKROE_FLASH_PART_LIST;
|
||||
const char *ptr;
|
||||
FAR struct mtd_dev_s *mtd_part;
|
||||
char partname[4];
|
||||
{
|
||||
int partno;
|
||||
int partsize;
|
||||
int partoffset;
|
||||
const char *partstring = CONFIG_MIKROE_FLASH_PART_LIST;
|
||||
const char *ptr;
|
||||
FAR struct mtd_dev_s *mtd_part;
|
||||
char partname[4];
|
||||
|
||||
/* Now create a partition on the FLASH device */
|
||||
/* Now create a partition on the FLASH device */
|
||||
|
||||
partno = 0;
|
||||
ptr = partstring;
|
||||
partoffset = 0;
|
||||
partno = 0;
|
||||
ptr = partstring;
|
||||
partoffset = 0;
|
||||
|
||||
while (*ptr != '\0')
|
||||
{
|
||||
/* Get the partition size */
|
||||
while (*ptr != '\0')
|
||||
{
|
||||
/* Get the partition size */
|
||||
|
||||
partsize = atoi(ptr);
|
||||
mtd_part = mtd_partition(mtd, partoffset, (partsize >> 2) * 16);
|
||||
partoffset += (partsize >> 2) * 16;
|
||||
partsize = atoi(ptr);
|
||||
mtd_part = mtd_partition(mtd, partoffset,
|
||||
(partsize >> 2) * 16);
|
||||
partoffset += (partsize >> 2) * 16;
|
||||
|
||||
#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART
|
||||
/* Test if this is the config partition */
|
||||
/* Test if this is the config partition */
|
||||
|
||||
if (CONFIG_MIKROE_FLASH_CONFIG_PART_NUMBER == partno)
|
||||
{
|
||||
/* Register the partition as the config device */
|
||||
if (CONFIG_MIKROE_FLASH_CONFIG_PART_NUMBER == partno)
|
||||
{
|
||||
/* Register the partition as the config device */
|
||||
|
||||
mtdconfig_register(mtd_part);
|
||||
}
|
||||
else
|
||||
mtdconfig_register(mtd_part);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* Now initialize a SMART Flash block device and bind it
|
||||
* to the MTD device.
|
||||
*/
|
||||
{
|
||||
/* Now initialize a SMART Flash block device and bind it
|
||||
* to the MTD device.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS)
|
||||
sprintf(partname, "p%d", partno);
|
||||
smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd_part, partname);
|
||||
#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS)
|
||||
sprintf(partname, "p%d", partno);
|
||||
smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd_part,
|
||||
partname);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* Update the pointer to point to the next size in the list */
|
||||
/* Update the pointer to point to the next size in the list */
|
||||
|
||||
while ((*ptr >= '0') && (*ptr <= '9'))
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
while ((*ptr >= '0') && (*ptr <= '9'))
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
|
||||
if (*ptr == ',')
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
if (*ptr == ',')
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
|
||||
/* Increment the part number */
|
||||
/* Increment the part number */
|
||||
|
||||
partno++;
|
||||
}
|
||||
}
|
||||
partno++;
|
||||
}
|
||||
}
|
||||
#else /* CONFIG_MIKROE_FLASH_PART */
|
||||
|
||||
/* Configure the device with no partition support */
|
||||
|
|
@ -292,17 +294,20 @@ int board_app_initialize(uintptr_t arg)
|
|||
/* Create a RAM MTD device if configured */
|
||||
|
||||
#if defined(CONFIG_RAMMTD) && defined(CONFIG_MIKROE_RAMMTD)
|
||||
{
|
||||
uint8_t *start = (uint8_t *) kmm_malloc(CONFIG_MIKROE_RAMMTD_SIZE * 1024);
|
||||
mtd = rammtd_initialize(start, CONFIG_MIKROE_RAMMTD_SIZE * 1024);
|
||||
mtd->ioctl(mtd, MTDIOC_BULKERASE, 0);
|
||||
{
|
||||
uint8_t *start =
|
||||
(uint8_t *) kmm_malloc(CONFIG_MIKROE_RAMMTD_SIZE * 1024);
|
||||
mtd = rammtd_initialize(start, CONFIG_MIKROE_RAMMTD_SIZE * 1024);
|
||||
mtd->ioctl(mtd, MTDIOC_BULKERASE, 0);
|
||||
|
||||
/* Now initialize a SMART Flash block device and bind it to the MTD device */
|
||||
/* Now initialize a SMART Flash block device and bind it to the
|
||||
* MTD device
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS)
|
||||
smart_initialize(CONFIG_MIKROE_RAMMTD_MINOR, mtd, NULL);
|
||||
smart_initialize(CONFIG_MIKROE_RAMMTD_MINOR, mtd, NULL);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RAMMTD && CONFIG_MIKROE_RAMMTD */
|
||||
|
||||
|
|
@ -310,6 +315,7 @@ int board_app_initialize(uintptr_t arg)
|
|||
#endif /* CONFIG_STM32_SPI3 */
|
||||
|
||||
/* Create the SPI FLASH MTD instance */
|
||||
|
||||
/* The M25Pxx is not a good media to implement a file system..
|
||||
* its block sizes are too large
|
||||
*/
|
||||
|
|
@ -322,10 +328,12 @@ int board_app_initialize(uintptr_t arg)
|
|||
syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n",
|
||||
CONFIG_NSH_MMCSDMINOR);
|
||||
|
||||
ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, CONFIG_NSH_MMCSDSLOTNO, spi);
|
||||
ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR,
|
||||
CONFIG_NSH_MMCSDSLOTNO, spi);
|
||||
if (ret != OK)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to bind SPI to the MMC/SD driver: %d\n", ret);
|
||||
syslog(LOG_ERR, "ERROR: Failed to bind SPI to the MMC/SD driver:"
|
||||
" %d\n", ret);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -334,8 +342,8 @@ int board_app_initialize(uintptr_t arg)
|
|||
#endif
|
||||
|
||||
#ifdef HAVE_USBHOST
|
||||
/* Initialize USB host operation. stm32_usbhost_initialize() starts a thread
|
||||
* will monitor for USB connection and disconnection events.
|
||||
/* Initialize USB host operation. stm32_usbhost_initialize() starts a
|
||||
* thread will monitor for USB connection and disconnection events.
|
||||
*/
|
||||
|
||||
ret = stm32_usbhost_initialize();
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#define HAVE_MMCSD 1
|
||||
#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \
|
||||
|
|
@ -58,9 +58,9 @@
|
|||
# undef HAVE_MMCSD
|
||||
#endif
|
||||
|
||||
/* LED. User LD2: the green LED is a user LED connected to Arduino signal D13
|
||||
* corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on the STM32
|
||||
* target.
|
||||
/* LED. User LD2: the green LED is a user LED connected to Arduino signal
|
||||
* D13 corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on
|
||||
* the STM32 target.
|
||||
*
|
||||
* - When the I/O is HIGH value, the LED is on.
|
||||
* - When the I/O is LOW, the LED is off.
|
||||
|
|
@ -225,7 +225,7 @@ extern struct sdio_dev_s *g_sdio;
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#define HAVE_MMCSD 1
|
||||
#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \
|
||||
|
|
@ -58,10 +58,9 @@
|
|||
# undef HAVE_MMCSD
|
||||
#endif
|
||||
|
||||
/* LED. User LD2: the green LED is a user LED connected to Arduino signal D13
|
||||
* corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on the
|
||||
* STM32
|
||||
* target.
|
||||
/* LED. User LD2: the green LED is a user LED connected to Arduino signal
|
||||
* D13 corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on
|
||||
* the STM32 target.
|
||||
*
|
||||
* - When the I/O is HIGH value, the LED is on.
|
||||
* - When the I/O is LOW, the LED is off.
|
||||
|
|
@ -233,7 +232,7 @@ extern struct sdio_dev_s *g_sdio;
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -51,7 +51,9 @@
|
|||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* Configuration ****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* How many SPI modules does this chip support? */
|
||||
|
||||
#if STM32_NSPI < 1
|
||||
|
|
@ -65,27 +67,29 @@
|
|||
# undef CONFIG_STM32_SPI3
|
||||
#endif
|
||||
|
||||
/* STM32F3Discovery GPIOs **************************************************************************/
|
||||
/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by logic on
|
||||
* the board and are not available for software control:
|
||||
/* STM32F3Discovery GPIOs ***************************************************/
|
||||
|
||||
/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 PWR: red LED indicates that the board is powered.
|
||||
* LD2 COM: LD2 default status is red. LD2 turns to green to indicate that
|
||||
* communications are in progress between the PC and the ST-LINK/V2.
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2.
|
||||
*
|
||||
* And eight can be controlled by software:
|
||||
*
|
||||
* User LD3: red LED is a user LED connected to the I/O PE9 of the STM32F303VCT6.
|
||||
* User LD4: blue LED is a user LED connected to the I/O PE8 of the STM32F303VCT6.
|
||||
* User LD5: orange LED is a user LED connected to the I/O PE10 of the STM32F303VCT6.
|
||||
* User LD6: green LED is a user LED connected to the I/O PE15 of the STM32F303VCT6.
|
||||
* User LD7: green LED is a user LED connected to the I/O PE11 of the STM32F303VCT6.
|
||||
* User LD8: orange LED is a user LED connected to the I/O PE14 of the STM32F303VCT6.
|
||||
* User LD9: blue LED is a user LED connected to the I/O PE12 of the STM32F303VCT6.
|
||||
* User LD10: red LED is a user LED connected to the I/O PE13 of the STM32F303VCT6.
|
||||
* User LD3: red LED is a user LED connected to PE9
|
||||
* User LD4: blue LED is a user LED connected to PE8
|
||||
* User LD5: orange LED is a user LED connected to PE10
|
||||
* User LD6: green LED is a user LED connected to PE15
|
||||
* User LD7: green LED is a user LED connected to PE11
|
||||
* User LD8: orange LED is a user LED connected to PE14
|
||||
* User LD9: blue LED is a user LED connected to PE12
|
||||
* User LD10: red LED is a user LED connected to PE13
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
|
||||
* way. The following definitions are used to access individual LEDs.
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
|
||||
* in any way. The following definitions are used to access individual LEDs.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
|
|
@ -105,12 +109,14 @@
|
|||
#define GPIO_LED8 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13)
|
||||
|
||||
/* Button definitions ***************************************************************/
|
||||
/* The STM32F3Discovery supports two buttons; only one button is controllable by
|
||||
* software:
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
/* The STM32F3Discovery supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F303VCT6.
|
||||
* B2 RESET: pushbutton connected to NRST is used to RESET the STM32F303VCT6.
|
||||
* B1 USER: user and wake-up button connected to PA0
|
||||
* B2 RESET: pushbutton connected to NRST is used to RESET
|
||||
* the STM32F303VCT6.
|
||||
*
|
||||
* NOTE that EXTI interrupts are configured
|
||||
*/
|
||||
|
|
@ -139,7 +145,7 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -162,7 +168,8 @@ int stm32_bringup(void);
|
|||
* Name: stm32_spidev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the stm32f3discovery board.
|
||||
* Called to configure SPI chip select GPIO pins for the stm32f3discovery
|
||||
* board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
|
@ -172,8 +179,8 @@ void weak_function stm32_spidev_initialize(void);
|
|||
* Name: stm32_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_usbinitialize very early in inialization to setup USB-related
|
||||
* GPIO pins for the STM32F3Discovery board.
|
||||
* Called from stm32_usbinitialize very early in inialization to setup
|
||||
* USB-related GPIO pins for the STM32F3Discovery board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -176,122 +176,125 @@ int stm32_bringup(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART
|
||||
{
|
||||
int partno;
|
||||
int partsize;
|
||||
int partoffset;
|
||||
int partszbytes;
|
||||
int erasesize;
|
||||
const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST;
|
||||
const char *ptr;
|
||||
FAR struct mtd_dev_s *mtd_part;
|
||||
char partref[4];
|
||||
{
|
||||
int partno;
|
||||
int partsize;
|
||||
int partoffset;
|
||||
int partszbytes;
|
||||
int erasesize;
|
||||
const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST;
|
||||
const char *ptr;
|
||||
FAR struct mtd_dev_s *mtd_part;
|
||||
char partref[4];
|
||||
|
||||
/* Now create a partition on the FLASH device */
|
||||
/* Now create a partition on the FLASH device */
|
||||
|
||||
partno = 0;
|
||||
ptr = partstring;
|
||||
partoffset = 0;
|
||||
partno = 0;
|
||||
ptr = partstring;
|
||||
partoffset = 0;
|
||||
|
||||
/* Get the Flash erase size */
|
||||
/* Get the Flash erase size */
|
||||
|
||||
erasesize = geo.erasesize;
|
||||
erasesize = geo.erasesize;
|
||||
|
||||
while (*ptr != '\0')
|
||||
{
|
||||
/* Get the partition size */
|
||||
while (*ptr != '\0')
|
||||
{
|
||||
/* Get the partition size */
|
||||
|
||||
partsize = atoi(ptr);
|
||||
partszbytes = (partsize << 10); /* partsize is defined in KB */
|
||||
partsize = atoi(ptr);
|
||||
partszbytes = (partsize << 10); /* partsize is defined in KB */
|
||||
|
||||
/* Check if partition size is bigger then erase block */
|
||||
/* Check if partition size is bigger then erase block */
|
||||
|
||||
if (partszbytes < erasesize)
|
||||
{
|
||||
ferr("ERROR: Partition size is lesser than erasesize!\n");
|
||||
return -1;
|
||||
}
|
||||
if (partszbytes < erasesize)
|
||||
{
|
||||
ferr("ERROR: Partition size is lesser than erasesize!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check if partition size is multiple of erase block */
|
||||
/* Check if partition size is multiple of erase block */
|
||||
|
||||
if ((partszbytes % erasesize) != 0)
|
||||
{
|
||||
ferr("ERROR: Partition size is not multiple of erasesize!\n");
|
||||
return -1;
|
||||
}
|
||||
if ((partszbytes % erasesize) != 0)
|
||||
{
|
||||
ferr("ERROR: Partition size is not multiple of"
|
||||
" erasesize!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize);
|
||||
partoffset += partszbytes / erasesize;
|
||||
mtd_part = mtd_partition(mtd, partoffset,
|
||||
partszbytes / erasesize);
|
||||
partoffset += partszbytes / erasesize;
|
||||
|
||||
#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART
|
||||
/* Test if this is the config partition */
|
||||
/* Test if this is the config partition */
|
||||
|
||||
if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno)
|
||||
{
|
||||
/* Register the partition as the config device */
|
||||
if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno)
|
||||
{
|
||||
/* Register the partition as the config device */
|
||||
|
||||
mtdconfig_register(mtd_part);
|
||||
}
|
||||
else
|
||||
mtdconfig_register(mtd_part);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* Now initialize a SMART Flash block device and bind it
|
||||
* to the MTD device.
|
||||
*/
|
||||
{
|
||||
/* Now initialize a SMART Flash block device and bind it
|
||||
* to the MTD device.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS)
|
||||
sprintf(partref, "p%d", partno);
|
||||
smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd_part, partref);
|
||||
sprintf(partref, "p%d", partno);
|
||||
smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR,
|
||||
mtd_part, partref);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MTD_PARTITION_NAMES)
|
||||
/* Set the partition name */
|
||||
/* Set the partition name */
|
||||
|
||||
if (mtd_part == NULL)
|
||||
{
|
||||
ferr("ERROR: failed to create partition %s\n", partname);
|
||||
return -1;
|
||||
}
|
||||
if (mtd_part == NULL)
|
||||
{
|
||||
ferr("ERROR: failed to create partition %s\n", partname);
|
||||
return -1;
|
||||
}
|
||||
|
||||
mtd_setpartitionname(mtd_part, partname);
|
||||
mtd_setpartitionname(mtd_part, partname);
|
||||
|
||||
/* Now skip to next name. We don't need to split the string here
|
||||
* because the MTD partition logic will only display names up to
|
||||
* the comma, thus allowing us to use a single static name
|
||||
* in the code.
|
||||
*/
|
||||
/* Now skip to next name. We don't need to split the string
|
||||
* here because the MTD partition logic will only display names
|
||||
* up to the comma, thus allowing us to use a single static
|
||||
* name in the code.
|
||||
*/
|
||||
|
||||
while (*partname != ',' && *partname != '\0')
|
||||
{
|
||||
/* Skip to next ',' */
|
||||
while (*partname != ',' && *partname != '\0')
|
||||
{
|
||||
/* Skip to next ',' */
|
||||
|
||||
partname++;
|
||||
}
|
||||
partname++;
|
||||
}
|
||||
|
||||
if (*partname == ',')
|
||||
{
|
||||
partname++;
|
||||
}
|
||||
if (*partname == ',')
|
||||
{
|
||||
partname++;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Update the pointer to point to the next size in the list */
|
||||
/* Update the pointer to point to the next size in the list */
|
||||
|
||||
while ((*ptr >= '0') && (*ptr <= '9'))
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
while ((*ptr >= '0') && (*ptr <= '9'))
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
|
||||
if (*ptr == ',')
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
if (*ptr == ',')
|
||||
{
|
||||
ptr++;
|
||||
}
|
||||
|
||||
/* Increment the part number */
|
||||
/* Increment the part number */
|
||||
|
||||
partno++;
|
||||
}
|
||||
}
|
||||
partno++;
|
||||
}
|
||||
}
|
||||
#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */
|
||||
|
||||
/* Configure the device with no partition support */
|
||||
|
|
@ -317,23 +320,27 @@ int stm32_bringup(void)
|
|||
#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD)
|
||||
/* Create a RAM MTD device if configured */
|
||||
|
||||
{
|
||||
uint8_t *start = (uint8_t *) kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024);
|
||||
mtd = rammtd_initialize(start, CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024);
|
||||
mtd->ioctl(mtd, MTDIOC_BULKERASE, 0);
|
||||
{
|
||||
uint8_t *start =
|
||||
(uint8_t *) kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024);
|
||||
mtd = rammtd_initialize(start,
|
||||
CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024);
|
||||
mtd->ioctl(mtd, MTDIOC_BULKERASE, 0);
|
||||
|
||||
/* Now initialize a SMART Flash block device and bind it to the MTD device */
|
||||
/* Now initialize a SMART Flash block device and bind it to the MTD
|
||||
* device
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS)
|
||||
smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL);
|
||||
smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */
|
||||
|
||||
#ifdef HAVE_USBHOST
|
||||
/* Initialize USB host operation. stm32_usbhost_initialize() starts a thread
|
||||
* will monitor for USB connection and disconnection events.
|
||||
/* Initialize USB host operation. stm32_usbhost_initialize() starts a
|
||||
* thread will monitor for USB connection and disconnection events.
|
||||
*/
|
||||
|
||||
ret = stm32_usbhost_initialize();
|
||||
|
|
@ -368,11 +375,11 @@ int stm32_bringup(void)
|
|||
ret = board_l3gd20_initialize(0, 5);
|
||||
if (ret != OK)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor: %d\n", ret);
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor:"
|
||||
" %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_PWM
|
||||
/* Initialize PWM and register the PWM device. */
|
||||
|
||||
|
|
|
|||
|
|
@ -117,15 +117,13 @@
|
|||
|
||||
/* STMPE811 on I2C3 */
|
||||
|
||||
//#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
||||
//#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
||||
|
||||
#define STMPE811_ADDR1 0x41
|
||||
#define STMPE811_ADDR2 0x44
|
||||
|
||||
#define GPIO_IO_EXPANDER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
/* STM32F429 Discovery GPIOs ************************************************/
|
||||
|
||||
/* LEDs */
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
|
|
@ -143,8 +141,8 @@
|
|||
|
||||
/* PWM
|
||||
*
|
||||
* The STM32F429 Discovery has no real on-board PWM devices, but the board can be
|
||||
* configured to output a pulse train using TIM4 CH2 on PD13.
|
||||
* The STM32F429 Discovery has no real on-board PWM devices, but the board
|
||||
* can be configured to output a pulse train using TIM4 CH2 on PD13.
|
||||
*/
|
||||
|
||||
#define STM32F429I_DISCO_PWMTIMER 4
|
||||
|
|
@ -192,8 +190,7 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -297,7 +294,6 @@ void stm32_ledpminitialize(void);
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
* Name: stm32_pmbuttons
|
||||
*
|
||||
* Description:
|
||||
|
|
|
|||
|
|
@ -269,7 +269,6 @@
|
|||
#define GPIO_GS2200M_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN5)
|
||||
|
||||
|
||||
#define GPIO_ENC28J60_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,9 @@
|
|||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* Configuration ****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* How many SPI modules does this chip support? */
|
||||
|
||||
#if STM32_NSPI < 1
|
||||
|
|
@ -64,20 +66,23 @@
|
|||
# undef CONFIG_STM32_SPI3
|
||||
#endif
|
||||
|
||||
/* STM32L-Discovery GPIOs ***************************************************************************/
|
||||
/* The STM32L-Discovery board has four LEDs. Two of these are controlled by logic on the board and
|
||||
* are not available for software control:
|
||||
/* STM32L-Discovery GPIOs ***************************************************/
|
||||
|
||||
/* The STM32L-Discovery board has four LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD2 default status is red. LD2 turns to green to indicate that communications are in
|
||||
* progress between the PC and the ST-LINK/V2.
|
||||
* LD1 COM: LD2 default status is red. LD2 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2.
|
||||
* LD2 PWR: Red LED indicates that the board is powered.
|
||||
*
|
||||
* And two LEDs can be controlled by software:
|
||||
*
|
||||
* User LD3: Green LED is a user LED connected to the I/O PB7 of the STM32L152 MCU.
|
||||
* User LD4: Blue LED is a user LED connected to the I/O PB6 of the STM32L152 MCU.
|
||||
* User LD3: Green LED is a user LED connected to PB7
|
||||
* User LD4: Blue LED is a user LED connected to PB6
|
||||
*
|
||||
* The other side of the LED connects to ground so high value will illuminate the LED.
|
||||
* The other side of the LED connects to ground so high value will illuminate
|
||||
* the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
|
|
@ -85,11 +90,14 @@
|
|||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
|
||||
|
||||
/* Button definitions ****************************************************************************/
|
||||
/* The STM32L-Discovery supports two buttons; only one button is controllable by software:
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
/* The STM32L-Discovery supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F303VCT6.
|
||||
* B2 RESET: pushbutton connected to NRST is used to RESET the STM32F303VCT6.
|
||||
* B1 USER: user and wake-up button connected to PA0
|
||||
* B2 RESET: pushbutton connected to NRST is used to RESET
|
||||
* the STM32F303VCT6.
|
||||
*
|
||||
* NOTE that EXTI interrupts are configured
|
||||
*/
|
||||
|
|
@ -100,10 +108,11 @@
|
|||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTA | GPIO_PIN0)
|
||||
|
||||
/* LCD definitions ****************************************************************************/
|
||||
/* LCD. The STM32L152RBT6 supports either a 4x32 or 8x28. The STM32L-Discovery
|
||||
* has an LCD 24 segments, 4 commons. On that board, LCD pins are mapped as
|
||||
* follows:
|
||||
/* LCD definitions **********************************************************/
|
||||
|
||||
/* LCD. The STM32L152RBT6 supports either a 4x32 or 8x28.
|
||||
* The STM32L-Discovery has an LCD 24 segments, 4 commons. On that board,
|
||||
* LCD pins are mapped as follows:
|
||||
*
|
||||
* The 24 segments are represented by the letters A, B, C, D, E, F, G, H, J,
|
||||
* K, M, N, P, Q, COL (colon), and DP (decimal point)
|
||||
|
|
@ -120,7 +129,8 @@
|
|||
* --------- |_| DP
|
||||
* D
|
||||
*
|
||||
* Plus BAR0-3. The following is of each segment of each of the 6 characters 4 x 24:
|
||||
* Plus BAR0-3. The following is of each segment of each of the 6 characters
|
||||
* 4 x 24:
|
||||
*
|
||||
* ---- ----- ----- ----- ----- ---------------
|
||||
* GPIO COM3 COM2 COM1 COM0 SIGNAL NAME
|
||||
|
|
@ -232,7 +242,7 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -259,7 +269,8 @@ int stm32_bringup(void);
|
|||
* Name: stm32_spidev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the stm32ldiscovery board.
|
||||
* Called to configure SPI chip select GPIO pins for the stm32ldiscovery
|
||||
* board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@
|
|||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* Default MMC/SD SLOT number */
|
||||
|
|
|
|||
|
|
@ -149,7 +149,9 @@ static struct l3gd20_dev_s *g_l3gd20_list = NULL;
|
|||
static void l3gd20_read_register(FAR struct l3gd20_dev_s *dev,
|
||||
uint8_t const reg_addr, uint8_t *reg_data)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the
|
||||
* same time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -185,7 +187,9 @@ static void l3gd20_write_register(FAR struct l3gd20_dev_s *dev,
|
|||
uint8_t const reg_addr,
|
||||
uint8_t const reg_data)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the same
|
||||
* time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -218,7 +222,7 @@ static void l3gd20_reset(FAR struct l3gd20_dev_s *dev)
|
|||
{
|
||||
/* Reboot memory content */
|
||||
|
||||
l3gd20_write_register(dev, L3GD20_CTRL_REG_5, L3GD20_CTRL_REG_5_BOOT_bm);
|
||||
l3gd20_write_register(dev, L3GD20_CTRL_REG_5, L3GD20_CTRL_REG_5_BOOT_BM);
|
||||
|
||||
up_mdelay(100);
|
||||
}
|
||||
|
|
@ -275,7 +279,9 @@ static void l3gd20_read_gyroscope_data(FAR struct l3gd20_dev_s *dev,
|
|||
uint16_t * x_gyr, uint16_t * y_gyr,
|
||||
uint16_t * z_gyr)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the same
|
||||
* time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -316,7 +322,9 @@ static void l3gd20_read_gyroscope_data(FAR struct l3gd20_dev_s *dev,
|
|||
static void l3gd20_read_temperature(FAR struct l3gd20_dev_s *dev,
|
||||
FAR uint8_t *temperature)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the same
|
||||
* time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -367,8 +375,8 @@ static int l3gd20_interrupt_handler(int irq, FAR void *context,
|
|||
}
|
||||
|
||||
/* Task the worker with retrieving the latest sensor data. We should not do
|
||||
* this in a interrupt since it might take too long. Also we cannot lock the
|
||||
* SPI bus from within an interrupt.
|
||||
* this in a interrupt since it might take too long. Also we cannot lock
|
||||
* the SPI bus from within an interrupt.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(priv->work.worker == NULL);
|
||||
|
|
@ -419,7 +427,7 @@ static int l3gd20_open(FAR struct file *filep)
|
|||
|
||||
l3gd20_write_register(priv,
|
||||
L3GD20_CTRL_REG_3,
|
||||
L3GD20_CTRL_REG_3_I2_DRDY_bm);
|
||||
L3GD20_CTRL_REG_3_I2_DRDY_BM);
|
||||
|
||||
/* Enable the maximum full scale mode.
|
||||
* Enable block data update for gyro sensor data.
|
||||
|
|
@ -428,9 +436,9 @@ static int l3gd20_open(FAR struct file *filep)
|
|||
|
||||
l3gd20_write_register(priv,
|
||||
L3GD20_CTRL_REG_4,
|
||||
L3GD20_CTRL_REG_4_BDU_bm |
|
||||
L3GD20_CTRL_REG_4_FS_1_bm |
|
||||
L3GD20_CTRL_REG_4_FS_0_bm);
|
||||
L3GD20_CTRL_REG_4_BDU_BM |
|
||||
L3GD20_CTRL_REG_4_FS_1_BM |
|
||||
L3GD20_CTRL_REG_4_FS_0_BM);
|
||||
|
||||
/* Enable X,Y,Z axis
|
||||
* DR=00 -> Output data rate = 95 Hz, Cut-off = 12.5
|
||||
|
|
@ -438,10 +446,10 @@ static int l3gd20_open(FAR struct file *filep)
|
|||
|
||||
l3gd20_write_register(priv,
|
||||
L3GD20_CTRL_REG_1,
|
||||
L3GD20_CTRL_REG_1_POWERDOWN_bm |
|
||||
L3GD20_CTRL_REG_1_X_EN_bm |
|
||||
L3GD20_CTRL_REG_1_Y_EN_bm |
|
||||
L3GD20_CTRL_REG_1_Z_EN_bm);
|
||||
L3GD20_CTRL_REG_1_POWERDOWN_BM |
|
||||
L3GD20_CTRL_REG_1_X_EN_BM |
|
||||
L3GD20_CTRL_REG_1_Y_EN_BM |
|
||||
L3GD20_CTRL_REG_1_Z_EN_BM);
|
||||
|
||||
/* Read measurement data to ensure DRDY is low */
|
||||
|
||||
|
|
@ -505,7 +513,8 @@ static ssize_t l3gd20_read(FAR struct file *filep, FAR char *buffer,
|
|||
|
||||
if (buflen < sizeof(FAR struct l3gd20_sensor_data_s))
|
||||
{
|
||||
snerr("ERROR: Not enough memory for reading out a sensor data sample\n");
|
||||
snerr("ERROR: Not enough memory for reading out a sensor data"
|
||||
" sample\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -145,7 +145,9 @@ static struct lis3dsh_dev_s *g_lis3dsh_list = NULL;
|
|||
static void lis3dsh_read_register(FAR struct lis3dsh_dev_s *dev,
|
||||
uint8_t const reg_addr, uint8_t * reg_data)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the same
|
||||
* time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -181,7 +183,9 @@ static void lis3dsh_write_register(FAR struct lis3dsh_dev_s *dev,
|
|||
uint8_t const reg_addr,
|
||||
uint8_t const reg_data)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the same
|
||||
* time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -212,7 +216,8 @@ static void lis3dsh_write_register(FAR struct lis3dsh_dev_s *dev,
|
|||
|
||||
static void lis3dsh_reset(FAR struct lis3dsh_dev_s *dev)
|
||||
{
|
||||
lis3dsh_write_register(dev, LIS3DSH_CTRL_REG_6, LIS3DSH_CTRL_REG_6_BOOT_bm);
|
||||
lis3dsh_write_register(dev, LIS3DSH_CTRL_REG_6,
|
||||
LIS3DSH_CTRL_REG_6_BOOT_BM);
|
||||
|
||||
up_mdelay(100);
|
||||
}
|
||||
|
|
@ -261,10 +266,13 @@ static void lis3dsh_read_measurement_data(FAR struct lis3dsh_dev_s *dev)
|
|||
****************************************************************************/
|
||||
|
||||
static void lis3dsh_read_acclerometer_data(FAR struct lis3dsh_dev_s *dev,
|
||||
uint16_t * x_acc, uint16_t * y_acc,
|
||||
uint16_t * x_acc,
|
||||
uint16_t * y_acc,
|
||||
uint16_t * z_acc)
|
||||
{
|
||||
/* Lock the SPI bus so that only one device can access it at the same time */
|
||||
/* Lock the SPI bus so that only one device can access it at the same
|
||||
* time
|
||||
*/
|
||||
|
||||
SPI_LOCK(dev->spi, true);
|
||||
|
||||
|
|
@ -272,8 +280,8 @@ static void lis3dsh_read_acclerometer_data(FAR struct lis3dsh_dev_s *dev,
|
|||
|
||||
SPI_SELECT(dev->spi, dev->config->spi_devid, true);
|
||||
|
||||
/* Transmit the register address from where we want to start reading 0x80 ->
|
||||
* MSB is set -> Read Indication.
|
||||
/* Transmit the register address from where we want to start reading
|
||||
* 0x80 -> MSB is set -> Read Indication.
|
||||
*/
|
||||
|
||||
SPI_SEND(dev->spi, (LIS3DSH_OUT_X_L_REG | 0x80));
|
||||
|
|
@ -305,8 +313,8 @@ static void lis3dsh_read_acclerometer_data(FAR struct lis3dsh_dev_s *dev,
|
|||
static int lis3dsh_interrupt_handler(int irq, FAR void *context,
|
||||
FAR void *arg)
|
||||
{
|
||||
/* This function should be called upon a rising edge on the LIS3DSH new data
|
||||
* interrupt pin since it signals that new data has been measured.
|
||||
/* This function should be called upon a rising edge on the LIS3DSH new
|
||||
* data interrupt pin since it signals that new data has been measured.
|
||||
*/
|
||||
|
||||
FAR struct lis3dsh_dev_s *priv = NULL;
|
||||
|
|
@ -323,8 +331,8 @@ static int lis3dsh_interrupt_handler(int irq, FAR void *context,
|
|||
DEBUGASSERT(priv != NULL);
|
||||
|
||||
/* Task the worker with retrieving the latest sensor data. We should not do
|
||||
* this in a interrupt since it might take too long. Also we cannot lock the
|
||||
* SPI bus from within an interrupt.
|
||||
* this in a interrupt since it might take too long. Also we cannot lock
|
||||
* the SPI bus from within an interrupt.
|
||||
*/
|
||||
|
||||
if (work_available(&priv->work))
|
||||
|
|
@ -372,52 +380,57 @@ static int lis3dsh_open(FAR struct file *filep)
|
|||
/* Enable - the full scale range (FS = +/- 16 g) */
|
||||
|
||||
lis3dsh_write_register(priv,
|
||||
LIS3DSH_CTRL_REG_5, LIS3DSH_CTRL_REG_5_FSCALE_2_bm);
|
||||
LIS3DSH_CTRL_REG_5, LIS3DSH_CTRL_REG_5_FSCALE_2_BM);
|
||||
|
||||
/* Enable - Auto increment of address when reading multiple bytes */
|
||||
|
||||
lis3dsh_write_register(priv,
|
||||
LIS3DSH_CTRL_REG_6, LIS3DSH_CTRL_REG_6_ADD_INC_bm);
|
||||
LIS3DSH_CTRL_REG_6, LIS3DSH_CTRL_REG_6_ADD_INC_BM);
|
||||
|
||||
/* Enable - Measurement of X-, Y-, and Z-axis - Block data update for
|
||||
* accelerating data This should prevent race conditions when reading sensor
|
||||
* data - fastest output data rate (ODR = 1600 Hz).
|
||||
* accelerating data This should prevent race conditions when reading
|
||||
* sensor data - fastest output data rate (ODR = 1600 Hz).
|
||||
*/
|
||||
|
||||
lis3dsh_write_register(priv,
|
||||
LIS3DSH_CTRL_REG_4,
|
||||
LIS3DSH_CTRL_REG_4_XEN_bm | LIS3DSH_CTRL_REG_4_YEN_bm |
|
||||
LIS3DSH_CTRL_REG_4_ZEN_bm | LIS3DSH_CTRL_REG_4_BDU_bm |
|
||||
LIS3DSH_CTRL_REG_4_ODR_3_bm | LIS3DSH_CTRL_REG_4_ODR_0_bm);
|
||||
LIS3DSH_CTRL_REG_4_XEN_BM |
|
||||
LIS3DSH_CTRL_REG_4_YEN_BM |
|
||||
LIS3DSH_CTRL_REG_4_ZEN_BM |
|
||||
LIS3DSH_CTRL_REG_4_BDU_BM |
|
||||
LIS3DSH_CTRL_REG_4_ODR_3_BM |
|
||||
LIS3DSH_CTRL_REG_4_ODR_0_BM);
|
||||
|
||||
/* Enable - DRDY signal enable to INT 1 */
|
||||
|
||||
lis3dsh_write_register(priv,
|
||||
LIS3DSH_CTRL_REG_3,
|
||||
LIS3DSH_CTRL_REG_3_DR_EN_bm | LIS3DSH_CTRL_REG_3_IEA_bm |
|
||||
LIS3DSH_CTRL_REG_3_IEL_bm | LIS3DSH_CTRL_REG_3_INT1_EN_bm);
|
||||
LIS3DSH_CTRL_REG_3_DR_EN_BM |
|
||||
LIS3DSH_CTRL_REG_3_IEA_BM |
|
||||
LIS3DSH_CTRL_REG_3_IEL_BM |
|
||||
LIS3DSH_CTRL_REG_3_INT1_EN_BM);
|
||||
|
||||
/* Read back the content of all control registers for debug purposes */
|
||||
|
||||
#ifdef CONFIG_DEBUG_SENSORS_INFO
|
||||
{
|
||||
uint8_t reg_content = 0;
|
||||
{
|
||||
uint8_t reg_content = 0;
|
||||
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_1, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_1 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_2, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_2 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_3, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_3 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_4, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_4 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_5, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_5 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_6, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_6 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_STATUS_REG, ®_content);
|
||||
sninfo("STATUS_REG = %04x\n", reg_content);
|
||||
}
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_1, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_1 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_2, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_2 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_3, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_3 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_4, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_4 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_5, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_5 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_CTRL_REG_6, ®_content);
|
||||
sninfo("LIS3DSH_CTRL_REG_6 = %04x\n", reg_content);
|
||||
lis3dsh_read_register(priv, LIS3DSH_STATUS_REG, ®_content);
|
||||
sninfo("STATUS_REG = %04x\n", reg_content);
|
||||
}
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
|
|
@ -459,7 +472,8 @@ static ssize_t lis3dsh_read(FAR struct file *filep, FAR char *buffer,
|
|||
|
||||
if (buflen < sizeof(FAR struct lis3dsh_sensor_data_s))
|
||||
{
|
||||
snerr("ERROR: Not enough memory for reading out a sensor data sample\n");
|
||||
snerr("ERROR: Not enough memory for reading out a sensor data"
|
||||
" sample\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
|
|
@ -553,7 +567,8 @@ int lis3dsh_register(FAR const char *devpath, FAR struct spi_dev_s *spi,
|
|||
|
||||
/* Initialize the LIS3DSH device structure */
|
||||
|
||||
priv = (FAR struct lis3dsh_dev_s *)kmm_malloc(sizeof(struct lis3dsh_dev_s));
|
||||
priv =
|
||||
(FAR struct lis3dsh_dev_s *)kmm_malloc(sizeof(struct lis3dsh_dev_s));
|
||||
if (priv == NULL)
|
||||
{
|
||||
snerr("ERROR: Failed to allocate instance\n");
|
||||
|
|
|
|||
|
|
@ -51,12 +51,15 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* SPI BUS PARAMETERS ********************************************************/
|
||||
/* SPI BUS PARAMETERS *******************************************************/
|
||||
|
||||
#define L3GD20_SPI_FREQUENCY (4000000) /* 4 MHz */
|
||||
#define L3GD20_SPI_MODE (SPIDEV_MODE3) /* Device uses SPI Mode 3: CPOL=1, CPHA=1 *
|
||||
#define L3GD20_SPI_MODE (SPIDEV_MODE3) /* Device uses SPI Mode 3:
|
||||
* CPOL=1, CPHA=1
|
||||
*/
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Gyroscope registers */
|
||||
|
||||
#define L3GD20_WHO_AM_I 0x0F /* Accelerometer and gyroscope device identification */
|
||||
|
|
@ -94,81 +97,80 @@
|
|||
|
||||
/* Gyroscope control register 1 */
|
||||
|
||||
#define L3GD20_CTRL_REG_1_X_EN_bm (1 << 0)
|
||||
#define L3GD20_CTRL_REG_1_Y_EN_bm (1 << 1)
|
||||
#define L3GD20_CTRL_REG_1_Z_EN_bm (1 << 2)
|
||||
#define L3GD20_CTRL_REG_1_POWERDOWN_bm (1 << 3)
|
||||
#define L3GD20_CTRL_REG_1_BW_0_bm (1 << 4)
|
||||
#define L3GD20_CTRL_REG_1_BW_1_bm (1 << 5)
|
||||
#define L3GD20_CTRL_REG_1_DR_0_bm (1 << 6)
|
||||
#define L3GD20_CTRL_REG_1_DR_1_bm (1 << 7)
|
||||
#define L3GD20_CTRL_REG_1_X_EN_BM (1 << 0)
|
||||
#define L3GD20_CTRL_REG_1_Y_EN_BM (1 << 1)
|
||||
#define L3GD20_CTRL_REG_1_Z_EN_BM (1 << 2)
|
||||
#define L3GD20_CTRL_REG_1_POWERDOWN_BM (1 << 3)
|
||||
#define L3GD20_CTRL_REG_1_BW_0_BM (1 << 4)
|
||||
#define L3GD20_CTRL_REG_1_BW_1_BM (1 << 5)
|
||||
#define L3GD20_CTRL_REG_1_DR_0_BM (1 << 6)
|
||||
#define L3GD20_CTRL_REG_1_DR_1_BM (1 << 7)
|
||||
|
||||
/* Gyroscope control register 2 */
|
||||
|
||||
#define L3GD20_CTRL_REG_2_HPCF_0_bm (1 << 0)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_1_bm (1 << 1)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_2_bm (1 << 2)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_3_bm (1 << 3)
|
||||
#define L3GD20_CTRL_REG_2_HPM_0_bm (1 << 4)
|
||||
#define L3GD20_CTRL_REG_2_HPM_1_bm (1 << 5)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_0_BM (1 << 0)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_1_BM (1 << 1)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_2_BM (1 << 2)
|
||||
#define L3GD20_CTRL_REG_2_HPCF_3_BM (1 << 3)
|
||||
#define L3GD20_CTRL_REG_2_HPM_0_BM (1 << 4)
|
||||
#define L3GD20_CTRL_REG_2_HPM_1_BM (1 << 5)
|
||||
#define L3GD20_CTRL_REG_2_RES6_ (1 << 6)
|
||||
#define L3GD20_CTRL_REG_2_RES7_ (1 << 7)
|
||||
|
||||
/* Gyroscope control register 3 */
|
||||
|
||||
#define L3GD20_CTRL_REG_3_I2_EMPTY_bm (1 << 0)
|
||||
#define L3GD20_CTRL_REG_3_I2_ORUN_bm (1 << 1)
|
||||
#define L3GD20_CTRL_REG_3_I2_WTM_bm (1 << 2)
|
||||
#define L3GD20_CTRL_REG_3_I2_DRDY_bm (1 << 3)
|
||||
#define L3GD20_CTRL_REG_3_PP_OD_bm (1 << 4)
|
||||
#define L3GD20_CTRL_REG_3_H_LACTIVE_bm (1 << 5)
|
||||
#define L3GD20_CTRL_REG_3_I1_BOOT_bm (1 << 6)
|
||||
#define L3GD20_CTRL_REG_3_I1_INT1_bm (1 << 7)
|
||||
|
||||
#define L3GD20_CTRL_REG_3_I2_EMPTY_BM (1 << 0)
|
||||
#define L3GD20_CTRL_REG_3_I2_ORUN_BM (1 << 1)
|
||||
#define L3GD20_CTRL_REG_3_I2_WTM_BM (1 << 2)
|
||||
#define L3GD20_CTRL_REG_3_I2_DRDY_BM (1 << 3)
|
||||
#define L3GD20_CTRL_REG_3_PP_OD_BM (1 << 4)
|
||||
#define L3GD20_CTRL_REG_3_H_LACTIVE_BM (1 << 5)
|
||||
#define L3GD20_CTRL_REG_3_I1_BOOT_BM (1 << 6)
|
||||
#define L3GD20_CTRL_REG_3_I1_INT1_BM (1 << 7)
|
||||
|
||||
/* Gyroscope control register 4 */
|
||||
|
||||
#define L3GD20_CTRL_REG_4_SIM_bm (1 << 0)
|
||||
#define L3GD20_CTRL_REG_4_SIM_BM (1 << 0)
|
||||
#define L3GD20_CTRL_REG_4_RES1_ (1 << 1)
|
||||
#define L3GD20_CTRL_REG_4_RES2_ (1 << 2)
|
||||
#define L3GD20_CTRL_REG_4_RES3_ (1 << 3)
|
||||
#define L3GD20_CTRL_REG_4_FS_0_bm (1 << 4)
|
||||
#define L3GD20_CTRL_REG_4_FS_1_bm (1 << 5)
|
||||
#define L3GD20_CTRL_REG_4_BLE_bm (1 << 6)
|
||||
#define L3GD20_CTRL_REG_4_BDU_bm (1 << 7)
|
||||
#define L3GD20_CTRL_REG_4_FS_0_BM (1 << 4)
|
||||
#define L3GD20_CTRL_REG_4_FS_1_BM (1 << 5)
|
||||
#define L3GD20_CTRL_REG_4_BLE_BM (1 << 6)
|
||||
#define L3GD20_CTRL_REG_4_BDU_BM (1 << 7)
|
||||
|
||||
/* Gyroscope control register 5 */
|
||||
|
||||
#define L3GD20_CTRL_REG_5_OUT_SEL_0_bm (1 << 0)
|
||||
#define L3GD20_CTRL_REG_5_OUT_SEL_1_bm (1 << 1)
|
||||
#define L3GD20_CTRL_REG_5_INT1_SEL_0_bm (1 << 2)
|
||||
#define L3GD20_CTRL_REG_5_INT1_SEL_1_bm (1 << 3)
|
||||
#define L3GD20_CTRL_REG_5_HP_EN_bm (1 << 4)
|
||||
#define L3GD20_CTRL_REG_5_OUT_SEL_0_BM (1 << 0)
|
||||
#define L3GD20_CTRL_REG_5_OUT_SEL_1_BM (1 << 1)
|
||||
#define L3GD20_CTRL_REG_5_INT1_SEL_0_BM (1 << 2)
|
||||
#define L3GD20_CTRL_REG_5_INT1_SEL_1_BM (1 << 3)
|
||||
#define L3GD20_CTRL_REG_5_HP_EN_BM (1 << 4)
|
||||
#define L3GD20_CTRL_REG_5_RES5_ (1 << 5)
|
||||
#define L3GD20_CTRL_REG_5_FIFO_EN_bm (1 << 6)
|
||||
#define L3GD20_CTRL_REG_5_BOOT_bm (1 << 7)
|
||||
#define L3GD20_CTRL_REG_5_FIFO_EN_BM (1 << 6)
|
||||
#define L3GD20_CTRL_REG_5_BOOT_BM (1 << 7)
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define L3GD20_STATUS_REG_X_DA_bm (1 << 0)
|
||||
#define L3GD20_STATUS_REG_Y_DA_bm (1 << 1)
|
||||
#define L3GD20_STATUS_REG_Z_DA_bm (1 << 2)
|
||||
#define L3GD20_STATUS_REG_ZYX_DA_bm (1 << 3)
|
||||
#define L3GD20_STATUS_REG_X_OR_bm (1 << 4)
|
||||
#define L3GD20_STATUS_REG_Y_OR_bm (1 << 5)
|
||||
#define L3GD20_STATUS_REG_Z_OR_bm (1 << 6)
|
||||
#define L3GD20_STATUS_REG_ZYX_OR_bm (1 << 7)
|
||||
#define L3GD20_STATUS_REG_X_DA_BM (1 << 0)
|
||||
#define L3GD20_STATUS_REG_Y_DA_BM (1 << 1)
|
||||
#define L3GD20_STATUS_REG_Z_DA_BM (1 << 2)
|
||||
#define L3GD20_STATUS_REG_ZYX_DA_BM (1 << 3)
|
||||
#define L3GD20_STATUS_REG_X_OR_BM (1 << 4)
|
||||
#define L3GD20_STATUS_REG_Y_OR_BM (1 << 5)
|
||||
#define L3GD20_STATUS_REG_Z_OR_BM (1 << 6)
|
||||
#define L3GD20_STATUS_REG_ZYX_OR_BM (1 << 7)
|
||||
|
||||
/* FIFO control register */
|
||||
|
||||
#define L3GD20_FIFO_CTRL_WTM_0_bm (1 << 0)
|
||||
#define L3GD20_FIFO_CTRL_WTM_1_bm (1 << 1)
|
||||
#define L3GD20_FIFO_CTRL_WTM_2_bm (1 << 2)
|
||||
#define L3GD20_FIFO_CTRL_WTM_3_bm (1 << 3)
|
||||
#define L3GD20_FIFO_CTRL_WTM_4_bm (1 << 4)
|
||||
#define L3GD20_FIFO_CTRL_FM_0_bm (1 << 5)
|
||||
#define L3GD20_FIFO_CTRL_FM_1_bm (1 << 6)
|
||||
#define L3GD20_FIFO_CTRL_FM_2_bm (1 << 7)
|
||||
#define L3GD20_FIFO_CTRL_WTM_0_BM (1 << 0)
|
||||
#define L3GD20_FIFO_CTRL_WTM_1_BM (1 << 1)
|
||||
#define L3GD20_FIFO_CTRL_WTM_2_BM (1 << 2)
|
||||
#define L3GD20_FIFO_CTRL_WTM_3_BM (1 << 3)
|
||||
#define L3GD20_FIFO_CTRL_WTM_4_BM (1 << 4)
|
||||
#define L3GD20_FIFO_CTRL_FM_0_BM (1 << 5)
|
||||
#define L3GD20_FIFO_CTRL_FM_1_BM (1 << 6)
|
||||
#define L3GD20_FIFO_CTRL_FM_2_BM (1 << 7)
|
||||
#define L3GD20_FIFO_CTRL_FMODE_BYPASS (0)
|
||||
#define L3GD20_FIFO_CTRL_FMODE_FIFO (L3GD20_FIFO_CTRL_FM0)
|
||||
#define L3GD20_FIFO_CTRL_FMODE_CONT (L3GD20_FIFO_CTRL_FM1)
|
||||
|
|
@ -177,36 +179,35 @@
|
|||
|
||||
/* FIFO status control register */
|
||||
|
||||
#define L3GD20_FIFO_SRC_FSS_0_bm (1 << 0)
|
||||
#define L3GD20_FIFO_SRC_FSS_1_bm (1 << 1)
|
||||
#define L3GD20_FIFO_SRC_FSS_2_bm (1 << 2)
|
||||
#define L3GD20_FIFO_SRC_FSS_3_bm (1 << 3)
|
||||
#define L3GD20_FIFO_SRC_FSS_4_bm (1 << 4)
|
||||
#define L3GD20_FIFO_SRC_EMPTY_bm (1 << 5)
|
||||
#define L3GD20_FIFO_SRC_OVRUN_bm (1 << 6)
|
||||
#define L3GD20_FIFO_SRC_WTM_bm (1 << 7)
|
||||
#define L3GD20_FIFO_SRC_FSS_0_BM (1 << 0)
|
||||
#define L3GD20_FIFO_SRC_FSS_1_BM (1 << 1)
|
||||
#define L3GD20_FIFO_SRC_FSS_2_BM (1 << 2)
|
||||
#define L3GD20_FIFO_SRC_FSS_3_BM (1 << 3)
|
||||
#define L3GD20_FIFO_SRC_FSS_4_BM (1 << 4)
|
||||
#define L3GD20_FIFO_SRC_EMPTY_BM (1 << 5)
|
||||
#define L3GD20_FIFO_SRC_OVRUN_BM (1 << 6)
|
||||
#define L3GD20_FIFO_SRC_WTM_BM (1 << 7)
|
||||
|
||||
/* Gyroscope interrupt configuration */
|
||||
|
||||
#define L3GD20_INT_GEN_CFG_X_L_IE_bm (1 << 0)
|
||||
#define L3GD20_INT_GEN_CFG_X_H_IE_bm (1 << 1)
|
||||
#define L3GD20_INT_GEN_CFG_Y_L_IE_bm (1 << 2)
|
||||
#define L3GD20_INT_GEN_CFG_Y_H_IE_bm (1 << 3)
|
||||
#define L3GD20_INT_GEN_CFG_Z_L_IE_bm (1 << 4)
|
||||
#define L3GD20_INT_GEN_CFG_Z_H_IE_bm (1 << 5)
|
||||
#define L3GD20_INT_GEN_CFG_LIR_bm (1 << 6)
|
||||
#define L3GD20_INT_GEN_CFG_AOI_bm (1 << 7)
|
||||
|
||||
#define L3GD20_INT_GEN_CFG_X_L_IE_BM (1 << 0)
|
||||
#define L3GD20_INT_GEN_CFG_X_H_IE_BM (1 << 1)
|
||||
#define L3GD20_INT_GEN_CFG_Y_L_IE_BM (1 << 2)
|
||||
#define L3GD20_INT_GEN_CFG_Y_H_IE_BM (1 << 3)
|
||||
#define L3GD20_INT_GEN_CFG_Z_L_IE_BM (1 << 4)
|
||||
#define L3GD20_INT_GEN_CFG_Z_H_IE_BM (1 << 5)
|
||||
#define L3GD20_INT_GEN_CFG_LIR_BM (1 << 6)
|
||||
#define L3GD20_INT_GEN_CFG_AOI_BM (1 << 7)
|
||||
|
||||
/* Gyroscope interrupt source */
|
||||
|
||||
#define L3GD20_INT_GEN_SRC_X_L_bm (1 << 0)
|
||||
#define L3GD20_INT_GEN_SRC_X_H_bm (1 << 1)
|
||||
#define L3GD20_INT_GEN_SRC_Y_L_bm (1 << 2)
|
||||
#define L3GD20_INT_GEN_SRC_Y_H_bm (1 << 3)
|
||||
#define L3GD20_INT_GEN_SRC_Z_L_bm (1 << 4)
|
||||
#define L3GD20_INT_GEN_SRC_Z_H_bm (1 << 5)
|
||||
#define L3GD20_INT_GEN_SRC_I_A_bm (1 << 6)
|
||||
#define L3GD20_INT_GEN_SRC_X_L_BM (1 << 0)
|
||||
#define L3GD20_INT_GEN_SRC_X_H_BM (1 << 1)
|
||||
#define L3GD20_INT_GEN_SRC_Y_L_BM (1 << 2)
|
||||
#define L3GD20_INT_GEN_SRC_Y_H_BM (1 << 3)
|
||||
#define L3GD20_INT_GEN_SRC_Z_L_BM (1 << 4)
|
||||
#define L3GD20_INT_GEN_SRC_Z_H_BM (1 << 5)
|
||||
#define L3GD20_INT_GEN_SRC_I_A_BM (1 << 6)
|
||||
#define L3GD20_INT_GEN_SRC_RES7_ (1 << 7)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* LIS3DSH Register Definitions **********************************************/
|
||||
/* LIS3DSH Register Definitions *********************************************/
|
||||
|
||||
#define LIS3DSH_INFO_REG_1 (0x0D)
|
||||
#define LIS3DSH_INFO_REG_2 (0x0E)
|
||||
|
|
@ -153,48 +153,48 @@
|
|||
#define LIS3DSH_TC2_REG_1 (0x7D)
|
||||
#define LIS3DSH_TC2_REG_2 (0x7E)
|
||||
|
||||
/* LIS3DSH CTRL_REG_3 Definitions **********************************************/
|
||||
/* LIS3DSH CTRL_REG_3 Definitions *******************************************/
|
||||
|
||||
#define LIS3DSH_CTRL_REG_3_DR_EN_bm (1<<7) /* DRDY signal enable to INT 1 */
|
||||
#define LIS3DSH_CTRL_REG_3_IEA_bm (1<<6) /* Interrupt signal polarity */
|
||||
#define LIS3DSH_CTRL_REG_3_IEL_bm (1<<5) /* Interrupt signal latching */
|
||||
#define LIS3DSH_CTRL_REG_3_INT2_EN_bm (1<<4) /* Interrupt 2 enable / disable */
|
||||
#define LIS3DSH_CTRL_REG_3_INT1_EN_bm (1<<3) /* Interrupt 1 enable / disable */
|
||||
#define LIS3DSH_CTRL_REG_3_VFILT_bm (1<<2) /* Vector filter enable / disable */
|
||||
#define LIS3DSH_CTRL_REG_3_STRT_bm (1<<0) /* Enable soft reset */
|
||||
#define LIS3DSH_CTRL_REG_3_DR_EN_BM (1<<7) /* DRDY signal enable to INT 1 */
|
||||
#define LIS3DSH_CTRL_REG_3_IEA_BM (1<<6) /* Interrupt signal polarity */
|
||||
#define LIS3DSH_CTRL_REG_3_IEL_BM (1<<5) /* Interrupt signal latching */
|
||||
#define LIS3DSH_CTRL_REG_3_INT2_EN_BM (1<<4) /* Interrupt 2 enable / disable */
|
||||
#define LIS3DSH_CTRL_REG_3_INT1_EN_BM (1<<3) /* Interrupt 1 enable / disable */
|
||||
#define LIS3DSH_CTRL_REG_3_VFILT_BM (1<<2) /* Vector filter enable / disable */
|
||||
#define LIS3DSH_CTRL_REG_3_STRT_BM (1<<0) /* Enable soft reset */
|
||||
|
||||
/* LIS3DSH CTRL_REG_4 Definitions **********************************************/
|
||||
/* LIS3DSH CTRL_REG_4 Definitions *******************************************/
|
||||
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_3_bm (1<<7) /* Output data rate and power mode selection bit 3 */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_2_bm (1<<6) /* Output data rate and power mode selection bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_1_bm (1<<5) /* Output data rate and power mode selection bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_0_bm (1<<4) /* Output data rate and power mode selection bit 0 */
|
||||
#define LIS3DSH_CTRL_REG_4_BDU_bm (1<<3) /* Enable block data update for accelerating data */
|
||||
#define LIS3DSH_CTRL_REG_4_ZEN_bm (1<<2) /* Enable Z-axis */
|
||||
#define LIS3DSH_CTRL_REG_4_YEN_bm (1<<1) /* Enable Y-axis */
|
||||
#define LIS3DSH_CTRL_REG_4_XEN_bm (1<<0) /* Enable X-axis */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_3_BM (1<<7) /* Output data rate and power mode selection bit 3 */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_2_BM (1<<6) /* Output data rate and power mode selection bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_1_BM (1<<5) /* Output data rate and power mode selection bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_4_ODR_0_BM (1<<4) /* Output data rate and power mode selection bit 0 */
|
||||
#define LIS3DSH_CTRL_REG_4_BDU_BM (1<<3) /* Enable block data update for accelerating data */
|
||||
#define LIS3DSH_CTRL_REG_4_ZEN_BM (1<<2) /* Enable Z-axis */
|
||||
#define LIS3DSH_CTRL_REG_4_YEN_BM (1<<1) /* Enable Y-axis */
|
||||
#define LIS3DSH_CTRL_REG_4_XEN_BM (1<<0) /* Enable X-axis */
|
||||
|
||||
/* LIS3DSH CTRL_REG_5 Definitions **********************************************/
|
||||
/* LIS3DSH CTRL_REG_5 Definitions *******************************************/
|
||||
|
||||
#define LIS3DSH_CTRL_REG_5_BW_2_bm (1<<7) /* Anti-aliasing filter bandwidth bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_5_BW_1_bm (1<<6) /* Anti-aliasing filter bandwidth bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_5_FSCALE_2_bm (1<<5) /* Full-scale selection bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_5_FSCALE_1_bm (1<<4) /* Full-scale selection bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_5_FSCALE_0_bm (1<<3) /* Full-scale selection bit 0 */
|
||||
#define LIS3DSH_CTRL_REG_5_ST_2_bm (1<<2) /* Enable self-test bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_5_ST_1_bm (1<<1) /* Enable self-test bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_5_SIM_bm (1<<0) /* Enable SPI 4-wire interface */
|
||||
#define LIS3DSH_CTRL_REG_5_BW_2_BM (1<<7) /* Anti-aliasing filter bandwidth bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_5_BW_1_BM (1<<6) /* Anti-aliasing filter bandwidth bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_5_FSCALE_2_BM (1<<5) /* Full-scale selection bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_5_FSCALE_1_BM (1<<4) /* Full-scale selection bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_5_FSCALE_0_BM (1<<3) /* Full-scale selection bit 0 */
|
||||
#define LIS3DSH_CTRL_REG_5_ST_2_BM (1<<2) /* Enable self-test bit 2 */
|
||||
#define LIS3DSH_CTRL_REG_5_ST_1_BM (1<<1) /* Enable self-test bit 1 */
|
||||
#define LIS3DSH_CTRL_REG_5_SIM_BM (1<<0) /* Enable SPI 4-wire interface */
|
||||
|
||||
/* LIS3DSH CTRL_REG_6 Definitions **********************************************/
|
||||
/* LIS3DSH CTRL_REG_6 Definitions *******************************************/
|
||||
|
||||
#define LIS3DSH_CTRL_REG_6_BOOT_bm (1<<7) /* Force reboot, cleared as soon as the reboot is finished. Active high */
|
||||
#define LIS3DSH_CTRL_REG_6_FIFO_EN_bm (1<<6) /* Enable FIFO */
|
||||
#define LIS3DSH_CTRL_REG_6_WTM_EN_bm (1<<5) /* Enable FIFO watermark level use */
|
||||
#define LIS3DSH_CTRL_REG_6_ADD_INC_bm (1<<4) /* Register address automatically incremented during a multiple byte access with a serial interface */
|
||||
#define LIS3DSH_CTRL_REG_6_P1_EMPTY_bm (1<<3) /* Enable FIFO empty indication on Int1 */
|
||||
#define LIS3DSH_CTRL_REG_6_P1_WTM_bm (1<<2) /* FIFO watermark interrupt Int1 */
|
||||
#define LIS3DSH_CTRL_REG_6_P1_OVERRUN_bm (1<<1) /* FIFO overrun interrupt on Int1 */
|
||||
#define LIS3DSH_CTRL_REG_6_P2_BOOT_bm (1<<0) /* BOOT interrupt on Int2 */
|
||||
#define LIS3DSH_CTRL_REG_6_BOOT_BM (1<<7) /* Force reboot, cleared as soon as the reboot is finished. Active high */
|
||||
#define LIS3DSH_CTRL_REG_6_FIFO_EN_BM (1<<6) /* Enable FIFO */
|
||||
#define LIS3DSH_CTRL_REG_6_WTM_EN_BM (1<<5) /* Enable FIFO watermark level use */
|
||||
#define LIS3DSH_CTRL_REG_6_ADD_INC_BM (1<<4) /* Register address automatically incremented during a multiple byte access with a serial interface */
|
||||
#define LIS3DSH_CTRL_REG_6_P1_EMPTY_BM (1<<3) /* Enable FIFO empty indication on Int1 */
|
||||
#define LIS3DSH_CTRL_REG_6_P1_WTM_BM (1<<2) /* FIFO watermark interrupt Int1 */
|
||||
#define LIS3DSH_CTRL_REG_6_P1_OVERRUN_BM (1<<1) /* FIFO overrun interrupt on Int1 */
|
||||
#define LIS3DSH_CTRL_REG_6_P2_BOOT_BM (1<<0) /* BOOT interrupt on Int2 */
|
||||
|
||||
/* SPI BUS PARAMETERS *******************************************************/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue