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arch/x86_64/include/intel64/irq.h: align definitions
align all definitions in intel64/irq.h Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
Xiang Xiao
parent
cfaeb74dd3
commit
eeef185558
1 changed files with 356 additions and 355 deletions
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@ -47,306 +47,306 @@
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/* ISR and IRQ numbers */
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#define ISR0 0 /* Division by zero exception */
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#define ISR1 1 /* Debug exception */
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#define ISR2 2 /* Non maskable interrupt */
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#define ISR3 3 /* Breakpoint exception */
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#define ISR4 4 /* 'Into detected overflow' */
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#define ISR5 5 /* Out of bounds exception */
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#define ISR6 6 /* Invalid opcode exception */
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#define ISR7 7 /* No coprocessor exception */
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#define ISR8 8 /* Double fault (pushes an error code) */
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#define ISR9 9 /* Coprocessor segment overrun */
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#define ISR10 10 /* Bad TSS (pushes an error code) */
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#define ISR11 11 /* Segment not present (pushes an error code) */
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#define ISR12 12 /* Stack fault (pushes an error code) */
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#define ISR13 13 /* General protection fault (pushes an error code) */
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#define ISR14 14 /* Page fault (pushes an error code) */
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#define ISR15 15 /* Unknown interrupt exception */
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#define ISR16 16 /* Coprocessor fault */
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#define ISR17 17 /* Alignment check exception */
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#define ISR18 18 /* Machine check exception */
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#define ISR19 19 /* SIMD Float-Point Exception*/
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#define ISR20 20 /* Virtualization Exception */
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#define ISR21 21 /* Reserved */
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#define ISR22 22 /* Reserved */
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#define ISR23 23 /* Reserved */
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#define ISR24 24 /* Reserved */
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#define ISR25 25 /* Reserved */
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#define ISR26 26 /* Reserved */
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#define ISR27 27 /* Reserved */
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#define ISR28 28 /* Reserved */
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#define ISR29 29 /* Reserved */
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#define ISR30 30 /* Security Exception */
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#define ISR31 31 /* Reserved */
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#define ISR0 0 /* Division by zero exception */
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#define ISR1 1 /* Debug exception */
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#define ISR2 2 /* Non maskable interrupt */
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#define ISR3 3 /* Breakpoint exception */
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#define ISR4 4 /* 'Into detected overflow' */
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#define ISR5 5 /* Out of bounds exception */
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#define ISR6 6 /* Invalid opcode exception */
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#define ISR7 7 /* No coprocessor exception */
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#define ISR8 8 /* Double fault (pushes an error code) */
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#define ISR9 9 /* Coprocessor segment overrun */
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#define ISR10 10 /* Bad TSS (pushes an error code) */
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#define ISR11 11 /* Segment not present (pushes an error code) */
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#define ISR12 12 /* Stack fault (pushes an error code) */
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#define ISR13 13 /* General protection fault (pushes an error code) */
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#define ISR14 14 /* Page fault (pushes an error code) */
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#define ISR15 15 /* Unknown interrupt exception */
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#define ISR16 16 /* Coprocessor fault */
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#define ISR17 17 /* Alignment check exception */
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#define ISR18 18 /* Machine check exception */
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#define ISR19 19 /* SIMD Float-Point Exception*/
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#define ISR20 20 /* Virtualization Exception */
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#define ISR21 21 /* Reserved */
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#define ISR22 22 /* Reserved */
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#define ISR23 23 /* Reserved */
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#define ISR24 24 /* Reserved */
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#define ISR25 25 /* Reserved */
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#define ISR26 26 /* Reserved */
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#define ISR27 27 /* Reserved */
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#define ISR28 28 /* Reserved */
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#define ISR29 29 /* Reserved */
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#define ISR30 30 /* Security Exception */
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#define ISR31 31 /* Reserved */
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#define IRQ0 32 /* System timer (cannot be changed) */
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#define IRQ1 33 /* Keyboard controller (cannot be changed) */
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#define IRQ2 34 /* Cascaded signals from IRQs 8~15 */
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#define IRQ3 35 /* Serial port controller for COM2/4 */
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#define IRQ4 36 /* serial port controller for COM1/3 */
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#define IRQ5 37 /* LPT port 2 or sound card */
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#define IRQ6 38 /* Floppy disk controller */
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#define IRQ7 39 /* LPT port 1 or sound card */
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#define IRQ8 40 /* Real time clock (RTC) */
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#define IRQ9 41 /* Open interrupt/available or SCSI host adapter */
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#define IRQ10 42 /* Open interrupt/available or SCSI or NIC */
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#define IRQ11 43 /* Open interrupt/available or SCSI or NIC */
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#define IRQ12 44 /* Mouse on PS/2 connector */
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#define IRQ13 45 /* Math coprocessor */
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#define IRQ14 46 /* Primary ATA channel */
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#define IRQ15 47 /* Secondary ATA channel */
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#define IRQ16 48
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#define IRQ17 49
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#define IRQ18 50
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#define IRQ19 51
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#define IRQ20 52
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#define IRQ21 53
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#define IRQ22 54
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#define IRQ23 55
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#define IRQ24 56
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#define IRQ25 57
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#define IRQ26 58
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#define IRQ27 59
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#define IRQ28 60
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#define IRQ29 61
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#define IRQ30 62
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#define IRQ31 63
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#define IRQ32 64
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#define IRQ33 65
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#define IRQ34 66
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#define IRQ35 67
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#define IRQ36 68
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#define IRQ37 69
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#define IRQ38 70
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#define IRQ39 71
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#define IRQ40 72
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#define IRQ41 73
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#define IRQ42 74
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#define IRQ43 75
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#define IRQ44 76
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#define IRQ45 77
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#define IRQ46 78
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#define IRQ47 79
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#define IRQ48 80
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#define IRQ49 81
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#define IRQ50 82
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#define IRQ51 83
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#define IRQ52 84
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#define IRQ53 85
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#define IRQ54 86
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#define IRQ55 87
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#define IRQ56 88
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#define IRQ57 89
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#define IRQ58 90
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#define IRQ59 91
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#define IRQ60 92
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#define IRQ61 93
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#define IRQ62 94
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#define IRQ63 95
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#define IRQ64 96
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#define IRQ65 97
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#define IRQ66 98
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#define IRQ67 99
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#define IRQ68 100
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#define IRQ69 101
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#define IRQ70 102
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#define IRQ71 103
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#define IRQ72 104
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#define IRQ73 105
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#define IRQ74 106
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#define IRQ75 107
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#define IRQ76 108
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#define IRQ77 109
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#define IRQ78 110
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#define IRQ79 111
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#define IRQ80 112
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#define IRQ81 113
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#define IRQ82 114
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#define IRQ83 115
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#define IRQ84 116
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#define IRQ85 117
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#define IRQ86 118
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#define IRQ87 119
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#define IRQ88 120
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#define IRQ89 121
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#define IRQ90 122
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#define IRQ91 123
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#define IRQ92 124
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#define IRQ93 125
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#define IRQ94 126
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#define IRQ95 127
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#define IRQ96 128
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#define IRQ97 129
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#define IRQ98 130
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#define IRQ99 131
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#define IRQ100 132
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#define IRQ101 133
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#define IRQ102 134
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#define IRQ103 135
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#define IRQ104 136
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#define IRQ105 137
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#define IRQ106 138
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#define IRQ107 139
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#define IRQ108 140
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#define IRQ109 141
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#define IRQ110 142
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#define IRQ111 143
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#define IRQ112 144
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#define IRQ113 145
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#define IRQ114 146
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#define IRQ115 147
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#define IRQ116 148
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#define IRQ117 149
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#define IRQ118 150
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#define IRQ119 151
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#define IRQ120 152
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#define IRQ121 153
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#define IRQ122 154
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#define IRQ123 155
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#define IRQ124 156
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#define IRQ125 157
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#define IRQ126 158
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#define IRQ127 159
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#define IRQ128 160
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#define IRQ129 161
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#define IRQ130 162
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#define IRQ131 163
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#define IRQ132 164
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#define IRQ133 165
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#define IRQ134 166
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#define IRQ135 167
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#define IRQ136 168
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#define IRQ137 169
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#define IRQ138 170
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#define IRQ139 171
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#define IRQ140 172
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#define IRQ141 173
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#define IRQ142 174
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#define IRQ143 175
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#define IRQ144 176
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#define IRQ145 177
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#define IRQ146 178
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#define IRQ147 179
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#define IRQ148 180
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#define IRQ149 181
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#define IRQ150 182
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#define IRQ151 183
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#define IRQ152 184
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#define IRQ153 185
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#define IRQ154 186
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#define IRQ155 187
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#define IRQ156 188
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#define IRQ157 189
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#define IRQ158 190
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#define IRQ159 191
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#define IRQ160 192
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#define IRQ161 193
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#define IRQ162 194
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#define IRQ163 195
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#define IRQ164 196
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#define IRQ165 197
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#define IRQ166 198
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#define IRQ167 199
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#define IRQ168 200
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#define IRQ169 201
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#define IRQ170 202
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#define IRQ171 203
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#define IRQ172 204
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#define IRQ173 205
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#define IRQ174 206
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#define IRQ175 207
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#define IRQ176 208
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#define IRQ177 209
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#define IRQ178 210
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#define IRQ179 211
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#define IRQ180 212
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#define IRQ181 213
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#define IRQ182 214
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#define IRQ183 215
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#define IRQ184 216
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#define IRQ185 217
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#define IRQ186 218
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#define IRQ187 219
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#define IRQ188 220
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#define IRQ189 221
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#define IRQ190 222
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#define IRQ191 223
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#define IRQ192 224
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#define IRQ193 225
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#define IRQ194 226
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#define IRQ195 227
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#define IRQ196 228
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#define IRQ197 229
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#define IRQ198 230
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#define IRQ199 231
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#define IRQ200 232
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#define IRQ201 233
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#define IRQ202 234
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#define IRQ203 235
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#define IRQ204 236
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#define IRQ205 237
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#define IRQ206 238
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#define IRQ207 239
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#define IRQ208 240
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#define IRQ209 241
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#define IRQ210 242
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#define IRQ211 243
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#define IRQ212 244
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#define IRQ213 245
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#define IRQ214 246
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#define IRQ215 247
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#define IRQ216 248
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#define IRQ217 249
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#define IRQ218 250
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#define IRQ219 251
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#define IRQ220 252
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#define IRQ221 253
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#define IRQ222 254
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#define IRQ223 255
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#define IRQ224 256
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#define IRQ225 257
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#define IRQ226 258
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#define IRQ227 259
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#define IRQ228 260
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#define IRQ229 261
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#define IRQ230 262
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#define IRQ231 263
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#define IRQ232 264
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#define IRQ233 265
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#define IRQ234 266
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#define IRQ235 267
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#define IRQ236 268
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#define IRQ237 269
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#define IRQ238 270
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#define IRQ239 271
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#define IRQ240 272
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#define IRQ241 273
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#define IRQ242 274
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#define IRQ243 275
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#define IRQ244 276
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#define IRQ245 277
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#define IRQ246 278
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#define IRQ247 279
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#define IRQ248 280
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#define IRQ249 281
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#define IRQ250 282
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#define IRQ251 283
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#define IRQ252 284
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#define IRQ253 285
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#define IRQ254 286
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#define IRQ255 287
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#define IRQ0 32 /* System timer (cannot be changed) */
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#define IRQ1 33 /* Keyboard controller (cannot be changed) */
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#define IRQ2 34 /* Cascaded signals from IRQs 8~15 */
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#define IRQ3 35 /* Serial port controller for COM2/4 */
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#define IRQ4 36 /* serial port controller for COM1/3 */
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#define IRQ5 37 /* LPT port 2 or sound card */
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#define IRQ6 38 /* Floppy disk controller */
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#define IRQ7 39 /* LPT port 1 or sound card */
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#define IRQ8 40 /* Real time clock (RTC) */
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#define IRQ9 41 /* Open interrupt/available or SCSI host adapter */
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#define IRQ10 42 /* Open interrupt/available or SCSI or NIC */
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#define IRQ11 43 /* Open interrupt/available or SCSI or NIC */
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#define IRQ12 44 /* Mouse on PS/2 connector */
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#define IRQ13 45 /* Math coprocessor */
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#define IRQ14 46 /* Primary ATA channel */
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#define IRQ15 47 /* Secondary ATA channel */
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#define IRQ16 48
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#define IRQ17 49
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#define IRQ18 50
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#define IRQ19 51
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#define IRQ20 52
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#define IRQ21 53
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#define IRQ22 54
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#define IRQ23 55
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#define IRQ24 56
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#define IRQ25 57
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#define IRQ26 58
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#define IRQ27 59
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#define IRQ28 60
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#define IRQ29 61
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#define IRQ30 62
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#define IRQ31 63
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#define IRQ32 64
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#define IRQ33 65
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#define IRQ34 66
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#define IRQ35 67
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#define IRQ36 68
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#define IRQ37 69
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#define IRQ38 70
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#define IRQ39 71
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#define IRQ40 72
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#define IRQ41 73
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#define IRQ42 74
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#define IRQ43 75
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#define IRQ44 76
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#define IRQ45 77
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#define IRQ46 78
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#define IRQ47 79
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#define IRQ48 80
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#define IRQ49 81
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#define IRQ50 82
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#define IRQ51 83
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#define IRQ52 84
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#define IRQ53 85
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#define IRQ54 86
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#define IRQ55 87
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#define IRQ56 88
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#define IRQ57 89
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#define IRQ58 90
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#define IRQ59 91
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#define IRQ60 92
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#define IRQ61 93
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#define IRQ62 94
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#define IRQ63 95
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#define IRQ64 96
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#define IRQ65 97
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#define IRQ66 98
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#define IRQ67 99
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#define IRQ68 100
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#define IRQ69 101
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#define IRQ70 102
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#define IRQ71 103
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#define IRQ72 104
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#define IRQ73 105
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#define IRQ74 106
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#define IRQ75 107
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#define IRQ76 108
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#define IRQ77 109
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#define IRQ78 110
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#define IRQ79 111
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#define IRQ80 112
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#define IRQ81 113
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#define IRQ82 114
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#define IRQ83 115
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#define IRQ84 116
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#define IRQ85 117
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#define IRQ86 118
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#define IRQ87 119
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#define IRQ88 120
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#define IRQ89 121
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#define IRQ90 122
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#define IRQ91 123
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#define IRQ92 124
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#define IRQ93 125
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#define IRQ94 126
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#define IRQ95 127
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#define IRQ96 128
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#define IRQ97 129
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#define IRQ98 130
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#define IRQ99 131
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#define IRQ100 132
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#define IRQ101 133
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#define IRQ102 134
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#define IRQ103 135
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#define IRQ104 136
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#define IRQ105 137
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#define IRQ106 138
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#define IRQ107 139
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#define IRQ108 140
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#define IRQ109 141
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#define IRQ110 142
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#define IRQ111 143
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#define IRQ112 144
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#define IRQ113 145
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#define IRQ114 146
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#define IRQ115 147
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#define IRQ116 148
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#define IRQ117 149
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#define IRQ118 150
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#define IRQ119 151
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#define IRQ120 152
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#define IRQ121 153
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#define IRQ122 154
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#define IRQ123 155
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#define IRQ124 156
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#define IRQ125 157
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#define IRQ126 158
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#define IRQ127 159
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#define IRQ128 160
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#define IRQ129 161
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#define IRQ130 162
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#define IRQ131 163
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#define IRQ132 164
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#define IRQ133 165
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#define IRQ134 166
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#define IRQ135 167
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#define IRQ136 168
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#define IRQ137 169
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#define IRQ138 170
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#define IRQ139 171
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#define IRQ140 172
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#define IRQ141 173
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#define IRQ142 174
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#define IRQ143 175
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#define IRQ144 176
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#define IRQ145 177
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#define IRQ146 178
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#define IRQ147 179
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#define IRQ148 180
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#define IRQ149 181
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#define IRQ150 182
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#define IRQ151 183
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#define IRQ152 184
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#define IRQ153 185
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#define IRQ154 186
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#define IRQ155 187
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#define IRQ156 188
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#define IRQ157 189
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#define IRQ158 190
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#define IRQ159 191
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#define IRQ160 192
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#define IRQ161 193
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#define IRQ162 194
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#define IRQ163 195
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#define IRQ164 196
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||||
#define IRQ165 197
|
||||
#define IRQ166 198
|
||||
#define IRQ167 199
|
||||
#define IRQ168 200
|
||||
#define IRQ169 201
|
||||
#define IRQ170 202
|
||||
#define IRQ171 203
|
||||
#define IRQ172 204
|
||||
#define IRQ173 205
|
||||
#define IRQ174 206
|
||||
#define IRQ175 207
|
||||
#define IRQ176 208
|
||||
#define IRQ177 209
|
||||
#define IRQ178 210
|
||||
#define IRQ179 211
|
||||
#define IRQ180 212
|
||||
#define IRQ181 213
|
||||
#define IRQ182 214
|
||||
#define IRQ183 215
|
||||
#define IRQ184 216
|
||||
#define IRQ185 217
|
||||
#define IRQ186 218
|
||||
#define IRQ187 219
|
||||
#define IRQ188 220
|
||||
#define IRQ189 221
|
||||
#define IRQ190 222
|
||||
#define IRQ191 223
|
||||
#define IRQ192 224
|
||||
#define IRQ193 225
|
||||
#define IRQ194 226
|
||||
#define IRQ195 227
|
||||
#define IRQ196 228
|
||||
#define IRQ197 229
|
||||
#define IRQ198 230
|
||||
#define IRQ199 231
|
||||
#define IRQ200 232
|
||||
#define IRQ201 233
|
||||
#define IRQ202 234
|
||||
#define IRQ203 235
|
||||
#define IRQ204 236
|
||||
#define IRQ205 237
|
||||
#define IRQ206 238
|
||||
#define IRQ207 239
|
||||
#define IRQ208 240
|
||||
#define IRQ209 241
|
||||
#define IRQ210 242
|
||||
#define IRQ211 243
|
||||
#define IRQ212 244
|
||||
#define IRQ213 245
|
||||
#define IRQ214 246
|
||||
#define IRQ215 247
|
||||
#define IRQ216 248
|
||||
#define IRQ217 249
|
||||
#define IRQ218 250
|
||||
#define IRQ219 251
|
||||
#define IRQ220 252
|
||||
#define IRQ221 253
|
||||
#define IRQ222 254
|
||||
#define IRQ223 255
|
||||
#define IRQ224 256
|
||||
#define IRQ225 257
|
||||
#define IRQ226 258
|
||||
#define IRQ227 259
|
||||
#define IRQ228 260
|
||||
#define IRQ229 261
|
||||
#define IRQ230 262
|
||||
#define IRQ231 263
|
||||
#define IRQ232 264
|
||||
#define IRQ233 265
|
||||
#define IRQ234 266
|
||||
#define IRQ235 267
|
||||
#define IRQ236 268
|
||||
#define IRQ237 269
|
||||
#define IRQ238 270
|
||||
#define IRQ239 271
|
||||
#define IRQ240 272
|
||||
#define IRQ241 273
|
||||
#define IRQ242 274
|
||||
#define IRQ243 275
|
||||
#define IRQ244 276
|
||||
#define IRQ245 277
|
||||
#define IRQ246 278
|
||||
#define IRQ247 279
|
||||
#define IRQ248 280
|
||||
#define IRQ249 281
|
||||
#define IRQ250 282
|
||||
#define IRQ251 283
|
||||
#define IRQ252 284
|
||||
#define IRQ253 285
|
||||
#define IRQ254 286
|
||||
#define IRQ255 287
|
||||
|
||||
#define NR_IRQS 288
|
||||
#define MAX_NR_IRQS 255
|
||||
#define NR_IRQS 288
|
||||
#define MAX_NR_IRQS 255
|
||||
|
||||
#define IRQ_ERROR 51 /* APIC Error */
|
||||
#define IRQ_SPURIOUS 0xff /* Spurious Interrupts */
|
||||
#define IRQ_ERROR 51 /* APIC Error */
|
||||
#define IRQ_SPURIOUS 0xff /* Spurious Interrupts */
|
||||
|
||||
/* Use legacy routing for HPET */
|
||||
|
||||
#define HPET0_IRQ IRQ2
|
||||
#define HPET1_IRQ IRQ8
|
||||
#define HPET0_IRQ IRQ2
|
||||
#define HPET1_IRQ IRQ8
|
||||
|
||||
/* NuttX custom interrupts configuration starts from here.
|
||||
* IRQ16-IRQ23 are reserved for GOLDFISH so we start from IRQ24.
|
||||
|
|
@ -354,16 +354,16 @@
|
|||
|
||||
/* Use IRQ24 IRQ25 for SMP */
|
||||
|
||||
#define SMP_IPI_CALL_IRQ IRQ24
|
||||
#define SMP_IPI_SCHED_IRQ IRQ25
|
||||
#define SMP_IPI_CALL_IRQ IRQ24
|
||||
#define SMP_IPI_SCHED_IRQ IRQ25
|
||||
|
||||
/* Use IRQ32 and above for MSI */
|
||||
|
||||
#define IRQ_MSI_START IRQ32
|
||||
#define IRQ_MSI_START IRQ32
|
||||
|
||||
/* Use IRQ17 for TLB shootdown */
|
||||
|
||||
#define SMP_IPI_TLBSHOOTDOWN_IRQ IRQ17
|
||||
#define SMP_IPI_TLBSHOOTDOWN_IRQ IRQ17
|
||||
|
||||
/* Common register save structure created by up_saveusercontext() and by
|
||||
* ISR/IRQ interrupt processing.
|
||||
|
|
@ -379,25 +379,25 @@
|
|||
/* XSAVE state depneds on enabled features */
|
||||
|
||||
# ifdef CONFIG_ARCH_X86_64_AVX
|
||||
# define XSTATE_AVX_STATE X86_XSAVE_AVX
|
||||
# define XSTATE_AVX_SIZE XSAVE_AVX_SIZE
|
||||
# define XSTATE_AVX_STATE X86_XSAVE_AVX
|
||||
# define XSTATE_AVX_SIZE XSAVE_AVX_SIZE
|
||||
# else
|
||||
# define XSTATE_AVX_STATE 0
|
||||
# define XSTATE_AVX_SIZE 0
|
||||
# define XSTATE_AVX_STATE 0
|
||||
# define XSTATE_AVX_SIZE 0
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_ARCH_X86_64_AVX512
|
||||
# define XSTATE_AVX512_STATE (X86_XSAVE_AVX512_OPMASK | \
|
||||
X86_XSAVE_AVX512_HI256 | \
|
||||
X86_XSAVE_AVX512_HI16)
|
||||
# define XSTATE_AVX512_SIZE (XSAVE_MXP_BNDREGS_SIZE + \
|
||||
XSAVE_MXP_BNDCSR_SIZE + \
|
||||
XSAVE_AVX512OPMASK_SIZE + \
|
||||
XSAVE_AVX512HI256_SIZE + \
|
||||
XSAVE_AVX512HI16_SIZE)
|
||||
# define XSTATE_AVX512_STATE (X86_XSAVE_AVX512_OPMASK | \
|
||||
X86_XSAVE_AVX512_HI256 | \
|
||||
X86_XSAVE_AVX512_HI16)
|
||||
# define XSTATE_AVX512_SIZE (XSAVE_MXP_BNDREGS_SIZE + \
|
||||
XSAVE_MXP_BNDCSR_SIZE + \
|
||||
XSAVE_AVX512OPMASK_SIZE + \
|
||||
XSAVE_AVX512HI256_SIZE + \
|
||||
XSAVE_AVX512HI16_SIZE)
|
||||
# else
|
||||
# define XSTATE_AVX512_STATE 0
|
||||
# define XSTATE_AVX512_SIZE 0
|
||||
# define XSTATE_AVX512_STATE 0
|
||||
# define XSTATE_AVX512_SIZE 0
|
||||
# endif
|
||||
|
||||
/* State component bitmap */
|
||||
|
|
@ -418,79 +418,80 @@
|
|||
/* Align registers to 64-bytes */
|
||||
|
||||
#ifdef CONFIG_ARCH_X86_64_AVX512
|
||||
# define XMMAREA_REG_ALIGN (13)
|
||||
# define XMMAREA_REG_ALIGN (13)
|
||||
#else
|
||||
# define XMMAREA_REG_ALIGN (7)
|
||||
# define XMMAREA_REG_ALIGN (7)
|
||||
#endif
|
||||
|
||||
/* Register offset in XMMAREA */
|
||||
|
||||
#define XMMAREA_OFFSET (XCPTCONTEXT_XMM_AREA_SIZE / 8)
|
||||
#define XMMAREA_REG_OFFSET (XMMAREA_REG_ALIGN + XMMAREA_OFFSET)
|
||||
#define XMMAREA_OFFSET (XCPTCONTEXT_XMM_AREA_SIZE / 8)
|
||||
#define XMMAREA_REG_OFFSET (XMMAREA_REG_ALIGN + XMMAREA_OFFSET)
|
||||
|
||||
/* Data segments */
|
||||
|
||||
#define REG_FS (0 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_GS (1 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_ES (2 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_DS (3 + XMMAREA_REG_OFFSET) /* Data segment selector */
|
||||
#define REG_FS (0 + XMMAREA_REG_OFFSET)
|
||||
#define REG_GS (1 + XMMAREA_REG_OFFSET)
|
||||
#define REG_ES (2 + XMMAREA_REG_OFFSET)
|
||||
#define REG_DS (3 + XMMAREA_REG_OFFSET) /* Data segment selector */
|
||||
|
||||
/* Remaining regs */
|
||||
|
||||
#define REG_RAX (4 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RBX (5 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RBP (6 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R10 (7 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R11 (8 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R12 (9 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R13 (10 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R14 (11 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R15 (12 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RAX (4 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RBX (5 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RBP (6 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R10 (7 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R11 (8 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R12 (9 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R13 (10 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R14 (11 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R15 (12 + XMMAREA_REG_OFFSET)
|
||||
|
||||
/* ABI calling convention */
|
||||
|
||||
#define REG_R9 (13 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R8 (14 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RCX (15 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RDX (16 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RSI (17 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_RDI (18 + XMMAREA_REG_OFFSET) /* " " "" " " */
|
||||
#define REG_R9 (13 + XMMAREA_REG_OFFSET)
|
||||
#define REG_R8 (14 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RCX (15 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RDX (16 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RSI (17 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RDI (18 + XMMAREA_REG_OFFSET)
|
||||
|
||||
/* IRQ saved */
|
||||
|
||||
#define REG_ERRCODE (19 + XMMAREA_REG_OFFSET) /* Error code */
|
||||
#define REG_RIP (20 + XMMAREA_REG_OFFSET) /* Pushed by process on interrupt processing */
|
||||
#define REG_CS (21 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_RFLAGS (22 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_RSP (23 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_SS (24 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
|
||||
#define REG_ERRCODE (19 + XMMAREA_REG_OFFSET) /* Error code */
|
||||
#define REG_RIP (20 + XMMAREA_REG_OFFSET) /* Pushed by process on interrupt processing */
|
||||
#define REG_CS (21 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RFLAGS (22 + XMMAREA_REG_OFFSET)
|
||||
#define REG_RSP (23 + XMMAREA_REG_OFFSET)
|
||||
#define REG_SS (24 + XMMAREA_REG_OFFSET)
|
||||
|
||||
#define XMMAREA_REGS (25)
|
||||
#define XMMAREA_REGS (25)
|
||||
|
||||
/* Aux register used by implementation */
|
||||
|
||||
#define REG_AUX (26 + XMMAREA_REG_OFFSET)
|
||||
#define REG_AUX (26 + XMMAREA_REG_OFFSET)
|
||||
|
||||
/* NOTE 2: This is not really state data. Rather, this is just a convenient
|
||||
* way to pass parameters from the interrupt handler to C code.
|
||||
*/
|
||||
|
||||
#define XCPTCONTEXT_REGS (XMMAREA_REGS + XMMAREA_REG_ALIGN + \
|
||||
XCPTCONTEXT_XMM_AREA_SIZE / 8)
|
||||
#define XCPTCONTEXT_REGS (XMMAREA_REGS + \
|
||||
XMMAREA_REG_ALIGN + \
|
||||
XCPTCONTEXT_XMM_AREA_SIZE / 8)
|
||||
|
||||
#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
|
||||
#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
|
||||
|
||||
/* Always align XCPTCONTEXT to 64-bytes to support XSAVE */
|
||||
|
||||
#define XCPTCONTEXT_ALIGN (64)
|
||||
#define XCPTCONTEXT_ALIGN (64)
|
||||
|
||||
#define XCP_ALIGN_MASK (XCPTCONTEXT_ALIGN - 1)
|
||||
#define XCP_ALIGN_DOWN(a) ((a) & ~XCP_ALIGN_MASK)
|
||||
#define XCP_ALIGN_UP(a) (((a) + XCP_ALIGN_MASK) & ~XCP_ALIGN_MASK)
|
||||
#define XCP_ALIGN_MASK (XCPTCONTEXT_ALIGN - 1)
|
||||
#define XCP_ALIGN_DOWN(a) ((a) & ~XCP_ALIGN_MASK)
|
||||
#define XCP_ALIGN_UP(a) (((a) + XCP_ALIGN_MASK) & ~XCP_ALIGN_MASK)
|
||||
|
||||
/* Aux register flags */
|
||||
|
||||
#define REG_AUX_FULLCONTEXT (1 << 0) /* Force full context switch */
|
||||
#define REG_AUX_FULLCONTEXT (1 << 0) /* Force full context switch */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
@ -499,10 +500,10 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
enum ioapic_trigger_mode
|
||||
{
|
||||
TRIGGER_RISING_EDGE = 0,
|
||||
TRIGGER_FALLING_EDGE = (1 << 13),
|
||||
TRIGGER_LEVEL_ACTIVE_HIGH = 1 << 15,
|
||||
TRIGGER_LEVEL_ACTIVE_LOW = (1 << 15) | (1 << 13),
|
||||
TRIGGER_RISING_EDGE = 0,
|
||||
TRIGGER_FALLING_EDGE = (1 << 13),
|
||||
TRIGGER_LEVEL_ACTIVE_HIGH = (1 << 15),
|
||||
TRIGGER_LEVEL_ACTIVE_LOW = (1 << 15) | (1 << 13),
|
||||
};
|
||||
|
||||
/* This structure represents the return state from a system call */
|
||||
|
|
|
|||
Loading…
Reference in a new issue