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We have ported NuttX on Renesas RX65N Micro-controller. This port includes following interfaces

Browse source 
1. Serial (UART) driver (13 ports)
2. Ethernet driver

This port is provided on two boards
1. RSK RX65N-2MB
2. GR-Rose

The port is built on Cygwin environment.

As part of this port, we have created two documents
1. Readme.txt for each board
2. User manual to provide information about development environment setup
Both these documents are placed under
1. /boards/renesas/rx65n/rx65n-grrose
2. /boards/renesas/rx65n/rx65n-rsk2mb

We have run 'nxstyle' for coding guidelines and 'ostest' for testing NuttX features on test platform.
We have shared the log with no errors as confirmation of valid port.
This commit is contained in:
Anjana 2019-10-11 23:36:57 +08:00 committed by Gregory Nutt
parent df1bcc4229
commit fae7e63479
80 changed files with 41796 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
arch/renesas/Kconfig
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@ -22,12 +22,47 @@ config ARCH_CHIP_M30262F8
---help---
Renesas M30262F8 (M16C)
config ARCH_CHIP_R5F565NEDDFC
bool "R5F565NEDDFC"
select ARCH_RX65N_RSK1MB
select ARCH_RX65N
---help---
Renesas RX65N on RSKRX65N-1MB
config ARCH_CHIP_R5F565NEHDFC
bool "R5F565NEHDFC"
select ARCH_RX65N_RSK2MB
---help---
Renesas RX65N on RSKRX65N-2MB
config ARCH_CHIP_R5F565NEHDFP
bool "R5F565NEHDFP"
select ARCH_RX65N_GRROSE
---help---
Renesas RX65N on GR-ROSE
endchoice
config ARCH_SH1
bool
default n
config ARCH_RX65N
bool
default n
config ARCH_RX65N_RSK1MB
bool
default n
config ARCH_RX65N_RSK2MB
bool
default n
config ARCH_RX65N_GRROSE
bool
default n
config ARCH_M16C
bool
default n
@ -36,9 +71,14 @@ config ARCH_CHIP
string
default "sh1" if ARCH_SH1
default "m16c" if ARCH_M16C
default "rx65n" if ARCH_RX65N
default "rx65n" if ARCH_RX65N_RSK1MB
default "rx65n" if ARCH_RX65N_RSK2MB
default "rx65n" if ARCH_RX65N_GRROSE
source arch/renesas/src/common/Kconfig
source arch/renesas/src/m16c/Kconfig
source arch/renesas/src/sh1/Kconfig
source arch/renesas/src/rx65n/Kconfig
endif # ARCH_RENESAS

240
arch/renesas/include/rx65n/inttypes.h Normal file
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@ -0,0 +1,240 @@
/****************************************************************************
* arch/renesas/include/rx65n/inttypes.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H
#define __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define PRId8 "d"
#define PRId16 "d"
#define PRId32 "d"
#define PRId64 "lld"
#define PRIdLEAST8 "d"
#define PRIdLEAST16 "d"
#define PRIdLEAST32 "d"
#define PRIdLEAST64 "lld"
#define PRIdFAST8 "d"
#define PRIdFAST16 "d"
#define PRIdFAST32 "d"
#define PRIdFAST64 "lld"
#define PRIdMAX "lld"
#define PRIdPTR "d"
#define PRIi8 "i"
#define PRIi16 "i"
#define PRIi32 "i"
#define PRIi64 "lli"
#define PRIiLEAST8 "i"
#define PRIiLEAST16 "i"
#define PRIiLEAST32 "i"
#define PRIiLEAST64 "lli"
#define PRIiFAST8 "i"
#define PRIiFAST16 "i"
#define PRIiFAST32 "i"
#define PRIiFAST64 "lli"
#define PRIiMAX "lli"
#define PRIiPTR "i"
#define PRIo8 "o"
#define PRIo16 "o"
#define PRIo32 "o"
#define PRIo64 "llo"
#define PRIoLEAST8 "o"
#define PRIoLEAST16 "o"
#define PRIoLEAST32 "o"
#define PRIoLEAST64 "llo"
#define PRIoFAST8 "o"
#define PRIoFAST16 "o"
#define PRIoFAST32 "o"
#define PRIoFAST64 "llo"
#define PRIoMAX "llo"
#define PRIoPTR "o"
#define PRIu8 "u"
#define PRIu16 "u"
#define PRIu32 "u"
#define PRIu64 "llu"
#define PRIuLEAST8 "u"
#define PRIuLEAST16 "u"
#define PRIuLEAST32 "u"
#define PRIuLEAST64 "llu"
#define PRIuFAST8 "u"
#define PRIuFAST16 "u"
#define PRIuFAST32 "u"
#define PRIuFAST64 "llu"
#define PRIuMAX "llu"
#define PRIuPTR "u"
#define PRIx8 "x"
#define PRIx16 "x"
#define PRIx32 "x"
#define PRIx64 "llx"
#define PRIxLEAST8 "x"
#define PRIxLEAST16 "x"
#define PRIxLEAST32 "x"
#define PRIxLEAST64 "llx"
#define PRIxFAST8 "x"
#define PRIxFAST16 "x"
#define PRIxFAST32 "x"
#define PRIxFAST64 "llx"
#define PRIxMAX "llx"
#define PRIxPTR "x"
#define PRIX8 "X"
#define PRIX16 "X"
#define PRIX32 "X"
#define PRIX64 "llX"
#define PRIXLEAST8 "X"
#define PRIXLEAST16 "X"
#define PRIXLEAST32 "X"
#define PRIXLEAST64 "llX"
#define PRIXFAST8 "X"
#define PRIXFAST16 "X"
#define PRIXFAST32 "X"
#define PRIXFAST64 "llX"
#define PRIXMAX "llX"
#define PRIXPTR "X"
#define SCNd8 "hhd"
#define SCNd16 "hd"
#define SCNd32 "d"
#define SCNd64 "lld"
#define SCNdLEAST8 "hhd"
#define SCNdLEAST16 "hd"
#define SCNdLEAST32 "d"
#define SCNdLEAST64 "lld"
#define SCNdFAST8 "hhd"
#define SCNdFAST16 "hd"
#define SCNdFAST32 "d"
#define SCNdFAST64 "lld"
#define SCNdMAX "lld"
#define SCNdPTR "d"
#define SCNi8 "hhi"
#define SCNi16 "hi"
#define SCNi32 "i"
#define SCNi64 "lli"
#define SCNiLEAST8 "hhi"
#define SCNiLEAST16 "hi"
#define SCNiLEAST32 "i"
#define SCNiLEAST64 "lli"
#define SCNiFAST8 "hhi"
#define SCNiFAST16 "hi"
#define SCNiFAST32 "i"
#define SCNiFAST64 "lli"
#define SCNiMAX "lli"
#define SCNiPTR "i"
#define SCNo8 "hho"
#define SCNo16 "ho"
#define SCNo32 "o"
#define SCNo64 "llo"
#define SCNoLEAST8 "hho"
#define SCNoLEAST16 "ho"
#define SCNoLEAST32 "o"
#define SCNoLEAST64 "llo"
#define SCNoFAST8 "hho"
#define SCNoFAST16 "ho"
#define SCNoFAST32 "o"
#define SCNoFAST64 "llo"
#define SCNoMAX "llo"
#define SCNoPTR "o"
#define SCNu8 "hhu"
#define SCNu16 "hu"
#define SCNu32 "u"
#define SCNu64 "llu"
#define SCNuLEAST8 "hhu"
#define SCNuLEAST16 "hu"
#define SCNuLEAST32 "u"
#define SCNuLEAST64 "llu"
#define SCNuFAST8 "hhu"
#define SCNuFAST16 "hu"
#define SCNuFAST32 "u"
#define SCNuFAST64 "llu"
#define SCNuMAX "llu"
#define SCNuPTR "u"
#define SCNx8 "hhx"
#define SCNx16 "hx"
#define SCNx32 "x"
#define SCNx64 "llx"
#define SCNxLEAST8 "hhx"
#define SCNxLEAST16 "hx"
#define SCNxLEAST32 "x"
#define SCNxLEAST64 "llx"
#define SCNxFAST8 "hhx"
#define SCNxFAST16 "hx"
#define SCNxFAST32 "x"
#define SCNxFAST64 "llx"
#define SCNxMAX "llx"
#define SCNxPTR "x"
#endif /* __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H */

18050
arch/renesas/include/rx65n/iodefine.h Normal file
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File diff suppressed because it is too large Load diff

1076
arch/renesas/include/rx65n/irq.h Normal file
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File diff suppressed because it is too large Load diff

84
arch/renesas/include/rx65n/limits.h Normal file
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@ -0,0 +1,84 @@
/****************************************************************************
* arch/renesas/include/rx65n/limits.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H
#define __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H
=/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CHAR_BIT 8
#define SCHAR_MIN (-SCHAR_MAX - 1)
#define SCHAR_MAX 127
#define UCHAR_MAX 255
/* These could be different on machines where char is unsigned */
#ifdef __CHAR_UNSIGNED__
#define CHAR_MIN 0
#define CHAR_MAX UCHAR_MAX
#else
#define CHAR_MIN SCHAR_MIN
#define CHAR_MAX SCHAR_MAX
#endif
#define SHRT_MIN (-SHRT_MAX - 1)
#define SHRT_MAX 32767
#define USHRT_MAX 65535U
/* On SH-1, type 'int' is 32-bits */
#define INT_MIN (-INT_MAX - 1)
#define INT_MAX 2147483647
#define UINT_MAX 4294967295U
/* On SH-1, type 'long' is the same size as type 'int', 32-bits */
#define LONG_MIN (-LONG_MAX - 1)
#define LONG_MAX 2147483647L
#define ULONG_MAX 4294967295UL
#define LLONG_MIN (-LLONG_MAX - 1)
#define LLONG_MAX 9223372036854775807LL
#define ULLONG_MAX 18446744073709551615ULL
/* A pointer is 4 bytes */
#define PTR_MIN (-PTR_MAX - 1)
#define PTR_MAX 2147483647
#define UPTR_MAX 4294967295U
#endif /* __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H */

96
arch/renesas/include/rx65n/types.h Normal file
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@ -0,0 +1,96 @@
/****************************************************************************
* arch/renesas/include/rx65n/types.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly\
* through sys/types.h
*/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_TYPES_H
#define __ARCH_RENESAS_INCLUDE_RX65N_TYPES_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Type Declarations
****************************************************************************/
#ifndef __ASSEMBLY__
/* These are the sizes of the standard integer types. NOTE that these type
* names have a leading underscore character. This file will be included
* (indirectly) by include/stdint.h and typedef'ed to the final name without
* the underscore character. This roundabout way of doings things allows
* the stdint.h to be removed from the include/ directory in the event that
* the user prefers to use the definitions provided by their toolchain header
* files
*/
typedef signed char _int8_t;
typedef unsigned char _uint8_t;
typedef signed short _int16_t;
typedef unsigned short _uint16_t;
typedef signed int _int32_t;
typedef unsigned int _uint32_t;
typedef signed long long _int64_t;
typedef unsigned long long _uint64_t;
#define __INT64_DEFINED
/* A pointer is 4 bytes */
typedef signed int _intptr_t;
typedef unsigned int _uintptr_t;
/* This is the size of the interrupt state save returned by
* up_irq_save()
*/
typedef unsigned long irqstate_t;
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_RENESAS_INCLUDE_SH1_TYPES_H */

33
arch/renesas/src/Makefile
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@ -43,18 +43,18 @@ CXXFLAGS += $(EXTRADEFINES)
ifeq ($(CONFIG_WINDOWS_NATIVE),y)
ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src
NUTTX = $(TOPDIR)\nuttx$(EXEEXT)
CFLAGS += -I$(ARCH_SRCDIR)\chip
CFLAGS += -I$(ARCH_SRCDIR)\common
CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR)
CFLAGS += -I$(TOPDIR)\sched
CFLAGS += -I=$(ARCH_SRCDIR)\chip
CFLAGS += -I=$(ARCH_SRCDIR)\common
CFLAGS += -I=$(ARCH_SRCDIR)\$(ARCH_SUBDIR)
CFLAGS += -I=$(TOPDIR)\sched
else
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}"
CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}"
NUTTX = ${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}
CFLAGS += -I ${shell cygpath -w $(ARCH_SRCDIR)/chip}
CFLAGS += -I ${shell cygpath -w $(ARCH_SRCDIR)/common}
CFLAGS += -I ${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}
CFLAGS += -I. -isystem ${shell cygpath -w $(TOPDIR)/sched}
else
NUTTX = $(TOPDIR)/nuttx$(EXEEXT)
CFLAGS += -I$(ARCH_SRCDIR)/chip
@ -64,13 +64,13 @@ else
endif
endif
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(TOPDIR)/sched
CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched
HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT))
STARTUP_OBJS ?= $(HEAD_OBJ)
ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS)
AOBJS = $(ASRCS:.S=$(OBJEXT))
AOBJS = $(CHIP_ASRCS:.S=$(OBJEXT))
CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS)
COBJS = $(CSRCS:.c=$(OBJEXT))
@ -138,6 +138,16 @@ board/libboard$(LIBEXT):
nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
@echo "LD: nuttx"
ifeq ($(WINTOOL),y)
$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o ${shell cygpath -m "$(TOPDIR)"}/$@ $(HEAD_OBJ) \
$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) "$(LIBGCC)" $(LDENDGROUP)
@echo "LD: nuttx"
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
$(Q) $(NM) /cygwin64$(TOPDIR)/$@ | \
grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
sort > $(TOPDIR)/System.map
endif
else
$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(TOPDIR)/$@ $(HEAD_OBJ) \
$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
@ -145,6 +155,7 @@ ifneq ($(CONFIG_WINDOWS_NATIVE),y)
grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
sort > $(TOPDIR)/System.map
endif
endif
# This is part of the top-level export target

532
arch/renesas/src/rx65n/Kconfig Normal file
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@ -0,0 +1,532 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_RX65N
comment "RX65N Configuration Options"
menu "RX65N Peripheral Selections"
config RX65N_SCI2
bool "SCI2"
default n
select SCI2_SERIALDRIVER
config RX65N_ICU
bool "ICU"
default y
config RX65N_CMT0
bool "CMT0"
default y
config RX65N_CMTW0
bool "CMTW0"
default y
config RX65N_CMTW1
bool "CMTW1"
default y
config RX65N_CMT2
bool "CMT2"
default y
config RX65N_CMT3
bool "CMT3"
default y
config RX65N_PERIB
bool "PERIB"
default y
config RX65N_IRQ_GROUP
bool "IRQ_GROUP"
default y
endmenu # RX65N Peripheral Selections
endif
if ARCH_RX65N_RSK1MB
comment "RX65N on RSKRX65N-1MB Configuration Options"
menu "RX65N Peripheral Selections"
config RX65N_SCI2
bool "SCI2"
default n
select SCI2_SERIALDRIVER
config RX65N_ICU
bool "ICU"
default y
config RX65N_CMT0
bool "CMT0"
default y
config RX65N_CMT2
bool "CMT2"
default y
config RX65N_CMT3
bool "CMT3"
default y
config RX65N_PERIB
bool "PERIB"
default y
config RX65N_IRQ_GROUP
bool "IRQ_GROUP"
default y
config RX65N_EMAC
bool
default n
select ARCH_HAVE_NETDEV_STATISTICS
---help---
NOTE that write-through caching is automatically selected. This is
to work around issues with the RX and TX descriptors with are 8-bytes
in size. But the D-Cache cache line size is 32-bytes. That means
that you cannot reload, clean or invalidate a descriptor without also
effecting three neighboring descriptors. Setting write through mode
eliminates the need for cleaning. If only reloading and invalidating
are done, then there is no problem.
config RX65N_EMAC0
bool "Ethernet MAC (GMAC)"
default n
select RX65N_EMAC
select NETDEVICES
select ARCH_HAVE_PHY
endmenu # RX65N Peripheral Selections
endif
if ARCH_RX65N_RSK2MB
comment "RX65N on RSKRX65N-2MB Configuration Options"
menu "RX65N Peripheral Selections"
config RX65N_SCI2
bool "SCI2"
select SCI2_SERIALDRIVER
config RX65N_SCI8
bool "SCI8"
select SCI8_SERIALDRIVER
config RX65N_SCI9
bool "SCI9"
default n
select SCI9_SERIALDRIVER
config RX65N_SCI10
bool "SCI10"
default n
select SCI10_SERIALDRIVER
config RX65N_SCI11
bool "SCI11"
default n
select SCI11_SERIALDRIVER
config RX65N_SCI12
bool "SCI12"
default n
select SCI12_SERIALDRIVER
config RX65N_ICU
bool "ICU"
default y
config RX65N_CMT0
bool "CMT0"
default y
config RX65N_CMT2
bool "CMT2"
default y
config RX65N_CMT3
bool "CMT3"
default y
config RX65N_PERIB
bool "PERIB"
default y
config RX65N_IRQ_GROUP
bool "IRQ_GROUP"
default y
config RX65N_EMAC
bool
default n
select ARCH_HAVE_NETDEV_STATISTICS
---help---
NOTE that write-through caching is automatically selected. This is
to work around issues with the RX and TX descriptors with are 8-bytes
in size. But the D-Cache cache line size is 32-bytes. That means
that you cannot reload, clean or invalidate a descriptor without also
effecting three neighboring descriptors. Setting write through mode
eliminates the need for cleaning. If only reloading and invalidating
are done, then there is no problem.
config RX65N_EMAC0
bool "Ethernet MAC (GMAC)"
default n
select RX65N_EMAC
select NETDEVICES
select ARCH_HAVE_PHY
endmenu # RX65N Peripheral Selections
endif
if ARCH_RX65N_GRROSE
comment "RX65N on GR-ROSE Configuration Options"
menu "RX65N Peripheral Selections"
config RX65N_SCI0
bool "SCI0"
default n
select SCI0_SERIALDRIVER
config RX65N_SCI1
bool "SCI1"
default y
select SCI1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config RX65N_SCI2
bool "SCI2"
default y
select SCI2_SERIALDRIVER
config RX65N_SCI3
bool "SCI3"
default n
select SCI3_SERIALDRIVER
config RX65N_SCI4
bool "SCI4"
default n
select SCI4_SERIALDRIVER
config RX65N_SCI5
bool "SCI5"
default y
select SCI5_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config RX65N_SCI6
bool "SCI6"
default y
select SCI6_SERIALDRIVER
config RX65N_SCI7
bool "SCI7"
default n
select SCI7_SERIALDRIVER
config RX65N_SCI8
bool "SCI8"
default y
select SCI8_SERIALDRIVER
config RX65N_SCI9
bool "SCI9"
default n
select SCI9_SERIALDRIVER
config RX65N_SCI10
bool "SCI10"
default n
select SCI10_SERIALDRIVER
config RX65N_SCI11
bool "SCI11"
default n
select SCI11_SERIALDRIVER
config RX65N_SCI12
bool "SCI12"
default n
select SCI12_SERIALDRIVER
config RX65N_ICU
bool "ICU"
default y
config RX65N_CMT0
bool "CMT0"
default y
config RX65N_CMT2
bool "CMT2"
default y
config RX65N_CMT3
bool "CMT3"
default y
config RX65N_PERIB
bool "PERIB"
default y
config RX65N_IRQ_GROUP
bool "IRQ_GROUP"
default y
config RX65N_EMAC
bool
default n
select ARCH_HAVE_NETDEV_STATISTICS
---help---
NOTE that write-through caching is automatically selected. This is
to work around issues with the RX and TX descriptors with are 8-bytes
in size. But the D-Cache cache line size is 32-bytes. That means
that you cannot reload, clean or invalidate a descriptor without also
effecting three neighboring descriptors. Setting write through mode
eliminates the need for cleaning. If only reloading and invalidating
are done, then there is no problem.
config RX65N_EMAC0
bool "Ethernet MAC (GMAC)"
default n
select RX65N_EMAC
select NETDEVICES
select ARCH_HAVE_PHY
endmenu # RX65N Peripheral Selections
endif
menu "EMAC device driver options"
depends on RX65N_EMAC0
config RX65N_EMAC0_NRXBUFFERS
int "Number of RX buffers"
default 16
---help---
EMAC buffer memory is segmented into 128 byte units (not
configurable). This setting provides the number of such 128 byte
units used for reception. This is also equal to the number of RX
descriptors that will be allocated The selected value must be an
even power of 2.
NOTE that the defaut of 16 correspond to a total of only 2Kb of
RX buffering. That can easily exceeded on a busy network or with
large packet MTUs. You will know if this happens because you will
see the "Buffer Not Available (BNA)" receive error.
config RX65N_EMAC0_NTXBUFFERS
int "Number of TX buffers"
default 8
---help---
EMAC buffer memory is segmented into full Ethernet packets (size
CONFIG_NET_BUFSIZE bytes). This setting provides the number of such
packets that can be in flight. This is also equal to the number of TX
descriptors that will be allocated.
config RX65N_EMAC0_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config RX65N_EMAC0_PHYINIT
bool "Board-specific PHY Initialization"
default n
---help---
Some boards require specialized initialization of the PHY before it can be used.
This may include such things as configuring GPIOs, resetting the PHY, etc. If
RX65N_EMAC0_PHYINIT is defined in the configuration then the board specific logic must
provide sam_phyinitialize(); The RX65N EMAC driver will call this function
one time before it first uses the PHY.
choice
prompt "PHY interface"
default RX65N_EMAC0_MII
config RX65N_EMAC0_MII
bool "MII"
---help---
Support Ethernet MII interface (vs RMII).
config RX65N_EMAC0_RMII
bool "RMII"
depends on !ARCH_CHIP_SAM4E
---help---
Support Ethernet RMII interface (vs MII).
endchoice # PHY interface
config RX65N_EMAC0_CLAUSE45
bool "Clause 45 MII"
depends on RX65N_EMAC0_MII
---help---
MDIO was originally defined in Clause 22 of IEEE RFC802.3. In the
original specification, a single MDIO interface is able to access up
to 32 registers in 32 different PHY devices. To meet the needs the
expanding needs of 10-Gigabit Ethernet devices, Clause 45 of the
802.3ae specification provided the following additions to MDIO:
- Ability to access 65,536 registers in 32 different devices on
32 different ports
- Additional OP-code and ST-code for Indirect Address register
access for 10 Gigabit Ethernet
- End-to-end fault signaling
- Multiple loopback points
- Low voltage electrical specification
By default, Clause 22 PHYs will be supported unless this option is
selected.
config RX65N_EMAC0_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
config RX65N_EMAC0_ETHFD
bool "Full duplex"
default n
depends on !RX65N_EMAC0_AUTONEG
---help---
If RX65N_EMAC0_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
config RX65N_EMAC0_ETH100MBPS
bool "100 Mbps"
default n
depends on !RX65N_EMAC0_AUTONEG
---help---
If RX65N_EMAC0_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
config RX65N_EMAC0_PHYSR
int "PHY Status Register Address (decimal)"
depends on RX65N_EMAC0_AUTONEG
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
config RX65N_EMAC0_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on RX65N_EMAC0_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
if RX65N_EMAC0_AUTONEG
if RX65N_EMAC0_PHYSR_ALTCONFIG
config RX65N_EMAC0_PHYSR_ALTMODE
hex "PHY Mode Mask"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config RX65N_EMAC0_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config RX65N_EMAC0_PHYSR_100HD
hex "100Base-T Half Duplex Value"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config RX65N_EMAC0_PHYSR_10FD
hex "10Base-T Full Duplex Value"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config RX65N_EMAC0_PHYSR_100FD
hex "100Base-T Full Duplex Value"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
endif # RX65N_EMAC0_PHYSR_ALTCONFIG
if !RX65N_EMAC0_PHYSR_ALTCONFIG
config RX65N_EMAC0_PHYSR_SPEED
hex "PHY Speed Mask"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config RX65N_EMAC0_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config RX65N_EMAC0_PHYSR_MODE
hex "PHY Mode Mask"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides the
bit mask for isolating the full or half duplex mode bits.
config RX65N_EMAC0_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
---help---
This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
endif # !RX65N_EMAC0_PHYSR_ALTCONFIG
endif # RX65N_EMAC0_AUTONEG
# These apply to both EMAC0 and EMAC1 (but are in the EMAC0 menu for now
# because there is not yet any RX65N chip that supports two Ethernet MACS
config RX65N_EMAC0_ISETH0
bool
default y
config RX65N_EMAC_PREALLOCATE
bool "Preallocate buffers"
default n
---help---
Buffer an descriptor many may either be allocated from the memory
pool or pre-allocated to lie in .bss. This options selected pre-
allocated buffer memory.
config RX65N_EMAC_NBC
bool "Disable Broadcast"
default n
---help---
Select to disable receipt of broadcast packets.
config RX65N_EMAC_DEBUG
bool "Force EMAC0/1 DEBUG"
default n
depends on DEBUG_FEATURES && !DEBUG_NET
---help---
This option will force debug output from EMAC driver even without
network debug output enabled. This is not normally something
that would want to do but is convenient if you are debugging the
driver and do not want to get overloaded with other
network-related debug output.
config RX65N_EMAC_REGDEBUG
bool "Register-Level Debug"
default y
depends on DEBUG_NET
---help---
Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET.
endmenu # EMAC0 device driver options

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##############################################################################
# arch/renesas/src/rx65n/Make.defs
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
##############################################################################
HEAD_ASRC = rx65n_head.S
CMN_ASRCS =
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_interruptcontext.c up_lowputs.c up_mdelay.c up_puts.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c
CHIP_ASRCS = rx65n_vector.S
CHIP_CSRCS = rx65n_lowputc.c rx65n_serial.c rx65n_copystate.c rx65n_irq.c
CHIP_CSRCS += rx65n_schedulesigaction.c rx65n_sigdeliver.c rx65n_initialstate.c
CHIP_CSRCS += rx65n_hardware_setup.c rx65n_icu.c rx65n_port.c rx65n_sci.c
CHIP_CSRCS += rx65n_cgc.c rx65n_dumpstate.c rx65n_vector_table.c
CHIP_CSRCS += rx65n_timerisr.c
ifeq ($(CONFIG_RX65N_EMAC),y)
CHIP_CSRCS += rx65n_eth.c rx65n_cmtw0.c
endif

72
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/****************************************************************************
* arch/renesas/src/rx65n/chip.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CHIP_H
#define __ARCH_RENESAS_SRC_RX65N_CHIP_H
#ifndef __ASSEMBLY__
/****************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h>
#ifdef CONFIG_ARCH_CHIP_R5F565NEDDF
# include "rx65n_definitions.h"
#endif
#include "rx65n_definitions.h"
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/****************************************************************************
* Public Types
***************************************************************************/
/***************************************************************************
* Public Data
**************************************************************************/
#ifndef __ASSEMBLY__
extern uint16_t ebss;
#endif
/**************************************************************************
* Public Functions
*************************************************************************/
#endif
#endif /* __ARCH_RENESAS_SRC_SH1_CHIP_H */

230
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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cgc.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_cgc.h"
#include "arch/board/board.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: r_cgc_create
*
* Description:
* Clock generator Initialization
****************************************************************************/
void r_cgc_create(void)
{
#if ((24 * RX_CLK_1MHz) == RX_RESONATOR)
/* Set main clock control registers */
SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR |
_00_CGC_MAINOSC_UNDER24M;
SYSTEM.MOSCWTCR.BYTE = _5C_CGC_MOSCWTCR_VALUE;
/* Set main clock operation */
SYSTEM.MOSCCR.BIT.MOSTP = 0u;
/* Wait for main clock oscillator wait counter overflow */
while (1u != SYSTEM.OSCOVFSR.BIT.MOOVF)
{
/* Do nothing */
}
/* Set system clock */
SYSTEM.SCKCR.LONG = _00000002_CGC_PCLKD_DIV_4 | _00000020_CGC_PCLKC_DIV_4 |
_00000200_CGC_PCLKB_DIV_4 | _00001000_CGC_PCLKA_DIV_2 |
_00010000_CGC_BCLK_DIV_2 | _01000000_CGC_ICLK_DIV_2 |
_20000000_CGC_FCLK_DIV_4;
/* Set PLL circuit */
SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 |
_0000_CGC_PLL_SOURCE_MAIN |
_1300_CGC_PLL_FREQ_MUL_10_0;
SYSTEM.PLLCR2.BIT.PLLEN = 0u;
/* Wait for PLL wait counter overflow */
while (1u != SYSTEM.OSCOVFSR.BIT.PLOVF)
{
/* Do nothing */
}
/* Stop sub-clock */
RTC.RCR3.BIT.RTCEN = 0u;
/* Wait for the register modification to complete */
while (0u != RTC.RCR3.BIT.RTCEN)
{
/* Do nothing */
}
/* Stop sub-clock */
SYSTEM.SOSCCR.BIT.SOSTP = 1u;
/* Wait for the register modification to complete */
while (1u != SYSTEM.SOSCCR.BIT.SOSTP)
{
/* Do nothing */
}
/* Wait for sub-clock oscillation stopping */
while (0u != SYSTEM.OSCOVFSR.BIT.SOOVF)
{
/* Do nothing */
}
/* Set UCLK */
SYSTEM.SCKCR2.WORD = _0040_CGC_UCLK_DIV_5 | _0001_SCKCR2_BIT0;
/* Set ROM wait cycle */
SYSTEM.ROMWT.BYTE = _02_CGC_ROMWT_CYCLE_2;
/* Set SDCLK */
SYSTEM.SCKCR.BIT.PSTOP0 = 1U;
/* Set clock source */
SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL;
/* Set LOCO */
SYSTEM.LOCOCR.BIT.LCSTP = 1U;
#elif ((12 * RX_CLK_1MHz) == RX_RESONATOR)
SYSTEM.MOFCR.BIT.MOFXIN = 0;
SYSTEM.MOFCR.BIT.MOSEL = 0;
if (1 == SYSTEM.HOCOCR.BIT.HCSTP)
{
SYSTEM.HOCOPCR.BYTE = 0x01;
}
else
{
while (0 == SYSTEM.OSCOVFSR.BIT.HCOVF);
}
SYSTEM.MOFCR.BIT.MODRV2 = 2;
SYSTEM.MOSCWTCR.BYTE = 0x53;
SYSTEM.MOSCCR.BYTE = 0x00;
if (0x00 == SYSTEM.MOSCCR.BYTE)
{
__asm("nop");
}
while (0 == SYSTEM.OSCOVFSR.BIT.MOOVF);
if (0 == SYSTEM.RSTSR1.BIT.CWSF)
{
volatile uint8_t i;
RTC.RCR4.BIT.RCKSEL = 0;
for (i = 0; i < 4; i++)
{
__asm("nop");
}
if (0 != RTC.RCR4.BIT.RCKSEL)
{
__asm("nop");
}
RTC.RCR3.BIT.RTCEN = 0;
for (i = 0; i < 4; i++)
{
__asm("nop");
}
if (0 != RTC.RCR3.BIT.RTCEN)
{
__asm("nop");
}
SYSTEM.SOSCCR.BYTE = 0x01;
if (0x01 != SYSTEM.SOSCCR.BYTE)
{
__asm("nop");
}
while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF);
}
else
{
SYSTEM.SOSCCR.BYTE = 0x01;
if (0x01 != SYSTEM.SOSCCR.BYTE)
{
__asm("nop");
}
while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF);
}
SYSTEM.PLLCR.BIT.PLIDIV = 0;
SYSTEM.PLLCR.BIT.PLLSRCSEL = 0;
SYSTEM.PLLCR.BIT.STC = (20 * 2) - 1;
SYSTEM.PLLCR2.BYTE = 0x00;
while (0 == SYSTEM.OSCOVFSR.BIT.PLOVF);
SYSTEM.ROMWT.BYTE = 0x02;
if (0x02 == SYSTEM.ROMWT.BYTE)
{
__asm("nop");
}
SYSTEM.SCKCR.LONG = 0x21c11222;
SYSTEM.SCKCR2.WORD = 0x0011;
SYSTEM.SCKCR3.WORD = 4u << 8; /* BSP_CFG_CLOCK_SOURCE */
SYSTEM.LOCOCR.BYTE = 0x01;
#else
# error "RX_RESONATOR is not defined in board.h"
#endif
}

295
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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cgc.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CGC_H
#define __ARCH_RENESAS_SRC_RX65N_CGC_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System Clock Control Register (SCKCR) */
/* Peripheral Module Clock D (PCLKD) */
#define _00000000_CGC_PCLKD_DIV_1 (0x00000000ul) /* x1 */
#define _00000001_CGC_PCLKD_DIV_2 (0x00000001ul) /* x1/2 */
#define _00000002_CGC_PCLKD_DIV_4 (0x00000002ul) /* x1/4 */
#define _00000003_CGC_PCLKD_DIV_8 (0x00000003ul) /* x1/8 */
#define _00000004_CGC_PCLKD_DIV_16 (0x00000004ul) /* x1/16 */
#define _00000005_CGC_PCLKD_DIV_32 (0x00000005ul) /* x1/32 */
#define _00000006_CGC_PCLKD_DIV_64 (0x00000006ul) /* x1/64 */
/* Peripheral Module Clock C (PCLKC) */
#define _00000000_CGC_PCLKC_DIV_1 (0x00000000ul) /* x1 */
#define _00000010_CGC_PCLKC_DIV_2 (0x00000010ul) /* x1/2 */
#define _00000020_CGC_PCLKC_DIV_4 (0x00000020ul) /* x1/4 */
#define _00000030_CGC_PCLKC_DIV_8 (0x00000030ul) /* x1/8 */
#define _00000040_CGC_PCLKC_DIV_16 (0x00000040ul) /* x1/16 */
#define _00000050_CGC_PCLKC_DIV_32 (0x00000050ul) /* x1/32 */
#define _00000060_CGC_PCLKC_DIV_64 (0x00000060ul) /* x1/64 */
/* Peripheral Module Clock B (PCLKB) */
#define _00000000_CGC_PCLKB_DIV_1 (0x00000000ul) /* x1 */
#define _00000100_CGC_PCLKB_DIV_2 (0x00000100ul) /* x1/2 */
#define _00000200_CGC_PCLKB_DIV_4 (0x00000200ul) /* x1/4 */
#define _00000300_CGC_PCLKB_DIV_8 (0x00000300ul) /* x1/8 */
#define _00000400_CGC_PCLKB_DIV_16 (0x00000400ul) /* x1/16 */
#define _00000500_CGC_PCLKB_DIV_32 (0x00000500ul) /* x1/32 */
#define _00000600_CGC_PCLKB_DIV_64 (0x00000600ul) /* x1/64 */
/* Peripheral Module Clock A (PCLKA) */
#define _00000000_CGC_PCLKA_DIV_1 (0x00000000ul) /* x1 */
#define _00001000_CGC_PCLKA_DIV_2 (0x00001000ul) /* x1/2 */
#define _00002000_CGC_PCLKA_DIV_4 (0x00002000ul) /* x1/4 */
#define _00003000_CGC_PCLKA_DIV_8 (0x00003000ul) /* x1/8 */
#define _00004000_CGC_PCLKA_DIV_16 (0x00004000ul) /* x1/16 */
#define _00005000_CGC_PCLKA_DIV_32 (0x00005000ul) /* x1/32 */
#define _00006000_CGC_PCLKA_DIV_64 (0x00006000ul) /* x1/64 */
/* External Bus Clock (BCLK) */
#define _00000000_CGC_BCLK_DIV_1 (0x00000000ul) /* x1 */
#define _00010000_CGC_BCLK_DIV_2 (0x00010000ul) /* x1/2 */
#define _00020000_CGC_BCLK_DIV_4 (0x00020000ul) /* x1/4 */
#define _00030000_CGC_BCLK_DIV_8 (0x00030000ul) /* x1/8 */
#define _00040000_CGC_BCLK_DIV_16 (0x00040000ul) /* x1/16 */
#define _00050000_CGC_BCLK_DIV_32 (0x00050000ul) /* x1/32 */
#define _00060000_CGC_BCLK_DIV_64 (0x00060000ul) /* x1/64 */
/* System Clock (ICLK) */
#define _00000000_CGC_ICLK_DIV_1 (0x00000000ul) /* x1 */
#define _01000000_CGC_ICLK_DIV_2 (0x01000000ul) /* x1/2 */
#define _02000000_CGC_ICLK_DIV_4 (0x02000000ul) /* x1/4 */
#define _03000000_CGC_ICLK_DIV_8 (0x03000000ul) /* x1/8 */
#define _04000000_CGC_ICLK_DIV_16 (0x04000000ul) /* x1/16 */
#define _05000000_CGC_ICLK_DIV_32 (0x05000000ul) /* x1/32 */
#define _06000000_CGC_ICLK_DIV_64 (0x06000000ul) /* x1/64 */
/* System Clock (FCLK) */
#define _00000000_CGC_FCLK_DIV_1 (0x00000000ul) /* x1 */
#define _10000000_CGC_FCLK_DIV_2 (0x10000000ul) /* x1/2 */
#define _20000000_CGC_FCLK_DIV_4 (0x20000000ul) /* x1/4 */
#define _30000000_CGC_FCLK_DIV_8 (0x30000000ul) /* x1/8 */
#define _40000000_CGC_FCLK_DIV_16 (0x40000000ul) /* x1/16 */
#define _50000000_CGC_FCLK_DIV_32 (0x50000000ul) /* x1/32 */
#define _60000000_CGC_FCLK_DIV_64 (0x60000000ul) /* x1/64 */
/* ROM Wait Cycle Setting Register (ROMWT) */
/* ROM Wait Cycle Setting (ROMWT) */
#define _00_CGC_ROMWT_CYCLE_0 (0x00u) /* No wait */
#define _01_CGC_ROMWT_CYCLE_1 (0x01u) /* One wait cycle */
#define _02_CGC_ROMWT_CYCLE_2 (0x02u) /* Two wait cycles */
/* System Clock Control Register 2 (SCKCR2) */
#define _0010_CGC_UCLK_DIV_1 (0x0010u) /* x1/2 */
#define _0020_CGC_UCLK_DIV_3 (0x0020u) /* x1/3 */
#define _0030_CGC_UCLK_DIV_4 (0x0030u) /* x1/4 */
#define _0040_CGC_UCLK_DIV_5 (0x0040u) /* x1/5 */
#define _0001_SCKCR2_BIT0 (0x0001u) /* RESERVE BIT0 */
/* System Clock Control Register 3 (SCKCR3) */
#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000u) /* LOCO */
#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100u) /* HOCO */
#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200u) /* Main clock oscillator */
#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300u) /* Sub-clock oscillator */
#define _0400_CGC_CLOCKSOURCE_PLL (0x0400u) /* PLL circuit */
/* PLL Control Register (PLLCR) */
/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000u) /* x1 */
#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001u) /* x1/2 */
#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002u) /* x1/3 */
/* PLL Clock Source Select (PLLSRCSEL) */
#define _0000_CGC_PLL_SOURCE_MAIN (0x0000u) /* Main clock oscillator */
#define _0010_CGC_PLL_SOURCE_HOCO (0x0010u) /* HOCO */
/* Frequency Multiplication Factor Select (STC[5:0]) */
#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300u) /* x10.0 */
#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400u) /* x10.5 */
#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500u) /* x11.0 */
#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600u) /* x11.5 */
#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700u) /* x12.0 */
#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800u) /* x12.5 */
#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900u) /* x13.0 */
#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1a00u) /* x13.5 */
#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1b00u) /* x14.0 */
#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1c00u) /* x14.5 */
#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1d00u) /* x15.0 */
#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1e00u) /* x15.5 */
#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1f00u) /* x16.0 */
#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000u) /* x16.5 */
#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100u) /* x17.0 */
#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200u) /* x17.5 */
#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300u) /* x18.0 */
#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400u) /* x18.5 */
#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500u) /* x19.0 */
#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600u) /* x19.5 */
#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700u) /* x20.0 */
#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800u) /* x20.5 */
#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900u) /* x21.0 */
#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2a00u) /* x21.5 */
#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2b00u) /* x22.0 */
#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2c00u) /* x22.5 */
#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2d00u) /* x23.0 */
#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2e00u) /* x23.5 */
#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2f00u) /* x24.0 */
#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000u) /* x24.5 */
#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100u) /* x25.0 */
#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200u) /* x25.5 */
#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300u) /* x26.0 */
#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400u) /* x26.5 */
#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500u) /* x27.0 */
#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600u) /* x27.5 */
#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700u) /* x28.0 */
#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800u) /* x28.5 */
#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900u) /* x29.0 */
#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3a00u) /* x29.5 */
#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3b00u) /* x30.0 */
/* Oscillation Stop Detection Control Register (OSTDCR) */
/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
/* The oscillation stop detection interrupt is disabled */
#define _00_CGC_OSC_STOP_INT_DISABLE (0x00u)
/* The oscillation stop detection interrupt is enabled */
#define _01_CGC_OSC_STOP_INT_ENABLE (0x01u)
/* Oscillation Stop Detection Function Enable (OSTDE) */
/* Oscillation stop detection function is disabled */
#define _00_CGC_OSC_STOP_DISABLE (0x00u)
/* Oscillation stop detection function is enabled */
#define _80_CGC_OSC_STOP_ENABLE (0x80u)
/* High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) */
/* HOCO Frequency Setting (HCFRQ[1:0]) */
#define _00_CGC_HOCO_CLK_16 (0x00u) /* 16 MHz */
#define _01_CGC_HOCO_CLK_18 (0x01u) /* 18 MHz */
#define _02_CGC_HOCO_CLK_20 (0x02u) /* 20 MHz */
/* Main Clock Oscillator Forced Oscillation Control Register (MOFCR) */
/* Main Clock Oscillator Forced Oscillation (MOFXIN) */
/* Oscillator is not controlled by this bit */
#define _00_CGC_MAINOSC_NOT_CONTROLLED (0x00u)
/* The main clock oscillator is forcedly oscillated */
#define _01_CGC_MAINOSC_FORCE_OSCILLATED (0x01u)
/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */
#define _00_CGC_MAINOSC_UNDER24M (0x00u) /* 20.1 to 24 MHz */
#define _10_CGC_MAINOSC_UNDER20M (0x10u) /* 16.1 to 20 MHz */
#define _20_CGC_MAINOSC_UNDER16M (0x20u) /* 8.1 to 16 MHz */
#define _30_CGC_MAINOSC_EQUATE8M (0x30u) /* 8 MHz */
/* Main Clock Oscillator Switch (MOSEL) */
#define _00_CGC_MAINOSC_RESONATOR (0x00u) /* Resonator */
#define _40_CGC_MAINOSC_EXTERNAL (0x40u) /* External oscillator input */
/* RTC Control Register 4 (RCR4) */
/* Count source select (RCKSEL) */
#define _00_RTC_SOURCE_SELECT_SUB (0x00u) /* Select sub-clock oscillator */
#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01u) /* Select main clock oscillator */
/* Interrupt Source Priority Register n (IPRn) */
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_CGC_PRIORITY_LEVEL0 (0x00u) /* Level 0 (interrupt disabled) */
#define _01_CGC_PRIORITY_LEVEL1 (0x01u) /* Level 1 */
#define _02_CGC_PRIORITY_LEVEL2 (0x02u) /* Level 2 */
#define _03_CGC_PRIORITY_LEVEL3 (0x03u) /* Level 3 */
#define _04_CGC_PRIORITY_LEVEL4 (0x04u) /* Level 4 */
#define _05_CGC_PRIORITY_LEVEL5 (0x05u) /* Level 5 */
#define _06_CGC_PRIORITY_LEVEL6 (0x06u) /* Level 6 */
#define _07_CGC_PRIORITY_LEVEL7 (0x07u) /* Level 7 */
#define _08_CGC_PRIORITY_LEVEL8 (0x08u) /* Level 8 */
#define _09_CGC_PRIORITY_LEVEL9 (0x09u) /* Level 9 */
#define _0A_CGC_PRIORITY_LEVEL10 (0x0au) /* Level 10 */
#define _0B_CGC_PRIORITY_LEVEL11 (0x0bu) /* Level 11 */
#define _0C_CGC_PRIORITY_LEVEL12 (0x0cu) /* Level 12 */
#define _0D_CGC_PRIORITY_LEVEL13 (0x0du) /* Level 13 */
#define _0E_CGC_PRIORITY_LEVEL14 (0x0eu) /* Level 14 */
#define _0F_CGC_PRIORITY_LEVEL15 (0x0fu) /* Level 15 (highest) */
/* Main clock oscillator wait time */
#define _5C_CGC_MOSCWTCR_VALUE (0x5cu)
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
/****************************************************************************
* Name: r_cgc_create
*
* Description:
* Clock Initialization
****************************************************************************/
void r_cgc_create(void);
#endif

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmt.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMT_H
#define __ARCH_RENESAS_SRC_RX65N_CMT_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Compare Match Timer Control Register (CMCR) */
/* Interrupt Source Priority Register n (IPRn) */
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_CMT_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */
#define _01_CMT_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
#define _02_CMT_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
#define _03_CMT_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
#define _04_CMT_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
#define _05_CMT_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
#define _06_CMT_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
#define _07_CMT_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
#define _08_CMT_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
#define _09_CMT_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
#define _0A_CMT_PRIORITY_LEVEL10 (0x0aU) /* Level 10 */
#define _0B_CMT_PRIORITY_LEVEL11 (0x0bU) /* Level 11 */
#define _0C_CMT_PRIORITY_LEVEL12 (0x0cU) /* Level 12 */
#define _0D_CMT_PRIORITY_LEVEL13 (0x0dU) /* Level 13 */
#define _0E_CMT_PRIORITY_LEVEL14 (0x0eU) /* Level 14 */
#define _0F_CMT_PRIORITY_LEVEL15 (0x0fU) /* Level 15 (highest) */
#endif /* __ARCH_RENESAS_SRC_RX65N_CMT_H */

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Surya Prakash <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW_H
#define __ARCH_RENESAS_SRC_RX65N_CMTW_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Timer Start Register (CMWSTR) */
#define _0000_CMTW_CMWSTR_COUNTER_STOP (0x0000U) /* Stop counter count */
#define _0001_CMTW_CMWSTR_COUNTER_START (0x0001U) /* Start counter count */
/* Timer Control Register (CMWCR) */
/* Clock select (CKS[1:0]) */
#define _0000_CMTW_CMWCR_CLOCK_PCLK8 (0x0000U) /* PCLK/8 */
#define _0001_CMTW_CMWCR_CLOCK_PCLK32 (0x0001U) /* PCLK/32 */
#define _0002_CMTW_CMWCR_CLOCK_PCLK128 (0x0002U) /* PCLK/128 */
#define _0003_CMTW_CMWCR_CLOCK_PCLK512 (0x0003U) /* PCLK/512 */
/* Compare Match Interrupt Enable (CMWIE) */
/* Disable Compare Match Interrupt */
#define _0000_CMTW_CMWCR_CMWIE_DISABLE (0x0000U)
/* Enable Compare Match Interrupt */
#define _0008_CMTW_CMWCR_CMWIE_ENABLE (0x0008U)
/* Input Capture 0 Interrupt Enable (IC0IE) */
/* Disable Input Capture 0 Interrupt */
#define _0000_CMTW_CMWCR_IC0IE_DISABLE (0x0000U)
/* Enable Input Capture 0 Interrupt */
#define _0010_CMTW_CMWCR_IC0IE_ENABLE (0x0010U)
/* Input Capture 1 Interrupt Enable (IC1IE) */
/* Disable Input Capture 1 Interrupt */
#define _0000_CMTW_CMWCR_IC1IE_DISABLE (0x0000U)
/* Enable Input Capture 1 Interrupt */
#define _0020_CMTW_CMWCR_IC1IE_ENABLE (0x0020U)
/* Output Compare 0 Interrupt Enable (OC0IE) */
/* Disable Output Compare 0 Interrupt */
#define _0000_CMTW_CMWCR_OC0IE_DISABLE (0x0000U)
/* Enable Output Compare 0 Interrupt */
#define _0040_CMTW_CMWCR_OC0IE_ENABLE (0x0040U)
/* Output Compare 1 Interrupt Enable (OC1IE) */
/* Disable Output Compare 1 Interrupt */
#define _0000_CMTW_CMWCR_OC1IE_DISABLE (0x0000U)
/* Enable Output Compare 1 Interrupt */
#define _0080_CMTW_CMWCR_OC1IE_ENABLE (0x0080U)
/* Timer Counter Size (CMS) */
#define _0000_CMTW_CMWCR_COUNTER_SIZE_32 (0x0000U) /* 32 bits */
#define _0200_CMTW_CMWCR_COUNTER_SIZE_16 (0x0200U) /* 16 bits */
/* Counter Clear (CCLR[2:0]) */
/* CMWCNT counter cleared by CMWCOR */
#define _0000_CMTW_CMWCR_CCLR_ENABLE_CMWCOR (0x6000U)
/* Clearing of CMWCNT counter disabled */
#define _2000_CMTW_CMWCR_CCLR_DISABLE (0x2000U)
/* Clearing of CMWCNT counter disabled */
#define _4000_CMTW_CMWCR_CCLR_DISABLE (0x4000U)
/* Clearing of CMWCNT counter disabled */
#define _6000_CMTW_CMWCR_CCLR_DISABLE (0x6000U)
/* CMWCNT counter cleared by CMWICR0 */
#define _8000_CMTW_CMWCR_CCLR_CMWICR0_ENABLE (0x8000U)
/* CMWCNT counter cleared by CMWICR1 */
#define _A000_CMTW_CMWCR_CCLR_CMWICR1_ENABLE (0xa000U)
/* CMWCNT counter cleared by CMWOCR0 */
#define _C000_CMTW_CMWCR_CCLR_CMWOCR0_ENABLE (0xc000U)
/* CMWCNT counter cleared by CMWOCR1 */
#define _E000_CMTW_CMWCR_CCLR_CMWOCR1_ENABLE (0xe000U)
/* Timer I/O Control Register (CMWIOR) */
/* Input Compare Control 0 (IC0[1:0]) */
#define _0000_CMTW_CMWIOR_IC0_RISE (0x0000U) /* Rising edge */
#define _0001_CMTW_CMWIOR_IC0_FALL (0x0001U) /* Falling edge */
#define _0002_CMTW_CMWIOR_IC0_BOTH (0x0002U) /* Both edges */
/* Input Capture Control 1 (IC1[1:0]) */
#define _0000_CMTW_CMWIOR_IC1_RISE (0x0000U) /* Rising edge */
#define _0004_CMTW_CMWIOR_IC1_FALL (0x0004U) /* Falling edge */
#define _0008_CMTW_CMWIOR_IC1_BOTH (0x0008U) /* Both edges */
/* Input Capture Enable 0 (IC0E) */
/* Disable input capture of CMWICR0 */
#define _0000_CMTW_CMWIOR_IC0E_DISABLE (0x0000U)
/* Enable input capture of CMWICR0 */
#define _0010_CMTW_CMWIOR_IC0E_ENABLE (0x0010U)
/* Input Capture Enable 1 (IC1E) */
/* Disable input capture of CMWICR1 */
#define _0000_CMTW_CMWIOR_IC1E_DISABLE (0x0000U)
/* Enable input capture of CMWICR1 */
#define _0020_CMTW_CMWIOR_IC1E_ENABLE (0x0020U)
/* Output Compare Control 0 (OC0[1:0]) */
/* Retains the output value */
#define _0000_CMTW_CMWIOR_OC0_RETAIN (0x0000U)
/* Initially outputs 0 */
#define _0100_CMTW_CMWIOR_OC0_OUTPUT0 (0x0100U)
/* Initially outputs 1 */
#define _0200_CMTW_CMWIOR_OC0_OUTPUT1 (0x0200U)
/* Output Compare Control 1 (OC1[1:0]) */
/* Retains the output value */
#define _0000_CMTW_CMWIOR_OC1_RETAIN (0x0000U)
/* Initially outputs 0 */
#define _0400_CMTW_CMWIOR_OC1_OUTPUT0 (0x0400U)
/* Initially outputs 1 */
#define _0800_CMTW_CMWIOR_OC1_OUTPUT1 (0x0800U)
/* Compare Match Enable 0 (OC0E) */
/* Disable compare match using CMWOCR0 */
#define _0000_CMTW_CMWIOR_OC0E_DISABLE (0x0000U)
/* Enable compare match using CMWOCR0 */
#define _1000_CMTW_CMWIOR_OC0E_ENABLE (0x1000U)
/* Compare Match Enable 1 (OC1E) */
/* Disable compare match using CMWOCR1 */
#define _0000_CMTW_CMWIOR_OC1E_DISABLE (0x0000U)
/* Enable compare match using CMWOCR1 */
#define _2000_CMTW_CMWIOR_OC1E_ENABLE (0x2000U)
/* Compare Match Enable (CMWE) */
/* Disable compare match using CMWCOR */
#define _0000_CMTW_CMWIOR_CMWE_DISABLE (0x0000U)
/* Enable compare match using CMWCOR */
#define _8000_CMTW_CMWIOR_CMWE_ENABLE (0x8000U)
/* Interrupt Source Priority Register n (IPRn) */
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_CMTW_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */
#define _01_CMTW_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
#define _02_CMTW_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
#define _03_CMTW_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
#define _04_CMTW_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
#define _05_CMTW_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
#define _06_CMTW_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
#define _07_CMTW_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
#define _08_CMTW_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
#define _09_CMTW_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
#define _0A_CMTW_PRIORITY_LEVEL10 (0x0aU) /* Level 10 */
#define _0B_CMTW_PRIORITY_LEVEL11 (0x0bU) /* Level 11 */
#define _0C_CMTW_PRIORITY_LEVEL12 (0x0cU) /* Level 12 */
#define _0D_CMTW_PRIORITY_LEVEL13 (0x0dU) /* Level 13 */
#define _0E_CMTW_PRIORITY_LEVEL14 (0x0eU) /* Level 14 */
#define _0F_CMTW_PRIORITY_LEVEL15 (0x0fU) /* Level 15 (highest) */
#endif /* __ARCH_RENESAS_SRC_RX65N_CMTW_H */

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw0.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author:Surya Prakash <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include <string.h>
#include <debug.h>
#include <queue.h>
#include <errno.h>
#include "rx65n_cmtw0.h"
#include "rx65n/iodefine.h"
#include "rx65n/irq.h"
#include "rx65n_definitions.h"
#include <nuttx/irq.h>
#include "rx65n_eth.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rx65n_cmtw0_create
*
* Description:
* CMTW0 Timer Initialization
****************************************************************************/
void rx65n_cmtw0_create(uint32_t txpoll_time, uint32_t txtimeout_time)
{
/* Disable OC0I0 interrupt */
IEN(PERIB, INTB170) = 0U;
/* Disable OC1I0 interrupt */
IEN(PERIB, INTB171) = 0U;
/* Cancel CMTW stop state in LPC */
MSTP(CMTW0) = 0U;
/* Stop CMTW0 count */
CMTW0.CMWSTR.BIT.STR = 0U;
/* Set timer I/O control register */
CMTW0.CMWIOR.WORD = _1000_CMTW_CMWIOR_OC0E_ENABLE |
_0000_CMTW_CMWIOR_OC0_RETAIN |
_2000_CMTW_CMWIOR_OC1E_ENABLE |
_0000_CMTW_CMWIOR_OC1_RETAIN |
_8000_CMTW_CMWIOR_CMWE_ENABLE;
/* Set compare match register */
CMTW0.CMWCOR = _000000BB_CMTW0_CMWCOR_VALUE;
/* Set output compare register 0 */
CMTW0.CMWOCR0 = txpoll_time;
/* Set output compare register 1 */
CMTW0.CMWOCR1 = txtimeout_time;
/* Set control registers */
CMTW0.CMWCR.WORD = _0001_CMTW_CMWCR_CLOCK_PCLK32 |
_0040_CMTW_CMWCR_OC0IE_ENABLE |
_0080_CMTW_CMWCR_OC1IE_ENABLE |
_0000_CMTW_CMWCR_COUNTER_SIZE_32 |
_0000_CMTW_CMWCR_CCLR_ENABLE_CMWCOR;
/* Set OC0I0 interrupt and priority level */
ICU.SLIBR170.BYTE = 0x2bu;
IPR(PERIB, INTB170) = _0F_CMTW_PRIORITY_LEVEL15;
/* Set OC1I0 interrupt and priority level */
ICU.SLIBR171.BYTE = 0x2cu;
IPR(PERIB, INTB171) = _0F_CMTW_PRIORITY_LEVEL15;
/* Set TIC0 pin */
MPC.PC6PFS.BYTE = 0x1du;
PORTC.PMR.BYTE |= 0x40u;
/* Set TIC1 pin */
MPC.PE6PFS.BYTE = 0x1du;
PORTE.PMR.BYTE |= 0x40u;
/* Set TOC0 pin */
MPC.PC7PFS.BYTE = 0x1du;
PORTC.PMR.BYTE |= 0x80u;
/* Set TOC1 pin */
MPC.PE7PFS.BYTE = 0x1du;
PORTE.PMR.BYTE |= 0x80u;
/* Attach the IRQ for poll expiry */
irq_attach(RX65N_INTB170_IRQ, (xcpt_t)rx65n_poll_expiry, NULL);
/* Attach the IRQ for tx timeout */
irq_attach(RX65N_INTB171_IRQ, (xcpt_t)rx65n_txtimeout_expiry, NULL);
}
/****************************************************************************
* Name: rx65n_cmtw0_start
*
* Description:
* CMTW0 Timer Initialization
****************************************************************************/
void rx65n_cmtw0_start(uint8_t type, uint32_t timeout)
{
/* Update OC0I0 for polling */
if (type == rx65n_cmtw0_txpoll)
{
CMTW0.CMWOCR0 = CMTW0.CMWCNT + timeout;
/* Enable OC0I0 interrupt in ICU */
IEN(PERIB, INTB170) = 1U;
/* Enabling OC0 */
CMTW0.CMWIOR.WORD |= _1000_CMTW_CMWIOR_OC0E_ENABLE;
}
/* Update OC0I1 for timeout */
if (type == rx65n_cmtw0_timeout)
{
CMTW0.CMWOCR1 = CMTW0.CMWCNT + timeout;
/* Enable OC1I0 interrupt in ICU */
IEN(PERIB, INTB171) = 1U;
/* Enabling OC1 */
CMTW0.CMWIOR.WORD |= _2000_CMTW_CMWIOR_OC1E_ENABLE;
}
/* Start CMTW0 count */
CMTW0.CMWSTR.BIT.STR = 1U;
}
/****************************************************************************
* Name: rx65n_cmtw0_stop
*
* Description:
* CMTW0 Timer Initialization
****************************************************************************/
void rx65n_cmtw0_stop(uint8_t type)
{
/* STOP OC0I0 fot polling */
if (type == rx65n_cmtw0_txpoll)
{
/* Disable OC0I0 interrupt in ICU */
IEN(PERIB, INTB170) = 0U;
/* Enabling OC0 */
CMTW0.CMWIOR.WORD &= ~(_1000_CMTW_CMWIOR_OC0E_ENABLE);
}
/* Stop OC0I1 fot timeout */
if (type == rx65n_cmtw0_timeout)
{
/* Disable OC1I0 interrupt in ICU */
IEN(PERIB, INTB171) = 0U;
/* Disabling OC1 */
CMTW0.CMWIOR.WORD &= ~(_2000_CMTW_CMWIOR_OC1E_ENABLE);
}
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw0.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Surya Prakash <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW0_H
#define __ARCH_RENESAS_SRC_RX65N_CMTW0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_cmtw.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Compare Match Constant Register (CMWCOR) */
#define _000000BB_CMTW0_CMWCOR_VALUE (0xfffffffful)
/* Output Compare Registers 0 (CMWOCR0) */
#define _0000000A_CMTW0_CMWOCR0_VALUE (0x0000000aul)
/* Output Compare Registers 1 (CMWOCR1) */
#define _0000000A_CMTW0_CMWOCR1_VALUE (0x0000000aul)
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
/****************************************************************************
* Name: rx65n_cmtw0_create
*
* Description:
* Initializes CMTW0 Timer
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void rx65n_cmtw0_create(uint32_t txpoll_time, uint32_t txtimeout_time);
/****************************************************************************
* Name: rx65n_cmtw0_start
*
* Description:
* Start CMTW0 Timer
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void rx65n_cmtw0_start(uint8_t type, uint32_t timeout);
/****************************************************************************
* Name: rx65n_cmtw0_stop
*
* Description:
* Stop CMTW0 Timer
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void rx65n_cmtw0_stop(uint8_t type);
#endif /* __ARCH_RENESAS_SRC_RX65N_CMTW0_H */

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/****************************************************************************
* arch/renesas/src/rx65n/up_copystate.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <arch/irq.h>
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_copystate
****************************************************************************/
/* A little faster than most memcpy's */
void up_copystate(uint32_t *dest, uint32_t *src)
{
memcpy(dest, src, XCPTCONTEXT_SIZE);
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_definitions.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Surya <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_DEFINITIONS_H
#define __ARCH_RENESAS_SRC_RX65N_RX65N_DEFINITIONS_H
/****************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h>
#include "rx65n/iodefine.h"
#include "arch/board/board.h"
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Memory-mapped register addresses ****************************************/
#define RX65N_SCI0_BASE (uint32_t)&SCI0
#define RX65N_SCI1_BASE (uint32_t)&SCI1
#define RX65N_SCI2_BASE (uint32_t)&SCI2
#define RX65N_SCI3_BASE (uint32_t)&SCI3
#define RX65N_SCI4_BASE (uint32_t)&SCI4
#define RX65N_SCI5_BASE (uint32_t)&SCI5
#define RX65N_SCI6_BASE (uint32_t)&SCI6
#define RX65N_SCI7_BASE (uint32_t)&SCI7
#define RX65N_SCI8_BASE (uint32_t)&SCI8
#define RX65N_SCI9_BASE (uint32_t)&SCI9
#define RX65N_SCI10_BASE (uint32_t)&SCI10
#define RX65N_SCI11_BASE (uint32_t)&SCI11
#define RX65N_SCI12_BASE (uint32_t)&SCI12
/* Serial Communications interface (SCI) */
#define RX_SCISMR_CKSMASK (0x03) /* Bit 0-1: Internal clock source */
#define RX_SCISMR_DIV1 (0x00) /* System clock (phi) */
#define RX_SCISMR_DIV4 (0x01) /* phi/4 */
#define RX_SCISMR_DIV16 (0x02) /* phi/16 */
#define RX_SCISMR_DIV64 (0x03) /* phi/64 */
#define RX_SCISMR_MP (0x04) /* Bit 2: Multiprocessor select */
#define RX_SCISMR_STOP (0x08) /* Bit 3: 0:One stop bit, 1:Two stop bits */
#define RX_SCISMR_OE (0x10) /* Bit 4: 0:Even parity, 1:Odd parity */
#define RX_SCISMR_PE (0x20) /* Bit 5: Parity enable */
#define RX_SCISMR_CHR (0x40) /* Bit 6: 0:8-bit data, 1:7-bit data */
#define RX_SCISMR_CA (0x80) /* Bit 7: 0:Asynchronous, 1:clocked synchronous */
#define RX_SCISCR_CKEMASK (0x03) /* Bit 0-1: Internal clock source */
/* Asynchronous mode: */
/* Internal clock, SCK pin used for input pin */
#define RX_SCISCR_AISIN (0x00)
/* Internal clock, SCK pin used for clock output */
#define RX_SCISCR_AISOUT (0x01)
/* External clock, SCK pin used for clock input */
#define RX_SCISCR_AXSIN1 (0x02)
/* External clock, SCK pin used for clock input */
#define RX_SCISCR_AXSIN2 (0x03)
/* Synchronous mode: */
/* Internal clock, SCK pin used for clock output */
#define RX_SCISCR_SISOUT2 (0x01)
/* External clock, SCK pin used for clock input */
#define RX_SCISCR_SXSIN1 (0x02)
/* External clock, SCK pin used for clock input */
#define RX_SCISCR_SXSIN2 (0x03)
/* Bit 2: 1=Transmit end interrupt enable */
#define RX_SCISCR_TEIE (0x04)
/* Bit 3: 1=Multiprocessor interrupt enable */
#define RX_SCISCR_MPIE (0x08)
#define RX_SCISCR_RE (0x10) /* Bit 4: 1=Receiver enable */
#define RX_SCISCR_TE (0x20) /* Bit 5: 1=Transmitter enable */
/* Bit 6: 1=Recieve-data-full interrupt enable */
#define RX_SCISCR_RIE (0x40)
/* Bit 7: 1=Transmit-data-empty interrupt enable */
#define RX_SCISCR_TIE (0x80)
#define RX_SCISCR_ALLINTS (0xcc)
/* Bit 0: Multi-processor Bit in Transmit data */
#define RX_SCISSR_MPBT (0x01)
/* Bit 1: Multi-processor Bit in receive data */
#define RX_SCISSR_MPB (0x02)
#define RX_SCISSR_TEND (0x04) /* Bit 2: End of transmission */
#define RX_SCISSR_PER (0x08) /* Bit 3: Receive parity error */
#define RX_SCISSR_FER (0x10) /* Bit 4: Receive framing error */
#define RX_SCISSR_ORER (0x20) /* Bit 5: Receive overrun error */
/* Bit 6: RDR contains valid received data */
#define RX_SCISSR_RDRF (0x40)
/* Bit 7: TDR does not contain valid transmit data */
#define RX_SCISSR_TDRE (0x80)
#define RX65N_CMT_CMSTR0_ADDR (0x00088000) /* 8-bits wide */
#define RX65N_CMT0_CMCNT_ADDR (0x00088004)
#define RX65N_CMT0_CMCOR_ADDR (0x00088006)
#define RX65N_CMT0_CMCR_ADDR (0x00088002)
/* CMTW0 used for Ethernet TX polling and TX timeout */
#define RX65N_CMTW0_CMWSTR_ADDR (0x00094200)
#define RX65N_CMTW0_CMWCR_ADDR (0x00094204)
#define RX65N_CMTW0_CMWIOR_ADDR (0x00094208)
#define RX65N_CMTW0_CMWCNT_ADDR (0x00094210)
#define RX65N_CMTW0_CMWCOR_ADDR (0x00094214)
#define RX65N_CMTW0_CMWICR0_ADDR (0x00094218)
#define RX65N_CMTW0_CMWICR1_ADDR (0x0009421c)
#define RX65N_CMTW0_CMWOCR0_ADDR (0x00094220)
#define RX65N_CMTW0_CMWOCR1_ADDR (0x00094224)
#define RX65N_CMTW0_TICKFREQ (1) /* 1Hz tick frequency */
#define RX65N_CMTW0_DIV_VALUE (32)
#define RX65N_CMTW0_COUNT_VALUE_FOR_TXPOLL ((RX_PCLKB / RX65N_CMTW0_DIV_VALUE)/(RX65N_CMTW0_TICKFREQ))
#define RX65N_CMTW0_COUNT_VALUE_FOR_TXTIMEOUT (((RX_PCLKB / RX65N_CMTW0_DIV_VALUE)/(RX65N_CMTW0_TICKFREQ))*60)
#define rx65n_cmtw0_txpoll 1
#define rx65n_cmtw0_timeout 2
#define RX65N_MSTPCRA_ADDR (0x00080010)
#define RX65N_CMT0_TICKFREQ (100) /* 100Hz tick frequency */
#define RX65N_CMT_DIV32 (0x0001)
#define RX65N_CMT0_DIV_VALUE (32)
#define RX65N_CMT0_COUNT_VALUE ((RX_PCLKB / RX65N_CMT0_DIV_VALUE)/(RX65N_CMT0_TICKFREQ))
#define RX65N_CMT_CMCR_INIT (RX65N_CMT_DIV32 |\
RX65N_CMT_CMCR_CMIE_ENABLE |\
RX65N_CMT_CMCR_DEFAULT)
#define RX65N_CMTW_DIV32 (0x0001)
#define RX65N_CMTW_CMWCR_INIT (RX65N_CMTW_DIV32 |\
RX65N_CMTW_CMWCR_CMWIE_ENABLE |\
RX65N_CMTW_CMWCR_DEFAULT)
#define RX65N_CMTW_CMWCR_DEFAULT (0x0000)
#define RX65N_CMTW_CMWCR_CMWIE_ENABLE (0x0008)
#define RX65N_CMT_CMCR_DEFAULT (0x0080)
#define RX65N_CMT_CMCR_CMIE_ENABLE (0x0040)
#define RX65N_CMT_MSTPCRA_STOP (0x00008000) /*Release unit0(CMT0 and CMT1) from module stop state*/
#define RX65N_CMT_UNIT1_MSTPCRA_STOP (0x00004000) /*Release unit1(CMT2 and CMT3) from module stop state*/
#define RX65N_CMTW_UNIT1_MSTPCRA_STOP (0x00000001) /*Release CMTW unit1 from module stop state*/
#define RX65N_CMTW_UNIT0_MSTPCRA_STOP (0x00000002) /*Release CMTW unit0 from module stop state*/
#define RX65N_CMTCMSTR0_STR0 (0x0001) /* Bit 0: TCNT0 is counting */
#define RX65N_CMTCMSTR0_STR1 (0x0002) /* Bit 1: TCNT1 is counting */
#define RX65N_CMTCMSTR1_STR2 (0x0001) /* Bit 0: TCNT0 is counting */
#define RX65N_CMTCMSTR1_STR3 (0x0002) /* Bit 1: TCNT1 is counting */
#define RX65N_PRCR_ADDR (0x000803fe)
#define RX65N_PRCR_VALUE (0xa50b)
#define RX65N_GRPBE0_ADDR (0x00087600)
#define RX65N_GRPBL0_ADDR (0x00087630)
#define RX65N_GRPBL1_ADDR (0x00087634)
#define RX65N_GRPBL2_ADDR (0x00087638)
#define RX65N_GRPAL0_ADDR (0x00087830)
#define RX65N_GRPAL1_ADDR (0x00087834)
#define RX65N_GENBE0_ADDR (0x00087640)
#define RX65N_GENBL0_ADDR (0x00087670)
#define RX65N_GENBL1_ADDR (0x00087674)
#define RX65N_GENBL2_ADDR (0x00087678)
#define RX65N_GENAL0_ADDR (0x00087870)
#define RX65N_GENAL1_ADDR (0x00087874)
#define RX65N_GRPBL0_TEI0_MASK (1U << 0) /* (0x00000001) */
#define RX65N_GRPBL0_ERI0_MASK (1U << 1) /* (0x00000002) */
#define RX65N_GRPBL0_TEI1_MASK (1U << 2) /* (0x00000004) */
#define RX65N_GRPBL0_ERI1_MASK (1U << 3) /* (0x00000008) */
#define RX65N_GRPBL0_TEI2_MASK (1U << 4) /* (0x00000010) */
#define RX65N_GRPBL0_ERI2_MASK (1U << 5) /* (0x00000020) */
#define RX65N_GRPBL0_TEI3_MASK (1U << 6) /* (0x00000040) */
#define RX65N_GRPBL0_ERI3_MASK (1U << 7) /* (0x00000080) */
#define RX65N_GRPBL0_TEI4_MASK (1U << 8) /* (0x00000100) */
#define RX65N_GRPBL0_ERI4_MASK (1U << 9) /* (0x00000200) */
#define RX65N_GRPBL0_TEI5_MASK (1U << 10) /* (0x00000400) */
#define RX65N_GRPBL0_ERI5_MASK (1U << 11) /* (0x00000800) */
#define RX65N_GRPBL0_TEI6_MASK (1U << 12) /* (0x00001000) */
#define RX65N_GRPBL0_ERI6_MASK (1U << 13) /* (0x00002000) */
#define RX65N_GRPBL0_TEI7_MASK (1U << 14) /* (0x00004000) */
#define RX65N_GRPBL0_ERI7_MASK (1U << 15) /* (0x00008000) */
#define RX65N_GRPBL1_TEI8_MASK (1U << 24)
#define RX65N_GRPBL1_ERI8_MASK (1U << 25)
#define RX65N_GRPBL1_TEI9_MASK (1U << 26)
#define RX65N_GRPBL1_ERI9_MASK (1U << 27)
#define RX65N_GRPAL0_TEI10_MASK (1U << 8)
#define RX65N_GRPAL0_ERI10_MASK (1U << 9)
#define RX65N_GRPAL0_TEI11_MASK (1U << 12)
#define RX65N_GRPAL0_ERI11_MASK (1U << 13)
#define RX65N_GRPBL0_TEI12_MASK (1U << 16)
#define RX65N_GRPBL0_ERI12_MASK (1U << 17)
/* Start Ethernet and EDMAC Interface */
/* ETHERC and EDMAC base Addresses */
#define RX65N_EDMAC0_BASE (0x000c0000) /* EDMAC base address */
#define RX65N_ETHERC0_BASE (0x000c0100) /* Ethernet MAC base address */
/* Ethernet Addresses */
/* Register Offsets */
/* MAC Registers */
#define RX65N_ETH_ECMR_OFFSET (0x0000) /* ETHERC Mode register */
#define RX65N_ETH_RFLR_OFFSET (0x0008) /* Receive Frame Maximum Length Register */
#define RX65N_ETH_ECSR_OFFSET (0x0010) /* ETHERC Status Register */
#define RX65N_ETH_ECSIPR_OFFSET (0x0018) /* ETHERC Interrupt Enable Register */
#define RX65N_ETH_PIR_OFFSET (0x0020) /* PHY Interface Register */
#define RX65N_ETH_PSR_OFFSET (0x0028) /* PHY Status Register */
#define RX65N_ETH_RDMLR_OFFSET (0x0040) /* Random Number Generation Counter Limit Setting Register */
#define RX65N_ETH_IPGR_OFFSET (0x0050) /* Interpacket Gap Register */
#define RX65N_ETH_APR_OFFSET (0x0054) /* Automatic PAUSE Frame Register */
#define RX65N_ETH_MPR_OFFSET (0x0058) /* Manual PAUSE Frame Register */
#define RX65N_ETH_RFCF_OFFSET (0x0060) /* Received PAUSE Frame Counter */
#define RX65N_ETH_TPAUSER_OFFSET (0x0064) /* PAUSE Frame Retransmit Count Setting Register */
#define RX65N_ETH_TPAUSECR_OFFSET (0x0068) /* PAUSE Frame Retransmit Counter */
#define RX65N_ETH_BCFRR_OFFSET (0x006c) /* Broadcast Frame Receive Count Setting Register */
#define RX65N_ETH_MAHR_OFFSET (0x00c0) /* MAC Address Upper Bit Register */
#define RX65N_ETH_MALR_OFFSET (0x00c8) /* MAC Address Lower Bit Register */
#define RX65N_ETH_TROCR_OFFSET (0x00d0) /* Transmit Retry Over Counter Register */
#define RX65N_ETH_CDCR_OFFSET (0x00d4) /* Late Collision Detect Counter Register */
#define RX65N_ETH_LCCR_OFFSET (0x00d8) /* Lost Carrier Counter Register */
#define RX65N_ETH_CNDCR_OFFSET (0x00dc) /* Carrier Not Detect Counter Register */
#define RX65N_ETH_CEFCR_OFFSET (0x00e4) /* CRC Error Frame Receive Counter Register */
#define RX65N_ETH_FRECR_OFFSET (0x00e8) /* Frame Receive Error Counter Register */
#define RX65N_ETH_TSFRCR_OFFSET (0x00ec) /* Too-Short Frame Receive Counter Register */
#define RX65N_ETH_TLFRCR_OFFSET (0x00f0) /* Too-Long Frame Receive Counter Register */
#define RX65N_ETH_RFCR_OFFSET (0x00f4) /* Received Alignment Error Frame Counter Register */
#define RX65N_ETH_MAFCR_OFFSET (0x00f8) /* Multicast Address Frame Receive Counter Register */
/* DMA Registers */
#define RX65N_ETHD_EDMR_OFFSET (0x0000) /* EDMAC Mode Register */
#define RX65N_ETHD_EDTRR_OFFSET (0x0008) /* EDMAC Transmit Request Register */
#define RX65N_ETHD_EDRRR_OFFSET (0x0010) /* EDMAC Receive Request Register */
#define RX65N_ETHD_TDLAR_OFFSET (0x0018) /* Transmit Descriptor List Start Address Register */
#define RX65N_ETHD_RDLAR_OFFSET (0x0020) /* Receive Descriptor List Start Address Register */
#define RX65N_ETHD_EESR_OFFSET (0x0028) /* ETHERC/EDMAC Status Register */
#define RX65N_ETHD_EESIPR_OFFSET (0x0030) /* ETHERC/EDMAC Status Interrupt Enable Register */
#define RX65N_ETHD_TRSCER_OFFSET (0x0038) /* ETHERC/EDMAC Transmit/Receive Status Copy Enable Register */
#define RX65N_ETHD_RMFCR_OFFSET (0x0040) /* Missed-Frame Counter Register */
#define RX65N_ETHD_TFTR_OFFSET (0x0048) /* Transmit FIFO Threshold Register */
#define RX65N_ETHD_FDR_OFFSET (0x0050) /* FIFO Depth Register */
#define RX65N_ETHD_RMCR_OFFSET (0x0058) /* Receive Method Control Register */
#define RX65N_ETHD_TFUCR_OFFSET (0x0064) /* Transmit FIFO Underflow Counter */
#define RX65N_ETHD_RFOCR_OFFSET (0x0068) /* Receive FIFO Overflow Counter */
#define RX65N_ETHD_IOSR_OFFSET (0x006c) /* Independent Output Signal Setting Register */
#define RX65N_ETHD_FCFTR_OFFSET (0x0070) /* Flow Control Start FIFO Threshold Setting Register */
#define RX65N_ETHD_RPADIR_OFFSET (0x0078) /* Receive Data Padding Insert Register */
#define RX65N_ETHD_TRIMD_OFFSET (0x007c) /* Transmit Interrupt Setting Register */
#define RX65N_ETHD_RBWAR_OFFSET (0x00c8) /* Receive Buffer Write Address Register */
#define RX65N_ETHD_RDFAR_OFFSET (0x00cc) /* Receive Descriptor Fetch Address Register */
#define RX65N_ETHD_TBRAR_OFFSET (0x00d4) /* Transmit Buffer Read Address Register */
#define RX65N_ETHD_TDFAR_OFFSET (0x00d8) /* Transmit Descriptor Fetch Address Register */
/* Register Base Addresses */
/* MAC Registers */
#define RX65N_ETH_ECMR (RX65N_ETHERC0_BASE+RX65N_ETH_ECMR_OFFSET)
#define RX65N_ETH_RFLR (RX65N_ETHERC0_BASE+RX65N_ETH_RFLR_OFFSET)
#define RX65N_ETH_ECSR (RX65N_ETHERC0_BASE+RX65N_ETH_ECSR_OFFSET)
#define RX65N_ETH_ECSIPR (RX65N_ETHERC0_BASE+RX65N_ETH_ECSIPR_OFFSET)
#define RX65N_ETH_PIR (RX65N_ETHERC0_BASE+RX65N_ETH_PIR_OFFSET)
#define RX65N_ETH_PSR (RX65N_ETHERC0_BASE+RX65N_ETH_PSR_OFFSET)
#define RX65N_ETH_RDMLR (RX65N_ETHERC0_BASE+RX65N_ETH_RDMLR_OFFSET)
#define RX65N_ETH_IPGR (RX65N_ETHERC0_BASE+RX65N_ETH_IPGR_OFFSET)
#define RX65N_ETH_APR (RX65N_ETHERC0_BASE+RX65N_ETH_APR_OFFSET)
#define RX65N_ETH_MPR (RX65N_ETHERC0_BASE+RX65N_ETH_MPR_OFFSET)
#define RX65N_ETH_RFCF (RX65N_ETHERC0_BASE+RX65N_ETH_RFCF_OFFSET)
#define RX65N_ETH_TPAUSER (RX65N_ETHERC0_BASE+RX65N_ETH_TPAUSER_OFFSET)
#define RX65N_ETH_TPAUSECR (RX65N_ETHERC0_BASE+RX65N_ETH_TPAUSECR_OFFSET)
#define RX65N_ETH_BCFRR (RX65N_ETHERC0_BASE+RX65N_ETH_BCFRR_OFFSET)
#define RX65N_ETH_MAHR (RX65N_ETHERC0_BASE+RX65N_ETH_MAHR_OFFSET)
#define RX65N_ETH_MALR (RX65N_ETHERC0_BASE+RX65N_ETH_MALR_OFFSET)
#define RX65N_ETH_TROCR (RX65N_ETHERC0_BASE+RX65N_ETH_TROCR_OFFSET)
#define RX65N_ETH_CDCR (RX65N_ETHERC0_BASE+RX65N_ETH_CDCR_OFFSET)
#define RX65N_ETH_LCCR (RX65N_ETHERC0_BASE+RX65N_ETH_LCCR_OFFSET)
#define RX65N_ETH_CNDCR (RX65N_ETHERC0_BASE+RX65N_ETH_CNDCR_OFFSET)
#define RX65N_ETH_CEFCR (RX65N_ETHERC0_BASE+RX65N_ETH_CEFCR_OFFSET)
#define RX65N_ETH_FRECR (RX65N_ETHERC0_BASE+RX65N_ETH_FRECR_OFFSET)
#define RX65N_ETH_TSFRCR (RX65N_ETHERC0_BASE+RX65N_ETH_TSFRCR_OFFSET)
#define RX65N_ETH_TLFRCR (RX65N_ETHERC0_BASE+RX65N_ETH_TLFRCR_OFFSET)
#define RX65N_ETH_RFCR (RX65N_ETHERC0_BASE+RX65N_ETH_RFCR_OFFSET)
#define RX65N_ETH_MAFCR (RX65N_ETHERC0_BASE+RX65N_ETH_MAFCR_OFFSET)
/* DMA Registers */
#define RX65N_ETHD_EDMR (RX65N_EDMAC0_BASE+RX65N_ETHD_EDMR_OFFSET)
#define RX65N_ETHD_EDTRR (RX65N_EDMAC0_BASE+RX65N_ETHD_EDTRR_OFFSET)
#define RX65N_ETHD_EDRRR (RX65N_EDMAC0_BASE+RX65N_ETHD_EDRRR_OFFSET)
#define RX65N_ETHD_TDLAR (RX65N_EDMAC0_BASE+RX65N_ETHD_TDLAR_OFFSET)
#define RX65N_ETHD_RDLAR (RX65N_EDMAC0_BASE+RX65N_ETHD_RDLAR_OFFSET)
#define RX65N_ETHD_EESR (RX65N_EDMAC0_BASE+RX65N_ETHD_EESR_OFFSET)
#define RX65N_ETHD_EESIPR (RX65N_EDMAC0_BASE+RX65N_ETHD_EESIPR_OFFSET)
#define RX65N_ETHD_TRSCER (RX65N_EDMAC0_BASE+RX65N_ETHD_TRSCER_OFFSET)
#define RX65N_ETHD_RMFCR (RX65N_EDMAC0_BASE+RX65N_ETHD_RMFCR_OFFSET)
#define RX65N_ETHD_TFTR (RX65N_EDMAC0_BASE+RX65N_ETHD_TFTR_OFFSET)
#define RX65N_ETHD_FDR (RX65N_EDMAC0_BASE+RX65N_ETHD_FDR_OFFSET)
#define RX65N_ETHD_RMCR (RX65N_EDMAC0_BASE+RX65N_ETHD_RMCR_OFFSET)
#define RX65N_ETHD_TFUCR (RX65N_EDMAC0_BASE+RX65N_ETHD_TFUCR_OFFSET)
#define RX65N_ETHD_RFOCR (RX65N_EDMAC0_BASE+RX65N_ETHD_RFOCR_OFFSET)
#define RX65N_ETHD_IOSR (RX65N_EDMAC0_BASE+RX65N_ETHD_IOSR_OFFSET)
#define RX65N_ETHD_FCFTR (RX65N_EDMAC0_BASE+RX65N_ETHD_FCFTR_OFFSET)
#define RX65N_ETHD_RPADIR (RX65N_EDMAC0_BASE+RX65N_ETHD_RPADIR_OFFSET)
#define RX65N_ETHD_TRIMD (RX65N_EDMAC0_BASE+RX65N_ETHD_TRIMD_OFFSET)
#define RX65N_ETHD_RBWAR (RX65N_EDMAC0_BASE+RX65N_ETHD_RBWAR_OFFSET)
#define RX65N_ETHD_RDFAR (RX65N_EDMAC0_BASE+RX65N_ETHD_RDFAR_OFFSET)
#define RX65N_ETHD_TBRAR (RX65N_EDMAC0_BASE+RX65N_ETHD_TBRAR_OFFSET)
#define RX65N_ETHD_TDFAR (RX65N_EDMAC0_BASE+RX65N_ETHD_TDFAR_OFFSET)
/* MPC (Multifunction pin controller) Registers for Ethernet */
#define RX65N_MPC_PFENET (0x0008c10e)
#define RX65N_MPC_PWPR (0x0008c11f)
/* (Module control Registers) for Ethernet */
#define RX65N_MSTP_CRB (0x00080014)
/* Register Bit-Field Definitions */
/* MAC Registers */
#define ETH_ECSR_LCHNG (1 << 2) /* Bit 2: Link Signal Change Flag */
/* Bit 2: LINK Signal Change Interrupt enable/disable */
#define ETH_ECSIPR_LCHNGIP (1 << 2)
#define ETH_ECMR_CLR (0x00000000)
/* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */
#define ETH_ECSR_CLR (0x00000037)
#define ETH_ECMR_RE (1 << 6) /* Transmit function is enabled */
#define ETH_ECMR_TE (1 << 5) /* Receive function is enabled */
#define ETH_ECMR_DM (1 << 1) /* Duplex Mode */
#define ETH_ECMR_RTM (1 << 2) /* Bit Rate */
/* Bit 4:0:Interpacket Gap 96 bit time (initial value) */
#define ETH_IPGR_IPG_INITIAL (0x00000014)
/* Receive Frame Maximum Length */
#define ETH_RFLR_RFL (1518)
/* EDMA Registers */
/* Bit 22: ETHERC status interrupt request is enable/disabled. */
#define ETHD_EDMR_SWR (1 << 0)
/* Bit 6: Big Endian Mode/Little Endian Mode */
#define ETHD_EDMR_DE (1 << 6)
/* Clear all EDMAC status bits */
#define ETHD_EESR_EDMAC (0x47ff0f9f)
/* Frame transfer Complete status Flag check */
#define ETHD_EESR_TC (1 << 21)
/* ETHERC/EDMAC Status Register Source Flag */
#define ETHD_EESR_ECI (1 << 22)
#define ETHD_EESR_FR (1 << 18) /* Frame Receive Flag */
/* Frame Receive Interrupt Request Enable */
#define ETHD_EESIPR_FRIP (1 << 18)
/* Frame Transfer Complete Interrupt Request Enable */
#define ETHD_EESIPR_TCIP (1 << 21)
/* ETHERC/EDMAC Status Register Source Interrupt Request Enable */
#define ETHD_EESIPR_ECIIP (1 << 22)
/* ETHERC/EDMAC Write-Back Complete Interrupt Request Enable */
#define ETHD_EESIPR_TWBIP (1 << 30)
/* Bit 0:10: Transmit FIFO Threshold */
#define ETHD_TFTR_TFT (0x00000000)
/* Bit: 20: Transmit Descriptor Empty Flag */
#define ETHD_EESR_TDE (1<20)
/* Ether PSR register */
#define ETH_PSR_LMON (1)
/* End Ethernet and EDMAC Interface */
/* General Values LED: */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
# define LED_ON (0)
# define LED_OFF (1)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
# define LED_ON (1)
# define LED_OFF (0)
#else
# error "No Selection for PORT definition in rx65n_port.c"
#endif
/* Bit Set Values */
#define SET_BIT_HIGH (1)
#define SET_BIT_LOW (0)
#define SET_BYTE_HIGH (0xff)
#define SET_BYTE_LOW (0x00)
/****************************************************************************
* Public Types
***************************************************************************/
/****************************************************************************
* Public Data
***************************************************************************/
#ifndef __ASSEMBLER__
/* Serial Communications interface (SCI) */
enum E_RX_SCI
{
RX_SCI_SMR_OFFSET = 0,
RX_SCI_BRR_OFFSET,
RX_SCI_SCR_OFFSET,
RX_SCI_TDR_OFFSET,
RX_SCI_SSR_OFFSET,
RX_SCI_RDR_OFFSET,
RX_SCI_SCMR_OFFSET,
RX_SCI_SEMR_OFFSET,
RX_SCI_SNFR_OFFSET,
RX_SCI_SIMR1_OFFSET,
RX_SCI_SIMR2_OFFSET,
RX_SCI_SIMR3_OFFSET,
RX_SCI_SISR_OFFSET,
RX_SCI_SPMR_OFFSET,
RX_SCI_THRHL_OFFSET,
RX_SCI_RDRHL_OFFSET,
RX_SCI_MDDR_OFFSET
};
#endif /* __ASSEMBLER__ */
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_DEFINITIONS_H */

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_dumpstate.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "up_arch.h"
#include "up_internal.h"
#include "sched/sched.h"
#include "chip.h"
#include "rx65n/irq.h"
#ifdef CONFIG_ARCH_STACKDUMP
/****************************************************************************
* Private Data
****************************************************************************/
static uint32_t s_last_regs[XCPTCONTEXT_REGS];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rx65n_getsp
****************************************************************************/
static inline uint16_t rx65n_getsp(void)
{
uint16_t sp;
__asm__ __volatile__("\tmvfc usp, %0\n\t": "=r" (sp):: "memory"); /* check */
return sp;
}
/****************************************************************************
* Name: rx65n_getusersp
****************************************************************************/
#if CONFIG_ARCH_INTERRUPTSTACK > 3
static inline uint16_t rx65n_getusersp(void)
{
uint8_t *ptr = (uint8_t *) g_current_regs;
return (uint16_t)ptr[REG_SP] << 8 | ptr[REG_SP + 1]; /* check */
}
#endif
/****************************************************************************
* Name: rx65n_stackdump
****************************************************************************/
static void rx65n_stackdump(uint16_t sp, uint16_t stack_base)
{
uint16_t stack;
for (stack = sp & ~7; stack < stack_base; stack += 8) /* check */
{
uint8_t *ptr = (uint8_t *)&stack;
_alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
}
/****************************************************************************
* Name: rx65n_registerdump
****************************************************************************/
static inline void rx65n_registerdump(void)
{
uint8_t *ptr = (uint8_t *) g_current_regs;
uint32_t regs[XCPTCONTEXT_SIZE];
/* Are user registers available from interrupt processing? */
if (ptr == NULL)
{
/* No.. capture user registers by hand */
up_saveusercontext((uint32_t *)s_last_regs);
*regs = *s_last_regs;
}
/* Dump the interrupt registers */
_alert("PC: %08x PSW=%08x\n",
ptr[REG_PC], ptr[REG_PSW]);
_alert("FPSW: %08x ACC0LO: %08x ACC0HI: %08x ACC0GU: %08x"
"ACC1LO: %08x ACC1HI: %08x ACC1GU: %0.8x\n",
ptr[REG_FPSW], ptr[REG_ACC0LO], ptr[REG_ACC0HI],
ptr[REG_ACC0GU], ptr[REG_ACC1LO],
ptr[REG_ACC1HI], ptr[REG_ACC1GU]);
_alert("R%d:%08x %08x %08x %08x %08x %08x %08x\n", 0,
ptr[REG_R1], ptr[REG_R2], ptr[REG_R3],
ptr[REG_R4], ptr[REG_R5], ptr[REG_R6], ptr[REG_R7]);
_alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 8,
ptr[REG_R8], ptr[REG_R9], ptr[REG_R10], ptr[REG_R11],
ptr[REG_R12], ptr[REG_R13], ptr[REG_R14], ptr[REG_R15]);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_dumpstate
****************************************************************************/
void up_dumpstate(void)
{
struct tcb_s *rtcb = running_task();
uint32_t sp = rx65n_getsp();
uint32_t ustackbase;
uint32_t ustacksize;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
uint32_t istackbase;
uint32_t istacksize;
#endif
/* Dump the registers (if available) */
rx65n_registerdump();
/* Get the limits on the user stack memory */
if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
{
ustackbase = g_idle_topstack - 1;
ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
}
else
{
ustackbase = (uint32_t)rtcb->adj_stack_ptr;
ustacksize = (uint16_t)rtcb->adj_stack_size;
}
#if CONFIG_ARCH_INTERRUPTSTACK > 3
istackbase = ebss; /* check how to declare ebss, as of now declared in chip.h */
istacksize = CONFIG_ARCH_INTERRUPTSTACK;
/* Show interrupt stack info */
_alert("sp: %04x\n", sp);
_alert("IRQ stack:\n");
_alert(" base: %04x\n", istackbase);
_alert(" size: %04x\n", istacksize);
/* Does the current stack pointer lie within the interrupt
* stack?
*/
if (sp <= istackbase && sp > istackbase - istacksize)
{
/* Yes.. dump the interrupt stack */
rx65n_stackdump(sp, istackbase);
/* Extract the user stack pointer from the register area */
sp = rx65n_getusersp();
_alert("sp: %04x\n", sp);
}
else if (g_current_regs)
{
_alert("ERROR: Stack pointer is not within the interrupt stack\n");
rx65n_stackdump(istackbase - istacksize, istackbase);
}
/* Show user stack info */
_alert("User stack:\n");
_alert(" base: %04x\n", ustackbase);
_alert(" size: %04x\n", ustacksize);
#else
_alert("sp: %04x\n", sp);
_alert("stack base: %04x\n", ustackbase);
_alert("stack size: %04x\n", ustacksize);
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
* stack memory.
*/
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
_alert("ERROR: Stack pointer is not within allocated stack\n");
rx65n_stackdump(ustackbase - ustacksize, ustackbase);
}
else
{
rx65n_stackdump(sp, ustackbase);
}
}
#endif /* CONFIG_ARCH_STACKDUMP */

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_eth.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H
#define __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H
/****************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Understood PHY types */
/* Definitions for use with rx65n_phy_boardinitialize */
#define RX65N_NETHERNET 1
#define EMAC0_INTF 0
/****************************************************************************
* Public Functions
***************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
***************************************************************************/
/****************************************************************************
* Function: rx65n_ethinitialize
*
* Description:
* Initialize the EMAC driver.
*
* Input Parameters:
* intf - If multiple EMAC peripherals are supported, this identifies the
* the EMAC peripheral being initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
* Called very early in the initialization sequence.
*
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
int rx65n_ethinitialize(int intf);
/****************************************************************************
* Function: rx65n_poll_expiry
*
* Description:
* Poll Expiry timer
*
* Input Parameters:
* argc - Input argument
* arg - Input argument
*
* Returned Value:
* None
*
****************************************************************************/
void rx65n_poll_expiry(int argc, uint32_t arg, ...);
/****************************************************************************
* Function: rx65n_txtimeout_expiry
*
* Description:
* txtimeout timer
*
* Input Parameters:
* argc - Input argument
* arg - Input argument
*
* Returned Value:
* None
*
****************************************************************************/
void rx65n_txtimeout_expiry(int argc, uint32_t arg, ...);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H */

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_hardware_setup.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Surya <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_cgc.h"
#include "rx65n_icu.h"
#include "rx65n_port.h"
#include "rx65n_sci.h"
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "rx65n_definitions.h"
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
void r_ether_port_configuration(void);
void r_ether_pheriperal_enable(void);
/****************************************************************************
* Name: r_system_init
*
* Description:
* Initialization of hardware
****************************************************************************/
void r_system_init(void)
{
/* Enable writing to registers related to operating modes,LPC, CGC
* and software reset
*/
SYSTEM.PRCR.WORD = 0xa50b;
/* Enable writing to MPC pin function control registers */
MPC.PWPR.BIT.B0WI = 0;
MPC.PWPR.BIT.PFSWE = 1;
/* Set peripheral settings */
r_cgc_create();
r_icu_create();
r_port_create();
#ifdef CONFIG_RX65N_EMAC0
r_ether_port_configuration();
r_ether_pheriperal_enable();
#endif
/* Disable writing to MPC pin function control registers */
MPC.PWPR.BIT.PFSWE = 0;
MPC.PWPR.BIT.B0WI = 1;
/* Enable protection */
SYSTEM.PRCR.WORD = 0xa500;
r_config_icu_software_start();
r_config_icu_software2_start();
}
/****************************************************************************
* Name: hardware_setup
*
* Description:
* Initialization of hardware
****************************************************************************/
int hardware_setup(void)
{
r_system_init();
return (1U);
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_head.S
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/***************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h> /* NuttX configuration settings */
#include <arch/board/board.h> /* Board-specific settings */
#include <arch/irq.h> /* IRQ definitons */
#include "chip.h" /* Chip-specific settings */
#include "up_internal.h"
#include "up_arch.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/*****************************************************************************
* External references
*****************************************************************************/
/* Called functions */
.globl _up_lowsetup /* Early initialization of UART */
#ifdef USE_EARLYSERIALINIT
.globl _up_earlyconsoleinit /* Early initialization of console driver */
#endif
#ifdef CONFIG_ARCH_LEDS
.globl _board_autoled_initialize /* Boot LED setup */
#endif
#ifdef CONFIG_DEBUG_FEATURES
.globl _up_lowputc /* Low-level debug output */
#endif
.globl _nx_start /* NuttX entry point */
/* Variables set up by the linker script */
.globl _hardware_setup /* external Sub-routine to initialise Hardware */
.globl _up_lowsetup
.globl _data
.globl _mdata
.globl _ebss
.globl _bss
.globl _edata
.globl _ustack
.globl _istack
.globl _g_exp_vector_table
.type _g_exp_vector_table, object
/*****************************************************************************
* Macros
*****************************************************************************/
/*****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status. This macro will
* modify r0, r1, r2 and r14
*
*****************************************************************************/
.macro showprogress, code
#ifdef CONFIG_DEBUG_FEATURES
mov.l #_up_lowputc, r13 /* Address of up_earlyconsoleinit */
mov #\code, r1
jsr r13 /* Call it */
#endif
.endm
/****************************************************************************
* Code
***************************************************************************/
.section .text
/****************************************************************************
* Name: __start
*
* Description:
* After reset, program execution starts here.
*
***************************************************************************/
.text
.align 16
.globl __start
.type __start, #function
__start:
mvtc #_ustack, USP /* initialise user stack pointer */
mvtc #_istack, ISP /* initialise interrupt stack pointer */
#ifdef __RXv2__
mvtc #_except_vectors, extb /* setup exception vector (extb) */
#endif
mvtc #__int_vector_table, intb /* setup interrupt vector (intb) */
mvtc #100h, fpsw /* setup FPSW */
/* load data section from ROM to RAM */
mov #_mdata, r2 /* src ROM address of data section in R2 */
mov #_data, r1 /* dest start RAM address of data section in R1 */
mov #_edata, r3 /* end RAM address of data section in R3 */
sub r1, r3 /* size of data section in R3 (R3=R3-R1) */
smovf /* block copy R3 bytes from R2 to R1 */
/* bss initialisation : zero out bss */
mov #00h, r2 /* load R2 reg with zero */
mov #_ebss, r3 /* store the end address of bss in R3 */
mov #_bss, r1 /* store the start address of bss in R1 */
sub r1, r3 /* size of bss section in R3 (R3=R3-R1) */
sstr.b
/* call the hardware initialiser */
bsr.a _hardware_setup
nop
mvtc #30000h, psw /* Set Ubit & Ibit for PSW */
mov.l #_up_lowsetup, r15
jsr r15 /* Call up_lowsetup */
nop
#ifdef USE_EARLYSERIALINIT
mov.l #_up_earlyconsoleinit, r14
jsr r14 /* Call up_earlyconsoleinit */
nop
#endif
bsr.a _nx_start
nop
_exit:
nop
_loop_here:
bra _loop_here
nop
/****************************************************************************
* Data
***************************************************************************/
.section .data
.data
.align 4
.global _g_idle_topstack
.type _g_idle_topstack, @object
_g_idle_topstack:
.long _ebss + CONFIG_ARCH_INTERRUPTSTACK + CONFIG_IDLETHREAD_STACKSIZE
.size _g_idle_topstack, . - _g_idle_topstack
.end
/****************************************************************************
* EOF
***************************************************************************/

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_icu.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_icu.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: r_icu_create
*
* Description:
* ICU Initialization
****************************************************************************/
void r_icu_create(void)
{
/* Disable IRQ interrupts */
ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE |
_00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE |
_00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE |
_00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE ;
ICU.IER[0x09].BYTE = _00_ICU_IRQ8_DISABLE | _00_ICU_IRQ9_DISABLE |
_00_ICU_IRQ10_DISABLE | _00_ICU_IRQ11_DISABLE |
_00_ICU_IRQ12_DISABLE | _00_ICU_IRQ13_DISABLE |
_00_ICU_IRQ14_DISABLE | _00_ICU_IRQ15_DISABLE ;
/* Disable group interrupts */
IEN(ICU, GROUPBL0) = 0u;
/* Set IRQ settings */
ICU.IRQCR[8].BYTE = _04_ICU_IRQ_EDGE_FALLING;
ICU.IRQCR[9].BYTE = _04_ICU_IRQ_EDGE_FALLING;
/* Set IRQ8 priority level */
IPR(ICU, IRQ8) = _0F_ICU_PRIORITY_LEVEL15;
/* Set IRQ9 priority level */
IPR(ICU, IRQ9) = _0F_ICU_PRIORITY_LEVEL15;
/* Set Group BL0 priority level */
IPR(ICU, GROUPBL0) = _0F_ICU_PRIORITY_LEVEL15;
/* Enable group BL0 interrupt */
IEN(ICU, GROUPBL0) = 1U;
/* Disable software interrupt */
IEN(ICU, SWINT) = 0U;
IEN(ICU, SWINT2) = 0U;
/* Set SWINT priority level */
IPR(ICU, SWINT) = _0F_ICU_PRIORITY_LEVEL15;
/* Set SWINT2 priority level */
IPR(ICU, SWINT2) = _0F_ICU_PRIORITY_LEVEL15;
/* Set IRQ8 pin */
MPC.P00PFS.BYTE = 0x40u;
PORT0.PDR.BYTE &= 0xfeu;
PORT0.PMR.BYTE &= 0xfeu;
/* Set IRQ9 pin */
MPC.P01PFS.BYTE = 0x40u;
PORT0.PDR.BYTE &= 0xfdu;
PORT0.PMR.BYTE &= 0xfdu;
}
/****************************************************************************
* Name: r_icu_irq8_start
*
* Description:
* Enable IRQ8 Interrupt
****************************************************************************/
void r_icu_irq8_start(void)
{
/* Enable IRQ8 interrupt */
IEN(ICU, IRQ8) = 1u;
}
/****************************************************************************
* Name: r_icu_irq8_stop
*
* Description:
*Initialize IRQ9 Interrupt
****************************************************************************/
void r_icu_irq8_stop(void)
{
/* Disable IRQ8 interrupt */
IEN(ICU, IRQ8) = 0u;
}
/****************************************************************************
* Name: r_icu_irq9_start
*
* Description:
* Enable IRQ9 Interrupt
****************************************************************************/
void r_icu_irq9_start(void)
{
/* Enable IRQ9 interrupt */
IEN(ICU, IRQ9) = 1u;
}
/****************************************************************************
* Name: r_icu_irq9_stop
*
* Description:
* Disable IRQ9 Interrupt
****************************************************************************/
void r_icu_irq9_stop(void)
{
/* Disable IRQ9 interrupt */
IEN(ICU, IRQ9) = 0u;
}
/****************************************************************************
* Name: r_config_icu_software_start
*
* Description:
* Enable S/W Interrupt
****************************************************************************/
void r_config_icu_software_start(void)
{
/* Enable software interrupt */
IEN(ICU, SWINT) = 1u;
}
/****************************************************************************
* Name: r_config_icu_softwareinterrupt_generate
*
* Description:
* Generate S/W Interrupt
****************************************************************************/
void r_config_icu_softwareinterrupt_generate(void)
{
/* Generate software interrupt */
ICU.SWINTR.BIT.SWINT = 1u;
}
/****************************************************************************
* Name: r_config_icu_software_stop
*
* Description:
* Disable S/W Interrupt
****************************************************************************/
void r_config_icu_software_stop(void)
{
/* Disable software interrupt */
IEN(ICU, SWINT) = 0u;
}
/****************************************************************************
* Name: r_config_icu_software2_start
*
* Description:
* Enable S/W Interrupt 2
****************************************************************************/
void r_config_icu_software2_start(void)
{
/* Enable software interrupt 2 */
IEN(ICU, SWINT2) = 1u;
}
/****************************************************************************
* Name: r_config_icu_softwareinterrupt2_generate
*
* Description:
* Generate software interrupt 2
****************************************************************************/
void r_config_icu_softwareinterrupt2_generate(void)
{
/* Generate software interrupt 2 */
ICU.SWINT2R.BIT.SWINT2 = 1u;
}
/****************************************************************************
* Name: r_config_icu_softwareinterrupt2_stop
*
* Description:
* Disable software interrupt 2
****************************************************************************/
void r_config_icu_software2_stop(void)
{
/* Disable software interrupt 2 */
IEN(ICU, SWINT2) = 0u;
}
/****************************************************************************
* Name: r_icu_irqisfallingedge
*
* Description:
* Detect if falling edge interrupt is triggered
****************************************************************************/
uint8_t r_icu_irqisfallingedge (const uint8_t irq_no)
{
uint8_t falling_edge_trig = 0x0;
if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING)
{
falling_edge_trig = 1;
}
return (falling_edge_trig);
}
/****************************************************************************
* Name: r_icu_irqsetfallingedge
*
* Description:
* Sets or unsets falling edge triggered
****************************************************************************/
void r_icu_irqsetfallingedge (const uint8_t irq_no, const uint8_t set_f_edge)
{
if (1 == set_f_edge)
{
ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING;
}
else
{
ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING;
}
}
/****************************************************************************
* Name: r_icu_irqsetrisingedge
*
* Description:
* Sets or unsets rising edge triggered
****************************************************************************/
void r_icu_irqsetrisingedge (const uint8_t irq_no, const uint8_t set_r_edge)
{
if (1 == set_r_edge)
{
ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING;
}
else
{
ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING;
}
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_icu.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. Gregory Nutt.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_ICU_H
#define __ARCH_RENESAS_SRC_RX65N_RX65N_ICU_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt Request Enable Register 08 (IER08) */
/* Interrupt Request Enable/Disable(IENn) */
#define _00_ICU_IRQ0_DISABLE (0x00u)
#define _01_ICU_IRQ0_ENABLE (0x01u)
#define _00_ICU_IRQ1_DISABLE (0x00u)
#define _02_ICU_IRQ1_ENABLE (0x02u)
#define _00_ICU_IRQ2_DISABLE (0x00u)
#define _04_ICU_IRQ2_ENABLE (0x04u)
#define _00_ICU_IRQ3_DISABLE (0x00u)
#define _08_ICU_IRQ3_ENABLE (0x08u)
#define _00_ICU_IRQ4_DISABLE (0x00u)
#define _10_ICU_IRQ4_ENABLE (0x10u)
#define _00_ICU_IRQ5_DISABLE (0x00u)
#define _20_ICU_IRQ5_ENABLE (0x20u)
#define _00_ICU_IRQ6_DISABLE (0x00u)
#define _40_ICU_IRQ6_ENABLE (0x40u)
#define _00_ICU_IRQ7_DISABLE (0x00u)
#define _80_ICU_IRQ7_ENABLE (0x80u)
/* Interrupt Request Enable Register 09 (IER09) */
/* Interrupt Request Enable/Disable(IENn) */
#define _00_ICU_IRQ8_DISABLE (0x00u)
#define _01_ICU_IRQ8_ENABLE (0x01u)
#define _00_ICU_IRQ9_DISABLE (0x00u)
#define _02_ICU_IRQ9_ENABLE (0x02u)
#define _00_ICU_IRQ10_DISABLE (0x00u)
#define _04_ICU_IRQ10_ENABLE (0x04u)
#define _00_ICU_IRQ11_DISABLE (0x00u)
#define _08_ICU_IRQ11_ENABLE (0x08u)
#define _00_ICU_IRQ12_DISABLE (0x00u)
#define _10_ICU_IRQ12_ENABLE (0x10u)
#define _00_ICU_IRQ13_DISABLE (0x00u)
#define _20_ICU_IRQ13_ENABLE (0x20u)
#define _00_ICU_IRQ14_DISABLE (0x00u)
#define _40_ICU_IRQ14_ENABLE (0x40u)
#define _00_ICU_IRQ15_DISABLE (0x00u)
#define _80_ICU_IRQ15_ENABLE (0x80u)
/* Interrupt Source Priority Register n (IPRn) */
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_ICU_PRIORITY_LEVEL0 (0x00u)
#define _01_ICU_PRIORITY_LEVEL1 (0x01u)
#define _02_ICU_PRIORITY_LEVEL2 (0x02u)
#define _03_ICU_PRIORITY_LEVEL3 (0x03u)
#define _04_ICU_PRIORITY_LEVEL4 (0x04u)
#define _05_ICU_PRIORITY_LEVEL5 (0x05u)
#define _06_ICU_PRIORITY_LEVEL6 (0x06u)
#define _07_ICU_PRIORITY_LEVEL7 (0x07u)
#define _08_ICU_PRIORITY_LEVEL8 (0x08u)
#define _09_ICU_PRIORITY_LEVEL9 (0x09u)
#define _0A_ICU_PRIORITY_LEVEL10 (0x0au)
#define _0B_ICU_PRIORITY_LEVEL11 (0x0bu)
#define _0C_ICU_PRIORITY_LEVEL12 (0x0cu)
#define _0D_ICU_PRIORITY_LEVEL13 (0x0du)
#define _0E_ICU_PRIORITY_LEVEL14 (0x0eu)
#define _0F_ICU_PRIORITY_LEVEL15 (0x0fu)
/* Fast Interrupt Set Register (FIR) */
/* Fast Interrupt Enable (FIEN) */
#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000u)
#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000u)
/* IRQ Control Register i (IRQCRi) (i = 0 to 15) */
/* IRQ Detection Sense Select (IRQMD[1:0]) */
#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00u)
#define _04_ICU_IRQ_EDGE_FALLING (0x04u)
#define _08_ICU_IRQ_EDGE_RISING (0x08u)
#define _0C_ICU_IRQ_EDGE_BOTH (0x0cu)
/* IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) */
/* Digital Filter Enable (FLTEN0n) */
#define _00_ICU_IRQn_FILTER_DISABLE (0x00u)
#define _01_ICU_IRQ0_FILTER_ENABLE (0x01u)
#define _02_ICU_IRQ1_FILTER_ENABLE (0x02u)
#define _04_ICU_IRQ2_FILTER_ENABLE (0x04u)
#define _08_ICU_IRQ3_FILTER_ENABLE (0x08u)
#define _10_ICU_IRQ4_FILTER_ENABLE (0x10u)
#define _20_ICU_IRQ5_FILTER_ENABLE (0x20u)
#define _40_ICU_IRQ6_FILTER_ENABLE (0x40u)
#define _80_ICU_IRQ7_FILTER_ENABLE (0x80u)
/* IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1) */
/* Digital Filter Enable (FLTEN8~15) */
#define _01_ICU_IRQ8_FILTER_ENABLE (0x01u)
#define _02_ICU_IRQ9_FILTER_ENABLE (0x02u)
#define _04_ICU_IRQ10_FILTER_ENABLE (0x04u)
#define _08_ICU_IRQ11_FILTER_ENABLE (0x08u)
#define _10_ICU_IRQ12_FILTER_ENABLE (0x10u)
#define _20_ICU_IRQ13_FILTER_ENABLE (0x20u)
#define _40_ICU_IRQ14_FILTER_ENABLE (0x40u)
#define _80_ICU_IRQ15_FILTER_ENABLE (0x80u)
/* IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) */
/* IRQn Digital Filter Sampling Clock (FCLKSELn) */
#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000u)
#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001u)
#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002u)
#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003u)
#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000u)
#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004u)
#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008u)
#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000cu)
#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000u)
#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010u)
#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020u)
#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030u)
#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000u)
#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040u)
#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080u)
#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00c0u)
#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000u)
#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100u)
#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200u)
#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300u)
#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000u)
#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400u)
#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800u)
#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0c00u)
#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000u)
#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000u)
#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000u)
#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000u)
#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000u)
#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000u)
#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000u)
#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xc000u)
/* IRQ Pin Digital Filter Setting Register 0 (IRQFLTC1) */
/* IRQn Digital Filter Sampling Clock (FCLKSEL8~15) */
#define _0000_ICU_IRQ8_FILTER_PCLK (0x0000u)
#define _0001_ICU_IRQ8_FILTER_PCLK_8 (0x0001u)
#define _0002_ICU_IRQ8_FILTER_PCLK_32 (0x0002u)
#define _0003_ICU_IRQ8_FILTER_PCLK_64 (0x0003u)
#define _0000_ICU_IRQ9_FILTER_PCLK (0x0000u)
#define _0004_ICU_IRQ9_FILTER_PCLK_8 (0x0004u)
#define _0008_ICU_IRQ9_FILTER_PCLK_32 (0x0008u)
#define _000C_ICU_IRQ9_FILTER_PCLK_64 (0x000cu)
#define _0000_ICU_IRQ10_FILTER_PCLK (0x0000u)
#define _0010_ICU_IRQ10_FILTER_PCLK_8 (0x0010u)
#define _0020_ICU_IRQ10_FILTER_PCLK_32 (0x0020u)
#define _0030_ICU_IRQ10_FILTER_PCLK_64 (0x0030u)
#define _0000_ICU_IRQ11_FILTER_PCLK (0x0000u)
#define _0040_ICU_IRQ11_FILTER_PCLK_8 (0x0040u)
#define _0080_ICU_IRQ11_FILTER_PCLK_32 (0x0080u)
#define _00C0_ICU_IRQ11_FILTER_PCLK_64 (0x00c0u)
#define _0000_ICU_IRQ12_FILTER_PCLK (0x0000u)
#define _0100_ICU_IRQ12_FILTER_PCLK_8 (0x0100u)
#define _0200_ICU_IRQ12_FILTER_PCLK_32 (0x0200u)
#define _0300_ICU_IRQ12_FILTER_PCLK_64 (0x0300u)
#define _0000_ICU_IRQ13_FILTER_PCLK (0x0000u)
#define _0400_ICU_IRQ13_FILTER_PCLK_8 (0x0400u)
#define _0800_ICU_IRQ13_FILTER_PCLK_32 (0x0800u)
#define _0C00_ICU_IRQ13_FILTER_PCLK_64 (0x0c00u)
#define _0000_ICU_IRQ14_FILTER_PCLK (0x0000u)
#define _1000_ICU_IRQ14_FILTER_PCLK_8 (0x1000u)
#define _2000_ICU_IRQ14_FILTER_PCLK_32 (0x2000u)
#define _3000_ICU_IRQ14_FILTER_PCLK_64 (0x3000u)
#define _0000_ICU_IRQ15_FILTER_PCLK (0x0000u)
#define _4000_ICU_IRQ15_FILTER_PCLK_8 (0x4000u)
#define _8000_ICU_IRQ15_FILTER_PCLK_32 (0x8000u)
#define _C000_ICU_IRQ15_FILTER_PCLK_64 (0xc000u)
/* NMI Pin Interrupt Control Register (NMICR) */
/* NMI Detection Set (NMIMD) */
#define _00_ICU_NMI_EDGE_FALLING (0x00u)
#define _08_ICU_NMI_EDGE_RISING (0x08u)
/* NMI Pin Digital Filter Setting Register (NMIFLTC) */
/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */
#define _00_ICU_NMI_FILTER_PCLK (0x00u)
#define _01_ICU_NMI_FILTER_PCLK_8 (0x01u)
#define _02_ICU_NMI_FILTER_PCLK_32 (0x02u)
#define _03_ICU_NMI_FILTER_PCLK_64 (0x03u)
/* EXDMAC Activation Peripheral Interrupt Select Register (SELEXDR) */
/* EXDMAC0 Activation Peripheral Interrupt Select (SELEXD0) */
#define _00_ICU_EXDMAC0_SLIBR144 (0x00u)
#define _01_ICU_EXDMAC0_SLIAR208 (0x01u)
/* EXDMAC1 Activation Peripheral Interrupt Select (SELEXD1) */
#define _00_ICU_EXDMAC1_SLIBR145 (0x00u)
#define _02_ICU_EXDMAC1_SLIAR209 (0x02u)
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
/****************************************************************************
* Name: r_icu_create
*
* Description:
* Initializes ICU
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_create(void);
/****************************************************************************
* Name: r_icu_irq8_start
*
* Description:
* Enables IRQ8
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_irq8_start(void);
/****************************************************************************
* Name: r_icu_irq8_stop
*
* Description:
* Disables IRQ8
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_irq8_stop(void);
/****************************************************************************
* Name: r_icu_irq9_start
*
* Description:
* Enables IRQ9
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_irq9_start(void);
/****************************************************************************
* Name: r_icu_irq9_stop
*
* Description:
* Disables IRQ9
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_irq9_stop(void);
/****************************************************************************
* Name: r_config_icu_software_start
*
* Description:
* Enable Software Interrupt
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_config_icu_software_start(void);
/****************************************************************************
* Name: r_config_icu_softwareinterrupt_generate
*
* Description:
* Generate software interrupt
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_config_icu_softwareinterrupt_generate(void);
/****************************************************************************
* Name: r_config_icu_software_stop
*
* Description:
* Disable S/W Interrupt
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_config_icu_software_stop(void);
/****************************************************************************
* Name: r_config_icu_software2_start
*
* Description:
* Enable S/W Interrupt2
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_config_icu_software2_start(void);
/****************************************************************************
* Name: r_config_icu_softwareinterrupt2_generate
*
* Description:
* Generate software interrupt 2
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_config_icu_softwareinterrupt2_generate(void);
/****************************************************************************
* Name: r_config_icu_software2_stop
*
* Description:
* Disable software interrupt 2
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_config_icu_software2_stop(void);
/****************************************************************************
* Name: r_icu_irqisfallingedge
*
* Description:
* Detect if falling edge interrupt is triggered
*
* Input Parameters:
* irqno - irq number
*
* Returned Value:
* 1 is returned on success
*
****************************************************************************/
uint8_t r_icu_irqisfallingedge(const uint8_t irq_no);
/****************************************************************************
* Name: r_icu_irqsetfallingedge
*
* Description:
* Sets or unsets falling edge triggered
*
* Input Parameters:
* irqno - irq number
* set_f_edge - value that has to be set for falling edge
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_irqsetfallingedge(const uint8_t irq_no, const uint8_t set_f_edge);
/****************************************************************************
* Name: r_icu_irqsetfallingedge
*
* Description:
* Sets or unsets falling edge triggered
*
* Input Parameters:
* irqno - irq number
* set_r_edge - value that has to be set for rising edge
*
* Returned Value:
* None
*
****************************************************************************/
void r_icu_irqsetrisingedge(const uint8_t irq_no, const uint8_t set_r_edge);
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ICU_H *.

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_initialstate.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <nuttx/arch.h>
#include "chip/chip.h"
#include "up_internal.h"
#include "up_arch.h"
#include "rx65n/irq.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define up_getsr() __getsr()
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_initial_state
*
* Description:
* A new thread is being started and a new TCB
* has been created. This function is called to initialize
* the processor specific portions of the new TCB.
*
* This function must setup the intial architecture registers
* and/or stack so that execution will begin at tcb->start
* on the next context switch.
*
****************************************************************************/
void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
xcp->regs[REG_PC] = (uint32_t)tcb->start;
/* Enable or disable interrupts, based on user configuration */
#ifdef CONFIG_SUPPRESS_INTERRUPTS
xcp->regs[REG_PSW] = up_getsr() & ~0x00010000;
#else
xcp->regs[REG_PSW] = up_getsr() | 0x00010000;
#endif
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_irq.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Surya <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "rx65n/iodefine.h"
#include "up_internal.h"
/****************************************************************************
* Public Data
****************************************************************************/
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
/* Actually a pointer to the beginning of a uint8_t array */
volatile uint32_t *g_current_regs;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Currents_regs is non-NULL only while processing an interrupt */
g_current_regs = NULL;
/* Enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* On many architectures, there are three levels of interrupt enabling: (1)
* at the global level, (2) at the level of the interrupt controller,
* and (3) at the device level. In order to receive interrupts, they
* must be enabled at all three levels.
*
* This function implements disabling of the device specified by 'irq'
* at the interrupt controller level if supported by the architecture
* (up_irq_save() supports the global level, the device level is hardware
* specific).
*
****************************************************************************/
void up_disable_irq(int irq)
{
if (irq == RX65N_CMI0_IRQ)
{
ICU.IER[3].BIT.IEN4 = 0;
}
#ifdef CONFIG_RX65N_SCI0
if (irq == RX65N_RXI0_IRQ)
{
ICU.IER[7].BIT.IEN2 = 0;
}
if (irq == RX65N_TXI0_IRQ)
{
ICU.IER[7].BIT.IEN3 = 0;
}
if (irq == RX65N_ERI0_IRQ)
{
ICU.GRPBL0.BIT.IS1 = 0;
ICU.GENBL0.BIT.EN1 = 0;
}
if (irq == RX65N_TEI0_IRQ)
{
ICU.GRPBL0.BIT.IS0 = 0;
ICU.GENBL0.BIT.EN0 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI1
if (irq == RX65N_RXI1_IRQ)
{
ICU.IER[7].BIT.IEN4 = 0;
}
if (irq == RX65N_TXI1_IRQ)
{
ICU.IER[7].BIT.IEN5 = 0;
}
if (irq == RX65N_ERI1_IRQ)
{
ICU.GRPBL0.BIT.IS3 = 0;
ICU.GENBL0.BIT.EN3 = 0;
}
if (irq == RX65N_TEI1_IRQ)
{
ICU.GRPBL0.BIT.IS2 = 0;
ICU.GENBL0.BIT.EN2 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI2
if (irq == RX65N_RXI2_IRQ)
{
ICU.IER[7].BIT.IEN6 = 0;
}
if (irq == RX65N_TXI2_IRQ)
{
ICU.IER[7].BIT.IEN7 = 0;
}
if (irq == RX65N_ERI2_IRQ)
{
ICU.GRPBL0.BIT.IS5 = 0;
ICU.GENBL0.BIT.EN5 = 0;
}
if (irq == RX65N_TEI2_IRQ)
{
ICU.GRPBL0.BIT.IS4 = 0;
ICU.GENBL0.BIT.EN4 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI3
if (irq == RX65N_RXI3_IRQ)
{
ICU.IER[10].BIT.IEN0 = 0;
}
if (irq == RX65N_TXI3_IRQ)
{
ICU.IER[10].BIT.IEN1 = 0;
}
if (irq == RX65N_ERI3_IRQ)
{
ICU.GRPBL0.BIT.IS7 = 0;
ICU.GENBL0.BIT.EN7 = 0;
}
if (irq == RX65N_TEI3_IRQ)
{
ICU.GRPBL0.BIT.IS6 = 0;
ICU.GENBL0.BIT.EN6 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI4
if (irq == RX65N_RXI4_IRQ)
{
ICU.IER[10].BIT.IEN2 = 0;
}
if (irq == RX65N_TXI4_IRQ)
{
ICU.IER[10].BIT.IEN3 = 0;
}
if (irq == RX65N_ERI4_IRQ)
{
ICU.GRPBL0.BIT.IS9 = 0;
ICU.GENBL0.BIT.EN9 = 0;
}
if (irq == RX65N_TEI4_IRQ)
{
ICU.GRPBL0.BIT.IS8 = 0;
ICU.GENBL0.BIT.EN8 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI5
if (irq == RX65N_RXI5_IRQ)
{
ICU.IER[10].BIT.IEN4 = 0;
}
if (irq == RX65N_TXI5_IRQ)
{
ICU.IER[10].BIT.IEN5 = 0;
}
if (irq == RX65N_ERI5_IRQ)
{
ICU.GRPBL0.BIT.IS11 = 0;
ICU.GENBL0.BIT.EN11 = 0;
}
if (irq == RX65N_TEI5_IRQ)
{
ICU.GRPBL0.BIT.IS10 = 0;
ICU.GENBL0.BIT.EN10 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI6
if (irq == RX65N_RXI6_IRQ)
{
ICU.IER[10].BIT.IEN6 = 0;
}
if (irq == RX65N_TXI6_IRQ)
{
ICU.IER[10].BIT.IEN7 = 0;
}
if (irq == RX65N_ERI6_IRQ)
{
ICU.GRPBL0.BIT.IS13 = 0;
ICU.GENBL0.BIT.EN13 = 0;
}
if (irq == RX65N_TEI6_IRQ)
{
ICU.GRPBL0.BIT.IS12 = 0;
ICU.GENBL0.BIT.EN12 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI7
if (irq == RX65N_RXI7_IRQ)
{
ICU.IER[12].BIT.IEN2 = 0;
}
if (irq == RX65N_TXI7_IRQ)
{
ICU.IER[12].BIT.IEN3 = 0;
}
if (irq == RX65N_ERI7_IRQ)
{
ICU.GRPBL0.BIT.IS15 = 0;
ICU.GENBL0.BIT.EN15 = 0;
}
if (irq == RX65N_TEI7_IRQ)
{
ICU.GRPBL0.BIT.IS14 = 0;
ICU.GENBL0.BIT.EN14 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI8
if (irq == RX65N_RXI8_IRQ)
{
ICU.IER[12].BIT.IEN4 = 0;
}
if (irq == RX65N_TXI8_IRQ)
{
ICU.IER[12].BIT.IEN5 = 0;
}
if (irq == RX65N_ERI8_IRQ)
{
ICU.GRPBL1.BIT.IS25 = 0;
ICU.GENBL1.BIT.EN25 = 0;
}
if (irq == RX65N_TEI8_IRQ)
{
ICU.GRPBL1.BIT.IS24 = 0;
ICU.GENBL1.BIT.EN24 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI9
if (irq == RX65N_RXI9_IRQ)
{
ICU.IER[12].BIT.IEN6 = 0;
}
if (irq == RX65N_TXI9_IRQ)
{
ICU.IER[12].BIT.IEN7 = 0;
}
if (irq == RX65N_ERI9_IRQ)
{
ICU.GRPBL1.BIT.IS27 = 0;
ICU.GENBL1.BIT.EN27 = 0;
}
if (irq == RX65N_TEI9_IRQ)
{
ICU.GRPBL1.BIT.IS26 = 0;
ICU.GENBL1.BIT.EN26 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI10
if (irq == RX65N_RXI10_IRQ)
{
ICU.IER[10].BIT.IEN0 = 0;
}
if (irq == RX65N_TXI10_IRQ)
{
ICU.IER[10].BIT.IEN1 = 0;
}
if (irq == RX65N_ERI10_IRQ)
{
ICU.GRPAL0.BIT.IS9 = 0;
ICU.GENAL0.BIT.EN9 = 0;
}
if (irq == RX65N_TEI10_IRQ)
{
ICU.GRPAL0.BIT.IS8 = 0;
ICU.GENAL0.BIT.EN8 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI11
if (irq == RX65N_RXI11_IRQ)
{
ICU.IER[14].BIT.IEN2 = 0;
}
if (irq == RX65N_TXI11_IRQ)
{
ICU.IER[14].BIT.IEN3 = 0;
}
if (irq == RX65N_ERI11_IRQ)
{
ICU.GRPAL0.BIT.IS13 = 0;
ICU.GENAL0.BIT.EN13 = 0;
}
if (irq == RX65N_TEI11_IRQ)
{
ICU.GRPAL0.BIT.IS12 = 0;
ICU.GENAL0.BIT.EN12 = 0;
}
#endif
#ifdef CONFIG_RX65N_SCI12
if (irq == RX65N_RXI12_IRQ)
{
ICU.IER[14].BIT.IEN4 = 0;
}
if (irq == RX65N_TXI12_IRQ)
{
ICU.IER[14].BIT.IEN5 = 0;
}
if (irq == RX65N_ERI12_IRQ)
{
ICU.GRPBL0.BIT.IS17 = 0;
ICU.GENBL0.BIT.EN17 = 0;
}
if (irq == RX65N_TEI12_IRQ)
{
ICU.GRPBL0.BIT.IS16 = 0;
ICU.GENBL0.BIT.EN16 = 0;
}
#endif
#ifdef CONFIG_RX65N_EMAC
if (irq == RX65N_ETH_IRQ)
{
ICU.GRPAL1.BIT.IS4 = 0;
ICU.GENAL1.BIT.EN4 = 0;
}
#endif
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* This function implements enabling of the device specified by 'irq'
* at the interrupt controller level if supported by the architecture
* (up_irq_save() supports the global level, the device level is hardware
* specific).
*
****************************************************************************/
void up_enable_irq(int irq)
{
if (irq == RX65N_CMI0_IRQ)
{
ICU.IER[3].BIT.IEN4 = 1;
}
#ifdef CONFIG_RX65N_SCI0
if (irq == RX65N_RXI0_IRQ)
{
ICU.IER[7].BIT.IEN2 = 1;
}
if (irq == RX65N_TXI0_IRQ)
{
ICU.IER[7].BIT.IEN3 = 1;
}
if (irq == RX65N_ERI0_IRQ)
{
ICU.GRPBL0.BIT.IS1 = 1;
ICU.GENBL0.BIT.EN1 = 1;
}
if (irq == RX65N_TEI0_IRQ)
{
ICU.GRPBL0.BIT.IS0 = 1;
ICU.GENBL0.BIT.EN0 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI1
if (irq == RX65N_RXI1_IRQ)
{
ICU.IER[7].BIT.IEN4 = 1;
}
if (irq == RX65N_TXI1_IRQ)
{
ICU.IER[7].BIT.IEN5 = 1;
}
if (irq == RX65N_ERI1_IRQ)
{
ICU.GRPBL0.BIT.IS3 = 1;
ICU.GENBL0.BIT.EN3 = 1;
}
if (irq == RX65N_TEI1_IRQ)
{
ICU.GRPBL0.BIT.IS2 = 1;
ICU.GENBL0.BIT.EN2 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI2
if (irq == RX65N_RXI2_IRQ)
{
ICU.IER[7].BIT.IEN6 = 1;
}
if (irq == RX65N_TXI2_IRQ)
{
ICU.IER[7].BIT.IEN7 = 1;
}
if (irq == RX65N_ERI2_IRQ)
{
ICU.GRPBL0.BIT.IS5 = 1;
ICU.GENBL0.BIT.EN5 = 1;
}
if (irq == RX65N_TEI2_IRQ)
{
ICU.GRPBL0.BIT.IS4 = 1;
ICU.GENBL0.BIT.EN4 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI3
if (irq == RX65N_RXI3_IRQ)
{
ICU.IER[10].BIT.IEN0 = 1;
}
if (irq == RX65N_TXI3_IRQ)
{
ICU.IER[10].BIT.IEN1 = 1;
}
if (irq == RX65N_ERI3_IRQ)
{
ICU.GRPBL0.BIT.IS7 = 1;
ICU.GENBL0.BIT.EN7 = 1;
}
if (irq == RX65N_TEI3_IRQ)
{
ICU.GRPBL0.BIT.IS6 = 1;
ICU.GENBL0.BIT.EN6 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI4
if (irq == RX65N_RXI4_IRQ)
{
ICU.IER[10].BIT.IEN2 = 1;
}
if (irq == RX65N_TXI4_IRQ)
{
ICU.IER[10].BIT.IEN3 = 1;
}
if (irq == RX65N_ERI4_IRQ)
{
ICU.GRPBL0.BIT.IS9 = 1;
ICU.GENBL0.BIT.EN9 = 1;
}
if (irq == RX65N_TEI4_IRQ)
{
ICU.GRPBL0.BIT.IS8 = 1;
ICU.GENBL0.BIT.EN8 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI5
if (irq == RX65N_RXI5_IRQ)
{
ICU.IER[10].BIT.IEN4 = 1;
}
if (irq == RX65N_TXI5_IRQ)
{
ICU.IER[10].BIT.IEN5 = 1;
}
if (irq == RX65N_ERI5_IRQ)
{
ICU.GRPBL0.BIT.IS11 = 1;
ICU.GENBL0.BIT.EN11 = 1;
}
if (irq == RX65N_TEI5_IRQ)
{
ICU.GRPBL0.BIT.IS10 = 1;
ICU.GENBL0.BIT.EN10 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI6
if (irq == RX65N_RXI6_IRQ)
{
ICU.IER[10].BIT.IEN6 = 1;
}
if (irq == RX65N_TXI6_IRQ)
{
ICU.IER[10].BIT.IEN7 = 1;
}
if (irq == RX65N_ERI6_IRQ)
{
ICU.GRPBL0.BIT.IS13 = 1;
ICU.GENBL0.BIT.EN13 = 1;
}
if (irq == RX65N_TEI6_IRQ)
{
ICU.GRPBL0.BIT.IS12 = 1;
ICU.GENBL0.BIT.EN12 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI7
if (irq == RX65N_RXI7_IRQ)
{
ICU.IER[12].BIT.IEN2 = 1;
}
if (irq == RX65N_TXI7_IRQ)
{
ICU.IER[12].BIT.IEN3 = 1;
}
if (irq == RX65N_ERI7_IRQ)
{
ICU.GRPBL0.BIT.IS15 = 1;
ICU.GENBL0.BIT.EN15 = 1;
}
if (irq == RX65N_TEI7_IRQ)
{
ICU.GRPBL0.BIT.IS14 = 1;
ICU.GENBL0.BIT.EN14 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI8
if (irq == RX65N_RXI8_IRQ)
{
ICU.IER[12].BIT.IEN4 = 1;
}
if (irq == RX65N_TXI8_IRQ)
{
ICU.IER[12].BIT.IEN5 = 1;
}
if (irq == RX65N_ERI8_IRQ)
{
ICU.GRPBL1.BIT.IS25 = 1;
ICU.GENBL1.BIT.EN25 = 1;
}
if (irq == RX65N_TEI8_IRQ)
{
ICU.GRPBL1.BIT.IS24 = 1;
ICU.GENBL1.BIT.EN24 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI9
if (irq == RX65N_RXI9_IRQ)
{
ICU.IER[12].BIT.IEN6 = 1;
}
if (irq == RX65N_TXI9_IRQ)
{
ICU.IER[12].BIT.IEN7 = 1;
}
if (irq == RX65N_ERI9_IRQ)
{
ICU.GRPBL1.BIT.IS27 = 1;
ICU.GENBL1.BIT.EN27 = 1;
}
if (irq == RX65N_TEI9_IRQ)
{
ICU.GRPBL1.BIT.IS26 = 1;
ICU.GENBL1.BIT.EN26 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI10
if (irq == RX65N_RXI10_IRQ)
{
ICU.IER[10].BIT.IEN0 = 1;
}
if (irq == RX65N_TXI10_IRQ)
{
ICU.IER[10].BIT.IEN1 = 1;
}
if (irq == RX65N_ERI10_IRQ)
{
ICU.GRPAL0.BIT.IS9 = 1;
ICU.GENAL0.BIT.EN9 = 1;
}
if (irq == RX65N_TEI10_IRQ)
{
ICU.GRPAL0.BIT.IS8 = 1;
ICU.GENAL0.BIT.EN8 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI11
if (irq == RX65N_RXI11_IRQ)
{
ICU.IER[14].BIT.IEN2 = 1;
}
if (irq == RX65N_TXI11_IRQ)
{
ICU.IER[14].BIT.IEN3 = 1;
}
if (irq == RX65N_ERI11_IRQ)
{
ICU.GRPAL0.BIT.IS13 = 1;
ICU.GENAL0.BIT.EN13 = 1;
}
if (irq == RX65N_TEI11_IRQ)
{
ICU.GRPAL0.BIT.IS12 = 1;
ICU.GENAL0.BIT.EN12 = 1;
}
#endif
#ifdef CONFIG_RX65N_SCI12
if (irq == RX65N_RXI12_IRQ)
{
ICU.IER[14].BIT.IEN4 = 1;
}
if (irq == RX65N_TXI12_IRQ)
{
ICU.IER[14].BIT.IEN5 = 1;
}
if (irq == RX65N_ERI12_IRQ)
{
ICU.GRPBL0.BIT.IS17 = 1;
ICU.GENBL0.BIT.EN17 = 1;
}
if (irq == RX65N_TEI12_IRQ)
{
ICU.GRPBL0.BIT.IS16 = 1;
ICU.GENBL0.BIT.EN16 = 1;
}
#endif
#ifdef CONFIG_RX65N_EMAC
if (irq == RX65N_ETH_IRQ)
{
ICU.GRPAL1.BIT.IS4 = 1;
ICU.GENAL1.BIT.EN4 = 1;
}
#endif
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_lowputc.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include "chip.h"
#include "up_internal.h"
#include "up_arch.h"
#include "rx65n_definitions.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration **********************************************************/
/* Is there a serial console? */
#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI0)
# define HAVE_CONSOLE 1
# undef CONFIG_SCI1_SERIAL_CONSOLE
#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI2)
# define HAVE_CONSOLE 1
# undef CONFIG_SCI0_SERIAL_CONSOLE
#else
# if defined(CONFIG_SCI0_SERIAL_CONSOLE) || defined(CONFIG_SCI2_SERIAL_CONSOLE)
# error "Serial console selected, but corresponding SCI not enabled"
# endif
# undef HAVE_CONSOLE
#endif
/* Select UART parameters for the selected console */
#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI0_BASE
# define RX_SCI_BAUD CONFIG_SCI0_BAUD
# define RX_SCI_BITS CONFIG_SCI0_BITS
# define RX_SCI_PARITY CONFIG_SCI0_PARITY
# define RX_SCI_2STOP CONFIG_SCI0_2STOP
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI1_BASE
# define RX_SCI_BAUD CONFIG_SCI1_BAUD
# define RX_SCI_BITS CONFIG_SCI1_BITS
# define RX_SCI_PARITY CONFIG_SCI1_PARITY
# define RX_SCI_2STOP CONFIG_SCI1_2STOP
#elif defined(CONFIG_SCI2_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI2_BASE
# define RX_SCI_BAUD CONFIG_SCI2_BAUD
# define RX_SCI_BITS CONFIG_SCI2_BITS
# define RX_SCI_PARITY CONFIG_SCI2_PARITY
# define RX_SCI_2STOP CONFIG_SCI2_2STOP
#elif defined(CONFIG_SCI3_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI3_BASE
# define RX_SCI_BAUD CONFIG_SCI3_BAUD
# define RX_SCI_BITS CONFIG_SCI3_BITS
# define RX_SCI_PARITY CONFIG_SCI3_PARITY
# define RX_SCI_2STOP CONFIG_SCI3_2STOP
#elif defined(CONFIG_SCI4_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI4_BASE
# define RX_SCI_BAUD CONFIG_SCI4_BAUD
# define RX_SCI_BITS CONFIG_SCI4_BITS
# define RX_SCI_PARITY CONFIG_SCI4_PARITY
# define RX_SCI_2STOP CONFIG_SCI4_2STOP
#elif defined(CONFIG_SCI5_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI5_BASE
# define RX_SCI_BAUD CONFIG_SCI5_BAUD
# define RX_SCI_BITS CONFIG_SCI5_BITS
# define RX_SCI_PARITY CONFIG_SCI5_PARITY
# define RX_SCI_2STOP CONFIG_SCI5_2STOP
#elif defined(CONFIG_SCI6_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI6_BASE
# define RX_SCI_BAUD CONFIG_SCI6_BAUD
# define RX_SCI_BITS CONFIG_SCI6_BITS
# define RX_SCI_PARITY CONFIG_SCI6_PARITY
# define RX_SCI_2STOP CONFIG_SCI6_2STOP
#elif defined(CONFIG_SCI7_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI7_BASE
# define RX_SCI_BAUD CONFIG_SCI7_BAUD
# define RX_SCI_BITS CONFIG_SCI7_BITS
# define RX_SCI_PARITY CONFIG_SCI7_PARITY
# define RX_SCI_2STOP CONFIG_SCI7_2STOP
#elif defined(CONFIG_SCI8_SERIAL_CONSOLE)
# define RX_SCI_BASE RX65N_SCI8_BASE
# define RX_SCI_BAUD CONFIG_SCI8_BAUD
# define RX_SCI_BITS CONFIG_SCI8_BITS
# define RX_SCI_PARITY CONFIG_SCI8_PARITY
# define RX_SCI_2STOP CONFIG_SCI8_2STOP
#else
# error "No CONFIG_SCIn_SERIAL_CONSOLE Setting"
#endif
/* Get mode setting */
#if RX_SCI_BITS == 7
# define RX_SMR_MODE RX_SCISMR_CHR
#elif RX_SCI_BITS == 8
# define RX_SMR_MODE (0)
#else
# define RX_SMR_MODE (0)
#endif
#if RX_SCI_PARITY == 0
# define RX_SMR_PARITY (0)
#elif RX_SCI_PARITY == 1
# define RX_SMR_PARITY (RX_SCISMR_PE|RX_SCISMR_OE)
#elif RX_SCI_PARITY == 2
# define RX_SMR_PARITY RX_SCISMR_PE
#else
# define RX_SMR_PARITY (0)
#endif
#if RX_SCI_2STOP != 0
# define RX_SMR_STOP RX_SCISMR_STOP
#else
# define RX_SMR_STOP (0)
#endif
/* The full SMR setting also includes internal clocking with no divisor,
* aysnchronous operation and multiprocessor disabled:
*/
#define RX_SMR_VALUE (RX_SMR_MODE|RX_SMR_PARITY|RX_SMR_STOP)
/* Clocking ***************************************************************/
#define RX_DIVISOR (8 * RX_SCI_BAUD)
#define RX_BRR ((RX_PCLKB / RX_DIVISOR) - 1)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_txready
*
* Description:
* Return TRUE of the Transmit Data Register is empty
*
****************************************************************************/
#ifdef HAVE_CONSOLE
static inline int up_txready(void)
{
/* Check the TDRE bit in the SSR. 1=TDR is empty */
return ((getreg8(RX_SCI_BASE + RX_SCI_SSR_OFFSET) & RX_SCISSR_TDRE) != 0);
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
uint8_t ssr;
/* Wait until the TDR is avaible */
while (!up_txready());
/* Write the data to the TDR */
putreg8(ch, RX_SCI_BASE + RX_SCI_TDR_OFFSET);
/* Clear the TDRE bit in the SSR */
ssr = getreg8(RX_SCI_BASE + RX_SCI_SSR_OFFSET);
ssr &= ~RX_SCISSR_TDRE;
putreg8(ssr, RX_SCI_BASE + RX_SCI_SSR_OFFSET);
#endif
}
/****************************************************************************
* Name: up_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output availabe as soon
* as possible.
*
****************************************************************************/
void up_lowsetup(void)
{
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG)
uint8_t scr;
/* Disable the transmitter and receiver */
scr = getreg8(RX_SCI_BASE + RX_SCI_SCR_OFFSET);
scr &= ~(RX_SCISCR_TE | RX_SCISCR_RE);
putreg8(scr, RX_SCI_BASE + RX_SCI_SCR_OFFSET);
/* Set communication to be asynchronous with the configured number of data
* bits, parity, and stop bits. Use the internal clock (undivided)
*/
putreg8(RX_SMR_VALUE, RX_SCI_BASE + RX_SCI_SMR_OFFSET);
/* Set the baud based on the configured console baud and configured
* system clock.
*/
putreg8(RX_BRR, RX_SCI_BASE + RX_SCI_BRR_OFFSET);
/* Select the internal clock source as input */
scr &= ~RX_SCISCR_CKEMASK;
putreg8(scr, RX_SCI_BASE + RX_SCI_SCR_OFFSET);
/* Then enable the transmitter and reciever */
scr |= (RX_SCISCR_TE | RX_SCISCR_RE);
putreg8(scr, RX_SCI_BASE + RX_SCI_SCR_OFFSET);
#endif
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_macrodriver.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_STATUS_H
#define __ARCH_RENESAS_SRC_RX65N_STATUS_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#include "rx65n/iodefine.h"
#ifndef TRUE
#define TRUE (1)
#else
#if (1 != TRUE)
#error "TRUE is not defined by 1."
#endif
#endif
#ifndef FALSE
#define FALSE (0)
#else
#if (0 != FALSE)
#error "FALSE is not defined by 0."
#endif
#endif
#ifndef __TYPEDEF__
/* Status list definition */
#define MD_STATUSBASE (0x00U)
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
/* Error list definition */
#define MD_ERRORBASE (0x80U)
#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
/* error argument input error */
#define MD_ARGERROR (MD_ERRORBASE + 0x01U)
#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
#define nop() asm("nop;")
#define brk() asm("brk;")
#define wait() asm("wait;")
#endif
#ifndef __TYPEDEF__
#ifndef _STDINT_H
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
#endif
typedef unsigned short MD_STATUS;
#define __TYPEDEF__
#endif
#endif /* __ARCH_RENESAS_SRC_RX65N_STATUS_H */

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arch/renesas/src/rx65n/rx65n_port.c Normal file
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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_port.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Surya <surya.prakash@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: r_port_create
*
* Description:
* Port Initialization
****************************************************************************/
void r_port_create(void)
{
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
/* LED_PORTINIT(0); */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
PORT7.PMR.BYTE = 0x00u;
PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
/* LED_PORTINIT(0); */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
PORT7.PMR.BYTE = 0x00u;
PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
LED_PORTINIT(0);
/* SCI0(UART) direction */
PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
/* SCI2(UART) direction */
PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
/* SCI5(UART) direction */
PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
/* SCI6(UART) direction */
PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
/* SCI8(RS485) direction */
PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
#else
# error "No Selection for PORT definition in rx65n_port.c"
#endif
}
#ifdef CONFIG_RX65N_EMAC0
void r_ether_port_configuration(void)
{
/* Port configuration */
/* Enable LEDs. */
/* Start with LEDs OFF */
PORT7.PODR.BIT.B3 = 1;
PORTG.PODR.BIT.B7 = 1;
PORTG.PODR.BIT.B6 = 1;
PORTG.PODR.BIT.B5 = 1;
/* SET LED pins as outputs */
PORT7.PDR.BIT.B3 = 1;
PORTG.PDR.BIT.B7 = 1;
PORTG.PDR.BIT.B6 = 1;
PORTG.PDR.BIT.B5 = 1;
/* Enable Switches */
/* Set pins as Inputs */
PORT0.PDR.BIT.B3 = 0;
PORT0.PDR.BIT.B5 = 0;
PORT0.PDR.BIT.B7 = 0;
/* Set port mode registers for switches. */
PORT0.PMR.BIT.B3 = 0;
PORT0.PMR.BIT.B5 = 0;
PORT0.PMR.BIT.B7 = 0;
}
void r_ether_pheriperal_enable(void)
{
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
/* TODO */
#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
/* Set ET0_TX_CLK pin */
MPC.PC4PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B4 = 1u;
/* Set ET0_RX_CLK pin */
MPC.P76PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B6 = 1u;
/* Set ET0_TX_EN pin */
MPC.P80PFS.BYTE = 0x11u;
PORT8.PMR.BIT.BT0 = 1u;
/* Set ET0_ETXD3 pin */
MPC.PC6PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B6 = 1u;
/* Set ET0_ETXD2 pin */
MPC.PC5PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B5 = 1u;
/* Set ET0_ETXD1 pin */
MPC.P82PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B2 = 1u;
/* Set ET0_ETXD0 pin */
MPC.P81PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B1 = 1u;
/* Set ET0_TX_ER pin */
MPC.PC3PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B3 = 1u;
/* Set ET0_RX_DV pin */
MPC.PC2PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B2 = 1u;
/* Set ET0_ERXD3 pin */
MPC.PC0PFS.BYTE = 0x11u;
PORTC.PMR.BIT.BT0 = 1u;
/* Set ET0_ERXD2 pin */
MPC.PC1PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B1 = 1u;
/* Set ET0_ERXD1 pin */
MPC.P74PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B4 = 1u;
/* Set ET0_ERXD0 pin */
MPC.P75PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B5 = 1u;
/* Set ET0_RX_ER pin */
MPC.P77PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B7 = 1u;
/* Set ET0_CRS pin */
MPC.P83PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B3 = 1u;
/* Set ET0_COL pin */
MPC.PC7PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B7 = 1u;
/* Set ET0_MDC pin */
MPC.P72PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B2 = 1u;
/* Set ET0_MDIO pin */
MPC.P71PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B1 = 1u;
/* Set ET0_LINKSTA pin */
MPC.P54PFS.BYTE = 0x11u;
PORT5.PMR.BIT.B4 = 1u;
/* Set ET0_LINKSTA pin */
MPC.P34PFS.BYTE = 0x11u;
PORT3.PMR.BIT.B4 = 1u;
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
/* Set ET0_MDC(PA4_ET_MDC) pin */
MPC.PA4PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B4 = 1u;
/* Set ET0_MDIO(PA3_ET_MDIO) pin */
MPC.PA3PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B3 = 1u;
/* Set REF50CK0 (PB2_ET_CLK) pin */
MPC.PB2PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B2 = 1u;
/* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
MPC.PB7PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B7 = 1u;
/* Set RMII0_RXD0(PB1_ET_RXD0) pin */
MPC.PB1PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B1 = 1u;
/* Set RMII0_RXD1(PB0_ET_RXD1) pin */
MPC.PB0PFS.BYTE = 0x12u;
PORTB.PMR.BIT.BT0 = 1u;
/* Set RMII0_RX_ER(PB3_ET_RXER) pin */
MPC.PB3PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B3 = 1u;
/* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
MPC.PB5PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B5 = 1u;
/* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
MPC.PB6PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B6 = 1u;
/* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
MPC.PB4PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B4 = 1u;
/* Set RXD2 pin */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin */
PORT5.PODR.BYTE |= 0x01u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BYTE |= 0x01u;
/* Set ET0_LINKSTA(PA5_ET_LINK) pin */
MPC.PA5PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B5 = 1u;
/* Set ETHER reset(PA6_ET_RST) pin */
MPC.PA6PFS.BYTE = 0x12u;
PORTA.PMR.BIT.B6 = 1u;
#endif
}
#endif

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_port.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_PORT_H
#define __ARCH_RENESAS_SRC_RX65N_PORT_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Port Direction Register (PDR) */
/* Pmn Direction Control (B7 - B0) */
#define _00_PM0_MODE_NOT_USED (0x00u) /* PM0 not used */
#define _00_PM0_MODE_INPUT (0x00u) /* PM0 as input */
#define _01_PM0_MODE_OUTPUT (0x01u) /* PM0 as output */
#define _00_PM1_MODE_NOT_USED (0x00u) /* PM1 not used */
#define _00_PM1_MODE_INPUT (0x00u) /* PM1 as input */
#define _02_PM1_MODE_OUTPUT (0x02u) /* PM1 as output */
#define _00_PM2_MODE_NOT_USED (0x00u) /* PM2 not used */
#define _00_PM2_MODE_INPUT (0x00u) /* PM2 as input */
#define _04_PM2_MODE_OUTPUT (0x04u) /* PM2 as output */
#define _00_PM3_MODE_NOT_USED (0x00u) /* PM3 not used */
#define _00_PM3_MODE_INPUT (0x00u) /* PM3 as input */
#define _08_PM3_MODE_OUTPUT (0x08u) /* PM3 as output */
#define _00_PM4_MODE_NOT_USED (0x00u) /* PM4 not used */
#define _00_PM4_MODE_INPUT (0x00u) /* PM4 as input */
#define _10_PM4_MODE_OUTPUT (0x10u) /* PM4 as output */
#define _00_PM5_MODE_NOT_USED (0x00u) /* PM5 not used */
#define _00_PM5_MODE_INPUT (0x00u) /* PM5 as input */
#define _20_PM5_MODE_OUTPUT (0x20u) /* PM5 as output */
#define _00_PM6_MODE_NOT_USED (0x00u) /* PM6 not used */
#define _00_PM6_MODE_INPUT (0x00u) /* PM6 as input */
#define _40_PM6_MODE_OUTPUT (0x40u) /* PM6 as output */
#define _00_PM7_MODE_NOT_USED (0x00u) /* PM7 not used */
#define _00_PM7_MODE_INPUT (0x00u) /* PM7 as input */
#define _80_PM7_MODE_OUTPUT (0x80u) /* PM7 as output */
#define _50_PDR0_DEFAULT (0x50u) /* PDR0 default value */
#define _03_PDR1_DEFAULT (0x03u) /* PDR1 default value */
#define _80_PDR5_DEFAULT (0x80u) /* PDR5 default value */
#define _30_PDR8_DEFAULT (0x30u) /* PDR8 default value */
#define _F0_PDR9_DEFAULT (0xf0u) /* PDR9 default value */
#define _DF_PDRF_DEFAULT (0xdfu) /* PDRF default value */
#define _D7_PDRJ_DEFAULT (0xd7u) /* PDRJ default value */
/* Port Output Data Register (PODR) */
/* Pmn Output Data Store (B7 - B0) */
#define _00_PM0_OUTPUT_0 (0x00u) /* output low at B0 */
#define _01_PM0_OUTPUT_1 (0x01u) /* output high at B0 */
#define _00_PM1_OUTPUT_0 (0x00u) /* output low at B1 */
#define _02_PM1_OUTPUT_1 (0x02u) /* output high at B1 */
#define _00_PM2_OUTPUT_0 (0x00u) /* output low at B2 */
#define _04_PM2_OUTPUT_1 (0x04u) /* output high at B2 */
#define _00_PM3_OUTPUT_0 (0x00u) /* output low at B3 */
#define _08_PM3_OUTPUT_1 (0x08u) /* output high at B3 */
#define _00_PM4_OUTPUT_0 (0x00u) /* output low at B4 */
#define _10_PM4_OUTPUT_1 (0x10u) /* output high at B4 */
#define _00_PM5_OUTPUT_0 (0x00u) /* output low at B5 */
#define _20_PM5_OUTPUT_1 (0x20u) /* output high at B5 */
#define _00_PM6_OUTPUT_0 (0x00u) /* output low at B6 */
#define _40_PM6_OUTPUT_1 (0x40u) /* output high at B6 */
#define _00_PM7_OUTPUT_0 (0x00u) /* output low at B7 */
#define _80_PM7_OUTPUT_1 (0x80u) /* output high at B7 */
/* Open Drain Control Register 0 (ODR0) */
/* Pmn Output Type Select (Pm0 to Pm3) */
#define _00_PM0_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _01_PM0_NCH_OPEN_DRAIN (0x01u) /* NMOS open-drain output */
#define _00_PM1_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _04_PM1_NCH_OPEN_DRAIN (0x04u) /* NMOS open-drain output */
#define _08_PM1_PCH_OPEN_DRAIN (0x08u) /* PMOS open-drain output,for PE1 only */
#define _00_PM2_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _10_PM2_NCH_OPEN_DRAIN (0x10u) /* NMOS open-drain output */
#define _00_PM3_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _40_PM3_NCH_OPEN_DRAIN (0x40u) /* NMOS open-drain output */
/* Open Drain Control Register 1 (ODR1) */
/* Pmn Output Type Select (Pm4 to Pm7) */
#define _00_PM4_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _01_PM4_NCH_OPEN_DRAIN (0x01u) /* NMOS open-drain output */
#define _00_PM5_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _04_PM5_NCH_OPEN_DRAIN (0x04u) /* NMOS open-drain output */
#define _00_PM6_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _10_PM6_NCH_OPEN_DRAIN (0x10u) /* NMOS open-drain output */
#define _00_PM7_CMOS_OUTPUT (0x00u) /* CMOS output */
#define _40_PM7_NCH_OPEN_DRAIN (0x40u) /* NMOS open-drain output */
/* Pull-Up Control Register (PCR) */
/* Pmn Input Pull-Up Resistor Control (B7 - B0) */
/* PM0 pull-up resistor not connected */
#define _00_PM0_PULLUP_OFF (0x00u)
/* PM0 pull-up resistor connected */
#define _01_PM0_PULLUP_ON (0x01u)
/* PM1 pull-up resistor not connected */
#define _00_PM1_PULLUP_OFF (0x00u)
/* PM1 pull-up resistor connected */
#define _02_PM1_PULLUP_ON (0x02u)
/* PM2 Pull-up resistor not connected */
#define _00_PM2_PULLUP_OFF (0x00u)
/* PM2 pull-up resistor connected */
#define _04_PM2_PULLUP_ON (0x04u)
/* PM3 pull-up resistor not connected */
#define _00_PM3_PULLUP_OFF (0x00u)
/* PM3 pull-up resistor connected */
#define _08_PM3_PULLUP_ON (0x08u)
/* PM4 pull-up resistor not connected */
#define _00_PM4_PULLUP_OFF (0x00u)
/* PM4 pull-up resistor connected */
#define _10_PM4_PULLUP_ON (0x10u)
/* PM5 pull-up resistor not connected */
#define _00_PM5_PULLUP_OFF (0x00u)
/* PM5 pull-up resistor connected */
#define _20_PM5_PULLUP_ON (0x20u)
/* PM6 pull-up resistor not connected */
#define _00_PM6_PULLUP_OFF (0x00u)
/* PM6 pull-up resistor connected */
#define _40_PM6_PULLUP_ON (0x40u)
/* PM7 pull-up resistor not connected */
#define _00_PM7_PULLUP_OFF (0x00u)
/* Pm7 pull-up resistor connected */
#define _80_PM7_PULLUP_ON (0x80u)
/* Drive Capacity Control Register (DSCR) */
/* Pmn Drive Capacity Control (B7 - B0) */
#define _00_PM0_HIDRV_OFF (0x00u) /* PM0 Normal drive output */
#define _01_PM0_HIDRV_ON (0x01u) /* PM0 High-drive output */
#define _00_PM1_HIDRV_OFF (0x00u) /* PM1 Normal drive output */
#define _02_PM1_HIDRV_ON (0x02u) /* PM1 High-drive output */
#define _00_PM2_HIDRV_OFF (0x00u) /* PM2 Normal drive output */
#define _04_PM2_HIDRV_ON (0x04u) /* PM2 High-drive output */
#define _00_PM3_HIDRV_OFF (0x00u) /* PM3 Normal drive output */
#define _08_PM3_HIDRV_ON (0x08u) /* PM3 High-drive output */
#define _00_PM4_HIDRV_OFF (0x00u) /* PM4 Normal drive output */
#define _10_PM4_HIDRV_ON (0x10u) /* PM4 High-drive output */
#define _00_PM5_HIDRV_OFF (0x00u) /* PM5 Normal drive output */
#define _20_PM5_HIDRV_ON (0x20u) /* PM5 High-drive output */
#define _00_PM6_HIDRV_OFF (0x00u) /* PM6 Normal drive output */
#define _40_PM6_HIDRV_ON (0x40u) /* PM6 High-drive output */
#define _00_PM7_HIDRV_OFF (0x00u) /* PM7 Normal drive output */
#define _80_PM7_HIDRV_ON (0x80u) /* PM7 High-drive output */
/* Drive Capacity Control Register 2 (DSCR2) */
/* Pmn Drive Capacity Control (B7 - B0) */
/* PM0 Normal drive/high-drive output */
#define _00_PM0_HISPEED_OFF (0x00u)
/* PM0 High-speed interface high-drive output */
#define _01_PM0_HISPEED_ON (0x01u)
/* PM1 Normal drive/high-drive output */
#define _00_PM1_HISPEED_OFF (0x00u)
/* PM1 High-speed interface high-drive output */
#define _02_PM1_HISPEED_ON (0x02u)
/* PM2 Normal drive/high-drive output */
#define _00_PM2_HISPEED_OFF (0x00u)
/* PM2 High-speed interface high-drive output */
#define _04_PM2_HISPEED_ON (0x04u)
/* PM3 Normal drive/high-drive output */
#define _00_PM3_HISPEED_OFF (0x00u)
/* PM3 High-speed interface high-drive output */
#define _08_PM3_HISPEED_ON (0x08u)
/* PM4 Normal drive/high-drive output */
#define _00_PM4_HISPEED_OFF (0x00u)
/* PM4 High-speed interface high-drive output */
#define _10_PM4_HISPEED_ON (0x10u)
/* PM5 Normal drive/high-drive output */
#define _00_PM5_HISPEED_OFF (0x00u)
/* PM5 High-speed interface high-drive output */
#define _20_PM5_HISPEED_ON (0x20u)
/* PM6 Normal drive/high-drive output */
#define _00_PM6_HISPEED_OFF (0x00u)
/* PM6 High-speed interface high-drive output */
#define _40_PM6_HISPEED_ON (0x40u)
/* PM7 Normal drive/high-drive output */
#define _00_PM7_HISPEED_OFF (0x00u)
/* PM7 High-speed interface high-drive output */
#define _80_PM7_HISPEED_ON (0x80u)
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
/****************************************************************************
* Name: r_port_create
*
* Description:
* Initializes Ports of rx65n
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_port_create(void);
/****************************************************************************
* Name: r_ether_port_configuration
*
* Description:
* Initializes Ethernet Ports of rx65n
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_port_configuration(void);
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Pheriperal enabling
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_ether_pheriperal_enable(void);
#endif
#endif /* __ARCH_RENESAS_SRC_RX65N_PORT_H */

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_schedulesigaction.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "sched/sched.h"
#include "up_internal.h"
#include "up_arch.h"
/****************************************************************************
* Public Funictions
****************************************************************************/
/****************************************************************************
* Name: up_schedule_sigaction
*
* Description:
* This function is called by the OS when one or more
* signal handling actions have been queued for execution.
* The architecture specific code must configure things so
* that the 'igdeliver' callback is executed on the thread
* specified by 'tcb' as soon as possible.
*
* This function may be called from interrupt handling logic.
*
* This operation should not cause the task to be unblocked
* nor should it cause any immediate execution of sigdeliver.
* Typically, a few cases need to be considered:
*
* (1) This function may be called from an interrupt handler
* During interrupt processing, all xcptcontext structures
* should be valid for all tasks. That structure should
* be modified to invoke sigdeliver() either on return
* from (this) interrupt or on some subsequent context
* switch to the recipient task.
* (2) If not in an interrupt handler and the tcb is NOT
* the currently executing task, then again just modify
* the saved xcptcontext structure for the recipient
* task so it will invoke sigdeliver when that task is
* later resumed.
* (3) If not in an interrupt handler and the tcb IS the
* currently executing task -- just call the signal
* handler now.
*
****************************************************************************/
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
flags = enter_critical_section();
/* Refuse to handle nested signal actions */
if (!tcb->xcp.sigdeliver)
{
/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/
sinfo("rtcb=0x%p g_current_regs=0x%p\n", this_task(), g_current_regs);
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and
* a task is signalling itself for some reason.
*/
if (!g_current_regs)
{
/* In this case just deliver the signal now. */
sigdeliver(tcb);
}
/* CASE 2: We are in an interrupt handler AND the
* interrupted task is the same as the one that
* must receive the signal, then we will have to modify
* the return state as well as the state in the TCB.
*/
else
{
/* Save the return PC and SR and one scratch register
* These will be restored by the signal trampoline after
* the signals have been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = g_current_regs[REG_PC];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
g_current_regs[REG_PC] = (uint32_t)up_sigdeliver;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
up_copystate(tcb->xcp.regs, (uint32_t *)&g_current_regs);
}
}
/* Otherwise, we are (1) signaling a task is not running
* from an interrupt handler or (2) we are not in an
* interrupt handler and the running task is signalling
* some non-running task.
*/
else
{
/* Save the return PC and SR and one scratch register
* These will be restored by the signal trampoline after
* the signals have been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
tcb->xcp.saved_sr = tcb->xcp.regs[REG_PSW];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PSW] |= 0x00030000;
}
}
leave_critical_section(flags);
}

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/****************************************************************************
* arch/renesas/src/rx65n/rx65n_sigdeliver.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "sched/sched.h"
#include "up_internal.h"
#include "up_arch.h"
=/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_sigdeliver
*
* Description:
* This is the a signal handling trampoline. When a signal action was
* posted. The task context was mucked with and forced to branch to this
* location with interrupts disabled.
*
****************************************************************************/
void up_sigdeliver(void)
{
#ifndef CONFIG_DISABLE_SIGNALS
struct tcb_s *rtcb = this_task();
uint32_t regs[XCPTCONTEXT_REGS];
sig_deliver_t sigdeliver;
/* Save the errno. This must be preserved throughout the signal handling
* so that the user code final gets the correct errno value (probably
* EINTR).
*/
int saved_errno = rtcb->pterrno;
board_autoled_on(LED_SIGNAL);
sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
/* Save the real return state on the stack. */
up_copystate(regs, rtcb->xcp.regs);
regs[REG_PC] = rtcb->xcp.saved_pc;
regs[REG_PSW] = rtcb->xcp.saved_sr;
/* Get a local copy of the sigdeliver function pointer. We do this so
* that we can nullify the sigdeliver function pointer in the TCB and
* accept more signal deliveries while processing the current pending
* signals.
*/
sigdeliver = rtcb->xcp.sigdeliver;
rtcb->xcp.sigdeliver = NULL;
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Then make sure that interrupts are enabled. Signal handlers must always
* run with interrupts enabled.
*/
up_irq_enable();
#endif
/* Deliver the signals */
sigdeliver(rtcb);
/* Output any debug messages BEFORE restoring errno (because they may
* alter errno), then disable interrupts again and restore the original
* errno that is needed by the user logic (it is probably EINTR).
*/
sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
/* Then restore the correct state for this thread of
* execution.
*/
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
#endif
}

170
arch/renesas/src/rx65n/rx65n_timerisr.c Normal file
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@ -0,0 +1,170 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_timerisr.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "rx65n/irq.h"
#include "clock/clock.h"
#include "up_internal.h"
#include "up_arch.h"
#include "rx65n/iodefine.h"
#include "chip.h"
#include "rx65n_cmt.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* ITU1 operates in periodic timer mode. TCNT counts up until it matches
* the value of GRA0, then an interrupt is generated. Two values must be
* computed:
*
* (1) The divider that determines the rate at which TCNT increments, and
* (2) The value of GRA0 that cause the interrupt to occur.
*
* These must be selected so that the frequency of interrupt generation is
* CLK_TCK. Ideally, we would like to use the full range of GRA0 for better
* timing acuracy:
*/
/* The ideal divider would be one that generates exactly 65535 ticks in
* 1/CLK_TCK seconds. For example, if RX_CLOCK is 10MHz and CLK_TCK is
* 100, then the ideal divider must be less greater than or equal to:
*
* (10,000,000 / CLK_TCK) / 65535 = 1.525
*
* The actual selected divider would then have to be 2, resulting in a
* counting rate of 5,000,0000 and a GRA0 setting of 50,000.
*/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: rx65n_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int rx65n_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: renesas_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void renesas_timer_initialize(void)
{
uint16_t reg16;
uint32_t reg32;
/* Enable write to System registers */
putreg16(RX65N_PRCR_VALUE, RX65N_PRCR_ADDR);
/* Start CMT module */
reg32 = getreg32(RX65N_MSTPCRA_ADDR);
reg32 &= (~RX65N_CMT_MSTPCRA_STOP);
putreg32(reg32, RX65N_MSTPCRA_ADDR);
/* Disable CMT interrupt */
putreg16(RX65N_CMT_CMCR_DEFAULT, RX65N_CMT0_CMCR_ADDR);
IEN(CMT0, CMI0) = 0;
/* Set CMI0 priority level */
IPR(CMT0, CMI0) = _0F_CMT_PRIORITY_LEVEL15;
/* Set Counter to 0 initially */
putreg16(0, RX65N_CMT0_CMCNT_ADDR);
/* Set the CMCOR match value. The interrupt will be generated when TNCT
* increments to this value
*/
putreg16(RX65N_CMT0_COUNT_VALUE, RX65N_CMT0_CMCOR_ADDR);
/* Attach the IMIA0 IRQ */
irq_attach(RX65N_CMI0_IRQ, (xcpt_t)rx65n_timerisr, NULL);
/* Set control registers */
putreg16(RX65N_CMT_CMCR_INIT, RX65N_CMT0_CMCR_ADDR);
IEN(CMT0, CMI0) = 1;
/* Start the timer */
reg16 = getreg16(RX65N_CMT_CMSTR0_ADDR);
reg16 |= RX65N_CMTCMSTR0_STR0; /* Enable TCNT0 */
putreg16(reg16, RX65N_CMT_CMSTR0_ADDR); /* TCNT0 is counting */
}

1418
arch/renesas/src/rx65n/rx65n_vector.S Normal file
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File diff suppressed because it is too large Load diff

248
arch/renesas/src/rx65n/rx65n_vector_table.c Normal file
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@ -0,0 +1,248 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_vector_table.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "chip.h"
#include "stdint.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define OFS_REG __attribute__ ((section (".ofs1"))) /* 0xfe7f5d00 */
#define OFS_TMINF __attribute__ ((section (".ofs2"))) /* 0xfe7f5d10 */
#define OFS_SPCC __attribute__ ((section (".ofs3"))) /* 0xfe7f5d40 */
#define OFS_TMEF __attribute__ ((section (".ofs4"))) /* 0xfe7f5d48 */
#define OFS_OSIS __attribute__ ((section (".ofs5"))) /* 0xfe7f5d50 */
#define OFS_FAW __attribute__ ((section (".ofs6"))) /* 0xfe7f5d64 */
#define OFS_ROMCODE __attribute__ ((section (".ofs7"))) /* 0xfe7f5d70 */
/* SPCC register */
const unsigned long __spccreg OFS_SPCC = 0xffffffff;
/* TMEF register */
const unsigned long __tmefreg OFS_TMEF = 0xffffffff;
/* OSIS register (ID codes) */
const unsigned long __osisreg[4] OFS_OSIS =
{
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff
};
/* TMINF register */
const unsigned long __tminfreg OFS_TMINF = 0xffffffff;
/* FAW register */
const unsigned long __fawreg OFS_FAW = 0xffffffff;
/* ROMCODE register */
const unsigned long __romcodereg OFS_ROMCODE = 0xffffffff;
/* MDE register (Single Chip Mode) */
#ifdef __RX_BIG_ENDIAN__
const unsigned long __mdereg OFS_REG = 0xfffffff8; /* big */
#else
const unsigned long __mdereg OFS_REG = 0xffffffff; /* little */
#endif
const unsigned long __ofs0reg OFS_REG = 0xffffffff; /* OFS0 register */
const unsigned long __ofs1reg OFS_REG = 0xffffffff; /* OFS1 register */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: r_undefined_exception
*
* Description:
* Handler for undefined exception
****************************************************************************/
void r_undefined_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
/****************************************************************************
* Name: r_reserved_exception
*
* Description:
* Handler for reserved exception
****************************************************************************/
void r_reserved_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
/****************************************************************************
* Name: r_nmi_exception
*
* Description:
* Handler for nmi exception
****************************************************************************/
void r_nmi_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
/****************************************************************************
* Name: r_brk_exception
*
* Description:
* Handler for brk exception
****************************************************************************/
void r_brk_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
/****************************************************************************
* Name: r_privileged_exception
*
* Description:
* Handler for privileged exception
****************************************************************************/
void r_privileged_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
/****************************************************************************
* Name: r_access_exception
*
* Description:
* Handler for access exception
****************************************************************************/
void r_access_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
/****************************************************************************
* Name: r_floatingpoint_exception
*
* Description:
* Handler for floating point exception
****************************************************************************/
void r_floatingpoint_exception(void)
{
#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS
__asm("nop");
#endif
}
#define EXVECT_SECT __attribute__ ((section (".exvectors")))
const void *except_vectors[] EXVECT_SECT =
{
r_reserved_exception, /* 0xffffff80 Reserved */
r_reserved_exception, /* 0xffffff84 Reserved */
r_reserved_exception, /* 0xffffff88 Reserved */
r_reserved_exception, /* 0xffffff8c Reserved */
r_reserved_exception, /* 0xffffff90 Reserved */
r_reserved_exception, /* 0xffffff94 Reserved */
r_reserved_exception, /* 0xffffff98 Reserved */
r_reserved_exception, /* 0xffffff9c Reserved */
r_reserved_exception, /* 0xffffffa0 Reserved */
r_reserved_exception, /* 0xffffffa4 Reserved */
r_reserved_exception, /* 0xffffffa8 Reserved */
r_reserved_exception, /* 0xffffffac Reserved */
r_reserved_exception, /* 0xffffffb0 Reserved */
r_reserved_exception, /* 0xffffffb4 Reserved */
r_reserved_exception, /* 0xffffffb8 Reserved */
r_reserved_exception, /* 0xffffffbc Reserved */
r_reserved_exception, /* 0xffffffc0 Reserved */
r_reserved_exception, /* 0xffffffc4 Reserved */
r_reserved_exception, /* 0xffffffc8 Reserved */
r_reserved_exception, /* 0xffffffcc Reserved */
r_privileged_exception, /* 0xffffffd0 Exception */
r_access_exception, /* 0xffffffd4 Exception */
r_reserved_exception, /* 0xffffffd8 Reserved */
r_undefined_exception, /* 0xffffffdc Exception */
r_reserved_exception, /* 0xffffffe0 Reserved */
r_floatingpoint_exception, /* 0xffffffe4 Exception */
r_undefined_exception, /* 0xffffffe8 Reserved */
r_undefined_exception, /* 0xffffffec Reserved */
r_undefined_exception, /* 0xfffffff0 Reserved */
r_undefined_exception, /* 0xfffffff4 Reserved */
r_nmi_exception /* 0xfffffff8 NMI */
};
#define FVECT_SECT __attribute__ ((section (".fvectors")))
extern void _start(void); /* defined in rx65n_head.S */
const void *hardware_vectors[] FVECT_SECT =
{
/* 0xfffffffc RESET */
_start /* Power On Reset PC */
};
#define RVECT_SECT __attribute__ ((section (".rvectors")))
const void *relocatable_vectors[256] RVECT_SECT =
{
0
};

51
boards/Kconfig
View file

@ -1159,6 +1159,41 @@ config ARCH_BOARD_QEMU_I486
Port of NuttX to QEMU in i486 mode. This port will also run on real i486
hardwared (Google the Bifferboard).
config ARCH_BOARD_RX65N
bool "RX65N renesas board"
depends on ARCH_CHIP_R5F565NEDDFC
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
---help---
This is a port of the renesas RX65N on the Renesas RX65N board.
STATUS: Work has just began on this port.
config ARCH_BOARD_RX65N_RSK1MB
bool "RX65N on RSKRX65N-1MB renesas board"
depends on ARCH_CHIP_R5F565NEDDFC
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
---help---
This is a port of the renesas RX65N on the Renesas RX65N board.
STATUS: Work has just began on this port.
config ARCH_BOARD_RX65N_RSK2MB
bool "RX65N on RSKRX65N-2MB renesas board"
depends on ARCH_CHIP_R5F565NEHDFC
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
---help---
This is a port of the renesas RX65N on the Renesas RX65N board.
STATUS: Work has just began on this port.
config ARCH_BOARD_RX65N_GRROSE
bool "RX65N on GR-ROSE renesas board"
depends on ARCH_CHIP_R5F565NEHDFP
select ARCH_HAVE_LEDS
---help---
This is a port of the renesas RX65N on the Renesas RX65N board.
STATUS: Work has just began on this port.
config ARCH_BOARD_S32K118EVB
bool "NXP S32K118EVB"
depends on ARCH_CHIP_S32K118
@ -2022,6 +2057,10 @@ config ARCH_BOARD
default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB
default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT
default "qemu-i486" if ARCH_BOARD_QEMU_I486
default "rx65n" if ARCH_BOARD_RX65N
default "rx65n" if ARCH_BOARD_RX65N_RSK1MB
default "rx65n" if ARCH_BOARD_RX65N_RSK2MB
default "rx65n" if ARCH_BOARD_RX65N_GRROSE
default "s32k118evb" if ARCH_BOARD_S32K118EVB
default "s32k146evb" if ARCH_BOARD_S32K146EVB
default "s32k148evb" if ARCH_BOARD_S32K148EVB
@ -2647,6 +2686,18 @@ endif
if ARCH_BOARD_QEMU_I486
source "boards/x86/qemu/qemu-i486/Kconfig"
endif
if ARCH_BOARD_RX65N
source "boards/renesas/rx65n/rx65n/Kconfig"
endif
if ARCH_BOARD_RX65N_RSK1MB
source "boards/renesas/rx65n/rx65n-rsk1mb/Kconfig"
endif
if ARCH_BOARD_RX65N_RSK2MB
source "boards/renesas/rx65n/rx65n-rsk2mb/Kconfig"
endif
if ARCH_BOARD_RX65N_GRROSE
source "boards/renesas/rx65n/rx65n-grrose/Kconfig"
endif
if ARCH_BOARD_ESP32CORE
source "boards/xtensa/esp32/esp32-core/Kconfig"
endif

4
boards/renesas/rx65n/drivers/Kconfig Normal file
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@ -0,0 +1,4 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

7
boards/renesas/rx65n/rx65n-grrose/Kconfig Normal file
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@ -0,0 +1,7 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_RX65N_GRROSE
endif

254
boards/renesas/rx65n/rx65n-grrose/README.txt Normal file
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@ -0,0 +1,254 @@
README
======
This README file discusses the port of NuttX to “GR-ROSE” board produced by Gadget Renesas.This board features the RX65N (R5F565NEHDFP 100pin QFP)
Contents
========
- Board Features
- Status/Open Issues
- Serial Console
- LEDs
- Networking
- Debugging
Board Features
==============
- Micro controller - RX65N (R5F565NEHDFP 100pin QFP) RXv2 core [34 CoreMark/mA]
- ROM/RAM - 2MB/640KB
- Operating Frequency - 120MHz(12MHz 10 Multiplication)
- RTC Clock - 32.768kHz
- Sensors - Temperature(inside MCU)
- ROS I/F - Ethernet, USB(rosserial)
- Serial Servo I/F - TTL x 4, RS-485 x 1
- Analog I/F - ADC(12bit) x 6, DAC x 1
- Wireless - IEEE 802.11b/g/n
- PMOD I/F - 1 (I2C, SPI, UART)
- External power supply - USB VBUS or 4.5V～18V
- Supply to external - 3.3V, 5V
See the RX65N GRROSE website for further information about this board:
- http://gadget.renesas.com/en/product/rose.html
Status/Open Issues
==================
Ethernet
---------
1.Observed instability in Link Management, due to difference in hardware design.(No Seperate Interrupt line for PHY)
2.Currently tested only ping and udpblaster application.
3. Executed long run ping and udpblaster stress test for 12 hrs. Code is able to execute for 12hrs without any breakage.
Serial Console
==============
RX65N GRROSE supports 12 serial ports (SCI0 - SCI12), however only 5 ports can be tested(SCI0, SCI1, SCI2,
SCI5 & SCI6).
Please find the pin configurations for SCI0, SCI1, SCI2, SCI5 & SCI6
SCI0 Pin Configuration :
-----------
RX65N GRROSE
Function
-----------
P21 RXD0
P20 TXD0
------------
SCI1 Pin Configuration :
-----------
RX65N GRROSE
Function
-----------
P30 RXD1
P26 TXD1
------------
SCI2 Pin Configuration :
-----------
RX65N GRROSE
Function
-----------
P12 RXD2
P13 TXD2
------------
SCI3 Pin Configuration :
-----------
RX65N GRROSE
Function (connected to WiFi module)
-----------
P25 RXD3
P23 TXD3
------------
SCI5 Pin Configuration :
-----------
RX65N GRROSE
Function
-----------
PC2 RXD5
PC3 TXD5
------------
SCI6 Pin Configuration :
-----------
RX65N GRROSE
Function
-----------
P33 RXD6
P32 TXD6
------------
SCI8 Pin Configuration :
-----------
RX65N GRROSE
Function (Half duplication mode with RS485 driver)
-----------
PC6 RXD8
PC7 TXD8
PC5 Direction (L=TX, H=RX)
Serial Connection Configuration
--------------------------
1. GRROSE board needs to be connected to PC terminal, using USB to Serial Chip.
2. Connect TX of USB to serial chip to RX of SCIX(0,1,2,5,6)
3. Connect RX of USB to serial chip to TX of SCIX(0,1,2,5,6)
4. Connect GND to GND pin.
5. Configure Teraterm to 115200 baud.
LEDs
====
The RX65N GRROSE board has 2 LED's, 1 Power LED(LED3) and 2 User LED's(LED1, LED2),which are enabled through software.
If enabled the LED is simply turned on when the board boots
successfully, and is blinking on panic / assertion failed.
Networking
==========
Ethernet Connections
-----------
------ ---------
RX65N
GRROSE Ethernet
Pin Function
------ ---------
PA4 ET0_MDC
PA3 ET0_MDIO
PB2 REF50CK0
PB7 RMII0_CRS_DV
PB1 RMII0_RXD0
PB0 RMII0_RXD1
PB3 RMII0_RX_ER
PB5 RMII0_ETXD0
PB6 RMII0_ETXD1
PB4 RMII0_TXD_EN
PA5 ET0_LINKSTA
PA6_ET_RST ETHER reset
------ ---------
NuttX Configurations
---------------
The following configurations, need to be enabled for network.
CONFIG_RX65N_EMAC=y : Enable the EMAC Peripheral for RX65N
CONFIG_RX65N_EMAC0=y : Enable the EMAC Peripheral for RX65N
CONFIG_RX65N_EMAC0_PHYSR=30 : Address of PHY status register on LAN8720A
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18 : Needed for LAN8720A
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08 : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14 : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04 : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c : " " " " " "
CONFIG_RX65N_EMAC0_RMII=y
CONFIG_RX65N_EMAC0_PHYADDR=0 : LAN8720A PHY is at address 1
CONFIG_SCHED_WORKQUEUE=y : Work queue support is needed
CONFIG_SCHED_HPWORK=y : High Priority Work queue support
CONFIG_SCHED_LPWORK=y : Low Priority Work queue support
Using the network with NSH
--------------------------
The IP address is configured using DHCP, using the below mentioned configurations :
The IP address is configured using DHCP, using the below mentioned configurations :
CONFIG_NETUTILS_DHCPC=y
CONFIG_NETUTILS_DHCPD=y
CONFIG_NSH_DHCPC=y
CONFIG_NETINIT_DHCPC=y
nsh> ifconfig
eth0 HWaddr 00:e0:de:ad:be:ef at UP
IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0
You can use ping to test for connectivity to the host (Careful,
Window firewalls usually block ping-related ICMP traffic). On the
target side, you can:
nsh> ping 10.75.24.250
PING 10.75.24.250 56 bytes of data
56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms
10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
On the host side, you should also be able to ping the RX65N-GRROSE:
$ ping 10.75.24.53
Configure UDP blaster application as mentioned below :
CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801 (10.75.24.1) ------> Gateway IP
CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
Debugging
==========
1. NuttX needs to be compiled in Cygwin.
The following Configuration needs to be set, in order to do source level debugging.
CONFIG_DEBUG_SYMBOLS = y (Set this option, using menuconfig only, DO NOT Enable this as default configuration).
2. Download & Install Renesas e2studio IDE.
3. Load the project(NuttX built on Cygwin) as Makefile project with existing code
4. Right click on the project, and select Debug Configurations.
5. The binary(NuttX) needs to be loaded using E1/E2 Emulator.
6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used)
7. Select Connection type as FINE.
8. Load and run the binary.
Flashing NuttX
===============
Alternativly, NuttX binary can be flashed using Renesas flash programmer tool without using e2 studio/Cygwin
Below are the steps mentioned to flash NuttX binary using Renesas flash programmer tool(RFP).
1.In order to flash using Renesas flash programmer tool, nuttx.mot file should be generated.
2. Add the following lines in tools/Makefile.unix file :
ifeq ($(CONFIG_MOTOROLA_SREC),y)
@echo "CP: $(NUTTXNAME).mot"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns $(NUTTXNAME).mot
endif
3. Add CONFIG_MOTOROLA_SREC=y in defconfig file or choose make menucofig->Build Setup-> Binary Output Format->
Select Motorola SREC format.
4. Download Renesas flash programmer tool from https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads
5. Refer to the user manual document, for steps to flash NuttX binary using RFP tool.

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CONFIG_ARCH_BOARD_RX65N_GRROSE=y
CONFIG_ARCH_BOARD="rx65n-grrose"
CONFIG_ARCH_CHIP_R5F565NEHDFP=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
CONFIG_ARCH_CHIP="rx65n"
CONFIG_BOARD_LOOPSPERMSEC=15001
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_ETH0_PHY_LAN8720A=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=655360
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
CONFIG_RX65N_SCI0=y
CONFIG_RX65N_SCI1=y
CONFIG_RX65N_SCI2=y
CONFIG_RX65N_SCI5=y
CONFIG_RX65N_SCI6=y
CONFIG_RX65N_SCI8=y
CONFIG_SCI0_SERIALDRIVER=y
CONFIG_SCI0_BAUD=115200
CONFIG_SCI1_SERIAL_CONSOLE=y
CONFIG_SCI1_SERIALDRIVER=y
CONFIG_SCI1_BAUD=115200
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_BAUD=115200
CONFIG_SCI5_SERIALDRIVER=y
CONFIG_SCI5_BAUD=921600
CONFIG_SCI6_SERIALDRIVER=y
CONFIG_SCI6_BAUD=115200
CONFIG_SCI8_SERIALDRIVER=y
CONFIG_SCI8_BAUD=115200
CONFIG_RX65N_EMAC=y
CONFIG_RX65N_EMAC0=y
CONFIG_RX65N_EMAC0_PHYSR=30
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c
CONFIG_RX65N_EMAC0_RMII=y
CONFIG_RX65N_EMAC0_PHYADDR=0
CONFIG_SCHED_WORKQUEUE=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SYSTEM_PING=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_IDLETHREAD_STACKSIZE=1024
CONFIG_FS_PROCFS=y
CONFIG_FS_PROCFS_REGISTER=y
CONFIG_NET_ETH_PKTSIZE = 590
CONFIG_RX65N_CMTW0=y
CONFIG_RX65N_PERIB=y
CONFIG_NETUTILS_DHCPC=y
CONFIG_NETUTILS_DHCPD=y
CONFIG_NSH_DHCPC=y
CONFIG_NETINIT_DHCPC=y
CONFIG_SYSTEM_NSH_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER=y
CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y

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CONFIG_ARCH_BOARD_RX65N_GRROSE=y
CONFIG_ARCH_BOARD="rx65n-grrose"
CONFIG_ARCH_CHIP_R5F565NEHDFP=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
CONFIG_ARCH_CHIP="rx65n"
CONFIG_BOARD_LOOPSPERMSEC=15001
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=655360
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
CONFIG_RX65N_SCI0=y
CONFIG_RX65N_SCI1=y
CONFIG_RX65N_SCI2=y
CONFIG_RX65N_SCI5=y
CONFIG_RX65N_SCI6=y
CONFIG_RX65N_SCI8=y
CONFIG_SCI0_SERIALDRIVER=y
CONFIG_SCI0_BAUD=115200
CONFIG_SCI1_SERIAL_CONSOLE=y
CONFIG_SCI1_SERIALDRIVER=y
CONFIG_SCI1_BAUD=115200
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_BAUD=115200
CONFIG_SCI5_SERIALDRIVER=y
CONFIG_SCI5_BAUD=115200
CONFIG_SCI6_SERIALDRIVER=y
CONFIG_SCI6_BAUD=115200
CONFIG_SCI8_SERIALDRIVER=y
CONFIG_SCI8_BAUD=115200
CONFIG_SDCLONE_DISABLE=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_IDLETHREAD_STACKSIZE=1024

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/***************************************************************************
* configs/rx65n/include/board.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _CONFIGS_RX65N_BOARD_H
#define _CONFIGS_RX65N_BOARD_H
/***************************************************************************
* Included Files
***************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Clocking ****************************************************************/
#define RX_CLK_1MHz (1000UL * 1000UL)
#define RX_FCLK ( 60 * RX_CLK_1MHz)
#define RX_ICLK (120 * RX_CLK_1MHz)
#define RX_PCLKA (120 * RX_CLK_1MHz)
#define RX_PCLKB ( 60 * RX_CLK_1MHz)
#define RX_PCLKC ( 60 * RX_CLK_1MHz)
#define RX_PCLKD ( 60 * RX_CLK_1MHz)
#define RX_BCK (120 * RX_CLK_1MHz)
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define RX_RESONATOR ( 12 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#else
#error "Please definition RX_RESONATOR in board.h"
#endif
/* LED definitions */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define LED0 (PORT7.PODR.BIT.B3)
#define LED1 (PORTG.PODR.BIT.B7)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \
PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \
PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \
PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \
PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define LED0 (PORTA.PODR.BIT.BT0)
#define LED1 (PORTA.PODR.BIT.B1)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \
PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \
PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \
PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \
PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \
}
#else
#errror "LEDs are not defined."
#endif
#define LED_STARTED 1 /* ON OFF NC NC */
#define LED_HEAPALLOCATE 0 /* NC NC NC NC */
#define LED_IRQSENABLED 0 /* NC NC NC NC */
#define LED_STACKCREATED 2 /* ON ON NC NC */
#define LED_INIRQ 0 /* NC NC NC NC */
#define LED_SIGNAL 0 /* NC NC NC NC */
#define LED_ASSERTION 0 /* NC NC NC NC */
#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */
/* Button definitions *******************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* _CONFIGS_RX65N_BOARD_H */

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##############################################################################
# configs/rx65n-grrose/scripts/Make.defs
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
##############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ifeq ($(CONFIG_HOST_WINDOWS),y)
WINTOOL=y
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}"
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
else
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
endif
CROSSDEV = rx-elf-
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
AS = $(CROSSDEV)as
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
$(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDMODULEFLAGS = -r -e module_initialize
ifeq ($(WINTOOL),y)
LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
else
LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
ASMEXT = .asm
OBJEXT = .o
LIBEXT = .a
EXEEXT =
#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

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MEMORY
{
/* RSK-RX65N-1MB */
/*
RAM : ORIGIN = 0x0, LENGTH = 262144
ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
*/
/* RSK-RX65N-2MB | GR-ROSE */
RAM : ORIGIN = 0x0, LENGTH = 262144
RAMHI : ORIGIN = 0x800000, LENGTH = 393216
ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
}
SECTIONS
{
.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
{
_exvectors_start = .;
KEEP(*(.exvectors))
_exvectors_end = .;
} > ROM
.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
{
KEEP(*(.fvectors))
} > ROM
/* RSK-RX65N-1MB */
.text 0xFFF00000: AT(0xFFF00000)
/* RSK-RX65N-2MB | GR-ROSE */
/*.text 0xFFE00000: AT(0xFFE00000) */
{
*(.text)
. = ALIGN(4);
*(.text.*)
. = ALIGN(4);
*(P)
etext = .;
} > ROM
.rvectors :
{
_rvectors_start = .;
KEEP(*(.rvectors))
_rvectors_end = .;
} > ROM
/*.exvectors :
{
_exvectors_start = .;
KEEP(*(.exvectors))
_exvectors_end = .;
} > ROM */
.init :
{
KEEP(*(.init))
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
__init_array_start = (. + 3) & ~ 3;
KEEP(*(.init_array))
KEEP(*(SORT(.init_array.*)))
__init_array_end = .;
__fini_array_start = .;
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
__fini_array_end = .;
} > ROM
.fini :
{
KEEP(*(.fini))
} > ROM
.got :
{
*(.got)
*(.got.plt)
} > ROM
.rodata :
{
*(.rodata)
*(.rodata.*)
*(C_1)
*(C_2)
*(C)
_erodata = .;
} > ROM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > ROM
.eh_frame :
{
*(.eh_frame)
} > ROM
.jcr :
{
*(.jcr)
} > ROM
.tors :
{
__CTOR_LIST__ = .;
. = ALIGN(2);
___ctors = .;
*(.ctors)
___ctors_end = .;
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___dtors = .;
*(.dtors)
___dtors_end = .;
__DTOR_END__ = .;
. = ALIGN(2);
_mdata = .;
} > ROM
.ustack 0x400: AT(0x200)
{
_ustack = .;
} > RAM
.istack 0x200: AT(0x200)
{
_istack = .;
} > RAM
.data 0x404: AT(_mdata)
{
_data = .;
*(.data)
*(.data.*)
*(D)
*(D_1)
*(D_2)
_edata = .;
} > RAM
.gcc_exc :
{
*(.gcc_exc)
} > RAM
.bss :
{
_bss = .;
*(.bss)
*(.bss.**)
*(COMMON)
*(B)
*(B_1)
*(B_2)
_ebss = .;
_end = .;
} >RAM
.ofs1 0xFE7F5D40: AT(0xFE7F5D00)
{
KEEP(*(.ofs1))
} > OFS
.ofs2 0xFE7F5D48: AT(0xFE7F5D10)
{
KEEP(*(.ofs2))
} > OFS
.ofs3 0xFE7F5D50: AT(0xFE7F5D40)
{
KEEP(*(.ofs3))
} > OFS
.ofs4 0xFE7F5D10: AT(0xFE7F5D48)
{
KEEP(*(.ofs4))
} > OFS
.ofs5 0xFE7F5D10: AT(0xFE7F5D50)
{
KEEP(*(.ofs5))
} > OFS
.ofs6 0xFE7F5D10: AT(0xFE7F5D64)
{
KEEP(*(.ofs6))
} > OFS
.ofs7 0xFE7F5D10: AT(0xFE7F5D70)
{
KEEP(*(.ofs7))
} > OFS
}

82
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############################################################################
# configs/rx65n-grrose/src/Makefile
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched
CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
CSRCS = rx65n_main.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
OBJS = $(AOBJS) $(COBJS)
CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/include
all: libboard$(LIBEXT)
$(AOBJS): %$(OBJEXT): %$(ASMEXT)
$(call ASSEMBLE, $<, $@)
$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
libboard$(LIBEXT): $(OBJS)
$(call ARCHIVE, $@, $(OBJS))
.depend: Makefile $(SRCS)
$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) touch $@
depend: .depend
clean:
$(call DELFILE, libboard$(LIBEXT))
$(call CLEAN)
distclean: clean
$(call DELFILE, Make.dep)
$(call DELFILE, .depend)
ifneq ($(BOARD_CONTEXT),y)
context:
endif
-include Make.dep

126
boards/renesas/rx65n/rx65n-grrose/src/rx65n_main.c Normal file
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/****************************************************************************
* configs/rx65n-grrose/src/rx65n.main.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
*Included files
***************************************************************************/
#include "rx65n_macrodriver.h"
#include "arch/board/board.h"
#include "rx65n_definitions.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled1_on
*
* Description:
* Turns on LED 0
*
****************************************************************************/
void board_autoled1_on(int led)
{
LED0 = LED_ON;
}
/****************************************************************************
* Name: board_autoled2_on
*
* Description:
* Turns on LED 1
*
****************************************************************************/
void board_autoled2_on(int led)
{
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled_on
*
* Description:
* Turns on LED 0 & LED 1
*
****************************************************************************/
void board_autoled_on(int led)
{
LED0 = LED_ON;
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled1_off
*
* Description:
* Turns off LED 0
*
****************************************************************************/
void board_autoled1_off(int led)
{
LED0 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled2_off
*
* Description:
* Turns off LED 1
*
****************************************************************************/
void board_autoled2_off(int led)
{
LED1 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled_off
*
* Description:
* Turns off LED 0 & LED 1
*
****************************************************************************/
void board_autoled_off(int led)
{
LED0 = LED_OFF;
LED1 = LED_OFF;
}

7
boards/renesas/rx65n/rx65n-rsk1mb/Kconfig Normal file
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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_RX65N_RSK1MB
endif

102
boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig Normal file
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_RX65N=y
#CONFIG_ARCH_BOARD_RX65N_RSK1MB=y
CONFIG_ARCH_BOARD="rx65n"
CONFIG_ARCH_CHIP_R5F565NEDDFC=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
#CONFIG_BOARD_LOOPSPERMSEC=572
#CONFIG_DISABLE_MOUNTPOINT=y
#CONFIG_DISABLE_MQUEUE=y
#CONFIG_DISABLE_POLL=y
#CONFIG_DISABLE_POSIX_TIMERS=y
#CONFIG_DISABLE_PTHREAD=y
#CONFIG_DISABLE_SIGNALS=y
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_ETH0_PHY_KSZ8081=y
CONFIG_NET=y
#CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETDEV_STATISTICS=y
#CONFIG_NETUTILS_TELNETD=y
CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
#CONFIG_NSH_CONSOLE_LOGIN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=655360
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
#CONFIG_SCI0_SERIALDRIVER=y
#CONFIG_SCI0_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI0=y
#CONFIG_SCI1_SERIALDRIVER=y
#CONFIG_SCI1_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI1=y
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI2=y
#CONFIG_SCI8_SERIALDRIVER=y
#CONFIG_SCI8_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI8=y
CONFIG_RX65N_EMAC=y
CONFIG_RX65N_EMAC0=y
CONFIG_RX65N_EMAC0_PHYSR=30
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x6
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x2
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x5
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x1
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x7
CONFIG_RX65N_EMAC0_MII=y
CONFIG_RX65N_EMAC0_PHYADDR=30
CONFIG_SCHED_WORKQUEUE=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SYSTEM_PING=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_FS_PROCFS=y
CONFIG_FS_PROCFS_REGISTER=y
CONFIG_NET_ETH_PKTSIZE = 1518
CONFIG_RX65N_CMT2=y
CONFIG_RX65N_CMT3=y
CONFIG_RX65N_PERIB=y
#CONFIG_NET_IPv6=y
#CONFIG_NET_ICMPv6=y
#CONFIG_NET_MCASTGROUP=y

55
boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig Normal file
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_RX65N=y
#CONFIG_ARCH_BOARD_RX65N_RSK1MB=y
CONFIG_ARCH_BOARD="rx65n"
CONFIG_ARCH_CHIP_R5F565NEDDFC=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
#CONFIG_BOARD_LOOPSPERMSEC=572
#CONFIG_DISABLE_MOUNTPOINT=y
#CONFIG_DISABLE_MQUEUE=y
#CONFIG_DISABLE_POLL=y
#CONFIG_DISABLE_POSIX_TIMERS=y
#CONFIG_DISABLE_PTHREAD=y
#CONFIG_DISABLE_SIGNALS=y
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
#CONFIG_NSH_CONSOLE_LOGIN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=262144
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
#CONFIG_SCI0_SERIALDRIVER=y
#CONFIG_SCI0_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI0=y
#CONFIG_SCI1_SERIALDRIVER=y
#CONFIG_SCI1_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI1=y
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI2=y
#CONFIG_SCI8_SERIALDRIVER=y
#CONFIG_SCI8_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI8=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024

150
boards/renesas/rx65n/rx65n-rsk1mb/include/board.h Normal file
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/***************************************************************************
* configs/rx65n/include/board.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _CONFIGS_RX65N_BOARD_H
#define _CONFIGS_RX65N_BOARD_H
/***************************************************************************
* Included Files
***************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Clocking */
#define RX_CLK_1MHz (1000UL * 1000UL)
#define RX_FCLK ( 60 * RX_CLK_1MHz)
#define RX_ICLK (120 * RX_CLK_1MHz)
#define RX_PCLKA (120 * RX_CLK_1MHz)
#define RX_PCLKB ( 60 * RX_CLK_1MHz)
#define RX_PCLKC ( 60 * RX_CLK_1MHz)
#define RX_PCLKD ( 60 * RX_CLK_1MHz)
#define RX_BCK (120 * RX_CLK_1MHz)
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define RX_RESONATOR ( 12 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#else
#error "Please definition RX_RESONATOR in board.h"
#endif
/* LED definitions */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define LED0 (PORT7.PODR.BIT.B3)
#define LED1 (PORTG.PODR.BIT.B7)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \
PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \
PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \
PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \
PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define LED0 (PORTA.PODR.BIT.BT0)
#define LED1 (PORTA.PODR.BIT.B1)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \
PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \
PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \
PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \
PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \
}
#else
#errror "LEDs are not defined."
#endif
#define LED_STARTED 1 /* ON OFF NC NC */
#define LED_HEAPALLOCATE 0 /* NC NC NC NC */
#define LED_IRQSENABLED 0 /* NC NC NC NC */
#define LED_STACKCREATED 2 /* ON ON NC NC */
#define LED_INIRQ 0 /* NC NC NC NC */
#define LED_SIGNAL 0 /* NC NC NC NC */
#define LED_ASSERTION 0 /* NC NC NC NC */
#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */
/* Button definitions */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* _CONFIGS_RX65N_BOARD_H */

123
boards/renesas/rx65n/rx65n-rsk1mb/scripts/Make.defs Normal file
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##############################################################################
# configs/rx65n-rsk1mb/scripts/Make.defs
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
##############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ifeq ($(CONFIG_HOST_WINDOWS),y)
WINTOOL=y
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}"
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
else
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
endif
CROSSDEV = rx-elf-
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
AS = $(CROSSDEV)as
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
$(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDMODULEFLAGS = -r -e module_initialize
ifeq ($(WINTOOL),y)
LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
else
LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
ASMEXT = .asm
OBJEXT = .o
LIBEXT = .a
EXEEXT =
#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

167
boards/renesas/rx65n/rx65n-rsk1mb/scripts/linker_script.ld Normal file
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MEMORY
{
/* RSK-RX65N-1MB */
RAM : ORIGIN = 0x0, LENGTH = 262144
ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
/* RSK-RX65N-2MB | GR-ROSE */
/*
RAM : ORIGIN = 0x0, LENGTH = 655360
ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
*/
}
SECTIONS
{
.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
{
KEEP(*(.exvectors))
} > ROM
.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
{
KEEP(*(.fvectors))
} > ROM
/* RSK-RX65N-1MB */
.text 0xFFF00000: AT(0xFFF00000)
/* RSK-RX65N-2MB | GR-ROSE */
/*
.text 0xFFE00000: AT(0xFFE00000)
*/
{
*(.text)
. = ALIGN(4);
*(.text.*)
. = ALIGN(4);
*(P)
etext = .;
} > ROM
.rvectors :
{
_rvectors_start = .;
KEEP(*(.rvectors))
_rvectors_end = .;
} > ROM
.init :
{
KEEP(*(.init))
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
__init_array_start = (. + 3) & ~ 3;
KEEP(*(.init_array))
KEEP(*(SORT(.init_array.*)))
__init_array_end = .;
__fini_array_start = .;
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
__fini_array_end = .;
} > ROM
.fini :
{
KEEP(*(.fini))
} > ROM
.got :
{
*(.got)
*(.got.plt)
} > ROM
.rodata :
{
*(.rodata)
*(.rodata.*)
*(C_1)
*(C_2)
*(C)
_erodata = .;
} > ROM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > ROM
.eh_frame :
{
*(.eh_frame)
} > ROM
.jcr :
{
*(.jcr)
} > ROM
.tors :
{
__CTOR_LIST__ = .;
. = ALIGN(2);
___ctors = .;
*(.ctors)
___ctors_end = .;
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___dtors = .;
*(.dtors)
___dtors_end = .;
__DTOR_END__ = .;
. = ALIGN(2);
_mdata = .;
} > ROM
.ustack 0x400: AT(0x200)
{
_ustack = .;
} > RAM
.istack 0x200: AT(0x200)
{
_istack = .;
} > RAM
.data 0x404: AT(_mdata)
{
_data = .;
*(.data)
*(.data.*)
*(D)
*(D_1)
*(D_2)
_edata = .;
} > RAM
.gcc_exc :
{
*(.gcc_exc)
} > RAM
.bss :
{
_bss = .;
*(.bss)
*(.bss.**)
*(COMMON)
*(B)
*(B_1)
*(B_2)
_ebss = .;
_end = .;
} > RAM
.ofs1 0xFE7F5D40: AT(0xFE7F5D00)
{
KEEP(*(.ofs1))
} > OFS
.ofs2 0xFE7F5D48: AT(0xFE7F5D10)
{
KEEP(*(.ofs2))
} > OFS
.ofs3 0xFE7F5D50: AT(0xFE7F5D40)
{
KEEP(*(.ofs3))
} > OFS
.ofs4 0xFE7F5D10: AT(0xFE7F5D48)
{
KEEP(*(.ofs4))
} > OFS
.ofs5 0xFE7F5D10: AT(0xFE7F5D50)
{
KEEP(*(.ofs5))
} > OFS
.ofs6 0xFE7F5D10: AT(0xFE7F5D64)
{
KEEP(*(.ofs6))
} > OFS
.ofs7 0xFE7F5D10: AT(0xFE7F5D70)
{
KEEP(*(.ofs7))
} > OFS
}

81
boards/renesas/rx65n/rx65n-rsk1mb/src/Makefile Normal file
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############################################################################
# configs/rx65n/src/Makefile
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched
CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
CSRCS = rx65n_main.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
OBJS = $(AOBJS) $(COBJS)
CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src
all: libboard$(LIBEXT)
$(AOBJS): %$(OBJEXT): %$(ASMEXT)
$(call ASSEMBLE, $<, $@)
$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
libboard$(LIBEXT): $(OBJS)
$(call ARCHIVE, $@, $(OBJS))
.depend: Makefile $(SRCS)
$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) touch $@
depend: .depend
clean:
$(call DELFILE, libboard$(LIBEXT))
$(call CLEAN)
distclean: clean
$(call DELFILE, Make.dep)
$(call DELFILE, .depend)
ifneq ($(BOARD_CONTEXT),y)
context:
endif
-include Make.dep

126
boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_main.c Normal file
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/****************************************************************************
* configs/rx65n-grrose/src/rx65n.main.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
*Included files
***************************************************************************/
#include "rx65n_macrodriver.h"
#include "arch/board/board.h"
#include "rx65n_definitions.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled1_on
*
* Description:
* Turns on LED 0
*
****************************************************************************/
void board_autoled1_on(int led)
{
LED0 = LED_ON;
}
/****************************************************************************
* Name: board_autoled2_on
*
* Description:
* Turns on LED 1
*
****************************************************************************/
void board_autoled2_on(int led)
{
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled_on
*
* Description:
* Turns on LED 0 & LED 1
*
****************************************************************************/
void board_autoled_on(int led)
{
LED0 = LED_ON;
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled1_off
*
* Description:
* Turns off LED 0
*
****************************************************************************/
void board_autoled1_off(int led)
{
LED0 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled2_off
*
* Description:
* Turns off LED 1
*
****************************************************************************/
void board_autoled2_off(int led)
{
LED1 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled_off
*
* Description:
* Turns off LED 0 & LED 1
*
****************************************************************************/
void board_autoled_off(int led)
{
LED0 = LED_OFF;
LED1 = LED_OFF;
}

7
boards/renesas/rx65n/rx65n-rsk2mb/Kconfig Normal file
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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_RX65N_RSK2MB
endif

212
boards/renesas/rx65n/rx65n-rsk2mb/README.txt Normal file
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README
======
This README file discusses the port of NuttX to the RX65N RSK2MB board. This board features the RX65N (R5F565NEHDFC 176pin)
Contents
========
- Board Features
- Status/Open Issues
- Serial Console
- LEDs
- Networking
- Debugging
Board Features
==============
- Mounted devices: RX65N (R5F565NEDDFC: No Encrypt Function, Code Flash 2MB, Pin Count 176-pin),
or RX65N (R5F565NEHDFC: Supported Encrypt Function, Code Flash 2MB, Pin Count 176-pin)
- Mounts TFT Display. Graphic LCD controller can be evaluated
- 1 channel Ethernet can be evaluated
- RX65N builds in Trusted Secure IP. AES encryption function and robust key management can be evaluated (*)
- Mounts SD slot. If an optional Wireless LAN expansion board package for RSK (RTK0ZZZZZZP00000BR#WS) is used,
Wireless LAN can evaluated
- 1 channel USB Function and 1 channel USB Host can be evaluated
- In addition, CAN, RSPI, QSPI, etc. can be evaluated
See the RX65N RSK2MB website for further information about this board:
- https://www.renesas.com/br/en/products/software-tools/boards-and-kits/starter-kits/renesas-starter-kitplus-for-rx65n-2mb.html
Status/Open Issues
==================
Ethernet
---------
1.Observed instability in Link Management, due to difference in hardware design.(No Seperate Interrupt line for PHY)
2.Currently tested only ping and udpblaster application.
3. Executed long run ping and udpblaster stress test for 12 hrs. Code is able to execute for 12hrs without any breakage.
Serial Console
==============
RX65N RSK2MB supports 12 serial ports (SCI0 - SCI12), however only 1 port can be tested(SCI8, which is the serial console). Only SCI8 port can be tested which is connected to USB Serial port.
Serial ports SCI1, SCI2, SCI9-SCI12, cannot be tested because they are multiplexed to other Rx65N controller interfaces.
Following SCI ports are configured w.r.t RX65N pin configuration
SCI1 Pin Configuration :
-----------
RX65N RSK2MB
Function
-----------
PF2 RXD1
PF1 TXD1
------------
SCI2 Pin Configuration :
-----------
RX65N RSK2MB
Function
-----------
P52 RXD2
P50 TXD2
------------
SCI8 Pin Configuration :
-----------
RX65N RSK2MB
Function
-----------
PJ1 RXD8
PJ2 TXD8
------------
Serial Connection Configuration
-------------------------------
1. RSK2MB board needs to be connected to PC, using USB cable(One end of which is connected to PC, other end
connected to USB serial port on H/W board).
2. RSK USB Serial Driver needs to be downloaded on PC side.
3. Configure Teraterm to 115200 baud.
LEDs
====
The RX65N RSK2MB board has 2 Power LED's(PowerLED5 LED_G, PowerLED3 LED_G) and 4 user LED's (LED_G, LED_O, LED_R, LED_R).
If enabled 4 User LED's are simply turned on when the board boots
successfully, and is blinking on panic / assertion failed.
Networking
==========
Ethernet Connections
--------------------
------ ---------
RX65N
RSK2MB Ethernet
Pin Function
------ ---------
PC4 ET0_TX_CLK
P76 ET0_RX_CLK
P80 ET0_TX_EN
PC6 ET0_ETXD3
PC5 ET0_ETXD2
P82 ET0_ETXD1
P81 ET0_ETXD0
PC3 ET0_TX_ER
PC2 ET0_RX_DV
PC0 ET0_ERXD3
PC1 ET0_ERXD2
P74 ET0_ERXD1
P75 ET0_ERXD0
P77 ET0_RX_ER
P83 ET0_CRS
PC7 ET0_COL
P72 ET0_MDC
P71 ET0_MDIO
P54 ET0_LINKSTA
------ ---------
NuttX Configurations
--------------------
The following configurations, need to be enabled for network.
CONFIG_RX65N_EMAC=y : Enable the EMAC Peripheral for RX65N
CONFIG_RX65N_EMAC0=y : Enable the EMAC Peripheral for RX65N
CONFIG_RX65N_EMAC0_PHYSR=30 : Address of PHY status register
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18 : Needed for PHY CHIP
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08 : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14 : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04 : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y : " " " " " "
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c : " " " " " "
CONFIG_RX65N_EMAC0_RMII=y
CONFIG_RX65N_EMAC0_PHYADDR=0 : PHY is at address 1
CONFIG_SCHED_WORKQUEUE=y : Work queue support is needed
CONFIG_SCHED_HPWORK=y : High Priority Work queue support
CONFIG_SCHED_LPWORK=y : Low Priority Work queue support
Using the network with NSH
--------------------------
The IP address is configured using DHCP, using the below mentioned configurations :
CONFIG_NETUTILS_DHCPC=y
CONFIG_NETUTILS_DHCPD=y
CONFIG_NSH_DHCPC=y
CONFIG_NETINIT_DHCPC=y
nsh> ifconfig
eth0 HWaddr 00:e0:de:ad:be:ef at UP
IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0
You can use ping to test for connectivity to the host (Careful,
Window firewalls usually block ping-related ICMP traffic). On the
target side, you can:
nsh> ping 10.75.24.250
PING 10.75.24.250 56 bytes of data
56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms
56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms
10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
On the host side, you should also be able to ping the RX65N-RSK2MB:
$ ping 10.75.24.53
Configure UDP blaster application as mentioned below :
CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801 (10.75.24.1) ------> Gateway IP
CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
Debugging
==========
1. NuttX needs to be compiled in Cygwin environment on Windows.
The following Configuration needs to be set, in order to do source level debugging.
CONFIG_DEBUG_SYMBOLS = y (Set this option, using menuconfig only, DO NOT Enable this as default configuration).
2. Download & Install Renesas e2studio IDE
3. Load the project(NuttX built on Cygwin) as Makefile project with existing code
4. Right click on the project, and select Debug Configurations
5. The binary(NuttX) needs to be loaded using E1/E2 Emulator
6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used)
7. Select Connection type as JTAG
8. Load and run the binary
Flashing NuttX
===============
Alternativly, NuttX binary can be flashed using Renesas flash programmer tool without using e2 studio/Cygwin
Below are the steps mentioned to flash NuttX binary using Renesas flash programmer tool(RFP).
1.In order to flash using Renesas flash programmer tool, nuttx.mot file should be generated.
2. Add the following lines in tools/Makefile.unix file :
ifeq ($(CONFIG_MOTOROLA_SREC),y)
@echo "CP: $(NUTTXNAME).mot"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns $(NUTTXNAME).mot
endif
3. Add CONFIG_MOTOROLA_SREC=y in defconfig file or choose make menucofig->Build Setup-> Binary Output Format->
Select Motorola SREC format.
4. Download Renesas flash programmer tool from https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads
5. Refer to the user manual document, for steps to flash NuttX binary using RFP tool.

91
boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig Normal file
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CONFIG_ARCH_BOARD_RX65N_RSK2MB=y
CONFIG_ARCH_BOARD="rx65n"
CONFIG_ARCH_CHIP_R5F565NEHDFC=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
CONFIG_ARCH_CHIP="rx65n"
CONFIG_BOARD_LOOPSPERMSEC=15001
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_ETH0_PHY_DP83620=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=655360
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_RX65N_SCI2=y
CONFIG_SCI8_SERIALDRIVER=y
CONFIG_SCI8_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI8=y
CONFIG_RX65N_EMAC=y
CONFIG_RX65N_EMAC0=y
CONFIG_RX65N_EMAC0_PHYSR=30
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x4
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x0
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x6
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x2
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x6
CONFIG_RX65N_EMAC0_MII=y
CONFIG_RX65N_EMAC0_PHYADDR=30
CONFIG_SCHED_WORKQUEUE=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SYSTEM_PING=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_FS_PROCFS=y
CONFIG_FS_PROCFS_REGISTER=y
CONFIG_NET_ETH_PKTSIZE = 590
CONFIG_RX65N_CMTW0=y
CONFIG_RX65N_PERIB=y
CONFIG_NETUTILS_DHCPC=y
CONFIG_NETUTILS_DHCPD=y
CONFIG_NSH_DHCPC=y
CONFIG_NETINIT_DHCPC=y
CONFIG_SYSTEM_NSH_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER=y
CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y

54
boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig Normal file
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_RX65N_RSK2MB=y
CONFIG_ARCH_BOARD="rx65n"
CONFIG_ARCH_CHIP_R5F565NEHDFC=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
#CONFIG_BOARD_LOOPSPERMSEC=572
#CONFIG_DISABLE_MOUNTPOINT=y
#CONFIG_DISABLE_MQUEUE=y
#CONFIG_DISABLE_POLL=y
#CONFIG_DISABLE_POSIX_TIMERS=y
#CONFIG_DISABLE_PTHREAD=y
#CONFIG_DISABLE_SIGNALS=y
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
#CONFIG_NSH_CONSOLE_LOGIN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=655360
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
#CONFIG_SCI0_SERIALDRIVER=y
#CONFIG_SCI0_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI0=y
#CONFIG_SCI1_SERIALDRIVER=y
#CONFIG_SCI1_SERIAL_CONSOLE=y
#CONFIG_RX65N_SCI1=y
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI2=y
CONFIG_SCI8_SERIALDRIVER=y
#CONFIG_SCI8_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI8=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024

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boards/renesas/rx65n/rx65n-rsk2mb/include/board.h Normal file
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/***************************************************************************
* configs/rx65n/include/board.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _CONFIGS_RX65N_BOARD_H
#define _CONFIGS_RX65N_BOARD_H
/***************************************************************************
* Included Files
***************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Clocking ****************************************************************/
#define RX_CLK_1MHz (1000UL * 1000UL)
#define RX_FCLK ( 60 * RX_CLK_1MHz)
#define RX_ICLK (120 * RX_CLK_1MHz)
#define RX_PCLKA (120 * RX_CLK_1MHz)
#define RX_PCLKB ( 60 * RX_CLK_1MHz)
#define RX_PCLKC ( 60 * RX_CLK_1MHz)
#define RX_PCLKD ( 60 * RX_CLK_1MHz)
#define RX_BCK (120 * RX_CLK_1MHz)
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define RX_RESONATOR ( 12 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#else
#error "Please definition RX_RESONATOR in board.h"
#endif
/* LED definitions */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define LED0 (PORT7.PODR.BIT.B3)
#define LED1 (PORTG.PODR.BIT.B7)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \
PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \
PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \
PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \
PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define LED0 (PORTA.PODR.BIT.BT0)
#define LED1 (PORTA.PODR.BIT.B1)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \
PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \
PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \
PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \
PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \
}
#else
#errror "LEDs are not defined."
#endif
#define LED_STARTED 1 /* ON OFF NC NC */
#define LED_HEAPALLOCATE 0 /* NC NC NC NC */
#define LED_IRQSENABLED 0 /* NC NC NC NC */
#define LED_STACKCREATED 2 /* ON ON NC NC */
#define LED_INIRQ 0 /* NC NC NC NC */
#define LED_SIGNAL 0 /* NC NC NC NC */
#define LED_ASSERTION 0 /* NC NC NC NC */
#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */
/* Button definitions */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* _CONFIGS_RX65N_BOARD_H */

123
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##############################################################################
# configs/rx65n-rsk2mb/scripts/Make.defs
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
##############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ifeq ($(CONFIG_HOST_WINDOWS),y)
WINTOOL=y
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}"
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
else
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
endif
CROSSDEV = rx-elf-
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
AS = $(CROSSDEV)as
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
$(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDMODULEFLAGS = -r -e module_initialize
ifeq ($(WINTOOL),y)
LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
else
LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
ASMEXT = .asm
OBJEXT = .o
LIBEXT = .a
EXEEXT =
#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

168
boards/renesas/rx65n/rx65n-rsk2mb/scripts/linker_script.ld Normal file
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MEMORY
{
/* RSK-RX65N-1MB */
/*
RAM : ORIGIN = 0x0, LENGTH = 262144
ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
*/
/* RSK-RX65N-2MB | GR-ROSE */
RAM : ORIGIN = 0x0, LENGTH = 262144
RAMHI : ORIGIN = 0x800000, LENGTH = 393216
ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
}
SECTIONS
{
.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
{
KEEP(*(.exvectors))
} > ROM
.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
{
KEEP(*(.fvectors))
} > ROM
/* RSK-RX65N-1MB */
/*
.text 0xFFF00000: AT(0xFFF00000)
*/
/* RSK-RX65N-2MB | GR-ROSE */
.text 0xFFE00000: AT(0xFFE00000)
{
*(.text)
. = ALIGN(4);
*(.text.*)
. = ALIGN(4);
*(P)
etext = .;
} > ROM
.rvectors :
{
_rvectors_start = .;
KEEP(*(.rvectors))
_rvectors_end = .;
} > ROM
.init :
{
KEEP(*(.init))
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
__init_array_start = (. + 3) & ~ 3;
KEEP(*(.init_array))
KEEP(*(SORT(.init_array.*)))
__init_array_end = .;
__fini_array_start = .;
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
__fini_array_end = .;
} > ROM
.fini :
{
KEEP(*(.fini))
} > ROM
.got :
{
*(.got)
*(.got.plt)
} > ROM
.rodata :
{
*(.rodata)
*(.rodata.*)
*(C_1)
*(C_2)
*(C)
_erodata = .;
} > ROM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > ROM
.eh_frame :
{
*(.eh_frame)
} > ROM
.jcr :
{
*(.jcr)
} > ROM
.tors :
{
__CTOR_LIST__ = .;
. = ALIGN(2);
___ctors = .;
*(.ctors)
___ctors_end = .;
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___dtors = .;
*(.dtors)
___dtors_end = .;
__DTOR_END__ = .;
. = ALIGN(2);
_mdata = .;
} > ROM
.ustack 0x400: AT(0x200)
{
_ustack = .;
} > RAM
.istack 0x200: AT(0x200)
{
_istack = .;
} > RAM
.data 0x404: AT(_mdata)
{
_data = .;
*(.data)
*(.data.*)
*(D)
*(D_1)
*(D_2)
_edata = .;
} > RAM
.gcc_exc :
{
*(.gcc_exc)
} > RAM
.bss :
{
_bss = .;
*(.bss)
*(.bss.**)
*(COMMON)
*(B)
*(B_1)
*(B_2)
_ebss = .;
_end = .;
} > RAM
.ofs1 0xFE7F5D40: AT(0xFE7F5D00)
{
KEEP(*(.ofs1))
} > OFS
.ofs2 0xFE7F5D48: AT(0xFE7F5D10)
{
KEEP(*(.ofs2))
} > OFS
.ofs3 0xFE7F5D50: AT(0xFE7F5D40)
{
KEEP(*(.ofs3))
} > OFS
.ofs4 0xFE7F5D10: AT(0xFE7F5D48)
{
KEEP(*(.ofs4))
} > OFS
.ofs5 0xFE7F5D10: AT(0xFE7F5D50)
{
KEEP(*(.ofs5))
} > OFS
.ofs6 0xFE7F5D10: AT(0xFE7F5D64)
{
KEEP(*(.ofs6))
} > OFS
.ofs7 0xFE7F5D10: AT(0xFE7F5D70)
{
KEEP(*(.ofs7))
} > OFS
}

81
boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile Normal file
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############################################################################
# configs/rx65n-rsk2mb/src/Makefile
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched
CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
CSRCS = rx65n_main.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
OBJS = $(AOBJS) $(COBJS)
CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src
all: libboard$(LIBEXT)
$(AOBJS): %$(OBJEXT): %$(ASMEXT)
$(call ASSEMBLE, $<, $@)
$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
libboard$(LIBEXT): $(OBJS)
$(call ARCHIVE, $@, $(OBJS))
.depend: Makefile $(SRCS)
$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) touch $@
depend: .depend
clean:
$(call DELFILE, libboard$(LIBEXT))
$(call CLEAN)
distclean: clean
$(call DELFILE, Make.dep)
$(call DELFILE, .depend)
ifneq ($(BOARD_CONTEXT),y)
context:
endif
-include Make.dep

126
boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_main.c Normal file
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/****************************************************************************
* configs/rx65n-grrose/src/rx65n.main.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
*Included files
***************************************************************************/
#include "rx65n_macrodriver.h"
#include "arch/board/board.h"
#include "rx65n_definitions.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled1_on
*
* Description:
* Turns on LED 0
*
****************************************************************************/
void board_autoled1_on(int led)
{
LED0 = LED_ON;
}
/****************************************************************************
* Name: board_autoled2_on
*
* Description:
* Turns on LED 1
*
****************************************************************************/
void board_autoled2_on(int led)
{
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled_on
*
* Description:
* Turns on LED 0 & LED 1
*
****************************************************************************/
void board_autoled_on(int led)
{
LED0 = LED_ON;
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled1_off
*
* Description:
* Turns off LED 0
*
****************************************************************************/
void board_autoled1_off(int led)
{
LED0 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled2_off
*
* Description:
* Turns off LED 1
*
****************************************************************************/
void board_autoled2_off(int led)
{
LED1 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled_off
*
* Description:
* Turns off LED 0 & LED 1
*
****************************************************************************/
void board_autoled_off(int led)
{
LED0 = LED_OFF;
LED1 = LED_OFF;
}

7
boards/renesas/rx65n/rx65n/Kconfig Normal file
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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_RX65N
endif

36
boards/renesas/rx65n/rx65n/configs/nsh/defconfig Normal file
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CONFIG_ARCH_BOARD_RX65N=y
CONFIG_ARCH_BOARD="rx65n"
CONFIG_ARCH_CHIP_R5F565NEDDFC=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=262144
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI2=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024

150
boards/renesas/rx65n/rx65n/include/board.h Normal file
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/***************************************************************************
* configs/rx65n/include/board.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _CONFIGS_RX65N_BOARD_H
#define _CONFIGS_RX65N_BOARD_H
/***************************************************************************
* Included Files
***************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Clocking ****************************************************************/
#define RX_CLK_1MHz (1000UL * 1000UL)
#define RX_FCLK ( 60 * RX_CLK_1MHz)
#define RX_ICLK (120 * RX_CLK_1MHz)
#define RX_PCLKA (120 * RX_CLK_1MHz)
#define RX_PCLKB ( 60 * RX_CLK_1MHz)
#define RX_PCLKC ( 60 * RX_CLK_1MHz)
#define RX_PCLKD ( 60 * RX_CLK_1MHz)
#define RX_BCK (120 * RX_CLK_1MHz)
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define RX_RESONATOR ( 12 * RX_CLK_1MHz)
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define RX_RESONATOR ( 24 * RX_CLK_1MHz)
#else
#error "Please definition RX_RESONATOR in board.h"
#endif
/* LED definitions **********************************************************/
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define LED0 (PORT7.PODR.BIT.B3)
#define LED1 (PORTG.PODR.BIT.B7)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \
PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \
PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \
PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \
PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \
PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \
PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \
PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \
}
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define LED0 (PORTA.PODR.BIT.BT0)
#define LED1 (PORTA.PODR.BIT.B1)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \
PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \
PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \
PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \
PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \
}
#else
#errror "LEDs are not defined."
#endif
#define LED_STARTED 1 /* ON OFF NC NC */
#define LED_HEAPALLOCATE 0 /* NC NC NC NC */
#define LED_IRQSENABLED 0 /* NC NC NC NC */
#define LED_STACKCREATED 2 /* ON ON NC NC */
#define LED_INIRQ 0 /* NC NC NC NC */
#define LED_SIGNAL 0 /* NC NC NC NC */
#define LED_ASSERTION 0 /* NC NC NC NC */
#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */
/* Button definitions *******************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* _CONFIGS_RX65N_BOARD_H */

118
boards/renesas/rx65n/rx65n/scripts/Make.defs Normal file
View file

@ -0,0 +1,118 @@
##############################################################################
# configs/rx65n/scripts/Make.defs
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
##############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ifeq ($(CONFIG_HOST_WINDOWS),y)
WINTOOL=y
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}"
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
else
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld
ARCHPICFLAGS = -fpic
ARCHCFLAGS = -std=c99 -fno-builtin
#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data
ARCHCPUFLAGS = -mcpu=rx64m
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
endif
CROSSDEV = rx-elf-
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
AS = $(CROSSDEV)as
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
$(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDMODULEFLAGS = -r -e module_initialize
ifeq ($(WINTOOL),y)
LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
else
LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
ASMEXT = .asm
OBJEXT = .o
LIBEXT = .a
EXEEXT =
#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

176
boards/renesas/rx65n/rx65n/scripts/linker_script.ld Normal file
View file

@ -0,0 +1,176 @@
MEMORY
{
/* RSK-RX65N-1MB */
/*
RAM : ORIGIN = 0x0, LENGTH = 262144
ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
*/
/* RSK-RX65N-2MB | GR-ROSE */
RAM : ORIGIN = 0x0, LENGTH = 262144
RAMHI : ORIGIN = 0x800000, LENGTH = 393216
ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
}
SECTIONS
{
.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
{
_exvectors_start = .;
KEEP(*(.exvectors))
_exvectors_end = .;
} > ROM
.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
{
KEEP(*(.fvectors))
} > ROM
/* RSK-RX65N-1MB */
.text 0xFFF00000: AT(0xFFF00000)
/* RSK-RX65N-2MB | GR-ROSE */
/*.text 0xFFE00000: AT(0xFFE00000) */
{
*(.text)
. = ALIGN(4);
*(.text.*)
. = ALIGN(4);
*(P)
etext = .;
} > ROM
.rvectors :
{
_rvectors_start = .;
KEEP(*(.rvectors))
_rvectors_end = .;
} > ROM
/*.exvectors :
{
_exvectors_start = .;
KEEP(*(.exvectors))
_exvectors_end = .;
} > ROM */
.init :
{
KEEP(*(.init))
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
__init_array_start = (. + 3) & ~ 3;
KEEP(*(.init_array))
KEEP(*(SORT(.init_array.*)))
__init_array_end = .;
__fini_array_start = .;
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
__fini_array_end = .;
} > ROM
.fini :
{
KEEP(*(.fini))
} > ROM
.got :
{
*(.got)
*(.got.plt)
} > ROM
.rodata :
{
*(.rodata)
*(.rodata.*)
*(C_1)
*(C_2)
*(C)
_erodata = .;
} > ROM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > ROM
.eh_frame :
{
*(.eh_frame)
} > ROM
.jcr :
{
*(.jcr)
} > ROM
.tors :
{
__CTOR_LIST__ = .;
. = ALIGN(2);
___ctors = .;
*(.ctors)
___ctors_end = .;
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___dtors = .;
*(.dtors)
___dtors_end = .;
__DTOR_END__ = .;
. = ALIGN(2);
_mdata = .;
} > ROM
.ustack 0x400: AT(0x200)
{
_ustack = .;
} > RAM
.istack 0x200: AT(0x200)
{
_istack = .;
} > RAM
.data 0x404: AT(_mdata)
{
_data = .;
*(.data)
*(.data.*)
*(D)
*(D_1)
*(D_2)
_edata = .;
} > RAM
.gcc_exc :
{
*(.gcc_exc)
} > RAM
.bss :
{
_bss = .;
*(.bss)
*(.bss.**)
*(COMMON)
*(B)
*(B_1)
*(B_2)
_ebss = .;
_end = .;
} >RAM
.ofs1 0xFE7F5D40: AT(0xFE7F5D00)
{
KEEP(*(.ofs1))
} > OFS
.ofs2 0xFE7F5D48: AT(0xFE7F5D10)
{
KEEP(*(.ofs2))
} > OFS
.ofs3 0xFE7F5D50: AT(0xFE7F5D40)
{
KEEP(*(.ofs3))
} > OFS
.ofs4 0xFE7F5D10: AT(0xFE7F5D48)
{
KEEP(*(.ofs4))
} > OFS
.ofs5 0xFE7F5D10: AT(0xFE7F5D50)
{
KEEP(*(.ofs5))
} > OFS
.ofs6 0xFE7F5D10: AT(0xFE7F5D64)
{
KEEP(*(.ofs6))
} > OFS
.ofs7 0xFE7F5D10: AT(0xFE7F5D70)
{
KEEP(*(.ofs7))
} > OFS
}

82
boards/renesas/rx65n/rx65n/src/Makefile Normal file
View file

@ -0,0 +1,82 @@
############################################################################
# configs/rx65n/src/Makefile
#
# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
# Author: Anjana <anjana@tataelxsi.co.in>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched
CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
CSRCS = rx65n_main.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
OBJS = $(AOBJS) $(COBJS)
CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src
CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/include
all: libboard$(LIBEXT)
$(AOBJS): %$(OBJEXT): %$(ASMEXT)
$(call ASSEMBLE, $<, $@)
$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
libboard$(LIBEXT): $(OBJS)
$(call ARCHIVE, $@, $(OBJS))
.depend: Makefile $(SRCS)
$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) touch $@
depend: .depend
clean:
$(call DELFILE, libboard$(LIBEXT))
$(call CLEAN)
distclean: clean
$(call DELFILE, Make.dep)
$(call DELFILE, .depend)
ifneq ($(BOARD_CONTEXT),y)
context:
endif
-include Make.dep

126
boards/renesas/rx65n/rx65n/src/rx65n_main.c Normal file
View file

@ -0,0 +1,126 @@
/****************************************************************************
* configs/rx65n-grrose/src/rx65n.main.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
*Included files
***************************************************************************/
#include "rx65n_macrodriver.h"
#include "arch/board/board.h"
#include "rx65n_definitions.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled1_on
*
* Description:
* Turns on LED 0
*
****************************************************************************/
void board_autoled1_on(int led)
{
LED0 = LED_ON;
}
/****************************************************************************
* Name: board_autoled2_on
*
* Description:
* Turns on LED 1
*
****************************************************************************/
void board_autoled2_on(int led)
{
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled_on
*
* Description:
* Turns on LED 0 & LED 1
*
****************************************************************************/
void board_autoled_on(int led)
{
LED0 = LED_ON;
LED1 = LED_ON;
}
/****************************************************************************
* Name: board_autoled1_off
*
* Description:
* Turns off LED 0
*
****************************************************************************/
void board_autoled1_off(int led)
{
LED0 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled2_off
*
* Description:
* Turns off LED 1
*
****************************************************************************/
void board_autoled2_off(int led)
{
LED1 = LED_OFF;
}
/****************************************************************************
* Name: board_autoled_off
*
* Description:
* Turns off LED 0 & LED 1
*
****************************************************************************/
void board_autoled_off(int led)
{
LED0 = LED_OFF;
LED1 = LED_OFF;
}

55
drivers/serial/Kconfig
View file

@ -406,6 +406,61 @@ config SCI1_SERIAL_CONSOLE
depends on SCI1_SERIALDRIVER
select SERIAL_CONSOLE
config SCI2_SERIAL_CONSOLE
bool "SCI2"
depends on SCI2_SERIALDRIVER
select SERIAL_CONSOLE
config SCI3_SERIAL_CONSOLE
bool "SCI3"
depends on SCI3_SERIALDRIVER
select SERIAL_CONSOLE
config SCI4_SERIAL_CONSOLE
bool "SCI4"
depends on SCI4_SERIALDRIVER
select SERIAL_CONSOLE
config SCI5_SERIAL_CONSOLE
bool "SCI5"
depends on SCI5_SERIALDRIVER
select SERIAL_CONSOLE
config SCI6_SERIAL_CONSOLE
bool "SCI6"
depends on SCI6_SERIALDRIVER
select SERIAL_CONSOLE
config SCI7_SERIAL_CONSOLE
bool "SCI7"
depends on SCI7_SERIALDRIVER
select SERIAL_CONSOLE
config SCI8_SERIAL_CONSOLE
bool "SCI8"
depends on SCI8_SERIALDRIVER
select SERIAL_CONSOLE
config SCI9_SERIAL_CONSOLE
bool "SCI9"
depends on SCI9_SERIALDRIVER
select SERIAL_CONSOLE
config SCI10_SERIAL_CONSOLE
bool "SCI10"
depends on SCI10_SERIALDRIVER
select SERIAL_CONSOLE
config SCI11_SERIAL_CONSOLE
bool "SCI11"
depends on SCI11_SERIALDRIVER
select SERIAL_CONSOLE
config SCI12_SERIAL_CONSOLE
bool "SCI12"
depends on SCI12_SERIALDRIVER
select SERIAL_CONSOLE
config OTHER_SERIAL_CONSOLE
bool "Other serial console"
select SERIAL_CONSOLE

539
drivers/serial/Kconfig-sci
View file

@ -13,6 +13,61 @@ config SCI1_SERIALDRIVER
default n
select MCU_SERIAL
config SCI2_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI3_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI4_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI5_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI6_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI7_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI8_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI9_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI10_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI11_SERIALDRIVER
bool
default n
select MCU_SERIAL
config SCI12_SERIALDRIVER
bool
default n
select MCU_SERIAL
menu "SCI0 Configuration"
depends on SCI0_SERIALDRIVER
@ -100,3 +155,487 @@ config SCI1_2STOP
1=Two stop bits
endmenu # SCI1 Configuration
menu "SCI2 Configuration"
depends on SCI2_SERIALDRIVER
config SCI2_RXBUFSIZE
int "SCI2 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI2_TXBUFSIZE
int "SCI2 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI2_BAUD
int "SCI2 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI2_BITS
int "SCI2 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI2_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI2_2STOP
int "SCI2 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI2 Configuration
menu "SCI3 Configuration"
depends on SCI3_SERIALDRIVER
config SCI3_RXBUFSIZE
int "SCI3 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI3_TXBUFSIZE
int "SCI3 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI3_BAUD
int "SCI3 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI3_BITS
int "SCI3 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI3_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI3_2STOP
int "SCI3 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI3 Configuration
menu "SCI4 Configuration"
depends on SCI4_SERIALDRIVER
config SCI4_RXBUFSIZE
int "SCI4 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI4_TXBUFSIZE
int "SCI4 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI4_BAUD
int "SCI4 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI4_BITS
int "SCI4 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI4_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI4_2STOP
int "SCI4 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI4 Configuration
menu "SCI5 Configuration"
depends on SCI5_SERIALDRIVER
config SCI5_RXBUFSIZE
int "SCI5 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI5_TXBUFSIZE
int "SCI5 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI5_BAUD
int "SCI5 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI5_BITS
int "SCI5 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI5_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI5_2STOP
int "SCI5 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI5 Configuration
menu "SCI6 Configuration"
depends on SCI6_SERIALDRIVER
config SCI6_RXBUFSIZE
int "SCI6 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI6_TXBUFSIZE
int "SCI6 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI6_BAUD
int "SCI6 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI6_BITS
int "SCI6 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI6_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI6_2STOP
int "SCI6 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI6 Configuration
menu "SCI7 Configuration"
depends on SCI7_SERIALDRIVER
config SCI7_RXBUFSIZE
int "SCI7 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI7_TXBUFSIZE
int "SCI7 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI7_BAUD
int "SCI7 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI7_BITS
int "SCI7 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI7_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI7_2STOP
int "SCI7 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI7 Configuration
menu "SCI8 Configuration"
depends on SCI8_SERIALDRIVER
config SCI8_RXBUFSIZE
int "SCI8 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI8_TXBUFSIZE
int "SCI8 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI8_BAUD
int "SCI8 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI8_BITS
int "SCI8 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI8_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI8_2STOP
int "SCI8 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI8 Configuration
menu "SCI9 Configuration"
depends on SCI9_SERIALDRIVER
config SCI9_RXBUFSIZE
int "SCI9 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI9_TXBUFSIZE
int "SCI9 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI9_BAUD
int "SCI9 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI9_BITS
int "SCI9 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI9_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI9_2STOP
int "SCI9 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI9 Configuration
menu "SCI10 Configuration"
depends on SCI10_SERIALDRIVER
config SCI10_RXBUFSIZE
int "SCI10 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI10_TXBUFSIZE
int "SCI10 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI10_BAUD
int "SCI10 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI10_BITS
int "SCI10 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI10_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI10_2STOP
int "SCI10 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI10 Configuration
menu "SCI11 Configuration"
depends on SCI11_SERIALDRIVER
config SCI11_RXBUFSIZE
int "SCI11 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI11_TXBUFSIZE
int "SCI11 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI11_BAUD
int "SCI11 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI11_BITS
int "SCI11 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI11_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI11_2STOP
int "SCI11 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI11 Configuration
menu "SCI12 Configuration"
depends on SCI12_SERIALDRIVER
config SCI12_RXBUFSIZE
int "SCI12 receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config SCI12_TXBUFSIZE
int "SCI12 transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config SCI12_BAUD
int "SCI12 BAUD rate"
default 115200
---help---
The configured BAUD of the SCI.
config SCI12_BITS
int "SCI12 character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config SCI12_PARITY
int "Parity setting"
default 0
range 0 2
---help---
0=no parity, 1=odd parity, 2=even parity
config SCI12_2STOP
int "SCI12 use 2 stop bits"
default 0
---help---
1=Two stop bits
endmenu # SCI12 Configuration

1
tools/configure.c
View file

@ -193,6 +193,7 @@ static const char *g_chipnames[] =
"moxart",
"nrf52",
"nuc1xx",
"rx65n"
"s32k1xx",
"sam34",
"sama5",

2
tools/configure.sh
View file

@ -145,7 +145,7 @@ fi
archs="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
chips="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450
lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52
nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx
pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811
ez80 z180 z8 z80"

2
tools/refresh.sh
View file

@ -121,7 +121,7 @@ ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
CHIPLIST="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450
lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52
nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx
pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811
ez80 z180 z8 z80"

2
tools/testbuild.sh
View file

@ -301,7 +301,7 @@ for line in $testlist; do
ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
CHIPLIST="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450
lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52
nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx
pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811
ez80 z180 z8 z80"