Commit graph

23169 commits

Author SHA1 Message Date
simbit18
e4705e7f62 Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
2024-12-12 02:18:23 +08:00
Jukka Laitinen
fd3f0b7dd9 arch/risc-v/src/mpfs/mpfs_corespi.c: Add support for multiple bit widths
The corespi fpga block supports just one frame length, which is defined when
the block is instantiated on the FPGA.

This adds support for emulating different frame lengths if they are multiples
of 8-bit. That is, with 8-bit corespi one can do 8,16 and 24-bit transfers.

This is implemented by simply writing several 8-bit frames for a single word
when needed.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-12-12 02:05:16 +08:00
Tero Salminen
186b11c941 mpfs_corespi: fix semaphore race condition
SPI TX_DONE interrupt can be received after a semaphore timeout,
but before interrupts are disabled. This will leave the semaphore
to the signaled state.

After a timeout the semaphore is always reset to non-signaled state
to fix this race condition.

Signed-off-by: Tero Salminen <tero.salminen@unikie.com>
2024-12-12 02:05:16 +08:00
chao an
4eeb6546ec esp/mcpwm: fix unpaired spin lock
N/A

Signed-off-by: chao an <anchao@lixiang.com>
2024-12-11 21:36:51 +08:00
Tiago Medicci Serrano
f3ec1bd60c xtensa/esp32s3: Update the reserved size for struct __lock
After https://github.com/apache/nuttx/pull/15075, the static
assertion at `nuttx/arch/xtensa/src/esp32s3/esp32s3_libc_stubs.c`
was being triggered when building any of the ESP32-S3's defconfigs.
This commit updates the reserved size to reflect the changes
introduced by the related PR.
2024-12-11 21:36:20 +08:00
Jouni Ukkonen
8a7f96e7f4 arch/arm64/imx9: Fix usdhc dma receive
Invalidate cache when dma transfer is ready

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-12-11 21:35:41 +08:00
Gao Feng
10a1d17a85 xtensa/esp32s3: add lock for async operation work
g_work as singleton can be changed by context switching,
but previous one async operation have not finished yet.
2024-12-10 22:01:43 +08:00
Gao Feng
1c7d81881c xtensa/esp32: encrypted MTD for partition offset
Non-encrypted mtd can not be used for encrypted device.

Even without SPI Flash encryption,
encrypted MTD also can be used to read no-encrypted data.
2024-12-10 18:15:47 +08:00
chao an
4a9a43771b arm/cxd56xx: Add g_ prefix to rtc spin lock
continue work of a68b00206b

| commit a68b00206b
| Author: hujun5 <hujun5@xiaomi.com>
| Date:   Mon Dec 9 20:48:09 2024 +0800
|
|     cxd56_rtc.c: use small lock in arch/arm/src/cxd56xx/cxd56_rtc.c
|
|     reason:
|     We hope to remove all instances of spin_lock_irqsave(NULL).
|
|     Signed-off-by: hujun5 <hujun5@xiaomi.com>

Signed-off-by: chao an <anchao@lixiang.com>
2024-12-10 16:25:02 +08:00
Kyle Wilson
9b99493e14 Initial STM32H5 SPI Commit
Used STM32H7 spi driver as a base. The register set is nearly identical. All registers are named the same with the same offset. There are some bits within the registers that are different but are not referenced in stm32_spi.c. Therfore this driver may just work as is. I did modify the clock source selection for each SPI peripheral, but not much else. Differences in the registers were applied in hardware/stm32h5xxx_spi.h.

Added functionality to SPI to configure the SPI RCC clock.

Added SPI info to Kconfig, updated stm32_spi.c to select and set the RCC clock, and other minor updates.

Updated Pin Map for SPI, added CFG1_BPASS support

Fixed redefinition of GPIO_SPI6_SCK_2

Added SPI_MAX_KER_CK definition.

This definition was needed because the H50 chips allow a kernel clock of 250 MHz. However the datasheets for all other chips (H52, H53, H56, H57) have a max of 125 MHz.

Changed SPI Clock Source Configuration

Moved setting of SPIx clock sources to stm32h5xx_rcc.c. STM32_SPIx_FREQUENCY and STM32_RCC_CCIPR3_SPIxSEL are now defined in board.h. Added error checking in stm32_spi.c to make sure STM32_SPIx_FREQUENCY and STM32_RCC_CCIPR3_SPIxSEL are actually defined.

Style updates

Removed SPI Clock selection from Kconfig

Update arch/arm/src/stm32h5/stm32_spi.h

Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>

Update arch/arm/src/stm32h5/Kconfig

Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>

Update arch/arm/src/stm32h5/stm32_spi.h

Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
2024-12-10 09:32:10 +08:00
Alan Carvalho de Assis
d6ab368f32 Fix small typo in rp2040_adc.c 2024-12-10 09:28:20 +08:00
Ville Juven
fd20684a7b mpfs_entrypoints.c: Add simple ACK mechanism for CPU boot
CPUs will acknowledge that they have booted, the primary CPU handling the
boot can then wait for others to complete their boot, before booting
itself.
2024-12-10 01:54:04 +08:00
hujun5
0aa99e223f litex_serial: use small lock in arch/risc-v/src/litex/litex_serial.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:52:58 +08:00
hujun5
f65a33be8c lc823450_dma: use small lock in arch/arm/src/lc823450/lc823450_dma.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:52:35 +08:00
hujun5
1e64d93a73 s32k3xx_serial: use small lock in arch/arm/src/s32k3xx/s32k3xx_serial.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:29:27 +08:00
hujun5
a68b00206b cxd56_rtc.c: use small lock in arch/arm/src/cxd56xx/cxd56_rtc.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-10 01:29:14 +08:00
simbit18
11f412b7af fix nxstyle
Removed extra spaces from .h and .c files
2024-12-10 01:29:00 +08:00
hujun5
1e47441775 max32660_rtc: use small lock in arch/arm/src/max326xx/max32660/max32660_rtc.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 23:17:22 +08:00
Eero Nurkkala
12c9fd9683 risc-v/mpfs: make cache clearing optional
L2 needs to be zeroed to make the ECC happy. However, if there's
more than one bootloader in the chain, the cache doesn't need to
be wiped every time. One time is enough. Thus, make this optional
so that it's initialized only when really needed.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-12-09 22:14:07 +08:00
Jukka Laitinen
23a0239795 arch/arm64/src/imx9/imx9_usdhc.c: Simplify eventwait logic and remove race condition
There is a race condition when timeout and completion interrupts occur at the same time.

Fix this and simplify the eventwait code.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-12-09 21:22:28 +08:00
hujun5
0e1b432dd0 armv7/8m: fix regresion from https://github.com/apache/nuttx/pull/14881
reason:
svc call may trigger hardfault

Background
    The origin of this issue is our desire to eliminate the function of storing
"regs" in g_current_regs and instead utilize (*running_task)->xcp.regs for storage.
The benefits of this approach include faster storage speed and
avoiding multiple accesses to g_current_regs during context switching,
thus ensuring that whether returning from an interrupt or an exception,
we consistently use this_task()->xcp.regs

Issue Encountered
    However, when storing registers, we must ensure that (running_task)->xcp.regs is invalid
so that it can be safely overwritten.
According to the existing logic, the only scenario where (running_task)->xcp.regs
is valid is during restore_context. We must accurately identify this scenario.
Initially, we used the condition (running_task)==NULL for this purpose, but we deemed
this approach unsatisfactory as it did not align well with the actual logic.
(running_task) should not be NULL. Consequently, we adopted other arch-specific methods for judgment,
but due to special logic in some arch, the judgment was not accurate, leading to this issue.

Solution:
    For armv6-m, we haven't found a more suitable solution, so we are sticking with (*running_task)==NULL.
    For armv7-m/armv8-m, by removing support for primask, we can achieve accurate judgment.

    PRIMASK is a design in armv6-m, that's why arm introduce BASEPRI from armv7-m.
It's wrong to provide this option for armv7-m/armv8-m arch.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 12:20:13 +08:00
hujun5
d20189bdfa armv6m: fix regresion from https://github.com/apache/nuttx/pull/14881
reason:
svc call may trigger hardfalt

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-09 12:20:13 +08:00
Eren Terzioglu
001a663b74 esp32[s2|s3]: Add nxdiag without esptool wrapper 2024-12-07 11:45:59 +08:00
Eren Terzioglu
bbb9ce114f esp32[c3|c6|h2]: Add nxdiag without esptool wrapper 2024-12-07 11:45:59 +08:00
Alin Jerpelea
d368c0cc04 arch/arm: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-06 22:31:35 +08:00
hujun5
1e49cb4828 armv7-a/armv7-r/armv8-r: percpu reg store this_task
This is continue work of https://github.com/apache/nuttx/pull/13726

We can utilize percpu storage to hold information about the
current running task. If we intend to implement this feature, we would
need to define two macros that help us manage this percpu information
effectively.

up_this_task: This macro is designed to read the contents of the percpu
register to retrieve information about the current
running task.This allows us to quickly access
task-specific data without having to disable interrupts,
access global variables and obtain the current cpu index.

up_update_task: This macro is responsible for updating the contents of
the percpu register.It is typically called during
initialization or when a context switch occurs to ensure
that the percpu register reflects the information of the
newly running task.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-06 09:27:33 +08:00
Alin Jerpelea
344968b8c2 arch/arm: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-06 09:25:23 +08:00
xuxin19
f2b4ab283f cmake(bugfix):fix CMake build break on MacOS
report by https://github.com/apache/nuttx/issues/14936

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-12-05 23:36:16 +08:00
Xiang Xiao
60fb917eda Remove FAR from 32/64bit arch
since these arch doesn't distinguish between near and far pointers

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-12-05 22:55:39 +08:00
hujun5
cbd07a86c9 s32k1xx_serial: arch/arm/src/s32k1xx/s32k1xx_serial.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-05 22:16:45 +08:00
buxiasen
617fee66ff Revert "arm/rp2040: use custom vectors to make smp_call work with exception_common"
This reverts commit 9464afe7c3.
2024-12-05 20:42:22 +08:00
buxiasen
108aaf8bbb Revert "arm/lc823450: use custom vectors to make smp_call work with exception_common"
This reverts commit c2cb58ff31.
2024-12-05 20:42:22 +08:00
buxiasen
9473cee85b Revert "arm/cxd56: use chip specific vectors to allow smpcall update regs"
This reverts commit 4a1afab88e.
2024-12-05 20:42:22 +08:00
buxiasen
af3c159cff arm-v6/7/8m: sigaction forward to pendsv
For exception directly, tcb->xcp.regs should not be used.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-12-05 20:42:22 +08:00
buxiasen
55822753be arm-v6/7/8m: sigaction should use running_task
Nested irq possible cause readytorun not match with regs

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-12-05 20:42:22 +08:00
chenxiaoyi
f313ee5715 xtensa: inline up_switch_context
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-05 20:32:45 +08:00
wangmingrong1
fe5ee0c6ac arm64/toolchain: Fix toolchain judgment after opening lto
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-12-05 13:23:13 +08:00
hujun5
3e3701b272 riscv: Some judgments are missing
This commit fixes the regression from https://github.com/apache/nuttx/pull/14984

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-05 00:07:38 +08:00
zhangyuan29
1dc1e65202 arch/xtensa: use arch atomic when enable iram heap
S32C1I instructions may target cached, cache-bypass,
and data RAM memory locations. S32C1I instructions
are not permitted to access memory addresses in data ROM,
instruction memory or the address region allocated to
the XLMI port. Attempts to direct the S32C1I at these
addresses will cause an exception.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2024-12-05 00:05:15 +08:00
hujun5
dabf589940 remove redundant judgments *running_task != NULL
reason:
In irq, g_running_tasks is always valid.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-04 22:50:08 +08:00
wangmingrong1
cc88063646 debug symbol level: Use config instead
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-12-04 22:36:45 +08:00
zhangyuan29
dcea1b90e7 arch_atomic: only support atomic_xx and atomic64_xx function
Modify the kernel to use only atomic_xx and atomic64_xx interfaces,
avoiding the use of sizeof or typeof to determine the type of
atomic operations, thereby simplifying the kernel's atomic
interface operations.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2024-12-04 14:03:14 +01:00
Masayuki Ishikawa
6e8375f97b arch: lc823450: Add missing license info to lc823450_symbols.ld
Summary:
- The file includes symbol information provided by ON Semiconductor.
- The license information is the same as lc823450_sdc.c

Impact:
- None

Testing:
- lc823450-xgevk:rndis (build only)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2024-12-04 12:04:38 +01:00
hujun5
79a1ebb9cd rp23xx: use small lock in arch/arm/src/rp23xx/rp23xx_usbdev.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-04 14:48:48 +08:00
hujun5
bc844509e2 addrenv: Ensure that the transmission parameter of addrenv_switch is not NULL
reason:
avoid obtaining this_task multiple times.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-04 14:20:12 +08:00
Tiago Medicci Serrano
5358f5b940 libm: Do not link the toolchain's libm unless explicitly selected
Fix CMake-based build system to include the toolchain's libm only
when `CONFIG_LIBM_TOOLCHAIN` is selected. Before this commit, if
the user selected `CONFIG_LIBM_NEWLIB`, for instance, the build
system would still link the toolchain's libm functions instead of
the ones provided by newlib.

PS: this commit applies the same changes previously introduced for
the other architectures.
2024-12-04 09:30:33 +08:00
Tiago Medicci Serrano
80dd961f23 libm: Do not link the toolchain's libm unless explicitly selected
Fix CMake-based build system to include the toolchain's libm only
when `CONFIG_LIBM_TOOLCHAIN` is selected. Before this commit, if
the user selected `CONFIG_LIBM_NEWLIB`, for instance, the build
system would still link the toolchain's libm functions instead of
the ones provided by newlib.
2024-12-04 02:06:17 +08:00
hujun5
d5fba177b1 cxd56xx: use small lock in arch/arm/src/cxd56xx/cxd56_nxaudio_src.c
reason:
We hope to remove all instances of spin_lock_irqsave(NULL).

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 23:51:47 +08:00
hujun5
4f3f9751c1 fix compile error
lcd/st7565.c:107:4: warning: #warning "Optimal setting of CONFIG_LCD_MAXCONTRAST is 255" [-Wcpp]
  107 | #  warning "Optimal setting of CONFIG_LCD_MAXCONTRAST is 255"
      |    ^~~~~~~
chip/lc823450_cpuindex.c:36: warning: "CORE_COREID" redefined
   36 | #define CORE_COREID (LC823450_CORE_BASE + 0x0)
      |
In file included from /home/hujun5/downloads1/vela_sim/nuttx/arch/arm/src/common/arm_internal.h:37,
                 from chip/lc823450_cpuindex.c:29:
/home/hujun5/downloads1/vela_sim/nuttx/arch/arm/src/chip/chip.h:48: note: this is the location of the previous definition
   48 | #define CORE_COREID         (LC823450_CORE_BASE + 0)
      |
chip/lc823450_cpuindex.c:37: warning: "CORE_COREID_ID" redefined
   37 | #define   CORE_COREID_ID  (0x1 << 0)
      |
/home/hujun5/downloads1/vela_sim/nuttx/arch/arm/src/chip/chip.h:49: note: this is the location of the previous definition
   49 | #define CORE_COREID_ID      (1 << 0)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 18:27:54 +08:00
hujun5
2b22ee03d6 arm: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 18:27:54 +08:00
hujun5
03af486d68 arm: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
   a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete.
Therefore, we need to rename up_set_current_regs to better reflect its actual meaning,
which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-03 18:27:54 +08:00
chao an
5cd3eed323 arm64/imx8: fix build break
Error: chip/imx8qm_lowputc.S:23:1: error: "/*" within comment [-Werror=comment]
   23 | /****************************************************************************
      |
Signed-off-by: chao an <anchao@lixiang.com>
2024-12-03 09:38:35 +08:00
Kyle Wilson
e1e1d534af Add STM32H5 FDCAN Hardware File
Adding the STM32H5 FDCAN Hardware definitions. The register set is identical to the STM32G4. No major changes other than changing G4 to H5 and removing ifdef requirement for STM32G4.

Fixed style issues
2024-12-03 08:33:31 +08:00
Kyle Wilson
d417e1525b First commit of STM32H5 SPI Hardware file.
This file is heavily based on the STM32H7 implementation. CFG1_BPASS and UDRCFG were the main differences.
2024-12-03 08:32:50 +08:00
hujun5
3a4b8edf2c riscv: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 22:46:04 +08:00
Alin Jerpelea
879d38d511 arch/arm64: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
7428644711 arch/avr: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
6e268f3c45 arch/ceva: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
d2b24c8e3a arch/hc: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
d69ac54147 arch/misps: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
7693764f34 arch/misoc: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
35ff0d834e arch/or1k: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
wangmingrong1
9555f9ff55 arm64/mte: Add support for arm64 mte
For details, please refer to the kernel's introduction to this at "https://docs.kernel.org/arch/arm64/memory-tagging-extension.html" and Android's introduction to this at "https://source.android.com/docs/security/test/memory-safety/arm-mte"

Of course, there is also the following detailed principle introduction
https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Arm_Memory_Tagging_Extension_Whitepaper.pdf

The modification of this patch is only to merge the simplest MTE function support. In the future, the MTE function will be integrated into the kernel to a greater extent, for example, hardware MTE Kasan will be supported in the future.

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-12-02 11:04:11 -03:00
wangmingrong1
1e32122709 arm64/qemu: Add support for arm64 qemu's maximum feature cpu
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-12-02 11:04:11 -03:00
hujun5
64c3e972a0 fix compile error
CC:  mqueue.c common/riscv_exit.c: In function 'up_exit':
common/riscv_exit.c:65:33: error: 'tcb' undeclared (first use in this function); did you mean 'tcb_s'?
   65 |   g_running_tasks[this_cpu()] = tcb;
      |                                 ^~~
      |                                 tcb_s

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 20:50:21 +08:00
hujun5
cc96289e2d xtensa: syscall SYS_switch_context and SYS_restore_context use 0 para
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)

size nuttx

before
   text    data     bss     dec     hex filename
 187620    1436  169296  358352   577d0 nuttx
after
   text    data     bss     dec     hex filename
 187576    1452  169280  358308   577a4 nuttx

size reduce -44

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 20:05:05 +08:00
Michal Lenc
9fbb81e8a4 samv7: fix bytes to words calculation in user signature read
EEFC read sequence requires read length in words instead of bytes,
therefore bytes given by the user has to be recalculated to words.
The calculation however had a mistake in brackets and was just adding
1 to buflen instead of recalculating it to 4 byte words. This caused
global array g_page_buffer to overflow for some reads.

This fixes the calculation.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-12-02 19:47:43 +08:00
hujun5
400239877d risc-v: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 17:41:16 +08:00
Alin Jerpelea
19e42a8978 arch/tricore: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
3013ff9ba9 arch/renesas: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
3dde10adaa arch/risk-v: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
eea3d77a6e arch/sim: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
7d3fe64a6a arch/sparc: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
b6a32301ee arch/x86: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
5e0347b20a arch/x86_64: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
8d50457dfc arch/xtensa: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
b3e1e21c65 arch/z16: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
2024-12-02 17:23:25 +08:00
Alin Jerpelea
99d8641cdd arch/z80: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
2024-12-02 17:23:25 +08:00
hujun5
3c32517b94 riscv: syscall SYS_switch_context and SYS_restore_context use 0 para
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)

size nuttx
before
   text    data     bss     dec     hex filename
 148021     921   26944  175886   2af0e nuttx

after
   text    data     bss     dec     hex filename
 147995     921   26928  175844   2aee4 nuttx

size reduce -42

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 14:44:37 +08:00
hujun5
8b46a4d916 lc823450_usbdev: use small lock in arch/arm/src/lc823450/lc823450_usbdev.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:35:14 +08:00
hujun5
c116b6578a max32660_wdt: use small lock in arch/arm/src/max326xx/max32660/max32660_wdt.c
reason:
we plan to remove all instances of spin_lock_irqsave(NULL)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:34:53 +08:00
hujun5
a0420df332 xtensa: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:29:59 +08:00
hujun5
30940d9251 imxrt_serial: use small lock in arch/arm/src/imxrt/imxrt_serial.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-01 18:02:10 +08:00
wangjianyu3
074c494f8f nrf91: Support using different nbuffer for each topic
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2024-11-30 14:10:57 +08:00
hujun5
ab0fb80e2b arm64: change some format
fix the comment in https://github.com/apache/nuttx/pull/14980

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 03:15:54 +08:00
hujun5
74dfcdfbd6 cxd56xx: use small lock in arch/arm/src/cxd56xx/cxd56_clock.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 03:15:02 +08:00
Eero Nurkkala
53f4216977 risc-v/mpfs: clear IPIs at boot
Inter-processor interrupts (IPIs) are not cleared via mie/mip registers but
rather, at the MPFS_CLINT_BASE + mhartid * 4 (a word or 4-byte offset for
each hart).

If there's an IPI waiting, the system will continue to boot altough it's
expected to stay at the wfi loop waiting for the IPI.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-11-30 03:14:10 +08:00
Eero Nurkkala
e111c9a256 risc-v/mpfs: introduce CONFIG_MPFS_CLKINIT flag
This CONFIG_MPFS_CLKINIT is set with bootloaders by default. However,
this gives an option to have it unset. In some cases, the clocks
may be already set so it becomes unnecessary to re-initialize them.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-11-30 03:14:10 +08:00
buxiasen
7a4fac0df6 coredump: add BOARD_CRASHDUMP_CUSTOM support
For only board specific crashdump and no syslog/blk/mtd coredump

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-11-30 03:08:35 +08:00
hujun5
321419491e missing update running_task
This commit fixes the regression from https://github.com/apache/nuttx/pull/14865

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 02:48:58 +08:00
hujun5
635da96bae xtensa: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 02:48:58 +08:00
wangmingrong1
137ca05249 arm64/toolchain: Cmake alignment makefile writing
They should be a relationship of choice:
ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
  ARCHCPUFLAGS += -mcpu=cortex-a53
else ifeq ($(CONFIG_ARCH_CORTEX_A55),y)
  ARCHCPUFLAGS += -mcpu=cortex-a55
else ifeq ($(CONFIG_ARCH_CORTEX_A57),y)
  ARCHCPUFLAGS += -mcpu=cortex-a57
else ifeq ($(CONFIG_ARCH_CORTEX_A72),y)
  ARCHCPUFLAGS += -mcpu=cortex-a72
else ifeq ($(CONFIG_ARCH_CORTEX_R82),y)
  ARCHCPUFLAGS += -mcpu=cortex-r82
else ifeq ($(CONFIG_ARCH_ARMV8A),y)
  ARCHCPUFLAGS += -march=armv8-a
else ifeq ($(CONFIG_ARCH_ARMV8R),y)
  ARCHCPUFLAGS += -march=armv8-r
endif

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-29 18:37:21 +08:00
chao an
8257b11944 arm/isr: move up_set_interrupt_context() to chip define
up_set_interrupt_context() is chip specific implement, move this function to correct place

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-29 18:37:08 +08:00
hujun5
d89f22eb98 arm64: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-29 10:04:50 +01:00
Jouni Ukkonen
1bfe8bcf71 arch/arm64/imx9: Boot, move mmu init to correct place
MMU init must be after ddrinit.

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-29 10:03:28 +01:00
simbit18
9c9b945876 fix nxstyle
Removed extra spaces from .h and .c files
2024-11-28 20:40:13 +08:00
YAMAMOTO Takashi
388ab6c2db esp32s3: don't clear pending interrupts on eg. up_putc
Fixes https://github.com/apache/nuttx/issues/14872
2024-11-28 19:00:21 +08:00
hujun5
0bba53ce12 remove redundant scheduling records
reason:
Since the scheduling records have already been moved to the interrupt exit in this submission,
we need to delete the original records' locations.
This commit fixes the regression from https://github.com/apache/nuttx/pull/13651

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-28 18:56:13 +08:00
guoshichao
a2fcd9862c nuttx/arch: remove the custom board check in up_testset implementation
the up_testset implementation is common code, should not add custom
board check

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-28 15:06:57 +08:00
Jouni Ukkonen
6b38b83331 arch/arm64/imx9: Clear DMA channel interrupts on init
Avoid spurious interrupts on reboot

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-28 15:02:15 +08:00