Merge a7390aeb03 into 43797ea6cc

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>

arch/arm64/src/common/arm64_addrenv.c

@@ -179,8 +179,8 @@ static int create_spgtables(arch_addrenv_t *addrenv)
 
   /* Synchronize data and instruction pipelines */
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   return i;
 }
@@ -337,8 +337,8 @@ static int create_region(arch_addrenv_t *addrenv, uintptr_t vaddr,
 
   /* Synchronize data and instruction pipelines */
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   return npages;
 }
@@ -514,8 +514,8 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
 
   /* Synchronize data and instruction pipelines */
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   return OK;
 
@@ -603,8 +603,8 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv)
 
   /* Synchronize data and instruction pipelines */
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   memset(addrenv, 0, sizeof(arch_addrenv_t));
   return OK;

arch/arm64/src/common/arm64_addrenv_pgmap.c

@@ -218,7 +218,7 @@ int up_addrenv_kmap_init(void)
 
   /* When all is set and done, flush the data caches */
 
-  ARM64_DSB();
+  __MB();
 
   return OK;
 }

arch/arm64/src/common/arm64_arch.h

@@ -321,13 +321,13 @@ static inline uint8_t getreg8(unsigned long addr)
 
   __asm__ volatile ("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
 
-  ARM64_DMB();
+  __DMB();
   return val;
 }
 
 static inline void putreg8(uint8_t data, unsigned long addr)
 {
-  ARM64_DMB();
+  __DMB();
   __asm__ volatile ("strb %w0, [%1]" : : "r" (data), "r" (addr));
 }
 
@@ -337,13 +337,13 @@ static inline uint16_t getreg16(unsigned long addr)
 
   __asm__ volatile ("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
 
-  ARM64_DMB();
+  __DMB();
   return val;
 }
 
 static inline void putreg16(uint16_t data, unsigned long addr)
 {
-  ARM64_DMB();
+  __DMB();
   __asm__ volatile ("strh %w0, [%1]" : : "r" (data), "r" (addr));
 }
 
@@ -353,13 +353,13 @@ static inline uint32_t getreg32(unsigned long addr)
 
   __asm__ volatile ("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
 
-  ARM64_DMB();
+  __DMB();
   return val;
 }
 
 static inline void putreg32(uint32_t data, unsigned long addr)
 {
-  ARM64_DMB();
+  __DMB();
   __asm__ volatile ("str %w0, [%1]" : : "r" (data), "r" (addr));
 }
 
@@ -369,13 +369,13 @@ static inline uint64_t getreg64(unsigned long addr)
 
   __asm__ volatile ("ldr %x0, [%1]" : "=r" (val) : "r" (addr));
 
-  ARM64_DMB();
+  __DMB();
   return val;
 }
 
 static inline void putreg64(uint64_t data, unsigned long addr)
 {
-  ARM64_DMB();
+  __DMB();
   __asm__ volatile ("str %x0, [%1]" : : "r" (data), "r" (addr));
 }
 

arch/arm64/src/common/arm64_boot.c

@@ -66,7 +66,7 @@ void arm64_boot_el3_init(void)
   /* Setup vector table */
 
   write_sysreg((uint64_t)_vector_table, vbar_el3);
-  ARM64_ISB();
+  __ISB();
 
   reg = 0U;                   /* Mostly RES0 */
   reg &= ~(CPTR_TTA_BIT |     /* Do not trap sysreg accesses */
@@ -101,7 +101,7 @@ void arm64_boot_el3_init(void)
   write_sysreg(reg, ICC_SRE_EL3);
 #endif
 
-  ARM64_ISB();
+  __ISB();
 }
 
 void arm64_boot_el3_get_next_el(uint64_t switch_addr)
@@ -175,7 +175,7 @@ void arm64_boot_el2_init(void)
    * write_cnthp_cval_el2(~(uint64_t)0);
    */
 
-  ARM64_ISB();
+  __ISB();
 }
 
 void arm64_boot_el1_init(void)
@@ -185,7 +185,7 @@ void arm64_boot_el1_init(void)
   /* Setup vector table */
 
   write_sysreg((uint64_t)_vector_table, vbar_el1);
-  ARM64_ISB();
+  __ISB();
 
   reg = 0U;                       /* RES0 */
   reg |= CPACR_EL1_FPEN_NOTRAP;   /* Do not trap NEON/SIMD/FP initially */
@@ -209,7 +209,7 @@ void arm64_boot_el1_init(void)
    * write_cntps_cval_el1(~(uint64_t)0);
    */
 
-  ARM64_ISB();
+  __ISB();
 }
 
 void arm64_boot_primary_c_routine(void)

arch/arm64/src/common/arm64_cache.c

@@ -206,8 +206,8 @@ static inline int arm64_dcache_range(uintptr_t start_addr,
       start_addr += line_size;
     }
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   return 0;
 }
@@ -232,7 +232,7 @@ static inline int arm64_dcache_all(int op)
 
   /* Data barrier before start */
 
-  ARM64_DSB();
+  __MB();
 
   clidr_el1 = read_sysreg(clidr_el1);
 
@@ -259,7 +259,7 @@ static inline int arm64_dcache_all(int op)
 
       csselr_el1 = cache_level << 1;
       write_sysreg(csselr_el1, csselr_el1);
-      ARM64_ISB();
+      __ISB();
 
       ccsidr_el1    = read_sysreg(ccsidr_el1);
       line_size     =
@@ -319,8 +319,8 @@ static inline int arm64_dcache_all(int op)
   /* Restore csselr_el1 to level 0 */
 
   write_sysreg(0, csselr_el1);
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   return 0;
 }
@@ -427,7 +427,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
 
   start = LINE_ALIGN_DOWN(start, line_size);
 
-  ARM64_DSB();
+  __MB();
 
   while (start < end)
     {
@@ -435,7 +435,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
       start += line_size;
     }
 
-  ARM64_ISB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -456,7 +456,7 @@ void up_enable_icache(void)
 {
   uint64_t value = read_sysreg(sctlr_el1);
   write_sysreg((value | SCTLR_I_BIT), sctlr_el1);
-  ARM64_ISB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -477,7 +477,7 @@ void up_disable_icache(void)
 {
   uint64_t value = read_sysreg(sctlr_el1);
   write_sysreg((value & ~SCTLR_I_BIT), sctlr_el1);
-  ARM64_ISB();
+  __ISB();
 }
 
 #endif /* CONFIG_ARCH_ICACHE */
@@ -668,7 +668,7 @@ void up_enable_dcache(void)
 
   value = read_sysreg(sctlr_el1);
   write_sysreg((value | SCTLR_C_BIT), sctlr_el1);
-  ARM64_ISB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -689,7 +689,7 @@ void up_disable_dcache(void)
 {
   uint64_t value = read_sysreg(sctlr_el1);
   write_sysreg((value & ~SCTLR_C_BIT), sctlr_el1);
-  ARM64_ISB();
+  __ISB();
 }
 
 /****************************************************************************

arch/arm64/src/common/arm64_fork.c

@@ -66,7 +66,7 @@ void arm64_fork_fpureg_save(struct fork_s *context)
   flags = enter_critical_section();
 
   arm64_fpu_save(context->fpu);
-  ARM64_DSB();
+  __MB();
 
   leave_critical_section(flags);
 }

arch/arm64/src/common/arm64_fpu.c

@@ -134,7 +134,7 @@ static void arm64_fpu_access_trap_enable(void)
   cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
   write_sysreg(cpacr, cpacr_el1);
 
-  ARM64_ISB();
+  __ISB();
 }
 
 /* disable FPU access trap */
@@ -147,7 +147,7 @@ static void arm64_fpu_access_trap_disable(void)
   cpacr |= CPACR_EL1_FPEN_NOTRAP;
   write_sysreg(cpacr, cpacr_el1);
 
-  ARM64_ISB();
+  __ISB();
 }
 
 #ifdef CONFIG_FS_PROCFS_REGISTER

arch/arm64/src/common/arm64_gicv3.c

@@ -303,7 +303,7 @@ unsigned int arm64_gic_get_active_irq(void)
    * to be visible until after the execution of a DSB.
    */
 
-  ARM64_DSB();
+  __MB();
   return intid;
 }
 
@@ -322,7 +322,7 @@ unsigned int arm64_gic_get_active_fiq(void)
    * to be visible until after the execution of a DSB.
    */
 
-  ARM64_DSB();
+  __MB();
   return intid;
 }
 #endif
@@ -340,13 +340,13 @@ void aarm64_gic_eoi_irq(unsigned int intid)
    * DEVICE nGnRnE attribute.
    */
 
-  ARM64_DSB();
+  __MB();
 
   /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
 
   write_sysreg(intid, ICC_EOIR1_EL1);
 
-  ARM64_ISB();
+  __ISB();
 }
 
 #ifdef CONFIG_ARM64_DECODEFIQ
@@ -363,12 +363,12 @@ void arm64_gic_eoi_fiq(unsigned int intid)
    * DEVICE nGnRnE attribute.
    */
 
-  ARM64_DSB();
+  __MB();
 
   /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
 
   write_sysreg(intid, ICC_EOIR0_EL1);
-  ARM64_ISB();
+  __ISB();
 }
 #endif
 
@@ -392,7 +392,7 @@ static int arm64_gic_send_sgi(unsigned int sgi_id, uint64_t target_aff,
   sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
                              target_list);
 
-  ARM64_DSB();
+  __MB();
 
   /* Read the IGROUPR0 value we set in `gicv3_cpuif_init` */
 
@@ -407,7 +407,7 @@ static int arm64_gic_send_sgi(unsigned int sgi_id, uint64_t target_aff,
       write_sysreg(sgi_val, ICC_SGI0R_EL1); /* Group 0 */
     }
 
-  ARM64_ISB();
+  __ISB();
 
   return 0;
 }
@@ -520,7 +520,7 @@ static void gicv3_cpuif_init(void)
          ICC_SRE_ELX_DFB_BIT);
       write_sysreg(icc_sre, ICC_SRE_EL1);
 
-      ARM64_ISB();
+      __ISB();
 
       icc_sre = read_sysreg(ICC_SRE_EL1);
 
@@ -537,7 +537,7 @@ static void gicv3_cpuif_init(void)
   write_sysreg(1, ICC_IGRPEN0_EL1);
 #endif
 
-  ARM64_ISB();
+  __ISB();
 }
 
 static void gicv3_dist_init(void)

arch/arm64/src/common/arm64_mmu.c

@@ -576,8 +576,8 @@ static void enable_mmu_el3(unsigned int flags)
 
   /* Ensure these changes are seen before MMU is enabled */
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   /* Enable the MMU and data cache */
 
@@ -590,7 +590,7 @@ static void enable_mmu_el3(unsigned int flags)
 
   /* Ensure the MMU enable takes effect immediately */
 
-  ARM64_ISB();
+  __ISB();
 #ifdef CONFIG_MMU_DEBUG
   sinfo("MMU enabled with dcache\n");
 #endif
@@ -609,8 +609,8 @@ static void enable_mmu_el1(unsigned int flags)
 
   /* Ensure these changes are seen before MMU is enabled */
 
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 
   /* Enable the MMU and data cache */
 
@@ -623,7 +623,7 @@ static void enable_mmu_el1(unsigned int flags)
 
   /* Ensure the MMU enable takes effect immediately */
 
-  ARM64_ISB();
+  __ISB();
 #ifdef CONFIG_MMU_DEBUG
   sinfo("MMU enabled with dcache\n");
 #endif

arch/arm64/src/common/arm64_mpu.c

@@ -128,8 +128,8 @@ static void mpu_init(void)
   uint64_t mair = MPU_MAIR_ATTRS;
 
   write_sysreg(mair, mair_el1);
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -185,15 +185,15 @@ void mpu_freeregion(unsigned int region)
   DEBUGASSERT(region < num_regions);
 
   write_sysreg(region, prselr_el1);
-  ARM64_DSB();
+  __MB();
 
   /* Set the region base, limit and attribute */
 
   write_sysreg(0, prbar_el1);
   write_sysreg(0, prlar_el1);
   g_mpu_region &= ~(1 << region);
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -221,8 +221,8 @@ void arm64_mpu_enable(void)
 #endif
          );
   write_sysreg(val, sctlr_el1);
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -245,13 +245,13 @@ void arm64_mpu_disable(void)
 
   /* Force any outstanding transfers to complete before disabling MPU */
 
-  ARM64_DMB();
+  __DMB();
 
   val = read_sysreg(sctlr_el1);
   val &= ~(SCTLR_M_BIT | SCTLR_C_BIT);
   write_sysreg(val, sctlr_el1);
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 }
 
 /****************************************************************************
@@ -290,14 +290,14 @@ void mpu_modify_region(unsigned int region,
   /* Select the region */
 
   write_sysreg(region, prselr_el1);
-  ARM64_DSB();
+  __MB();
 
   /* Set the region base, limit and attribute */
 
   write_sysreg(rbar, prbar_el1);
   write_sysreg(rlar, prlar_el1);
-  ARM64_DSB();
-  ARM64_ISB();
+  __MB();
+  __ISB();
 }
 
 /****************************************************************************

arch/arm64/src/common/barriers.h

@@ -37,13 +37,13 @@
  * ARM DDI 0487E.a C6.2.81
  */
 
-#define __DSB(arg) __asm__ volatile ("dsb " #arg : : : "memory");
+#define __MB() __asm__ volatile ("dsb sy" : : : "memory");
 
 /* See Arm® Architecture Reference Manual
  * ARM DDI 0487E.a C6.2.79
  */
 
-#define __DMB(arg) __asm__ volatile ("dmb " #arg : : : "memory");
+#define __DMB() __asm__ volatile ("dmb sy" : : : "memory");
 
 /* See Arm® Architecture Reference Manual
  * ARM DDI 0487E.a C6.2.96
@@ -51,12 +51,6 @@
 
 #define __ISB()    __asm__ volatile ("isb" : : : "memory");
 
-/* THe most common barriers */
-
-#define ARM64_DSB()  __DSB(sy)
-#define ARM64_DMB()  __DMB(sy)
-#define ARM64_ISB()  __ISB()
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* ___ARCH_ARM64_SRC_COMMON_BARRIERS_H */

arch/arm64/src/fvp-v8r/fvp_boot.c

@@ -113,7 +113,7 @@ void arm64_el_init(void)
 {
   write_sysreg(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cntfrq_el0);
 
-  ARM64_ISB();
+  __ISB();
 }
 
 #ifdef CONFIG_SMP

arch/arm64/src/goldfish/goldfish_boot.c

@@ -134,7 +134,7 @@ void arm64_el_init(void)
 {
   write_sysreg(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cntfrq_el0);
 
-  ARM64_ISB();
+  __ISB();
 }
 
 /****************************************************************************

arch/arm64/src/imx8/imx8_boot.c

@@ -89,7 +89,7 @@ void arm64_el_init(void)
   if (el == 3)
     {
       write_sysreg(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cntfrq_el0);
-      ARM64_ISB();
+      __ISB();
     }
 }
 

arch/arm64/src/imx9/imx9_ccm.c

@@ -43,12 +43,12 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define mb()       \
-  do               \
-    {              \
-      ARM64_DSB(); \
-      ARM64_ISB(); \
-    }              \
+#define mb()   \
+  do           \
+    {          \
+      __MB();  \
+      __ISB(); \
+    }          \
   while (0)
 
 /****************************************************************************

arch/arm64/src/imx9/imx9_clockconfig.c

@@ -52,12 +52,12 @@
 
 /* Common barrier */
 
-#define mb()       \
-  do               \
-    {              \
-      ARM64_DSB(); \
-      ARM64_ISB(); \
-    }              \
+#define mb()   \
+  do           \
+    {          \
+      __MB();  \
+      __ISB(); \
+    }          \
   while (0)
 
 /****************************************************************************

arch/arm64/src/imx9/imx9_enet.c

@@ -611,7 +611,7 @@ static int imx9_transmit(struct imx9_driver_s *priv, uint32_t *buf_swap)
 
   txdesc2->data = buf + split;
 
-  ARM64_DSB();
+  __MB();
 
   /* Make sure the buffer data is in memory */
 
@@ -650,9 +650,9 @@ static int imx9_transmit(struct imx9_driver_s *priv, uint32_t *buf_swap)
    * is safe to clean the cache
    */
 
-  ARM64_DMB();
+  __DMB();
   txdesc->status1 = TXDESC_R;
-  ARM64_DSB();
+  __MB();
 
   /* Make sure the descriptors are written from cache to memory */
 
@@ -999,9 +999,9 @@ static void imx9_receive(struct imx9_driver_s *priv)
                * to this descriptor pair.
                */
 
-              ARM64_DMB();
+              __DMB();
               rxdesc->status1  = RXDESC_E;
-              ARM64_DSB();
+              __MB();
 
               up_clean_dcache((uintptr_t)&rxdesc[(-1)],
                               (uintptr_t)&rxdesc[(-1)] +
@@ -2955,7 +2955,7 @@ static void imx9_initbuffers(struct imx9_driver_s *priv)
   priv->txdesc[IMX9_ENET_NTXBUFFERS - 1].d2.status1 |= TXDESC_W;
   priv->rxdesc[IMX9_ENET_NRXBUFFERS - 1].status1 |= RXDESC_W;
 
-  ARM64_DSB();
+  __MB();
 
   up_clean_dcache((uintptr_t)priv->txdesc,
                   (uintptr_t)priv->txdesc +

arch/arm64/src/imx9/imx9_flexcan.c

@@ -1280,7 +1280,7 @@ static void imx9_txtimeout_work(void *arg)
       /* Disable interrupt for this MB */
 
       modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, mb_bit, 0);
-      ARM64_DSB();
+      __MB();
 
       if (priv->txmb[txmbi].deadline.tv_sec != 0
           && (now->tv_sec > priv->txmb[txmbi].deadline.tv_sec

arch/arm64/src/imx9/imx9_usbdev.c

@@ -871,7 +871,7 @@ static void imx9_readsetup(struct imx9_usb_s *priv, uint8_t epphy,
   /* Set the trip wire */
 
   imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_SUTW);
-  ARM64_DSB();
+  __MB();
 
   DEBUGASSERT(IS_CACHE_ALIGNED(dqh, sizeof(struct imx9_dqh_s)));
   up_invalidate_dcache((uintptr_t)dqh,
@@ -895,7 +895,7 @@ static void imx9_readsetup(struct imx9_usb_s *priv, uint8_t epphy,
 
   imx9_putreg(priv, IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET,
               IMX9_ENDPTMASK(IMX9_EP0_OUT));
-  ARM64_DSB();
+  __MB();
 }
 
 /****************************************************************************
@@ -1325,7 +1325,7 @@ static inline void imx9_ep0state(struct imx9_usb_s *priv,
       break;
     }
 
-  ARM64_DSB();
+  __MB();
 }
 
 /****************************************************************************

arch/arm64/src/zynq-mpsoc/zynq_boot.c

@@ -99,7 +99,7 @@ void arm64_el_init(void)
   /* At EL3, cntfrq_el0 is uninitialized. It must be set. */
 
   write_sysreg(CONFIG_XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ, cntfrq_el0);
-  ARM64_ISB();
+  __ISB();
 #endif
 }
 

boards/arm64/a64/pinephone/src/pinephone_display.c

@@ -914,9 +914,9 @@ void pinephone_display_test_pattern(void)
 
       /* Fixes missing rows in the rendered image, not sure why */
 
-      ARM64_DMB();
-      ARM64_DSB();
-      ARM64_ISB();
+      __DMB();
+      __MB();
+      __ISB();
     }
 
   /* Init Framebuffer 1:
@@ -931,9 +931,9 @@ void pinephone_display_test_pattern(void)
 
       /* Fixes missing rows in the rendered image, not sure why */
 
-      ARM64_DMB();
-      ARM64_DSB();
-      ARM64_ISB();
+      __DMB();
+      __MB();
+      __ISB();
     }
 
   /* Init Framebuffer 2:
@@ -972,9 +972,9 @@ void pinephone_display_test_pattern(void)
 
           /* Fixes missing rows in the rendered image, not sure why */
 
-          ARM64_DMB();
-          ARM64_DSB();
-          ARM64_ISB();
+          __DMB();
+          __MB();
+          __ISB();
         }
     }
 }