Merge 4d45e6cd44 into a2d4d74af7

reason:
We would like to replace the critical section with a small lock.

Signed-off-by: hujun5 <hujun5@xiaomi.com>

CMakeLists.txt

@@ -87,7 +87,7 @@ find_program(KCONFIGLIB olddefconfig)
 if(NOT KCONFIGLIB)
   message(
     FATAL_ERROR "Kconfig environment depends on kconfiglib, Please install:
-  $ sudo apt install python3-kconfiglib")
+  $ sudo pip3 install kconfiglib")
 endif()
 
 # BOARD CONFIG can be set to directory path, or <board-name>[/:]<config-name>
@@ -727,6 +727,7 @@ else()
       OUTPUT nuttx.rel
       COMMAND
         ${CMAKE_C_COMPILER} ARGS -r $<$<BOOL:${CONFIG_SIM_M32}>:-m32>
+        $<$<BOOL:${CONFIG_HOST_LINUX}>:-Wl,-z,noexecstack>
         $<TARGET_OBJECTS:sim_head> $<$<NOT:$<BOOL:${APPLE}>>:-Wl,--start-group>
         ${nuttx_libs_paths} $<$<NOT:$<BOOL:${APPLE}>>:-Wl,--end-group> -o
         nuttx.rel

arch/arm/src/common/Toolchain.defs

@@ -546,7 +546,9 @@ ifeq ($(CONFIG_PIC),y)
   # Generate an executable elf, need to ignore undefined symbols
   LDELFFLAGS += --unresolved-symbols=ignore-in-object-files --emit-relocs
 else
-  LDELFFLAGS += -r
+  ifneq ($(CONFIG_BINFMT_ELF_EXECUTABLE),y)
+    LDELFFLAGS += -r
+  endif
 endif
 
 LDELFFLAGS +=  -e main -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)libs$(DELIM)libc$(DELIM)modlib$(DELIM)gnu-elf.ld)

arch/arm/src/imx9/imx9_lpi2c.c

@@ -1103,7 +1103,7 @@ static void imx9_lpi2c_setclock(struct imx9_lpi2c_priv_s *priv,
                                             &src_freq);
 
           /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
-           *   (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale)
+           *   (CLKLO + 1 + CLKHI + 1 + ALIGN_DOWN((2 + FILTSCL)/2^prescale)
            *
            * Assume  CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2
            */

arch/arm/src/imxrt/imxrt_lpi2c.c

@@ -1161,7 +1161,7 @@ static void imxrt_lpi2c_setclock(struct imxrt_lpi2c_priv_s *priv,
 #endif
 
           /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
-           *   (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale)
+           *   (CLKLO + 1 + CLKHI + 1 + ALIGN_DOWN((2 + FILTSCL)/2^prescale)
            *
            * Assume  CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2
            */

arch/arm/src/qemu/Kconfig

@@ -15,6 +15,7 @@ config ARCH_CHIP_QEMU_CORTEXA7
 	bool "Qemu virtual Processor (cortex-a7)"
 	select ARCH_CORTEXA7
 	select ARCH_HAVE_ADDRENV
+	select ARCH_HAVE_ELF_EXECUTABLE
 	select ARCH_HAVE_LOWVECTORS
 	select ARCH_HAVE_MULTICPU
 	select ARCH_NEED_ADDRENV_MAPPING

arch/arm/src/s32k1xx/s32k1xx_lpi2c.c

@@ -1010,7 +1010,7 @@ static void s32k1xx_lpi2c_setclock(struct s32k1xx_lpi2c_priv_s *priv,
           DEBUGASSERT(src_freq != 0);
 
           /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
-           *   (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale)
+           *   (CLKLO + 1 + CLKHI + 1 + ALIGN_DOWN((2 + FILTSCL)/2^prescale)
            *
            * Assume  CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2
            */

arch/arm/src/s32k3xx/s32k3xx_lpi2c.c

@@ -990,7 +990,7 @@ static void s32k3xx_lpi2c_setclock(struct s32k3xx_lpi2c_priv_s *priv,
           DEBUGASSERT(src_freq != 0);
 
           /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
-           *   (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale)
+           *   (CLKLO + 1 + CLKHI + 1 + ALIGN_DOWN((2 + FILTSCL)/2^prescale)
            *
            * Assume  CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2
            */

arch/arm/src/stm32h5/Kconfig

@@ -2920,10 +2920,10 @@ config STM32H5_ADC1_SAMPLE_FREQUENCY
 config STM32H5_ADC1_TIMTRIG
 	int "ADC1 Timer Trigger"
 	default 0
-	range 0 4
+	range 0 5
 	depends on STM32H5_HAVE_ADC1_TIMER
 	---help---
-		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
 
 config STM32H5_ADC2_SAMPLE_FREQUENCY
 	int "ADC2 Sampling Frequency"
@@ -2935,10 +2935,10 @@ config STM32H5_ADC2_SAMPLE_FREQUENCY
 config STM32H5_ADC2_TIMTRIG
 	int "ADC2 Timer Trigger"
 	default 0
-	range 0 4
+	range 0 5
 	depends on STM32H5_HAVE_ADC2_TIMER
 	---help---
-		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
 
 config STM32H5_TIM1_CAP
 	bool "TIM1 Capture"

arch/arm/src/stm32h5/hardware/stm32_tim.h

@@ -363,6 +363,26 @@
 #define STM32_TIM16_DCR          (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
 #define STM32_TIM16_DMAR         (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
 
+#define STM32_TIM17_CR1          (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
+#define STM32_TIM17_CR2          (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
+#define STM32_TIM17_DIER         (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
+#define STM32_TIM17_SR           (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
+#define STM32_TIM17_EGR          (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
+#define STM32_TIM17_CCMR1        (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
+#define STM32_TIM17_CCER         (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
+#define STM32_TIM17_CNT          (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
+#define STM32_TIM17_PSC          (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
+#define STM32_TIM17_ARR          (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
+#define STM32_TIM17_RCR          (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
+#define STM32_TIM17_CCR1         (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
+#define STM32_TIM17_BDTR         (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
+#define STM32_TIM17_DTR2         (STM32_TIM17_BASE+STM32_GTIM_DTR2_OFFSET)
+#define STM32_TIM17_TISEL        (STM32_TIM17_BASE+STM32_GTIM_TISEL_OFFSET)
+#define STM32_TIM17_AF1          (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET)
+#define STM32_TIM17_AF2          (STM32_TIM17_BASE+STM32_GTIM_AF2_OFFSET)
+#define STM32_TIM17_DCR          (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
+#define STM32_TIM17_DMAR         (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
+
 /* Register Bitfield Definitions ********************************************/
 
 /* Basic Timers - TIM6 and TIM7 */
@@ -764,6 +784,12 @@
 #define ATIM_CCER_CC4E            (1 << 12)   /* Bit 12: Capture/Compare 4 output enable */
 #define ATIM_CCER_CC4P            (1 << 13)   /* Bit 13: Capture/Compare 4 output Polarity */
 #define ATIM_CCER_CC4NE           (1 << 14)   /* Bit 14: Capture/compare 4 Complementary output enable */
+#define ATIM_CCER_CC4NP           (1 << 15)   /* Bit 15: Capture/Compare 4 Complementary output polarity */
+#define ATIM_CCER_CC5E            (1 << 16)   /* Bit 16: Capture/Compare 5 output enable */
+#define ATIM_CCER_CC5P            (1 << 17)   /* Bit 17: Capture/Compare 5 output Polarity */
+#define ATIM_CCER_CC6E            (1 << 20)   /* Bit 20: Capture/Compare 6 output enable */
+#define ATIM_CCER_CC6P            (1 << 21)   /* Bit 21: Capture/Compare 6 output Polarity */
+
 #define ATIM_CCER_CCXBASE(ch)     ((ch) << 2) /* Each channel uses 4-bits */
 
 /* Counter Register */

arch/arm/src/stm32h5/stm32_adc.c

@@ -47,6 +47,7 @@
 
 #include "chip.h"
 #include "stm32_adc.h"
+#include "stm32_tim.h"
 #include "stm32_rcc.h"
 
 #ifdef CONFIG_ADC
@@ -166,6 +167,16 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value);
 static void adc_modifyreg(struct stm32_dev_s *priv, int offset,
                               uint32_t clrbits, uint32_t setbits);
 
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset);
+static void     tim_putreg(struct stm32_dev_s *priv, int offset,
+                           uint16_t value);
+static void     tim_modifyreg(struct stm32_dev_s *priv, int offset,
+                              uint16_t clrbits, uint16_t setbits);
+static void     tim_dumpregs(struct stm32_dev_s *priv,
+                             const char *msg);
+#endif
+
 /* ADC Miscellaneous Helpers */
 
 static void adc_rccreset(struct stm32_dev_s *priv, bool reset);
@@ -178,6 +189,11 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr);
 static void adc_startconv(struct stm32_dev_s *priv, bool enable);
 static void adc_wdog_enable(struct stm32_dev_s *priv);
 
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(struct stm32_dev_s *priv, bool enable);
+static int  adc_timinit(struct stm32_dev_s *priv);
+#endif
+
 /* ADC Interrupt Handler */
 
 static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval);
@@ -220,6 +236,15 @@ static struct stm32_dev_s g_adcpriv1 =
   .base        = STM32_ADC1_BASE,
   .mbase       = STM32_ADC1_BASE,
   .initialized = false,
+#ifdef ADC1_HAVE_TIMER
+  .trigger     = CONFIG_STM32H5_ADC1_TIMTRIG,
+  .tbase       = ADC1_TIMER_BASE,
+  .trcc_enr    = ADC1_TIMER_RCC_ENR,
+  .trcc_en     = ADC1_TIMER_RCC_EN,
+  .extsel      = ADC1_EXTSEL_VALUE,
+  .pclck       = ADC1_TIMER_PCLK_FREQUENCY,
+  .freq        = CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY,
+#endif
 };
 
 static struct adc_dev_s g_adcdev1 =
@@ -240,6 +265,15 @@ static struct stm32_dev_s g_adcpriv2 =
   .base        = STM32_ADC2_BASE,
   .mbase       = STM32_ADC2_BASE,
   .initialized = false,
+#ifdef ADC2_HAVE_TIMER
+  .trigger     = CONFIG_STM32H5_ADC2_TIMTRIG,
+  .tbase       = ADC2_TIMER_BASE,
+  .trcc_enr    = ADC2_TIMER_RCC_ENR,
+  .trcc_en     = ADC2_TIMER_RCC_EN,
+  .extsel      = ADC2_EXTSEL_VALUE,
+  .pclck       = ADC2_TIMER_PCLK_FREQUENCY,
+  .freq        = CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY,
+#endif
 };
 
 static struct adc_dev_s g_adcdev2 =
@@ -1212,7 +1246,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
   if ((adcisr & ADC_INT_EOC) != 0)
     {
       /* Read from the ADC_DR register until 8 stage FIFO is empty.
-       * The FIFO is first mentioned in STM32H7 Reference Manual
+       * The FIFO is first mentioned in STM32H5 Reference Manual
        * rev. 7, though, not yet indicated in the block diagram!
        */
 
@@ -1307,6 +1341,521 @@ static int adc12_interrupt(int irq, void *context, void *arg)
 }
 #endif
 
+/****************************************************************************
+ * Name: tim_getreg
+ *
+ * Description:
+ *   Read the value of an ADC timer register.
+ *
+ * Input Parameters:
+ *   priv   - A reference to the ADC block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   The current contents of the specified register
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset)
+{
+  return getreg16(priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_putreg
+ *
+ * Description:
+ *   Write a value to an ADC timer register.
+ *
+ * Input Parameters:
+ *   priv   - A reference to the ADC block status
+ *   offset - The offset to the register to write to
+ *   value  - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_putreg(struct stm32_dev_s *priv, int offset,
+                       uint16_t value)
+{
+  putreg16(value, priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_modifyreg
+ *
+ * Description:
+ *   Modify the value of an ADC timer register (not atomic).
+ *
+ * Input Parameters:
+ *   priv    - A reference to the ADC block status
+ *   offset  - The offset to the register to modify
+ *   clrbits - The bits to clear
+ *   setbits - The bits to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_modifyreg(struct stm32_dev_s *priv, int offset,
+                          uint16_t clrbits, uint16_t setbits)
+{
+  tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_dumpregs
+ *
+ * Description:
+ *   Dump all timer registers.
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg)
+{
+  ainfo("%s:\n", msg);
+  ainfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+        tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
+        tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+        tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
+  ainfo("   SR: %04x EGR:  0000 CCMR1: %04x CCMR2: %04x\n",
+        tim_getreg(priv, STM32_GTIM_SR_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+  ainfo(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
+        tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
+        tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
+        tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
+  ainfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
+        tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
+
+  if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
+    {
+      ainfo("  RCR: %04x BDTR: %04x DCR:   %04x DMAR:  %04x\n",
+            tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
+            tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
+            tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
+            tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
+    }
+  else
+    {
+      ainfo("  DCR: %04x DMAR: %04x\n",
+            tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
+            tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_timstart
+ *
+ * Description:
+ *   Start (or stop) the timer counter
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *   enable - True: Start conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(struct stm32_dev_s *priv, bool enable)
+{
+  ainfo("enable: %d\n", enable ? 1 : 0);
+
+  if (enable)
+    {
+      /* Start the counter */
+
+      tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
+    }
+  else
+    {
+      /* Disable the counter */
+
+      tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_timinit
+ *
+ * Description:
+ *   Initialize the timer that drivers the ADC sampling for this channel
+ *   using the pre-calculated timer divider definitions.
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static int adc_timinit(struct stm32_dev_s *priv)
+{
+  uint32_t prescaler;
+  uint32_t reload;
+  uint32_t timclk;
+
+  uint16_t clrbits = 0;
+  uint16_t setbits = 0;
+  uint16_t cr2;
+  uint16_t ccmr1;
+  uint16_t ccmr2;
+  uint16_t ocmode1;
+  uint16_t ocmode2;
+  uint16_t ccenable;
+  uint16_t ccer;
+  uint16_t egr;
+
+  /* If the timer base address is zero, then this ADC was not configured to
+   * use a timer.
+   */
+
+  if (priv->tbase == 0)
+    {
+      return ERROR;
+    }
+
+  /* EXTSEL selection: These bits select the external event used to trigger
+   * the start of conversion of a regular group.  NOTE:
+   *
+   * - The position with of the EXTSEL field varies from one STM32 MCU
+   *   to another.
+   * - The width of the EXTSEL field varies from one STM32 MCU to another.
+   * - The value in priv->extsel is already shifted into the correct bit
+   *   position.
+   */
+
+  ainfo("Initializing timers extsel = 0x%08" PRIx32 "\n", priv->extsel);
+
+  adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET,
+                ADC_CFGR_EXTEN_MASK | ADC_CFGR_EXTSEL_MASK,
+                ADC_CFGR_EXTEN_RISING | priv->extsel);
+
+  /* Configure the timer channel to drive the ADC */
+
+  /* Enable Timer clocking */
+
+  modifyreg32(priv->trcc_enr, 0, priv->trcc_en);
+
+  /* Calculate optimal values for the timer prescaler and for the timer
+   * reload register.  If freq is the desired frequency, then
+   *
+   *   reload = timclk / freq
+   *   reload = (pclck / prescaler) / freq
+   *
+   * There are many solutions to do this, but the best solution will be the
+   * one that has the largest reload value and the smallest prescaler value.
+   * That is the solution that should give us the most accuracy in the timer
+   * control.  Subject to:
+   *
+   *   0 <= prescaler  <= 65536
+   *   1 <= reload <= 65535
+   *
+   * So ( prescaler = pclck / 65535 / freq ) would be optimal.
+   */
+
+  prescaler = (priv->pclck / priv->freq + 65534) / 65535;
+
+  /* We need to decrement the prescaler value by one, but only, the value
+   * does not underflow.
+   */
+
+  if (prescaler < 1)
+    {
+      awarn("WARNING: Prescaler underflowed.\n");
+      prescaler = 1;
+    }
+
+  /* Check for overflow */
+
+  else if (prescaler > 65536)
+    {
+      awarn("WARNING: Prescaler overflowed.\n");
+      prescaler = 65536;
+    }
+
+  timclk = priv->pclck / prescaler;
+
+  reload = timclk / priv->freq;
+  if (reload < 1)
+    {
+      awarn("WARNING: Reload value underflowed.\n");
+      reload = 1;
+    }
+
+  else if (reload > 65535)
+    {
+      awarn("WARNING: Reload value overflowed.\n");
+      reload = 65535;
+    }
+
+  /* Disable the timer until we get it configured */
+
+  adc_timstart(priv, false);
+
+  /* Set up the timer CR1 register.
+   *
+   * Select the Counter Mode == count up:
+   *
+   * ATIM_CR1_EDGE: The counter counts up or down depending on the
+   *                direction bit(DIR).
+   * ATIM_CR1_DIR: 0: count up, 1: count down
+   *
+   * Set the clock division to zero for all
+   */
+
+  clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK;
+  setbits = GTIM_CR1_EDGE;
+  tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits);
+
+  /* Set the reload and prescaler values */
+
+  tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1);
+  tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
+
+  /* Clear the advanced timers repetition counter in TIM1 */
+
+  if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
+    {
+      tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
+      tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
+    }
+
+  /* TIMx event generation: Bit 0 UG: Update generation */
+
+  tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
+
+  /* Handle channel specific setup */
+
+  ocmode1 = 0;
+  ocmode2 = 0;
+
+  switch (priv->trigger)
+    {
+      case 0: /* TimerX CC1 event */
+        {
+          ccenable = ATIM_CCER_CC1E;
+          ocmode1  = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
+                     (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) |
+                     ATIM_CCMR1_OC1PE;
+
+          /* Set the event CC1 */
+
+          egr      = ATIM_EGR_CC1G;
+
+          /* Set the duty cycle by writing to the CCR register for this
+           * channel
+           */
+
+          tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1));
+        }
+        break;
+
+      case 1: /* TimerX CC2 event */
+        {
+          ccenable = ATIM_CCER_CC2E;
+          ocmode1  = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) |
+                     (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) |
+                     ATIM_CCMR1_OC2PE;
+
+          /* Set the event CC2 */
+
+          egr      = ATIM_EGR_CC2G;
+
+          /* Set the duty cycle by writing to the CCR register for this
+           * channel
+           */
+
+          tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1));
+        }
+        break;
+
+      case 2: /* TimerX CC3 event */
+        {
+          ccenable = ATIM_CCER_CC3E;
+          ocmode2  = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) |
+                     (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) |
+                     ATIM_CCMR2_OC3PE;
+
+          /* Set the event CC3 */
+
+          egr      = ATIM_EGR_CC3G;
+
+          /* Set the duty cycle by writing to the CCR register for this
+           * channel
+           */
+
+          tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1));
+        }
+        break;
+
+      case 3: /* TimerX CC4 event */
+        {
+          ccenable = ATIM_CCER_CC4E;
+          ocmode2  = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) |
+                     (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) |
+                     ATIM_CCMR2_OC4PE;
+
+          /* Set the event CC4 */
+
+          egr      = ATIM_EGR_CC4G;
+
+          /* Set the duty cycle by writing to the CCR register for this
+           * channel
+           */
+
+          tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
+        }
+        break;
+
+      case 4: /* TimerX TRGO event */
+        {
+          /* TODO: TRGO support not yet implemented */
+
+          /* Set the event TRGO */
+
+          ccenable = 0;
+          egr      = GTIM_EGR_TG;
+
+          /* Set the duty cycle by writing to the CCR register for this
+           * channel
+           */
+
+          tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
+        }
+        break;
+
+      case 5: /* TimerX TRGO2 event */
+        {
+          /* TODO: TRGO2 support not yet implemented */
+
+          /* Set the event TRGO2 */
+
+          ccenable = 0;
+          egr      = GTIM_EGR_TG;
+
+          /* Set the duty cycle by writing to the CCR register for this
+           * channel
+           */
+
+          tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
+        }
+        break;
+
+      default:
+        aerr("ERROR: No such trigger: %d\n", priv->trigger);
+        return -EINVAL;
+    }
+
+  /* Disable the Channel by resetting the CCxE Bit in the CCER register */
+
+  ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET);
+  ccer &= ~ccenable;
+  tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+
+  /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */
+
+  cr2   = tim_getreg(priv, STM32_GTIM_CR2_OFFSET);
+  ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
+  ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
+
+  /* Reset the Output Compare Mode Bits and set the select output compare
+   * mode
+   */
+
+  ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE |
+             ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE);
+  ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE |
+             ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE);
+  ccmr1 |= ocmode1;
+  ccmr2 |= ocmode2;
+
+  /* Reset the output polarity level of all channels (selects high
+   * polarity)
+   */
+
+  ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P |
+            ATIM_CCER_CC3P | ATIM_CCER_CC4P);
+
+  /* Enable the output state of the selected channel (only) */
+
+  ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E |
+            ATIM_CCER_CC3E | ATIM_CCER_CC4E);
+  ccer |= ccenable;
+
+  if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
+    {
+      /* Reset output N polarity level, output N state, output compare state,
+       * output compare N idle state.
+       */
+
+      ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP |
+                ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
+                ATIM_CCER_CC3NE | ATIM_CCER_CC3NP |
+                ATIM_CCER_CC4NP);
+
+      /* Reset the output compare and output compare N IDLE State */
+
+      cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N |
+               ATIM_CR2_OIS2 | ATIM_CR2_OIS2N |
+               ATIM_CR2_OIS3 | ATIM_CR2_OIS3N |
+               ATIM_CR2_OIS4);
+    }
+  else
+    {
+      ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP);
+    }
+
+  /* Save the modified register values */
+
+  tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2);
+  tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
+  tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2);
+  tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+  tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr);
+
+  /* Set the ARR Preload Bit */
+
+  tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
+
+  /* Enable the timer counter */
+
+  adc_timstart(priv, true);
+
+  tim_dumpregs(priv, "After starting timers");
+
+  return OK;
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -1368,4 +1917,5 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf,
   return dev;
 }
 #endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */
-#endif /* CONFIG_ADC */
+#endif /* CONFIG_ADC */
+

arch/arm/src/stm32h5/stm32_adc.h

@@ -38,6 +38,462 @@
 
 #if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
 
+/* Configuration ************************************************************/
+
+/* Timer devices may be used for different purposes.  One special purpose is
+ * to control periodic ADC sampling.  If CONFIG_STM32H5_TIMn is defined then
+ * CONFIG_STM32H5_TIMn_ADC must also be defined to indicate that timer "n"
+ * is intended to be used for that purpose. Timers 1,2,3,6 and 15 may be
+ * used on STM32H5X3, while STM32H5X6 adds support for timers 4 and 8 as
+ * well.
+ */
+
+#ifndef CONFIG_STM32H5_TIM1
+#  undef CONFIG_STM32H5_TIM1_ADC
+#  undef CONFIG_STM32H5_TIM1_ADC1
+#  undef CONFIG_STM32H5_TIM1_ADC2
+#  undef CONFIG_STM32H5_TIM1_ADC3
+#endif
+#ifndef CONFIG_STM32H5_TIM2
+#  undef CONFIG_STM32H5_TIM2_ADC
+#  undef CONFIG_STM32H5_TIM2_ADC1
+#  undef CONFIG_STM32H5_TIM2_ADC2
+#  undef CONFIG_STM32H5_TIM2_ADC3
+#endif
+#ifndef CONFIG_STM32H5_TIM3
+#  undef CONFIG_STM32H5_TIM3_ADC
+#  undef CONFIG_STM32H5_TIM3_ADC1
+#  undef CONFIG_STM32H5_TIM3_ADC2
+#  undef CONFIG_STM32H5_TIM3_ADC3
+#endif
+#ifndef CONFIG_STM32H5_TIM4
+#  undef CONFIG_STM32H5_TIM4_ADC
+#  undef CONFIG_STM32H5_TIM4_ADC1
+#  undef CONFIG_STM32H5_TIM4_ADC2
+#  undef CONFIG_STM32H5_TIM4_ADC3
+#endif
+#ifndef CONFIG_STM32H5_TIM6
+#  undef CONFIG_STM32H5_TIM6_ADC
+#  undef CONFIG_STM32H5_TIM6_ADC1
+#  undef CONFIG_STM32H5_TIM6_ADC2
+#  undef CONFIG_STM32H5_TIM6_ADC3
+#endif
+#ifndef CONFIG_STM32H5_TIM8
+#  undef CONFIG_STM32H5_TIM8_ADC
+#  undef CONFIG_STM32H5_TIM8_ADC1
+#  undef CONFIG_STM32H5_TIM8_ADC2
+#  undef CONFIG_STM32H5_TIM8_ADC3
+#endif
+#ifndef CONFIG_STM32H5_TIM15
+#  undef CONFIG_STM32H5_TIM15_ADC
+#  undef CONFIG_STM32H5_TIM15_ADC1
+#  undef CONFIG_STM32H5_TIM15_ADC2
+#  undef CONFIG_STM32H5_TIM15_ADC3
+#endif
+
+/* Timer configuration:  If a timer trigger is specified, then get
+ * information about the timer.
+ */
+
+#if defined(CONFIG_STM32H5_TIM1_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM1_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB2ENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB2ENR_TIM1EN
+#elif defined(CONFIG_STM32H5_TIM2_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM2_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB1LENR_TIM2EN
+#elif defined(CONFIG_STM32H5_TIM3_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM3_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB1LENR_TIM3EN
+#elif defined(CONFIG_STM32H5_TIM4_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM4_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB1LENR_TIM4EN
+#elif defined(CONFIG_STM32H5_TIM6_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM6_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB1LENR_TIM6EN
+#elif defined(CONFIG_STM32H5_TIM8_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM8_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB2ENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB2ENR_TIM8EN
+#elif defined(CONFIG_STM32H5_TIM15_ADC1)
+#    define ADC1_HAVE_TIMER           1
+#    define ADC1_TIMER_BASE           STM32_TIM15_BASE
+#    define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
+#    define ADC1_TIMER_RCC_ENR        STM32_RCC_APB2ENR
+#    define ADC1_TIMER_RCC_EN         RCC_APB2ENR_TIM15EN
+#else
+#    undef  ADC1_HAVE_TIMER
+#endif
+
+#ifdef ADC1_HAVE_TIMER
+#  ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY
+#    error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined"
+#  endif
+#  ifndef CONFIG_STM32H5_ADC1_TIMTRIG
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG not defined"
+#    warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H5_TIM1_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM1_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB2ENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB2ENR_TIM1EN
+#elif defined(CONFIG_STM32H5_TIM2_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM2_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB1LENR_TIM2EN
+#elif defined(CONFIG_STM32H5_TIM3_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM3_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB1LENR_TIM3EN
+#elif defined(CONFIG_STM32H5_TIM4_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM4_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB1LENR_TIM4EN
+#elif defined(CONFIG_STM32H5_TIM6_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM6_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB1LENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB1LENR_TIM6EN
+#elif defined(CONFIG_STM32H5_TIM8_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM8_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB2ENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB2ENR_TIM8EN
+#elif defined(CONFIG_STM32H5_TIM15_ADC2)
+#    define ADC2_HAVE_TIMER           1
+#    define ADC2_TIMER_BASE           STM32_TIM15_BASE
+#    define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
+#    define ADC2_TIMER_RCC_ENR        STM32_RCC_APB2ENR
+#    define ADC2_TIMER_RCC_EN         RCC_APB2ENR_TIM15EN
+#else
+#    undef  ADC2_HAVE_TIMER
+#endif
+
+#ifdef ADC2_HAVE_TIMER
+#  ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY
+#    error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined"
+#  endif
+#  ifndef CONFIG_STM32H5_ADC2_TIMTRIG
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG not defined"
+#    warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
+#  endif
+#endif
+
+#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER)
+#  define ADC_HAVE_TIMER 1
+#else
+#  undef ADC_HAVE_TIMER
+#endif
+
+/* Timer 1 */
+
+#define ADC1_EXTSEL_T1CC1      ADC_CFGR_EXTSEL_T1CC1
+#define ADC1_EXTSEL_T1CC2      ADC_CFGR_EXTSEL_T1CC2
+#define ADC1_EXTSEL_T1CC3      ADC_CFGR_EXTSEL_T1CC3
+#define ADC1_EXTSEL_T1CC4      ADC_CFGR_EXTSEL_T1CC4
+#define ADC1_EXTSEL_T1TRGO     ADC_CFGR_EXTSEL_T1TRGO
+#define ADC1_EXTSEL_T1TRGO2    ADC_CFGR_EXTSEL_T1TRGO2
+#define ADC2_EXTSEL_T1CC1      ADC_CFGR_EXTSEL_T1CC1
+#define ADC2_EXTSEL_T1CC2      ADC_CFGR_EXTSEL_T1CC2
+#define ADC2_EXTSEL_T1CC3      ADC_CFGR_EXTSEL_T1CC3
+#define ADC2_EXTSEL_T1CC4      ADC_CFGR_EXTSEL_T1CC4
+#define ADC2_EXTSEL_T1TRGO     ADC_CFGR_EXTSEL_T1TRGO
+#define ADC2_EXTSEL_T1TRGO2    ADC_CFGR_EXTSEL_T1TRGO2
+
+/* Timer 2 */
+
+#define ADC1_EXTSEL_T2CC2      ADC_CFGR_EXTSEL_T2CC2
+#define ADC1_EXTSEL_T2TRGO     ADC_CFGR_EXTSEL_T2TRGO
+#define ADC2_EXTSEL_T2CC2      ADC_CFGR_EXTSEL_T2CC2
+#define ADC2_EXTSEL_T2TRGO     ADC_CFGR_EXTSEL_T2TRGO
+
+/* Timer 3 */
+
+#define ADC1_EXTSEL_T3CC4      ADC_CFGR_EXTSEL_T3CC4
+#define ADC1_EXTSEL_T3TRGO     ADC_CFGR_EXTSEL_T3TRGO
+#define ADC2_EXTSEL_T3CC4      ADC_CFGR_EXTSEL_T3CC4
+#define ADC2_EXTSEL_T3TRGO     ADC_CFGR_EXTSEL_T3TRGO
+
+/* Timer 4 */
+
+#define ADC1_EXTSEL_T4CC4      ADC_CFGR_EXTSEL_T4CC4
+#define ADC1_EXTSEL_T4TRGO     ADC_CFGR_EXTSEL_T4TRGO
+#define ADC2_EXTSEL_T4CC4      ADC_CFGR_EXTSEL_T4CC4
+#define ADC2_EXTSEL_T4TRGO     ADC_CFGR_EXTSEL_T4TRGO
+
+/* Timer 6 */
+
+#define ADC1_EXTSEL_T6TRGO     ADC_CFGR_EXTSEL_T6TRGO
+#define ADC2_EXTSEL_T6TRGO     ADC_CFGR_EXTSEL_T6TRGO
+
+/* Timer 8 */
+
+#define ADC1_EXTSEL_T8TRGO     ADC_CFGR_EXTSEL_T8TRGO
+#define ADC1_EXTSEL_T8TRGO2    ADC_CFGR_EXTSEL_T8TRGO2
+#define ADC2_EXTSEL_T8TRGO     ADC_CFGR_EXTSEL_T8TRGO
+#define ADC2_EXTSEL_T8TRGO2    ADC_CFGR_EXTSEL_T8TRGO2
+
+/* Timer 15 */
+
+#define ADC1_EXTSEL_T15TRGO    ADC_CFGR_EXTSEL_T15TRGO
+#define ADC2_EXTSEL_T15TRGO    ADC_CFGR_EXTSEL_T15TRGO
+
+#if defined(CONFIG_STM32H5_TIM1_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM2_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM3_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM4_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM6_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM8_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM15_ADC1)
+#  if CONFIG_STM32H5_ADC1_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
+#    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO
+#  elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
+#  else
+#    error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)"
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H5_TIM1_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM2_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM3_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM4_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM6_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM8_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)"
+#  endif
+#elif defined(CONFIG_STM32H5_TIM15_ADC2)
+#  if CONFIG_STM32H5_ADC2_TIMTRIG == 0
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
+#    define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO
+#  elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
+#  else
+#    error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)"
+#  endif
+#endif
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/

arch/arm64/src/imx9/imx9_lpi2c.c

@@ -1122,7 +1122,7 @@ static void imx9_lpi2c_setclock(struct imx9_lpi2c_priv_s *priv,
           imx9_get_rootclock(priv->config->clk_root, &src_freq);
 
           /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
-           *   (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale)
+           *   (CLKLO + 1 + CLKHI + 1 + ALIGN_DOWN((2 + FILTSCL)/2^prescale)
            *
            * Assume  CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2
            */

arch/risc-v/src/common/Toolchain.defs

@@ -433,7 +433,12 @@ LDMODULEFLAGS = -r -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld)
 CELFFLAGS = $(CFLAGS) -fvisibility=hidden
 CXXELFFLAGS = $(CXXFLAGS) -fvisibility=hidden
 
-LDELFFLAGS = -r -e main
+LDELFFLAGS = -e main
+
+ifeq ($(CONFIG_BINFMT_ELF_RELOCATABLE),y)
+  LDELFFLAGS += -r
+endif
+
 ifeq ($(CONFIG_ARCH_RV32),y)
   LDELFFLAGS += --oformat elf32-littleriscv
 else

arch/sim/src/cmake/Toolchain.cmake

@@ -200,3 +200,7 @@ else()
   add_link_options(-Wl,--gc-sections)
   add_link_options(-Wl,-Ttext-segment=0x40000000)
 endif()
+
+if(CONFIG_HOST_LINUX)
+  add_link_options(-Wl,-z,noexecstack)
+endif()

arch/x86/src/common/Toolchain.defs

@@ -87,3 +87,4 @@ CXXELFFLAGS = $(CXXFLAGS) -fvisibility=hidden
 
 LDELFFLAGS = -r -e main
 LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)libs$(DELIM)libc$(DELIM)modlib$(DELIM)gnu-elf.ld)
+EXEEXT = .elf

arch/x86/src/i486/Toolchain.defs

@@ -0,0 +1,21 @@
+############################################################################
+# arch/x86/src/i486/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/arch/x86_64/src/common/Toolchain.defs

binfmt/binfmt_copyactions.c

@@ -31,18 +31,13 @@
 #include <errno.h>
 
 #include <nuttx/kmalloc.h>
+#include <nuttx/nuttx.h>
 #include <nuttx/binfmt/binfmt.h>
 
 #include "binfmt.h"
 
 #if defined(CONFIG_ARCH_ADDRENV) && defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_BINFMT_DISABLE)
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define ROUNDUP(x, y)     (((x) + (y) - 1) / (y) * (y))
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -98,8 +93,8 @@ int binfmt_copyactions(FAR const posix_spawn_file_actions_t **copy,
 
           case SPAWN_FILE_ACTION_OPEN:
             open = (FAR struct spawn_open_file_action_s *)entry;
-            size += ROUNDUP(SIZEOF_OPEN_FILE_ACTION_S(strlen(open->path)),
-                            sizeof(FAR void *));
+            size += ALIGN_UP(SIZEOF_OPEN_FILE_ACTION_S(strlen(open->path)),
+                             sizeof(FAR void *));
             break;
 
           default:
@@ -155,8 +150,8 @@ int binfmt_copyactions(FAR const posix_spawn_file_actions_t **copy,
             strcpy(open->path, tmp->path);
 
             buffer = (FAR char *)buffer +
-                     ROUNDUP(SIZEOF_OPEN_FILE_ACTION_S(strlen(tmp->path)),
-                             sizeof(FAR void *));
+                     ALIGN_UP(SIZEOF_OPEN_FILE_ACTION_S(strlen(tmp->path)),
+                              sizeof(FAR void *));
             break;
 
           default:

boards/x86/qemu/qemu-i486/scripts/Make.defs

@@ -22,47 +22,6 @@
 
 include $(TOPDIR)/.config
 include $(TOPDIR)/tools/Config.mk
-
-ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
-  ARCHOPTIMIZATION = -g
-endif
-
-ifneq ($(CONFIG_DEBUG_NOOPT),y)
-  ARCHOPTIMIZATION += -O2
-endif
+include $(TOPDIR)/arch/x86/src/i486/Toolchain.defs
 
 ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)qemu.ld
-
-ARCHCPUFLAGS = -march=i486 -mtune=i486 -fno-stack-protector
-ARCHPICFLAGS = -fpic
-ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
-
-# Check if building a 32-bit target with a 64-bit toolchain
-
-ifeq ($(CONFIG_ARCH_X86_M32),y)
-ARCHCPUFLAGS += -m32
-LDFLAGS += -m elf_i386
-endif
-
-# We have to use a cross-development toolchain under Cygwin because the native
-# Cygwin toolchains don't generate ELF binaries.
-
-ifeq ($(CONFIG_WINDOWS_CYGWIN),y)
-CROSSDEV = i486-nuttx-elf-
-endif
-
-CC = $(CROSSDEV)gcc
-CPP = $(CROSSDEV)gcc -E
-LD = $(CROSSDEV)ld
-STRIP = $(CROSSDEV)strip --strip-unneeded
-AR = $(CROSSDEV)ar rcs
-NM = $(CROSSDEV)nm
-OBJCOPY = $(CROSSDEV)objcopy
-OBJDUMP = $(CROSSDEV)objdump
-
-CFLAGS := $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
-CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
-AFLAGS := $(CFLAGS) -D__ASSEMBLY__
-
-EXEEXT = .elf
-

drivers/timers/Kconfig

@@ -439,6 +439,14 @@ menuconfig WATCHDOG_AUTOMONITOR
 
 if WATCHDOG_AUTOMONITOR
 
+config WATCHDOG_TIMEOUT_NOTIFIER
+	bool "Enable watchdog timeout notifier"
+	default n
+	---help---
+		The watchdog timeout notifier chain mechanism supports users registering
+		custom callback functions, which will be called when the watchdog timer
+		managed by Auto-monitor times out.
+
 choice
 	prompt "Auto-monitor keepalive by"
 	default WATCHDOG_AUTOMONITOR_BY_WDOG

drivers/timers/watchdog.c

@@ -71,6 +71,20 @@
 #  endif
 #endif
 
+#if defined(CONFIG_WATCHDOG_AUTOMONITOR_BY_ONESHOT)
+#  define WATCHDOG_NOTIFIER_ACTION WATCHDOG_KEEPALIVE_BY_ONESHOT
+#elif defined(CONFIG_WATCHDOG_AUTOMONITOR_BY_TIMER)
+#  define WATCHDOG_NOTIFIER_ACTION WATCHDOG_KEEPALIVE_BY_TIMER
+#elif defined(CONFIG_WATCHDOG_AUTOMONITOR_BY_WDOG)
+#  define WATCHDOG_NOTIFIER_ACTION WATCHDOG_KEEPALIVE_BY_WDOG
+#elif defined(CONFIG_WATCHDOG_AUTOMONITOR_BY_WORKER)
+#  define WATCHDOG_NOTIFIER_ACTION WATCHDOG_KEEPALIVE_BY_WORKER
+#elif defined(CONFIG_WATCHDOG_AUTOMONITOR_BY_CAPTURE)
+#  define WATCHDOG_NOTIFIER_ACTION WATCHDOG_KEEPALIVE_BY_CAPTURE
+#elif defined(CONFIG_WATCHDOG_AUTOMONITOR_BY_IDLE)
+#  define WATCHDOG_NOTIFIER_ACTION WATCHDOG_KEEPALIVE_BY_IDLE
+#endif
+
 /****************************************************************************
  * Private Type Definitions
  ****************************************************************************/
@@ -135,6 +149,10 @@ static const struct file_operations g_wdogops =
   wdog_ioctl, /* ioctl */
 };
 
+#ifdef CONFIG_WATCHDOG_TIMEOUT_NOTIFIER
+static ATOMIC_NOTIFIER_HEAD(g_watchdog_notifier_list);
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -699,6 +717,55 @@ static int wdog_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Public Functions
  ****************************************************************************/
 
+#ifdef CONFIG_WATCHDOG_TIMEOUT_NOTIFIER
+/****************************************************************************
+ * Name:  watchdog_notifier_chain_register
+ *
+ * Description:
+ *   Add notifier to the watchdog notifier chain
+ *
+ * Input Parameters:
+ *    nb - New entry in notifier chain
+ *
+ ****************************************************************************/
+
+void watchdog_notifier_chain_register(FAR struct notifier_block *nb)
+{
+  atomic_notifier_chain_register(&g_watchdog_notifier_list, nb);
+}
+
+/****************************************************************************
+ * Name:  watchdog_notifier_chain_unregister
+ *
+ * Description:
+ *   Remove notifier from the watchdog notifier chain
+ *
+ * Input Parameters:
+ *    nb - Entry to remove from notifier chain
+ *
+ ****************************************************************************/
+
+void watchdog_notifier_chain_unregister(FAR struct notifier_block *nb)
+{
+  atomic_notifier_chain_unregister(&g_watchdog_notifier_list, nb);
+}
+
+/****************************************************************************
+ * Name: watchdog_automonitor_timeout
+ *
+ * Description:
+ *   This function can be called in the watchdog timeout interrupt handler.
+ *   If so, callbacks on the watchdog timer notify chain are called when the
+ *   watchdog timer times out.
+ *
+ ****************************************************************************/
+
+void watchdog_automonitor_timeout(void)
+{
+  atomic_notifier_call_chain(&g_watchdog_notifier_list, action, data);
+}
+#endif /* CONFIG_WATCHDOG_TIMEOUT_NOTIFIER */
+
 /****************************************************************************
  * Name: watchdog_register
  *

drivers/vhost/vhost-rng.c

@@ -30,6 +30,7 @@
 #include <stdlib.h>
 
 #include <nuttx/kmalloc.h>
+#include <nuttx/spinlock.h>
 #include <nuttx/vhost/vhost.h>
 #include <nuttx/wqueue.h>
 
@@ -151,7 +152,7 @@ static int vhost_rng_probe(FAR struct vhost_device *hdev)
 
   vqnames[0]  = "virtio_rng";
   callback[0] = vhost_rng_handler;
-  ret = vhost_create_virtqueues(hdev, 0, 1, vqnames, callback);
+  ret = vhost_create_virtqueues(hdev, 0, 1, vqnames, callback, NULL);
   if (ret < 0)
     {
       vhosterr("virtio_device_create_virtqueue failed, ret=%d\n", ret);

drivers/vhost/vhost.c

@@ -83,8 +83,15 @@ static struct vhost_bus_s g_vhost_bus =
 
 static bool vhost_status_driver_ok(FAR struct vhost_device *hdev)
 {
-  uint8_t status = vhost_get_status(hdev);
   bool driver_ok = false;
+  uint8_t status;
+  int ret;
+
+  ret = vhost_get_status(hdev, &status);
+  if (ret)
+    {
+      return driver_ok;
+    }
 
   /* Busy wait until the remote is ready */
 

include/nuttx/addrenv.h

@@ -29,6 +29,8 @@
 
 #include <nuttx/config.h>
 
+#ifndef __ASSEMBLY__
+
 #ifdef CONFIG_BUILD_KERNEL
 #  include <signal.h>
 #endif
@@ -40,6 +42,8 @@
 
 #include <arch/arch.h>
 
+#endif /* __ASSEMBLY__ */
+
 #ifdef CONFIG_ARCH_ADDRENV
 
 /****************************************************************************
@@ -241,6 +245,9 @@
      (CONFIG_ARCH_PGPOOL_VBASE + CONFIG_ARCH_PGPOOL_SIZE)
 
 #endif
+
+#ifndef __ASSEMBLY__
+
 /****************************************************************************
  * Public Type Definitions
  ****************************************************************************/
@@ -251,8 +258,6 @@ struct tcb_s;                  /* Forward reference to TCB */
  * Public Types
  ****************************************************************************/
 
-#ifndef __ASSEMBLY__
-
 struct addrenv_s
 {
   struct arch_addrenv_s addrenv; /* The address environment page directory  */

include/nuttx/nuttx.h

@@ -48,7 +48,7 @@
 #endif
 
 #ifndef ALIGN_UP
-#  define ALIGN_UP(x,a)        (((x) + ((a) - 1)) & ~((a) - 1))
+#  define ALIGN_UP(x,a)        ((((x) + (a) - 1) / (a)) * (a))
 #endif
 
 #ifndef ALIGN_UP_MASK
@@ -56,7 +56,7 @@
 #endif
 
 #ifndef ALIGN_DOWN
-#  define ALIGN_DOWN(x,a)      ((x) & (~((a) - 1)))
+#  define ALIGN_DOWN(x,a)      (((x) / (a)) * (a))
 #endif
 
 #ifndef ALIGN_DOWN_MASK

include/nuttx/timers/watchdog.h

@@ -31,6 +31,7 @@
 #include <nuttx/compiler.h>
 #include <nuttx/irq.h>
 #include <nuttx/fs/ioctl.h>
+#include <nuttx/notifier.h>
 
 #ifdef CONFIG_WATCHDOG
 
@@ -88,6 +89,35 @@
 #define WDFLAGS_CAPTURE  (1 << 2) /* 1=Call the user function when the
                                    *   watchdog timer expires */
 
+/* Keepalive Actions ********************************************************/
+
+/* According to the keepalive action specified by the Auto-monitor, callback
+ * functions registered on the watchdog notifier chain may take corresponding
+ * actions.
+ *
+ * These are detected and handled by the "upper half" watchdog timer driver.
+ *
+ * WATCHDOG_KEEPALIVE_BY_ONESHOT      - The watchdog timer is keepalive by
+ *                                      oneshot timer.
+ * WATCHDOG_KEEPALIVE_BY_TIMER        - The watchdog timer is keepalive by
+ *                                      timer.
+ * WATCHDOG_KEEPALIVE_BY_WDOG         - The watchdog timer is keepalive by
+ *                                      wdog.
+ * WATCHDOG_KEEPALIVE_BY_WORKER       - The watchdog timer is keepalive by
+ *                                      worker queue.
+ * WATCHDOG_KEEPALIVE_BY_CAPTURE      - The watchdog timer is keepalive by
+ *                                      capture.
+ * WATCHDOG_KEEPALIVE_BY_IDLE         - The watchdog timer is keepalive by
+ *                                      idle task.
+ */
+
+#define WATCHDOG_KEEPALIVE_BY_ONESHOT 0
+#define WATCHDOG_KEEPALIVE_BY_TIMER   1
+#define WATCHDOG_KEEPALIVE_BY_WDOG    2
+#define WATCHDOG_KEEPALIVE_BY_WORKER  3
+#define WATCHDOG_KEEPALIVE_BY_CAPTURE 4
+#define WATCHDOG_KEEPALIVE_BY_IDLE    5
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -197,6 +227,47 @@ extern "C"
 #define EXTERN extern
 #endif
 
+#ifdef CONFIG_WATCHDOG_TIMEOUT_NOTIFIER
+/****************************************************************************
+ * Name:  watchdog_notifier_chain_register
+ *
+ * Description:
+ *   Add notifier to the watchdog notifier chain
+ *
+ * Input Parameters:
+ *    nb - New entry in notifier chain
+ *
+ ****************************************************************************/
+
+void watchdog_notifier_chain_register(FAR struct notifier_block *nb);
+
+/****************************************************************************
+ * Name:  watchdog_notifier_chain_unregister
+ *
+ * Description:
+ *   Remove notifier from the watchdog notifier chain
+ *
+ * Input Parameters:
+ *    nb - Entry to remove from notifier chain
+ *
+ ****************************************************************************/
+
+void watchdog_notifier_chain_unregister(FAR struct notifier_block *nb);
+
+/****************************************************************************
+ * Name: watchdog_automonitor_timeout
+ *
+ * Description:
+ *   This function can be called in the watchdog timeout interrupt handler.
+ *   If so, callbacks on the watchdog timer notify chain are called when the
+ *   watchdog timer times out.
+ *
+ ****************************************************************************/
+
+void watchdog_automonitor_timeout(void);
+
+#endif /* CONFIG_WATCHDOG_TIMEOUT_NOTIFIER */
+
 /****************************************************************************
  * Name: watchdog_register
  *

libs/libbuiltin/libgcc/profile.c

@@ -35,6 +35,7 @@
 #include <nuttx/init.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/fs/fs.h>
+#include <nuttx/nuttx.h>
 #include <nuttx/spinlock.h>
 
 /****************************************************************************
@@ -112,11 +113,6 @@
 
 #define MAXARCS         (1 << 20)
 
-/* General rounding functions. */
-
-#define ROUNDDOWN(x, y) (((x) / (y)) * (y))
-#define ROUNDUP(x, y)   ((((x) + (y) - 1) / (y)) * (y))
-
 /* See profil(2) where this is described (incorrectly) */
 
 #define SCALE_1_TO_1    0x10000
@@ -288,13 +284,13 @@ void moncontrol(int mode)
 
   if (mode)
     {
-      uintptr_t lowpc = ROUNDDOWN((uintptr_t)&_stext,
+      uintptr_t lowpc = ALIGN_DOWN((uintptr_t)&_stext,
                                    HISTFRACTION * sizeof(HISTCOUNTER));
-      uintptr_t highpc = ROUNDUP((uintptr_t)&_etext,
-                                 HISTFRACTION * sizeof(HISTCOUNTER));
+      uintptr_t highpc = ALIGN_UP((uintptr_t)&_etext,
+                                  HISTFRACTION * sizeof(HISTCOUNTER));
       size_t textsize = highpc - lowpc;
-      size_t kcountsize = ROUNDUP(textsize / HISTFRACTION,
-                                  sizeof(*p->kcount));
+      size_t kcountsize = ALIGN_UP(textsize / HISTFRACTION,
+                                   sizeof(*p->kcount));
       int scale = kcountsize >= textsize ? SCALE_1_TO_1 :
                   (float)kcountsize / textsize * SCALE_1_TO_1;
       FAR unsigned short *kcount = kmm_zalloc(kcountsize);
@@ -370,10 +366,10 @@ void monstartup(unsigned long lowpc, unsigned long highpc)
    * so the rest of the scaling (here and in gprof) stays in ints.
    */
 
-  lowpc = ROUNDDOWN(lowpc, HISTFRACTION * sizeof(HISTCOUNTER));
-  highpc = ROUNDUP(highpc, HISTFRACTION * sizeof(HISTCOUNTER));
+  lowpc = ALIGN_DOWN(lowpc, HISTFRACTION * sizeof(HISTCOUNTER));
+  highpc = ALIGN_UP(highpc, HISTFRACTION * sizeof(HISTCOUNTER));
   textsize = highpc - lowpc;
-  fromssize = ROUNDUP(textsize / HASHFRACTION, sizeof(*p->froms));
+  fromssize = ALIGN_UP(textsize / HASHFRACTION, sizeof(*p->froms));
   tolimit = textsize * ARCDENSITY / 100;
 
   if (tolimit < MINARCS)

libs/libc/.gitignore

@@ -1,2 +1,3 @@
 /exec_symtab.c
 /modlib_symtab.c
+modlib/gnu-elf.ld

libs/libc/Makefile

@@ -183,6 +183,10 @@ context:: bin kbin
 ifeq ($(CONFIG_LIBC_ZONEINFO_ROMFS),y)
 	$(Q) $(MAKE) -C zoneinfo context BIN=$(BIN)
 endif
+ifeq ($(CONFIG_LIBC_MODLIB),y)
+	$(Q) $(MAKE) -C modlib context
+endif
+
 
 # Dependencies
 
@@ -210,6 +214,7 @@ depend:: .depend
 
 clean::
 	$(Q) $(MAKE) -C zoneinfo clean BIN=$(BIN)
+	$(Q) $(MAKE) -C modlib clean
 	$(call DELFILE, $(BIN))
 	$(call DELFILE, $(KBIN))
 	$(call CLEAN)
@@ -218,6 +223,7 @@ clean::
 
 distclean:: clean
 	$(Q) $(MAKE) -C zoneinfo distclean BIN=$(BIN)
+	$(Q) $(MAKE) -C modlib distclean
 	$(call DELFILE, exec_symtab.c)
 	$(call DELFILE, .depend)
 	$(call DELDIR, bin)

libs/libc/modlib/Makefile

@@ -0,0 +1,40 @@
+############################################################################
+# libs/libc/modlib/Makefile
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+
+# Generate gnu-elf.ld from gnu-elf.ld.in
+
+gnu-elf.ld: gnu-elf.ld.in
+	$(call PREPROCESS, $<, $@)
+
+# Create initial context
+
+context: gnu-elf.ld
+
+.PHONY: context clean distclean
+
+clean:
+	$(call CLEAN)
+
+distclean: clean
+	$(call DELFILE, gnu-elf.ld)

libs/libc/modlib/gnu-elf.ld.in

@@ -1,5 +1,5 @@
 /****************************************************************************
- * libs/libc/modlib/gnu-elf.ld
+ * libs/libc/modlib/gnu-elf.ld.in
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -18,9 +18,23 @@
  *
  ****************************************************************************/
 
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_BINFMT_ELF_EXECUTABLE)
+#  define __ASSEMBLY__
+#  include <nuttx/addrenv.h>
+
+#  define TEXT CONFIG_ARCH_TEXT_VBASE
+#  define DATA CONFIG_ARCH_DATA_VBASE + ARCH_DATA_RESERVE_SIZE
+#else
+#  define TEXT 0x0
+#  define DATA
+#endif
+
 SECTIONS
 {
-  .text 0x00000000 :
+  .text TEXT :
     {
       _stext = . ;
       *(.text)
@@ -58,7 +72,7 @@ SECTIONS
       _erodata = . ;
     }
 
-  .data :
+  .data DATA :
     {
       _sdata = . ;
       *(.data)

mm/iob/iob.h

@@ -41,8 +41,6 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define ROUNDUP(x, y)            (((x) + (y) - 1) / (y) * (y))
-
 #if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_IOB_DEBUG)
 #  define ioberr                 _err
 #  define iobwarn                _warn

mm/iob/iob_alloc.c

@@ -35,6 +35,7 @@
 #ifdef CONFIG_IOB_ALLOC
 #  include <nuttx/kmalloc.h>
 #endif
+#include <nuttx/nuttx.h>
 #include <nuttx/mm/iob.h>
 
 #include "iob.h"
@@ -333,7 +334,7 @@ FAR struct iob_s *iob_alloc_dynamic(uint16_t size)
   FAR struct iob_s *iob;
   size_t alignsize;
 
-  alignsize = ROUNDUP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT) + size;
+  alignsize = ALIGN_UP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT) + size;
 
   iob = kmm_memalign(CONFIG_IOB_ALIGNMENT, alignsize);
   if (iob)
@@ -344,8 +345,8 @@ FAR struct iob_s *iob_alloc_dynamic(uint16_t size)
       iob->io_bufsize = size;             /* Total length of the iob buffer */
       iob->io_pktlen  = 0;                /* Total length of the packet */
       iob->io_free    = iob_free_dynamic; /* Customer free callback */
-      iob->io_data    = (FAR uint8_t *)ROUNDUP((uintptr_t)(iob + 1),
-                                               CONFIG_IOB_ALIGNMENT);
+      iob->io_data    = (FAR uint8_t *)ALIGN_UP((uintptr_t)(iob + 1),
+                                                CONFIG_IOB_ALIGNMENT);
     }
 
   return iob;

mm/iob/iob_initialize.c

@@ -28,6 +28,7 @@
 
 #include <stdbool.h>
 
+#include <nuttx/nuttx.h>
 #include <nuttx/mm/iob.h>
 
 #include "iob.h"
@@ -39,10 +40,10 @@
 /* Fix the I/O Buffer size with specified alignment size */
 
 #ifdef CONFIG_IOB_ALLOC
-#  define IOB_ALIGN_SIZE  ROUNDUP(sizeof(struct iob_s) + CONFIG_IOB_BUFSIZE, \
-                                  CONFIG_IOB_ALIGNMENT)
+#  define IOB_ALIGN_SIZE  ALIGN_UP(sizeof(struct iob_s) + CONFIG_IOB_BUFSIZE, \
+                                   CONFIG_IOB_ALIGNMENT)
 #else
-#  define IOB_ALIGN_SIZE  ROUNDUP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT)
+#  define IOB_ALIGN_SIZE  ALIGN_UP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT)
 #endif
 
 #define IOB_BUFFER_SIZE   (IOB_ALIGN_SIZE * CONFIG_IOB_NBUFFERS + \
@@ -137,8 +138,8 @@ void iob_initialize(void)
    * aligned to the CONFIG_IOB_ALIGNMENT memory boundary
    */
 
-  buf = ROUNDUP((uintptr_t)g_iob_buffer + offsetof(struct iob_s, io_data),
-                CONFIG_IOB_ALIGNMENT) - offsetof(struct iob_s, io_data);
+  buf = ALIGN_UP((uintptr_t)g_iob_buffer + offsetof(struct iob_s, io_data),
+                 CONFIG_IOB_ALIGNMENT) - offsetof(struct iob_s, io_data);
 
   /* Get I/O buffer instance from the start address and add each I/O buffer
    * to the free list

mm/mempool/mempool.c

@@ -397,16 +397,17 @@ retry:
 
   pool->nalloc++;
   spin_unlock_irqrestore(&pool->lock, flags);
-  blk = kasan_unpoison(blk, pool->blocksize);
-#ifdef CONFIG_MM_FILL_ALLOCATIONS
-  memset(blk, MM_ALLOC_MAGIC, pool->blocksize);
-#endif
 
 #if CONFIG_MM_BACKTRACE >= 0
   mempool_add_backtrace(pool, (FAR struct mempool_backtrace_s *)
                               ((FAR char *)blk + pool->blocksize));
 #endif
 
+  blk = kasan_unpoison(blk, pool->blocksize);
+#ifdef CONFIG_MM_FILL_ALLOCATIONS
+  memset(blk, MM_ALLOC_MAGIC, pool->blocksize);
+#endif
+
   return blk;
 }
 

mm/mm_heap/mm.h

@@ -282,6 +282,8 @@ typedef CODE void (*mm_node_handler_t)(FAR struct mm_allocnode_s *node,
 
 int mm_lock(FAR struct mm_heap_s *heap);
 void mm_unlock(FAR struct mm_heap_s *heap);
+irqstate_t mm_lock_irq(FAR struct mm_heap_s *heap);
+void mm_unlock_irq(FAR struct mm_heap_s *heap, irqstate_t state);
 
 /* Functions contained in mm_shrinkchunk.c **********************************/
 

mm/mm_heap/mm_free.c

@@ -49,7 +49,7 @@ static void add_delaylist(FAR struct mm_heap_s *heap, FAR void *mem)
 
   /* Delay the deallocation until a more appropriate time. */
 
-  flags = up_irq_save();
+  flags = mm_lock_irq(heap);
 
 #  ifdef CONFIG_DEBUG_ASSERTIONS
   FAR struct mm_freenode_s *node;
@@ -65,7 +65,7 @@ static void add_delaylist(FAR struct mm_heap_s *heap, FAR void *mem)
   heap->mm_delaycount[this_cpu()]++;
 #endif
 
-  up_irq_restore(flags);
+  mm_unlock_irq(heap, flags);
 #endif
 }
 

mm/mm_heap/mm_lock.c

@@ -117,3 +117,31 @@ void mm_unlock(FAR struct mm_heap_s *heap)
 
   DEBUGVERIFY(nxmutex_unlock(&heap->mm_lock));
 }
+
+/****************************************************************************
+ * Name: mm_lock_irq
+ *
+ * Description:
+ *   Locking by pausing interruption
+ *
+ ****************************************************************************/
+
+irqstate_t mm_lock_irq(FAR struct mm_heap_s *heap)
+{
+  UNUSED(heap);
+  return up_irq_save();
+}
+
+/****************************************************************************
+ * Name: mm_unlock_irq
+ *
+ * Description:
+ *   Release the lock by resuming the interrupt
+ *
+ ****************************************************************************/
+
+void mm_unlock_irq(FAR struct mm_heap_s *heap, irqstate_t state)
+{
+  UNUSED(heap);
+  up_irq_restore(state);
+}

mm/mm_heap/mm_malloc.c

@@ -65,7 +65,7 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force)
 
   /* Move the delay list to local */
 
-  flags = up_irq_save();
+  flags = mm_lock_irq(heap);
 
   tmp = heap->mm_delaylist[this_cpu()];
 
@@ -74,7 +74,7 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force)
       (!force &&
         heap->mm_delaycount[this_cpu()] < CONFIG_MM_FREE_DELAYCOUNT_MAX))
     {
-      up_irq_restore(flags);
+      mm_unlock_irq(heap, flags);
       return false;
     }
 
@@ -83,7 +83,7 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force)
 
   heap->mm_delaylist[this_cpu()] = NULL;
 
-  up_irq_restore(flags);
+  mm_unlock_irq(heap, flags);
 
   /* Test if the delayed is empty */
 

mm/tlsf/mm_tlsf.c

@@ -181,6 +181,34 @@ static void mm_delayfree(struct mm_heap_s *heap, void *mem, bool delay);
  * Private Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: mm_lock_irq
+ *
+ * Description:
+ *   Locking by pausing interruption
+ *
+ ****************************************************************************/
+
+static irqstate_t mm_lock_irq(FAR struct mm_heap_s *heap)
+{
+  UNUSED(heap);
+  return up_irq_save();
+}
+
+/****************************************************************************
+ * Name: mm_unlock_irq
+ *
+ * Description:
+ *   Release the lock by resuming the interrupt
+ *
+ ****************************************************************************/
+
+static void mm_unlock_irq(FAR struct mm_heap_s *heap, irqstate_t state)
+{
+  UNUSED(heap);
+  up_irq_restore(state);
+}
+
 static void memdump_allocnode(FAR void *ptr, size_t size)
 {
 #if CONFIG_MM_BACKTRACE < 0
@@ -301,7 +329,7 @@ static void add_delaylist(FAR struct mm_heap_s *heap, FAR void *mem)
 
   /* Delay the deallocation until a more appropriate time. */
 
-  flags = up_irq_save();
+  flags = mm_lock_irq(heap);
 
   tmp->flink = heap->mm_delaylist[this_cpu()];
   heap->mm_delaylist[this_cpu()] = tmp;
@@ -310,7 +338,7 @@ static void add_delaylist(FAR struct mm_heap_s *heap, FAR void *mem)
   heap->mm_delaycount[this_cpu()]++;
 #endif
 
-  up_irq_restore(flags);
+  mm_unlock_irq(heap, flags);
 #endif
 }
 
@@ -327,7 +355,7 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force)
 
   /* Move the delay list to local */
 
-  flags = up_irq_save();
+  flags = mm_lock_irq(heap);
 
   tmp = heap->mm_delaylist[this_cpu()];
 
@@ -336,7 +364,7 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force)
       (!force &&
         heap->mm_delaycount[this_cpu()] < CONFIG_MM_FREE_DELAYCOUNT_MAX))
     {
-      up_irq_restore(flags);
+      mm_unlock_irq(heap, flags);
       return false;
     }
 
@@ -345,7 +373,7 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force)
 
   heap->mm_delaylist[this_cpu()] = NULL;
 
-  up_irq_restore(flags);
+  mm_unlock_irq(heap, flags);
 
   /* Test if the delayed is empty */
 

sched/clock/clock_timekeeping.c

@@ -53,6 +53,7 @@ static struct timespec g_clock_wall_time;
 static uint64_t        g_clock_last_counter;
 static uint64_t        g_clock_mask;
 static long            g_clock_adjust;
+static spinlock_t      g_clock_lock = SP_UNLOCKED;
 
 /****************************************************************************
  * Private Functions
@@ -72,7 +73,7 @@ static int clock_get_current_time(FAR struct timespec *ts,
   time_t sec;
   int ret;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_clock_lock);
 
   ret = up_timer_gettick(&counter);
   if (ret < 0)
@@ -96,7 +97,7 @@ static int clock_get_current_time(FAR struct timespec *ts,
   ts->tv_sec = base->tv_sec + sec;
 
 errout_in_critical_section:
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_clock_lock, flags);
   return ret;
 }
 
@@ -123,7 +124,7 @@ int clock_timekeeping_set_wall_time(FAR const struct timespec *ts)
   uint64_t counter;
   int ret;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_clock_lock);
 
   ret = up_timer_gettick(&counter);
   if (ret < 0)
@@ -137,7 +138,7 @@ int clock_timekeeping_set_wall_time(FAR const struct timespec *ts)
   g_clock_last_counter = counter;
 
 errout_in_critical_section:
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_clock_lock, flags);
   return ret;
 }
 
@@ -188,7 +189,7 @@ int adjtime(FAR const struct timeval *delta, FAR struct timeval *olddelta)
       return -1;
     }
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_clock_lock);
 
   adjust_usec = delta->tv_sec * USEC_PER_SEC + delta->tv_usec;
 
@@ -199,7 +200,7 @@ int adjtime(FAR const struct timeval *delta, FAR struct timeval *olddelta)
 
   g_clock_adjust = adjust_usec;
 
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_clock_lock, flags);
 
   return OK;
 }
@@ -217,7 +218,7 @@ void clock_update_wall_time(void)
   time_t sec;
   int ret;
 
-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_clock_lock);
 
   ret = up_timer_gettick(&counter);
   if (ret < 0)
@@ -271,7 +272,7 @@ void clock_update_wall_time(void)
   g_clock_last_counter = counter;
 
 errout_in_critical_section:
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_clock_lock, flags);
 }
 
 /****************************************************************************
@@ -280,6 +281,9 @@ errout_in_critical_section:
 
 void clock_inittimekeeping(FAR const struct timespec *tp)
 {
+  irqstate_t flags;
+
+  flags = spin_lock_irqsave(&g_clock_lock);
   up_timer_getmask(&g_clock_mask);
 
   if (tp)
@@ -292,6 +296,7 @@ void clock_inittimekeeping(FAR const struct timespec *tp)
     }
 
   up_timer_gettick(&g_clock_last_counter);
+  spin_unlock_irqrestore(&g_clock_lock, flags);
 }
 
 #endif /* CONFIG_CLOCK_TIMEKEEPING */

sched/misc/coredump.c

@@ -32,6 +32,7 @@
 
 #include <nuttx/coredump.h>
 #include <nuttx/elf.h>
+#include <nuttx/nuttx.h>
 #include <nuttx/sched.h>
 
 #include "sched/sched.h"
@@ -54,9 +55,6 @@
 
 #define PROGRAM_ALIGNMENT 64
 
-#define ROUNDUP(x, y)     ((x + (y - 1)) / (y)) * (y)
-#define ROUNDDOWN(x ,y)   (((x) / (y)) * (y))
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -166,8 +164,8 @@ static int elf_emit(FAR struct elf_dumpinfo_s *cinfo,
 
 static int elf_emit_align(FAR struct elf_dumpinfo_s *cinfo)
 {
-  off_t align = ROUNDUP(cinfo->stream->nput,
-                        ELF_PAGESIZE) - cinfo->stream->nput;
+  off_t align = ALIGN_UP(cinfo->stream->nput,
+                         ELF_PAGESIZE) - cinfo->stream->nput;
   unsigned char null[256];
   off_t total = align;
   off_t ret = 0;
@@ -258,10 +256,10 @@ static int elf_get_note_size(int stksegs)
 {
   int total;
 
-  total  = stksegs * (sizeof(Elf_Nhdr) + ROUNDUP(CONFIG_TASK_NAME_SIZE, 8) +
-                     sizeof(elf_prstatus_t));
-  total += stksegs * (sizeof(Elf_Nhdr) + ROUNDUP(CONFIG_TASK_NAME_SIZE, 8) +
-                     sizeof(elf_prpsinfo_t));
+  total  = stksegs * (sizeof(Elf_Nhdr) + ALIGN_UP(CONFIG_TASK_NAME_SIZE, 8) +
+                      sizeof(elf_prstatus_t));
+  total += stksegs * (sizeof(Elf_Nhdr) + ALIGN_UP(CONFIG_TASK_NAME_SIZE, 8) +
+                      sizeof(elf_prpsinfo_t));
   return total;
 }
 
@@ -276,7 +274,7 @@ static int elf_get_note_size(int stksegs)
 static void elf_emit_tcb_note(FAR struct elf_dumpinfo_s *cinfo,
                               FAR struct tcb_s *tcb)
 {
-  char name[ROUNDUP(CONFIG_TASK_NAME_SIZE, 8)];
+  char name[ALIGN_UP(CONFIG_TASK_NAME_SIZE, 8)];
   elf_prstatus_t status;
   elf_prpsinfo_t info;
   FAR uintptr_t *regs;
@@ -414,8 +412,8 @@ static void elf_emit_tcb_stack(FAR struct elf_dumpinfo_s *cinfo,
             (tcb->stack_base_ptr - tcb->stack_alloc_ptr);
     }
 
-  sp  = ROUNDDOWN(buf, PROGRAM_ALIGNMENT);
-  len = ROUNDUP(len + (buf - sp), PROGRAM_ALIGNMENT);
+  sp  = ALIGN_DOWN(buf, PROGRAM_ALIGNMENT);
+  len = ALIGN_UP(len + (buf - sp), PROGRAM_ALIGNMENT);
   buf = sp;
 
   elf_emit(cinfo, (FAR void *)buf, len);
@@ -546,17 +544,17 @@ static void elf_emit_tcb_phdr(FAR struct elf_dumpinfo_s *cinfo,
                       (tcb->stack_base_ptr - tcb->stack_alloc_ptr);
     }
 
-  sp = ROUNDDOWN(phdr->p_vaddr, PROGRAM_ALIGNMENT);
-  phdr->p_filesz = ROUNDUP(phdr->p_filesz +
-                           (phdr->p_vaddr - sp), PROGRAM_ALIGNMENT);
+  sp = ALIGN_DOWN(phdr->p_vaddr, PROGRAM_ALIGNMENT);
+  phdr->p_filesz = ALIGN_UP(phdr->p_filesz +
+                            (phdr->p_vaddr - sp), PROGRAM_ALIGNMENT);
   phdr->p_vaddr  = sp;
 
   phdr->p_type   = PT_LOAD;
-  phdr->p_offset = ROUNDUP(*offset, ELF_PAGESIZE);
+  phdr->p_offset = ALIGN_UP(*offset, ELF_PAGESIZE);
   phdr->p_paddr  = phdr->p_vaddr;
   phdr->p_memsz  = phdr->p_filesz;
   phdr->p_flags  = PF_X | PF_W | PF_R;
-  *offset       += ROUNDUP(phdr->p_memsz, ELF_PAGESIZE);
+  *offset       += ALIGN_UP(phdr->p_memsz, ELF_PAGESIZE);
 
   elf_emit(cinfo, phdr, sizeof(*phdr));
 }
@@ -608,13 +606,13 @@ static void elf_emit_phdr(FAR struct elf_dumpinfo_s *cinfo,
   for (i = 0; i < memsegs; i++)
     {
       phdr.p_type   = PT_LOAD;
-      phdr.p_offset = ROUNDUP(offset, ELF_PAGESIZE);
+      phdr.p_offset = ALIGN_UP(offset, ELF_PAGESIZE);
       phdr.p_vaddr  = cinfo->regions[i].start;
       phdr.p_paddr  = phdr.p_vaddr;
       phdr.p_filesz = cinfo->regions[i].end - cinfo->regions[i].start;
       phdr.p_memsz  = phdr.p_filesz;
       phdr.p_flags  = cinfo->regions[i].flags;
-      offset       += ROUNDUP(phdr.p_memsz, ELF_PAGESIZE);
+      offset       += ALIGN_UP(phdr.p_memsz, ELF_PAGESIZE);
       elf_emit(cinfo, &phdr, sizeof(phdr));
     }
 }

tools/nxstyle.c

@@ -617,6 +617,17 @@ static const char *g_white_content_list[] =
   "unzGetCurrentFileInfo64",
   "unzGoToNextFile",
   "unzGoToFirstFile",
+
+  /* Ref:
+   * apps/netutils/telnetc/telnetc.c
+   */
+
+  "deflateInit",
+  "deflateEnd",
+  "inflateInit",
+  "inflateEnd",
+  "zError",
+
   NULL
 };