Kyle Wilson 400f2960e6 Added PLLxFRACN definitions. Updated board.h to use them. Updated board.h to set SYSCLK to 250 MHz properly. ... PLL1FRACN was being set improperly. stm32h5xxx_rcc.c does not shift the value provided by board.h. So it was being set wrong. The defintions in stm32h5xxx_rcc.h shift the FRACN value and are now used by board.h. Also, board.h was not setting PLL1P properly. PLL1P can not have odd divisors. Therefore a value of 0 was invalid. Set it to a value of 1 (divide by 2), then adjust PLL1N to 31 and PLL1FRAC1 to 2048 to actually set SYSCLK to 250MHz.		2024-11-06 16:25:09 -03:00
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configs/nsh	H5 with NSH support for Nucleo-H563ZI.	2024-11-06 10:28:49 +08:00
include	Added PLLxFRACN definitions. Updated board.h to use them. Updated board.h to set SYSCLK to 250 MHz properly.	2024-11-06 16:25:09 -03:00
scripts	H5 with NSH support for Nucleo-H563ZI.	2024-11-06 10:28:49 +08:00
src	H5 with NSH support for Nucleo-H563ZI.	2024-11-06 10:28:49 +08:00
Kconfig	H5 with NSH support for Nucleo-H563ZI.	2024-11-06 10:28:49 +08:00