Huang Qi 93d75129de riscv: Add Vector CSRs to csr.h ... The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2024-04-19 00:31:07 +08:00
..
arm	arch/arm/src/samv7/sam_qencoder.c: add support for GETINDEX ioctl call	2024-04-17 19:44:34 +08:00
arm64	arm64/imx9: Add LPSPI driver	2024-04-18 10:58:02 -03:00
avr	fix nxstyle	2024-04-15 15:33:17 -03:00
ceva	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
dummy	arch: Add custom arch chip build support	2020-10-20 14:48:16 +08:00
hc	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
mips	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
misoc	comments/docs: fix typos in comments	2024-03-06 13:31:50 +08:00
or1k	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
renesas	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
risc-v	riscv: Add Vector CSRs to csr.h	2024-04-19 00:31:07 +08:00
sim	simwifi:change script path from absolute path to soft link	2024-04-17 19:46:42 +08:00
sparc	arch: Remove xxx_intstack_top and xxx_intstack_alloc	2024-04-09 16:59:00 -03:00
tricore	arch/tricore: add spinlock support	2024-03-21 18:47:14 +08:00
x86	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
x86_64	stack: update up_get_intstackbase API to support cpu id	2024-04-09 16:59:00 -03:00
xtensa	esp32s3: add simple boot support	2024-04-17 19:43:05 +08:00
z16	comments/docs: fix typos in comments	2024-03-06 13:31:50 +08:00
z80	comments/docs: fix typos in comments	2024-03-06 13:31:50 +08:00
CMakeLists.txt	build/cmake: add initial KERNEL mode support	2024-03-15 16:21:23 +08:00
Kconfig	arch/kconfig: revising kernel mapping configs	2024-04-18 17:10:04 +08:00