fix nxstyle
Remove TABs
This commit is contained in:
simbit18
Xiang Xiao
parent
51171d66f2
commit
0476895c0d
6 changed files with 36 additions and 36 deletions
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@ -36,10 +36,10 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define CSK6_IOMUX_BASE 0x46200000 // size=1MB
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#define CSK6_SYSCTRL_BASE 0x46000000 // size=64KB
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#define CSK6_IOMUX_BASE 0x46200000 // size=1MB
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#define CSK6_SYSCTRL_BASE 0x46000000 // size=64KB
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#define CSK6_SYSPLL_CTRL_BASE 0x46020000 // size=64KB
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#define CSK6_UART0_BASE 0x45000000 // size=1MB
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#define CSK6_UART0_BASE 0x45000000 // size=1MB
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#define CSK6011A_NANO_BOARD_H_XTAL_SRC_FREQ 24000000UL
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#define CSK6011A_NANO_BOARD_L_XTAL_SRC_FREQ 32768UL
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@ -119,7 +119,7 @@ static uint32_t get_flash_page_size(void)
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}
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#else
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return STM32_FLASH_PAGESIZE;
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#endif
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#endif
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}
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static uint32_t get_flash_npages(void)
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@ -135,7 +135,7 @@ static uint32_t get_flash_npages(void)
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}
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#else
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return STM32_FLASH_NPAGES;
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#endif
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#endif
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}
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static void flash_unlock(void)
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@ -43,7 +43,7 @@
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#define AHAB_CMD_TAG 0x17
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#define AHAB_RESP_TAG 0xe1
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#define ELE_RELEASE_RDC_REQ 0xc4
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#define ELE_READ_FUSE_REQ 0x97
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#define ELE_READ_FUSE_REQ 0x97
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#define ELE_OK 0xd6
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#define FSB_BASE 0x47510000UL
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@ -51,15 +51,15 @@
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#define BLK_CTRL_NS_ANOMIX_BASE IMX9_BLK_CTRL_NS_AONMIX1_BASE
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#define ELE_MU_TCR (IMX9_S3MUA_BASE+ 0x120)
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#define ELE_MU_TSR (IMX9_S3MUA_BASE+ 0x124)
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#define ELE_MU_RCR (IMX9_S3MUA_BASE+ 0x128)
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#define ELE_MU_RSR (IMX9_S3MUA_BASE+ 0x12c)
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#define ELE_MU_TCR (IMX9_S3MUA_BASE+ 0x120)
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#define ELE_MU_TSR (IMX9_S3MUA_BASE+ 0x124)
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#define ELE_MU_RCR (IMX9_S3MUA_BASE+ 0x128)
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#define ELE_MU_RSR (IMX9_S3MUA_BASE+ 0x12c)
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#define ELE_RR_NUM 4
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#define ELE_TR_NUM 8
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#define ELE_MU_TR(i) (IMX9_S3MUA_BASE + 0x200 + (i) * 4)
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#define ELE_MU_RR(i) (IMX9_S3MUA_BASE + 0x280 + (i) * 4)
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#define ELE_MU_TR(i) (IMX9_S3MUA_BASE + 0x200 + (i) * 4)
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#define ELE_MU_RR(i) (IMX9_S3MUA_BASE + 0x280 + (i) * 4)
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#define DID_NUM 16
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#define MBC_MAX_NUM 4
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@ -70,7 +70,7 @@
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#define MBC_BLK_NUM(GLBCFG) (GLBCFG & 0x3FF)
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#define MRC_RGN_NUM(GLBCFG) (GLBCFG & 0x1F)
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#define GLBAC_SETTING_MASK (0x7777)
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#define GLBAC_SETTING_MASK (0x7777)
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#define GLBAC_LOCK_MASK BIT(31)
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struct ele_header_t
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@ -42,7 +42,7 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define mmio_read_32(c) getreg32(c)
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#define mmio_read_32(c) getreg32(c)
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#define mmio_write_32(c, v) putreg32(v, c)
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#define mmio_clrbits_32(addr, clear) modifyreg32(addr, clear, 0)
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#define mmio_setbits_32(addr, set) modifyreg32(addr, 0, set)
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@ -124,7 +124,7 @@
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***************************************************************************/
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#define XUARTPS_CR_STOPBRK 0x00000100U /* Stop transmission of break */
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#define XUARTPS_CR_STARTBRK 0x00000080U /* Set break */
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#define XUARTPS_CR_STARTBRK 0x00000080U /* Set break */
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#define XUARTPS_CR_TORST 0x00000040U /* RX timeout counter restart */
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#define XUARTPS_CR_TX_DIS 0x00000020U /* TX disabled. */
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#define XUARTPS_CR_TX_EN 0x00000010U /* TX enabled */
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@ -235,8 +235,8 @@
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*
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***************************************************************************/
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#define XUARTPS_BAUDDIV_MASK 0x000000FFU /* 8 bit baud divider mask */
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#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /* Reset value */
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#define XUARTPS_BAUDDIV_MASK 0x000000FFU /* 8 bit baud divider mask */
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#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /* Reset value */
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/***************************************************************************
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* The following constant defines the amount of error that is allowed for
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@ -298,9 +298,9 @@
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*
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***************************************************************************/
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#define XUARTPS_MODEMCR_FCM 0x00000020U /* Flow control mode */
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#define XUARTPS_MODEMCR_RTS 0x00000002U /* Request to send */
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#define XUARTPS_MODEMCR_DTR 0x00000001U /* Data terminal ready */
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#define XUARTPS_MODEMCR_FCM 0x00000020U /* Flow control mode */
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#define XUARTPS_MODEMCR_RTS 0x00000002U /* Request to send */
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#define XUARTPS_MODEMCR_DTR 0x00000001U /* Data terminal ready */
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/***************************************************************************
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* Modem Status Register
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@ -361,7 +361,7 @@
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*
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***************************************************************************/
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#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /* Valid bit mask */
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#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /* Valid bit mask */
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/***************************************************************************
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* Receiver FIFO Byte Status Register
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@ -376,18 +376,18 @@
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***************************************************************************/
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#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /* Byte3 Break Error */
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#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /* Byte3 Frame Error */
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#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /* Byte3 Parity Error */
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#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /* Byte2 Break Error */
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#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /* Byte2 Frame Error */
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#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /* Byte2 Parity Error */
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#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /* Byte1 Break Error */
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#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /* Byte1 Frame Error */
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#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /* Byte1 Parity Error */
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#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /* Byte0 Break Error */
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#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /* Byte0 Frame Error */
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#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /* Byte0 Parity Error */
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#define XUARTPS_RXBS_MASK 0x00000007U /* 3 bit RX byte status mask */
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#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /* Byte3 Frame Error */
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#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /* Byte3 Parity Error */
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#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /* Byte2 Break Error */
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#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /* Byte2 Frame Error */
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#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /* Byte2 Parity Error */
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#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /* Byte1 Break Error */
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#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /* Byte1 Frame Error */
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#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /* Byte1 Parity Error */
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#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /* Byte0 Break Error */
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#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /* Byte0 Frame Error */
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#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /* Byte0 Parity Error */
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#define XUARTPS_RXBS_MASK 0x00000007U /* 3 bit RX byte status mask */
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/***************************************************************************
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* Private Types
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@ -34,9 +34,9 @@
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/* Register offsets */
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#define BL808_M0IC_STATUS_OFFSET(n) (0x00 + 4 * (n))
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#define BL808_M0IC_MASK_OFFSET(n) (0x08 + 4 * (n))
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#define BL808_M0IC_CLEAR_OFFSET(n) (0x10 + 4 * (n))
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#define BL808_M0IC_STATUS_OFFSET(n) (0x00 + 4 * (n))
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#define BL808_M0IC_MASK_OFFSET(n) (0x08 + 4 * (n))
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#define BL808_M0IC_CLEAR_OFFSET(n) (0x10 + 4 * (n))
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/* Register locations */
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