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add Artery at32

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This commit is contained in:
xiao 2023-09-16 18:11:01 +08:00 committed by Xiang Xiao
parent 51a412c6b4
commit 1487aa267e
159 changed files with 84482 additions and 0 deletions
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19
arch/arm/Kconfig
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@ -659,6 +659,21 @@ config ARCH_CHIP_GOLDFISH_ARM
---help---
GOLDFISH virt platform (ARMv7a)
config ARCH_CHIP_AT32
bool "Artery AT32 F4"
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_TIMEKEEPING
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
Artery AT32 architectures (ARM Cortex-M4)
config ARCH_CHIP_ARM_CUSTOM
bool "Custom ARM chip"
select ARCH_CHIP_CUSTOM
@ -1065,6 +1080,7 @@ config ARCH_CHIP
default "tlsr82" if ARCH_CHIP_TLSR82
default "qemu" if ARCH_CHIP_QEMU_ARM
default "goldfish" if ARCH_CHIP_GOLDFISH_ARM
default "at32" if ARCH_CHIP_AT32
config ARM_THUMB
bool "Thumb Mode"
@ -1543,4 +1559,7 @@ endif
if ARCH_CHIP_GOLDFISH_ARM
source "arch/arm/src/goldfish/Kconfig"
endif
if ARCH_CHIP_AT32
source "arch/arm/src/at32/Kconfig"
endif
endif # ARCH_ARM

184
arch/arm/include/at32/at32f43xxx_irq.h Normal file
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@ -0,0 +1,184 @@
/****************************************************************************
* arch/arm/include/at32/at32f43xxx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_AT32_AT32F43XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_AT32_AT32F43XXX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can
* be found in nuttx/arch/arm/include/at32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define AT32_IRQ_WWDG (AT32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define AT32_IRQ_PVD (AT32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define AT32_IRQ_TAMPER (AT32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define AT32_IRQ_TIMESTAMP (AT32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define AT32_IRQ_RTC_WKUP (AT32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define AT32_IRQ_FLASH (AT32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define AT32_IRQ_RCC (AT32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define AT32_IRQ_EXTI0 (AT32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define AT32_IRQ_EXTI1 (AT32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define AT32_IRQ_EXTI2 (AT32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define AT32_IRQ_EXTI3 (AT32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define AT32_IRQ_EXTI4 (AT32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define AT32_IRQ_EDMAS1 (AT32_IRQ_FIRST+11) /* 11: EDMA Stream 1 global interrupt */
#define AT32_IRQ_EDMAS2 (AT32_IRQ_FIRST+12) /* 12: EDMA Stream 2 global interrupt */
#define AT32_IRQ_EDMAS3 (AT32_IRQ_FIRST+13) /* 13: EDMA Stream 3 global interrupt */
#define AT32_IRQ_EDMAS4 (AT32_IRQ_FIRST+14) /* 14: EDMA Stream 4 global interrupt */
#define AT32_IRQ_EDMAS5 (AT32_IRQ_FIRST+15) /* 15: EDMA Stream 5 global interrupt */
#define AT32_IRQ_EDMAS6 (AT32_IRQ_FIRST+16) /* 16: EDMA Stream 6 global interrupt */
#define AT32_IRQ_EDMAS7 (AT32_IRQ_FIRST+17) /* 17: EDMA Stream 7 global interrupt */
#define AT32_IRQ_ADC (AT32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define AT32_IRQ_CAN1TX (AT32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define AT32_IRQ_CAN1RX0 (AT32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define AT32_IRQ_CAN1RX1 (AT32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define AT32_IRQ_CAN1SCE (AT32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define AT32_IRQ_EXTI95 (AT32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define AT32_IRQ_TIM1BRK (AT32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define AT32_IRQ_TIM9 (AT32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define AT32_IRQ_TIM1UP (AT32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define AT32_IRQ_TIM10 (AT32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define AT32_IRQ_TIM1TRGCOM (AT32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define AT32_IRQ_TIM11 (AT32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define AT32_IRQ_TIM1CC (AT32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define AT32_IRQ_TIM2 (AT32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define AT32_IRQ_TIM3 (AT32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define AT32_IRQ_TIM4 (AT32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define AT32_IRQ_I2C1EV (AT32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define AT32_IRQ_I2C1ER (AT32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define AT32_IRQ_I2C2EV (AT32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define AT32_IRQ_I2C2ER (AT32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define AT32_IRQ_SPI1 (AT32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define AT32_IRQ_SPI2 (AT32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define AT32_IRQ_USART1 (AT32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define AT32_IRQ_USART2 (AT32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define AT32_IRQ_USART3 (AT32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define AT32_IRQ_EXTI1510 (AT32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define AT32_IRQ_RTCALRM (AT32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define AT32_IRQ_OTGFSWKUP (AT32_IRQ_FIRST+42) /* 42: USB On-The-Go FS1 Wakeup through EXTI line interrupt */
#define AT32_IRQ_TIM8BRK (AT32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define AT32_IRQ_TIM12 (AT32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define AT32_IRQ_TIM8UP (AT32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define AT32_IRQ_TIM13 (AT32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define AT32_IRQ_TIM8TRGCOM (AT32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define AT32_IRQ_TIM14 (AT32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define AT32_IRQ_TIM8CC (AT32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define AT32_IRQ_EDMAS8 (AT32_IRQ_FIRST+47) /* 47: EDMA Stream 8 global interrupt */
#define AT32_IRQ_XSMC (AT32_IRQ_FIRST+48) /* 48: XSMC global interrupt */
#define AT32_IRQ_SDIO (AT32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
#define AT32_IRQ_TIM5 (AT32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define AT32_IRQ_SPI3 (AT32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define AT32_IRQ_UART4 (AT32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define AT32_IRQ_UART5 (AT32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define AT32_IRQ_TIM6 (AT32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define AT32_IRQ_DAC (AT32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define AT32_IRQ_TIM7 (AT32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define AT32_IRQ_DMA1CH1 (AT32_IRQ_FIRST+56) /* 56: DMA1 Stream 1 global interrupt */
#define AT32_IRQ_DMA1CH2 (AT32_IRQ_FIRST+57) /* 57: DMA1 Stream 2 global interrupt */
#define AT32_IRQ_DMA1CH3 (AT32_IRQ_FIRST+58) /* 58: DMA1 Stream 3 global interrupt */
#define AT32_IRQ_DMA1CH4 (AT32_IRQ_FIRST+59) /* 59: DMA1 Stream 4 global interrupt */
#define AT32_IRQ_DMA1CH5 (AT32_IRQ_FIRST+60) /* 60: DMA1 Stream 5 global interrupt */
#if defined(CONFIG_AT32_AT32F437)
# define AT32_IRQ_ETH (AT32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
# define AT32_IRQ_ETHWKUP (AT32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#endif
#define AT32_IRQ_CAN2TX (AT32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define AT32_IRQ_CAN2RX0 (AT32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define AT32_IRQ_CAN2RX1 (AT32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define AT32_IRQ_CAN2SCE (AT32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define AT32_IRQ_OTGFS (AT32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define AT32_IRQ_DMA1CH6 (AT32_IRQ_FIRST+68) /* 68: DMA1 Stream 6 global interrupt */
#define AT32_IRQ_DMA1CH7 (AT32_IRQ_FIRST+69) /* 69: DMA1 Stream 7 global interrupt */
#define AT32_IRQ_USART6 (AT32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define AT32_IRQ_I2C3EV (AT32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define AT32_IRQ_I2C3ER (AT32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define AT32_IRQ_OTGFS2 (AT32_IRQ_FIRST+77) /* 77: USB On The Go FS2 global interrupt */
#define AT32_IRQ_DVP (AT32_IRQ_FIRST+78) /* 78: DVP global interrupt */
#define AT32_IRQ_FPU (AT32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define AT32_IRQ_UART7 (AT32_IRQ_FIRST+82) /* 82: UART7 interrupt */
#define AT32_IRQ_UART8 (AT32_IRQ_FIRST+83) /* 83: UART8 interrupt */
#define AT32_IRQ_SPI4 (AT32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
#define AT32_IRQ_QUADSPI2 (AT32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */
#define AT32_IRQ_QUADSPI1 (AT32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */
#define AT32_IRQ_DMAMUX (AT32_IRQ_FIRST+94) /* DMAMUX over interrupt */
#define AT32_IRQ_SDIO2 (AT32_IRQ_FIRST+102) /* SDIO2 interrupt */
#define AT32_IRQ_ACC (AT32_IRQ_FIRST+103) /* ACC interrupt */
#define AT32_IRQ_TIM20BRK (AT32_IRQ_FIRST+104) /* TIM20 break up interrupt */
#define AT32_IRQ_TIM20UP (AT32_IRQ_FIRST+105) /* TIM20 over interrupt */
#define AT32_IRQ_TIM20 (AT32_IRQ_FIRST+106) /* TIM20 global interrupt */
#define AT32_IRQ_TIM20CC (AT32_IRQ_FIRST+107) /* TIM20 Capture Compare interrupt */
#define AT32_IRQ_DMA2CH1 (AT32_IRQ_FIRST+108) /* DMA2 Stream 1 global interrupt */
#define AT32_IRQ_DMA2CH2 (AT32_IRQ_FIRST+109) /* DMA2 Stream 2 global interrupt */
#define AT32_IRQ_DMA2CH3 (AT32_IRQ_FIRST+110) /* DMA2 Stream 3 global interrupt */
#define AT32_IRQ_DMA2CH4 (AT32_IRQ_FIRST+111) /* DMA2 Stream 4 global interrupt */
#define AT32_IRQ_DMA2CH5 (AT32_IRQ_FIRST+112) /* DMA2 Stream 5 global interrupt */
#define AT32_IRQ_DMA2CH6 (AT32_IRQ_FIRST+113) /* DMA2 Stream 6 global interrupt */
#define AT32_IRQ_DMA2CH7 (AT32_IRQ_FIRST+114) /* DMA2 Stream 7 global interrupt */
#if defined(CONFIG_AT32_AT32F435) || defined(CONFIG_AT32_AT32F437)
# define AT32_IRQ_NEXTINT (115)
# define NR_IRQS (AT32_IRQ_FIRST+115)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_AT32_AT32F43XXX_IRQ_H */

560
arch/arm/include/at32/chip.h Normal file
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@ -0,0 +1,560 @@
/****************************************************************************
* arch/arm/include/at32/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_AT32_CHIP_H
#define __ARCH_ARM_INCLUDE_AT32_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* Check the AT32 family configuration.
* It must be done in arch/arm/src/at32/Kconfig !
*/
#ifdef CONFIG_AT32_AT32F43XX
# define __HAVE_F4 1
#else
# define __HAVE_F4 0
#endif
#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \
__HAVE_G4 + __HAVE_L1) != 1)
# error "Only one AT32 family must be selected !"
#endif
#ifdef CONFIG_AT32_LOWDENSITY
# define __HAVE_LD 1
#else
# define __HAVE_LD 0
#endif
#ifdef CONFIG_AT32_MEDIUMDENSITY
# define __HAVE_MD 1
#else
# define __HAVE_MD 0
#endif
#ifdef CONFIG_AT32_MEDIUMPLUSDENSITY
# define __HAVE_MPD 1
#else
# define __HAVE_MPD 0
#endif
#ifdef CONFIG_AT32_HIGHDENSITY
# define __HAVE_HD 1
#else
# define __HAVE_HD 0
#endif
#if (__HAVE_LD +__HAVE_MD + __HAVE_MPD + __HAVE_HD) > 1
# error "Up to one density configuration must be selected"
#endif
/* Get customizations for each supported chip and provide alternate function
* pin-mapping
*
* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
* particular pin-mapping will depend on the package and AT32 family. If
* you are incorporating a new AT32 chip into NuttX, you will need to add
* the pin-mapping to a header file and to include that header file below.
* The chip-specific pin-mapping is defined in the chip datasheet.
*/
/* AT32 F4 Family ***********************************************************/
#if defined(CONFIG_ARCH_CHIP_AT32F435RC) /* LQFP 64 10x10x1.4 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 3 /* 3 advanced timers TIM1 and 8 */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* 2 basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 4 /* SPI1-4 */
# define AT32_NI2S 4 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 8 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 2 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 2 /* USB OTG FS/HS */
# define AT32_NGPIO 53 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 0 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 53 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435RM) /* LQFP 64 10x10x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 53 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435VC) /* LQFP 100 14x14x1.4 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 84 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 84 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435VM) /* LQFP 100 14x14x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 84 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435ZC) /* LQFP 144 20x20x1.4 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 116 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 116 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F435ZM) /* LQFP 144 20x20x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 116 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437RC) /* LQFP 64 10x10x1.4 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 53 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 53 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437RM) /* LQFP 64 10x10x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 53 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 0 /* No Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437VC) /* LQFP-100 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 84 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 3 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 4 /* SPI1-3 */
# define AT32_NI2S 4 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 8 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 2 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 2 /* USB OTG FS/HS */
# define AT32_NGPIO 84 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 1 /* 12-bit DAC1, 1 channel */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define AT32_NRNG 0 /* Random number generator (RNG) */
# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437VM) /* LQFP-100 14x14x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 3 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 4 /* SPI1-3 */
# define AT32_NI2S 4 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 8 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 2 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 2 /* USB OTG FS/HS */
# define AT32_NGPIO 84 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define AT32_NDAC 1 /* 12-bit DAC1, 1 channel */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define AT32_NRNG 0 /* Random number generator (RNG) */
# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437ZC) /* LQFP-144 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 116 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 116 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_AT32F437ZM) /* LQFP 144 20x20x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
# define AT32_NSPI 3 /* SPI1-3 */
# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
# define AT32_NI2C 3 /* I2C1-3 */
# define AT32_NCAN 2 /* CAN1-2 */
# define AT32_NSDIO 1 /* SDIO */
# define AT32_NLCD 0 /* No LCD */
# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
# define AT32_NGPIO 116 /* GPIOA-I */
# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
# define AT32_NCRC 1 /* CRC */
# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define AT32_NRNG 1 /* Random number generator (RNG) */
# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# error "Unsupported AT32 chip"
#endif
/* Peripheral IP versions ***************************************************/
/* Peripheral IP versions are invariant and should be decided here, not in
* Kconfig.
*
* REVISIT: Currently only SPI IP version is handled here, with others being
* handled in Kconfig. Those others need to be gradually refactored
* and resolved here.
*/
#if defined(CONFIG_AT32_AT32F43XX)
# define AT32_HAVE_IP_SPI_V2
#else
# error "Did not resolve peripheral IP versions!"
#endif
/* NVIC priority levels *****************************************************/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_AT32_CHIP_H */

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/****************************************************************************
* arch/arm/include/at32/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_AT32_IRQ_H
#define __ARCH_ARM_INCLUDE_AT32_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/at32/chip.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define AT32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define AT32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define AT32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define AT32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define AT32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define AT32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define AT32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define AT32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define AT32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define AT32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific
*/
#define AT32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
/****************************************************************************
* Included Files
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
# include <arch/at32/at32f43xxx_irq.h>
#else
# error "Unsupported AT32 chip"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_AT32_IRQ_H */

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############################################################################
# arch/arm/src/at32/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include armv7-m/Make.defs
CHIP_CSRCS = at32_allocateheap.c at32_start.c at32_rcc.c at32_lse.c
CHIP_CSRCS += at32_lsi.c at32_gpio.c at32_exti_gpio.c at32_flash.c
CHIP_CSRCS += at32_irq.c at32_lowputc.c
CHIP_CSRCS += at32_waste.c at32_uid.c
CHIP_CSRCS += at32_serial.c
ifeq ($(CONFIG_AT32_TIM),y)
CHIP_CSRCS += at32_tim.c
endif
ifeq ($(CONFIG_AT32_SDIO),y)
CHIP_CSRCS += at32_sdio.c
endif
ifeq ($(CONFIG_AT32_SPI),y)
CHIP_CSRCS += at32_spi.c
endif
ifeq ($(CONFIG_AT32_DMA),y)
CHIP_CSRCS += at32_dma.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += at32_tim_lowerhalf.c
endif
ifdef CONFIG_AT32_TICKLESS_TIMER
CHIP_CSRCS += at32_tickless.c
else
CHIP_CSRCS += at32_timerisr.c
endif
ifeq ($(CONFIG_AT32_ONESHOT),y)
CHIP_CSRCS += at32_oneshot.c at32_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_AT32_FREERUN),y)
CHIP_CSRCS += at32_freerun.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += at32_userspace.c at32_mpuinit.c
endif
ifeq ($(CONFIG_AT32_I2C),y)
CHIP_CSRCS += at32_i2c.c
endif
ifeq ($(CONFIG_USBDEV),y)
ifeq ($(CONFIG_AT32_USB),y)
CHIP_CSRCS += at32_usbdev.c
endif
ifeq ($(CONFIG_AT32_USBFS),y)
CHIP_CSRCS += at32_usbfs.c
endif
ifeq ($(CONFIG_AT32_OTGFS),y)
CHIP_CSRCS += at32_otgfsdev.c
endif
endif
ifeq ($(CONFIG_AT32_USBHOST),y)
ifeq ($(CONFIG_AT32_OTGFS),y)
CHIP_CSRCS += at32_otgfshost.c
endif
ifeq ($(CONFIG_USBHOST_TRACE),y)
CHIP_CSRCS += at32_usbhost.c
else
ifeq ($(CONFIG_DEBUG_USB),y)
CHIP_CSRCS += at32_usbhost.c
endif
endif
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += at32_idle.c
endif
CHIP_CSRCS += at32_pmstop.c at32_pmstandby.c at32_pmsleep.c
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += at32_pminitialize.c
endif
ifeq ($(CONFIG_AT32_ETHMAC),y)
CHIP_CSRCS += at32_eth.c
endif
ifeq ($(CONFIG_AT32_PWR),y)
CHIP_CSRCS += at32_pwr.c at32_exti_pwr.c
endif
ifeq ($(CONFIG_AT32_RTC),y)
CHIP_CSRCS += at32_rtc.c
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += at32_exti_alarm.c
endif
ifeq ($(CONFIG_RTC_PERIODIC),y)
CHIP_CSRCS += at32_exti_wakeup.c
endif
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += at32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_AT32_ADC),y)
CHIP_CSRCS += at32_adc.c
endif
ifeq ($(CONFIG_AT32_DAC),y)
CHIP_CSRCS += at32_dac.c
endif
ifeq ($(CONFIG_AT32_1WIREDRIVER),y)
CHIP_CSRCS += at32_1wire.c
endif
ifeq ($(CONFIG_AT32_HCIUART),y)
CHIP_CSRCS += at32_hciuart.c
endif
ifeq ($(CONFIG_AT32_PWM),y)
CHIP_CSRCS += at32_pwm.c
endif
ifeq ($(CONFIG_AT32_CAP),y)
CHIP_CSRCS += at32_capture_lowerhalf.c
endif
ifeq ($(CONFIG_SENSORS_HALL3PHASE),y)
CHIP_CSRCS += at32_hall3ph.c
endif
ifeq ($(CONFIG_AT32_CAN),y)
ifeq ($(CONFIG_AT32_CAN_CHARDRIVER),y)
CHIP_CSRCS += at32_can.c
endif
ifeq ($(CONFIG_AT32_CAN_SOCKET),y)
CHIP_CSRCS += at32_can_sock.c
endif
endif
ifeq ($(CONFIG_AT32_IWDG),y)
CHIP_CSRCS += at32_iwdg.c
endif
ifeq ($(CONFIG_AT32_WWDG),y)
CHIP_CSRCS += at32_wwdg.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += at32_dumpgpio.c
endif
ifeq ($(CONFIG_AT32_FOC),y)
CHIP_CSRCS += at32_foc.c
endif

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/****************************************************************************
* arch/arm/src/at32/at32.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_H
#define __ARCH_ARM_SRC_AT32_AT32_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals **************************************************************/
#include "chip.h"
#include "at32_gpio.h"
#include "at32_uart.h"
#include "at32_exti.h"
#include "at32_flash.h"
#include "at32_dma.h"
#include "at32_pwr.h"
#include "at32_rcc.h"
#include "at32_lowputc.h"
#include "at32_adc.h"
#include "at32_can.h"
#include "at32_i2c.h"
#include "at32_rtc.h"
#include "at32_sdio.h"
#include "at32_spi.h"
#include "at32_tim.h"
#include "at32_eth.h"
#include "at32_wdg.h"
#include "at32_dbgmcu.h"
#endif /* __ARCH_ARM_SRC_AT32_AT32_H */

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/****************************************************************************
* arch/arm/src/at32/at32_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "arm_internal.h"
#include "at32_mpuinit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Internal SRAM is available in all members of the AT32 family. The
* following definitions must be provided to specify the size and
* location of internal(system) SRAM:
*
* CONFIG_RAM_END : End address (+1) of SRAM
*
* The F4 family also contains internal CCM SRAM. This SRAM is different
* because it cannot be used for DMA. So if DMA needed, then the following
* should be defined to exclude CCM SRAM from the heap:
*
*
* In addition to internal SRAM, external RAM may also be available through
* the FMC/FSMC. To use external RAM, the following things need to be present
* in the NuttX configuration file:
*
* CONFIG_AT32_FSMC=y : Enables the FSMC
* CONFIG_AT32_FMC=y : Enables the FMC
* CONFIG_AT32_EXTERNAL_RAM=y : Indicates external RAM is available via the
* FMC/FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the external RAM
* CONFIG_HEAP2_SIZE : The size of the external RAM
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the external RAM (as determined by
* the rules provided below)
*/
#if !defined(CONFIG_AT32_FSMC) && !defined(CONFIG_AT32_FMC)
# undef CONFIG_AT32_EXTERNAL_RAM
#endif
/* For the AT32F43XXX family, all internal SRAM is in one contiguous
* block starting at g_idle_topstack and extending through CONFIG_RAM_END
* (my apologies for the bad naming). In addition, external FSMC SRAM
* may be available.
*/
#if defined(CONFIG_AT32_AT32F43XX)
/* Set the end of system SRAM */
# define SRAM1_END 0x20060000
/* Check if external FSMC SRAM is provided */
# ifdef CONFIG_AT32_EXTERNAL_RAM
# if CONFIG_MM_REGIONS < 2
# warning "FSMC SRAM not included in the heap"
# undef CONFIG_AT32_EXTERNAL_RAM
# elif CONFIG_MM_REGIONS > 2
# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
# endif
# elif CONFIG_MM_REGIONS > 1
# error "CONFIG_MM_REGIONS > 1 but I don't know what the other region(s) are"
# endif
#else
# error "Unsupported AT32 chip"
#endif
/* If FSMC SRAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_AT32_EXTERNAL_RAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_AT32_EXTERNAL_RAM
# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_heap_color
*
* Description:
* Set heap memory to a known, non-zero state to checking heap usage.
*
****************************************************************************/
#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
}
#else
# define up_heap_color(start,size)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region Size determined at link time
* Kernel .bss region Size determined at link time
* Kernel IDLE thread stack Size determined by
* CONFIG_IDLETHREAD_STACKSIZE
* Padding for alignment
* User .data region Size determined at link time
* User .bss region Size determined at link time
* Kernel heap Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE
* User heap Extends to the end of SRAM
*
****************************************************************************/
void up_allocate_heap(void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
at32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;
/* Colorize the heap for debug */
up_heap_color(*heap_start, *heap_size);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifdef CONFIG_AT32_EXTERNAL_RAM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
at32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Colorize the heap for debug */
up_heap_color((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/at32/at32_can.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_CAN_H
#define __ARCH_ARM_SRC_AT32_AT32_CAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/at32_can.h"
#include <nuttx/can/can.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Up to 2 CAN interfaces are supported */
#if AT32_NCAN < 2
# undef CONFIG_AT32_CAN2
#endif
#if AT32_NCAN < 1
# undef CONFIG_AT32_CAN1
#endif
/* CAN BAUD */
#if defined(CONFIG_AT32_CAN1) && !defined(CONFIG_AT32_CAN1_BAUD)
# error "CONFIG_AT32_CAN1_BAUD is not defined"
#endif
#if defined(CONFIG_AT32_CAN2) && !defined(CONFIG_AT32_CAN2_BAUD)
# error "CONFIG_AT32_CAN2_BAUD is not defined"
#endif
/* User-defined TSEG1 and TSEG2 settings may be used.
*
* CONFIG_AT32_CAN_TSEG1 = the number of CAN time quanta in segment 1
* CONFIG_AT32_CAN_TSEG2 = the number of CAN time quanta in segment 2
* CAN_BIT_QUANTA = The number of CAN time quanta in on bit time
*/
#ifndef CONFIG_AT32_CAN_TSEG1
# define CONFIG_AT32_CAN_TSEG1 13
#endif
#if CONFIG_AT32_CAN_TSEG1 < 1 || CONFIG_AT32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX
# error "CONFIG_AT32_CAN_TSEG1 is out of range"
#endif
#ifndef CONFIG_AT32_CAN_TSEG2
# define CONFIG_AT32_CAN_TSEG2 2
#endif
#if CONFIG_AT32_CAN_TSEG2 < 1 || CONFIG_AT32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX
# error "CONFIG_AT32_CAN_TSEG2 is out of range"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_AT32_CAN_CHARDRIVER
/****************************************************************************
* Name: at32_caninitialize
*
* Description:
* Initialize the selected CAN port as character device
*
* Input Parameters:
* Port number (for hardware that has multiple CAN interfaces)
*
* Returned Value:
* Valid CAN device structure reference on success; a NULL on failure
*
****************************************************************************/
struct can_dev_s;
struct can_dev_s *at32_caninitialize(int port);
#endif
#ifdef CONFIG_AT32_CAN_SOCKET
/****************************************************************************
* Name: at32_cansockinitialize
*
* Description:
* Initialize the selected CAN port as SocketCAN interface
*
* Input Parameters:
* Port number (for hardware that has multiple CAN interfaces)
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
int at32_cansockinitialize(int port);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_CAN_H */

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/****************************************************************************
* arch/arm/src/at32/at32_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_DBGMCU_H
#define __ARCH_ARM_SRC_AT32_AT32_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/at32_dbgmcu.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_AT32_AT32_DBGMCU_H */

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/****************************************************************************
* arch/arm/src/at32/at32_dma.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is only a thin shell that includes the correct DMA
* implementation for the selected AT32 IP core:
* - AT32 DMA IP version 1 - F43X
*
*/
#if defined(CONFIG_AT32_HAVE_IP_DMA_V1)
# if defined(CONFIG_AT32_HAVE_DMAMUX)
# include "at32_dma_v1mux.c"
# else
# include "at32_dma_v1.c"
# endif
#elif defined(CONFIG_AT32_HAVE_IP_DMA_V2)
# include "at32_dma_v2.c"
#endif
/****************************************************************************
* Private Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/at32/at32_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_DMA_H
#define __ARCH_ARM_SRC_AT32_AT32_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "chip.h"
#include "hardware/at32_dma.h"
#ifdef CONFIG_AT32_HAVE_DMAMUX
# include "hardware/at32_dmamux.h"
#endif
/* These definitions provide the bit encoding of the 'status' parameter
* passed to the DMA callback function (see dma_callback_t).
*/
#define DMA_STATUS_FEIF 0 /* (Not available in F1) */
#define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
#define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
#define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
#define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
#define DMA_STATUS_ERROR (DMA_STATUS_FEIF | DMA_STATUS_DMEIF | DMA_STATUS_TEIF)
#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF)
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA_HANDLE provides an opaque reference that can be used to represent a
* DMA channel (F1) or a DMA stream (F4).
*/
typedef void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:
* handle - Refers to the DMA channel or stream
* status - A bit encoded value that provides the completion status. See
* the DMASTATUS_* definitions above.
* arg - A user-provided value that was provided when at32_dmastart()
* was called.
*/
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
#ifdef CONFIG_DEBUG_DMA_INFO
struct at32_dmaregs_s
{
uint32_t isr;
uint32_t ccr;
uint32_t cndtr;
uint32_t cpar;
uint32_t cmar;
};
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_dmachannel
*
* Description:
* Allocate a DMA channel. This function gives the caller mutually
* exclusive access to the DMA channel specified by the 'chan' argument.
* DMA channels are shared on the AT32: Devices sharing the same DMA
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
* at32_dma.h.
*
* If the DMA channel is not available, then at32_dmachannel() will wait
* until the holder of the channel relinquishes the channel by calling
* at32_dmafree(). WARNING: If you have two devices sharing a DMA
* channel and the code never releases the channel, the at32_dmachannel
* call for the other will hang forever in this function! Don't let your
* design do that!
*
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
* Input Parameters:
* chan - Identifies the channel resource
*
* Returned Value:
* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
* void* DMA channel handle. (If 'chan' is invalid, the function will
* assert if debug is enabled or do something ignorant otherwise).
*
* Assumptions:
* - The caller does not hold he DMA channel.
* - The caller can wait for the DMA channel to be freed if it is no
* available.
*
****************************************************************************/
DMA_HANDLE at32_dmachannel(unsigned int chan);
/****************************************************************************
* Name: at32_dmafree
*
* Description:
* Release a DMA channel. If another thread is waiting for this DMA
* channel in a call to at32_dmachannel, then this function will re-
* assign the DMA channel to that thread and wake it up.
*
* NOTE: The 'handle' used in this argument must NEVER be used again
* until at32_dmachannel() is called again to re-gain access to the
* channel.
*
* Returned Value:
* None
*
* Assumptions:
* - The caller holds the DMA channel.
* - There is no DMA in progress
*
****************************************************************************/
void at32_dmafree(DMA_HANDLE handle);
/****************************************************************************
* Name: at32_dmasetup
*
* Description:
* Configure DMA before using
*
****************************************************************************/
void at32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t ntransfers, uint32_t ccr);
/****************************************************************************
* Name: at32_dmastart
*
* Description:
* Start the DMA transfer
*
* Assumptions:
* - DMA handle allocated by at32_dmachannel()
* - No DMA in progress
*
****************************************************************************/
void at32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg,
bool half);
/****************************************************************************
* Name: at32_dmastop
*
* Description:
* Cancel the DMA. After at32_dmastop() is called, the DMA channel is
* reset and at32_dmasetup() must be called before at32_dmastart() can be
* called again
*
* Assumptions:
* - DMA handle allocated by at32_dmachannel()
*
****************************************************************************/
void at32_dmastop(DMA_HANDLE handle);
/****************************************************************************
* Name: at32_dmaresidual
*
* Description:
* Returns the number of bytes remaining to be transferred
*
* Assumptions:
* - DMA handle allocated by at32_dmachannel()
*
****************************************************************************/
size_t at32_dmaresidual(DMA_HANDLE handle);
/****************************************************************************
* Name: at32_dmacapable
*
* Description:
* Check if the DMA controller can transfer data to/from given memory
* address with the given configuration. This depends on the internal
* connections in the ARM bus matrix of the processor. Note that this only
* applies to memory addresses, it will return false for any peripheral
* address.
*
* Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
#ifdef CONFIG_AT32_DMACAPABLE
bool at32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr);
#else
# define at32_dmacapable(maddr, count, ccr) (true)
#endif
/****************************************************************************
* Name: at32_dmasample
*
* Description:
* Sample DMA register contents
*
* Assumptions:
* - DMA handle allocated by at32_dmachannel()
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void at32_dmasample(DMA_HANDLE handle, struct at32_dmaregs_s *regs);
#else
# define at32_dmasample(handle,regs)
#endif
/****************************************************************************
* Name: at32_dmadump
*
* Description:
* Dump previously sampled DMA register contents
*
* Assumptions:
* - DMA handle allocated by at32_dmachannel()
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void at32_dmadump(DMA_HANDLE handle, const struct at32_dmaregs_s *regs,
const char *msg);
#else
# define at32_dmadump(handle,regs,msg)
#endif
/* High performance, zero latency DMA interrupts need some additional
* interfaces.
*
* TODO: For now the interface is different for AT32 DMAv1 and AT32 DMAv2.
* It should be unified somehow.
*/
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
/****************************************************************************
* Name: at32_dma_intack
*
* Description:
* Public visible interface to acknowledge interrupts on DMA channel
*
****************************************************************************/
void at32_dma_intack(unsigned int chndx, uint32_t isr);
/****************************************************************************
* Name: at32_dma_intget
*
* Description:
* Public visible interface to get pending interrupts from DMA channel
*
****************************************************************************/
uint32_t at32_dma_intget(unsigned int chndx);
#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_DMA_H */

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/****************************************************************************
* arch/arm/src/at32/at32_dumpgpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Output debug info even if debug output is not selected. */
#undef CONFIG_DEBUG_INFO
#define CONFIG_DEBUG_INFO 1
#include <sys/types.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_gpio.h"
#include "at32_rcc.h"
#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
static const char g_portchar[AT32_NGPIO_PORTS] =
{
#if AT32_NGPIO_PORTS > 8
# error "Additional support required for this number of GPIOs"
#elif AT32_NGPIO_PORTS > 7
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
#elif AT32_NGPIO_PORTS > 6
'A', 'B', 'C', 'D', 'E', 'F', 'G'
#elif AT32_NGPIO_PORTS > 5
'A', 'B', 'C', 'D', 'E', 'F'
#elif AT32_NGPIO_PORTS > 4
'A', 'B', 'C', 'D', 'E'
#elif AT32_NGPIO_PORTS > 3
'A', 'B', 'C', 'D'
#elif AT32_NGPIO_PORTS > 2
'A', 'B', 'C'
#elif AT32_NGPIO_PORTS > 1
'A', 'B'
#elif AT32_NGPIO_PORTS > 0
'A'
#else
# error "Bad number of GPIOs"
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: at32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
int at32_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
unsigned int port;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
base = g_gpiobase[port];
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
#if defined(CONFIG_AT32_AT32F43XX)
DEBUGASSERT(port < AT32_NGPIO_PORTS);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(AT32_CRM_AHBEN1) & CRM_AHB1EN1_GPIOEN(port)) != 0)
{
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + AT32_GPIO_CFGR_OFFSET),
getreg32(base + AT32_GPIO_OMODER_OFFSET),
getreg32(base + AT32_GPIO_ODRVR_OFFSET),
getreg32(base + AT32_GPIO_PULL_OFFSET));
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + AT32_GPIO_IDT_OFFSET),
getreg32(base + AT32_GPIO_ODT_OFFSET),
getreg32(base + AT32_GPIO_SCR_OFFSET),
getreg32(base + AT32_GPIO_WPR_OFFSET));
_info(" AFRH: %08x AFRL: %08x\n",
getreg32(base + AT32_GPIO_MUXH_OFFSET),
getreg32(base + AT32_GPIO_MUXL_OFFSET));
}
else
{
_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
g_portchar[port], getreg32(AT32_CRM_AHBEN1));
}
#else
# error "Unsupported AT32 chip"
#endif
leave_critical_section(flags);
return OK;
}
#endif /* CONFIG_DEBUG_FEATURES */

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/****************************************************************************
* arch/arm/src/at32/at32_eth.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_ETH_H
#define __ARCH_ARM_SRC_AT32_AT32_ETH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if AT32_NETHERNET > 0
#include "hardware/at32_eth.h"
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: at32_ethinitialize
*
* Description:
* Initialize the Ethernet driver for one interface. If the AT32 chip
* supports multiple Ethernet controllers, then board specific logic must
* implement arm_netinitialize() and call this function to initialize the
* desired interfaces.
*
* Input Parameters:
* intf - In the case where there are multiple EMACs, this value
* identifies which EMAC is to be initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
#if AT32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT)
int at32_ethinitialize(int intf);
#endif
/****************************************************************************
* Function: at32_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_AT32_PHYINIT is defined in the configuration
* then the board specific logic must provide at32_phyinitialize(); The
* AT32 Ethernet driver will call this function one time before it first
* uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_AT32_PHYINIT
int at32_phy_boardinitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* AT32_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_AT32_AT32_ETH_H */

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/****************************************************************************
* arch/arm/src/at32/at32_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_EXTI_H
#define __ARCH_ARM_SRC_AT32_AT32_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "hardware/at32_exti.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* - pinset: gpio pin configuration
* - rising/falling edge: enables
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int at32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Name: at32_gpioswirq
*
* Description:
* Trigger an extended interrupt (EXTI) via software on the EXTI line
* corresponding to a GPIO pin.
*
* Input Parameters:
* pinset - GPIO pin to trigger an EXTI on.
*
****************************************************************************/
void at32_gpioswirq(uint32_t pinset);
/****************************************************************************
* Name: at32_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int at32_exti_alarm(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: at32_exti_wakeup
*
* Description:
* Sets/clears EXTI wakeup interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
int at32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_EXTI_H */

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/****************************************************************************
* arch/arm/src/at32/at32_exti_alarm.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <arch/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_gpio.h"
#include "at32_exti.h"
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to the ALARM EXTI */
static xcpt_t g_alarm_callback;
static void *g_callback_arg;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_exti_alarm_isr
*
* Description:
* EXTI ALARM interrupt service routine/dispatcher
*
****************************************************************************/
static int at32_exti_alarm_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Clear the pending EXTI interrupt */
putreg32(EXTI_RTC_ALARM, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_alarm_callback)
{
ret = g_alarm_callback(irq, context, g_callback_arg);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edge
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int at32_exti_alarm(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg)
{
g_alarm_callback = func;
g_callback_arg = arg;
/* Install external interrupt handlers (if not already attached) */
if (func)
{
irq_attach(AT32_IRQ_RTCALRM, at32_exti_alarm_isr, NULL);
up_enable_irq(AT32_IRQ_RTCALRM);
}
else
{
up_disable_irq(AT32_IRQ_RTCALRM);
}
/* Configure rising/falling edges */
modifyreg32(AT32_EXTI_RTSR,
risingedge ? 0 : EXTI_RTC_ALARM,
risingedge ? EXTI_RTC_ALARM : 0);
modifyreg32(AT32_EXTI_FTSR,
fallingedge ? 0 : EXTI_RTC_ALARM,
fallingedge ? EXTI_RTC_ALARM : 0);
/* Enable Events and Interrupts */
modifyreg32(AT32_EXTI_EMR,
event ? 0 : EXTI_RTC_ALARM,
event ? EXTI_RTC_ALARM : 0);
modifyreg32(AT32_EXTI_IMR,
func ? 0 : EXTI_RTC_ALARM,
func ? EXTI_RTC_ALARM : 0);
return OK;
}

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/****************************************************************************
* arch/arm/src/at32/at32_exti_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_gpio.h"
#include "at32_exti.h"
/****************************************************************************
* Private Types
****************************************************************************/
struct gpio_callback_s
{
xcpt_t callback;
void *arg;
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to each EXTI */
static struct gpio_callback_s g_gpio_callbacks[16];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Interrupt Service Routines - Dispatchers
****************************************************************************/
static int at32_exti0_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0001, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_gpio_callbacks[0].callback != NULL)
{
xcpt_t callback = g_gpio_callbacks[0].callback;
void *cbarg = g_gpio_callbacks[0].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
static int at32_exti1_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0002, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_gpio_callbacks[1].callback != NULL)
{
xcpt_t callback = g_gpio_callbacks[1].callback;
void *cbarg = g_gpio_callbacks[1].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
static int at32_exti2_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0004, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_gpio_callbacks[2].callback != NULL)
{
xcpt_t callback = g_gpio_callbacks[2].callback;
void *cbarg = g_gpio_callbacks[2].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
static int at32_exti3_isr(int irq, void *context, void * arg)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0008, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_gpio_callbacks[3].callback != NULL)
{
xcpt_t callback = g_gpio_callbacks[3].callback;
void *cbarg = g_gpio_callbacks[3].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
static int at32_exti4_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Clear the pending interrupt */
putreg32(0x0010, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_gpio_callbacks[4].callback != NULL)
{
xcpt_t callback = g_gpio_callbacks[4].callback;
void *cbarg = g_gpio_callbacks[4].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
static int at32_exti_multiisr(int irq, void *context, void *arg,
int first, int last)
{
uint32_t pr;
int pin;
int ret = OK;
/* Examine the state of each pin in the group */
pr = getreg32(AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
for (pin = first; pin <= last; pin++)
{
/* Is an interrupt pending on this pin? */
uint32_t mask = (1 << pin);
if ((pr & mask) != 0)
{
/* Clear the pending interrupt */
putreg32(mask, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_gpio_callbacks[pin].callback != NULL)
{
xcpt_t callback = g_gpio_callbacks[pin].callback;
void *cbarg = g_gpio_callbacks[pin].arg;
int tmp;
tmp = callback(irq, context, cbarg);
if (tmp < 0)
{
ret = tmp;
}
}
}
}
return ret;
}
static int at32_exti95_isr(int irq, void *context, void *arg)
{
return at32_exti_multiisr(irq, context, arg, 5, 9);
}
static int at32_exti1510_isr(int irq, void *context, void *arg)
{
return at32_exti_multiisr(irq, context, arg, 10, 15);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* - pinset: GPIO pin configuration
* - risingedge: Enables interrupt on rising edges
* - fallingedge: Enables interrupt on falling edges
* - event: Generate event when set
* - func: When non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int at32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg)
{
struct gpio_callback_s *shared_cbs;
uint32_t pin = pinset & GPIO_PIN_MASK;
uint32_t exti = AT32_EXTI_BIT(pin);
int irq;
xcpt_t handler;
int nshared;
int i;
/* Select the interrupt handler for this EXTI pin */
if (pin < 5)
{
irq = pin + AT32_IRQ_EXTI0;
nshared = 1;
shared_cbs = &g_gpio_callbacks[pin];
switch (pin)
{
case 0:
handler = at32_exti0_isr;
break;
case 1:
handler = at32_exti1_isr;
break;
case 2:
handler = at32_exti2_isr;
break;
case 3:
handler = at32_exti3_isr;
break;
default:
handler = at32_exti4_isr;
break;
}
}
else if (pin < 10)
{
irq = AT32_IRQ_EXTI95;
handler = at32_exti95_isr;
shared_cbs = &g_gpio_callbacks[5];
nshared = 5;
}
else
{
irq = AT32_IRQ_EXTI1510;
handler = at32_exti1510_isr;
shared_cbs = &g_gpio_callbacks[10];
nshared = 6;
}
/* Get the previous GPIO IRQ handler; Save the new IRQ handler. */
g_gpio_callbacks[pin].callback = func;
g_gpio_callbacks[pin].arg = arg;
/* Install external interrupt handlers */
if (func)
{
irq_attach(irq, handler, NULL);
up_enable_irq(irq);
}
else
{
/* Only disable IRQ if shared handler does not have any active
* callbacks.
*/
for (i = 0; i < nshared; i++)
{
if (shared_cbs[i].callback != NULL)
{
break;
}
}
if (i == nshared)
{
up_disable_irq(irq);
}
}
/* Configure GPIO, enable EXTI line enabled if event or interrupt is
* enabled.
*/
if (event || func)
{
pinset |= GPIO_EXTI;
}
at32_configgpio(pinset);
/* Configure rising/falling edges */
modifyreg32(AT32_EXTI_RTSR,
risingedge ? 0 : exti,
risingedge ? exti : 0);
modifyreg32(AT32_EXTI_FTSR,
fallingedge ? 0 : exti,
fallingedge ? exti : 0);
/* Enable Events and Interrupts */
modifyreg32(AT32_EXTI_EMR,
event ? 0 : exti,
event ? exti : 0);
modifyreg32(AT32_EXTI_IMR,
func ? 0 : exti,
func ? exti : 0);
return OK;
}
/****************************************************************************
* Name: at32_gpioswirq
*
* Description:
* Trigger an extended interrupt (EXTI) via software on the EXTI line
* corresponding to a GPIO pin.
*
* Input Parameters:
* pinset - GPIO pin to trigger an EXTI on.
*
****************************************************************************/
void at32_gpioswirq(uint32_t pinset)
{
putreg32(1u << (pinset & GPIO_PIN_MASK), AT32_EXTI_SWIER);
}

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/****************************************************************************
* arch/arm/src/at32/at32_exti_pwr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <arch/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_gpio.h"
#include "at32_exti.h"
#include "at32_exti_pwr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to the PVD EXTI */
static xcpt_t g_pvd_callback;
static void *g_callback_arg;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_exti_pvd_isr
*
* Description:
* EXTI PVD interrupt service routine/dispatcher
*
****************************************************************************/
static int at32_exti_pvd_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Clear the pending EXTI interrupt */
putreg32(EXTI_PVD_LINE, AT32_EXTI_PR);
/* And dispatch the interrupt to the handler */
if (g_pvd_callback != NULL)
{
ret = g_pvd_callback(irq, context, g_callback_arg);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_exti_pvd
*
* Description:
* Sets/clears EXTI PVD interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edge
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
int at32_exti_pvd(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg)
{
/* Get the previous GPIO IRQ handler; Save the new IRQ handler. */
g_pvd_callback = func;
g_callback_arg = arg;
/* Install external interrupt handlers (if not already attached) */
if (func)
{
irq_attach(AT32_IRQ_PVD, at32_exti_pvd_isr, NULL);
up_enable_irq(AT32_IRQ_PVD);
}
else
{
up_disable_irq(AT32_IRQ_PVD);
}
/* Configure rising/falling edges */
modifyreg32(AT32_EXTI_RTSR,
risingedge ? 0 : EXTI_PVD_LINE,
risingedge ? EXTI_PVD_LINE : 0);
modifyreg32(AT32_EXTI_FTSR,
fallingedge ? 0 : EXTI_PVD_LINE,
fallingedge ? EXTI_PVD_LINE : 0);
/* Enable Events and Interrupts */
modifyreg32(AT32_EXTI_EMR,
event ? 0 : EXTI_PVD_LINE,
event ? EXTI_PVD_LINE : 0);
modifyreg32(AT32_EXTI_IMR,
func ? 0 : EXTI_PVD_LINE,
func ? EXTI_PVD_LINE : 0);
return OK;
}

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/****************************************************************************
* arch/arm/src/at32/at32_exti_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef AT32_EXTI_PWR_H_
#define AT32_EXTI_PWR_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdbool.h>
#include <nuttx/irq.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_exti_pvd
*
* Description:
* Sets/clears EXTI PVD interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edge
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
int at32_exti_pvd(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif /* AT32_EXTI_PWR_H_ */

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/****************************************************************************
* arch/arm/src/at32/at32_exti_wakeup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <arch/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_gpio.h"
#include "at32_exti.h"
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to the RTC WAKEUP EXTI */
static xcpt_t g_wakeup_callback;
static void *g_callback_arg;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_exti_wakeup_isr
*
* Description:
* EXTI periodic WAKEUP interrupt service routine/dispatcher
*
****************************************************************************/
static int at32_exti_wakeup_isr(int irq, void *context, void *arg)
{
int ret = OK;
/* Dispatch the interrupt to the handler */
if (g_wakeup_callback != NULL)
{
ret = g_wakeup_callback(irq, context, g_callback_arg);
}
/* Clear the pending EXTI interrupt */
putreg32(EXTI_RTC_WAKEUP, AT32_EXTI_PR);
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_exti_wakeup
*
* Description:
* Sets/clears EXTI wakeup interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int at32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg)
{
g_wakeup_callback = func;
g_callback_arg = arg;
/* Install external interrupt handlers (if not already attached) */
if (func)
{
irq_attach(AT32_IRQ_RTC_WKUP, at32_exti_wakeup_isr, NULL);
up_enable_irq(AT32_IRQ_RTC_WKUP);
}
else
{
up_disable_irq(AT32_IRQ_RTC_WKUP);
}
/* Configure rising/falling edges */
modifyreg32(AT32_EXTI_RTSR,
risingedge ? 0 : EXTI_RTC_WAKEUP,
risingedge ? EXTI_RTC_WAKEUP : 0);
modifyreg32(AT32_EXTI_FTSR,
fallingedge ? 0 : EXTI_RTC_WAKEUP,
fallingedge ? EXTI_RTC_WAKEUP : 0);
/* Enable Events and Interrupts */
modifyreg32(AT32_EXTI_EMR,
event ? 0 : EXTI_RTC_WAKEUP,
event ? EXTI_RTC_WAKEUP : 0);
modifyreg32(AT32_EXTI_IMR,
func ? 0 : EXTI_RTC_WAKEUP,
func ? EXTI_RTC_WAKEUP : 0);
return OK;
}

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/****************************************************************************
* arch/arm/src/at32/at32_flash.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the correct FLASH implementation for the selection AT32 part */
#if defined (CONFIG_AT32_AT32F43XX)
# include "at32f43xx_flash.c"
#else
# warning "No FLASH support for the selected part"
#endif
/****************************************************************************
* Private Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/at32/at32_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_FLASH_H
#define __ARCH_ARM_SRC_AT32_AT32_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/progmem.h>
#include "chip.h"
#include "hardware/at32_flash.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_eeprom_size
*
* Description:
* Get EEPROM data memory size
*
* Returned Value:
* Length of EEPROM memory region
*
****************************************************************************/
size_t at32_eeprom_size(void);
/****************************************************************************
* Name: at32_eeprom_getaddress
*
* Description:
* Get EEPROM data memory address
*
* Returned Value:
* Address of EEPROM memory region
*
****************************************************************************/
size_t at32_eeprom_getaddress(void);
/****************************************************************************
* Name: at32_eeprom_write
*
* Description:
* Write buffer to EEPROM data memory address
*
* Returned Value:
* Number of written bytes or error code.
*
****************************************************************************/
ssize_t at32_eeprom_write(size_t addr, const void *buf, size_t buflen);
/****************************************************************************
* Name: at32_eeprom_erase
*
* Description:
* Erase memory on EEPROM data memory address
*
* Returned Value:
* Number of erased bytes or error code.
*
****************************************************************************/
ssize_t at32_eeprom_erase(size_t addr, size_t eraselen);
#endif /* __ARCH_ARM_SRC_AT32_AT32_FLASH_H */

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/****************************************************************************
* arch/arm/src/at32/at32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_syscfg.h"
#include "at32_gpio.h"
/****************************************************************************
* Public Data
****************************************************************************/
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[AT32_NGPIO_PORTS] =
{
#if AT32_NGPIO_PORTS > 0
AT32_GPIOA_BASE,
#endif
#if AT32_NGPIO_PORTS > 1
AT32_GPIOB_BASE,
#endif
#if AT32_NGPIO_PORTS > 2
AT32_GPIOC_BASE,
#endif
#if AT32_NGPIO_PORTS > 3
AT32_GPIOD_BASE,
#endif
#if AT32_NGPIO_PORTS > 4
AT32_GPIOE_BASE,
#endif
#if AT32_NGPIO_PORTS > 5
AT32_GPIOF_BASE,
#endif
#if AT32_NGPIO_PORTS > 6
AT32_GPIOG_BASE,
#endif
#if AT32_NGPIO_PORTS > 7
AT32_GPIOH_BASE,
#endif
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: at32_gpioremap
*
* Description:
*
* Based on configuration within the .config file, this function will
* remaps positions of alternative functions.
*
****************************************************************************/
static inline void at32_gpioremap(void)
{
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: at32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from at32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exclusion is necessary.
*
****************************************************************************/
void at32_gpioinit(void)
{
/* Remap according to the configuration within .config file */
at32_gpioremap();
}
/****************************************************************************
* Name: at32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with at32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port, or when pin is locked as ALT
* function.
*
* To-Do: Auto Power Enable
****************************************************************************/
/****************************************************************************
* Name: at32_configgpio (for the AT32F43xxx families).
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
int at32_configgpio(uint32_t cfgset)
{
uintptr_t base;
uint32_t regval;
uint32_t setting;
uint32_t alt_setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
unsigned int pos;
unsigned int pinmode;
irqstate_t flags;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= AT32_NGPIO_PORTS)
{
return -EINVAL;
}
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and select the port configuration register for that
* pin
*/
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set up the mode register (and remember whether the pin mode) */
switch (cfgset & GPIO_MODE_MASK)
{
default:
case GPIO_INPUT: /* Input mode */
pinmode = GPIO_CFGR_INPUT;
break;
case GPIO_OUTPUT: /* General purpose output mode */
/* Set the initial output value */
at32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
pinmode = GPIO_CFGR_OUTPUT;
break;
case GPIO_ALT: /* Alternate function mode */
pinmode = GPIO_CFGR_AF;
break;
case GPIO_ANALOG: /* Analog mode */
pinmode = GPIO_CFGR_ANALOG;
break;
}
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = enter_critical_section();
/* Determine the alternate function (Only alternate function pins) */
if (pinmode == GPIO_CFGR_AF)
{
alt_setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
}
else
{
alt_setting = 0;
}
/* Set the alternate function (Only alternate function pins)
* This is done before configuring the Outputs on a change to
* an Alternate function.
*/
if (alt_setting != 0)
{
if (pin < 8)
{
regoffset = AT32_GPIO_MUXL_OFFSET;
pos = pin;
}
else
{
regoffset = AT32_GPIO_MUXH_OFFSET;
pos = pin - 8;
}
regval = getreg32(base + regoffset);
regval &= ~GPIO_MUX_MASK(pos);
regval |= (alt_setting << GPIO_MUX_SHIFT(pos));
putreg32(regval, base + regoffset);
}
/* Now apply the configuration to the mode register */
regval = getreg32(base + AT32_GPIO_CFGR_OFFSET);
regval &= ~GPIO_CFGR_MASK(pin);
regval |= ((uint32_t)pinmode << GPIO_CFGR_SHIFT(pin));
putreg32(regval, base + AT32_GPIO_CFGR_OFFSET);
/* Set up the pull-up/pull-down configuration (all but analog pins) */
setting = GPIO_PULL_NONE;
if (pinmode != GPIO_CFGR_ANALOG)
{
switch (cfgset & GPIO_PUPD_MASK)
{
default:
case GPIO_FLOAT: /* No pull-up, pull-down */
break;
case GPIO_PULLUP: /* Pull-up */
setting = GPIO_PULL_PULLUP;
break;
case GPIO_PULLDOWN: /* Pull-down */
setting = GPIO_PULL_PULLDOWN;
break;
}
}
regval = getreg32(base + AT32_GPIO_PULL_OFFSET);
regval &= ~GPIO_PULL_MASK(pin);
regval |= (setting << GPIO_PULL_SHIFT(pin));
putreg32(regval, base + AT32_GPIO_PULL_OFFSET);
/* Set the alternate function (Only alternate function pins)
* This is done after configuring the the pin's connection
* on a change away from an Alternate function.
*/
if (alt_setting == 0)
{
if (pin < 8)
{
regoffset = AT32_GPIO_MUXL_OFFSET;
pos = pin;
}
else
{
regoffset = AT32_GPIO_MUXH_OFFSET;
pos = pin - 8;
}
regval = getreg32(base + regoffset);
regval &= ~GPIO_MUX_MASK(pos);
regval |= (alt_setting << GPIO_MUX_SHIFT(pos));
putreg32(regval, base + regoffset);
}
/* Set drive capability */
if (pinmode == GPIO_CFGR_OUTPUT || pinmode == GPIO_CFGR_AF)
{
switch (cfgset & GPIO_DRV_MASK)
{
case GPIO_DRV_STRONG:
setting = GPIO_ODRVR_STRONG;
break;
case GPIO_DRV_MODETATE:
setting = GPIO_ODRVR_MODERATE;
break;
}
}
else
{
setting = 0;
}
regval = getreg32(base + AT32_GPIO_ODRVR_OFFSET);
regval &= ~GPIO_ODRVR_MASK(pin);
regval |= (setting << GPIO_ODRVR_SHIFT(pin));
putreg32(regval, base + AT32_GPIO_ODRVR_OFFSET);
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
regval = getreg32(base + AT32_GPIO_OMODER_OFFSET);
setting = GPIO_OMODER_OD(pin);
if ((pinmode == GPIO_CFGR_OUTPUT || pinmode == GPIO_CFGR_AF) &&
(cfgset & GPIO_OPENDRAIN) != 0)
{
regval |= setting;
}
else
{
regval &= ~setting;
}
putreg32(regval, base + AT32_GPIO_OMODER_OFFSET);
/* Otherwise, it is an input pin. Should it configured as an EXTI
* interrupt?
*/
if (pinmode != GPIO_CFGR_OUTPUT && (cfgset & GPIO_EXTI) != 0)
{
uint32_t regaddr;
int shift;
/* Set the bits in the SYSCFG EXTICR register */
regaddr = AT32_SCFG_EXTICR(pin);
regval = getreg32(regaddr);
shift = SCFG_EXINTCR_EXTI_SHIFT(pin);
regval &= ~(SCFG_EXINTCR_PORT_MASK << shift);
regval |= (((uint32_t)port) << shift);
putreg32(regval, regaddr);
}
leave_critical_section(flags);
return OK;
}
#endif
/****************************************************************************
* Name: at32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as an alternative function
* (GPIO_ALT | GPIO_CNF_AFPP | ...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port
*
* To-Do: Auto Power Disable
****************************************************************************/
int at32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
#if defined(CONFIG_AT32_AT32F43XX)
cfgset |= GPIO_INPUT | GPIO_FLOAT;
#else
# error "Unsupported AT32 chip"
#endif
/* To-Do: Mark its unuse for automatic power saving options */
return at32_configgpio(cfgset);
}
/****************************************************************************
* Name: at32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void at32_gpiowrite(uint32_t pinset, bool value)
{
uint32_t base;
#if defined(CONFIG_AT32_AT32F43XX)
uint32_t bit;
#endif
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < AT32_NGPIO_PORTS)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set or clear the output on the pin */
#if defined(CONFIG_AT32_AT32F43XX)
if (value)
{
bit = GPIO_SCR_SET(pin);
}
else
{
bit = GPIO_SCR_RESET(pin);
}
putreg32(bit, base + AT32_GPIO_SCR_OFFSET);
#else
# error "Unsupported AT32 chip"
#endif
}
}
/****************************************************************************
* Name: at32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool at32_gpioread(uint32_t pinset)
{
uint32_t base;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < AT32_NGPIO_PORTS)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and return the input state of that pin */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
return ((getreg32(base + AT32_GPIO_IDT_OFFSET) & (1 << pin)) != 0);
}
return 0;
}
/****************************************************************************
* Name: at32_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
* supply.
*
* The I/O compensation cell can be used only when the supply voltage
* ranges from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_AT32_HAVE_IOCOMPENSATION
void at32_iocompensation(void)
{
}
#endif

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/****************************************************************************
* arch/arm/src/at32/at32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_GPIO_H
#define __ARCH_ARM_SRC_AT32_AT32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include "chip.h"
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_gpio.h"
#else
# error "Unrecognized AT32 chip"
#endif
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
/* Bit-encoded input to at32_configgpio() */
#if defined(CONFIG_AT32_AT32F43XX)
/* Each port bit of the general-purpose I/O (GPIO) ports can be
* individually configured by software in several modes:
*
* - Input floating
* - Input pull-up
* - Input-pull-down
* - Output open-drain with pull-up or pull-down capability
* - Output push-pull with pull-up or pull-down capability
* - Alternate function push-pull with pull-up or pull-down capability
* - Alternate function open-drain with pull-up or pull-down capability
* - Analog
*
* 20-bit Encoding: 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* Inputs: MMUU .... ...X PPPP BBBB
* Outputs: MMUU .... FFOV PPPP BBBB
* Alternate Functions: MMUU AAAA FFO. PPPP BBBB
* Analog: MM.. .... .... PPPP BBBB
*/
/* Mode:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* MM.. .... .... .... ....
*/
#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
/* Input/output pull-ups/downs (not used with analog):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* ..UU .... .... .... ....
*/
#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */
#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */
/* Alternate Functions:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... AAAA .... .... ....
*/
#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT)
# define GPIO_AF0 (0 << GPIO_AF_SHIFT)
# define GPIO_AF1 (1 << GPIO_AF_SHIFT)
# define GPIO_AF2 (2 << GPIO_AF_SHIFT)
# define GPIO_AF3 (3 << GPIO_AF_SHIFT)
# define GPIO_AF4 (4 << GPIO_AF_SHIFT)
# define GPIO_AF5 (5 << GPIO_AF_SHIFT)
# define GPIO_AF6 (6 << GPIO_AF_SHIFT)
# define GPIO_AF7 (7 << GPIO_AF_SHIFT)
# define GPIO_AF8 (8 << GPIO_AF_SHIFT)
# define GPIO_AF9 (9 << GPIO_AF_SHIFT)
# define GPIO_AF10 (10 << GPIO_AF_SHIFT)
# define GPIO_AF11 (11 << GPIO_AF_SHIFT)
# define GPIO_AF12 (12 << GPIO_AF_SHIFT)
# define GPIO_AF13 (13 << GPIO_AF_SHIFT)
# define GPIO_AF14 (14 << GPIO_AF_SHIFT)
# define GPIO_AF15 (15 << GPIO_AF_SHIFT)
/* Output/Alt function drive selection:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... FF.. .... ....
*/
#define GPIO_DRV_SHIFT (10)
#define GPIO_DRV_MASK (3 << GPIO_DRV_SHIFT)
#define GPIO_DRV_STRONG (1 << GPIO_DRV_SHIFT)
#define GPIO_DRV_MODETATE (0 << GPIO_DRV_SHIFT)
/* Output/Alt function type selection:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ..O. .... ....
*/
#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */
#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */
/* If the pin is a GPIO digital output, then this identifies the initial
* output value. If the pin is an input, this bit is overloaded to
* provide the qualifier to distinguish input pull-up and -down:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ...V .... ....
*/
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* External interrupt selection (GPIO inputs only):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ...X .... ....
*/
#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */
/* This identifies the GPIO port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... PPPP ....
*/
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
/* This identifies the bit in the port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... .... BBBB
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
#else
# error "Unrecognized AT32 chip"
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpiobase[AT32_NGPIO_PORTS];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with at32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
****************************************************************************/
int at32_configgpio(uint32_t cfgset);
/****************************************************************************
* Name: at32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* ERROR on invalid port
*
****************************************************************************/
int at32_unconfiggpio(uint32_t cfgset);
/****************************************************************************
* Name: at32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void at32_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: at32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool at32_gpioread(uint32_t pinset);
/****************************************************************************
* Name: at32_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
* supply.
*
* The I/O compensation cell can be used only when the supply voltage
* ranges from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_AT32_HAVE_IOCOMPENSATION
void at32_iocompensation(void);
#endif
/****************************************************************************
* Name: at32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* - pinset: gpio pin configuration
* - rising/falling edge: enables
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int at32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Function: at32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int at32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define at32_dumpgpio(p,m)
#endif
/****************************************************************************
* Function: at32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from at32_start().
*
****************************************************************************/
void at32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_GPIO_H */

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/****************************************************************************
* arch/arm/src/at32/at32_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_I2C_H
#define __ARCH_ARM_SRC_AT32_AT32_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
#include "hardware/at32_i2c.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_AT32_I2C_DYNTIMEO
# if CONFIG_AT32_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_AT32_I2C_DYNTIMEO because of CONFIG_AT32_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_AT32_I2C_DYNTIMEO
# endif
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
struct i2c_master_s *at32_i2cbus_initialize(int port);
/****************************************************************************
* Name: at32_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameters:
* Device structure as returned by the at32_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int at32_i2cbus_uninitialize(struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_AT32_AT32_I2C_H */

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/****************************************************************************
* arch/arm/src/at32/at32_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "at32_pm.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
at32_pmstop(true);
break;
case PM_SLEEP:
at32_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power.
*
*
* "2.17.11 Ethernet DMA not working after WFI/WFE instruction
* Description
* If a WFI/WFE instruction is executed to put the system in sleep mode
* while the Ethernet MAC master clock on the AHB bus matrix is ON and
* all remaining masters clocks are OFF, the Ethernet DMA will be not
* able to perform any AHB master accesses during sleep mode."
*
* Workaround
* Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before
* executing the WFI/WFE instruction."
*
*/
#if !defined(CONFIG_AT32_CONNECTIVITYLINE) || !defined(CONFIG_AT32_ETHMAC)
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_AT32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
#endif
}

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/****************************************************************************
* arch/arm/src/at32/at32_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
#include "nvic.h"
#ifdef CONFIG_ARCH_RAMVECTORS
# include "ram_vectors.h"
#endif
#include "arm_internal.h"
#include "at32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void at32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else
# define at32_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: at32_nmi, at32_pendsv,
* at32_dbgmonitor, at32_pendsv, at32_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int at32_nmi(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int at32_pendsv(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int at32_dbgmonitor(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int at32_reserved(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: at32_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_USEBASEPRI
static inline void at32_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: at32_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int at32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= AT32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= AT32_IRQ_FIRST)
{
n = irq - AT32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == AT32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == AT32_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == AT32_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == AT32_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < NR_IRQS - AT32_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
#if defined(__ICCARM__)
putreg32((uint32_t)__vector_table, NVIC_VECTAB);
#else
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
arm_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(AT32_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(AT32_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(AT32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
at32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARM_MPU
irq_attach(AT32_IRQ_MEMFAULT, arm_memfault, NULL);
up_enable_irq(AT32_IRQ_MEMFAULT);
#endif
#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL)
/* RTC was initialized earlier but IRQs weren't ready at that time */
at32_rtc_irqinitialize();
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(AT32_IRQ_NMI, at32_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(AT32_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(AT32_IRQ_BUSFAULT, arm_busfault, NULL);
irq_attach(AT32_IRQ_USAGEFAULT, arm_usagefault, NULL);
irq_attach(AT32_IRQ_PENDSV, at32_pendsv, NULL);
irq_attach(AT32_IRQ_DBGMONITOR, at32_dbgmonitor, NULL);
irq_attach(AT32_IRQ_RESERVED, at32_reserved, NULL);
#endif
at32_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (at32_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= AT32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (at32_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= AT32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= AT32_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < AT32_IRQ_FIRST)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= AT32_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
at32_dumpnvic("prioritize", irq);
return OK;
}
#endif

696
arch/arm/src/at32/at32_iwdg.c Normal file
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@ -0,0 +1,696 @@
/****************************************************************************
* arch/arm/src/at32/at32_iwdg.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <inttypes.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/timers/watchdog.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "at32_rcc.h"
#include "hardware/at32_dbgmcu.h"
#include "at32_wdg.h"
#if defined(CONFIG_WATCHDOG) && defined(CONFIG_AT32_IWDG)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The minimum frequency of the IWDG clock is:
*
* Fmin = Flsi / 256
*
* So the maximum delay (in milliseconds) is then:
*
* 1000 * IWDG_RLR_MAX / Fmin
*
* For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the
* maximum delay is:
*
* Fmin = 117.1875
* 1000 * 4095 / Fmin = 34,944 MSec
*/
#define IWDG_FMIN (AT32_LSI_FREQUENCY / 256)
#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN)
/* Configuration ************************************************************/
#ifndef CONFIG_AT32_IWDG_DEFTIMOUT
# define CONFIG_AT32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT
#endif
#ifndef CONFIG_DEBUG_WATCHDOG_INFO
# undef CONFIG_AT32_IWDG_REGDEBUG
#endif
/* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never go
* to zero. So we defer setting up these registers until the watchdog
* is started, then refuse any further attempts to change timeout.
*/
#define CONFIG_AT32_IWDG_ONETIMESETUP 1
/* REVISIT: Another possibility is that we CAN change the prescaler and
* reload values after starting the timer. This option is untested but the
* implementation place conditioned on the following:
*/
#undef CONFIG_AT32_IWDG_DEFERREDSETUP
/* But you can only try one at a time */
#if defined(CONFIG_AT32_IWDG_ONETIMESETUP) && defined(CONFIG_AT32_IWDG_DEFERREDSETUP)
# error "Both CONFIG_AT32_IWDG_ONETIMESETUP and CONFIG_AT32_IWDG_DEFERREDSETUP are defined"
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
*/
struct at32_lowerhalf_s
{
const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_AT32_IWDG_REGDEBUG
static uint16_t at32_getreg(uint32_t addr);
static void at32_putreg(uint16_t val, uint32_t addr);
#else
# define at32_getreg(addr) getreg16(addr)
# define at32_putreg(val,addr) putreg16(val,addr)
#endif
static inline void at32_setprescaler(struct at32_lowerhalf_s *priv);
/* "Lower half" driver methods **********************************************/
static int at32_start(struct watchdog_lowerhalf_s *lower);
static int at32_stop(struct watchdog_lowerhalf_s *lower);
static int at32_keepalive(struct watchdog_lowerhalf_s *lower);
static int at32_getstatus(struct watchdog_lowerhalf_s *lower,
struct watchdog_status_s *status);
static int at32_settimeout(struct watchdog_lowerhalf_s *lower,
uint32_t timeout);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
{
.start = at32_start,
.stop = at32_stop,
.keepalive = at32_keepalive,
.getstatus = at32_getstatus,
.settimeout = at32_settimeout,
.capture = NULL,
.ioctl = NULL,
};
/* "Lower half" driver state */
static struct at32_lowerhalf_s g_wdgdev;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_getreg
*
* Description:
* Get the contents of an AT32 IWDG register
*
****************************************************************************/
#ifdef CONFIG_AT32_IWDG_REGDEBUG
static uint16_t at32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
static uint32_t count = 0;
static uint16_t preval = 0;
/* Read the value from the register */
uint16_t val = getreg16(addr);
/* Is this the same value that we read from the same register last time?
* Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
wdinfo("...\n");
}
return val;
}
}
/* No this is a new address or value */
else
{
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
wdinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
/****************************************************************************
* Name: at32_putreg
*
* Description:
* Set the contents of an AT32 register to a value
*
****************************************************************************/
#ifdef CONFIG_AT32_IWDG_REGDEBUG
static void at32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
wdinfo("%08x<-%04x\n", addr, val);
/* Write the value */
putreg16(val, addr);
}
#endif
/****************************************************************************
* Name: at32_setprescaler
*
* Description:
* Set up the prescaler and reload values. This seems to be something
* that can only be done one time.
*
* Input Parameters:
* priv - A pointer the internal representation of the "lower-half"
* driver state structure.
*
****************************************************************************/
static inline void at32_setprescaler(struct at32_lowerhalf_s *priv)
{
/* Enable write access to IWDG_PR and IWDG_RLR registers */
at32_putreg(IWDG_KR_KEY_ENABLE, AT32_IWDG_KR);
/* Wait for the PVU and RVU bits to be reset be hardware. These bits
* were set the last time that the PR register was written and may not
* yet be cleared.
*
* If the setup is only permitted one time, then this wait should not
* be necessary.
*/
#ifndef CONFIG_AT32_IWDG_ONETIMESETUP
while ((at32_getreg(AT32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0);
#endif
/* Set the prescaler */
at32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, AT32_IWDG_PR);
/* Set the reload value */
at32_putreg((uint16_t)priv->reload, AT32_IWDG_RLR);
/* Reload the counter (and disable write access) */
at32_putreg(IWDG_KR_KEY_RELOAD, AT32_IWDG_KR);
}
/****************************************************************************
* Name: at32_start
*
* Description:
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_start(struct watchdog_lowerhalf_s *lower)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
irqstate_t flags;
wdinfo("Entry: started\n");
DEBUGASSERT(priv);
/* Have we already been started? */
if (!priv->started)
{
/* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never
* go to 0. So we defer setting up these registers until the watchdog
* is started, then refuse any further attempts to change timeout.
*/
/* Set up prescaler and reload value for the selected timeout before
* starting the watchdog timer.
*/
#if defined(CONFIG_AT32_IWDG_ONETIMESETUP) || defined(CONFIG_AT32_IWDG_DEFERREDSETUP)
at32_setprescaler(priv);
#endif
/* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
* If the "Hardware watchdog" feature is enabled through the device
* option bits, the watchdog is automatically enabled at power-on.
*/
flags = enter_critical_section();
at32_putreg(IWDG_KR_KEY_START, AT32_IWDG_KR);
priv->lastreset = clock_systime_ticks();
priv->started = true;
leave_critical_section(flags);
}
return OK;
}
/****************************************************************************
* Name: at32_stop
*
* Description:
* Stop the watchdog timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_stop(struct watchdog_lowerhalf_s *lower)
{
/* There is no way to disable the IDWG timer once it has been started */
wdinfo("Entry\n");
return -ENOSYS;
}
/****************************************************************************
* Name: at32_keepalive
*
* Description:
* Reset the watchdog timer to the current timeout value, prevent any
* imminent watchdog timeouts. This is sometimes referred as "pinging"
* the watchdog timer or "petting the dog".
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_keepalive(struct watchdog_lowerhalf_s *lower)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
irqstate_t flags;
wdinfo("Entry\n");
/* Reload the IWDG timer */
flags = enter_critical_section();
at32_putreg(IWDG_KR_KEY_RELOAD, AT32_IWDG_KR);
priv->lastreset = clock_systime_ticks();
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: at32_getstatus
*
* Description:
* Get the current watchdog timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_getstatus(struct watchdog_lowerhalf_s *lower,
struct watchdog_status_s *status)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
uint32_t ticks;
uint32_t elapsed;
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
status->flags = WDFLAGS_RESET;
if (priv->started)
{
status->flags |= WDFLAGS_ACTIVE;
}
/* Return the actual timeout in milliseconds */
status->timeout = priv->timeout;
/* Get the elapsed time since the last ping */
ticks = clock_systime_ticks() - priv->lastreset;
elapsed = (int32_t)TICK2MSEC(ticks);
if (elapsed > priv->timeout)
{
elapsed = priv->timeout;
}
/* Return the approximate time until the watchdog timer expiration */
status->timeleft = priv->timeout - elapsed;
wdinfo("Status :\n");
wdinfo(" flags : %08" PRIx32 "\n", status->flags);
wdinfo(" timeout : %" PRId32 "\n", status->timeout);
wdinfo(" timeleft : %" PRId32 "\n", status->timeleft);
return OK;
}
/****************************************************************************
* Name: at32_settimeout
*
* Description:
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_settimeout(struct watchdog_lowerhalf_s *lower,
uint32_t timeout)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
uint32_t fiwdg;
uint64_t reload;
int prescaler;
int shift;
wdinfo("Entry: timeout=%" PRId32 "\n", timeout);
DEBUGASSERT(priv);
/* Can this timeout be represented? */
if (timeout < 1 || timeout > IWDG_MAXTIMEOUT)
{
wderr("ERROR: Cannot represent timeout=%" PRId32 " > %d\n",
timeout, IWDG_MAXTIMEOUT);
return -ERANGE;
}
/* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never go
* to zero.
*/
#ifdef CONFIG_AT32_IWDG_ONETIMESETUP
if (priv->started)
{
wdwarn("WARNING: Timer is already started\n");
return -EBUSY;
}
#endif
/* Select the smallest prescaler that will result in a reload value that is
* less than the maximum.
*/
for (prescaler = 0; ; prescaler++)
{
/* PR = 0 -> Divider = 4 = 1 << 2
* PR = 1 -> Divider = 8 = 1 << 3
* PR = 2 -> Divider = 16 = 1 << 4
* PR = 3 -> Divider = 32 = 1 << 5
* PR = 4 -> Divider = 64 = 1 << 6
* PR = 5 -> Divider = 128 = 1 << 7
* PR = 6 -> Divider = 256 = 1 << 8
* PR = n -> Divider = 1 << (n+2)
*/
shift = prescaler + 2;
/* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
* this is value in the range of 7500 and 125.
*/
fiwdg = priv->lsifreq >> shift;
/* We want:
* 1000 * reload / Fiwdg = timeout
* Or:
* reload = Fiwdg * timeout / 1000
*/
reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000;
/* If this reload valid is less than the maximum or we are not ready
* at the prescaler value, then break out of the loop to use these
* settings.
*/
if (reload <= IWDG_RLR_MAX || prescaler == 6)
{
/* Note that we explicitly break out of the loop rather than using
* the 'for' loop termination logic because we do not want the
* value of prescaler to be incremented.
*/
break;
}
}
/* Make sure that the final reload value is within range */
if (reload > IWDG_RLR_MAX)
{
reload = IWDG_RLR_MAX;
}
/* Get the actual timeout value in milliseconds.
*
* We have:
* reload = Fiwdg * timeout / 1000
* So we want:
* timeout = 1000 * reload / Fiwdg
*/
priv->timeout = (1000 * (uint32_t)reload) / fiwdg;
/* Save setup values for later use */
priv->prescaler = prescaler;
priv->reload = reload;
/* Write the prescaler and reload values to the IWDG registers.
*
* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never go
* to zero.
*/
#ifndef CONFIG_AT32_IWDG_ONETIMESETUP
/* If CONFIG_AT32_IWDG_DEFERREDSETUP is selected, then perform the
* register configuration only if the timer has been started.
*/
#ifdef CONFIG_AT32_IWDG_DEFERREDSETUP
if (priv->started)
#endif
{
at32_setprescaler(priv);
}
#endif
wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n",
prescaler, fiwdg, reload);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog timer. The watchdog timer is initialized
* and registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
* Returned Value:
* None
*
****************************************************************************/
void at32_iwdginitialize(const char *devpath, uint32_t lsifreq)
{
struct at32_lowerhalf_s *priv = &g_wdgdev;
wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq);
/* NOTE we assume that clocking to the IWDG has already been provided by
* the RCC initialization logic.
*/
/* Initialize the driver state structure. */
priv->ops = &g_wdgops;
priv->lsifreq = lsifreq;
priv->started = false;
/* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator
* is enabled here but is not disabled by this file, because this file does
* not know the global usage of the oscillator. Any clock management
* logic (say, as part of a power management scheme) needs handle other
* LSI controls outside of this file.
*/
at32_rcc_enablelsi();
wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(AT32_CRM_CTRLSTS));
/* Select an arbitrary initial timeout value. But don't start the watchdog
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
* device option bits, the watchdog is automatically enabled at power-on.
*/
at32_settimeout((struct watchdog_lowerhalf_s *)priv,
CONFIG_AT32_IWDG_DEFTIMOUT);
/* Register the watchdog driver as /dev/watchdog0 */
watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv);
/* When the microcontroller enters debug mode (Cortex-M4F core halted),
* the IWDG counter either continues to work normally or stops, depending
* on DBG_IWDG_STOP configuration bit in DBG module.
*/
#if defined(CONFIG_AT32_JTAG_FULL_ENABLE) || \
defined(CONFIG_AT32_JTAG_NOJNTRST_ENABLE) || \
defined(CONFIG_AT32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_AT32_AT32F43XX)
uint32_t cr = getreg32(AT32_DEBUG_APB1_PAUSE);
cr |= DEBUG_APB1_APUSE_WDT_PAUSE;
putreg32(cr, AT32_DEBUG_APB1_PAUSE);
#endif
}
#endif
}
#endif /* CONFIG_WATCHDOG && CONFIG_AT32_IWDG */

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/****************************************************************************
* arch/arm/src/at32/at32_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32.h"
#include "at32_rcc.h"
#include "at32_gpio.h"
#include "at32_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select USART parameters for the selected console */
#ifdef HAVE_CONSOLE
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_USART1_BASE
# define AT32_APBCLOCK AT32_PCLK2_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB2EN
# define AT32_CONSOLE_APBEN CRM_APB2EN_USART1EN
# define AT32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define AT32_CONSOLE_BITS CONFIG_USART1_BITS
# define AT32_CONSOLE_PARITY CONFIG_USART1_PARITY
# define AT32_CONSOLE_2STOP CONFIG_USART1_2STOP
# define AT32_CONSOLE_TX GPIO_USART1_TX
# define AT32_CONSOLE_RX GPIO_USART1_RX
# ifdef CONFIG_USART1_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_USART2_BASE
# define AT32_APBCLOCK AT32_PCLK1_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB1EN
# define AT32_CONSOLE_APBEN CRM_APB1EN_USART2EN
# define AT32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define AT32_CONSOLE_BITS CONFIG_USART2_BITS
# define AT32_CONSOLE_PARITY CONFIG_USART2_PARITY
# define AT32_CONSOLE_2STOP CONFIG_USART2_2STOP
# define AT32_CONSOLE_TX GPIO_USART2_TX
# define AT32_CONSOLE_RX GPIO_USART2_RX
# ifdef CONFIG_USART2_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_USART3_BASE
# define AT32_APBCLOCK AT32_PCLK1_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB1EN
# define AT32_CONSOLE_APBEN CRM_APB1EN_USART3EN
# define AT32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define AT32_CONSOLE_BITS CONFIG_USART3_BITS
# define AT32_CONSOLE_PARITY CONFIG_USART3_PARITY
# define AT32_CONSOLE_2STOP CONFIG_USART3_2STOP
# define AT32_CONSOLE_TX GPIO_USART3_TX
# define AT32_CONSOLE_RX GPIO_USART3_RX
# ifdef CONFIG_USART3_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_UART4_BASE
# define AT32_APBCLOCK AT32_PCLK1_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB1EN
# define AT32_CONSOLE_APBEN CRM_APB1EN_UART4EN
# define AT32_CONSOLE_BAUD CONFIG_UART4_BAUD
# define AT32_CONSOLE_BITS CONFIG_UART4_BITS
# define AT32_CONSOLE_PARITY CONFIG_UART4_PARITY
# define AT32_CONSOLE_2STOP CONFIG_UART4_2STOP
# define AT32_CONSOLE_TX GPIO_UART4_TX
# define AT32_CONSOLE_RX GPIO_UART4_RX
# ifdef CONFIG_UART4_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_UART5_BASE
# define AT32_APBCLOCK AT32_PCLK1_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB1EN
# define AT32_CONSOLE_APBEN CRM_APB1EN_UART4EN
# define AT32_CONSOLE_BAUD CONFIG_UART5_BAUD
# define AT32_CONSOLE_BITS CONFIG_UART5_BITS
# define AT32_CONSOLE_PARITY CONFIG_UART5_PARITY
# define AT32_CONSOLE_2STOP CONFIG_UART5_2STOP
# define AT32_CONSOLE_TX GPIO_UART5_TX
# define AT32_CONSOLE_RX GPIO_UART5_RX
# ifdef CONFIG_UART5_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_USART6_BASE
# define AT32_APBCLOCK AT32_PCLK2_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB2EN
# define AT32_CONSOLE_APBEN CRM_APB2EN_USART6EN
# define AT32_CONSOLE_BAUD CONFIG_USART6_BAUD
# define AT32_CONSOLE_BITS CONFIG_USART6_BITS
# define AT32_CONSOLE_PARITY CONFIG_USART6_PARITY
# define AT32_CONSOLE_2STOP CONFIG_USART6_2STOP
# define AT32_CONSOLE_TX GPIO_USART6_TX
# define AT32_CONSOLE_RX GPIO_USART6_RX
# ifdef CONFIG_USART6_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_UART7_BASE
# define AT32_APBCLOCK AT32_PCLK1_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB1EN
# define AT32_CONSOLE_APBEN CRM_APB1EN_UART7EN
# define AT32_CONSOLE_BAUD CONFIG_UART7_BAUD
# define AT32_CONSOLE_BITS CONFIG_UART7_BITS
# define AT32_CONSOLE_PARITY CONFIG_UART7_PARITY
# define AT32_CONSOLE_2STOP CONFIG_UART7_2STOP
# define AT32_CONSOLE_TX GPIO_UART7_TX
# define AT32_CONSOLE_RX GPIO_UART7_RX
# ifdef CONFIG_UART7_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR
# if (CONFIG_UART7_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
# define AT32_CONSOLE_BASE AT32_UART8_BASE
# define AT32_APBCLOCK AT32_PCLK1_FREQUENCY
# define AT32_CONSOLE_APBREG AT32_CRM_APB1EN
# define AT32_CONSOLE_APBEN CRM_APB1EN_UART8EN
# define AT32_CONSOLE_BAUD CONFIG_UART8_BAUD
# define AT32_CONSOLE_BITS CONFIG_UART8_BITS
# define AT32_CONSOLE_PARITY CONFIG_UART8_PARITY
# define AT32_CONSOLE_2STOP CONFIG_UART8_2STOP
# define AT32_CONSOLE_TX GPIO_UART8_TX
# define AT32_CONSOLE_RX GPIO_UART8_RX
# ifdef CONFIG_UART8_RS485
# define AT32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR
# if (CONFIG_UART8_RS485_DIR_POLARITY == 0)
# define AT32_CONSOLE_RS485_DIR_POLARITY false
# else
# define AT32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */
# if AT32_CONSOLE_BITS == 9
# define USART_CR1_M_VALUE (USART_CTRL1_DBN0 | (~USART_CTRL1_DBN1))
# elif AT32_CONSOLE_BITS == 7
# define USART_CR1_M_VALUE ((~USART_CTRL1_DBN0) | USART_CTRL1_DBN1)
# else
# define USART_CR1_M_VALUE 0
# endif
# if AT32_CONSOLE_PARITY == 1
# define USART_CR1_PARITY_VALUE (USART_CTRL1_PEN|USART_CTRL1_PSEL)
# elif AT32_CONSOLE_PARITY == 2
# define USART_CR1_PARITY_VALUE USART_CTRL1_PEN
# else
# define USART_CR1_PARITY_VALUE 0
# endif
# define USART_CR1_CLRBITS\
(USART_CTRL1_DBN0 | USART_CTRL1_DBN1 | USART_CTRL1_PEN | USART_CTRL1_PSEL | \
USART_CTRL1_TEN | USART_CTRL1_REN | USART_CTRL1_IDLEIEN | USART_CTRL1_RDBFIEN | \
USART_CTRL1_TDCIEN |USART_CTRL1_TDBEIEN | USART_CTRL1_PERRIEN)
# define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE)
/* CR2 settings */
# if AT32_CONSOLE_2STOP != 0
# define USART_CR2_STOP2_VALUE USART_CTRL2_STOPBN_20
# else
# define USART_CR2_STOP2_VALUE 0
# endif
# define USART_CR2_CLRBITS \
(USART_CTRL2_STOPBN_MASK | USART_CTRL2_CLKEN | USART_CTRL2_CLKPOL | USART_CTRL2_CLKPHA | \
USART_CTRL2_LBCP | USART_CTRL2_BFIEN)
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
/* CR3 settings */
# define USART_CR3_CLRBITS \
(USART_CTRL3_CTSCFIEN | USART_CTRL3_CTSEN | USART_CTRL3_RTSEN | USART_CTRL3_ERRIEN)
# define USART_CR3_SETBITS 0
#endif /* HAVE_CONSOLE */
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(AT32_CONSOLE_BASE + AT32_USART_STS_OFFSET) &
USART_STS_TDC) == 0);
#ifdef AT32_CONSOLE_RS485_DIR
at32_gpiowrite(AT32_CONSOLE_RS485_DIR,
AT32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
putreg32((uint32_t)ch, AT32_CONSOLE_BASE + AT32_USART_DT_OFFSET);
#ifdef AT32_CONSOLE_RS485_DIR
while ((getreg32(AT32_CONSOLE_BASE + AT32_USART_STS_OFFSET) &
USART_STS_TDC) == 0);
at32_gpiowrite(AT32_CONSOLE_RS485_DIR,
!AT32_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: at32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
void at32_lowsetup(void)
{
#if defined(HAVE_SERIALDRIVER)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
modifyreg32(AT32_CONSOLE_APBREG, 0, AT32_CONSOLE_APBEN);
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in at32_rcc.c
*/
#ifdef AT32_CONSOLE_TX
at32_configgpio(AT32_CONSOLE_TX);
#endif
#ifdef AT32_CONSOLE_RX
at32_configgpio(AT32_CONSOLE_RX);
#endif
#ifdef AT32_CONSOLE_RS485_DIR
at32_configgpio(AT32_CONSOLE_RS485_DIR);
at32_gpiowrite(AT32_CONSOLE_RS485_DIR,
!AT32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Enable and configure the selected console device */
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Ensure the USART is disabled because some bits of the following
* registers cannot be modified otherwise.
*
* Although the USART is expected to be disabled at power on reset, this
* might not be the case if we boot from a serial bootloader that does not
* clean up properly.
*/
cr = getreg32(AT32_CONSOLE_BASE + AT32_USART_CTRL1_OFFSET);
cr &= ~USART_CTRL1_UEN;
putreg32(cr, AT32_CONSOLE_BASE + AT32_USART_CTRL1_OFFSET);
/* Configure CR2 */
cr = getreg32(AT32_CONSOLE_BASE + AT32_USART_CTRL2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg32(cr, AT32_CONSOLE_BASE + AT32_USART_CTRL2_OFFSET);
/* Configure CR1 */
cr = getreg32(AT32_CONSOLE_BASE + AT32_USART_CTRL1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg32(cr, AT32_CONSOLE_BASE + AT32_USART_CTRL1_OFFSET);
/* Configure CR3 */
cr = getreg32(AT32_CONSOLE_BASE + AT32_USART_CTRL3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg32(cr, AT32_CONSOLE_BASE + AT32_USART_CTRL3_OFFSET);
/* Configure the USART Baud Rate */
uint32_t temp_val = (AT32_APBCLOCK * 10 / AT32_CONSOLE_BAUD);
temp_val = ((temp_val % 10) < 5) ? (temp_val / 10) : (temp_val / 10 + 1);
putreg32(temp_val, AT32_CONSOLE_BASE + AT32_USART_BAUDR_OFFSET);
/* Enable Rx, Tx, and the USART */
cr |= (USART_CTRL1_UEN | USART_CTRL1_TEN | USART_CTRL1_REN);
putreg32(cr, AT32_CONSOLE_BASE + AT32_USART_CTRL1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_SERIALDRIVER */
}
#else
# error "Unsupported AT32 chip"
#endif

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/****************************************************************************
* arch/arm/src/at32/at32_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_LOWPUTC_H
#define __ARCH_ARM_SRC_AT32_AT32_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: at32_lowsetup
*
* Description:
* Called at the very beginning of _start.
* Performs low level initialization of serial console.
*
****************************************************************************/
void at32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/at32/at32_lse.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "at32_pwr.h"
#include "at32_rcc.h"
#include "at32_waste.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) oscillator.
*
* Todo:
* Check for LSE good timeout and return with -1,
*
****************************************************************************/
void at32_rcc_enablelse(void)
{
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
at32_pwr_enablebkp(true);
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC BDCR register.
*/
modifyreg16(AT32_CRM_BPDC, 0, CRM_BPDC_LEXTEN);
/* Wait for the LSE clock to be ready */
while ((getreg16(AT32_CRM_BPDC) & CRM_BPDC_LEXTSTBL) == 0)
{
at32_waste();
}
/* Disable backup domain access if it was disabled on entry */
at32_pwr_enablebkp(false);
}

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/****************************************************************************
* arch/arm/src/at32/at32_lsi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "at32_rcc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void at32_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit in the CRM CTRLSTS register.
*/
modifyreg32(AT32_CRM_CTRLSTS, 0, CRM_CTRLSTS_LICKEN);
/* Wait for the internal RC 40 kHz oscillator to be stable. */
while ((getreg32(AT32_CRM_CTRLSTS) & CRM_CTRLSTS_LICKSTBL) == 0);
}
/****************************************************************************
* Name: at32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void at32_rcc_disablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit in the CRM CTRLSTS register.
*/
modifyreg32(AT32_CRM_CTRLSTS, CRM_CTRLSTS_LICKEN, 0);
/* LSIRDY should go low after 3 LSI clock cycles */
}

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/****************************************************************************
* arch/arm/src/at32/at32_mpuinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <sys/param.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "at32_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
*
****************************************************************************/
void at32_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Reset MPU if enabled */
mpu_reset();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: at32_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void at32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */

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/****************************************************************************
* arch/arm/src/at32/at32_mpuinit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_MPUINIT_H
#define __ARCH_ARM_SRC_AT32_AT32_MPUINIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void at32_mpuinitialize(void);
#else
# define at32_mpuinitialize()
#endif
/****************************************************************************
* Name: at32_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void at32_mpu_uheap(uintptr_t start, size_t size);
#else
# define at32_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_AT32_AT32_MPUINIT_H */

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/****************************************************************************
* arch/arm/src/at32/at32_otgfs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_OTGFS_H
#define __ARCH_ARM_SRC_AT32_AT32_OTGFS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "at32.h"
#include "hardware/at32fxxxxx_otgfs.h"
#if defined(CONFIG_AT32_OTGFS)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: at32_otgfshost_initialize
*
* Description:
* Initialize USB host device controller hardware.
*
* Input Parameters:
* controller -- If the device supports more than USB host controller,
* then this identifies which controller is being initializeed.
* Normally, this is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
* use this interface to (1) call the wait() method to wait for a device
* to be connected, and (2) call the enumerate() method to bind the device
* to a class driver.
*
* Assumptions:
* - This function should called in the initialization sequence in order to
* initialize the USB device functionality.
* - Class drivers should be initialized prior to calling this function.
* Otherwise, there is a race condition if the device is already
* connected.
*
****************************************************************************/
#ifdef CONFIG_AT32_USBHOST
struct usbhost_connection_s;
struct usbhost_connection_s *at32_otgfshost_initialize(int controller);
#endif
/****************************************************************************
* Name: at32_usbsuspend
*
* Description:
* Board logic must provide the at32_usbsuspend logic if the OTG FS
* device driver is used. This function is called whenever the USB enters
* or leaves suspend mode. This is an opportunity for the board logic to
* shutdown clocks, power, etc. while the USB is suspended.
*
****************************************************************************/
void at32_usbsuspend(struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_AT32_OTGFS */
#endif /* __ARCH_ARM_SRC_AT32_AT32_OTGFS_H */

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/****************************************************************************
* arch/arm/src/at32/at32_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_PM_H
#define __ARCH_ARM_SRC_AT32_AT32_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_pmstop
*
* Description:
* Enter STOP mode.
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
* internal voltage regulator in low-power mode using the LPDS bit
* of the Power control register (PWR_CR).
*
* Returned Value:
* Zero means that the STOP was successfully entered and the system has
* been re-awakened. The internal voltage regulator is back to its
* original state. Otherwise, STOP mode did not occur and a negated
* errno value is returned to indicate the cause of the failure.
*
****************************************************************************/
int at32_pmstop(bool lpds);
/****************************************************************************
* Name: at32_pmstandby
*
* Description:
* Enter STANDBY mode.
*
* Input Parameters:
* None
*
* Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
* failure.
*
****************************************************************************/
int at32_pmstandby(void);
/****************************************************************************
* Name: at32_pmsleep
*
* Description:
* Enter SLEEP mode.
*
* Input Parameters:
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
* mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
****************************************************************************/
void at32_pmsleep(bool sleeponexit);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_PM_H */

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/****************************************************************************
* arch/arm/src/at32/at32_pminitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/power/pm.h>
#include "arm_internal.h"
#include "at32_pm.h"
#ifdef CONFIG_PM
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_pminitialize
*
* Description:
* This function is called by MCU-specific logic at power-on reset in
* order to provide one-time initialization the power management subsystem.
* This function must be called *very* early in the initialization sequence
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void arm_pminitialize(void)
{
/* Initialize the NuttX power management subsystem proper */
pm_initialize();
}
#endif /* CONFIG_PM */

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/****************************************************************************
* arch/arm/src/at32/at32_pmsleep.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "nvic.h"
#include "at32_pwr.h"
#include "at32_pm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_pmsleep
*
* Description:
* Enter SLEEP mode.
*
* Input Parameters:
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
* mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
****************************************************************************/
void at32_pmsleep(bool sleeponexit)
{
uint32_t regval;
/* Clear SLEEPDEEP bit of Cortex System Control Register */
regval = getreg32(NVIC_SYSCON);
regval &= ~NVIC_SYSCON_SLEEPDEEP;
if (sleeponexit)
{
regval |= NVIC_SYSCON_SLEEPONEXIT;
}
else
{
regval &= ~NVIC_SYSCON_SLEEPONEXIT;
}
putreg32(regval, NVIC_SYSCON);
/* Sleep until the wakeup interrupt or event occurs */
#ifdef CONFIG_PM_WFE
/* Mode: SLEEP + Entry with WFE */
asm("wfe");
#else
/* Mode: SLEEP + Entry with WFI */
asm("wfi");
#endif
}

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/****************************************************************************
* arch/arm/src/at32/at32_pmstandby.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "nvic.h"
#include "at32_pwr.h"
#include "at32_pm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_pmstandby
*
* Description:
* Enter STANDBY mode.
*
* Input Parameters:
* None
*
* Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
* failure.
*
****************************************************************************/
int at32_pmstandby(void)
{
uint32_t regval;
/* Clear the Wake-Up Flag by setting the CWUF bit in the power control
* register.
*/
regval = getreg32(AT32_PWC_CTRL);
regval |= PWC_CTRL_CLSWEF;
putreg32(regval, AT32_PWC_CTRL);
/* Set the Power Down Deep Sleep (PDDS) bit in the power control
* register.
*/
regval |= PWC_CTRL_LPSEL;
putreg32(regval, AT32_PWC_CTRL);
/* Set SLEEPDEEP bit of Cortex System Control Register */
regval = getreg32(NVIC_SYSCON);
regval |= NVIC_SYSCON_SLEEPDEEP;
putreg32(regval, NVIC_SYSCON);
/* Sleep until the wakeup reset occurs */
asm("wfi");
return OK; /* Won't get here */
}

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/****************************************************************************
* arch/arm/src/at32/at32_pmstop.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "nvic.h"
#include "at32_pwr.h"
#include "at32_pm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_pmstop
*
* Description:
* Enter STOP mode.
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
* internal voltage regulator in low-power mode using the LPDS bit
* of the Power control register (PWR_CR).
*
* Returned Value:
* Zero means that the STOP was successfully entered and the system has
* been re-awakened. The internal voltage regulator is back to its
* original state. Otherwise, STOP mode did not occur and a negated
* errno value is returned to indicate the cause of the failure.
*
****************************************************************************/
int at32_pmstop(bool lpds)
{
uint32_t regval;
/* Clear the Power Down Deep Sleep (PDDS) and the Low Power Deep Sleep
* (LPDS)) bits in the power control register.
*/
regval = getreg32(AT32_PWC_CTRL);
regval &= ~(PWC_CTRL_VRSEL | PWC_CTRL_LPSEL);
/* Set the Low Power Deep Sleep (LPDS) bit if so requested */
if (lpds)
{
regval |= PWC_CTRL_VRSEL;
}
putreg32(regval, AT32_PWC_CTRL);
/* Set SLEEPDEEP bit of Cortex System Control Register */
regval = getreg32(NVIC_SYSCON);
regval |= NVIC_SYSCON_SLEEPDEEP;
putreg32(regval, NVIC_SYSCON);
/* Sleep until the wakeup interrupt or event occurs */
#ifdef CONFIG_PM_WFE
/* Mode: SLEEP + Entry with WFE */
asm("wfe");
#else
/* Mode: SLEEP + Entry with WFI */
asm("wfi");
#endif
return OK;
}

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/****************************************************************************
* arch/arm/src/at32/at32_pwr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "at32_pwr.h"
#if defined(CONFIG_AT32_PWR)
/****************************************************************************
* Private Data
****************************************************************************/
/* Wakeup Pin Definitions: See chip/at32_pwr.h */
#undef HAVE_PWR_WKUP2
#undef HAVE_PWR_WKUP3
#if defined(CONFIG_AT32_AT32F43XXX)
# define HAVE_PWR_WKUP2 1
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static uint16_t g_bkp_writable_counter = 0;
/****************************************************************************
* Private Functions
****************************************************************************/
static inline uint32_t at32_pwr_getreg32(uint8_t offset)
{
return getreg32(AT32_PWC_BASE + (uint32_t)offset);
}
static inline void at32_pwr_putreg32(uint8_t offset, uint32_t value)
{
putreg32(value, AT32_PWC_BASE + (uint32_t)offset);
}
static inline void at32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits,
uint32_t setbits)
{
modifyreg32(AT32_PWC_BASE + (uint32_t)offset, clearbits, setbits);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_pwr_initbkp
*
* Description:
* Insures the referenced count access to the backup domain (RTC registers,
* RTC backup data registers and backup SRAM is consistent with the HW
* state without relying on a variable.
*
* NOTE: This function should only be called by SoC Start up code.
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* None
*
****************************************************************************/
void at32_pwr_initbkp(bool writable)
{
uint16_t regval;
/* Make the HW not writable */
regval = at32_pwr_getreg32(AT32_PWC_CTRL_OFFSET);
regval &= ~PWC_CTRL_BPWEN;
at32_pwr_putreg32(AT32_PWC_CTRL_OFFSET, regval);
/* Make the reference count agree */
g_bkp_writable_counter = 0;
at32_pwr_enablebkp(writable);
}
/****************************************************************************
* Name: at32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
*
* NOTE:
* Reference counting is used in order to supported nested calls to this
* function. As a consequence, every call to at32_pwr_enablebkp(true)
* must be followed by a matching call to at32_pwr_enablebkp(false).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* None
*
****************************************************************************/
void at32_pwr_enablebkp(bool writable)
{
irqstate_t flags;
uint16_t regval;
bool waswritable;
bool wait = false;
flags = enter_critical_section();
/* Get the current state of the AT32 PWR control register */
regval = at32_pwr_getreg32(AT32_PWC_CTRL_OFFSET);
waswritable = ((regval & PWC_CTRL_BPWEN) != 0);
if (writable)
{
DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
g_bkp_writable_counter++;
}
else if (g_bkp_writable_counter > 0)
{
g_bkp_writable_counter--;
}
/* Enable or disable the ability to write */
if (waswritable && g_bkp_writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWC_CTRL_BPWEN;
at32_pwr_putreg32(AT32_PWC_CTRL_OFFSET, regval);
}
else if (!waswritable && g_bkp_writable_counter > 0)
{
/* Enable backup domain access */
regval |= PWC_CTRL_BPWEN;
at32_pwr_putreg32(AT32_PWC_CTRL_OFFSET, regval);
wait = true;
}
leave_critical_section(flags);
if (wait)
{
/* Enable does not happen right away */
up_udelay(4);
}
}
/****************************************************************************
* Name: at32_pwr_enablewkup
*
* Description:
* Enables the WKUP pin.
*
* Input Parameters:
* wupin - Selects the WKUP pin to enable/disable
* wupon - state to set it to
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure. The only cause of failure is if the selected MCU does not
* support the requested wakeup pin.
*
****************************************************************************/
int at32_pwr_enablewkup(enum at32_pwr_wupin_e wupin, bool wupon)
{
uint16_t pinmask;
/* Select the PWR_CSR bit associated with the requested wakeup pin */
switch (wupin)
{
case PWC_WUPIN_1: /* Wake-up pin 1 (all parts) */
pinmask = PWC_CTRLSTS_SWPEN1;
break;
#ifdef HAVE_PWR_WKUP2
case PWC_WUPIN_2: /* Wake-up pin 2 */
pinmask = PWC_CTRLSTS_SWPEN2;
break;
#endif
#ifdef HAVE_PWR_WKUP3
case PWC_WUPIN_3: /* Wake-up pin 3 */
pinmask = PWR_CSR_EWUP3;
break;
#endif
default:
return -EINVAL;
}
/* Set/clear the the wakeup pin enable bit in the CSR. This must be done
* within a critical section because the CSR is shared with other functions
* that may be running concurrently on another thread.
*/
if (wupon)
{
/* Enable the wakeup pin by setting the bit in the CSR. */
at32_pwr_modifyreg32(AT32_PWC_CTRLSTS_OFFSET, 0, pinmask);
}
else
{
/* Disable the wakeup pin by clearing the bit in the CSR. */
at32_pwr_modifyreg32(AT32_PWC_CTRLSTS_OFFSET, pinmask, 0);
}
return OK;
}
/****************************************************************************
* Name: at32_pwr_getsbf
*
* Description:
* Return the standby flag.
*
****************************************************************************/
bool at32_pwr_getsbf(void)
{
return (at32_pwr_getreg32(AT32_PWC_CTRLSTS_OFFSET) & PWC_CTRLSTS_SEF) != 0;
}
/****************************************************************************
* Name: at32_pwr_getwuf
*
* Description:
* Return the wakeup flag.
*
****************************************************************************/
bool at32_pwr_getwuf(void)
{
return (at32_pwr_getreg32(AT32_PWC_CTRLSTS_OFFSET) \
& PWC_CTRLSTS_SWEF) != 0;
}
/****************************************************************************
* Name: at32_pwr_setpvd
*
* Description:
* Sets power voltage detector
*
* Input Parameters:
* pls - PVD level
*
* Returned Value:
* None
*
* Assumptions:
* At present, this function is called only from initialization logic.
* If used for any other purpose that protection to assure that its
* operation is atomic will be required.
*
****************************************************************************/
void at32_pwr_setpvd(uint16_t pls)
{
uint16_t regval;
/* Set PLS */
regval = at32_pwr_getreg32(AT32_PWC_CTRL_OFFSET);
regval &= ~PWC_CTRL_PVMSEL_MASK;
regval |= (pls & PWC_CTRL_PVMSEL_MASK);
/* Write value to register */
at32_pwr_putreg32(AT32_PWC_CTRL_OFFSET, regval);
}
/****************************************************************************
* Name: at32_pwr_enablepvd
*
* Description:
* Enable the Programmable Voltage Detector
*
****************************************************************************/
void at32_pwr_enablepvd(void)
{
/* Enable PVD by setting the PVDE bit in PWR_CR register. */
at32_pwr_modifyreg32(AT32_PWC_CTRL_OFFSET, 0, PWC_CTRL_PVMEN);
}
/****************************************************************************
* Name: at32_pwr_disablepvd
*
* Description:
* Disable the Programmable Voltage Detector
*
****************************************************************************/
void at32_pwr_disablepvd(void)
{
/* Disable PVD by clearing the PVDE bit in PWR_CR register. */
at32_pwr_modifyreg32(AT32_PWC_CTRL_OFFSET, PWC_CTRL_PVMEN, 0);
}
#endif /* CONFIG_AT32_PWR */

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/****************************************************************************
* arch/arm/src/at32/at32_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_PWR_H
#define __ARCH_ARM_SRC_AT32_AT32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/at32_pwr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* Identify MCU-specific wakeup pin.
* Different AT32 parts support differing numbers of wakeup pins.
*/
enum at32_pwr_wupin_e
{
PWC_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */
PWC_WUPIN_2, /* Wake-up pin 2 */
PWC_WUPIN_3 /* Wake-up pin 3 */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_pwr_initbkp
*
* Description:
* Insures the referenced count access to the backup domain
* (RTC registers, RTC backup data registers and backup SRAM is consistent
* with the HW state without relying on a variable.
*
* NOTE: This function should only be called by SoC Start up code.
*
* Input Parameters:
* writable - set the initial state of the enable and the
* bkp_writable_counter
*
* Returned Value:
* None
*
****************************************************************************/
void at32_pwr_initbkp(bool writable);
/****************************************************************************
* Name: at32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain
* (RTC registers, RTC backup data registers and backup SRAM).
*
* NOTE:
* Reference counting is used in order to supported nested calls to this
* function. As a consequence, every call to at32_pwr_enablebkp(true)
* must be followed by a matching call to at32_pwr_enablebkp(false).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* None
*
****************************************************************************/
void at32_pwr_enablebkp(bool writable);
/****************************************************************************
* Name: at32_pwr_enablewkup
*
* Description:
* Enables the WKUP pin.
*
* Input Parameters:
* wupin - Selects the WKUP pin to enable/disable
* wupon - state to set it to
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure. The only cause of failure is if the selected MCU does not
* support the requested wakeup pin.
*
****************************************************************************/
int at32_pwr_enablewkup(enum at32_pwr_wupin_e wupin, bool wupon);
/****************************************************************************
* Name: at32_pwr_getsbf
*
* Description:
* Return the standby flag.
*
****************************************************************************/
bool at32_pwr_getsbf(void);
/****************************************************************************
* Name: at32_pwr_getwuf
*
* Description:
* Return the wakeup flag.
*
****************************************************************************/
bool at32_pwr_getwuf(void);
/****************************************************************************
* Name: at32_pwr_setpvd
*
* Description:
* Sets power voltage detector for EnergyLite devices.
*
* Input Parameters:
* pls - PVD level
*
* Returned Value:
* None
*
* Assumptions:
* At present, this function is called only from initialization logic.
*
****************************************************************************/
void at32_pwr_setpvd(uint16_t pls);
/****************************************************************************
* Name: at32_pwr_enablepvd
*
* Description:
* Enable the Programmable Voltage Detector
*
****************************************************************************/
void at32_pwr_enablepvd(void);
/****************************************************************************
* Name: at32_pwr_disablepvd
*
* Description:
* Disable the Programmable Voltage Detector
*
****************************************************************************/
void at32_pwr_disablepvd(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_PWR_H */

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/****************************************************************************
* arch/arm/src/at32/at32_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_gpio.h"
#include "at32_rcc.h"
#include "at32_rtc.h"
#include "at32_flash.h"
#include "at32.h"
#include "at32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/****************************************************************************
* Included Files
****************************************************************************/
/* Include chip-specific clocking initialization logic */
#if defined(CONFIG_AT32_AT32F43XX)
# include "at32f43xxx_rcc.c"
#else
# error "Unsupported AT32 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
# define AT32_RCC_XXX AT32_CRM_BPDC
# define RCC_XXX_YYYRST CRM_BPDC_BPDRST
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rcc_resetbkp
*
* Description:
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
* the Backup Domain renders to disabling the LSE as consequence.
* In order to avoid resetting the Backup Domain when we already
* configured LSE we will reset the Backup Domain early (here).
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_AT32_RTC) && defined(CONFIG_AT32_PWR)
static inline void rcc_resetbkp(void)
{
uint32_t regval;
/* Check if the RTC is already configured */
at32_pwr_initbkp(false);
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
{
at32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
*/
modifyreg32(AT32_RCC_XXX, 0, RCC_XXX_YYYRST);
modifyreg32(AT32_RCC_XXX, RCC_XXX_YYYRST, 0);
at32_pwr_enablebkp(false);
}
}
#else
# define rcc_resetbkp()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called at32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void at32_clockconfig(void)
{
/* Make sure that we are starting in the reset state */
rcc_reset();
/* Reset backup domain if appropriate */
rcc_resetbkp();
#if defined(CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
at32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
at32_stdclockconfig();
#endif
/* Enable peripheral clocking */
rcc_enableperipherals();
#ifdef CONFIG_AT32_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
at32_iocompensation();
#endif
}
/****************************************************************************
* Name: at32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings
* in board.h. This function is only available to support low-power
* modes of operation: When re-awakening from deep-sleep modes, it is
* necessary to re-enable/re-start the PLL
*
* This functional performs a subset of the operations performed by
* at32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called at32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void at32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
at32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
at32_stdclockconfig();
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/at32/at32_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_RCC_H
#define __ARCH_ARM_SRC_AT32_AT32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "chip.h"
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_rcc.h"
#else
# error "Unsupported AT32 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: at32_mco1config
*
* Description:
* Selects the clock source to output on MCO1 pin (PA8). PA8 should be
* configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCO1 definitions from
* chip/at32f4xxxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE,
* RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL}
* div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from
* chip/at32f4xxxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2,
* RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5}
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
static inline void at32_mco1config(uint32_t source, uint32_t div)
{
uint32_t regval;
regval = getreg32(AT32_CRM_CFG);
regval &= ~(CRM_CFG_CLKOUT1_SEL_MASK | CRM_CFG_CLKOUT1DIV1_MASK);
regval |= (source | div);
putreg32(regval, AT32_CRM_CFG);
}
#endif
/****************************************************************************
* Name: at32_mco2config
*
* Description:
* Selects the clock source to output on MCO2 pin (PC9). PC9 should be
* configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCO2 definitions from
* chip/at32f4xxxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S,
* RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL}
* div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from
* chip/at32f4xxxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2,
* RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5}
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
static inline void at32_mco2config(uint32_t source, uint32_t div)
{
uint32_t regval;
regval = getreg32(AT32_CRM_CFG);
regval &= ~(CRM_CFG_CLKOUT2_SEL1_MASK | CRM_CFG_CLKOUT2DIV1_MASK);
regval |= (source | div);
putreg32(regval, AT32_CRM_CFG);
}
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called at32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void at32_clockconfig(void);
/****************************************************************************
* Name: at32_board_clockconfig
*
* Description:
* Any AT32 board may replace the "standard" board clock configuration
* logic with its own, custom clock configuration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG
void at32_board_clockconfig(void);
#endif
/****************************************************************************
* Name: at32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h.
* This function is only available to support low-power modes of operation:
* When re-awakening from deep-sleep modes, it is necessary to re-enable/
* re-start the PLL
*
* This functional performs a subset of the operations performed by
* at32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called at32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void at32_clockenable(void);
#endif
/****************************************************************************
* Name: at32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void at32_rcc_enablelse(void);
/****************************************************************************
* Name: at32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void at32_rcc_enablelsi(void);
/****************************************************************************
* Name: at32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void at32_rcc_disablelsi(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_RCC_H */

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/****************************************************************************
* arch/arm/src/at32/at32_rtc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is only a thin shell that includes the correct RTC
* implementation for the selected AT32 family. The correct file cannot be
* selected by the make system because it needs the intelligence that only
* exists in chip.h that can associate an AT32 part number with an AT32
* family.
*/
#if defined(CONFIG_AT32_AT32F43XX)
# include "at32f43xxx_rtcc.c"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/at32/at32_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_RTC_H
#define __ARCH_ARM_SRC_AT32_AT32_RTC_H
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32_rtcc.h"
#endif
/* Alarm function differs from part to part */
#if defined(CONFIG_AT32_AT32F43XX)
# include "at32f43xxx_alarm.h"
#else
# include "at32_alarm.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define AT32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a
* second base */
#define AT32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if !defined(CONFIG_AT32_RTC_MAGIC)
# define CONFIG_AT32_RTC_MAGIC (0xfacefeed)
#endif
#if !defined(CONFIG_AT32_RTC_MAGIC_TIME_SET)
# define CONFIG_AT32_RTC_MAGIC_TIME_SET (0xf00dface)
#endif
#if !defined(CONFIG_AT32_RTC_MAGIC_REG)
# define CONFIG_AT32_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC_REG AT32_RTC_BKR(CONFIG_AT32_RTC_MAGIC_REG)
#define RTC_MAGIC CONFIG_AT32_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_AT32_RTC_MAGIC_TIME_SET
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_rtc_irqinitialize
*
* Description:
* Initialize IRQs for RTC, not possible during up_rtc_initialize because
* up_irqinitialize is called later.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int at32_rtc_irqinitialize(void);
/****************************************************************************
* Name: at32_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
* Thatsub-second accuracy is returned through 'nsec'.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_AT32_HAVE_RTC_SUBSECONDS
int at32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec);
#endif
/****************************************************************************
* Name: at32_rtc_setdatetime
*
* Description:
* Set the RTC to the provided time. RTC implementations which provide
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
* this function.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_DATETIME
struct tm;
int at32_rtc_setdatetime(const struct tm *tp);
#endif
/****************************************************************************
* Name: at32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the AT32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "at32_rtc.h"
*
* struct rtc_lowerhalf_s *lower;
* lower = at32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_DRIVER
struct rtc_lowerhalf_s;
struct rtc_lowerhalf_s *at32_rtc_lowerhalf(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_RTC_H */

915
arch/arm/src/at32/at32_rtc_lowerhalf.c Normal file
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@ -0,0 +1,915 @@
/****************************************************************************
* arch/arm/src/at32/at32_rtc_lowerhalf.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/mutex.h>
#include <nuttx/timers/rtc.h>
#include "arm_internal.h"
#include "chip.h"
#include "at32_rtc.h"
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
# define AT32_NALARMS 2
#else
# define AT32_NALARMS 1
#endif
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct at32_cbinfo_s
{
volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */
volatile void *priv; /* Private argument to accompany callback */
#if defined(CONFIG_AT32_AT32F43XX)
uint8_t id; /* Identifies the alarm */
#endif
};
#endif
/* This is the private type for the RTC state. It must be cast compatible
* with struct rtc_lowerhalf_s.
*/
struct at32_lowerhalf_s
{
/* This is the contained reference to the read-only, lower-half
* operations vtable (which may lie in FLASH or ROM)
*/
const struct rtc_ops_s *ops;
/* Data following is private to this driver and not visible outside of
* this file.
*/
mutex_t devlock; /* Threads can only exclusively access the RTC */
#ifdef CONFIG_RTC_ALARM
/* Alarm callback information */
struct at32_cbinfo_s cbinfo[AT32_NALARMS];
#endif
#ifdef CONFIG_RTC_PERIODIC
/* Periodic wakeup information */
struct lower_setperiodic_s periodic;
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Prototypes for static methods in struct rtc_ops_s */
static int at32_rdtime(struct rtc_lowerhalf_s *lower,
struct rtc_time *rtctime);
static int at32_settime(struct rtc_lowerhalf_s *lower,
const struct rtc_time *rtctime);
static bool at32_havesettime(struct rtc_lowerhalf_s *lower);
#ifdef CONFIG_RTC_ALARM
static int at32_setalarm(struct rtc_lowerhalf_s *lower,
const struct lower_setalarm_s *alarminfo);
static int at32_setrelative(struct rtc_lowerhalf_s *lower,
const struct lower_setrelative_s *alarminfo);
static int at32_cancelalarm(struct rtc_lowerhalf_s *lower,
int alarmid);
static int at32_rdalarm(struct rtc_lowerhalf_s *lower,
struct lower_rdalarm_s *alarminfo);
#endif
#ifdef CONFIG_RTC_PERIODIC
static int at32_setperiodic(struct rtc_lowerhalf_s *lower,
const struct lower_setperiodic_s *alarminfo);
static int at32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* AT32 RTC driver operations */
static const struct rtc_ops_s g_rtc_ops =
{
.rdtime = at32_rdtime,
.settime = at32_settime,
.havesettime = at32_havesettime,
#ifdef CONFIG_RTC_ALARM
.setalarm = at32_setalarm,
.setrelative = at32_setrelative,
.cancelalarm = at32_cancelalarm,
.rdalarm = at32_rdalarm,
#endif
#ifdef CONFIG_RTC_PERIODIC
.setperiodic = at32_setperiodic,
.cancelperiodic = at32_cancelperiodic,
#endif
};
/* AT32 RTC device state */
static struct at32_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_alarm_callback
*
* Description:
* This is the function that is called from the RTC driver when the alarm
* goes off. It just invokes the upper half drivers callback.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
#if defined(CONFIG_AT32_AT32F43XX)
static void at32_alarm_callback(void *arg, unsigned int alarmid)
{
struct at32_lowerhalf_s *lower;
struct at32_cbinfo_s *cbinfo;
rtc_alarm_callback_t cb;
void *priv;
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
lower = (struct at32_lowerhalf_s *)arg;
cbinfo = &lower->cbinfo[alarmid];
/* Sample and clear the callback information to minimize the window in
* time in which race conditions can occur.
*/
cb = (rtc_alarm_callback_t)cbinfo->cb;
priv = (void *)cbinfo->priv;
DEBUGASSERT(priv != NULL);
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Perform the callback */
if (cb != NULL)
{
cb(priv, alarmid);
}
}
#else
static void at32_alarm_callback(void)
{
struct at32_cbinfo_s *cbinfo = &g_rtc_lowerhalf.cbinfo[0];
/* Sample and clear the callback information to minimize the window in
* time in which race conditions can occur.
*/
rtc_alarm_callback_t cb = (rtc_alarm_callback_t)cbinfo->cb;
void *arg = (void *)cbinfo->priv;
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Perform the callback */
if (cb != NULL)
{
cb(arg, 0);
}
}
#endif /* CONFIG_AT32_AT32F43XX*/
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: at32_rdtime
*
* Description:
* Implements the rdtime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The location in which to return the current RTC time.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int at32_rdtime(struct rtc_lowerhalf_s *lower,
struct rtc_time *rtctime)
{
#if defined(CONFIG_RTC_DATETIME)
/* This operation depends on the fact that struct rtc_time is cast
* compatible with struct tm.
*/
return up_rtc_getdatetime((struct tm *)rtctime);
#elif defined(CONFIG_RTC_HIRES)
struct timespec ts;
int ret;
/* Get the higher resolution time */
ret = up_rtc_gettime(&ts);
if (ret < 0)
{
goto errout;
}
/* Convert the one second epoch time to a struct tm. This operation
* depends on the fact that struct rtc_time and struct tm are cast
* compatible.
*/
if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime))
{
ret = -get_errno();
goto errout;
}
return OK;
errout:
DEBUGASSERT(ret < 0);
return ret;
#else
time_t timer;
/* The resolution of time is only 1 second */
timer = up_rtc_time();
/* Convert the one second epoch time to a struct tm */
if (!gmtime_r(&timer, (struct tm *)rtctime))
{
int errcode = get_errno();
DEBUGASSERT(errcode > 0);
return -errcode;
}
return OK;
#endif
}
/****************************************************************************
* Name: at32_settime
*
* Description:
* Implements the settime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The new time to set
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int at32_settime(struct rtc_lowerhalf_s *lower,
const struct rtc_time *rtctime)
{
#ifdef CONFIG_RTC_DATETIME
/* This operation depends on the fact that struct rtc_time is cast
* compatible with struct tm.
*/
return at32_rtc_setdatetime((const struct tm *)rtctime);
#else
struct timespec ts;
/* Convert the struct rtc_time to a time_t. Here we assume that struct
* rtc_time is cast compatible with struct tm.
*/
ts.tv_sec = timegm((struct tm *)rtctime);
ts.tv_nsec = 0;
/* Now set the time (to one second accuracy) */
return up_rtc_settime(&ts);
#endif
}
/****************************************************************************
* Name: at32_havesettime
*
* Description:
* Implements the havesettime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
*
* Returned Value:
* Returns true if RTC date-time have been previously set.
*
****************************************************************************/
static bool at32_havesettime(struct rtc_lowerhalf_s *lower)
{
return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET;
}
/****************************************************************************
* Name: at32_setalarm
*
* Description:
* Set a new alarm. This function implements the setalarm() method of the
* RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int at32_setalarm(struct rtc_lowerhalf_s *lower,
const struct lower_setalarm_s *alarminfo)
{
#if defined(CONFIG_AT32_AT32F43XX)
struct at32_lowerhalf_s *priv;
struct at32_cbinfo_s *cbinfo;
struct alm_setalarm_s lowerinfo;
int ret;
/* ID0-> Alarm A; ID1 -> Alarm B */
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
priv = (struct at32_lowerhalf_s *)lower;
ret = nxmutex_lock(&priv->devlock);
if (ret < 0)
{
return ret;
}
ret = -EINVAL;
if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB)
{
/* Remember the callback information */
cbinfo = &priv->cbinfo[alarminfo->id];
cbinfo->cb = alarminfo->cb;
cbinfo->priv = alarminfo->priv;
cbinfo->id = alarminfo->id;
/* Set the alarm */
lowerinfo.as_id = alarminfo->id;
lowerinfo.as_cb = at32_alarm_callback;
lowerinfo.as_arg = priv;
memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm));
/* And set the alarm */
ret = at32_rtc_setalarm(&lowerinfo);
if (ret < 0)
{
cbinfo->cb = NULL;
cbinfo->priv = NULL;
}
}
nxmutex_unlock(&priv->devlock);
return ret;
#else
struct at32_lowerhalf_s *priv;
struct at32_cbinfo_s *cbinfo;
int ret;
DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0);
priv = (struct at32_lowerhalf_s *)lower;
ret = nxmutex_lock(&priv->devlock);
if (ret < 0)
{
return ret;
}
ret = -EINVAL;
if (alarminfo->id == 0)
{
struct timespec ts;
/* Convert the RTC time to a timespec (1 second accuracy) */
ts.tv_sec = timegm((struct tm *)&alarminfo->time);
ts.tv_nsec = 0;
/* Remember the callback information */
cbinfo = &priv->cbinfo[0];
cbinfo->cb = alarminfo->cb;
cbinfo->priv = alarminfo->priv;
/* And set the alarm */
ret = at32_rtc_setalarm(&ts, at32_alarm_callback);
if (ret < 0)
{
cbinfo->cb = NULL;
cbinfo->priv = NULL;
}
}
nxmutex_unlock(&priv->devlock);
return ret;
#endif
}
#endif
/****************************************************************************
* Name: at32_setrelative
*
* Description:
* Set a new alarm relative to the current time. This function implements
* the setrelative() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int at32_setrelative(struct rtc_lowerhalf_s *lower,
const struct lower_setrelative_s *alarminfo)
{
#if defined(CONFIG_AT32_AT32F43XX)
struct lower_setalarm_s setalarm;
struct tm time;
time_t seconds;
int ret = -EINVAL;
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) &&
alarminfo->reltime > 0)
{
/* Disable pre-emption while we do this so that we don't have to worry
* about being suspended and working on an old time.
*/
sched_lock();
/* Get the current time in broken out format */
ret = up_rtc_getdatetime(&time);
if (ret >= 0)
{
/* Convert to seconds since the epoch */
seconds = timegm(&time);
/* Add the seconds offset. Add one to the number of seconds
* because we are unsure of the phase of the timer.
*/
seconds += (alarminfo->reltime + 1);
/* And convert the time back to broken out format */
gmtime_r(&seconds, (struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */
setalarm.id = alarminfo->id;
setalarm.cb = alarminfo->cb;
setalarm.priv = alarminfo->priv;
ret = at32_setalarm(lower, &setalarm);
}
sched_unlock();
}
return ret;
#else
struct at32_lowerhalf_s *priv;
struct at32_cbinfo_s *cbinfo;
#if defined(CONFIG_RTC_DATETIME)
struct tm time;
#endif
struct timespec ts;
int ret = -EINVAL;
DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0);
priv = (struct at32_lowerhalf_s *)lower;
if (alarminfo->id == 0 && alarminfo->reltime > 0)
{
/* Disable pre-emption while we do this so that we don't have to worry
* about being suspended and working on an old time.
*/
sched_lock();
/* Get the current time in seconds */
#if defined(CONFIG_RTC_DATETIME)
/* Get the broken out time and convert to seconds */
ret = up_rtc_getdatetime(&time);
if (ret < 0)
{
sched_unlock();
return ret;
}
ts.tv_sec = timegm(&time);
ts.tv_nsec = 0;
#elif defined(CONFIG_RTC_HIRES)
/* Get the higher resolution time */
ret = up_rtc_gettime(&ts);
if (ret < 0)
{
sched_unlock();
return ret;
}
#else
/* The resolution of time is only 1 second */
ts.tv_sec = up_rtc_time();
ts.tv_nsec = 0;
#endif
/* Add the seconds offset. Add one to the number of seconds because
* we are unsure of the phase of the timer.
*/
ts.tv_sec += (alarminfo->reltime + 1);
/* Remember the callback information */
cbinfo = &priv->cbinfo[0];
cbinfo->cb = alarminfo->cb;
cbinfo->priv = alarminfo->priv;
/* And set the alarm */
ret = at32_rtc_setalarm(&ts, at32_alarm_callback);
if (ret < 0)
{
cbinfo->cb = NULL;
cbinfo->priv = NULL;
}
sched_unlock();
}
return ret;
#endif
}
#endif
/****************************************************************************
* Name: at32_cancelalarm
*
* Description:
* Cancel the current alarm. This function implements the cancelalarm()
* method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int at32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid)
{
#if defined(CONFIG_AT32_AT32F43XX)
struct at32_lowerhalf_s *priv;
struct at32_cbinfo_s *cbinfo;
int ret;
DEBUGASSERT(lower != NULL);
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
priv = (struct at32_lowerhalf_s *)lower;
ret = nxmutex_lock(&priv->devlock);
if (ret < 0)
{
return ret;
}
/* ID0-> Alarm A; ID1 -> Alarm B */
ret = -EINVAL;
if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB)
{
/* Nullify callback information to reduce window for race conditions */
cbinfo = &priv->cbinfo[alarmid];
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Then cancel the alarm */
ret = at32_rtc_cancelalarm((enum alm_id_e)alarmid);
}
nxmutex_unlock(&priv->devlock);
return ret;
#else
struct at32_lowerhalf_s *priv;
struct at32_cbinfo_s *cbinfo;
DEBUGASSERT(lower != NULL);
DEBUGASSERT(alarmid == 0);
priv = (struct at32_lowerhalf_s *)lower;
/* Nullify callback information to reduce window for race conditions */
cbinfo = &priv->cbinfo[0];
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Then cancel the alarm */
return at32_rtc_cancelalarm();
#endif
}
#endif
/****************************************************************************
* Name: at32_rdalarm
*
* Description:
* Query the RTC alarm.
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to query the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int at32_rdalarm(struct rtc_lowerhalf_s *lower,
struct lower_rdalarm_s *alarminfo)
{
struct alm_rdalarm_s lowerinfo;
int ret = -EINVAL;
DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB)
{
/* Disable pre-emption while we do this so that we don't have to worry
* about being suspended and working on an old time.
*/
sched_lock();
lowerinfo.ar_id = alarminfo->id;
lowerinfo.ar_time = alarminfo->time;
ret = at32_rtc_rdalarm(&lowerinfo);
sched_unlock();
}
return ret;
}
#endif
/****************************************************************************
* Name: at32_periodic_callback
*
* Description:
* This is the function that is called from the RTC driver when the
* periodic wakeup goes off. It just invokes the upper half drivers
* callback.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
static int at32_periodic_callback(void)
{
struct at32_lowerhalf_s *lower;
struct lower_setperiodic_s *cbinfo;
rtc_wakeup_callback_t cb;
void *priv;
lower = (struct at32_lowerhalf_s *)&g_rtc_lowerhalf;
cbinfo = &lower->periodic;
cb = (rtc_wakeup_callback_t)cbinfo->cb;
priv = (void *)cbinfo->priv;
/* Perform the callback */
if (cb != NULL)
{
cb(priv, 0);
}
return OK;
}
#endif /* CONFIG_RTC_PERIODIC */
/****************************************************************************
* Name: at32_setperiodic
*
* Description:
* Set a new periodic wakeup relative to the current time, with a given
* period. This function implements the setperiodic() method of the RTC
* driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the wakeup activity
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
static int at32_setperiodic(struct rtc_lowerhalf_s *lower,
const struct lower_setperiodic_s *alarminfo)
{
struct at32_lowerhalf_s *priv;
int ret;
DEBUGASSERT(lower != NULL && alarminfo != NULL);
priv = (struct at32_lowerhalf_s *)lower;
ret = nxmutex_lock(&priv->devlock);
if (ret < 0)
{
return ret;
}
memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s));
ret = at32_rtc_setperiodic(&alarminfo->period, at32_periodic_callback);
nxmutex_unlock(&priv->devlock);
return ret;
}
#endif
/****************************************************************************
* Name: at32_cancelperiodic
*
* Description:
* Cancel the current periodic wakeup activity. This function implements
* the cancelperiodic() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
static int at32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id)
{
struct at32_lowerhalf_s *priv;
int ret;
DEBUGASSERT(lower != NULL);
priv = (struct at32_lowerhalf_s *)lower;
DEBUGASSERT(id == 0);
ret = nxmutex_lock(&priv->devlock);
if (ret < 0)
{
return ret;
}
ret = at32_rtc_cancelperiodic();
nxmutex_unlock(&priv->devlock);
return ret;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the AT32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "at32_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = at32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
struct rtc_lowerhalf_s *at32_rtc_lowerhalf(void)
{
return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}
#endif /* CONFIG_RTC_DRIVER */

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/****************************************************************************
* arch/arm/src/at32/at32_sdio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_SDIO_H
#define __ARCH_ARM_SRC_AT32_AT32_SDIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/at32_sdio.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: sdio_initialize
*
* Description:
* Initialize SDIO for operation.
*
* Input Parameters:
* slotno - Not used.
*
* Returned Value:
* A reference to an SDIO interface structure. NULL is returned on
* failures.
*
****************************************************************************/
struct sdio_dev_s; /* See include/nuttx/sdio.h */
struct sdio_dev_s *sdio_initialize(int slotno);
/****************************************************************************
* Name: sdio_mediachange
*
* Description:
* Called by board-specific logic -- possibly from an interrupt handler --
* in order to signal to the driver that a card has been inserted or
* removed from the slot
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* cardinslot - true is a card has been detected in the slot; false if a
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
* Returned Value:
* None
*
****************************************************************************/
void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot);
/****************************************************************************
* Name: sdio_wrprotect
*
* Description:
* Called by board-specific logic to report if the card in the slot is
* mechanically write protected.
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
* Returned Value:
* None
*
****************************************************************************/
void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect);
/****************************************************************************
* Name: sdio_set_sdio_card_isr
*
* Description:
* SDIO card generates interrupt via SDIO_DATA_1 pin.
* Called by board-specific logic to register an ISR for SDIO card.
*
* Input Parameters:
* func - callback function.
* arg - arg to be passed to the function.
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_AT32_SDIO_CARD
void sdio_set_sdio_card_isr(struct sdio_dev_s *dev,
int (*func)(void *), void *arg);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_SDIO_H */

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/****************************************************************************
* arch/arm/src/at32/at32_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_SPI_H
#define __ARCH_ARM_SRC_AT32_AT32_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi/spi.h>
#include "chip.h"
#include "hardware/at32_spi.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
struct spi_dev_s;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameters:
* bus number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct spi_dev_s *at32_spibus_initialize(int bus);
/****************************************************************************
* Name: at32_spi1/2/...select and at32_spi1/2/...status
*
* Description:
* The external functions, at32_spi1/2/...select, at32_spi1/2/...status,
* and at32_spi1/2/...cmddata must be provided by board-specific logic.
* These are implementations of the select, status, and cmddata methods of
* the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including
* at32_spibus_initialize()) are provided by common AT32 logic. To use
* this common SPI logic on your board:
*
* 1. Provide logic in at32_boardinitialize() to configure SPI chip
* select pins.
* 2. Provide at32_spi1/2/...select() and at32_spi1/2/...status()
* functions in your board-specific logic. These functions will
* perform chip selection and status operations using GPIOs in the way
* your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
* then provide at32_spi1/2/...cmddata() functions in your board-
* specific logic. These functions will perform cmd/data selection
* operations using GPIOs in the way your board is configured.
* 4. Add a calls to at32_spibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by at32_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_AT32_SPI1
void at32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t at32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int at32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_AT32_SPI2
void at32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t at32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int at32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_AT32_SPI3
void at32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t at32_spi3status(struct spi_dev_s *dev, uint32_t devid);
int at32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_AT32_SPI4
void at32_spi4select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t at32_spi4status(struct spi_dev_s *dev, uint32_t devid);
int at32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/****************************************************************************
* Name: at32_spi1/2/...register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s)
* must be implemented. These functions implements the registercallback
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_AT32_SPI1
int at32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_AT32_SPI2
int at32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_AT32_SPI3
int at32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_AT32_SPI4
int at32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_SPI_H */

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/****************************************************************************
* arch/arm/src/at32/at32_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include "arm_internal.h"
#include "nvic.h"
#include "mpu.h"
#include "at32.h"
#include "at32_gpio.h"
#include "at32_userspace.h"
#include "at32_start.h"
#include "arch/board/board.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EABI requires 64 bit stack alignment.
*/
#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* If enabled reset the MPU */
mpu_early_reset();
/* Configure the UART so that we can get debug output as soon as possible */
at32_clockconfig();
arm_fpuconfig();
at32_lowsetup();
at32_gpioinit();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = (uint32_t *)_START_BSS; dest < (uint32_t *)_END_BSS; )
{
*dest++ = 0;
}
showprogress('B');
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = (const uint32_t *)_DATA_INIT,
dest = (uint32_t *)_START_DATA; dest < (uint32_t *)_END_DATA;
)
{
*dest++ = *src++;
}
showprogress('C');
#ifdef CONFIG_SCHED_IRQMONITOR
up_perf_init((void *)AT32_SYSCLK_FREQUENCY);
#endif
#ifdef CONFIG_ARMV7M_ITMSYSLOG
/* Perform ARMv7-M ITM SYSLOG initialization */
itm_syslog_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('D');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
at32_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
at32_boardinitialize();
showprogress('F');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; );
}

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/****************************************************************************
* arch/arm/src/at32/at32_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_START_H
#define __ARCH_ARM_SRC_AT32_AT32_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_boardinitialize
*
* Description:
* All AT32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after
* clocking and memory have been configured but before caches have been
* enabled and before any devices have been initialized.
*
****************************************************************************/
void at32_boardinitialize(void);
#endif /* __ARCH_ARM_SRC_AT32_AT32_START_H */

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/****************************************************************************
* arch/arm/src/at32/at32_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_SYSCFG_H
#define __ARCH_ARM_SRC_AT32_AT32_SYSCFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_syscfg.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_AT32_AT32_SYSCFG_H */

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/****************************************************************************
* arch/arm/src/at32/at32_tim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_TIM_H
#define __ARCH_ARM_SRC_AT32_AT32_TIM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/at32_tim.h"
#include <nuttx/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Helpers ******************************************************************/
#define AT32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define AT32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define AT32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define AT32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
#define AT32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c))
#define AT32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d))
#define AT32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define AT32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define AT32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define AT32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
#define AT32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define AT32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define AT32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
#define AT32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* TIM Device Structure */
struct at32_tim_dev_s
{
struct at32_tim_ops_s *ops;
};
/* TIM Modes of Operation */
typedef enum
{
AT32_TIM_MODE_UNUSED = -1,
/* One of the following */
AT32_TIM_MODE_MASK = 0x0310,
AT32_TIM_MODE_DISABLED = 0x0000,
AT32_TIM_MODE_UP = 0x0100,
AT32_TIM_MODE_DOWN = 0x0110,
AT32_TIM_MODE_UPDOWN = 0x0200,
AT32_TIM_MODE_PULSE = 0x0300,
/* One of the following */
AT32_TIM_MODE_CK_INT = 0x0000,
/* AT32_TIM_MODE_CK_INT_TRIG = 0x0400, */
/* AT32_TIM_MODE_CK_EXT = 0x0800, */
/* AT32_TIM_MODE_CK_EXT_TRIG = 0x0C00, */
/* Clock sources, OR'ed with CK_EXT */
/* AT32_TIM_MODE_CK_CHINVALID = 0x0000, */
/* AT32_TIM_MODE_CK_CH1 = 0x0001, */
/* AT32_TIM_MODE_CK_CH2 = 0x0002, */
/* AT32_TIM_MODE_CK_CH3 = 0x0003, */
/* AT32_TIM_MODE_CK_CH4 = 0x0004 */
/* Todo: external trigger block */
} at32_tim_mode_t;
/* TIM Channel Modes */
typedef enum
{
AT32_TIM_CH_DISABLED = 0x00,
/* Common configuration */
AT32_TIM_CH_POLARITY_POS = 0x00,
AT32_TIM_CH_POLARITY_NEG = 0x01,
/* MODES: */
AT32_TIM_CH_MODE_MASK = 0x06,
/* Output Compare Modes */
AT32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */
/* AT32_TIM_CH_OUTCOMPARE = 0x06, */
/* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */
/* AT32_TIM_CH_INCAPTURE = 0x10, */
/* AT32_TIM_CH_INPWM = 0x20 */
/* AT32_TIM_CH_DRIVE_OC -- open collector mode */
} at32_tim_channel_t;
/* TIM Operations */
struct at32_tim_ops_s
{
/* Basic Timers */
int (*setmode)(struct at32_tim_dev_s *dev, at32_tim_mode_t mode);
int (*setclock)(struct at32_tim_dev_s *dev, uint32_t freq);
void (*setperiod)(struct at32_tim_dev_s *dev, uint32_t period);
uint32_t (*getcounter)(struct at32_tim_dev_s *dev);
void (*setcounter)(struct at32_tim_dev_s *dev, uint32_t count);
/* General and Advanced Timers Adds */
int (*getwidth)(struct at32_tim_dev_s *dev);
int (*setchannel)(struct at32_tim_dev_s *dev, uint8_t channel,
at32_tim_channel_t mode);
int (*setcompare)(struct at32_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
int (*getcapture)(struct at32_tim_dev_s *dev, uint8_t channel);
/* Timer interrupts */
int (*setisr)(struct at32_tim_dev_s *dev,
xcpt_t handler, void * arg, int source);
void (*enableint)(struct at32_tim_dev_s *dev, int source);
void (*disableint)(struct at32_tim_dev_s *dev, int source);
void (*ackint)(struct at32_tim_dev_s *dev, int source);
int (*checkint)(struct at32_tim_dev_s *dev, int source);
};
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/* Power-up timer and get its structure */
struct at32_tim_dev_s *at32_tim_init(int timer);
/* Power-down timer, mark it as unused */
int at32_tim_deinit(struct at32_tim_dev_s *dev);
/****************************************************************************
* Name: at32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device.
* This should be of the form /dev/timer0
* timer - the timer number.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_TIMER
int at32_timer_initialize(const char *devpath, int timer);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_TIM_H */

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/****************************************************************************
* arch/arm/src/at32/at32_tim_lowerhalf.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/timers/timer.h>
#include <arch/board/board.h>
#include "at32_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_AT32_TIM1) || defined(CONFIG_AT32_TIM2) || \
defined(CONFIG_AT32_TIM3) || defined(CONFIG_AT32_TIM4) || \
defined(CONFIG_AT32_TIM5) || defined(CONFIG_AT32_TIM6) || \
defined(CONFIG_AT32_TIM7) || defined(CONFIG_AT32_TIM8) || \
defined(CONFIG_AT32_TIM9) || defined(CONFIG_AT32_TIM10) || \
defined(CONFIG_AT32_TIM11) || defined(CONFIG_AT32_TIM12) || \
defined(CONFIG_AT32_TIM13) || defined(CONFIG_AT32_TIM14) || \
defined(CONFIG_AT32_TIM20))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define AT32_TIM1_RES 16
#define AT32_TIM2_RES 32
#define AT32_TIM3_RES 16
#define AT32_TIM4_RES 16
#define AT32_TIM5_RES 32
#define AT32_TIM6_RES 16
#define AT32_TIM7_RES 16
#define AT32_TIM8_RES 16
#define AT32_TIM9_RES 16
#define AT32_TIM10_RES 16
#define AT32_TIM11_RES 16
#define AT32_TIM12_RES 16
#define AT32_TIM13_RES 16
#define AT32_TIM14_RES 16
#define AT32_TIM20_RES 16
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* timer_lowerhalf_s structure.
*/
struct at32_lowerhalf_s
{
const struct timer_ops_s *ops; /* Lower half operations */
struct at32_tim_dev_s *tim; /* at32 timer driver */
tccb_t callback; /* Current user interrupt callback */
void *arg; /* Argument passed to upper half callback */
bool started; /* True: Timer has been started */
const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int at32_timer_handler(int irq, void * context, void * arg);
/* "Lower half" driver methods **********************************************/
static int at32_start(struct timer_lowerhalf_s *lower);
static int at32_stop(struct timer_lowerhalf_s *lower);
static int at32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout);
static void at32_setcallback(struct timer_lowerhalf_s *lower,
tccb_t callback, void *arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct timer_ops_s g_timer_ops =
{
.start = at32_start,
.stop = at32_stop,
.getstatus = NULL,
.settimeout = at32_settimeout,
.setcallback = at32_setcallback,
.ioctl = NULL,
};
#ifdef CONFIG_AT32_TIM1
static struct at32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM1_RES,
};
#endif
#ifdef CONFIG_AT32_TIM2
static struct at32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM2_RES,
};
#endif
#ifdef CONFIG_AT32_TIM3
static struct at32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM3_RES,
};
#endif
#ifdef CONFIG_AT32_TIM4
static struct at32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM4_RES,
};
#endif
#ifdef CONFIG_AT32_TIM5
static struct at32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM5_RES,
};
#endif
#ifdef CONFIG_AT32_TIM6
static struct at32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM6_RES,
};
#endif
#ifdef CONFIG_AT32_TIM7
static struct at32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM7_RES,
};
#endif
#ifdef CONFIG_AT32_TIM8
static struct at32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM8_RES,
};
#endif
#ifdef CONFIG_AT32_TIM9
static struct at32_lowerhalf_s g_tim9_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM9_RES,
};
#endif
#ifdef CONFIG_AT32_TIM10
static struct at32_lowerhalf_s g_tim10_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM10_RES,
};
#endif
#ifdef CONFIG_AT32_TIM11
static struct at32_lowerhalf_s g_tim11_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM11_RES,
};
#endif
#ifdef CONFIG_AT32_TIM12
static struct at32_lowerhalf_s g_tim12_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM12_RES,
};
#endif
#ifdef CONFIG_AT32_TIM13
static struct at32_lowerhalf_s g_tim13_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM13_RES,
};
#endif
#ifdef CONFIG_AT32_TIM14
static struct at32_lowerhalf_s g_tim14_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM14_RES,
};
#endif
#ifdef CONFIG_AT32_TIM20
static struct at32_lowerhalf_s g_tim20_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = AT32_TIM20_RES,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_timer_handler
*
* Description:
* timer interrupt handler
*
* Input Parameters:
*
* Returned Value:
*
****************************************************************************/
static int at32_timer_handler(int irq, void * context, void * arg)
{
struct at32_lowerhalf_s *lower = (struct at32_lowerhalf_s *) arg;
uint32_t next_interval_us = 0;
AT32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE);
if (lower->callback(&next_interval_us, lower->arg))
{
if (next_interval_us > 0)
{
AT32_TIM_SETPERIOD(lower->tim, next_interval_us);
}
}
else
{
at32_stop((struct timer_lowerhalf_s *)lower);
}
return OK;
}
/****************************************************************************
* Name: at32_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_start(struct timer_lowerhalf_s *lower)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
if (!priv->started)
{
AT32_TIM_SETMODE(priv->tim, AT32_TIM_MODE_UP);
if (priv->callback != NULL)
{
AT32_TIM_SETISR(priv->tim, at32_timer_handler, priv, 0);
AT32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE);
}
priv->started = true;
return OK;
}
/* Return EBUSY to indicate that the timer was already running */
return -EBUSY;
}
/****************************************************************************
* Name: at32_stop
*
* Description:
* Stop the timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_stop(struct timer_lowerhalf_s *lower)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
if (priv->started)
{
AT32_TIM_SETMODE(priv->tim, AT32_TIM_MODE_DISABLED);
AT32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE);
AT32_TIM_SETISR(priv->tim, NULL, NULL, 0);
priv->started = false;
return OK;
}
/* Return ENODEV to indicate that the timer was not running */
return -ENODEV;
}
/****************************************************************************
* Name: at32_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in microseconds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
uint64_t maxtimeout;
if (priv->started)
{
return -EPERM;
}
maxtimeout = (1 << priv->resolution) - 1;
if (timeout > maxtimeout)
{
uint64_t freq = (maxtimeout * 1000000) / timeout;
AT32_TIM_SETCLOCK(priv->tim, freq);
AT32_TIM_SETPERIOD(priv->tim, maxtimeout);
}
else
{
AT32_TIM_SETCLOCK(priv->tim, 1000000);
AT32_TIM_SETPERIOD(priv->tim, timeout);
}
return OK;
}
/****************************************************************************
* Name: at32_setcallback
*
* Description:
* Call this user provided timeout callback.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* callback - The new timer expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
* arg - Argument that will be provided in the callback
*
* Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
****************************************************************************/
static void at32_setcallback(struct timer_lowerhalf_s *lower,
tccb_t callback, void *arg)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
irqstate_t flags = enter_critical_section();
/* Save the new callback */
priv->callback = callback;
priv->arg = arg;
if (callback != NULL && priv->started)
{
AT32_TIM_SETISR(priv->tim, at32_timer_handler, priv, 0);
AT32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE);
}
else
{
AT32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE);
AT32_TIM_SETISR(priv->tim, NULL, NULL, 0);
}
leave_critical_section(flags);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the
* form /dev/timer0
* timer - the timer's number.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int at32_timer_initialize(const char *devpath, int timer)
{
struct at32_lowerhalf_s *lower;
switch (timer)
{
#ifdef CONFIG_AT32_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM9
case 9:
lower = &g_tim9_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM10
case 10:
lower = &g_tim10_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM11
case 11:
lower = &g_tim11_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM12
case 12:
lower = &g_tim12_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM13
case 13:
lower = &g_tim13_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM14
case 14:
lower = &g_tim14_lowerhalf;
break;
#endif
#ifdef CONFIG_AT32_TIM20
case 20:
lower = &g_tim20_lowerhalf;
break;
#endif
default:
return -ENODEV;
}
/* Initialize the elements of lower half state structure */
lower->started = false;
lower->callback = NULL;
lower->tim = at32_tim_init(timer);
if (lower->tim == NULL)
{
return -EINVAL;
}
/* Register the timer driver as /dev/timerX. The returned value from
* timer_register is a handle that could be used with timer_unregister().
* REVISIT: The returned handle is discard here.
*/
void *drvr = timer_register(devpath,
(struct timer_lowerhalf_s *)lower);
if (drvr == NULL)
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
return OK;
}
#endif /* CONFIG_TIMER */

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/****************************************************************************
* arch/arm/src/at32/at32_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/arch_timer.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "systick.h"
#include "chip.h"
#include "at32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
* divided by 8. The SysTick can work either with this clock or with the
* Cortex clock (HCLK), configurable in the SysTick Control and Status
* register.
*/
#undef CONFIG_AT32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
/* And I don't know now to re-configure it yet */
#ifdef CONFIG_AT32_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((AT32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((AT32_HCLK_FREQUENCY / CLK_TCK) - 1)
#endif
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: at32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
static int at32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#ifdef CONFIG_AT32_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
#endif
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
up_timer_set_lowerhalf(systick_initialize(true, AT32_HCLK_FREQUENCY, -1));
#else
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
irq_attach(AT32_IRQ_SYSTICK, (xcpt_t)at32_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(AT32_IRQ_SYSTICK);
#endif
}

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/****************************************************************************
* arch/arm/src/at32/at32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_STC_AT32_AT32_UART_H
#define __ARCH_ARM_STC_AT32_AT32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip.h"
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_uart.h"
#else
# error "Unsupported AT32 UART"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
#if AT32_NUSART < 8 || !defined(CONFIG_AT32_HAVE_UART8)
# undef CONFIG_AT32_UART8
#endif
#if AT32_NUSART < 7 || !defined(CONFIG_AT32_HAVE_UART7)
# undef CONFIG_AT32_UART7
#endif
#if AT32_NUSART < 6 || !defined(CONFIG_AT32_HAVE_USART6)
# undef CONFIG_AT32_USART6
#endif
#if AT32_NUSART < 5 || !defined(CONFIG_AT32_HAVE_UART5)
# undef CONFIG_AT32_UART5
#endif
#if AT32_NUSART < 4 || !defined(CONFIG_AT32_HAVE_UART4)
# undef CONFIG_AT32_UART4
#endif
#if AT32_NUSART < 3 || !defined(CONFIG_AT32_HAVE_USART3)
# undef CONFIG_AT32_USART3
#endif
#if AT32_NUSART < 2
# undef CONFIG_AT32_USART2
#endif
#if AT32_NUSART < 1
# undef CONFIG_AT32_USART1
#endif
/* Sanity checks */
#if !defined(CONFIG_AT32_USART1)
# undef CONFIG_AT32_USART1_SERIALDRIVER
# undef CONFIG_AT32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_USART2)
# undef CONFIG_AT32_USART2_SERIALDRIVER
# undef CONFIG_AT32_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_USART3)
# undef CONFIG_AT32_USART3_SERIALDRIVER
# undef CONFIG_AT32_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_UART4)
# undef CONFIG_AT32_UART4_SERIALDRIVER
# undef CONFIG_AT32_UART4_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_UART5)
# undef CONFIG_AT32_UART5_SERIALDRIVER
# undef CONFIG_AT32_UART5_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_USART6)
# undef CONFIG_AT32_USART6_SERIALDRIVER
# undef CONFIG_AT32_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_UART7)
# undef CONFIG_AT32_UART7_SERIALDRIVER
# undef CONFIG_AT32_UART7_1WIREDRIVER
#endif
#if !defined(CONFIG_AT32_UART8)
# undef CONFIG_AT32_UART8_SERIALDRIVER
# undef CONFIG_AT32_UART8_1WIREDRIVER
#endif
/* Check 1-Wire and U(S)ART conflicts */
#if defined(CONFIG_AT32_USART1_1WIREDRIVER) && defined(CONFIG_AT32_USART1_SERIALDRIVER)
# error Both CONFIG_AT32_USART1_1WIREDRIVER and CONFIG_AT32_USART1_SERIALDRIVER defined
# undef CONFIG_AT32_USART1_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_USART2_1WIREDRIVER) && defined(CONFIG_AT32_USART2_SERIALDRIVER)
# error Both CONFIG_AT32_USART2_1WIREDRIVER and CONFIG_AT32_USART2_SERIALDRIVER defined
# undef CONFIG_AT32_USART2_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_USART3_1WIREDRIVER) && defined(CONFIG_AT32_USART3_SERIALDRIVER)
# error Both CONFIG_AT32_USART3_1WIREDRIVER and CONFIG_AT32_USART3_SERIALDRIVER defined
# undef CONFIG_AT32_USART3_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_UART4_1WIREDRIVER) && defined(CONFIG_AT32_UART4_SERIALDRIVER)
# error Both CONFIG_AT32_UART4_1WIREDRIVER and CONFIG_AT32_UART4_SERIALDRIVER defined
# undef CONFIG_AT32_UART4_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_UART5_1WIREDRIVER) && defined(CONFIG_AT32_UART5_SERIALDRIVER)
# error Both CONFIG_AT32_UART5_1WIREDRIVER and CONFIG_AT32_UART5_SERIALDRIVER defined
# undef CONFIG_AT32_UART5_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_USART6_1WIREDRIVER) && defined(CONFIG_AT32_USART6_SERIALDRIVER)
# error Both CONFIG_AT32_USART6_1WIREDRIVER and CONFIG_AT32_USART6_SERIALDRIVER defined
# undef CONFIG_AT32_USART6_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_UART7_1WIREDRIVER) && defined(CONFIG_AT32_UART7_SERIALDRIVER)
# error Both CONFIG_AT32_UART7_1WIREDRIVER and CONFIG_AT32_UART7_SERIALDRIVER defined
# undef CONFIG_AT32_UART7_1WIREDRIVER
#endif
#if defined(CONFIG_AT32_UART8_1WIREDRIVER) && defined(CONFIG_AT32_UART8_SERIALDRIVER)
# error Both CONFIG_AT32_UART8_1WIREDRIVER and CONFIG_AT32_UART8_SERIALDRIVER defined
# undef CONFIG_AT32_UART8_1WIREDRIVER
#endif
/* Is the serial driver enabled? */
#if defined(CONFIG_AT32_USART1_SERIALDRIVER) || defined(CONFIG_AT32_USART2_SERIALDRIVER) || \
defined(CONFIG_AT32_USART3_SERIALDRIVER) || defined(CONFIG_AT32_UART4_SERIALDRIVER) || \
defined(CONFIG_AT32_UART5_SERIALDRIVER) || defined(CONFIG_AT32_USART6_SERIALDRIVER) || \
defined(CONFIG_AT32_UART7_SERIALDRIVER) || defined(CONFIG_AT32_UART8_SERIALDRIVER)
# define HAVE_SERIALDRIVER 1
#endif
/* Is the 1-Wire driver? */
#if defined(CONFIG_AT32_USART1_1WIREDRIVER) || defined(CONFIG_AT32_USART2_1WIREDRIVER) || \
defined(CONFIG_AT32_USART3_1WIREDRIVER) || defined(CONFIG_AT32_UART4_1WIREDRIVER) || \
defined(CONFIG_AT32_UART5_1WIREDRIVER) || defined(CONFIG_AT32_USART6_1WIREDRIVER) || \
defined(CONFIG_AT32_UART7_1WIREDRIVER) || defined(CONFIG_AT32_UART8_1WIREDRIVER)
# define HAVE_1WIREDRIVER 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_AT32_USART1_SERIALDRIVER)
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_AT32_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_AT32_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_AT32_UART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_AT32_UART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_AT32_USART6_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_AT32_UART7_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_AT32_UART8_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define CONSOLE_UART 8
# define HAVE_CONSOLE 1
#else
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 0
# undef HAVE_CONSOLE
#endif
/* DMA support is only provided if CONFIG_ARCH_DMA is in the
* NuttX configuration
*/
#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA)
# undef CONFIG_USART1_RXDMA
# undef CONFIG_USART1_TXDMA
# undef CONFIG_USART2_RXDMA
# undef CONFIG_USART2_TXDMA
# undef CONFIG_USART3_RXDMA
# undef CONFIG_USART3_TXDMA
# undef CONFIG_UART4_RXDMA
# undef CONFIG_UART4_TXDMA
# undef CONFIG_UART5_RXDMA
# undef CONFIG_UART5_TXDMA
# undef CONFIG_USART6_RXDMA
# undef CONFIG_USART6_TXDMA
# undef CONFIG_UART7_RXDMA
# undef CONFIG_UART7_TXDMA
# undef CONFIG_UART8_RXDMA
# undef CONFIG_UART8_TXDMA
#endif
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_AT32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
# undef CONFIG_USART1_TXDMA
#endif
#ifndef CONFIG_AT32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
# undef CONFIG_USART2_TXDMA
#endif
#ifndef CONFIG_AT32_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
# undef CONFIG_USART3_TXDMA
#endif
#ifndef CONFIG_AT32_UART4_SERIALDRIVER
# undef CONFIG_UART4_RXDMA
# undef CONFIG_UART4_TXDMA
#endif
#ifndef CONFIG_AT32_UART5_SERIALDRIVER
# undef CONFIG_UART5_RXDMA
# undef CONFIG_UART5_TXDMA
#endif
#ifndef CONFIG_AT32_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
# undef CONFIG_USART6_TXDMA
#endif
#ifndef CONFIG_AT32_UART7_SERIALDRIVER
# undef CONFIG_UART7_RXDMA
# undef CONFIG_UART7_TXDMA
#endif
#ifndef CONFIG_AT32_UART8_SERIALDRIVER
# undef CONFIG_UART8_RXDMA
# undef CONFIG_UART8_TXDMA
#endif
/* Is DMA available on any (enabled) USART? */
#undef SERIAL_HAVE_RXDMA
#if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
defined(CONFIG_USART3_RXDMA) || defined(CONFIG_UART4_RXDMA) || \
defined(CONFIG_UART5_RXDMA) || defined(CONFIG_USART6_RXDMA) || \
defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA)
# define SERIAL_HAVE_RXDMA 1
#endif
/* Is TX DMA available on any (enabled) USART? */
#undef SERIAL_HAVE_TXDMA
#if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART2_TXDMA) || \
defined(CONFIG_USART3_TXDMA) || defined(CONFIG_UART4_TXDMA) || \
defined(CONFIG_UART5_TXDMA) || defined(CONFIG_USART6_TXDMA) || \
defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA)
# define SERIAL_HAVE_TXDMA 1
#endif
/* Is RX DMA used on the console UART? */
#undef SERIAL_HAVE_CONSOLE_RXDMA
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
#endif
/* Is TX DMA used on the console UART? */
#undef SERIAL_HAVE_CONSOLE_TXDMA
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
#endif
/* Is RX DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_RXDMA 1
#if defined(CONFIG_AT32_USART1) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_USART2) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_USART3) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_UART4) && !defined(CONFIG_UART4_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_UART5) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_USART6) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_UART7) && !defined(CONFIG_UART7_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_AT32_UART8) && !defined(CONFIG_UART8_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#endif
/* Is TX DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_TXDMA 1
#if defined(CONFIG_AT32_USART1) && !defined(CONFIG_USART1_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_USART2) && !defined(CONFIG_USART2_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_USART3) && !defined(CONFIG_USART3_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_UART4) && !defined(CONFIG_UART4_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_UART5) && !defined(CONFIG_UART5_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_USART6) && !defined(CONFIG_USART6_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_UART7) && !defined(CONFIG_UART7_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_AT32_UART8) && !defined(CONFIG_UART8_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#endif
#undef SERIAL_HAVE_ONLY_DMA
#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA)
# define SERIAL_HAVE_ONLY_DMA 1
#endif
/* No DMA ops */
#undef SERIAL_HAVE_NODMA_OPS
#if defined(CONFIG_AT32_USART1) && !defined(CONFIG_USART1_RXDMA) && \
!defined(CONFIG_USART1_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_USART2) && !defined(CONFIG_USART2_RXDMA) && \
!defined(CONFIG_USART2_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_USART3) && !defined(CONFIG_USART3_RXDMA) && \
!defined(CONFIG_USART3_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_UART4) && !defined(CONFIG_UART4_RXDMA) && \
!defined(CONFIG_UART4_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_UART5) && !defined(CONFIG_UART5_RXDMA) && \
!defined(CONFIG_UART5_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_USART6) && !defined(CONFIG_USART6_RXDMA) && \
!defined(CONFIG_USART6_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_UART7) && !defined(CONFIG_UART7_RXDMA) && \
!defined(CONFIG_UART7_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#elif defined(CONFIG_AT32_UART8) && !defined(CONFIG_UART8_RXDMA) && \
!defined(CONFIG_UART8_TXDMA)
# define SERIAL_HAVE_NODMA_OPS
#endif
/* RX+TX DMA ops */
#undef SERIAL_HAVE_RXTXDMA_OPS
#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#elif defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
# define SERIAL_HAVE_RXTXDMA_OPS
#endif
/* TX DMA ops */
#undef SERIAL_HAVE_TXDMA_OPS
#if !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
# define SERIAL_HAVE_TXDMA_OPS
#endif
/* RX DMA ops */
#undef SERIAL_HAVE_RXDMA_OPS
#if defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA)
# define SERIAL_HAVE_RXDMA_OPS
#endif
/* Is RS-485 used? */
#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \
defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485) || \
defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485) || \
defined(CONFIG_UART7_RS485) || defined(CONFIG_UART8_RS485)
# define HAVE_RS485 1
#endif
#ifdef HAVE_RS485
# define USART_CR1_USED_INTS (USART_CTRL1_RDBFIEN | USART_CTRL1_TDBEIEN | USART_CTRL1_PERRIEN | USART_CTRL1_TDCIEN)
#else
# define USART_CR1_USED_INTS (USART_CTRL1_RDBFIEN | USART_CTRL1_TDBEIEN | USART_CTRL1_PERRIEN)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_serial_get_uart
*
* Description:
* Get serial driver structure for AT32 USART
*
****************************************************************************/
uart_dev_t *at32_serial_get_uart(int uart_num);
/****************************************************************************
* Name: at32_serial_dma_poll
*
* Description:
* Must be called periodically if any AT32 UART is configured for DMA.
* The DMA callback is triggered for each fifo size/2 bytes, but this can
* result in some bytes being transferred but not collected if the incoming
* data is not a whole multiple of half the FIFO size.
*
* May be safely called from either interrupt or thread context.
*
****************************************************************************/
#ifdef SERIAL_HAVE_RXDMA
void at32_serial_dma_poll(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_AT32_AT32_UART_H */

46
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/****************************************************************************
* arch/arm/src/at32/at32_uid.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/at32_memorymap.h"
#include "at32_uid.h"
#ifdef AT32_SYSMEM_UID
/****************************************************************************
* Public Functions
****************************************************************************/
void at32_get_uniqueid(uint8_t uniqueid[12])
{
int i;
for (i = 0; i < 12; i++)
{
uniqueid[i] = *((uint8_t *)(AT32_SYSMEM_UID) + i);
}
}
#endif /* AT32_SYSMEM_UID */

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/****************************************************************************
* arch/arm/src/at32/at32_uid.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_UID_H
#define __ARCH_ARM_SRC_AT32_AT32_UID_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void at32_get_uniqueid(uint8_t uniqueid[12]);
#endif /* __ARCH_ARM_SRC_AT32_AT32_UID_H */

415
arch/arm/src/at32/at32_usbhost.c Normal file
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/****************************************************************************
* arch/arm/src/at32/at32_usbhost.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "at32_usbhost.h"
#ifdef HAVE_USBHOST_TRACE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define TR_FMT1 false
#define TR_FMT2 true
#define TRENTRY(id,fmt1,string) {string}
/****************************************************************************
* Private Types
****************************************************************************/
struct at32_usbhost_trace_s
{
#if 0
uint16_t id;
bool fmt2;
#endif
const char *string;
};
/****************************************************************************
* Private Data
****************************************************************************/
static const struct at32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] =
{
#ifdef CONFIG_AT32_OTGFS
TRENTRY(OTGFS_TRACE1_DEVDISCONN,
TR_FMT1,
"OTGFS ERROR: Host Port %d. Device disconnected\n"),
TRENTRY(OTGFS_TRACE1_IRQATTACH,
TR_FMT1,
"OTGFS ERROR: Failed to attach IRQ\n"),
TRENTRY(OTGFS_TRACE1_TRNSFRFAILED,
TR_FMT1,
"OTGFS ERROR: Transfer Failed. ret=%d\n"),
TRENTRY(OTGFS_TRACE1_SENDSETUP,
TR_FMT1,
"OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"),
TRENTRY(OTGFS_TRACE1_SENDDATA,
TR_FMT1,
"OTGFS ERROR: ctrl_senddata() failed with: %d\n"),
TRENTRY(OTGFS_TRACE1_RECVDATA,
TR_FMT1,
"OTGFS ERROR: ctrl_recvdata() failed with: %d\n"),
# ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OTGFS_VTRACE1_CONNECTED,
TR_FMT1,
"OTGFS Host Port %d connected.\n"),
TRENTRY(OTGFS_VTRACE1_DISCONNECTED,
TR_FMT1,
"OTGFS Host Port %d disconnected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT,
TR_FMT1,
"OTGFS Handling Interrupt. Entry Point.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_SOF,
TR_FMT1,
"OTGFS Handle the start of frame interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL,
TR_FMT1,
"OTGFS Handle the RxFIFO non-empty interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE,
TR_FMT1,
"OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_PTXFE,
TR_FMT1,
"OTGFS Handle the periodic TxFIFO empty interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HC,
TR_FMT1,
"OTGFS Handle the host channels interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT,
TR_FMT1,
"OTGFS Handle the host port interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG,
TR_FMT1,
"OTGFS HPRT: Port Over-Current Change.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET,
TR_FMT1,
"OTGFS HPRT: Port Connect Detect.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG,
TR_FMT1,
"OTGFS HPRT: Port Enable Changed.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV,
TR_FMT1,
"OTGFS HPRT: Low Speed Device Connected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV,
TR_FMT1,
"OTGFS HPRT: Full Speed Device Connected.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW,
TR_FMT1,
"OTGFS HPRT: Host Switch: LS -> FS.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW,
TR_FMT1,
"OTGFS HPRT: Host Switch: FS -> LS.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_DISC,
TR_FMT1,
"OTGFS Handle the disconnect detected interrupt.\n"),
TRENTRY(OTGFS_VTRACE1_GINT_IPXFR,
TR_FMT1,
"OTGFS Handle the incomplete periodic transfer.\n"),
# endif
#endif
#ifdef CONFIG_AT32_OTGHS
TRENTRY(OTGHS_TRACE1_DEVDISCONN,
TR_FMT1,
"OTGHS ERROR: Host Port %d. Device disconnected\n"),
TRENTRY(OTGHS_TRACE1_IRQATTACH,
TR_FMT1,
"OTGHS ERROR: Failed to attach IRQ\n"),
TRENTRY(OTGHS_TRACE1_TRNSFRFAILED,
TR_FMT1,
"OTGHS ERROR: Transfer Failed. ret=%d\n"),
TRENTRY(OTGHS_TRACE1_SENDSETUP,
TR_FMT1,
"OTGHS ERROR: ctrl_sendsetup() failed with: %d\n"),
TRENTRY(OTGHS_TRACE1_SENDDATA,
TR_FMT1,
"OTGHS ERROR: ctrl_senddata() failed with: %d\n"),
TRENTRY(OTGHS_TRACE1_RECVDATA,
TR_FMT1,
"OTGHS ERROR: ctrl_recvdata() failed with: %d\n"),
# ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OTGHS_VTRACE1_CONNECTED,
TR_FMT1,
"OTGHS Host Port %d connected.\n"),
TRENTRY(OTGHS_VTRACE1_DISCONNECTED,
TR_FMT1,
"OTGHS Host Port %d disconnected.\n"),
TRENTRY(OTGHS_VTRACE1_GINT,
TR_FMT1,
"OTGHS Handling Interrupt. Entry Point.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_SOF,
TR_FMT1,
"OTGHS Handle the start of frame interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_RXFLVL,
TR_FMT1,
"OTGHS Handle the RxFIFO non-empty interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_NPTXFE,
TR_FMT1,
"OTGHS Handle the non-periodic TxFIFO empty interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_PTXFE,
TR_FMT1,
"OTGHS Handle the periodic TxFIFO empty interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HC,
TR_FMT1,
"OTGHS Handle the host channels interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT,
TR_FMT1,
"OTGHS Handle the host port interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_POCCHNG,
TR_FMT1,
"OTGHS HPRT: Port Over-Current Change.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PCDET,
TR_FMT1,
"OTGHS HPRT: Port Connect Detect.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PENCHNG,
TR_FMT1,
"OTGHS HPRT: Port Enable Changed.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSDEV,
TR_FMT1,
"OTGHS HPRT: Low Speed Device Connected.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSDEV,
TR_FMT1,
"OTGHS HPRT: Full Speed Device Connected.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSHSSW,
TR_FMT1,
"OTGHS HPRT: Host Switch: LS -> HS.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSLSSW,
TR_FMT1,
"OTGHS HPRT: Host Switch: HS -> LS.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_DISC,
TR_FMT1,
"OTGHS Handle the disconnect detected interrupt.\n"),
TRENTRY(OTGHS_VTRACE1_GINT_IPXFR,
TR_FMT1,
"OTGHS Handle the incomplete periodic transfer.\n"),
# endif
#endif
};
static const struct at32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
{
#ifdef CONFIG_AT32_OTGFS
TRENTRY(OTGFS_TRACE2_CLIP,
TR_FMT2,
"OTGFS CLIP: chidx: %d buflen: %d\n"),
# ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN,
TR_FMT2,
"OTGFS EP%d(IN) wake up with result: %d\n"),
TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT,
TR_FMT2,
"OTGFS EP%d(OUT) wake up with result: %d\n"),
TRENTRY(OTGFS_VTRACE2_CTRLIN,
TR_FMT2,
"OTGFS CTRL_IN type: %02x req: %02x\n"),
TRENTRY(OTGFS_VTRACE2_CTRLOUT,
TR_FMT2,
"OTGFS CTRL_OUT type: %02x req: %02x\n"),
TRENTRY(OTGFS_VTRACE2_INTRIN,
TR_FMT2,
"OTGFS INTR_IN chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_INTROUT,
TR_FMT2,
"OTGFS INTR_OUT chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_BULKIN,
TR_FMT2,
"OTGFS BULK_IN chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_BULKOUT,
TR_FMT2,
"OTGFS BULK_OUT chidx: %02x len: %02x\n"),
TRENTRY(OTGFS_VTRACE2_ISOCIN,
TR_FMT2,
"OTGFS ISOC_IN chidx: %02x len: %04d\n"),
TRENTRY(OTGFS_VTRACE2_ISOCOUT,
TR_FMT2,
"OTGFS ISOC_OUT chidx: %02x req: %02x\n"),
TRENTRY(OTGFS_VTRACE2_STARTTRANSFER,
TR_FMT2,
"OTGFS Transfer chidx: %d buflen: %d\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"),
TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT,
TR_FMT2,
"OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"),
TRENTRY(OTGFS_VTRACE2_CHANHALT,
TR_FMT2,
"OTGFS Channel halted. chidx: %d, reason: %d\n"),
# endif
#endif
#ifdef CONFIG_AT32_OTGHS
TRENTRY(OTGHS_TRACE2_CLIP,
TR_FMT2,
"OTGHS CLIP: chidx: %d buflen: %d\n"),
# ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_IN,
TR_FMT2,
"OTGHS EP%d(IN) wake up with result: %d\n"),
TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_OUT,
TR_FMT2,
"OTGHS EP%d(OUT) wake up with result: %d\n"),
TRENTRY(OTGHS_VTRACE2_CTRLIN,
TR_FMT2,
"OTGHS CTRL_IN type: %02x req: %02x\n"),
TRENTRY(OTGHS_VTRACE2_CTRLOUT,
TR_FMT2,
"OTGHS CTRL_OUT type: %02x req: %02x\n"),
TRENTRY(OTGHS_VTRACE2_INTRIN,
TR_FMT2,
"OTGHS INTR_IN chidx: %02x len: %02x\n"),
TRENTRY(OTGHS_VTRACE2_INTROUT,
TR_FMT2,
"OTGHS INTR_OUT chidx: %02x len: %02x\n"),
TRENTRY(OTGHS_VTRACE2_BULKIN,
TR_FMT2,
"OTGHS BULK_IN chidx: %02x len: %02x\n"),
TRENTRY(OTGHS_VTRACE2_BULKOUT,
TR_FMT2,
"OTGHS BULK_OUT chidx: %02x len: %02x\n"),
TRENTRY(OTGHS_VTRACE2_ISOCIN,
TR_FMT2,
"OTGHS ISOC_IN chidx: %02x len: %04d\n"),
TRENTRY(OTGHS_VTRACE2_ISOCOUT,
TR_FMT2,
"OTGHS ISOC_OUT chidx: %02x req: %02x\n"),
TRENTRY(OTGHS_VTRACE2_STARTTRANSFER,
TR_FMT2,
"OTGHS Transfer chidx: %d buflen: %d\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_IN,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_OUT,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_IN,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_OUT,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_IN,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_OUT,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_IN,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"),
TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_OUT,
TR_FMT2,
"OTGHS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"),
TRENTRY(OTGHS_VTRACE2_CHANHALT,
TR_FMT2,
"OTGHS Channel halted. chidx: %d, reason: %d\n"),
# endif
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: usbhost_trformat1 and usbhost_trformat2
*
* Description:
* This interface must be provided by platform specific logic that knows
* the HCDs encoding of USB trace data.
*
* Given an 9-bit index, return a format string suitable for use with, say,
* printf. The returned format is expected to handle two unsigned integer
* values.
*
****************************************************************************/
const char *usbhost_trformat1(uint16_t id)
{
int ndx = TRACE1_INDEX(id);
if (ndx < TRACE1_NSTRINGS)
{
return g_trace1[ndx].string;
}
return NULL;
}
const char *usbhost_trformat2(uint16_t id)
{
int ndx = TRACE2_INDEX(id);
if (ndx < TRACE2_NSTRINGS)
{
return g_trace2[ndx].string;
}
return NULL;
}
#endif /* HAVE_USBHOST_TRACE */

280
arch/arm/src/at32/at32_usbhost.h Normal file
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@ -0,0 +1,280 @@
/****************************************************************************
* arch/arm/src/at32/at32_usbhost.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_USBHOST_H
#define __ARCH_ARM_SRC_AT32_AT32_USBHOST_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbhost_trace.h>
#include <stdint.h>
#include "chip.h"
#include "hardware/at32fxxxxx_otgfs.h"
#if (defined(CONFIG_AT32_OTGFS) || defined(CONFIG_AT32_OTGHS)) && \
defined(CONFIG_AT32_USBHOST)
/****************************************************************************
* Public Types
****************************************************************************/
#ifdef HAVE_USBHOST_TRACE
enum usbhost_trace1codes_e
{
__TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */
#ifdef CONFIG_AT32_OTGFS
OTGFS_TRACE1_DEVDISCONN, /* OTGFS ERROR: Host Port Device disconnected */
OTGFS_TRACE1_IRQATTACH, /* OTGFS ERROR: Failed to attach IRQ */
OTGFS_TRACE1_TRNSFRFAILED, /* OTGFS ERROR: Host Port Transfer Failed */
OTGFS_TRACE1_SENDSETUP, /* OTGFS ERROR: sendsetup() failed with: */
OTGFS_TRACE1_SENDDATA, /* OTGFS ERROR: senddata() failed with: */
OTGFS_TRACE1_RECVDATA, /* OTGFS ERROR: recvdata() failed with: */
# ifdef HAVE_USBHOST_TRACE_VERBOSE
OTGFS_VTRACE1_CONNECTED, /* OTGFS Host Port connected */
OTGFS_VTRACE1_DISCONNECTED, /* OTGFS Host Port disconnected */
OTGFS_VTRACE1_GINT, /* OTGFS Handling Interrupt. Entry Point */
OTGFS_VTRACE1_GINT_SOF, /* OTGFS Handle the start of frame interrupt */
OTGFS_VTRACE1_GINT_RXFLVL, /* OTGFS Handle the RxFIFO non-empty interrupt */
OTGFS_VTRACE1_GINT_NPTXFE, /* OTGFS Handle the non-periodic TxFIFO empty interrupt */
OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */
OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */
OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */
OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */
OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */
OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */
OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */
OTGFS_VTRACE1_GINT_HPRT_FSDEV, /* OTGFS HPRT: Full Speed Device Connected */
OTGFS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGFS HPRT: Host Switch: LS -> FS */
OTGFS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGFS HPRT: Host Switch: FS -> LS */
OTGFS_VTRACE1_GINT_DISC, /* OTGFS Handle the disconnect detected interrupt */
OTGFS_VTRACE1_GINT_IPXFR, /* OTGFS Handle the incomplete periodic transfer */
# endif
#endif
#ifdef CONFIG_AT32_OTGHS
OTGHS_TRACE1_DEVDISCONN, /* OTGHS ERROR: Host Port Device disconnected */
OTGHS_TRACE1_IRQATTACH, /* OTGHS ERROR: Failed to attach IRQ */
OTGHS_TRACE1_TRNSFRFAILED, /* OTGHS ERROR: Host Port Transfer Failed */
OTGHS_TRACE1_SENDSETUP, /* OTGHS ERROR: sendsetup() failed with: */
OTGHS_TRACE1_SENDDATA, /* OTGHS ERROR: senddata() failed with: */
OTGHS_TRACE1_RECVDATA, /* OTGHS ERROR: recvdata() failed with: */
# ifdef HAVE_USBHOST_TRACE_VERBOSE
OTGHS_VTRACE1_CONNECTED, /* OTGHS Host Port connected */
OTGHS_VTRACE1_DISCONNECTED, /* OTGHS Host Port disconnected */
OTGHS_VTRACE1_GINT, /* OTGHS Handling Interrupt. Entry Point */
OTGHS_VTRACE1_GINT_SOF, /* OTGHS Handle the start of frame interrupt */
OTGHS_VTRACE1_GINT_RXFLVL, /* OTGHS Handle the RxFIFO non-empty interrupt */
OTGHS_VTRACE1_GINT_NPTXFE, /* OTGHS Handle the non-periodic TxFIFO empty interrupt */
OTGHS_VTRACE1_GINT_PTXFE, /* OTGHS Handle the periodic TxFIFO empty interrupt */
OTGHS_VTRACE1_GINT_HC, /* OTGHS Handle the host channels interrupt */
OTGHS_VTRACE1_GINT_HPRT, /* OTGHS Handle the host port interrupt */
OTGHS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGHS HPRT: Port Over-Current Change */
OTGHS_VTRACE1_GINT_HPRT_PCDET, /* OTGHS HPRT: Port Connect Detect */
OTGHS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGHS HPRT: Port Enable Changed */
OTGHS_VTRACE1_GINT_HPRT_LSDEV, /* OTGHS HPRT: Low Speed Device Connected */
OTGHS_VTRACE1_GINT_HPRT_FSDEV, /* OTGHS HPRT: Full Speed Device Connected */
OTGHS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGHS HPRT: Host Switch: LS -> FS */
OTGHS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGHS HPRT: Host Switch: FS -> LS */
OTGHS_VTRACE1_GINT_DISC, /* OTGHS Handle the disconnect detected interrupt */
OTGHS_VTRACE1_GINT_IPXFR, /* OTGHS Handle the incomplete periodic transfer */
# endif
#endif
__TRACE1_NSTRINGS, /* Separates the format 1 from the format 2 strings */
#ifdef CONFIG_AT32_OTGFS
OTGFS_TRACE2_CLIP, /* OTGFS CLIP: chidx: buflen: */
# ifdef HAVE_USBHOST_TRACE_VERBOSE
OTGFS_VTRACE2_CHANWAKEUP_IN, /* OTGFS IN Channel wake up with result */
OTGFS_VTRACE2_CHANWAKEUP_OUT, /* OTGFS OUT Channel wake up with result */
OTGFS_VTRACE2_CTRLIN, /* OTGFS CTRLIN */
OTGFS_VTRACE2_CTRLOUT, /* OTGFS CTRLOUT */
OTGFS_VTRACE2_INTRIN, /* OTGFS INTRIN */
OTGFS_VTRACE2_INTROUT, /* OTGFS INTROUT */
OTGFS_VTRACE2_BULKIN, /* OTGFS BULKIN */
OTGFS_VTRACE2_BULKOUT, /* OTGFS BULKOUT */
OTGFS_VTRACE2_ISOCIN, /* OTGFS ISOCIN */
OTGFS_VTRACE2_ISOCOUT, /* OTGFS ISOCOUT */
OTGFS_VTRACE2_STARTTRANSFER, /* OTGFS EP buflen */
OTGFS_VTRACE2_CHANCONF_CTRL_IN,
OTGFS_VTRACE2_CHANCONF_CTRL_OUT,
OTGFS_VTRACE2_CHANCONF_INTR_IN,
OTGFS_VTRACE2_CHANCONF_INTR_OUT,
OTGFS_VTRACE2_CHANCONF_BULK_IN,
OTGFS_VTRACE2_CHANCONF_BULK_OUT,
OTGFS_VTRACE2_CHANCONF_ISOC_IN,
OTGFS_VTRACE2_CHANCONF_ISOC_OUT,
OTGFS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */
# endif
#endif
#ifdef CONFIG_AT32_OTGHS
OTGHS_TRACE2_CLIP, /* OTGHS CLIP: chidx: buflen: */
# ifdef HAVE_USBHOST_TRACE_VERBOSE
OTGHS_VTRACE2_CHANWAKEUP_IN, /* OTGHS IN Channel wake up with result */
OTGHS_VTRACE2_CHANWAKEUP_OUT, /* OTGHS OUT Channel wake up with result */
OTGHS_VTRACE2_CTRLIN, /* OTGHS CTRLIN */
OTGHS_VTRACE2_CTRLOUT, /* OTGHS CTRLOUT */
OTGHS_VTRACE2_INTRIN, /* OTGHS INTRIN */
OTGHS_VTRACE2_INTROUT, /* OTGHS INTROUT */
OTGHS_VTRACE2_BULKIN, /* OTGHS BULKIN */
OTGHS_VTRACE2_BULKOUT, /* OTGHS BULKOUT */
OTGHS_VTRACE2_ISOCIN, /* OTGHS ISOCIN */
OTGHS_VTRACE2_ISOCOUT, /* OTGHS ISOCOUT */
OTGHS_VTRACE2_STARTTRANSFER, /* OTGHS EP buflen */
OTGHS_VTRACE2_CHANCONF_CTRL_IN,
OTGHS_VTRACE2_CHANCONF_CTRL_OUT,
OTGHS_VTRACE2_CHANCONF_INTR_IN,
OTGHS_VTRACE2_CHANCONF_INTR_OUT,
OTGHS_VTRACE2_CHANCONF_BULK_IN,
OTGHS_VTRACE2_CHANCONF_BULK_OUT,
OTGHS_VTRACE2_CHANCONF_ISOC_IN,
OTGHS_VTRACE2_CHANCONF_ISOC_OUT,
OTGHS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */
# endif
#endif
__TRACE2_NSTRINGS /* Total number of enumeration values */
};
# define TRACE1_FIRST ((int)__TRACE1_BASEVALUE + 1)
# define TRACE1_INDEX(id) ((int)(id) - TRACE1_FIRST)
# define TRACE1_NSTRINGS TRACE1_INDEX(__TRACE1_NSTRINGS)
# define TRACE2_FIRST ((int)__TRACE1_NSTRINGS + 1)
# define TRACE2_INDEX(id) ((int)(id) - TRACE2_FIRST)
# define TRACE2_NSTRINGS TRACE2_INDEX(__TRACE2_NSTRINGS)
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* AT32 USB OTG FS Host Driver Support
*
* Pre-requisites
*
* CONFIG_AT32_USBHOST - Enable general USB host support
* CONFIG_USBHOST - Enable general USB host support
* CONFIG_AT32_OTGFS - Enable the AT32 USB OTG FS block
* or
* CONFIG_AT32_OTGHS - Enable the AT32 USB OTG HS block
* CONFIG_AT32_SYSCFG - Needed
*
* Options:
*
* CONFIG_AT32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
* Default 128 (512 bytes)
* CONFIG_AT32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
* in 32-bit words. Default 96 (384 bytes)
* CONFIG_AT32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
* words. Default 96 (384 bytes)
* CONFIG_AT32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
*
* CONFIG_AT32_OTGHS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
* Default 128 (512 bytes)
* CONFIG_AT32_OTGHS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
* in 32-bit words. Default 96 (384 bytes)
* CONFIG_AT32_OTGHS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
* words. Default 96 (384 bytes)
* CONFIG_AT32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
*
* CONFIG_AT32_USBHOST_REGDEBUG - Enable very low-level register access
* debug. Depends on CONFIG_DEBUG_FEATURES.
*/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: at32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided be each platform that implements the AT32 OTG FS host
* interface.
*
* "On-chip 5 V VBUS generation is not supported. For this reason, a
* charge pump or, if 5 V are available on the application board, a basic
* power switch, must be added externally to drive the 5 V VBUS line. The
* external charge pump can be driven by any GPIO output. When the
* application decides to power on VBUS using the chosen GPIO, it must
* also set the port power bit in the host port control and status
* register (PPWR bit in OTG_FS_HPRT).
*
* "The application uses this field to control power to this port, and the
* core clears this bit on an overcurrent condition."
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface.
* Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_AT32_OTGFS_VBUS_CONTROL) || \
defined(CONFIG_AT32_OTGHS_VBUS_CONTROL)
void at32_usbhost_vbusdrive(int iface, bool enable);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_AT32_OTGFS && CONFIG_AT32_USBHOST */
#endif /* __ARCH_ARM_SRC_AT32_AT32_USBHOST_H */

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/****************************************************************************
* arch/arm/src/at32/at32_userspace.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "at32_mpuinit.h"
#include "at32_userspace.h"
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
void at32_userspace(void)
{
uint8_t *src;
uint8_t *dest;
uint8_t *end;
/* Clear all of user-space .bss */
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
*dest++ = 0;
}
/* Initialize all of user-space .data */
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{
*dest++ = *src++;
}
/* Configure the MPU to permit user-space access to its FLASH and RAM */
at32_mpuinitialize();
}
#endif /* CONFIG_BUILD_PROTECTED */

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/****************************************************************************
* arch/arm/src/at32/at32_userspace.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_USERSPACE_H
#define __ARCH_ARM_SRC_AT32_AT32_USERSPACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void at32_userspace(void);
#endif
#endif /* __ARCH_ARM_SRC_AT32_AT32_USERSPACE_H */

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/****************************************************************************
* arch/arm/src/at32/at32_waste.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "at32_waste.h"
/****************************************************************************
* Public Data
****************************************************************************/
uint32_t g_waste_counter = 0;
/****************************************************************************
* Public Functions
****************************************************************************/
void at32_waste(void)
{
g_waste_counter++;
}

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/****************************************************************************
* arch/arm/src/at32/at32_waste.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_WASTE_H
#define __ARCH_ARM_SRC_AT32_AT32_WASTE_H
/* Waste CPU Time */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/** Waste CPU Time
*
* at32_waste() is the logic that will be executed when portions of kernel
* or user-app is polling some register or similar, waiting for desired
* status. This time is wasted away. This function offers a measure of
* badly written piece of software or some undesired behavior.
*
* At the same time this function adds to some IDLE time which portion
* cannot be used for other purposes (yet).
**/
void at32_waste(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AT32_AT32_WASTE_H */

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/****************************************************************************
* arch/arm/src/at32/at32_wdg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32_WDG_H
#define __ARCH_ARM_SRC_AT32_AT32_WDG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/at32_wdg.h"
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog time. The watchdog timer is initialized
* and registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_AT32_IWDG
void at32_iwdginitialize(const char *devpath, uint32_t lsifreq);
#endif
/****************************************************************************
* Name: at32_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog time. The watchdog timer is initializeed
* and registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_AT32_WWDG
void at32_wwdginitialize(const char *devpath);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
#endif /* __ARCH_ARM_SRC_AT32_AT32_WDG_H */

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/****************************************************************************
* arch/arm/src/at32/at32_wwdg.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/timers/watchdog.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "hardware/at32_dbgmcu.h"
#include "at32_wdg.h"
#if defined(CONFIG_WATCHDOG) && defined(CONFIG_AT32_WWDG)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The minimum frequency of the WWDG clock is:
*
* Fmin = PCLK1 / 4096 / 8
*
* So the maximum delay (in milliseconds) is then:
*
* 1000 * (WWDG_CR_T_MAX+1) / Fmin
*
* For example, if PCLK1 = 42MHz, then the maximum delay is:
*
* Fmin = 1281.74
* 1000 * 64 / Fmin = 49.93 msec
*/
#define WWDG_FMIN (AT32_PCLK1_FREQUENCY / 4096 / 8)
#define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN)
/* Configuration ************************************************************/
#ifndef CONFIG_AT32_WWDG_DEFTIMOUT
# define CONFIG_AT32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT
#endif
#ifndef CONFIG_DEBUG_WATCHDOG_INFO
# undef CONFIG_AT32_WWDG_REGDEBUG
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
*/
struct at32_lowerhalf_s
{
const struct watchdog_ops_s *ops; /* Lower half operations */
xcpt_t handler; /* Current EWI interrupt handler */
uint32_t timeout; /* The actual timeout value */
uint32_t fwwdg; /* WWDG clock frequency */
bool started; /* The timer has been started */
uint8_t reload; /* The 7-bit reload field reset value */
uint8_t window; /* The 7-bit window (W) field value */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_AT32_WWDG_REGDEBUG
static uint16_t at32_getreg(uint32_t addr);
static void at32_putreg(uint16_t val, uint32_t addr);
#else
# define at32_getreg(addr) getreg32(addr)
# define at32_putreg(val,addr) putreg32(val,addr)
#endif
static void at32_setwindow(struct at32_lowerhalf_s *priv,
uint8_t window);
/* Interrupt handling *******************************************************/
static int at32_interrupt(int irq, void *context, void *arg);
/* "Lower half" driver methods **********************************************/
static int at32_start(struct watchdog_lowerhalf_s *lower);
static int at32_stop(struct watchdog_lowerhalf_s *lower);
static int at32_keepalive(struct watchdog_lowerhalf_s *lower);
static int at32_getstatus(struct watchdog_lowerhalf_s *lower,
struct watchdog_status_s *status);
static int at32_settimeout(struct watchdog_lowerhalf_s *lower,
uint32_t timeout);
static xcpt_t at32_capture(struct watchdog_lowerhalf_s *lower,
xcpt_t handler);
static int at32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
{
.start = at32_start,
.stop = at32_stop,
.keepalive = at32_keepalive,
.getstatus = at32_getstatus,
.settimeout = at32_settimeout,
.capture = at32_capture,
.ioctl = at32_ioctl,
};
/* "Lower half" driver state */
static struct at32_lowerhalf_s g_wdgdev;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: at32_getreg
*
* Description:
* Get the contents of an AT32 register
*
****************************************************************************/
#ifdef CONFIG_AT32_WWDG_REGDEBUG
static uint16_t at32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
static uint32_t count = 0;
static uint16_t preval = 0;
/* Read the value from the register */
uint16_t val = getreg16(addr);
/* Is this the same value that we read from the same register last time?
* Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
wdinfo("...\n");
}
return val;
}
}
/* No this is a new address or value */
else
{
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
wdinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
/****************************************************************************
* Name: at32_putreg
*
* Description:
* Set the contents of an AT32 register to a value
*
****************************************************************************/
#ifdef CONFIG_AT32_WWDG_REGDEBUG
static void at32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
wdinfo("%08x<-%04x\n", addr, val);
/* Write the value */
putreg16(val, addr);
}
#endif
/****************************************************************************
* Name: at32_setwindow
*
* Description:
* Set the CFR window value. The window value is compared to the down-
* counter when the counter is updated. The WWDG counter should be updated
* only when the counter is below this window value (and greater than 64)
* otherwise a reset will be generated
*
****************************************************************************/
static void at32_setwindow(struct at32_lowerhalf_s *priv,
uint8_t window)
{
uint16_t regval;
/* Set W[6:0] bits according to selected window value */
regval = at32_getreg(AT32_WWDG_CFR);
regval &= ~WWDG_CFR_W_MASK;
regval |= window << WWDG_CFR_W_SHIFT;
at32_putreg(regval, AT32_WWDG_CFR);
/* Remember the window setting */
priv->window = window;
}
/****************************************************************************
* Name: at32_interrupt
*
* Description:
* WWDG early warning interrupt
*
* Input Parameters:
* Usual interrupt handler arguments.
*
* Returned Value:
* Always returns OK.
*
****************************************************************************/
static int at32_interrupt(int irq, void *context, void *arg)
{
struct at32_lowerhalf_s *priv = &g_wdgdev;
uint16_t regval;
/* Check if the EWI interrupt is really pending */
regval = at32_getreg(AT32_WWDG_SR);
if ((regval & WWDG_SR_EWIF) != 0)
{
/* Is there a registered handler? */
if (priv->handler)
{
/* Yes... NOTE: This interrupt service routine (ISR) must reload
* the WWDG counter to prevent the reset. Otherwise, we will reset
* upon return.
*/
priv->handler(irq, context, arg);
}
/* The EWI interrupt is cleared by writing '0' to the EWIF bit in the
* WWDG_SR register.
*/
regval &= ~WWDG_SR_EWIF;
at32_putreg(regval, AT32_WWDG_SR);
}
return OK;
}
/****************************************************************************
* Name: at32_start
*
* Description:
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_start(struct watchdog_lowerhalf_s *lower)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* The watchdog is always disabled after a reset. It is enabled by setting
* the WDGA bit in the WWDG_CR register, then it cannot be disabled again
* except by a reset.
*/
at32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, AT32_WWDG_CR);
priv->started = true;
return OK;
}
/****************************************************************************
* Name: at32_stop
*
* Description:
* Stop the watchdog timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_stop(struct watchdog_lowerhalf_s *lower)
{
/* The watchdog is always disabled after a reset. It is enabled by setting
* the WDGA bit in the WWDG_CR register, then it cannot be disabled again
* except by a reset.
*/
wdinfo("Entry\n");
return -ENOSYS;
}
/****************************************************************************
* Name: at32_keepalive
*
* Description:
* Reset the watchdog timer to the current timeout value, prevent any
* imminent watchdog timeouts. This is sometimes referred as "pinging"
* the watchdog timer or "petting the dog".
*
* The application program must write in the WWDG_CR register at regular
* intervals during normal operation to prevent an MCU reset. This
* operation must occur only when the counter value is lower than the
* window register value. The value to be stored in the WWDG_CR register
* must be between 0xff and 0xC0:
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_keepalive(struct watchdog_lowerhalf_s *lower)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Write to T[6:0] bits to configure the counter value, no need to do
* a read-modify-write; writing a 0 to WDGA bit does nothing.
*/
at32_putreg((WWDG_CR_T_RESET | priv->reload), AT32_WWDG_CR);
return OK;
}
/****************************************************************************
* Name: at32_getstatus
*
* Description:
* Get the current watchdog timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_getstatus(struct watchdog_lowerhalf_s *lower,
struct watchdog_status_s *status)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
uint32_t elapsed;
uint16_t reload;
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
status->flags = WDFLAGS_RESET;
if (priv->started)
{
status->flags |= WDFLAGS_ACTIVE;
}
if (priv->handler)
{
status->flags |= WDFLAGS_CAPTURE;
}
/* Return the actual timeout is milliseconds */
status->timeout = priv->timeout;
/* Get the time remaining until the watchdog expires (in milliseconds) */
reload = (at32_getreg(AT32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f;
elapsed = priv->reload - reload;
status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
wdinfo("Status :\n");
wdinfo(" flags : %08x\n", (unsigned)status->flags);
wdinfo(" timeout : %u\n", (unsigned)status->timeout);
wdinfo(" timeleft : %u\n", (unsigned)status->flags);
return OK;
}
/****************************************************************************
* Name: at32_settimeout
*
* Description:
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_settimeout(struct watchdog_lowerhalf_s *lower,
uint32_t timeout)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
uint32_t fwwdg;
uint32_t reload;
uint16_t regval;
int wdgtb;
DEBUGASSERT(priv);
wdinfo("Entry: timeout=%u\n", (unsigned)timeout);
/* Can this timeout be represented? */
if (timeout < 1 || timeout > WWDG_MAXTIMEOUT)
{
wderr("ERROR: Cannot represent timeout=%u > %lu\n",
(unsigned)timeout, WWDG_MAXTIMEOUT);
return -ERANGE;
}
/* Determine prescaler value.
*
* Fwwdg = PCLK1/4096/prescaler.
*
* Where
* Fwwwdg is the frequency of the WWDG clock
* wdgtb is one of {1, 2, 4, or 8}
*/
/* Select the smallest prescaler that will result in a reload field value
* that is less than the maximum.
*/
for (wdgtb = 0; ; wdgtb++)
{
/* WDGTB = 0 -> Divider = 1 = 1 << 0
* WDGTB = 1 -> Divider = 2 = 1 << 1
* WDGTB = 2 -> Divider = 4 = 1 << 2
* WDGTB = 3 -> Divider = 8 = 1 << 3
*/
/* Get the WWDG counter frequency in Hz. */
fwwdg = (AT32_PCLK1_FREQUENCY / 4096) >> wdgtb;
/* The formula to calculate the timeout value is given by:
*
* timeout = 1000 * (reload + 1) / Fwwdg, OR
* reload = timeout * Fwwdg / 1000 - 1
*
* Where
* timeout is the desired timeout in milliseconds
* reload is the contents of T{5:0]
* Fwwdg is the frequency of the WWDG clock
*/
reload = timeout * fwwdg / 1000 - 1;
/* If this reload valid is less than the maximum or we are not ready
* at the prescaler value, then break out of the loop to use these
* settings.
*/
#if 0
wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n",
wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg);
#endif
if (reload <= WWDG_CR_T_MAX || wdgtb == 3)
{
/* Note that we explicitly break out of the loop rather than using
* the 'for' loop termination logic because we do not want the
* value of wdgtb to be incremented.
*/
break;
}
}
/* Make sure that the final reload value is within range */
if (reload > WWDG_CR_T_MAX)
{
reload = WWDG_CR_T_MAX;
}
/* Calculate and save the actual timeout value in milliseconds:
*
* timeout = 1000 * (reload + 1) / Fwwdg
*/
priv->timeout = 1000 * (reload + 1) / fwwdg;
/* Remember the selected values */
priv->fwwdg = fwwdg;
priv->reload = reload;
wdinfo("wdgtb=%d fwwdg=%u reload=%u timeout=%u\n",
wdgtb, (unsigned)fwwdg, (unsigned)reload, (unsigned)priv->timeout);
/* Set WDGTB[1:0] bits according to calculated value */
regval = at32_getreg(AT32_WWDG_CFR);
regval &= ~WWDG_CFR_WDGTB_MASK;
regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT;
at32_putreg(regval, AT32_WWDG_CFR);
/* Reset the 7-bit window value to the maximum value.. essentially
* disabling the lower limit of the watchdog reset time.
*/
at32_setwindow(priv, 0x7f);
return OK;
}
/****************************************************************************
* Name: at32_capture
*
* Description:
* Don't reset on watchdog timer timeout; instead, call this user provider
* timeout handler. NOTE: Providing handler==NULL will restore the reset
* behavior.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* newhandler - The new watchdog expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
* Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
*
****************************************************************************/
static xcpt_t at32_capture(struct watchdog_lowerhalf_s *lower,
xcpt_t handler)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
irqstate_t flags;
xcpt_t oldhandler;
uint16_t regval;
DEBUGASSERT(priv);
wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
flags = enter_critical_section();
oldhandler = priv->handler;
/* Save the new handler */
priv->handler = handler;
/* Are we attaching or detaching the handler? */
regval = at32_getreg(AT32_WWDG_CFR);
if (handler)
{
/* Attaching... Enable the EWI interrupt */
regval |= WWDG_CFR_EWI;
at32_putreg(regval, AT32_WWDG_CFR);
up_enable_irq(AT32_IRQ_WWDG);
}
else
{
/* Detaching... Disable the EWI interrupt */
regval &= ~WWDG_CFR_EWI;
at32_putreg(regval, AT32_WWDG_CFR);
up_disable_irq(AT32_IRQ_WWDG);
}
leave_critical_section(flags);
return oldhandler;
}
/****************************************************************************
* Name: at32_ioctl
*
* Description:
* Any ioctl commands that are not recognized by the "upper-half" driver
* are forwarded to the lower half driver through this method.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
* cmd - The ioctl command value
* arg - The optional argument that accompanies the 'cmd'. The
* interpretation of this argument depends on the particular
* command.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int at32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg)
{
struct at32_lowerhalf_s *priv = (struct at32_lowerhalf_s *)lower;
int ret = -ENOTTY;
DEBUGASSERT(priv);
wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
/* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls
* are received within this time, a reset event will be generated.
* Argument: A 32-bit time value in milliseconds.
*/
if (cmd == WDIOC_MINTIME)
{
uint32_t mintime = (uint32_t)arg;
/* The minimum time should be strictly less than the total delay
* which, in turn, will be less than or equal to WWDG_CR_T_MAX
*/
ret = -EINVAL;
if (mintime < priv->timeout)
{
uint32_t window = (priv->timeout - mintime) * priv->fwwdg /
1000 - 1;
DEBUGASSERT(window < priv->reload);
at32_setwindow(priv, window | WWDG_CR_T_RESET);
ret = OK;
}
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog timer. The watchdog timer is initialized
* and registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
* Returned Value:
* None
*
****************************************************************************/
void at32_wwdginitialize(const char *devpath)
{
struct at32_lowerhalf_s *priv = &g_wdgdev;
wdinfo("Entry: devpath=%s\n", devpath);
/* NOTE we assume that clocking to the WWDG has already been provided by
* the RCC initialization logic.
*/
/* Initialize the driver state structure. Here we assume: (1) the state
* structure lies in .bss and was zeroed at reset time. (2) This function
* is only called once so it is never necessary to re-zero the structure.
*/
priv->ops = &g_wdgops;
/* Attach our EWI interrupt handler (But don't enable it yet) */
irq_attach(AT32_IRQ_WWDG, at32_interrupt, NULL);
/* Select an arbitrary initial timeout value. But don't start the watchdog
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
* device option bits, the watchdog is automatically enabled at power-on.
*/
at32_settimeout((struct watchdog_lowerhalf_s *)priv,
CONFIG_AT32_WWDG_DEFTIMOUT);
/* Register the watchdog driver as /dev/watchdog0 */
watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv);
/* When the microcontroller enters debug mode (Cortex-M core halted),
* the WWDG counter either continues to work normally or stops, depending
* on DBG_WWDG_STOP configuration bit in DBG module.
*/
#if defined(CONFIG_AT32_JTAG_FULL_ENABLE) || \
defined(CONFIG_AT32_JTAG_NOJNTRST_ENABLE) || \
defined(CONFIG_AT32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_AT32_AT32F43XX)
uint32_t cr = getreg32(AT32_DEBUG_APB1_PAUSE);
cr |= DEBUG_APB1_APUSE_WWDT_PAUSE;
putreg32(cr, AT32_DEBUG_APB1_PAUSE);
#endif
}
#endif
}
#endif /* CONFIG_WATCHDOG && CONFIG_AT32_WWDG */

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/****************************************************************************
* arch/arm/src/at32/at32f43xx_flash.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*
* Requirements during write/erase operations on FLASH:
* - HSI must be ON.
* - Low Power Modes are not permitted during write/erase
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/mutex.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include "at32_flash.h"
#include "at32_rcc.h"
#include "at32_waste.h"
#include "arm_internal.h"
/* Only for the AT32F43xx family. */
#if defined (CONFIG_AT32_AT32F43XX)
#if defined(CONFIG_AT32_FLASH_CONFIG_DEFAULT)
# warning "Default Flash Configuration Used - See Override Flash Size Designator"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xcdef89ab
#define FLASH_OPTKEY1 0x08192a3b
#define FLASH_OPTKEY2 0x4c5d6e7f
#define FLASH_ERASEDVALUE 0xff
/****************************************************************************
* Private Data
****************************************************************************/
static mutex_t g_lock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
****************************************************************************/
static void flash_unlock(void)
{
while (getreg32(AT32_FLASH_STS) & FLASH_STS_OBF)
{
at32_waste();
}
if (getreg32(AT32_FLASH_CTRL) & FLASH_CTRL_OPLK)
{
/* Unlock sequence */
putreg32(FLASH_KEY1, AT32_FLASH_UNLOCK);
putreg32(FLASH_KEY2, AT32_FLASH_UNLOCK);
}
#ifdef AT32_FLASH_BANK2_START
if (AT32_FLASH_BANK2_START < AT32_FLASH_NPAGES)
{
while (getreg32(AT32_FLASH_STS2) & FLASH_STS_OBF)
{
at32_waste();
}
if (getreg32(AT32_FLASH_CTRL2) & FLASH_CTRL_OPLK)
{
/* Unlock sequence */
putreg32(FLASH_KEY1, AT32_FLASH_UNLOCK2);
putreg32(FLASH_KEY2, AT32_FLASH_UNLOCK2);
}
}
#endif
}
static void flash_lock(void)
{
modifyreg32(AT32_FLASH_CTRL, 0, FLASH_CTRL_OPLK);
#ifdef AT32_FLASH_BANK2_START
if (AT32_FLASH_BANK2_START < AT32_FLASH_NPAGES)
modifyreg32(AT32_FLASH_CTRL2, 0, FLASH_CTRL_OPLK);
#endif
}
#if defined(CONFIG_AT32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
static void data_cache_disable(void)
{
modifyreg32(AT32_FLASH_PSR, FLASH_PSR_NZW_BST, 0);
}
static void data_cache_enable(void)
{
/* Enable data cache */
modifyreg32(AT32_FLASH_PSR, 0, FLASH_PSR_NZW_BST);
}
#endif /* defined(CONFIG_AT32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
/****************************************************************************
* Public Functions
****************************************************************************/
int at32_flash_unlock(void)
{
int ret;
ret = nxmutex_lock(&g_lock);
if (ret < 0)
{
return ret;
}
flash_unlock();
nxmutex_unlock(&g_lock);
return ret;
}
int at32_flash_lock(void)
{
int ret;
ret = nxmutex_lock(&g_lock);
if (ret < 0)
{
return ret;
}
flash_lock();
nxmutex_unlock(&g_lock);
return ret;
}
size_t up_progmem_pagesize(size_t page)
{
return AT32_FLASH_PAGESIZE;
}
size_t up_progmem_erasesize(size_t block)
{
return up_progmem_pagesize(block);
}
ssize_t up_progmem_getpage(size_t addr)
{
size_t page_end = 0;
size_t i;
if (addr >= AT32_FLASH_BASE)
{
addr -= AT32_FLASH_BASE;
}
if (addr >= AT32_FLASH_SIZE)
{
return -EFAULT;
}
for (i = 0; i < AT32_FLASH_NPAGES; ++i)
{
page_end += up_progmem_pagesize(i);
if (page_end > addr)
{
return i;
}
}
return -EFAULT;
}
size_t up_progmem_getaddress(size_t page)
{
size_t base_address = AT32_FLASH_BASE;
size_t i;
if (page >= AT32_FLASH_NPAGES)
{
return SIZE_MAX;
}
for (i = 0; i < page; ++i)
{
base_address += up_progmem_pagesize(i);
}
return base_address;
}
size_t up_progmem_neraseblocks(void)
{
return AT32_FLASH_NPAGES;
}
bool up_progmem_isuniform(void)
{
#ifdef AT32_FLASH_PAGESIZE
return true;
#else
return false;
#endif
}
ssize_t up_progmem_ispageerased(size_t page)
{
size_t addr;
size_t count;
size_t bwritten = 0;
if (page >= AT32_FLASH_NPAGES)
{
return -EFAULT;
}
/* Verify */
for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
count; count--, addr++)
{
if (getreg8(addr) != FLASH_ERASEDVALUE)
{
bwritten++;
}
}
return bwritten;
}
ssize_t up_progmem_eraseblock(size_t block)
{
unsigned int flash_ctrl;
unsigned int flash_addr;
unsigned int flash_sts;
if (block >= AT32_FLASH_NPAGES)
{
return -EFAULT;
}
#ifdef AT32_FLASH_BANK2_START
flash_ctrl = (block < AT32_FLASH_BANK2_START) ? \
AT32_FLASH_CTRL : AT32_FLASH_CTRL2;
flash_addr = (block < AT32_FLASH_BANK2_START) ? \
AT32_FLASH_ADDR : AT32_FLASH_ADDR2;
flash_sts = (block < AT32_FLASH_BANK2_START) ? \
AT32_FLASH_STS : AT32_FLASH_STS2;
#else
flash_ctrl = AT32_FLASH_CTRL;
flash_addr = AT32_FLASH_ADDR;
flash_sts = AT32_FLASH_STS;
#endif
nxmutex_lock(&g_lock);
/* Get flash ready and begin erasing single block */
flash_unlock();
modifyreg32(flash_ctrl, 0, FLASH_CTRL_SECERS);
modifyreg32(flash_addr, 0, block * AT32_FLASH_PAGESIZE);
modifyreg32(flash_ctrl, 0, FLASH_CTRL_ERSTR);
while (getreg32(flash_sts) & FLASH_STS_OBF)
{
at32_waste();
}
modifyreg32(flash_ctrl, FLASH_CTRL_SECERS, 0);
nxmutex_unlock(&g_lock);
/* Verify */
if (up_progmem_ispageerased(block) == 0)
{
return up_progmem_pagesize(block); /* success */
}
else
{
return -EIO; /* failure */
}
}
ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
{
uint16_t *hword = (uint16_t *)buf;
size_t written = count;
unsigned int flash_sts;
/* AT32 requires half-word access */
if (count & 1)
{
return -EINVAL;
}
/* Check for valid address range */
if (addr >= AT32_FLASH_BASE)
{
addr -= AT32_FLASH_BASE;
}
if ((addr + count) > AT32_FLASH_SIZE)
{
return -EFAULT;
}
nxmutex_lock(&g_lock);
/* Get flash ready and begin flashing */
flash_unlock();
#if defined(CONFIG_AT32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
data_cache_disable();
#endif
modifyreg32(AT32_FLASH_CTRL, 0, FLASH_CTRL_FPRGM);
modifyreg32(AT32_FLASH_CTRL2, 0, FLASH_CTRL_FPRGM);
for (addr += AT32_FLASH_BASE; count; count -= 2, hword++, addr += 2)
{
/* Write half-word and wait to complete */
putreg16(*hword, addr);
#ifdef AT32_FLASH_BANK2_START
flash_sts = (addr < AT32_FLASH_BANK2_START *AT32_FLASH_PAGESIZE) ? \
AT32_FLASH_STS : AT32_FLASH_STS2;
#else
flash_sts = AT32_FLASH_STS;
#endif
while (getreg32(flash_sts) & FLASH_STS_OBF)
{
at32_waste();
}
/* Verify */
if (getreg32(flash_sts) & FLASH_STS_PRGMERR)
{
modifyreg32(AT32_FLASH_CTRL, FLASH_CTRL_FPRGM, 0);
modifyreg32(AT32_FLASH_CTRL2, FLASH_CTRL_FPRGM, 0);
nxmutex_unlock(&g_lock);
return -EROFS;
}
if (getreg16(addr) != *hword)
{
modifyreg32(AT32_FLASH_CTRL, FLASH_CTRL_FPRGM, 0);
modifyreg32(AT32_FLASH_CTRL2, FLASH_CTRL_FPRGM, 0);
nxmutex_unlock(&g_lock);
return -EIO;
}
}
modifyreg32(AT32_FLASH_CTRL, FLASH_CTRL_FPRGM, 0);
modifyreg32(AT32_FLASH_CTRL2, FLASH_CTRL_FPRGM, 0);
#if defined(CONFIG_AT32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
data_cache_enable();
#endif
nxmutex_unlock(&g_lock);
return written;
}
uint8_t up_progmem_erasestate(void)
{
return FLASH_ERASEDVALUE;
}
#endif /* defined(CONFIG_AT32_AT32F43XX) */

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/****************************************************************************
* arch/arm/src/at32/at32f43xxx_alarm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_AT32F43XXX_ALARM_H
#define __ARCH_ARM_SRC_AT32_AT32F43XXX_ALARM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <time.h>
#ifdef CONFIG_RTC_ALARM
/****************************************************************************
* Public Types
****************************************************************************/
typedef void (*alm_callback_t)(void *arg, unsigned int alarmid);
/* These features are known to map to AT32 RTC from at32F4xx and appear to
* map to beyond at32F4xx and at32L0xx there appears to be a small variant
* with at32F3 but do not map to at32F0, F1, F2
*/
enum alm_id_e
{
RTC_ALARMA = 0, /* RTC ALARM A */
RTC_ALARMB, /* RTC ALARM B */
RTC_ALARM_LAST
};
/* Structure used to pass parameters to set an alarm */
struct alm_setalarm_s
{
int as_id; /* enum alm_id_e */
struct tm as_time; /* Alarm expiration time */
alm_callback_t as_cb; /* Callback (if non-NULL) */
void *as_arg; /* Argument for callback */
};
/* Structure used to pass parameters to query an alarm */
struct alm_rdalarm_s
{
int ar_id; /* enum alm_id_e */
struct rtc_time *ar_time; /* Argument for storing ALARM RTC time */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: at32_rtc_setalarm
*
* Description:
* Set an alarm to an absolute time using associated hardware.
*
* Input Parameters:
* alminfo - Information about the alarm configuration.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int at32_rtc_setalarm(struct alm_setalarm_s *alminfo);
/****************************************************************************
* Name: at32_rtc_rdalarm
*
* Description:
* Query an alarm configured in hardware.
*
* Input Parameters:
* alminfo - Information about the alarm configuration.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int at32_rtc_rdalarm(struct alm_rdalarm_s *alminfo);
/****************************************************************************
* Name: at32_rtc_cancelalarm
*
* Description:
* Cancel an alarm.
*
* Input Parameters:
* alarmid - Identifies the alarm to be cancelled
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int at32_rtc_cancelalarm(enum alm_id_e alarmid);
#endif /* CONFIG_RTC_ALARM */
#endif /* __ARCH_ARM_SRC_AT32_AT32F40XXX_ALARM_H */

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/****************************************************************************
* arch/arm/src/at32/at32f43xxx_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip.h"
#include "at32_pwr.h"
#include "hardware/at32f43xxx_rcc.h"
#include "itm_syslog.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway. Normally this is very fast, but I have seen at least one
* board that required this long, long timeout for the HSE to be ready.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* Same for HSI */
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
/* HSE divisor to yield ~1MHz RTC clock */
#define HSE_DIVISOR (AT32_HSE_FREQUENCY + 500000) / 1000000
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rcc_reset
*
* Description:
* Reset the RCC clock configuration to the default reset state
*
****************************************************************************/
static inline void rcc_reset(void)
{
uint32_t regval;
/* enable pwc clock */
regval = getreg32(AT32_CRM_APB1EN);
regval |= CRM_APB1EN_PWCEN;
putreg32(regval, AT32_CRM_APB1EN);
/* set ldo output 1.3V */
regval = getreg32(AT32_PWC_LDOOV);
regval &= ~PWC_LDOOV_SEL_MASK;
regval |= PWC_LDOOV_1V3;
putreg32(regval, AT32_PWC_LDOOV);
/* set flash div 3 */
regval = getreg32(AT32_FLASH_DIVR);
regval &= ~FLASH_DIVR_FDIV_MASK;
regval |= FLASH_DIVR_FDIV_3;
putreg32(regval, AT32_FLASH_DIVR);
#if (AT32_SYSCLK_FREQUENCY <= 192000000ul)
/* enable Flash non-zero wait area boost */
regval = getreg32(AT32_FLASH_PSR);
regval |= FLASH_PSR_NZW_BST;
putreg32(regval, AT32_FLASH_PSR);
#endif
/* Flash continue read enable */
regval = getreg32(AT32_FLASH_CONTR);
regval |= FLASH_CONTR_EN;
putreg32(regval, AT32_FLASH_CONTR);
/* reset the crm clock configuration to the default reset state */
/* set hicken bit */
regval = getreg32(AT32_CRM_CTRL);
regval |= CRM_CTRL_HICKEN;
putreg32(regval, AT32_CRM_CTRL);
/* Wait High speed internal crystal stable */
while ((getreg32(AT32_CRM_CTRL) & CRM_CTRL_HICKSTBL) != \
CRM_CTRL_HICKSTBL);
/* reset hexten, hextbyps, cfden and pllen bits */
regval = getreg32(AT32_CRM_CTRL);
regval &= ~CRM_CTRL_HEXTEN;
regval &= ~CRM_CTRL_HEXTBYPS;
regval &= ~CRM_CTRL_CFDEN;
regval &= ~CRM_CTRL_PLLEN;
putreg32(regval, AT32_CRM_CTRL);
/* reset cfg register, include sclk switch, ahbdiv,
* apb1div, apb2div, adcdiv, clkout bits
*/
regval = 0;
putreg32(regval, AT32_CRM_CFG);
/* reset pllms pllns pllfr pllrcs bits */
regval = 0x00033002ul;
putreg32(regval, AT32_CRM_PLL_CFG);
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
regval = 0;
putreg32(regval, AT32_CRM_MISC1);
/* disable all interrupts enable and clear pending bits */
regval = 0x009f0000ul;
putreg32(regval, AT32_CRM_CLKINT);
}
/****************************************************************************
* Name: rcc_enableahb1
*
* Description:
* Enable selected AHB1 peripherals
*
****************************************************************************/
static inline void rcc_enableahb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB1ENR register to enabled the
* selected AHB1 peripherals.
*/
regval = getreg32(AT32_CRM_AHBEN1);
/* Enable GPIOA, GPIOB, .... GPIOH */
#if AT32_NGPIO_PORTS > 0
regval |= (CRM_AHBEN1_GPIOAEN
#if AT32_NGPIO_PORTS > 1
| CRM_AHBEN1_GPIOBEN
#endif
#if AT32_NGPIO_PORTS > 2
| CRM_AHBEN1_GPIOCEN
#endif
#if AT32_NGPIO_PORTS > 3
| CRM_AHBEN1_GPIODEN
#endif
#if AT32_NGPIO_PORTS > 4
| CRM_AHBEN1_GPIOEEN
#endif
#if AT32_NGPIO_PORTS > 5
| CRM_AHBEN1_GPIOFEN
#endif
#if AT32_NGPIO_PORTS > 6
| CRM_AHBEN1_GPIOGEN
#endif
#if AT32_NGPIO_PORTS > 7
| CRM_AHBEN1_GPIOHEN
#endif
);
#endif
#ifdef CONFIG_AT32_CRC
/* CRC clock enable */
regval |= CRM_AHBEN1_CRCEN;
#endif
#ifdef CONFIG_AT32_EDMA
/* EDMA clock enable */
regval |= CRM_AHBEN1_EDMAEN;
#endif
#ifdef CONFIG_AT32_DMA1
/* DMA 1 clock enable */
regval |= CRM_AHBEN1_DMA1EN;
#endif
#ifdef CONFIG_AT32_DMA2
/* DMA 2 clock enable */
regval |= CRM_AHBEN1_DMA2EN;
#endif
#ifdef CONFIG_AT32_ETHMAC
/* Ethernet MAC clocking */
regval |= (CRM_AHBEN1_EMACEN | CRM_AHBEN1_EMACTXEN
| CRM_AHBEN1_EMACRXEN);
#ifdef CONFIG_AT32_ETH_PTP
/* Precision Time Protocol (PTP) */
regval |= CRM_AHBEN1_EMACPTPEN;
#endif
#endif
#ifdef CONFIG_AT32_OTGFS2
regval |= CRM_AHBEN1_OTGFS2EN;
#endif
putreg32(regval, AT32_CRM_AHBEN1); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableahb2
*
* Description:
* Enable selected AHB2 peripherals
*
****************************************************************************/
static inline void rcc_enableahb2(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB2ENR register to enabled the
* selected AHB2 peripherals.
*/
regval = getreg32(AT32_CRM_AHBEN2);
#ifdef CONFIG_AT32_DVP
/* Camera interface enable */
regval |= CRM_AHBEN2_DVPEN;
#endif
#ifdef CONFIG_AT32_OTGFS
/* USBOTG FS1 modules clock enable */
regval |= CRM_AHBEN2_OTGFS1EN;
#endif
#ifdef CONFIG_AT32_SDIO
/* SDIO1 clock enable */
regval |= CRM_AHBEN2_SDIO1EN;
#endif
putreg32(regval, AT32_CRM_AHBEN2); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableahb3
*
* Description:
* Enable selected AHB3 peripherals
*
****************************************************************************/
static inline void rcc_enableahb3(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB3ENR register to enabled the
* selected AHB3 peripherals.
*/
regval = getreg32(AT32_CRM_AHBEN3);
#ifdef CONFIG_AT32_XMC
/* Flexible static memory controller module clock enable */
regval |= CRM_AHBEN3_XMCEN;
#endif
#ifdef CONFIG_AT32_QSPI1
/* QSPI1 clock enable */
regval |= CRM_AHBEN3_QSPI1EN;
#endif
#ifdef CONFIG_AT32_QSPI2
/* QSPI2 clock enable */
regval |= CRM_AHBEN3_QSPI2EN;
#endif
#ifdef CONFIG_AT32_SDIO2
/* SDIO2 clock enable */
regval |= CRM_AHBEN3_SDIO2EN;
#endif
putreg32(regval, AT32_CRM_AHBEN3); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableapb1
*
* Description:
* Enable selected APB1 peripherals
*
****************************************************************************/
static inline void rcc_enableapb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB1ENR register to enabled the
* selected APB1 peripherals.
*/
regval = getreg32(AT32_CRM_APB1EN);
#ifdef CONFIG_AT32_TRM2
/* TRM2 clock enable */
regval |= CRM_APB1EN_TMR2EN;
#endif
#ifdef CONFIG_AT32_TRM3
/* TRM3 clock enable */
regval |= CRM_APB1EN_TMR3EN;
#endif
#ifdef CONFIG_AT32_TRM4
/* TRM4 clock enable */
regval |= CRM_APB1EN_TMR4EN;
#endif
#ifdef CONFIG_AT32_TRM5
/* TRM5 clock enable */
regval |= CRM_APB1EN_TMR5EN;
#endif
#ifdef CONFIG_AT32_TRM6
/* TRM6 clock enable */
regval |= CRM_APB1EN_TMR6EN;
#endif
#ifdef CONFIG_AT32_TRM7
/* TRM7 clock enable */
regval |= CRM_APB1EN_TMR7EN;
#endif
#ifdef CONFIG_AT32_TRM12
/* TRM12 clock enable */
regval |= CRM_APB1EN_TMR12EN;
#endif
#ifdef CONFIG_AT32_TRM13
/* TRM13 clock enable */
regval |= CRM_APB1EN_TMR13EN;
#endif
#ifdef CONFIG_AT32_TRM14
/* TRM14 clock enable */
regval |= CRM_APB1EN_TMR14EN;
#endif
#ifdef CONFIG_AT32_WWDT
/* Window watchdog clock enable */
regval |= CRM_APB1EN_WWDTEN;
#endif
#ifdef CONFIG_AT32_SPI2
/* SPI2 clock enable */
regval |= CRM_APB1EN_SPI2EN;
#endif
#ifdef CONFIG_AT32_SPI3
/* SPI3 clock enable */
regval |= CRM_APB1EN_SPI3EN;
#endif
#ifdef CONFIG_AT32_USART2
/* USART 2 clock enable */
regval |= CRM_APB1EN_USART2EN;
#endif
#ifdef CONFIG_AT32_USART3
/* USART3 clock enable */
regval |= CRM_APB1EN_USART3EN;
#endif
#ifdef CONFIG_AT32_UART4
/* UART4 clock enable */
regval |= CRM_APB1EN_UART4EN;
#endif
#ifdef CONFIG_AT32_UART5
/* UART5 clock enable */
regval |= CRM_APB1EN_UART5EN;
#endif
#ifdef CONFIG_AT32_I2C1
/* I2C1 clock enable */
regval |= CRM_APB1EN_I2C1EN;
#endif
#ifdef CONFIG_AT32_I2C2
/* I2C2 clock enable */
regval |= CRM_APB1EN_I2C2EN;
#endif
#ifdef CONFIG_AT32_I2C3
/* I2C3 clock enable */
regval |= CRM_APB1EN_I2C3EN;
#endif
#ifdef CONFIG_AT32_CAN1
/* CAN 1 clock enable */
regval |= CRM_APB1EN_CAN1EN;
#endif
#ifdef CONFIG_AT32_CAN2
/* CAN2 clock enable */
regval |= CRM_APB1EN_CAN2EN ;
#endif
/* Power interface clock enable. The PWR block is always enabled so that
* we can set the internal voltage regulator for maximum performance.
*/
regval |= CRM_APB1EN_PWCEN;
#if defined (CONFIG_AT32_DAC)
/* DAC interface clock enable */
regval |= CRM_APB1EN_DACEN;
#endif
#ifdef CONFIG_AT32_UART7
/* UART7 clock enable */
regval |= CRM_APB1EN_UART7EN;
#endif
#ifdef CONFIG_AT32_UART8
/* UART8 clock enable */
regval |= CRM_APB1EN_UART8EN;
#endif
putreg32(regval, AT32_CRM_APB1EN); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableapb2
*
* Description:
* Enable selected APB2 peripherals
*
****************************************************************************/
static inline void rcc_enableapb2(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB2ENR register to enabled the
* selected APB2 peripherals.
*/
regval = getreg32(AT32_CRM_APB2EN);
#ifdef CONFIG_AT32_TRM1
/* TRM1 clock enable */
regval |= CRM_APB2EN_TMR1EN;
#endif
#ifdef CONFIG_AT32_TRM8
/* TRM8 clock enable */
regval |= CRM_APB2EN_TMR8EN;
#endif
#ifdef CONFIG_AT32_USART1
/* USART1 clock enable */
regval |= CRM_APB2EN_USART1EN;
#endif
#ifdef CONFIG_AT32_USART6
/* USART6 clock enable */
regval |= CRM_APB2EN_USART6EN;
#endif
#ifdef CONFIG_AT32_ADC1
/* ADC1 clock enable */
regval |= CRM_APB2EN_ADC1EN;
#endif
#ifdef CONFIG_AT32_ADC2
/* ADC2 clock enable */
regval |= CRM_APB2EN_ADC2EN;
#endif
#ifdef CONFIG_AT32_ADC3
/* ADC3 clock enable */
regval |= CRM_APB2EN_ADC3EN;
#endif
#ifdef CONFIG_AT32_SPI1
/* SPI1 clock enable */
regval |= CRM_APB2EN_SPI1EN;
#endif
#ifdef CONFIG_AT32_SPI4
/* SPI4 clock enable */
regval |= CRM_APB2EN_SPI4EN;
#endif
#ifdef CONFIG_AT32_SYSCFG
/* System configuration controller clock enable */
regval |= CRM_APB2EN_SCFGEN;
#endif
#ifdef CONFIG_AT32_TRM9
/* TRM9 clock enable */
regval |= CRM_APB2EN_TMR9EN;
#endif
#ifdef CONFIG_AT32_TRM10
/* TRM10 clock enable */
regval |= CRM_APB2EN_TMR10EN;
#endif
#ifdef CONFIG_AT32_TRM11
/* TRM11 clock enable */
regval |= CRM_APB2EN_TMR11EN;
#endif
#ifdef CONFIG_AT32_TRM20
/* TRM20 clock enable */
regval |= CRM_APB2EN_TMR20EN;
#endif
#ifdef CONFIG_AT32_ACC
/* ACC clock enable */
regval |= CRM_APB2EN_ACCEN;
#endif
putreg32(regval, AT32_CRM_APB2EN); /* Enable peripherals */
}
/****************************************************************************
* Name: at32_stdclockconfig
*
* Description:
* Called to change to new clock based on settings in board.h
*
* NOTE: This logic would need to be extended if you need to select low-
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG
static void at32_stdclockconfig(void)
{
uint32_t regval;
/* config external crystal as clock source */
regval = getreg32(AT32_CRM_CTRL);
regval &= ~CRM_CTRL_HICKEN;
regval |= CRM_CTRL_HEXTEN;
putreg32(regval, AT32_CRM_CTRL);
/* Wait High speed external crystal stable */
while ((getreg32(AT32_CRM_CTRL) & CRM_CTRL_HEXTSTBL) != \
CRM_CTRL_HEXTSTBL);
regval = getreg32(AT32_CRM_CFG);
regval &= ~CRM_CFG_SCLKSEL_MASK;
regval |= CRM_CFG_SEL_HEXT;
putreg32(regval, AT32_CRM_CFG);
/* config PLL */
regval = getreg32(AT32_CRM_PLL_CFG);
regval |= CRM_PLL_CFG_PLLRCS;
regval &= ~CRM_PLL_CFG_PLL_MS_MASK;
regval |= AT32_PLLCFG_PLLM;
regval &= ~CRM_PLL_CFG_PLL_NS_MASK;
regval |= AT32_PLLCFG_PLLN;
regval &= ~CRM_PLL_CFG_PLL_FR_MASK;
regval |= AT32_PLLCFG_PLLP;
putreg32(regval, AT32_CRM_PLL_CFG);
/* enable pll */
regval = getreg32(AT32_CRM_CTRL);
regval |= CRM_CTRL_PLLEN;
putreg32(regval, AT32_CRM_CTRL);
while ((getreg32(AT32_CRM_CTRL) & CRM_CTRL_PLLSTBL) != \
CRM_CTRL_PLLSTBL);
regval = getreg32(AT32_CRM_CFG);
regval &= ~CRM_CFG_AHBDIV_MASK;
regval |= CRM_CFG_AHBDIV_NONE; /* ahb div 1 */
regval &= ~CRM_CFG_APB1DIV_MASK;
regval |= CRM_CFG_APB1DIV_2; /* apb1 div 2 */
regval &= ~CRM_CFG_APB2DIV_MASK;
regval |= CRM_CFG_APB2DIV_2; /* apb2 div 2 */
putreg32(regval, AT32_CRM_CFG);
/* entry step mode */
regval = getreg32(AT32_CRM_MISC2);
regval &= ~CRM_MISC2_AUTO_STEP_EN_MASK;
regval |= CRM_MISC2_AUTO_STEP_EN_ENABLE;
putreg32(regval, AT32_CRM_MISC2);
/* config pll as system clock */
regval = getreg32(AT32_CRM_CFG);
regval &= ~CRM_CFG_SCLKSEL_MASK;
regval |= CRM_CFG_SEL_PLL;
putreg32(regval, AT32_CRM_CFG);
while ((getreg32(AT32_CRM_CFG) & CRM_CFG_SCLKSTSL_MASK) != \
CRM_CFG_STS_PLL);
/* exit step mode */
regval = getreg32(AT32_CRM_MISC2);
regval &= ~CRM_MISC2_AUTO_STEP_EN_MASK;
regval |= CRM_MISC2_AUTO_STEP_EN_DISABLE;
putreg32(regval, AT32_CRM_MISC2);
#if defined(CONFIG_AT32_OTGFS) || defined(CONFIG_AT32_OTGFS2)
/* set usbfs clock use pll */
regval = getreg32(AT32_CRM_MISC1);
regval &= ~CRM_MISC1_HICK_TO_USB;
putreg32(regval, AT32_CRM_MISC1);
/* usbfs clock div */
regval = getreg32(AT32_CRM_MISC2);
regval &= ~CRM_MISC2_USBDIV_MASK;
regval |= USB_CONFIG_USBDIV;
putreg32(regval, AT32_CRM_MISC2);
#endif
}
#endif
/****************************************************************************
* Name: efm32_itm_syslog
*
* Description:
* Enable Serial wire output pin, configure debug clocking, and enable
* ITM syslog support.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_ITMSYSLOG
static inline void rcc_itm_syslog(void)
{
uint32_t regval;
regval = getreg32(AT32_DEBUG_CTRL);
regval &= ~DEBUG_CTRL_SLEEP_DEBUG;
putreg32(regval, AT32_DEBUG_CTRL);
}
#else
# define rcc_itm_syslog()
#endif
/****************************************************************************
* Name: rcc_enableperiphals
****************************************************************************/
static inline void rcc_enableperipherals(void)
{
rcc_enableahb1();
rcc_enableahb2();
rcc_enableahb3();
rcc_enableapb1();
rcc_enableapb2();
rcc_itm_syslog();
}
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/at32/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_CHIP_H
#define __ARCH_ARM_SRC_AT32_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the chip capabilities file */
#include <arch/at32/chip.h>
/* Include the chip interrupt definition file */
#include <arch/at32/irq.h>
/* Include the chip memory map */
#include "hardware/at32_memorymap.h"
/* Include the chip pinmap */
#include "hardware/at32_pinmap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition AT32_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/at32/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS AT32_IRQ_NEXTINT
#endif /* __ARCH_ARM_SRC_AT32_CHIP_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ADC_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_AT32_HAVE_IP_ADC_V1) && \
defined(CONFIG_AT32_HAVE_IP_ADC_V2)
# error Only one AT32 ADC IP version must be selected
#endif
#include "at32_adc_v1.h"
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ADC_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_adc_v1.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ADC_V1_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ADC_V1_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* This is implementation for AT32 ADC IPv1 - F1, F2, F37x, F4, F7.
* NOTE: L1 use modified IPv1 (look at chip/at32_adc_v1l1.h).
*/
#define HAVE_IP_ADC_V1
#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */
#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */
#undef HAVE_ADC_POWERDOWN /* No ADC power down */
/* F1 and F37x have basic version of ADC hardware
* - no common ADC registers
* - ADCs are not coupled in single ADC block (no common ADC base address)
* - no configurable resolution
* - no overrun
* - ...
*/
#if defined(CONFIG_AT32_HAVE_IP_ADC_V1_BASIC)
# define HAVE_BASIC_ADC
#else
# undef HAVE_BASIC_ADC
#endif
/* VBAT channel support only if no basic ADC */
#ifndef HAVE_BASIC_ADC
# define HAVE_ADC_VBAT
#else
# undef HAVE_ADC_VBAT
#endif
/* Base addresses ***********************************************************/
/* For the basic ADC IPv1,
* the ADCx_BASE definitions are defined in chip/at32xxx_memorymap.h files
*/
#ifndef HAVE_BASIC_ADC
# define AT32_ADC1_OFFSET 0x0000
# define AT32_ADC2_OFFSET 0x0100
# define AT32_ADC3_OFFSET 0x0200
# define AT32_ADC_CMN_OFFSET 0x0300
# define AT32_ADC1_BASE (AT32_ADC1_OFFSET + AT32_ADC_BASE) /* ADC1 ADC */
# define AT32_ADC2_BASE (AT32_ADC2_OFFSET + AT32_ADC_BASE) /* ADC2 ADC */
# define AT32_ADC3_BASE (AT32_ADC3_OFFSET + AT32_ADC_BASE) /* ADC3 ADC */
# define AT32_ADCCMN_BASE (AT32_ADC_CMN_OFFSET + AT32_ADC_BASE) /* ADC1, ADC2, ADC3 common */
#endif
/* Register Offsets *********************************************************/
#define AT32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
#define AT32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
#define AT32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
#define AT32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
#define AT32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
#define AT32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
#define AT32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
#define AT32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
#define AT32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
#define AT32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
#define AT32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
#define AT32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
#define AT32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
#define AT32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
#define AT32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
#define AT32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
#define AT32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
#define AT32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
#define AT32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
#define AT32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
#ifndef HAVE_BASIC_ADC
# define AT32_ADC_CSR_OFFSET 0x0000 /* Common status register */
# define AT32_ADC_CCR_OFFSET 0x0004 /* Common control register */
# define AT32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
#endif
/* Register Addresses *******************************************************/
#if AT32_NADC > 0
# define AT32_ADC1_SR (AT32_ADC1_BASE + AT32_ADC_SR_OFFSET)
# define AT32_ADC1_CR1 (AT32_ADC1_BASE + AT32_ADC_CR1_OFFSET)
# define AT32_ADC1_CR2 (AT32_ADC1_BASE + AT32_ADC_CR2_OFFSET)
# define AT32_ADC1_SMPR1 (AT32_ADC1_BASE + AT32_ADC_SMPR1_OFFSET)
# define AT32_ADC1_SMPR2 (AT32_ADC1_BASE + AT32_ADC_SMPR2_OFFSET)
# define AT32_ADC1_JOFR1 (AT32_ADC1_BASE + AT32_ADC_JOFR1_OFFSET)
# define AT32_ADC1_JOFR2 (AT32_ADC1_BASE + AT32_ADC_JOFR2_OFFSET)
# define AT32_ADC1_JOFR3 (AT32_ADC1_BASE + AT32_ADC_JOFR3_OFFSET)
# define AT32_ADC1_JOFR4 (AT32_ADC1_BASE + AT32_ADC_JOFR4_OFFSET)
# define AT32_ADC1_HTR (AT32_ADC1_BASE + AT32_ADC_HTR_OFFSET)
# define AT32_ADC1_LTR (AT32_ADC1_BASE + AT32_ADC_LTR_OFFSET)
# define AT32_ADC1_SQR1 (AT32_ADC1_BASE + AT32_ADC_SQR1_OFFSET)
# define AT32_ADC1_SQR2 (AT32_ADC1_BASE + AT32_ADC_SQR2_OFFSET)
# define AT32_ADC1_SQR3 (AT32_ADC1_BASE + AT32_ADC_SQR3_OFFSET)
# define AT32_ADC1_JSQR (AT32_ADC1_BASE + AT32_ADC_JSQR_OFFSET)
# define AT32_ADC1_JDR1 (AT32_ADC1_BASE + AT32_ADC_JDR1_OFFSET)
# define AT32_ADC1_JDR2 (AT32_ADC1_BASE + AT32_ADC_JDR2_OFFSET)
# define AT32_ADC1_JDR3 (AT32_ADC1_BASE + AT32_ADC_JDR3_OFFSET)
# define AT32_ADC1_JDR4 (AT32_ADC1_BASE + AT32_ADC_JDR4_OFFSET)
# define AT32_ADC1_DR (AT32_ADC1_BASE + AT32_ADC_DR_OFFSET)
#endif
#if AT32_NADC > 1
# define AT32_ADC2_SR (AT32_ADC2_BASE + AT32_ADC_SR_OFFSET)
# define AT32_ADC2_CR1 (AT32_ADC2_BASE + AT32_ADC_CR1_OFFSET)
# define AT32_ADC2_CR2 (AT32_ADC2_BASE + AT32_ADC_CR2_OFFSET)
# define AT32_ADC2_SMPR1 (AT32_ADC2_BASE + AT32_ADC_SMPR1_OFFSET)
# define AT32_ADC2_SMPR2 (AT32_ADC2_BASE + AT32_ADC_SMPR2_OFFSET)
# define AT32_ADC2_JOFR1 (AT32_ADC2_BASE + AT32_ADC_JOFR1_OFFSET)
# define AT32_ADC2_JOFR2 (AT32_ADC2_BASE + AT32_ADC_JOFR2_OFFSET)
# define AT32_ADC2_JOFR3 (AT32_ADC2_BASE + AT32_ADC_JOFR3_OFFSET)
# define AT32_ADC2_JOFR4 (AT32_ADC2_BASE + AT32_ADC_JOFR4_OFFSET)
# define AT32_ADC2_HTR (AT32_ADC2_BASE + AT32_ADC_HTR_OFFSET)
# define AT32_ADC2_LTR (AT32_ADC2_BASE + AT32_ADC_LTR_OFFSET)
# define AT32_ADC2_SQR1 (AT32_ADC2_BASE + AT32_ADC_SQR1_OFFSET)
# define AT32_ADC2_SQR2 (AT32_ADC2_BASE + AT32_ADC_SQR2_OFFSET)
# define AT32_ADC2_SQR3 (AT32_ADC2_BASE + AT32_ADC_SQR3_OFFSET)
# define AT32_ADC2_JSQR (AT32_ADC2_BASE + AT32_ADC_JSQR_OFFSET)
# define AT32_ADC2_JDR1 (AT32_ADC2_BASE + AT32_ADC_JDR1_OFFSET)
# define AT32_ADC2_JDR2 (AT32_ADC2_BASE + AT32_ADC_JDR2_OFFSET)
# define AT32_ADC2_JDR3 (AT32_ADC2_BASE + AT32_ADC_JDR3_OFFSET)
# define AT32_ADC2_JDR4 (AT32_ADC2_BASE + AT32_ADC_JDR4_OFFSET)
# define AT32_ADC2_DR (AT32_ADC2_BASE + AT32_ADC_DR_OFFSET)
#endif
#if AT32_NADC > 2
# define AT32_ADC3_SR (AT32_ADC3_BASE + AT32_ADC_SR_OFFSET)
# define AT32_ADC3_CR1 (AT32_ADC3_BASE + AT32_ADC_CR1_OFFSET)
# define AT32_ADC3_CR2 (AT32_ADC3_BASE + AT32_ADC_CR2_OFFSET)
# define AT32_ADC3_SMPR1 (AT32_ADC3_BASE + AT32_ADC_SMPR1_OFFSET)
# define AT32_ADC3_SMPR2 (AT32_ADC3_BASE + AT32_ADC_SMPR2_OFFSET)
# define AT32_ADC3_JOFR1 (AT32_ADC3_BASE + AT32_ADC_JOFR1_OFFSET)
# define AT32_ADC3_JOFR2 (AT32_ADC3_BASE + AT32_ADC_JOFR2_OFFSET)
# define AT32_ADC3_JOFR3 (AT32_ADC3_BASE + AT32_ADC_JOFR3_OFFSET)
# define AT32_ADC3_JOFR4 (AT32_ADC3_BASE + AT32_ADC_JOFR4_OFFSET)
# define AT32_ADC3_HTR (AT32_ADC3_BASE + AT32_ADC_HTR_OFFSET)
# define AT32_ADC3_LTR (AT32_ADC3_BASE + AT32_ADC_LTR_OFFSET)
# define AT32_ADC3_SQR1 (AT32_ADC3_BASE + AT32_ADC_SQR1_OFFSET)
# define AT32_ADC3_SQR2 (AT32_ADC3_BASE + AT32_ADC_SQR2_OFFSET)
# define AT32_ADC3_SQR3 (AT32_ADC3_BASE + AT32_ADC_SQR3_OFFSET)
# define AT32_ADC3_JSQR (AT32_ADC3_BASE + AT32_ADC_JSQR_OFFSET)
# define AT32_ADC3_JDR1 (AT32_ADC3_BASE + AT32_ADC_JDR1_OFFSET)
# define AT32_ADC3_JDR2 (AT32_ADC3_BASE + AT32_ADC_JDR2_OFFSET)
# define AT32_ADC3_JDR3 (AT32_ADC3_BASE + AT32_ADC_JDR3_OFFSET)
# define AT32_ADC3_JDR4 (AT32_ADC3_BASE + AT32_ADC_JDR4_OFFSET)
# define AT32_ADC3_DR (AT32_ADC3_BASE + AT32_ADC_DR_OFFSET)
#endif
#ifndef HAVE_BASIC_ADC
# define AT32_ADC_CSR (AT32_ADCCMN_BASE + AT32_ADC_CSR_OFFSET)
# define AT32_ADC_CCR (AT32_ADCCMN_BASE + AT32_ADC_CCR_OFFSET)
# define AT32_ADC_CDR (AT32_ADCCMN_BASE + AT32_ADC_CDR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* ADC status register */
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
#define ADC_SR_RDY (1 << 6) /* Bit 6 : ADC ready to conversion flag */
/* ADC control register 1 */
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
#ifndef HAVE_BASIC_ADC
# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles */
# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles */
# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */
# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */
# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
# define ADC_CR1_RESERVED (0xfb3f0000)
#endif
/* ADC control register 2 */
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */
#define ADC_CR2_ADABRT (1 << 4) /* Bit 4: ADC conversion abort */
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
/* Bits 12-15: Reserved */
#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 23/16-19: External event select for injected group */
#define ADC_CR2_JEXTSEL_MASK (0x8F << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */
# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */
# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */
# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */
# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */
# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */
# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */
# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */
# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */
# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
# define ADC_CR2_JEXTSEL_T20TRGO (0x80 << ADC_CR2_JEXTSEL_SHIFT) /* 10000000: Timer 20 TRGO1 event */
# define ADC_CR2_JEXTSEL_T20TRGO2 (0x81 << ADC_CR2_JEXTSEL_SHIFT) /* 10000001: Timer 20 TRGO2 event */
# define ADC_CR2_JEXTSEL_T20CC4 (0x82 << ADC_CR2_JEXTSEL_SHIFT) /* 10000002: Timer 20 CC4 event */
# define ADC_CR2_JEXTSEL_T1TRGO2 (0x83 << ADC_CR2_JEXTSEL_SHIFT) /* 10000011: Timer 1 TRGO2 event */
# define ADC_CR2_JEXTSEL_T8TRGO (0x84 << ADC_CR2_JEXTSEL_SHIFT) /* 10000100: Timer 8 TRGO event */
# define ADC_CR2_JEXTSEL_T8TRGO2 (0x85 << ADC_CR2_JEXTSEL_SHIFT) /* 10000101: Timer 8 TRGO2 event */
# define ADC_CR2_JEXTSEL_T3CC3 (0x86 << ADC_CR2_JEXTSEL_SHIFT) /* 10000110: Timer 3 CC3 event */
# define ADC_CR2_JEXTSEL_T3TRGO (0x87 << ADC_CR2_JEXTSEL_SHIFT) /* 10000111: Timer 3 TRGO event */
# define ADC_CR2_JEXTSEL_T3CC1 (0x88 << ADC_CR2_JEXTSEL_SHIFT) /* 10001000: Timer 3 CC1 event */
# define ADC_CR2_JEXTSEL_T6TRGO (0x89 << ADC_CR2_JEXTSEL_SHIFT) /* 10001001: Timer 6 TRGO event */
# define ADC_CR2_JEXTSEL_T4CC4 (0x8a << ADC_CR2_JEXTSEL_SHIFT) /* 10001010: Timer 4 CC4 event */
# define ADC_CR2_JEXTSEL_T1CC3 (0x8b << ADC_CR2_JEXTSEL_SHIFT) /* 10001011: Timer 1 CC3 event */
# define ADC_CR2_JEXTSEL_T20CC2 (0x8c << ADC_CR2_JEXTSEL_SHIFT) /* 10001100: Timer 20 CC2 event */
# define ADC_CR2_JEXTSEL_T7TRGO (0x8e << ADC_CR2_JEXTSEL_SHIFT) /* 10001110: Timer 7 TRGO event */
#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
/* Bit 23: Reserved, must be kept at reset value. */
#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 31/24-27: External Event Select for regular group */
#define ADC_CR2_EXTSEL_MASK (0x8F << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */
# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */
# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */
# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */
# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */
# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */
# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */
# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
# define ADC_CR2_EXTSEL_T20TRGO (0x80 << ADC_CR2_EXTSEL_SHIFT) /* 10000000: Timer 20 TRGO event */
# define ADC_CR2_EXTSEL_T20TRGO1 (0x81 << ADC_CR2_EXTSEL_SHIFT) /* 10000001: Timer 20 TRGO 2 event */
# define ADC_CR2_EXTSEL_T20CC1 (0x82 << ADC_CR2_EXTSEL_SHIFT) /* 10000010: Timer 20 CC1 event */
# define ADC_CR2_EXTSEL_T20CC2 (0x83 << ADC_CR2_EXTSEL_SHIFT) /* 10000011: Timer 20 CC2 event */
# define ADC_CR2_EXTSEL_T20CC3 (0x84 << ADC_CR2_EXTSEL_SHIFT) /* 10000100: Timer 20 CC3 event */
# define ADC_CR2_EXTSEL_T8TRGO1 (0x85 << ADC_CR2_EXTSEL_SHIFT) /* 10000101: Timer 20 TRGO 2 event */
# define ADC_CR2_EXTSEL_T1TRGO1 (0x86 << ADC_CR2_EXTSEL_SHIFT) /* 10000110: Timer 1 TRGO 2 event */
# define ADC_CR2_EXTSEL_T4TRGO (0x87 << ADC_CR2_EXTSEL_SHIFT) /* 10000111: Timer 4 TRGO event */
# define ADC_CR2_EXTSEL_T6TRGO (0x88 << ADC_CR2_EXTSEL_SHIFT) /* 10001000: Timer 6 TRGO event */
# define ADC_CR2_EXTSEL_T3CC4 (0x89 << ADC_CR2_EXTSEL_SHIFT) /* 10001001: Timer 3 CC4 event */
# define ADC_CR2_EXTSEL_T4CC1 (0x8a << ADC_CR2_EXTSEL_SHIFT) /* 10001010: Timer 3 CC4 event */
# define ADC_CR2_EXTSEL_T1TRGO (0x8b << ADC_CR2_EXTSEL_SHIFT) /* 10001011: Timer 1 TRGO event */
# define ADC_CR2_EXTSEL_T2CC1 (0x8c << ADC_CR2_EXTSEL_SHIFT) /* 10001100: Timer 2 CC1 event */
# define ADC_CR2_EXTSEL_T7TRGO (0x8e << ADC_CR2_EXTSEL_SHIFT) /* 10001110: Timer 7 TRGO event */
# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
# define ADC_CR2_RESERVED (0x8080f0fc)
/* ADC sample time register 1 */
#define ADC_SMPR_2p5 0 /* 000: 2.5 cycles */
#define ADC_SMPR_6p5 1 /* 001: 6.5 cycles */
#define ADC_SMPR_12p5 2 /* 010: 12.5 cycles */
#define ADC_SMPR_24p5 3 /* 011: 24.5 cycles */
#define ADC_SMPR_47p5 4 /* 100: 47.5 cycles */
#define ADC_SMPR_92p5 5 /* 101: 92.5 cycles */
#define ADC_SMPR_247p5 6 /* 110: 247.5 cycles */
#define ADC_SMPR_640p5 7 /* 111: 640.5 cycles */
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
/* ADC sample time register 2 */
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
/* ADC injected channel data offset register 1-4 */
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
/* ADC watchdog high threshold register */
#define ADC_HTR_SHIFT (0) /* Bits 15-0: Analog watchdog high threshold */
#define ADC_HTR_MASK (0xffff << ADC_HTR_SHIFT)
/* ADC watchdog low threshold register */
#define ADC_LTR_SHIFT (0) /* Bits 15-0: Analog watchdog low threshold */
#define ADC_LTR_MASK (0xffff << ADC_LTR_SHIFT)
/* ADC regular sequence register 1 */
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
#define ADC_SQR1_RESERVED (0xff000000)
#define ADC_SQR1_FIRST (13)
#define ADC_SQR1_LAST (16)
#define ADC_SQR1_SQ_OFFSET (0)
/* ADC regular sequence register 2 */
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
#define ADC_SQR2_RESERVED (0xc0000000)
#define ADC_SQR2_FIRST (7)
#define ADC_SQR2_LAST (12)
#define ADC_SQR2_SQ_OFFSET (0)
/* ADC regular sequence register 3 */
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
#define ADC_SQR3_RESERVED (0xc0000000)
#define ADC_SQR3_FIRST (1)
#define ADC_SQR3_LAST (6)
#define ADC_SQR3_SQ_OFFSET (0)
/* Offset between SQ bits */
#define ADC_SQ_OFFSET (5)
/* ADC injected sequence register */
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
#define ADC_JSQR_JSQ_SHIFT (5) /* Shift between JSQx bits */
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */
/* ADC injected data register 1-4 */
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
/* ADC regular data register */
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
/* Common status register */
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
#define ADC_CSR_RDY1 (1 << 6) /* Bit 6: ADC ready to conversion flag of ADC1 */
/* Bit 7: Reserved, must be kept at reset value. */
#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
#define ADC_CSR_RDY2 (1 << 14) /* Bit 14: ADC ready to conversion flag of ADC2 */
/* Bit 15: Reserved, must be kept at reset value. */
#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
#define ADC_CSR_RDY3 (1 << 22) /* Bit 22: ADC ready to conversion flag of ADC3 */
/* Bit 31: Reserved, must be kept at reset value. */
/* Common control register */
#define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
#define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
/* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
/* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
/* Bits 5-7: Reserved,
* must be kept at reset value.
*/
#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
/* Bit 12 Reserved,
* must be kept at reset value.
*/
#define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
#define ADC_CCR_DMA_SHIFT (14) /* Bits 28/14-15: Direct memory access mode for multi ADC mode */
#define ADC_CCR_DMA_MASK (0x4003 << ADC_CCR_DMA_SHIFT)
# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
# define ADC_CCR_DMA_MODE4 (0x4000 << ADC_CCR_DMA_SHIFT) /* 0x4000: DMA mode 4 enabled */
# define ADC_CCR_DMA_MODE5 (0x4001 << ADC_CCR_DMA_SHIFT) /* 0x4001: DMA mode 5 enabled */
#define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-19: ADC prescaler */
#define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 0000: HCLK divided by 2 */
# define ADC_CCR_ADCPRE_DIV3 (1 << ADC_CCR_ADCPRE_SHIFT) /* 0001: HCLK divided by 3 */
# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* 0010: HCLK divided by 4 */
# define ADC_CCR_ADCPRE_DIV5 (3 << ADC_CCR_ADCPRE_SHIFT) /* 0011: HCLK divided by 5 */
# define ADC_CCR_ADCPRE_DIV6 (4 << ADC_CCR_ADCPRE_SHIFT) /* 0100: HCLK divided by 6 */
# define ADC_CCR_ADCPRE_DIV7 (5 << ADC_CCR_ADCPRE_SHIFT) /* 0101: HCLK divided by 7 */
# define ADC_CCR_ADCPRE_DIV8 (6 << ADC_CCR_ADCPRE_SHIFT) /* 0110: HCLK divided by 8 */
# define ADC_CCR_ADCPRE_DIV9 (7 << ADC_CCR_ADCPRE_SHIFT) /* 0111: HCLK divided by 9 */
# define ADC_CCR_ADCPRE_DIV10 (8 << ADC_CCR_ADCPRE_SHIFT) /* 1000: HCLK divided by 10 */
# define ADC_CCR_ADCPRE_DIV11 (9 << ADC_CCR_ADCPRE_SHIFT) /* 1001: HCLK divided by 11 */
# define ADC_CCR_ADCPRE_DIV12 (10 << ADC_CCR_ADCPRE_SHIFT) /* 1010: HCLK divided by 12 */
# define ADC_CCR_ADCPRE_DIV13 (11 << ADC_CCR_ADCPRE_SHIFT) /* 1011: HCLK divided by 13 */
# define ADC_CCR_ADCPRE_DIV14 (12 << ADC_CCR_ADCPRE_SHIFT) /* 1100: HCLK divided by 14 */
# define ADC_CCR_ADCPRE_DIV15 (13 << ADC_CCR_ADCPRE_SHIFT) /* 1101: HCLK divided by 15 */
# define ADC_CCR_ADCPRE_DIV16 (14 << ADC_CCR_ADCPRE_SHIFT) /* 1110: HCLK divided by 16 */
# define ADC_CCR_ADCPRE_DIV17 (15 << ADC_CCR_ADCPRE_SHIFT) /* 1111: HCLK divided by 17 */
/* Bits 18-21: Reserved,
* must be kept at reset value.
*/
#define ADC_CCR_VBATEN (1 << 22) /* Bit 22: VBAT enable */
#define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
/* Bits 24-31 Reserved, must be kept at reset value. */
/* Over sample register */
#define ADC_OVSP_OOSEN (1 << 0) /* Bit 0: Ordinary oversampling enable */
#define ADC_OVSP_POSEN (1 << 1) /* Bit 1: Preempted oversampling enable */
#define ADC_OVSP_OSRSEL_SHIFT (2) /* Oversampling ratio select */
#define ADC_OVSP_OSRSEL_MASK (7 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_2 (0 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_4 (1 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_8 (2 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_16 (3 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_32 (4 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_64 (5 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_128 (6 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSRSEL_256 (7 << ADC_OVSP_OSRSEL_SHIFT)
#define ADC_OVSP_OSSSEL_SHIFT (5) /* Oversampling shift select */
#define ADC_OVSP_OSSSEL_MASK (15 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_1 (0 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_2 (1 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_3 (2 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_4 (3 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_5 (4 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_6 (5 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_7 (6 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OSSSEL_8 (7 << ADC_OVSP_OSSSEL_SHIFT)
#define ADC_OVSP_OOSTREN (9) /* Ordinary oversampling trigger mode enable */
#define ADC_OVSP_OOSRSEL (10) /* Ordinary oversampling restart mode select */
/* Calibration value register */
#define ADC_CALVAL_SHIFT (0)
#define ADC_CALVAL_MASK (0x7f << ADC_CALVAL_SHIFT)
# define ADC_CALVAL(n) (n << ADC_CALVAL_SHIFT)
/* Data register for dual and triple modes
* (32-bit data with no named fields)
*/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ADC_V1_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_can.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_CAN_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_CAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* 3 TX mailboxes */
#define CAN_TXMBOX1 0
#define CAN_TXMBOX2 1
#define CAN_TXMBOX3 2
/* 2 RX mailboxes */
#define CAN_RXMBOX1 0
#define CAN_RXMBOX2 1
/* Number of filters depends on silicon */
#if defined(CONFIG_AT32_AT32F43XX)
# define CAN_NFILTERS 28
#else
# define CAN_NFILTERS 14
#endif
/* Register Offsets *********************************************************/
/* CAN control and status registers */
#define AT32_CAN_MCTRL_OFFSET (0x000) /* CAN master control register */
#define AT32_CAN_MSTS_OFFSET (0x004) /* CAN master status register */
#define AT32_CAN_TSTS_OFFSET (0x008) /* CAN transmit status register */
#define AT32_CAN_RF_OFFSET(x) (0x00c+((x)<<2))
#define AT32_CAN_RF0_OFFSET (0x00c) /* CAN receive FIFO 0 register */
#define AT32_CAN_RF1_OFFSET (0x010) /* CAN receive FIFO 1 register */
#define AT32_CAN_INTEN_OFFSET (0x014) /* CAN interrupt enable register */
#define AT32_CAN_ESTS_OFFSET (0x018) /* CAN error status register */
#define AT32_CAN_BTMG_OFFSET (0x01c) /* CAN bit timing register */
/* CAN mailbox registers (3 TX and 2 RX) */
#define AT32_CAN_TMI_OFFSET(x) (0x180+((x)<<4))
#define AT32_CAN_TMI0_FFSET (0x180) /* TX mailbox identifier register 0 */
#define AT32_CAN_TMI1_FFSET (0x190) /* TX mailbox identifier register 1 */
#define AT32_CAN_TMI2_FFSET (0x1a0) /* TX mailbox identifier register 2 */
#define AT32_CAN_TMC_OFFSET(x) (0x184+((x)<<4))
#define AT32_CAN_TMC0_OFFSET (0x184) /* Mailbox data length control and time stamp register 0 */
#define AT32_CAN_TMC1_OFFSET (0x194) /* Mailbox data length control and time stamp register 1 */
#define AT32_CAN_TMC2_OFFSET (0x1a4) /* Mailbox data length control and time stamp register 2 */
#define AT32_CAN_TMDTL_OFFSET(x) (0x188+((x)<<4))
#define AT32_CAN_TMDTL0_OFFSET (0x188) /* Mailbox data low register 0 */
#define AT32_CAN_TMDTL1_OFFSET (0x198) /* Mailbox data low register 1 */
#define AT32_CAN_TMDTL2_OFFSET (0x1a8) /* Mailbox data low register 2 */
#define AT32_CAN_TMDTH_OFFSET(x) (0x18c+((x)<<4))
#define AT32_CAN_TMDTH0_OFFSET (0x18c) /* Mailbox data high register 0 */
#define AT32_CAN_TMDTH1_OFFSET (0x19c) /* Mailbox data high register 1 */
#define AT32_CAN_TMDTH2_OFFSET (0x1ac) /* Mailbox data high register 2 */
#define AT32_CAN_RFI_OFFSET(x) (0x1b0+((x)<<4))
#define AT32_CAN_RFI0_OFFSET (0x1b0) /* Rx FIFO mailbox identifier register 0 */
#define AT32_CAN_RFI1_OFFSET (0x1c0) /* Rx FIFO mailbox identifier register 1 */
#define AT32_CAN_RFC_OFFSET(x) (0x1b4+((x)<<4))
#define AT32_CAN_RFC0_OFFSET (0x1b4) /* Rx FIFO mailbox data length control and time stamp register 0 */
#define AT32_CAN_RFC1_OFFSET (0x1c4) /* Rx FIFO mailbox data length control and time stamp register 1 */
#define AT32_CAN_RFDTL_OFFSET(x) (0x1b8+((x)<<4))
#define AT32_CAN_RFDTL0_OFFSET (0x1b8) /* Receive FIFO mailbox data low register 0 */
#define AT32_CAN_RFDTL1_OFFSET (0x1c8) /* Receive FIFO mailbox data low register 1 */
#define AT32_CAN_RFDTH_OFFSET(x) (0x1bc+((x)<<4))
#define AT32_CAN_RFDTH0_OFFSET (0x1bc) /* Receive FIFO mailbox data high register 0 */
#define AT32_CAN_RFDTH1_OFFSET (0x1cc) /* Receive FIFO mailbox data high register 1 */
/* CAN filter registers */
#define AT32_CAN_FCTRL_OFFSET (0x200) /* CAN filter master register */
#define AT32_CAN_FMCFG_OFFSET (0x204) /* CAN filter mode register */
#define AT32_CAN_FSCFG_OFFSET (0x20c) /* CAN filter scale register */
#define AT32_CAN_FRF_OFFSET (0x214) /* CAN filter FIFO assignment register */
#define AT32_CAN_FACFG_OFFSET (0x21c) /* CAN filter activation register */
/* There are 14 or 28 filter banks (depending) on the device.
* Each filter bank is composed of two 32-bit registers, CAN_FiR:
* FB0F1 Offset 0x240
* FB0F2 Offset 0x244
* FB1F1 Offset 0x248
* FB1F2 Offset 0x24c
* ...
*/
#define AT32_CAN_FBF_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2))
/* Register Addresses *******************************************************/
#if AT32_NCAN > 0
# define AT32_CAN1_MCTRL (AT32_CAN1_BASE+AT32_CAN_MCTRL_OFFSET)
# define AT32_CAN1_MSTS (AT32_CAN1_BASE+AT32_CAN_MSTS_OFFSET)
# define AT32_CAN1_TSTS (AT32_CAN1_BASE+AT32_CAN_TSTS_OFFSET)
# define AT32_CAN1_RF0 (AT32_CAN1_BASE+AT32_CAN_RF0_OFFSET)
# define AT32_CAN1_RF1 (AT32_CAN1_BASE+AT32_CAN_RF1_OFFSET)
# define AT32_CAN1_INTEN (AT32_CAN1_BASE+AT32_CAN_INTEN_OFFSET)
# define AT32_CAN1_ESTS (AT32_CAN1_BASE+AT32_CAN_ESTS_OFFSET)
# define AT32_CAN1_BTMG (AT32_CAN1_BASE+AT32_CAN_BTMG_OFFSET)
# define AT32_CAN1_TMI(x) (AT32_CAN1_BASE+AT32_CAN_TMI_OFFSET(x))
# define AT32_CAN1_TMI0 (AT32_CAN1_BASE+AT32_CAN_TMI0_FFSET)
# define AT32_CAN1_TMI1 (AT32_CAN1_BASE+AT32_CAN_TMI1_FFSET)
# define AT32_CAN1_TMI2 (AT32_CAN1_BASE+AT32_CAN_TMI2_FFSET)
# define AT32_CAN1_TMC(x) (AT32_CAN1_BASE+AT32_CAN_TMC_OFFSET(x))
# define AT32_CAN1_TMC0 (AT32_CAN1_BASE+AT32_CAN_TMC0_OFFSET)
# define AT32_CAN1_TMC1 (AT32_CAN1_BASE+AT32_CAN_TMC1_OFFSET)
# define AT32_CAN1_TMC2 (AT32_CAN1_BASE+AT32_CAN_TMC2_OFFSET)
# define AT32_CAN1_TMDTL(x) (AT32_CAN1_BASE+AT32_CAN_TMDTL_OFFSET(x))
# define AT32_CAN1_TMDTL0 (AT32_CAN1_BASE+AT32_CAN_TMDTL0_OFFSET)
# define AT32_CAN1_TMDTL1 (AT32_CAN1_BASE+AT32_CAN_TMDTL1_OFFSET)
# define AT32_CAN1_TMDTL2 (AT32_CAN1_BASE+AT32_CAN_TMDTL2_OFFSET)
# define AT32_CAN1_TMDTH(x) (AT32_CAN1_BASE+AT32_CAN_TMDTH_OFFSET(x))
# define AT32_CAN1_TMDTH0 (AT32_CAN1_BASE+AT32_CAN_TMDTH0_OFFSET)
# define AT32_CAN1_TMDTH1 (AT32_CAN1_BASE+AT32_CAN_TMDTH1_OFFSET)
# define AT32_CAN1_TMDTH2 (AT32_CAN1_BASE+AT32_CAN_TMDTH2_OFFSET)
# define AT32_CAN1_RFI(x) (AT32_CAN1_BASE+AT32_CAN_RFI_OFFSET(x))
# define AT32_CAN1_RFI0 (AT32_CAN1_BASE+AT32_CAN_RFI0_OFFSET)
# define AT32_CAN1_RFI1 (AT32_CAN1_BASE+AT32_CAN_RFI1_OFFSET)
# define AT32_CAN1_RFC(x) (AT32_CAN1_BASE+AT32_CAN_RFC_OFFSET(x))
# define AT32_CAN1_RFC0 (AT32_CAN1_BASE+AT32_CAN_RFC0_OFFSET)
# define AT32_CAN1_RFC1 (AT32_CAN1_BASE+AT32_CAN_RFC1_OFFSET)
# define AT32_CAN1_RFDTL(x) (AT32_CAN1_BASE+AT32_CAN_RFDTL_OFFSET(x))
# define AT32_CAN1_RFDTL0 (AT32_CAN1_BASE+AT32_CAN_RFDTL0_OFFSET)
# define AT32_CAN1_RFDTL1 (AT32_CAN1_BASE+AT32_CAN_RFDTL1_OFFSET)
# define AT32_CAN1_RFDTH(x) (AT32_CAN1_BASE+AT32_CAN_RFDTH_OFFSET(x))
# define AT32_CAN1_RFDTH0 (AT32_CAN1_BASE+AT32_CAN_RFDTH0_OFFSET)
# define AT32_CAN1_RFDTH1 (AT32_CAN1_BASE+AT32_CAN_RFDTH1_OFFSET)
# define AT32_CAN1_FCTRL (AT32_CAN1_BASE+AT32_CAN_FCTRL_OFFSET)
# define AT32_CAN1_FMCFG (AT32_CAN1_BASE+AT32_CAN_FMCFG_OFFSET)
# define AT32_CAN1_FSCFG (AT32_CAN1_BASE+AT32_CAN_FSCFG_OFFSET)
# define AT32_CAN1_FRF (AT32_CAN1_BASE+AT32_CAN_FRF_OFFSET)
# define AT32_CAN1_FACFG (AT32_CAN1_BASE+AT32_CAN_FACFG_OFFSET)
# define AT32_CAN1_FIR(b,i) (AT32_CAN1_BASE+AT32_CAN_FIR_OFFSET(b,i))
#endif
#if AT32_NCAN > 1
# define AT32_CAN2_MCTRL (AT32_CAN2_BASE+AT32_CAN_MCTRL_OFFSET)
# define AT32_CAN2_MSTS (AT32_CAN2_BASE+AT32_CAN_MSTS_OFFSET)
# define AT32_CAN2_TSTS (AT32_CAN2_BASE+AT32_CAN_TSTS_OFFSET)
# define AT32_CAN2_RF0 (AT32_CAN2_BASE+AT32_CAN_RF0_OFFSET)
# define AT32_CAN2_RF1 (AT32_CAN2_BASE+AT32_CAN_RF1_OFFSET)
# define AT32_CAN2_INTEN (AT32_CAN2_BASE+AT32_CAN_INTEN_OFFSET)
# define AT32_CAN2_ESTS (AT32_CAN2_BASE+AT32_CAN_ESTS_OFFSET)
# define AT32_CAN2_BTMG (AT32_CAN2_BASE+AT32_CAN_BTMG_OFFSET)
# define AT32_CAN2_TMI(x) (AT32_CAN2_BASE+AT32_CAN_TMI_OFFSET(x))
# define AT32_CAN2_TMI0 (AT32_CAN2_BASE+AT32_CAN_TMI0_FFSET)
# define AT32_CAN2_TMI1 (AT32_CAN2_BASE+AT32_CAN_TMI1_FFSET)
# define AT32_CAN2_TMI2 (AT32_CAN2_BASE+AT32_CAN_TMI2_FFSET)
# define AT32_CAN2_TMC(x) (AT32_CAN2_BASE+AT32_CAN_TMC_OFFSET(x))
# define AT32_CAN2_TMC0 (AT32_CAN2_BASE+AT32_CAN_TMC0_OFFSET)
# define AT32_CAN2_TMC1 (AT32_CAN2_BASE+AT32_CAN_TMC1_OFFSET)
# define AT32_CAN2_TMC2 (AT32_CAN2_BASE+AT32_CAN_TMC2_OFFSET)
# define AT32_CAN2_TMDTL(x) (AT32_CAN2_BASE+AT32_CAN_TMDTL_OFFSET(x))
# define AT32_CAN2_TMDTL0 (AT32_CAN2_BASE+AT32_CAN_TMDTL0_OFFSET)
# define AT32_CAN2_TMDTL1 (AT32_CAN2_BASE+AT32_CAN_TMDTL1_OFFSET)
# define AT32_CAN2_TMDTL2 (AT32_CAN2_BASE+AT32_CAN_TMDTL2_OFFSET)
# define AT32_CAN2_TMDTH(x) (AT32_CAN2_BASE+AT32_CAN_TMDTH_OFFSET(x))
# define AT32_CAN2_TMDTH0 (AT32_CAN2_BASE+AT32_CAN_TMDTH0_OFFSET)
# define AT32_CAN2_TMDTH1 (AT32_CAN2_BASE+AT32_CAN_TMDTH1_OFFSET)
# define AT32_CAN2_TMDTH2 (AT32_CAN2_BASE+AT32_CAN_TMDTH2_OFFSET)
# define AT32_CAN2_RFI(x) (AT32_CAN2_BASE+AT32_CAN_RFI_OFFSET(x))
# define AT32_CAN2_RFI0 (AT32_CAN2_BASE+AT32_CAN_RFI0_OFFSET)
# define AT32_CAN2_RFI1 (AT32_CAN2_BASE+AT32_CAN_RFI1_OFFSET)
# define AT32_CAN2_RFC(x) (AT32_CAN2_BASE+AT32_CAN_RFC_OFFSET(x))
# define AT32_CAN2_RFC0 (AT32_CAN2_BASE+AT32_CAN_RFC0_OFFSET)
# define AT32_CAN2_RFC1 (AT32_CAN2_BASE+AT32_CAN_RFC1_OFFSET)
# define AT32_CAN2_RFDTL(x) (AT32_CAN2_BASE+AT32_CAN_RFDTL_OFFSET(x))
# define AT32_CAN2_RFDTL0 (AT32_CAN2_BASE+AT32_CAN_RFDTL0_OFFSET)
# define AT32_CAN2_RFDTL1 (AT32_CAN2_BASE+AT32_CAN_RFDTL1_OFFSET)
# define AT32_CAN2_RFDTH(x) (AT32_CAN2_BASE+AT32_CAN_RFDTH_OFFSET(x))
# define AT32_CAN2_RFDTH0 (AT32_CAN2_BASE+AT32_CAN_RFDTH0_OFFSET)
# define AT32_CAN2_RFDTH1 (AT32_CAN2_BASE+AT32_CAN_RFDTH1_OFFSET)
# define AT32_CAN2_FCTRL (AT32_CAN2_BASE+AT32_CAN_FCTRL_OFFSET)
# define AT32_CAN2_FMCFG (AT32_CAN2_BASE+AT32_CAN_FMCFG_OFFSET)
# define AT32_CAN2_FSCFG (AT32_CAN2_BASE+AT32_CAN_FSCFG_OFFSET)
# define AT32_CAN2_FRF (AT32_CAN2_BASE+AT32_CAN_FRF_OFFSET)
# define AT32_CAN2_FACFG (AT32_CAN2_BASE+AT32_CAN_FACFG_OFFSET)
# define AT32_CAN2_FIR(b,i) (AT32_CAN2_BASE+AT32_CAN_FIR_OFFSET(b,i))
#endif
/* Register Bitfield Definitions ********************************************/
/* CAN master control register */
#define CAN_MCTRL_FZEN (1 << 0) /* Freeze mode enable */
#define CAN_MCTRL_DZEN (1 << 1) /* Doze mode enable */
#define CAN_MCTRL_MMSSR (1 << 2) /* Multiple message sending sequence rule */
#define CAN_MCTRL_MDRSEL (1 << 3) /* Message discarding rule select when overflow */
#define CAN_MCTRL_PRSFEN (1 << 4) /* Prohibit retransmission when sending fails enable */
#define CAN_MCTRL_AEDEN (1 << 5) /* Automatic exit doze mode enable */
#define CAN_MCTRL_AEBOEN (1 << 6) /* Automatic exit bus-off enable */
#define CAN_MCTRL_TTCEN (1 << 7) /* Time triggered communication mode enable */
#define CAN_MCTRL_SPRST (1 << 15) /* Software partial reset */
#define CAN_MCTRL_PTD (1 << 16) /* Prohibit trans when debug */
/* CAN master status register */
#define CAN_MSTS_FZC (1 << 0) /* Freeze mode confirm */
#define CAN_MSTS_DZC (1 << 1) /* Doze mode confirm */
#define CAN_MSTS_EOIF (1 << 2) /* Error occur Interrupt flag */
#define CAN_MSTS_QDZIF (1 << 3) /* Quit doze mode interrupt flag */
#define CAN_MSTS_EDZIF (1 << 4) /* Enter doze mode interrupt flag */
#define CAN_MSTS_CUSS (1 << 8) /* Currently sending status */
#define CAN_MSTS_CURS (1 << 9) /* Currently receiving status */
#define CAN_MSTS_LSAMPRX (1 << 10) /* Last sample level of RX pin */
#define CAN_MSTS_REALRX (1 << 11) /* Real time level of RX pin */
/* CAN transmit status register */
#define CAN_TSTS_TM0TCF (1 << 0) /* Transmit mailbox 0 transmission completed flag */
#define CAN_TSTS_TM0TSF (1 << 1) /* Transmit mailbox 0 transmission success flag */
#define CAN_TSTS_TM0ALF (1 << 2) /* Transmit mailbox 0 arbitration lost flag */
#define CAN_TSTS_TM0TEF (1 << 3) /* Transmit mailbox 0 transmission error flag */
#define CAN_TSTS_TM0CT (1 << 7) /* Transmit mailbox 0 cancel transmit */
#define CAN_TSTS_TM1TCF (1 << 8) /* Transmit mailbox 1 transmission completed flag */
#define CAN_TSTS_TM1TSF (1 << 9) /* Transmit mailbox 1 transmission success flag */
#define CAN_TSTS_TM1ALF (1 << 10) /* Transmit mailbox 1 arbitration lost flag */
#define CAN_TSTS_TM1TEF (1 << 11) /* Transmit mailbox 1 transmission error flag */
#define CAN_TSTS_TM1CT (1 << 15) /* Transmit mailbox 1 cancel transmit */
#define CAN_TSTS_TM2TCF (1 << 16) /* transmit mailbox 2 transmission completed flag */
#define CAN_TSTS_TM2TSF (1 << 17) /* Transmit mailbox 2 transmission success flag */
#define CAN_TSTS_TM2ALF (1 << 18) /* Transmit mailbox 2 arbitration lost flag */
#define CAN_TSTS_TM2TEF (1 << 19) /* Transmit mailbox 2 transmission error flag */
#define CAN_TSTS_TM2CT (1 << 23) /* Transmit mailbox 2 cancel transmit */
#define CAN_TSTS_TMNR_SHIFT (24) /* Transmit Mailbox number record */
#define CAN_TSTS_TMNR_MASK (3 << CAN_TSTS_TMNR_SHIFT)
#define CAN_TSTS_TM0EF (1 << 26) /* Transmit mailbox 0 empty flag */
#define CAN_TSTS_TM1EF (1 << 27) /* Transmit mailbox 1 empty flag */
#define CAN_TSTS_TM2EF (1 << 28) /* Transmit mailbox 2 empty flag */
#define CAN_TSTS_TM0LPF (1 << 29) /* Transmit mailbox 0 lowest priority flag */
#define CAN_TSTS_TM1LPF (1 << 30) /* Transmit mailbox 1 lowest priority flag */
#define CAN_TSTS_TM2LPF (1 << 31) /* Transmit mailbox 2 lowest priority flag */
/* CAN receive FIFO 0/1 registers */
#define CAN_RF_RFMN_SHIFT (0) /* Receive FIFO message num */
#define CAN_RF_RFMN_MASK (3 << CAN_RF_RFMN_SHIFT)
#define CAN_RF_RFFF (1 << 3) /* Receive FIFO full flag */
#define CAN_RF_RFOF (1 << 4) /* Receive FIFO overflow flag */
#define CAN_RF_RFR (1 << 5) /* Receive FIFO release */
/* CAN interrupt enable register */
#define CAN_INTEN_TCIEN (1 << 0) /* Transmit mailbox empty interrupt enable */
#define CAN_INTEN_RF0MIEN (1 << 1) /* FIFO 0 receive message interrupt enable */
#define CAN_INTEN_RF0FIEN (1 << 2) /* Receive FIFO 0 full interrupt enable */
#define CAN_INTEN_RF0OIEN (1 << 3) /* Receive FIFO 0 overflow interrupt enable */
#define CAN_INTEN_RF1MIEN (1 << 4) /* FIFO 1 receive message interrupt enable */
#define CAN_INTEN_RF1FIEN (1 << 5) /* Receive FIFO 1 full interrupt enable */
#define CAN_INTEN_RF1OIEN (1 << 6) /* Receive FIFO 1 overflow interrupt enable */
#define CAN_INTEN_EAIEN (1 << 8) /* Error active interrupt enable */
#define CAN_INTEN_EPIEN (1 << 9) /* Error passive interrupt enable */
#define CAN_INTEN_BOIEN (1 << 10) /* Bus-off interrupt enable */
#define CAN_INTEN_ETRIEN (1 << 11) /* Error type record interrupt enable */
#define CAN_INTEN_EOIEN (1 << 15) /* Error occur interrupt enable */
#define CAN_INTEN_QDZIEN (1 << 16) /* Quit doze mode interrupt enable */
#define CAN_INTEN_EDZIEN (1 << 17) /* Enter doze mode interrupt enable */
/* CAN error status register */
#define CAN_ESTS_EAF (1 << 0) /* Error active flag */
#define CAN_ESTS_EPF (1 << 0) /* Error passive flag */
#define CAN_ESTS_BOF (1 << 0) /* Bus-off flag */
#define CAN_ESTS_ETR_SHIFT (4) /* Error type record */
#define CAN_ESTS_ETR_MASK (7 << CAN_ESTS_ETR_SHIFT)
#define CAN_ESTS_ETR_NONE (0 << CAN_ESTS_ETR_SHIFT) /* No error */
#define CAN_ESTS_ETR_STUFF (1 << CAN_ESTS_ETR_SHIFT) /* Stuff error */
#define CAN_ESTS_ETR_FORM (2 << CAN_ESTS_ETR_SHIFT) /* Form error */
#define CAN_ESTS_ETR_ACK (3 << CAN_ESTS_ETR_SHIFT) /* Ack error */
#define CAN_ESTS_ETR_BREC (4 << CAN_ESTS_ETR_SHIFT) /* Bit recessive error */
#define CAN_ESTS_ETR_BDOM (5 << CAN_ESTS_ETR_SHIFT) /* Bit domainant error */
#define CAN_ESTS_ETR_CRC (6 << CAN_ESTS_ETR_SHIFT) /* CRC error */
#define CAN_ESTS_ETR_SOFT (7 << CAN_ESTS_ETR_SHIFT) /* Set by soft */
#define CAN_ESTS_TEC_SHIFT (16) /* Transmit error counter */
#define CAN_ESTS_TEC_MASK (0xff << CAN_ESTS_TEC_SHIFT)
#define CAN_ESTS_REC_SHIFT (24) /* Receive error counter */
#define CAN_ESTS_REC_MASK (0xff << CAN_ESTS_REC_SHIFT)
/* CAN bit timing register */
#define CAN_BTMG_BRDIV_SHIFT (0) /* Baud rate division */
#define CAN_BTMG_BRDIV_MASK (0xfff << CAN_BTMG_BRDIV_SHIFT)
#define CAN_BTMG_BTS1_SHIFT (16) /* Bit time segment 1 */
#define CAN_BTMG_BTS1_MASK (0xf << CAN_BTMG_BTS1_SHIFT)
#define CAN_BTMG_BTS2_SHIFT (20) /* Bit time segment 2 */
#define CAN_BTMG_BTS2_MASK (7 << CAN_BTMG_BTS2_SHIFT)
#define CAN_BTMG_RSAW_SHIFT (24) /* Resynchronization adjust width */
#define CAN_BTMG_RSAW_MASK (3 << CAN_BTMG_RSAW_SHIFT)
#define CAN_BTMG_LBEN (1 << 30) /* Loop back mode */
#define CAN_BTMG_LOEN (1 << 31) /* Listen-Only mode */
#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */
#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */
#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */
/* TX mailbox identifier register */
#define CAN_TMI_TMSR (1 << 0) /* transmit mailbox send request */
#define CAN_TMI_TMFRSEL (1 << 1) /* Transmit mailbox frame type select */
#define CAN_TMI_TMIDSEL (1 << 2) /* Transmit mailbox identifier type select */
#define CAN_TMI_TMEID_SHIFT (3) /* Ttransmit mailbox extended identifier */
#define CAN_TMI_TMEID_MASK (0x1fffffff << CAN_TMI_TMEID_SHIFT)
#define CAN_TMI_TMSID_TMEID_SHIFT (21) /* Transmit mailbox standard identifier or extended identifier high bytes */
#define CAN_TMI_TMSID_TMEID_MASK (0x7ff << CAN_TMI_TMSID_TMEID_SHIFT)
/* Mailbox data length control and time stamp register */
#define CAN_TMC_TMDTBL_SHIFT (0) /* Transmit mailbox data byte length */
#define CAN_TMC_TMDTBL_MASK (15 << CAN_TMC_TMDTBL_SHIFT)
#define CAN_TMC_TMTSTEN (1 << 8) /* Transmit mailbox time stamp transmit enable */
#define CAN_TMC_TMTS_SHIFT (16) /* Transmit mailbox time stamp */
#define CAN_TMC_TMTS_MASK (0xffff << CAN_TMC_TMTS_SHIFT)
/* Mailbox data low register */
#define CAN_TMDTL_TMDT0_SHIFT (0) /* Transmit mailbox data byte 0 */
#define CAN_TMDTL_TMDT0_MASK (0xff << CAN_TMDTL_TMDT0_SHIFT)
#define CAN_TMDTL_TMDT1_SHIFT (8) /* Transmit mailbox data byte 1 */
#define CAN_TMDTL_TMDT1_MASK (0xff << CAN_TMDTL_TMDT1_SHIFT)
#define CAN_TMDTL_TMDT2_SHIFT (16) /* Transmit mailbox data byte 2 */
#define CAN_TMDTL_TMDT2_MASK (0xff << CAN_TMDTL_TMDT2_SHIFT)
#define CAN_TMDTL_TMDT3_SHIFT (24) /* Transmit mailbox data byte 3 */
#define CAN_TMDTL_TMDT3_MASK (0xff << CAN_TMDTL_TMDT3_SHIFT)
/* Mailbox data high register */
#define CAN_TMDTH_TMDT4_SHIFT (0) /* Transmit mailbox data byte 4 */
#define CAN_TMDTH_TMDT4_MASK (0xff << CAN_TMDTH_TMDT4_SHIFT)
#define CAN_TMDTH_TMDT5_SHIFT (8) /* Transmit mailbox data byte 5 */
#define CAN_TMDTH_TMDT5_MASK (0xff << CAN_TMDTH_TMDT5_SHIFT)
#define CAN_TMDTH_TMDT6_SHIFT (16) /* Transmit mailbox data byte 6 */
#define CAN_TMDTH_TMDT6_MASK (0xff << CAN_TMDTH_TMDT6_SHIFT)
#define CAN_TMDTH_TMDT7_SHIFT (24) /* Transmit mailbox data byte 7 */
#define CAN_TMDTH_TMDT7_MASK (0xff << CAN_TMDTH_TMDT7_SHIFT)
/* Rx FIFO mailbox identifier register */
#define CAN_RDI_RFFRI (1 << 1) /* Receive FIFO frame type indication */
#define CAN_RDI_RFIDI (1 << 2) /* Receive FIFO identifier type indication */
#define CAN_RDI_RFEID_SHIFT (3) /* Receive FIFO extended identifier */
#define CAN_RDI_RFEID_MASK (0x3fff << CAN_RDI_RFEID_SHIFT)
#define CAN_RDI_RFSID_RFEID_SHIFT (21) /* Receive FIFO standard identifier or receive FIFO extended identifier */
#define CAN_RDI_RFSID_RFEID_MASK (0x7ff << CAN_RDI_RFSID_RFEID_SHIFT)
/* Receive FIFO mailbox data length control and time stamp register */
#define CAN_RFC_RFDTL_SHIFT (0) /* Receive FIFO data length */
#define CAN_RFC_RFDTL_MASK (15 << CAN_RFC_RFDTL_SHIFT)
#define CAN_RFC_RFFMN_SHIFT (8) /* Receive FIFO filter match number */
#define CAN_RFC_RFFMN_MASK (0xff << CAN_RFC_RFFMN_SHIFT)
#define CAN_RFC_RFTS_SHIFT (16) /* Receive FIFO time stamp */
#define CAN_RFC_RFTS_MASK (0xffff << CAN_RFC_RFTS_SHIFT)
/* Receive FIFO mailbox data low register */
#define CAN_RFDTL_RFDT0_SHIFT (0) /* Receive FIFO data byte 0 */
#define CAN_RFDTL_RFDT0_MASK (0xff << CAN_RFDTL_RFDT0_SHIFT)
#define CAN_RFDTL_RFDT1_SHIFT (8) /* Receive FIFO data byte 1 */
#define CAN_RFDTL_RFDT1_MASK (0xff << CAN_RFDTL_RFDT1_SHIFT)
#define CAN_RFDTL_RFDT2_SHIFT (16) /* Receive FIFO data byte 2 */
#define CAN_RFDTL_RFDT2_MASK (0xff << CAN_RFDTL_RFDT2_SHIFT)
#define CAN_RFDTL_RFDT3_SHIFT (24) /* Receive FIFO data byte 3 */
#define CAN_RFDTL_RFDT3_MASK (0xff << CAN_RFDTL_RFDT3_SHIFT)
/* Receive FIFO mailbox data high register */
#define CAN_RFDTH_RFDT4_SHIFT (0) /* Receive FIFO data byte 4 */
#define CAN_RFDTH_RFDT4_MASK (0xff << CAN_RFDTH_RFDT4_SHIFT)
#define CAN_RFDTH_RFDT5_SHIFT (8) /* Receive FIFO data byte 5 */
#define CAN_RFDTH_RFDT5_MASK (0xff << CAN_RFDTH_RFDT5_SHIFT)
#define CAN_RFDTH_RFDT6_SHIFT (16) /* Receive FIFO data byte 6 */
#define CAN_RFDTH_RFDT6_MASK (0xff << CAN_RFDTH_RFDT6_SHIFT)
#define CAN_RFDTH_RFDT7_SHIFT (24) /* Receive FIFO data byte 7 */
#define CAN_RFDTH_RFDT7_MASK (0xff << CAN_RFDTH_RFDT7_SHIFT)
/* CAN filter master register */
#define CAN_FCTRL_FCS (1 << 0) /* Filters configure switch */
/* CAN filter mode register */
#define CAN_FMCFG_FMSEL_SHIFT (0) /* Filter mode select,0:mask 1:list */
#define CAN_FMCFG_FMSEL_MASK (0xfffffff << CAN_FMCFG_FMSEL_SHIFT)
/* CAN filter scale register */
#define CAN_FBWCFG_FBWSEL_SHIFT (0) /* Filter bit width select,0:two 16 bits 1:32bits */
#define CAN_FBWCFG_FBWSEL_MASK (0xfffffff << CAN_FBWCFG_FBWSEL_SHIFT)
/* CAN filter FIFO assignment register */
#define CAN_FRF_FRFSEL_SHIFT (0) /* Filter relation FIFO select,0:FIFO0 1:FIFO1 */
#define CAN_FRF_FRFSEL_MASK (0xfffffff << CAN_FRF_FRFSEL_SHIFT)
/* CAN filter activation register */
#define CAN_FACFG_FAEN_SHIFT (0) /* Filter active enable */
#define CAN_FACFG_FAEN_MASK (0xfffffff << CAN_FACFG_FAEN_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_CAN_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DBGMCU_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Addresses *******************************************************/
#define AT32_DEBUG_IDCODE 0xE0042000
#define AT32_DEBUG_CTRL 0xE0042004
#define AT32_DEBUG_APB1_PAUSE 0xE0042008
#define AT32_DEBUG_APB2_PAUSE 0xE004200C
#define AT32_DEBUG_SER_ID 0xE0042020
/* Register Bitfield Definitions ********************************************/
/* MCU identifier */
#define DEBUG_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
#define DEBUG_IDCODE_DEVID_MASK (0x0fff << DEBUG_IDCODE_DEVID_SHIFT)
#define DEBUG_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
#define DEBUG_IDCODE_REVID_MASK (0xffff << DEBUG_IDCODE_REVID_SHIFT)
/* MCU debug */
#define DEBUG_CTRL_SLEEP_DEBUG (1 << 0) /* Debug sleep mode*/
#define DEBUG_CTRL_DEEPSLEEP_DEBUG (1 << 1) /* Debug deep sleep mode */
#define DEBUG_CTRL_STANDBY_DEBUG (1 << 2) /* Debug standby mode */
/* APB1 pause */
#define DEBUG_APB1_APUSE_TMR2_PAUSE (1 << 0)
#define DEBUG_APB1_APUSE_TMR3_PAUSE (1 << 1)
#define DEBUG_APB1_APUSE_TMR4_PAUSE (1 << 2)
#define DEBUG_APB1_APUSE_TMR5_PAUSE (1 << 3)
#define DEBUG_APB1_APUSE_TMR6_PAUSE (1 << 4)
#define DEBUG_APB1_APUSE_TMR7_PAUSE (1 << 5)
#define DEBUG_APB1_APUSE_TMR12_PAUSE (1 << 6)
#define DEBUG_APB1_APUSE_TMR13_PAUSE (1 << 7)
#define DEBUG_APB1_APUSE_TMR14_PAUSE (1 << 8)
#define DEBUG_APB1_APUSE_ERTC_PAUSE (1 << 10)
#define DEBUG_APB1_APUSE_WWDT_PAUSE (1 << 11)
#define DEBUG_APB1_APUSE_WDT_PAUSE (1 << 12)
#define DEBUG_APB1_APUSE_ERTC_512_PAUSE (1 << 15)
#define DEBUG_APB1_APUSE_I2C1_SMBUS_TIMEOUT (1 << 24)
#define DEBUG_APB1_APUSE_CAN1_PAUSE (1 << 25)
#define DEBUG_APB1_APUSE_CAN2_PAUSE (1 << 26)
#define DEBUG_APB1_APUSE_I2C2_SMBUS_TIMEOUT (1 << 27)
#define DEBUG_APB1_APUSE_I2C3_SMBUS_TIMEOUT (1 << 28)
/* APB2 pause */
#define DEBUG_APB2_APUSE_TMR1_PAUSE (1 << 0)
#define DEBUG_APB2_APUSE_TMR8_PAUSE (1 << 1)
#define DEBUG_APB2_APUSE_TMR20_PAUSE (1 << 6)
#define DEBUG_APB2_APUSE_TMR9_PAUSE (1 << 16)
#define DEBUG_APB2_APUSE_TMR10_PAUSE (1 << 17)
#define DEBUG_APB2_APUSE_TMR11_PAUSE (1 << 18)
/* SER ID */
#define DEBUG_SER_ID_SHIFT (8)
# define DEBUG_SER_ID_F435 (0x0D << DEBUG_SER_ID_SHIFT)
# define DEBUG_SER_ID_F437 (0x0E << DEBUG_SER_ID_SHIFT)
#define DEBUG_REV_ID_SHIFT (0)
# define DEBUG_REV_ID (0 << DEBUG_REV_ID_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DBGMCU_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DMA_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* 2 DMA controllers */
#define DMA1 (0)
#define DMA2 (1)
#define DMA_CHAN1 (0)
#define DMA_CHAN2 (1)
#define DMA_CHAN3 (2)
#define DMA_CHAN4 (3)
#define DMA_CHAN5 (4)
#define DMA_CHAN6 (5)
#define DMA_CHAN7 (6)
#define DMA_CHAN8 (7)
/* Register Offsets *********************************************************/
#define AT32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
#define AT32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
#define AT32_DMACHAN_OFFSET(n) (0x0014*(n))
#define AT32_DMACHAN1_OFFSET 0x0000
#define AT32_DMACHAN2_OFFSET 0x0014
#define AT32_DMACHAN3_OFFSET 0x0028
#define AT32_DMACHAN4_OFFSET 0x003c
#define AT32_DMACHAN5_OFFSET 0x0050
#define AT32_DMACHAN6_OFFSET 0x0064
#define AT32_DMACHAN7_OFFSET 0x0078
#define AT32_DMACHAN8_OFFSET 0x008c
#define AT32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
#define AT32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
#define AT32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
#define AT32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */
#define AT32_DMA_CCR_OFFSET(n) (AT32_DMACHAN_CCR_OFFSET+AT32_DMACHAN_OFFSET(n))
#define AT32_DMA_CNDTR_OFFSET(n) (AT32_DMACHAN_CNDTR_OFFSET+AT32_DMACHAN_OFFSET(n))
#define AT32_DMA_CPAR_OFFSET(n) (AT32_DMACHAN_CPAR_OFFSET+AT32_DMACHAN_OFFSET(n))
#define AT32_DMA_CMAR_OFFSET(n) (AT32_DMACHAN_CMAR_OFFSET+AT32_DMACHAN_OFFSET(n))
#define AT32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
#define AT32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
#define AT32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
#define AT32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
#define AT32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
#define AT32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
#define AT32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
#define AT32_DMA_CCR8_OFFSET 0x0094 /* DMA channel 8 configuration register */
#define AT32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
#define AT32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
#define AT32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
#define AT32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
#define AT32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
#define AT32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
#define AT32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
#define AT32_DMA_CNDTR8_OFFSET 0x0098 /* DMA channel 8 number of data register */
#define AT32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
#define AT32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
#define AT32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
#define AT32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
#define AT32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
#define AT32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
#define AT32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
#define AT32_DMA_CPAR8_OFFSET 0x009c /* DMA channel 8 peripheral address register */
#define AT32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
#define AT32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
#define AT32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
#define AT32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
#define AT32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
#define AT32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
#define AT32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
#define AT32_DMA_CMAR8_OFFSET 0x00a0 /* DMA channel 8 memory address register */
#ifdef DMA_HAVE_CSELR
# define AT32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
#endif
/* Register Addresses *******************************************************/
#define AT32_DMA1_ISRC (AT32_DMA1_BASE+AT32_DMA_ISR_OFFSET)
#define AT32_DMA1_IFCR (AT32_DMA1_BASE+AT32_DMA_IFCR_OFFSET)
#define AT32_DMA1_CCR(n) (AT32_DMA1_BASE+AT32_DMA_CCR_OFFSET(n))
#define AT32_DMA1_CCR1 (AT32_DMA1_BASE+AT32_DMA_CCR1_OFFSET)
#define AT32_DMA1_CCR2 (AT32_DMA1_BASE+AT32_DMA_CCR2_OFFSET)
#define AT32_DMA1_CCR3 (AT32_DMA1_BASE+AT32_DMA_CCR3_OFFSET)
#define AT32_DMA1_CCR4 (AT32_DMA1_BASE+AT32_DMA_CCR4_OFFSET)
#define AT32_DMA1_CCR5 (AT32_DMA1_BASE+AT32_DMA_CCR5_OFFSET)
#define AT32_DMA1_CCR6 (AT32_DMA1_BASE+AT32_DMA_CCR6_OFFSET)
#define AT32_DMA1_CCR7 (AT32_DMA1_BASE+AT32_DMA_CCR7_OFFSET)
#define AT32_DMA1_CNDTR(n) (AT32_DMA1_BASE+AT32_DMA_CNDTR_OFFSET(n))
#define AT32_DMA1_CNDTR1 (AT32_DMA1_BASE+AT32_DMA_CNDTR1_OFFSET)
#define AT32_DMA1_CNDTR2 (AT32_DMA1_BASE+AT32_DMA_CNDTR2_OFFSET)
#define AT32_DMA1_CNDTR3 (AT32_DMA1_BASE+AT32_DMA_CNDTR3_OFFSET)
#define AT32_DMA1_CNDTR4 (AT32_DMA1_BASE+AT32_DMA_CNDTR4_OFFSET)
#define AT32_DMA1_CNDTR5 (AT32_DMA1_BASE+AT32_DMA_CNDTR5_OFFSET)
#define AT32_DMA1_CNDTR6 (AT32_DMA1_BASE+AT32_DMA_CNDTR6_OFFSET)
#define AT32_DMA1_CNDTR7 (AT32_DMA1_BASE+AT32_DMA_CNDTR7_OFFSET)
#define AT32_DMA1_CPAR(n) (AT32_DMA1_BASE+AT32_DMA_CPAR_OFFSET(n))
#define AT32_DMA1_CPAR1 (AT32_DMA1_BASE+AT32_DMA_CPAR1_OFFSET)
#define AT32_DMA1_CPAR2 (AT32_DMA1_BASE+AT32_DMA_CPAR2_OFFSET)
#define AT32_DMA1_CPAR3 (AT32_DMA1_BASE+AT32_DMA_CPAR3_OFFSET)
#define AT32_DMA1_CPAR4 (AT32_DMA1_BASE+AT32_DMA_CPAR4_OFFSET)
#define AT32_DMA1_CPAR5 (AT32_DMA1_BASE+AT32_DMA_CPAR5_OFFSET)
#define AT32_DMA1_CPAR6 (AT32_DMA1_BASE+AT32_DMA_CPAR6_OFFSET)
#define AT32_DMA1_CPAR7 (AT32_DMA1_BASE+AT32_DMA_CPAR7_OFFSET)
#define AT32_DMA1_CMAR(n) (AT32_DMA1_BASE+AT32_DMA_CMAR_OFFSET(n))
#define AT32_DMA1_CMAR1 (AT32_DMA1_BASE+AT32_DMA_CMAR1_OFFSET)
#define AT32_DMA1_CMAR2 (AT32_DMA1_BASE+AT32_DMA_CMAR2_OFFSET)
#define AT32_DMA1_CMAR3 (AT32_DMA1_BASE+AT32_DMA_CMAR3_OFFSET)
#define AT32_DMA1_CMAR4 (AT32_DMA1_BASE+AT32_DMA_CMAR4_OFFSET)
#define AT32_DMA1_CMAR5 (AT32_DMA1_BASE+AT32_DMA_CMAR5_OFFSET)
#define AT32_DMA1_CMAR6 (AT32_DMA1_BASE+AT32_DMA_CMAR6_OFFSET)
#define AT32_DMA1_CMAR7 (AT32_DMA1_BASE+AT32_DMA_CMAR7_OFFSET)
#define AT32_DMA2_ISRC (AT32_DMA2_BASE+AT32_DMA_ISR_OFFSET)
#define AT32_DMA2_IFCR (AT32_DMA2_BASE+AT32_DMA_IFCR_OFFSET)
#define AT32_DMA2_CCR(n) (AT32_DMA2_BASE+AT32_DMA_CCR_OFFSET(n))
#define AT32_DMA2_CCR1 (AT32_DMA2_BASE+AT32_DMA_CCR1_OFFSET)
#define AT32_DMA2_CCR2 (AT32_DMA2_BASE+AT32_DMA_CCR2_OFFSET)
#define AT32_DMA2_CCR3 (AT32_DMA2_BASE+AT32_DMA_CCR3_OFFSET)
#define AT32_DMA2_CCR4 (AT32_DMA2_BASE+AT32_DMA_CCR4_OFFSET)
#define AT32_DMA2_CCR5 (AT32_DMA2_BASE+AT32_DMA_CCR5_OFFSET)
#define AT32_DMA2_CCR6 (AT32_DMA2_BASE+AT32_DMA_CCR6_OFFSET)
#define AT32_DMA2_CCR7 (AT32_DMA2_BASE+AT32_DMA_CCR7_OFFSET)
#define AT32_DMA2_CNDTR(n) (AT32_DMA2_BASE+AT32_DMA_CNDTR_OFFSET(n))
#define AT32_DMA2_CNDTR1 (AT32_DMA2_BASE+AT32_DMA_CNDTR1_OFFSET)
#define AT32_DMA2_CNDTR2 (AT32_DMA2_BASE+AT32_DMA_CNDTR2_OFFSET)
#define AT32_DMA2_CNDTR3 (AT32_DMA2_BASE+AT32_DMA_CNDTR3_OFFSET)
#define AT32_DMA2_CNDTR4 (AT32_DMA2_BASE+AT32_DMA_CNDTR4_OFFSET)
#define AT32_DMA2_CNDTR5 (AT32_DMA2_BASE+AT32_DMA_CNDTR5_OFFSET)
#define AT32_DMA2_CNDTR6 (AT32_DMA2_BASE+AT32_DMA_CNDTR6_OFFSET)
#define AT32_DMA2_CNDTR7 (AT32_DMA2_BASE+AT32_DMA_CNDTR7_OFFSET)
#define AT32_DMA2_CPAR(n) (AT32_DMA2_BASE+AT32_DMA_CPAR_OFFSET(n))
#define AT32_DMA2_CPAR1 (AT32_DMA2_BASE+AT32_DMA_CPAR1_OFFSET)
#define AT32_DMA2_CPAR2 (AT32_DMA2_BASE+AT32_DMA_CPAR2_OFFSET)
#define AT32_DMA2_CPAR3 (AT32_DMA2_BASE+AT32_DMA_CPAR3_OFFSET)
#define AT32_DMA2_CPAR4 (AT32_DMA2_BASE+AT32_DMA_CPAR4_OFFSET)
#define AT32_DMA2_CPAR5 (AT32_DMA2_BASE+AT32_DMA_CPAR5_OFFSET)
#define AT32_DMA2_CPAR6 (AT32_DMA2_BASE+AT32_DMA_CPAR6_OFFSET)
#define AT32_DMA2_CPAR7 (AT32_DMA2_BASE+AT32_DMA_CPAR7_OFFSET)
#define AT32_DMA2_CMAR(n) (AT32_DMA2_BASE+AT32_DMA_CMAR_OFFSET(n))
#define AT32_DMA2_CMAR1 (AT32_DMA2_BASE+AT32_DMA_CMAR1_OFFSET)
#define AT32_DMA2_CMAR2 (AT32_DMA2_BASE+AT32_DMA_CMAR2_OFFSET)
#define AT32_DMA2_CMAR3 (AT32_DMA2_BASE+AT32_DMA_CMAR3_OFFSET)
#define AT32_DMA2_CMAR4 (AT32_DMA2_BASE+AT32_DMA_CMAR4_OFFSET)
#define AT32_DMA2_CMAR5 (AT32_DMA2_BASE+AT32_DMA_CMAR5_OFFSET)
#define AT32_DMA2_CMAR6 (AT32_DMA2_BASE+AT32_DMA_CMAR6_OFFSET)
#define AT32_DMA2_CMAR7 (AT32_DMA2_BASE+AT32_DMA_CMAR7_OFFSET)
/* Register Bitfield Definitions ********************************************/
#define DMA_CHAN_SHIFT(n) ((n) << 2)
#define DMA_CHAN_MASK 0x0f
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
/* DMA interrupt status register */
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
#define DMA_ISR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt status */
#define DMA_ISR_CHAN8_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN8_SHIFT)
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
/* DMA interrupt flag clear register */
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
#define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */
#define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT)
#if defined(CONFIG_AT32_HAVE_DMA1_CHAN8) || defined(CONFIG_AT32_HAVE_DMA2_CHAN678)
# define DMA_IFCR_ALLCHANNELS (0xffffffff)
#else
# define DMA_IFCR_ALLCHANNELS (0x0fffffff)
#endif
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
/* DMA channel configuration register */
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
/* DMA channel number of data register */
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
/* DMA Channel mapping.
* Each DMA channel has a mapping to several possible sources/sinks of data.
* The requests from peripherals assigned to a channel are simply OR'ed
* together before entering the DMA block. This means that onlyone request
* on a given channel can be enabled at once.
*
* Alternative DMA channel selections are provided with a numeric suffix like
* _1, _2, etc. Drivers, however, will use the pin selection without the
* numeric suffix. Additional definitions are required in the board.h file.
*/
#define AT32_DMA1_CHAN1 (0)
#define AT32_DMA1_CHAN2 (1)
#define AT32_DMA1_CHAN3 (2)
#define AT32_DMA1_CHAN4 (3)
#define AT32_DMA1_CHAN5 (4)
#define AT32_DMA1_CHAN6 (5)
#define AT32_DMA1_CHAN7 (6)
#define AT32_DMA2_CHAN1 (7)
#define AT32_DMA2_CHAN2 (8)
#define AT32_DMA2_CHAN3 (9)
#define AT32_DMA2_CHAN4 (10)
#define AT32_DMA2_CHAN5 (11)
#define AT32_DMA2_CHAN6 (12)
#define AT32_DMA2_CHAN7 (13)
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DMA_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_dmamux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DMAMUX_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define DMAMUX1 0
#define DMAMUX2 1
/* Register Offsets *********************************************************/
#define AT32_DMAMUX_CXCR_OFFSET(x) (0x0000 + (0x0004 * (x + 1))) /* DMAMUX1 request line multiplexer channel x configuration register */
#define AT32_DMAMUX_C0CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(0) /* 0x000 */
#define AT32_DMAMUX_C1CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(1) /* 0x004 */
#define AT32_DMAMUX_C2CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(2) /* 0x008 */
#define AT32_DMAMUX_C3CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(3) /* 0x00c */
#define AT32_DMAMUX_C4CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(4) /* 0x010 */
#define AT32_DMAMUX_C5CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(5) /* 0x014 */
#define AT32_DMAMUX_C6CR_OFFSET AT32_DMAMUX_CXCR_OFFSET(6) /* 0x018 */
/* 0x040-0x07C: Reserved */
#define AT32_DMAMUX_CSR_OFFSET 0x0030 /* DMAMUX1 request line multiplexer interrupt channel status register */
#define AT32_DMAMUX_CFR_OFFSET 0x0034 /* DMAMUX1 request line multiplexer interrupt clear flag register */
/* 0x088-0x0FC: Reserved */
#define AT32_DMAMUX_RGXCR_OFFSET(x) (0x0020 + (0x004 * (x))) /* DMAMUX1 request generator channel x configuration register */
#define AT32_DMAMUX_RG0CR_OFFSET AT32_DMAMUX_RGXCR_OFFSET(0)
#define AT32_DMAMUX_RG1CR_OFFSET AT32_DMAMUX_RGXCR_OFFSET(1)
#define AT32_DMAMUX_RG2CR_OFFSET AT32_DMAMUX_RGXCR_OFFSET(2)
#define AT32_DMAMUX_RG3CR_OFFSET AT32_DMAMUX_RGXCR_OFFSET(3)
#define AT32_DMAMUX_RGSR_OFFSET 0x0038 /* DMAMUX1 request generator interrupt status register */
#define AT32_DMAMUX_RGCFR_OFFSET 0x003c /* DMAMUX1 request generator interrupt clear flag register */
/* 0x148-0x3FC: Reserved */
/* Register Addresses *******************************************************/
/* Register Bitfield Definitions ********************************************/
/* DMAMUX1 CxCR - request line multiplexer channel x configuration register */
#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */
#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT)
# define DMAMUX_CCR_DMAREQID(x) ((x) << DMAMUX_CCR_DMAREQID_SHIFT)
#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */
#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */
#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT)
# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */
# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */
# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */
# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */
#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */
#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT)
#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */
#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT)
/* DMAMUX1 CSR - request line multiplexer interrupt channel status register */
#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */
/* DMAMUX1 CFR - request line multiplexer interrupt clear flag register */
#define DMAMUX1_CFR_SOF(x) (1 << (x)) /* Clear synchronization overrun event flag */
/* DMAMUX1 RGCR - request generator channel x configuration register */
#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */
#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT)
#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT)
# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */
# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */
# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */
# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */
#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */
#define DMAMUX_RGCR_GNBREQ_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT)
/* DMAMUX1 RGSR - request generator interrupt status register */
#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */
/* DMAMUX1 RGCFR - request generator interrupt clear flag register */
#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */
/* DMA channel mapping
*
* XXXXX.DDD.CCCCCCCC
* C - DMAMUX request
* D - DMA controller
* X - free bits
*/
#define DMAMAP_MAP(d,c) ((d) << 8 | (c))
#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07)
#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff)
/****************************************************************************
* Included Files
****************************************************************************/
/* Import DMAMUX map */
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_dmamux.h"
#else
# error "Unsupported AT32 sub family"
#endif
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_DMAMUX_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_eth.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ETH_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ETH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if AT32_NETHERNET > 0
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
/* MAC Registers */
#define AT32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */
#define AT32_ETH_MACFFR_OFFSET 0x0004 /* Ethernet MAC frame filter register */
#define AT32_ETH_MACHTHR_OFFSET 0x0008 /* Ethernet MAC hash table high register */
#define AT32_ETH_MACHTLR_OFFSET 0x000c /* Ethernet MAC hash table low register */
#define AT32_ETH_MACMIIAR_OFFSET 0x0010 /* Ethernet MAC MII address register */
#define AT32_ETH_MACMIIDR_OFFSET 0x0014 /* Ethernet MAC MII data register */
#define AT32_ETH_MACFCR_OFFSET 0x0018 /* Ethernet MAC flow control register */
#define AT32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */
#define AT32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */
#define AT32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */
#define AT32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */
#define AT32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */
#define AT32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */
#define AT32_ETH_MACA0LR_OFFSET 0x0044 /* Ethernet MAC address 0 low register */
#define AT32_ETH_MACA1HR_OFFSET 0x0048 /* Ethernet MAC address 1 high register */
#define AT32_ETH_MACA1LR_OFFSET 0x004c /* Ethernet MAC address1 low register */
#define AT32_ETH_MACA2HR_OFFSET 0x0050 /* Ethernet MAC address 2 high register */
#define AT32_ETH_MACA2LR_OFFSET 0x0054 /* Ethernet MAC address 2 low register */
#define AT32_ETH_MACA3HR_OFFSET 0x0058 /* Ethernet MAC address 3 high register */
#define AT32_ETH_MACA3LR_OFFSET 0x005c /* Ethernet MAC address 3 low register */
/* MMC Registers */
#define AT32_ETH_MMCCR_OFFSET 0x0100 /* Ethernet MMC control register */
#define AT32_ETH_MMCRIR_OFFSET 0x0104 /* Ethernet MMC receive interrupt register */
#define AT32_ETH_MMCTIR_OFFSET 0x0108 /* Ethernet MMC transmit interrupt register */
#define AT32_ETH_MMCRIMR_OFFSET 0x010c /* Ethernet MMC receive interrupt mask register */
#define AT32_ETH_MMCTIMR_OFFSET 0x0110 /* Ethernet MMC transmit interrupt mask register */
#define AT32_ETH_MMCTGFSCCR_OFFSET 0x014c /* Ethernet MMC transmitted good frames counter register (single collision) */
#define AT32_ETH_MMCTGFMSCCR_OFFSET 0x0150 /* Ethernet MMC transmitted good frames counter register (multiple-collision) */
#define AT32_ETH_MMCTGFCR_OFFSET 0x0168 /* Ethernet MMC transmitted good frames counter register */
#define AT32_ETH_MMCRFCECR_OFFSET 0x0194 /* Ethernet MMC received frames with CRC error counter register */
#define AT32_ETH_MMCRFAECR_OFFSET 0x0198 /* Ethernet MMC received frames with alignment error counter */
#define AT32_ETH_MMCRGUFCR_OFFSET 0x01c4 /* MMC received good unicast frames counter register */
/* IEEE 1588 time stamp registers */
#define AT32_ETH_PTPTSCR_OFFSET 0x0700 /* Ethernet PTP time stamp control register */
#define AT32_ETH_PTPSSIR_OFFSET 0x0704 /* Ethernet PTP subsecond increment register */
#define AT32_ETH_PTPTSHR_OFFSET 0x0708 /* Ethernet PTP time stamp high register */
#define AT32_ETH_PTPTSLR_OFFSET 0x070c /* Ethernet PTP time stamp low register */
#define AT32_ETH_PTPTSHUR_OFFSET 0x0710 /* Ethernet PTP time stamp high update register */
#define AT32_ETH_PTPTSLUR_OFFSET 0x0714 /* Ethernet PTP time stamp low update register */
#define AT32_ETH_PTPTSAR_OFFSET 0x0718 /* Ethernet PTP time stamp addend register */
#define AT32_ETH_PTPTTHR_OFFSET 0x071c /* Ethernet PTP target time high register */
#define AT32_ETH_PTPTTLR_OFFSET 0x0720 /* Ethernet PTP target time low register */
#define AT32_ETH_PTPTSSR_OFFSET 0x0728 /* Ethernet PTP time stamp status register */
#define AT32_ETH_PTPPPSCR_OFFSET 0x072c /* Ethernet PTP PPS control register */
/* DMA Registers */
#define AT32_ETH_DMABMR_OFFSET 0x1000 /* Ethernet DMA bus mode register */
#define AT32_ETH_DMATPDR_OFFSET 0x1004 /* Ethernet DMA transmit poll demand register */
#define AT32_ETH_DMARPDR_OFFSET 0x1008 /* Ethernet DMA receive poll demand register */
#define AT32_ETH_DMARDLAR_OFFSET 0x100c /* Ethernet DMA receive descriptor list address register */
#define AT32_ETH_DMATDLAR_OFFSET 0x1010 /* Ethernet DMA transmit descriptor list address register */
#define AT32_ETH_DMASR_OFFSET 0x1014 /* Ethernet DMA status register */
#define AT32_ETH_DMAOMR_OFFSET 0x1018 /* Ethernet DMA operation mode register */
#define AT32_ETH_DMAIER_OFFSET 0x101c /* Ethernet DMA interrupt enable register */
#define AT32_ETH_DMAMFBOC_OFFSET 0x1020 /* Ethernet DMA missed frame and buffer overflow counter register */
#define AT32_ETH_DMACHTDR_OFFSET 0x1048 /* Ethernet DMA current host transmit descriptor register */
#define AT32_ETH_DMACHRDR_OFFSET 0x104c /* Ethernet DMA current host receive descriptor register */
#define AT32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */
#define AT32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */
/* Register Base Addresses **************************************************/
/* MAC Registers */
#define AT32_ETH_MACCR (AT32_EMAC_BASE+AT32_ETH_MACCR_OFFSET)
#define AT32_ETH_MACFFR (AT32_EMAC_BASE+AT32_ETH_MACFFR_OFFSET)
#define AT32_ETH_MACHTHR (AT32_EMAC_BASE+AT32_ETH_MACHTHR_OFFSET)
#define AT32_ETH_MACHTLR (AT32_EMAC_BASE+AT32_ETH_MACHTLR_OFFSET)
#define AT32_ETH_MACMIIAR (AT32_EMAC_BASE+AT32_ETH_MACMIIAR_OFFSET)
#define AT32_ETH_MACMIIDR (AT32_EMAC_BASE+AT32_ETH_MACMIIDR_OFFSET)
#define AT32_ETH_MACFCR (AT32_EMAC_BASE+AT32_ETH_MACFCR_OFFSET)
#define AT32_ETH_MACVLANTR (AT32_EMAC_BASE+AT32_ETH_MACVLANTR_OFFSET)
#define AT32_ETH_MACRWUFFR (AT32_EMAC_BASE+AT32_ETH_MACRWUFFR_OFFSET)
#define AT32_ETH_MACPMTCSR (AT32_EMAC_BASE+AT32_ETH_MACPMTCSR_OFFSET)
#define AT32_ETH_MACSR (AT32_EMAC_BASE+AT32_ETH_MACSR_OFFSET)
#define AT32_ETH_MACIMR (AT32_EMAC_BASE+AT32_ETH_MACIMR_OFFSET)
#define AT32_ETH_MACA0HR (AT32_EMAC_BASE+AT32_ETH_MACA0HR_OFFSET)
#define AT32_ETH_MACA0LR (AT32_EMAC_BASE+AT32_ETH_MACA0LR_OFFSET)
#define AT32_ETH_MACA1HR (AT32_EMAC_BASE+AT32_ETH_MACA1HR_OFFSET)
#define AT32_ETH_MACA1LR (AT32_EMAC_BASE+AT32_ETH_MACA1LR_OFFSET)
#define AT32_ETH_MACA2HR (AT32_EMAC_BASE+AT32_ETH_MACA2HR_OFFSET)
#define AT32_ETH_MACA2LR (AT32_EMAC_BASE+AT32_ETH_MACA2LR_OFFSET)
#define AT32_ETH_MACA3HR (AT32_EMAC_BASE+AT32_ETH_MACA3HR_OFFSET)
#define AT32_ETH_MACA3LR (AT32_EMAC_BASE+AT32_ETH_MACA3LR_OFFSET)
/* MMC Registers */
#define AT32_ETH_MMCC (AT32_EMAC_BASE+AT32_ETH_MMCCR_OFFSET)
#define AT32_ETH_MMCRIR (AT32_EMAC_BASE+AT32_ETH_MMCRIR_OFFSET)
#define AT32_ETH_MMCTIR (AT32_EMAC_BASE+AT32_ETH_MMCTIR_OFFSET)
#define AT32_ETH_MMCRIMR (AT32_EMAC_BASE+AT32_ETH_MMCRIMR_OFFSET)
#define AT32_ETH_MMCTIMR (AT32_EMAC_BASE+AT32_ETH_MMCTIMR_OFFSET)
#define AT32_ETH_MMCTGFSCCR (AT32_EMAC_BASE+AT32_ETH_MMCTGFSCCR_OFFSET)
#define AT32_ETH_MMCTGFMSCCR (AT32_EMAC_BASE+AT32_ETH_MMCTGFMSCCR_OFFSET)
#define AT32_ETH_MMCTGFCR (AT32_EMAC_BASE+AT32_ETH_MMCTGFCR_OFFSET)
#define AT32_ETH_MMCRFCECR (AT32_EMAC_BASE+AT32_ETH_MMCRFCECR_OFFSET)
#define AT32_ETH_MMCRFAECR (AT32_EMAC_BASE+AT32_ETH_MMCRFAECR_OFFSET)
#define AT32_ETH_MMCRGUFCR (AT32_EMAC_BASE+AT32_ETH_MMCRGUFCR_OFFSET)
/* IEEE 1588 time stamp registers */
#define AT32_ETH_PTPTSCR (AT32_EMAC_BASE+AT32_ETH_PTPTSCR_OFFSET)
#define AT32_ETH_PTPSSIR (AT32_EMAC_BASE+AT32_ETH_PTPSSIR_OFFSET)
#define AT32_ETH_PTPTSHR (AT32_EMAC_BASE+AT32_ETH_PTPTSHR_OFFSET)
#define AT32_ETH_PTPTSLR (AT32_EMAC_BASE+AT32_ETH_PTPTSLR_OFFSET)
#define AT32_ETH_PTPTSHUR (AT32_EMAC_BASE+AT32_ETH_PTPTSHUR_OFFSET)
#define AT32_ETH_PTPTSLUR (AT32_EMAC_BASE+AT32_ETH_PTPTSLUR_OFFSET)
#define AT32_ETH_PTPTSAR (AT32_EMAC_BASE+AT32_ETH_PTPTSAR_OFFSET)
#define AT32_ETH_PTPTTHR (AT32_EMAC_BASE+AT32_ETH_PTPTTHR_OFFSET)
#define AT32_ETH_PTPTTLR (AT32_EMAC_BASE+AT32_ETH_PTPTTLR_OFFSET)
#define AT32_ETH_PTPTSSR (AT32_EMAC_BASE+AT32_ETH_PTPTSSR_OFFSET)
#define AT32_ETH_PTPPPSCR (AT32_EMAC_BASE+AT32_ETH_PTPPPSCR_OFFSET)
/* DMA Registers */
#define AT32_ETH_DMABMR (AT32_EMAC_BASE+AT32_ETH_DMABMR_OFFSET)
#define AT32_ETH_DMATPDR (AT32_EMAC_BASE+AT32_ETH_DMATPDR_OFFSET)
#define AT32_ETH_DMARPDR (AT32_EMAC_BASE+AT32_ETH_DMARPDR_OFFSET)
#define AT32_ETH_DMARDLAR (AT32_EMAC_BASE+AT32_ETH_DMARDLAR_OFFSET)
#define AT32_ETH_DMATDLAR (AT32_EMAC_BASE+AT32_ETH_DMATDLAR_OFFSET)
#define AT32_ETH_DMASR (AT32_EMAC_BASE+AT32_ETH_DMASR_OFFSET)
#define AT32_ETH_DMAOMR (AT32_EMAC_BASE+AT32_ETH_DMAOMR_OFFSET)
#define AT32_ETH_DMAIER (AT32_EMAC_BASE+AT32_ETH_DMAIER_OFFSET)
#define AT32_ETH_DMAMFBOC (AT32_EMAC_BASE+AT32_ETH_DMAMFBOC_OFFSET)
#define AT32_ETH_DMACHTDR (AT32_EMAC_BASE+AT32_ETH_DMACHTDR_OFFSET)
#define AT32_ETH_DMACHRDR (AT32_EMAC_BASE+AT32_ETH_DMACHRDR_OFFSET)
#define AT32_ETH_DMACHTBAR (AT32_EMAC_BASE+AT32_ETH_DMACHTBAR_OFFSET)
#define AT32_ETH_DMACHRBAR (AT32_EMAC_BASE+AT32_ETH_DMACHRBAR_OFFSET)
/* Register Bit-Field Definitions *******************************************/
/* MAC Registers */
/* Ethernet MAC configuration register */
#define ETH_MACCR_RE (1 << 2) /* Bit 2: Receiver enable */
#define ETH_MACCR_TE (1 << 3) /* Bit 3: Transmitter enable */
#define ETH_MACCR_DC (1 << 4) /* Bit 4: Deferral check */
#define ETH_MACCR_BL_SHIFT (5) /* Bits 5-6: Back-off limit */
#define ETH_MACCR_BL_MASK (3 << ETH_MACCR_BL_SHIFT)
# define ETH_MACCR_BL_10 (0 << ETH_MACCR_BL_SHIFT) /* 00: k = min (n, 10) */
# define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */
# define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */
# define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */
#define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */
#define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */
#define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */
#define ETH_MACCR_DM (1 << 11) /* Bit 11: Duplex mode */
#define ETH_MACCR_LM (1 << 12) /* Bit 12: Loopback mode */
#define ETH_MACCR_ROD (1 << 13) /* Bit 13: Receive own disable */
#define ETH_MACCR_FES (1 << 14) /* Bit 14: Fast Ethernet speed */
#define ETH_MACCR_CSD (1 << 16) /* Bit 16: Carrier sense disable */
#define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */
#define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT)
# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */
#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */
#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */
/* Ethernet MAC frame filter register */
#define ETH_MACFFR_PM (1 << 0) /* Bit 0: Promiscuous mode */
#define ETH_MACFFR_HU (1 << 1) /* Bit 1: Hash unicast */
#define ETH_MACFFR_HM (1 << 2) /* Bit 2: Hash multicast */
#define ETH_MACFFR_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */
#define ETH_MACFFR_PAM (1 << 4) /* Bit 4: Pass all multicast */
#define ETH_MACFFR_BFD (1 << 5) /* Bit 5: Broadcast frames disable */
#define ETH_MACFFR_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */
#define ETH_MACFFR_PCF_MASK (3 << ETH_MACFFR_PCF_SHIFT)
# define ETH_MACFFR_PCF_NONE (0 << ETH_MACFFR_PCF_SHIFT) /* Prevents all control frames */
# define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */
# define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */
# define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */
#define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */
#define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */
#define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */
#define ETH_MACFFR_RA (1 << 31) /* Bit 31: Receive all */
/* Ethernet MAC hash table high/low registers (32-bit values) */
/* Ethernet MAC MII address register */
#define ETH_MACMIIAR_MB (1 << 0) /* Bit 0: MII busy */
#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */
#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-5: Clock range */
#define ETH_MACMIIAR_CR_MASK (15 << ETH_MACMIIAR_CR_SHIFT)
#define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
#define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */
#define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
#define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
#define ETH_MACMIIAR_CR_150_250 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-250 MHz HCLK/102 */
#define ETH_MACMIIAR_CR_250_300 (5 << ETH_MACMIIAR_CR_SHIFT) /* 101 250-300 MHz HCLK/124 */
#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */
#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT)
#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */
#define ETH_MACMIIAR_PA_MASK (31 << ETH_MACMIIAR_PA_SHIFT)
/* Ethernet MAC MII data register */
#define ETH_MACMIIDR_MASK (0xffff)
/* Ethernet MAC flow control register */
#define ETH_MACFCR_FCB_BPA (1 << 0) /* Bit 0: Flow control busy/back pressure activate */
#define ETH_MACFCR_TFCE (1 << 1) /* Bit 1: Transmit flow control enable */
#define ETH_MACFCR_RFCE (1 << 2) /* Bit 2: Receive flow control enable */
#define ETH_MACFCR_UPFD (1 << 3) /* Bit 3: Unicast pause frame detect */
#define ETH_MACFCR_PLT_SHIFT (4) /* Bits 4-5: Pause low threshold */
#define ETH_MACFCR_PLT_MASK (3 << ETH_MACFCR_PLT_SHIFT)
# define ETH_MACFCR_PLT_M4 (0 << ETH_MACFCR_PLT_SHIFT) /* 00 Pause - 4 slot times */
# define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */
# define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */
# define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */
#define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */
#define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */
#define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT)
/* Ethernet MAC VLAN tag register */
#define ETH_MACVLANTR_VLANTI_SHIFT (0) /* Bits 0-15: VLAN tag identifier (for receive frames) */
#define ETH_MACVLANTR_VLANTI_MASK (0xffff << ETH_MACVLANTR_VLANTI_SHIFT)
#define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */
/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to
* remote remote wake-up filters.
*/
/* Ethernet MAC PMT control and status register */
#define ETH_MACPMTCSR_PD (1 << 0) /* Bit 0: Power down */
#define ETH_MACPMTCSR_MPE (1 << 1) /* Bit 1: Magic Packet enable */
#define ETH_MACPMTCSR_WFE (1 << 2) /* Bit 2: Wakeup frame enable */
#define ETH_MACPMTCSR_MPR (1 << 5) /* Bit 5: Magic packet received */
#define ETH_MACPMTCSR_WFR (1 << 6) /* Bit 6: Wakeup frame received */
#define ETH_MACPMTCSR_GU (1 << 9) /* Bit 9: Global unicast */
/* Ethernet MAC interrupt status register */
#define ETH_MACSR_PMTS (1 << 3) /* Bit 3: PMT status */
#define ETH_MACSR_MMCS (1 << 4) /* Bit 4: MMC status */
#define ETH_MACSR_MMCRS (1 << 5) /* Bit 5: MMC receive status */
#define ETH_MACSR_MMCTS (1 << 6) /* Bit 6: MMC transmit status */
#define ETH_MACSR_TSTS (1 << 9) /* Bit 9: Time stamp trigger status */
/* Ethernet MAC interrupt mask register */
#define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */
#define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */
#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM)
/* Ethernet MAC address 0 high register */
#define ETH_MACA0HR_MACA0H_SHIFT (0) /* Bits 0-15: MAC address0 high [47:32] */
#define ETH_MACA0HR_MACA0H_MASK (0xffff << ETH_MACA0HR_MACA0H_SHIFT)
#define ETH_MACA0HR_MO (1 << 31) /* Bit 31:Always */
/* Ethernet MAC address 0 low register (MAC address0 low [31:0]) */
/* Ethernet MAC address 1 high register */
#define ETH_MACA1HR_MACA1H_SHIFT (0) /* Bits 0-15: MAC address1 high [47:32] */
#define ETH_MACA1HR_MACA1H_MASK (0xffff << ETH_MACA1HR_MACA1H_SHIFT)
#define ETH_MACA1HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */
#define ETH_MACA1HR_MBC_MASK (0x3f << ETH_MACA1HR_MBC_SHIFT)
# define ETH_MACA1HR_MBC_40_47 (0x20 << ETH_MACA1HR_MBC_SHIFT) /* Bit 29: ETH_MACA1HR [8-15] */
# define ETH_MACA1HR_MBC_32_39 (0x10 << ETH_MACA1HR_MBC_SHIFT) /* Bit 28: ETH_MACA1HR [0-7] */
# define ETH_MACA1HR_MBC_24_31 (0x08 << ETH_MACA1HR_MBC_SHIFT) /* Bit 27: ETH_MACA1LR [24-31] */
# define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */
# define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */
# define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */
#define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */
#define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */
/* Ethernet MAC address1 low register (MAC address1 low [31:0]) */
/* Ethernet MAC address 2 high register */
#define ETH_MACA2HR_MACA2H_SHIFT (0) /* Bits 0-15: MAC address2 high [47:32] */
#define ETH_MACA2HR_MACA2H_MASK (0xffff << ETH_MACA2HR_MACA2H_SHIFT)
#define ETH_MACA2HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */
#define ETH_MACA2HR_MBC_MASK (0x3f << ETH_MACA2HR_MBC_SHIFT)
# define ETH_MACA2HR_MBC_40_47 (0x20 << ETH_MACA2HR_MBC_SHIFT) /* Bit 29: ETH_MACA2HR [8-15] */
# define ETH_MACA2HR_MBC_32_39 (0x10 << ETH_MACA2HR_MBC_SHIFT) /* Bit 28: ETH_MACA2HR [0-7] */
# define ETH_MACA2HR_MBC_24_31 (0x08 << ETH_MACA2HR_MBC_SHIFT) /* Bit 27: ETH_MACA2LR [24-31] */
# define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */
# define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */
# define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */
#define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */
#define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */
/* Ethernet MAC address 2 low register (MAC address2 low [31:0]) */
/* Ethernet MAC address 3 high register */
#define ETH_MACA3HR_MACA3H_SHIFT (0) /* Bits 0-15: MAC address3 high [47:32] */
#define ETH_MACA3HR_MACA3H_MASK (0xffff << ETH_MACA3HR_MACA3H_SHIFT)
#define ETH_MACA3HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */
#define ETH_MACA3HR_MBC_MASK (0x3f << ETH_MACA3HR_MBC_SHIFT)
# define ETH_MACA3HR_MBC_40_47 (0x20 << ETH_MACA3HR_MBC_SHIFT) /* Bit 29: ETH_MACA3HR [8-15] */
# define ETH_MACA3HR_MBC_32_39 (0x10 << ETH_MACA3HR_MBC_SHIFT) /* Bit 28: ETH_MACA3HR [0-7] */
# define ETH_MACA3HR_MBC_24_31 (0x08 << ETH_MACA3HR_MBC_SHIFT) /* Bit 27: ETH_MACA3LR [24-31] */
# define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */
# define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */
# define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */
#define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */
#define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */
/* Ethernet MAC address 3 low register (MAC address3 low [31:0]) */
/* MMC Registers */
/* Ethernet MMC control register */
#define ETH_MMCCR_CR (1 << 0) /* Bit 0: Counter reset */
#define ETH_MMCCR_CSR (1 << 1) /* Bit 1: Counter stop rollover */
#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */
#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */
/* Ethernet MMC receive interrupt and interrupt mask registers */
#define ETH_MMCRI_RFCE (1 << 5) /* Bit 5: Received frame CRC error */
#define ETH_MMCRI_RFAE (1 << 6) /* Bit 6: Received frames alignment error */
#define ETH_MMCRI_RGUF (1 << 17) /* Bit 17: Received good unicast frames */
/* Ethernet MMC transmit interrupt and interrupt mask register */
#define ETH_MMCTI_TGFSC (1 << 14) /* Bit 14: Transmitted good frames single collision */
#define ETH_MMCTI_TGFMSC (1 << 15) /* Bit 15: Transmitted good frames more single collision */
#define ETH_MMCTI_TGF (1 << 21) /* Bit 21: Transmitted good frames */
/* 32-bit counters:
*
* Ethernet MMC transmitted good frames counter register (single collision)
* Ethernet MMC transmitted good frames counter register (multiple-collision)
* Ethernet MMC transmitted good frames counter register
* Ethernet MMC received frames with CRC error counter register
* Ethernet MMC received frames with alignment error counter
* MMC received good unicast frames counter register
*/
/* IEEE 1588 time stamp registers */
/* Ethernet PTP time stamp control register */
#define ETH_PTPTSCR_TSE (1 << 0) /* Bit 0: Time stamp enable */
#define ETH_PTPTSCR_TSFCU (1 << 1) /* Bit 1: Time stamp fine or coarse update */
#define ETH_PTPTSCR_TSSTI (1 << 2) /* Bit 2: Time stamp system time initialize */
#define ETH_PTPTSCR_TSSTU (1 << 3) /* Bit 3: Time stamp system time update */
#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */
#if defined(CONFIG_AT32_AT32F43XX)
#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */
#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSCR_TSSPTPOEFE (1 << 11) /* Bit 11: Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSCR_TSSIPV6FE (1 << 12) /* Bit 12: Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSCR_TSSIPV4FE (1 << 13) /* Bit 13: Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSCR_TSSEME (1 << 14) /* Bit 14: Time stamp snapshot for event message enable */
#define ETH_PTPTSCR_TSSMRME (1 << 15) /* Bit 15: Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSCR_TSCNT_SHIFT (16) /* Bits 16-17: Time stamp clock node type */
#define ETH_PTPTSCR_TSCNT_MASK (3 << ETH_PTPTSCR_TSCNT_SHIFT)
# define ETH_PTPTSCR_TSCNT_ORDINARY (0 << ETH_PTPTSCR_TSCNT_SHIFT) /* 00: Ordinary clock */
# define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */
# define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */
# define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */
#define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */
#endif
/* Ethernet PTP subsecond increment register */
#define ETH_PTPSSIR_MASK (0xff)
/* Ethernet PTP time stamp high register (32-bit) */
/* Ethernet PTP time stamp low register */
#define ETH_PTPTSLR_STPNS (1 << 31) /* Bit 31: System time positive or negative sign */
#define ETH_PTPTSLR_MASK (0x7fffffff) /* Bits 0-30: System time subseconds */
/* Ethernet PTP time stamp high update register (32-bit) */
/* Ethernet PTP time stamp low update register */
#define ETH_PTPTSLU_TSUPNS (1 << 31) /* Bit 31: System time positive or negative sign */
#define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */
/* Ethernet PTP time stamp addend register (32-bit) */
/* Ethernet PTP target time high register (32-bit) */
/* Ethernet PTP target time low register (32-bit) */
/* Ethernet PTP time stamp status register */
#define ETH_PTPTSSR_TSSO (1 << 0) /* Bit 0: Time stamp second overflow */
#define ETH_PTPTSSR_TSTTR (1 << 1) /* Bit 1: Time stamp target time reached */
/* Ethernet PTP PPS control register */
#define ETH_PTPPPSCR_PPSFREQ_SHIFT (0) /* Bits 0-3: PPS frequency selection */
#define ETH_PTPPPSCR_PPSFREQ_MASK (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT)
# define ETH_PTPPPSCR_PPSFREQ_1HZ (0 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1 Hz with pulse width of 125/100 ms for binary/digital rollover */
# define ETH_PTPPPSCR_PPSFREQ_2HZ (1 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_4HZ (2 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_8HZ (3 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_16HZ (4 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_32HZ (5 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_64HZ (6 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 64 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_128HZ (7 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 128 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_256HZ (8 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 256 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_512HZ (9 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 512 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_1KHZ (10 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1024 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_2KHZ (11 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2048 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_4KHZ (12 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4096 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_8KHZ (13 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8192 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_16KHZ (14 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16384 Hz with 50% duty cycle */
# define ETH_PTPPPSCR_PPSFREQ_32KHZ (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32768 Hz with 50% duty cycle */
/* DMA Registers */
/* Ethernet DMA bus mode register */
#define ETH_DMABMR_SR (1 << 0) /* Bit 0: Software reset */
#define ETH_DMABMR_DA (1 << 1) /* Bit 1: DMA Arbitration */
#define ETH_DMABMR_DSL_SHIFT (2) /* Bits 2-6: Descriptor skip length */
#define ETH_DMABMR_DSL_MASK (31 << ETH_DMABMR_DSL_SHIFT)
# define ETH_DMABMR_DSL(n) ((n) << ETH_DMABMR_DSL_SHIFT)
#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */
# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT)
#define ETH_DMABMR_RTPR_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_MASK (3 << ETH_DMABMR_RTPR_SHIFT)
# define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_RTPR_SHIFT) /* 00: 1:1 */
# define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_RTPR_SHIFT) /* 01: 2:1 */
# define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_RTPR_SHIFT) /* 10: 3:1 */
# define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_RTPR_SHIFT) /* 11: 4:1 */
#define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */
#define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */
#define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT)
# define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */
#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 8xPBL mode */
#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */
/* Ethernet DMA transmit poll demand register (32-bit) */
/* Ethernet DMA receive poll demand register (32-bit) */
/* Ethernet DMA receive descriptor list address register (32-bit address) */
/* Ethernet DMA transmit descriptor list address register (32-bit address) */
/* Interrupt bit definitions common between the DMA status register (DMASR)
* and the DMA interrupt enable register (DMAIER).
*/
#define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */
#define ETH_DMAINT_TPSI (1 << 1) /* Bit 1: Transmit process stopped interrupt */
#define ETH_DMAINT_TBUI (1 << 2) /* Bit 2: Transmit buffer unavailable interrupt */
#define ETH_DMAINT_TJTI (1 << 3) /* Bit 3: Transmit jabber timeout interrupt */
#define ETH_DMAINT_ROI (1 << 4) /* Bit 4: Overflow interrupt */
#define ETH_DMAINT_TUI (1 << 5) /* Bit 5: Underflow interrupt */
#define ETH_DMAINT_RI (1 << 6) /* Bit 6: Receive interrupt */
#define ETH_DMAINT_RBUI (1 << 7) /* Bit 7: Receive buffer unavailable interrupt */
#define ETH_DMAINT_RPSI (1 << 8) /* Bit 8: Receive process stopped interrupt */
#define ETH_DMAINT_RWTI (1 << 9) /* Bit 9: Receive watchdog timeout interrupt */
#define ETH_DMAINT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */
#define ETH_DMAINT_FBEI (1 << 13) /* Bit 13: Fatal bus error interrupt */
#define ETH_DMAINT_ERI (1 << 14) /* Bit 14: Early receive interrupt */
#define ETH_DMAINT_AIS (1 << 15) /* Bit 15: Abnormal interrupt summary */
#define ETH_DMAINT_NIS (1 << 16) /* Bit 16: Normal interrupt summary */
/* Ethernet DMA status register (in addition to the interrupt bits above */
#define ETH_DMASR_RPS_SHIFT (17) /* Bits 17-19: Receive process state */
#define ETH_DMASR_RPS_MASK (7 << ETH_DMASR_RPS_SHIFT)
# define ETH_DMASR_RPS_STOPPED (0 << ETH_DMASR_RPS_SHIFT) /* 000: Stopped: Reset or Stop Receive Command issued */
# define ETH_DMASR_RPS_RXDESC (1 << ETH_DMASR_RPS_SHIFT) /* 001: Running: Fetching receive transfer descriptor */
# define ETH_DMASR_RPS_WAITING (3 << ETH_DMASR_RPS_SHIFT) /* 011: Running: Waiting for receive packet */
# define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */
# define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */
# define ETH_DMASR_RPS_TRANSFER (6 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */
#define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */
#define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT)
# define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */
# define ETH_DMASR_TPS_TXDESC (1 << ETH_DMASR_TPS_SHIFT) /* 001: Running; Fetching transmit transfer descriptor */
# define ETH_DMASR_TPS_WAITING (2 << ETH_DMASR_TPS_SHIFT) /* 010: Running; Waiting for status */
# define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */
# define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */
# define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */
#define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */
#define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT)
#define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */
#define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */
#define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */
#define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */
#define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */
#define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */
/* Ethernet DMA operation mode register */
#define ETH_DMAOMR_SR (1 << 1) /* Bit 1: Start/stop receive */
#define ETH_DMAOMR_OSF (1 << 2) /* Bit 2: Operate on second frame */
#define ETH_DMAOMR_RTC_SHIFT (3) /* Bits 3-4: Receive threshold control */
#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_SHIFT)
# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_SHIFT)
# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_SHIFT)
# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_SHIFT)
# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_SHIFT)
#define ETH_DMAOMR_FUGF (1 << 6) /* Bit 6: Forward undersized good frames */
#define ETH_DMAOMR_FEF (1 << 7) /* Bit 7: Forward error frames */
#define ETH_DMAOMR_ST (1 << 13) /* Bit 13: Start/stop transmission */
#define ETH_DMAOMR_TTC_SHIFT (14) /* Bits 14-16: Transmit threshold control */
#define ETH_DMAOMR_TTC_MASK (7 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_64 (0 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_128 (1 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_192 (2 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_256 (3 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_40 (4 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_32 (5 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_24 (6 << ETH_DMAOMR_TTC_SHIFT)
# define ETH_DMAOMR_TTC_16 (7 << ETH_DMAOMR_TTC_SHIFT)
#define ETH_DMAOMR_FTF (1 << 20) /* Bit 20: Flush transmit FIFO */
#define ETH_DMAOMR_TSF (1 << 21) /* Bit 21: Transmit store and forward */
#define ETH_DMAOMR_DFRF (1 << 24) /* Bit 24: Disable flushing of received frames */
#define ETH_DMAOMR_RSF (1 << 25) /* Bit 25: Receive store and forward */
#define ETH_DMAOMR_DTCEFD (1 << 26) /* Bit 26: Dropping of TCP/IP checksum error frames disable */
/* Ethernet DMA missed frame and buffer overflow counter register */
#define ETH_DMAMFBOC_MFC_SHIFT (0) /* Bits 0-15: Missed frames by the controller */
#define ETH_DMAMFBOC_MFC_MASK (0xffff << ETH_DMAMFBOC_MFC_SHIFT)
#define ETH_DMAMFBOC_OMFC (1 << 16) /* Bit 16: Overflow bit for missed frame counter */
#define ETH_DMAMFBOC_MFA_SHIFT (17) /* Bits 17-27: Missed frames by the application */
#define ETH_DMAMFBOC_MFA_MASK (0x7ff << ETH_DMAMFBOC_MFA_SHIFT)
#define ETH_DMAMFBOC_OFOC (1 << 28) /* Bit 28: Overflow bit for FIFO overflow counter */
/* Ethernet DMA current host transmit descriptor register
* (32-bit address)
*/
/* Ethernet DMA current host receive descriptor register
* (32-bit address)
*/
/* Ethernet DMA current host transmit buffer address register
* (32-bit address)
*/
/* Ethernet DMA current host receive buffer address register
* (32-bit address)
*/
/* DMA Descriptors **********************************************************/
/* TDES0: Transmit descriptor Word0 */
#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */
#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */
#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */
#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */
#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT)
#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */
#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */
#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */
#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */
#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */
#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */
#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */
#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */
#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */
#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */
#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */
#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */
#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */
#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */
#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT)
# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */
# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */
# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */
# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */
#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */
#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */
#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */
#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */
#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */
#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */
#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */
/* TDES1: Transmit descriptor Word1 */
#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */
#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT)
#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */
#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT)
/* TDES2: Transmit descriptor Word2 (32-bit address) */
/* TDES3: Transmit descriptor Word3 (32-bit address) */
/* RDES0: Receive descriptor Word0 */
#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */
#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */
#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */
#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */
#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */
#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */
#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */
#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */
#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */
#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */
#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */
#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */
#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */
#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */
#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */
#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */
#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */
#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT)
#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */
#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */
/* RDES1: Receive descriptor Word1 */
#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */
#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT)
/* Bit 13: Reserved */
#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */
#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */
#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */
#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT)
#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */
/* RDES2: Receive descriptor Word2 (32-bit address) */
/* RDES3: Receive descriptor Word3 (32-bit address) */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* Ethernet TX DMA Descriptor */
struct eth_txdesc_s
{
/* Normal DMA descriptor words */
volatile uint32_t tdes0; /* Status */
volatile uint32_t tdes1; /* Control and buffer1/2 lengths */
volatile uint32_t tdes2; /* Buffer1 address pointer */
volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */
};
/* Ethernet RX DMA Descriptor */
struct eth_rxdesc_s
{
volatile uint32_t rdes0; /* Status */
volatile uint32_t rdes1; /* Control and buffer1/2 lengths */
volatile uint32_t rdes2; /* Buffer1 address pointer */
volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */
};
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* AT32_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_ETH_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_EXTI_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
# define AT32_NEXTI 23
# define AT32_EXTI_MASK 0x007fffff
#endif
#define AT32_EXTI_BIT(n) (1 << (n))
/* Register Offsets *********************************************************/
#define AT32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
#define AT32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
#define AT32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
#define AT32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
#define AT32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
#define AT32_EXTI_PR_OFFSET 0x0014 /* Pending register */
/* Register Addresses *******************************************************/
# define AT32_EXTI_IMR (AT32_EXINT_BASE+AT32_EXTI_IMR_OFFSET)
# define AT32_EXTI_EMR (AT32_EXINT_BASE+AT32_EXTI_EMR_OFFSET)
# define AT32_EXTI_RTSR (AT32_EXINT_BASE+AT32_EXTI_RTSR_OFFSET)
# define AT32_EXTI_FTSR (AT32_EXINT_BASE+AT32_EXTI_FTSR_OFFSET)
# define AT32_EXTI_SWIER (AT32_EXINT_BASE+AT32_EXTI_SWIER_OFFSET)
# define AT32_EXTI_PR (AT32_EXINT_BASE+AT32_EXTI_PR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* EXTI lines > 15 are associated with internal devices: */
#if defined(CONFIG_AT32_AT32F43XX)
# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */
# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */
# define EXTI_OTGHS_WAKEUP (1 << 20) /* EXTI line 20 is connected to the USB OTG HS Wakeup event */
# define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
# define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
# define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */
#endif
/* Interrupt mask register */
#define EXTI_IMR_BIT(n) AT32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_IMR_MASK AT32_EXTI_MASK
/* Event mask register */
#define EXTI_EMR_BIT(n) AT32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EMR_MASK AT32_EXTI_MASK
/* Rising Trigger selection register */
#define EXTI_RTSR_BIT(n) AT32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
#define EXTI_RTSR_MASK AT32_EXTI_MASK
/* Falling Trigger selection register */
#define EXTI_FTSR_BIT(n) AT32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
#define EXTI_FTSR_MASK AT32_EXTI_MASK
/* Software interrupt event register */
#define EXTI_SWIER_BIT(n) AT32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
#define EXTI_SWIER_MASK AT32_EXTI_MASK
/* Pending register */
#define EXTI_PR_BIT(n) AT32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK AT32_EXTI_MASK
/* Compatibility Definitions ************************************************/
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_EXTI_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_FLASH_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_FLASH_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_AT32_FLASH_CONFIG_DEFAULT) && \
!defined(CONFIG_AT32_FLASH_CONFIG_C) && \
!defined(CONFIG_AT32_FLASH_CONFIG_G) && \
!defined(CONFIG_AT32_FLASH_CONFIG_M)
# define CONFIG_AT32_FLASH_CONFIG_DEFAULT
#endif
#if defined(CONFIG_AT32_FLASH_CONFIG_DEFAULT)
# if defined(CONFIG_AT32_AT32F43XX)
# define AT32_FLASH_NPAGES 512
# define AT32_FLASH_BANK2_START 256
# define AT32_FLASH_SIZE (AT32_FLASH_NPAGES * AT32_FLASH_PAGESIZE)
# define AT32_FLASH_PAGESIZE (2 * 1024)
# endif
#endif /* CONFIG_AT32_FLASH_CONFIG_DEFAULT */
/* Override of the Flash Has been Chosen */
#if !defined(CONFIG_AT32_FLASH_CONFIG_DEFAULT)
# if defined(CONFIG_AT32_AT32F43XX)
# if defined(CONFIG_AT32_FLASH_CONFIG_C)
# define AT32_FLASH_NPAGES 128
# undef AT32_FLASH_BANK2_START /* there is no bank2 */
# define AT32_FLASH_SIZE (AT32_FLASH_NPAGES * AT32_FLASH_PAGESIZE)
# define AT32_FLASH_PAGESIZE (2 * 1024)
# elif defined(CONFIG_AT32_FLASH_CONFIG_G)
# define AT32_FLASH_NPAGES 512
# define AT32_FLASH_BANK2_START 256
# define AT32_FLASH_SIZE (AT32_FLASH_NPAGES * AT32_FLASH_PAGESIZE)
# define AT32_FLASH_PAGESIZE (2 * 1024)
# elif defined(CONFIG_AT32_FLASH_CONFIG_M)
# define AT32_FLASH_NPAGES 1008
# define AT32_FLASH_BANK2_START 512
# define AT32_FLASH_PAGESIZE (4 * 1024)
# define AT32_FLASH_SIZE (AT32_FLASH_NPAGES * AT32_FLASH_PAGESIZE)
# else
# define AT32_FLASH_NPAGES 128
# undef AT32_FLASH_BANK2_START /* there is no bank2 */
# define AT32_FLASH_SIZE (AT32_FLASH_NPAGES * AT32_FLASH_PAGESIZE)
# define AT32_FLASH_PAGESIZE (2 * 1024)
# endif
# endif
#endif /* !defined(CONFIG_AT32_FLASH_CONFIG_DEFAULT) */
#if defined(CONFIG_AT32_AT32F43XX) && (AT32_FLASH_NPAGES > 128)
#if (AT32_FLASH_NPAGES > 128)
# define AT32_FLASH_DUAL_BANK 1
# if defined(CONFIG_AT32_FLASH_CONFIG_G)
# define AT32_FLASH_BANK0_NPAGES 256
# else
# define AT32_FLASH_BANK0_NPAGES 512
# endif
# define AT32_FLASH_BANK1_NPAGES (AT32_FLASH_NPAGES - AT32_FLASH_BANK0_NPAGES)
# define AT32_FLASH_BANK0_BASE (AT32_FLASH_BASE)
# define AT32_FLASH_BANK1_BASE \
(AT32_FLASH_BASE + AT32_FLASH_PAGESIZE * AT32_FLASH_BANK0_NPAGES)
#else
# define AT32_FLASH_BANK0_NPAGES 128
# define AT32_FLASH_BANK0_BASE (AT32_FLASH_BASE)
#endif
#endif
/* Register Offsets *********************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
#define AT32_FLASH_PSR_OFFSET 0x00
#define AT32_FLASH_UNLOCK_OFFSET 0x04
#define AT32_FLASH_USD_UNLOCK_OFFSET 0x08
#define AT32_FLASH_STS_OFFSET 0x0C
#define AT32_FLASH_CTRL_OFFSET 0x10
#define AT32_FLASH_ADDR_OFFSET 0x14
#define AT32_FLASH_USD_OFFSET 0x1C
#define AT32_FLASH_EPPS0_OFFSET 0x20
#define AT32_FLASH_EPPS1_OFFSET 0x2C
#define AT32_FLASH_UNLOCK2_OFFSET 0x44
#define AT32_FLASH_STS2_OFFSET 0x4C
#define AT32_FLASH_CTRL2_OFFSET 0x50
#define AT32_FLASH_ADDR2_OFFSET 0x54
#define AT32_FLASH_CONTR_OFFSET 0x58
#define AT32_FLASH_DIVR_OFFSET 0x60
#define AT32_SLIB_STS2_OFFSET 0xC8
#define AT32_SLIB_STS0_OFFSET 0xCC
#define AT32_SLIB_STS1_OFFSET 0xD0
#define AT32_SLIB_PWD_CRL_OFFSET 0xD4
#define AT32_SLIB_MISC_STS_OFFSET 0xD8
#define AT32_SLIB_SET_PWD_OFFSET 0xDC
#define AT32_SLIB_SET_RANGE0_OFFSET 0xE0
#define AT32_SLIB_SET_RANGE1_OFFSET 0xE4
#define AT32_SLIB_UNLOCK_OFFSET 0xF0
#define AT32_FLASH_CRC_CTRL_OFFSET 0xF4
#define AT32_FLASH_CRC_CHKR_OFFSET 0xF8
#endif
/* Register Addresses *******************************************************/
#if defined(CONFIG_AT32_AT32F43XX)
#define AT32_FLASH_PSR (AT32_FLASHIF_BASE+AT32_FLASH_PSR_OFFSET)
#define AT32_FLASH_UNLOCK (AT32_FLASHIF_BASE+AT32_FLASH_UNLOCK_OFFSET)
#define AT32_FLASH_USD_UNLOCK (AT32_FLASHIF_BASE+AT32_FLASH_USD_UNLOCK_OFFSET)
#define AT32_FLASH_STS (AT32_FLASHIF_BASE+AT32_FLASH_STS_OFFSET)
#define AT32_FLASH_CTRL (AT32_FLASHIF_BASE+AT32_FLASH_CTRL_OFFSET)
#define AT32_FLASH_ADDR (AT32_FLASHIF_BASE+AT32_FLASH_ADDR_OFFSET)
#define AT32_FLASH_USD (AT32_FLASHIF_BASE+AT32_FLASH_USD_OFFSET)
#define AT32_FLASH_EPPS0 (AT32_FLASHIF_BASE+AT32_FLASH_EPPS0_OFFSET)
#define AT32_FLASH_EPPS1 (AT32_FLASHIF_BASE+AT32_FLASH_EPPS1_OFFSET)
#define AT32_FLASH_UNLOCK2 (AT32_FLASHIF_BASE+AT32_FLASH_UNLOCK2_OFFSET)
#define AT32_FLASH_STS2 (AT32_FLASHIF_BASE+AT32_FLASH_STS2_OFFSET)
#define AT32_FLASH_CTRL2 (AT32_FLASHIF_BASE+AT32_FLASH_CTRL2_OFFSET)
#define AT32_FLASH_ADDR2 (AT32_FLASHIF_BASE+AT32_FLASH_ADDR2_OFFSET)
#define AT32_FLASH_CONTR (AT32_FLASHIF_BASE+AT32_FLASH_CONTR_OFFSET)
#define AT32_FLASH_DIVR (AT32_FLASHIF_BASE+AT32_FLASH_DIVR_OFFSET)
#define AT32_SLIB_STS2 (AT32_FLASHIF_BASE+AT32_SLIB_STS2_OFFSET)
#define AT32_SLIB_STS0 (AT32_FLASHIF_BASE+AT32_SLIB_STS0_OFFSET)
#define AT32_SLIB_STS1 (AT32_FLASHIF_BASE+AT32_SLIB_STS1_OFFSET)
#define AT32_SLIB_PWD_CRL (AT32_FLASHIF_BASE+AT32_SLIB_PWD_CRL_OFFSET)
#define AT32_SLIB_MISC_STS (AT32_FLASHIF_BASE+AT32_SLIB_MISC_STS_OFFSET)
#define AT32_SLIB_SET_PWD (AT32_FLASHIF_BASE+AT32_SLIB_SET_PWD_OFFSET)
#define AT32_SLIB_SET_RANGE0 (AT32_FLASHIF_BASE+AT32_SLIB_SET_RANGE0_OFFSET)
#define AT32_SLIB_SET_RANGE1 (AT32_FLASHIF_BASE+AT32_SLIB_SET_RANGE1_OFFSET)
#define AT32_SLIB_UNLOCK (AT32_FLASHIF_BASE+AT32_SLIB_UNLOCK_OFFSET)
#define AT32_FLASH_CRC_CTRL (AT32_FLASHIF_BASE+AT32_FLASH_CRC_CTRL_OFFSET)
#define AT32_FLASH_CRC_CHKR (AT32_FLASHIF_BASE+AT32_FLASH_CRC_CHKR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Flash Access Control Register (PSR) */
#if defined(CONFIG_AT32_AT32F43XX)
#define FLASH_PSR_NZW_BST (1 << 12) /* Flash non-zero wait area boost */
#define FLASH_PSR_NZW_BST_STS (1 << 13) /* Flash non-zero wait area boost status */
#endif
/* Flash status Register1(for bank1) */
#if defined(CONFIG_AT32_AT32F43XX)
#define FLASH_STS_OBF (1 << 0) /* Operation busy flag */
#define FLASH_STS_PRGMERR (1 << 2) /* Program error */
#define FLASH_STS_EPPERR (1 << 4) /* Erase/Program protection error */
#define FLASH_STS_ODF (1 << 5) /* Operation done flag */
#endif
/* Flash control Register(for bank1) */
#if defined(CONFIG_AT32_AT32F43XX)
#define FLASH_CTRL_FPRGM (1 << 0) /* Flash program */
#define FLASH_CTRL_SECERS (1 << 1) /* Sector erase */
#define FLASH_CTRL_BANKERS (1 << 2) /* Bank erase */
#define FLASH_CTRL_BLKERS (1 << 3) /* Block erase */
#define FLASH_CTRL_USDPRGM (1 << 4) /* User system data program */
#define FLASH_CTRL_USDERS (1 << 5) /* User system data erase */
#define FLASH_CTRL_ERSTR (1 << 6) /* Erasing start */
#define FLASH_CTRL_OPLK (1 << 7) /* Operation lock */
#define FLASH_CTRL_USDULKS (1 << 9) /* User system data unlock success */
#define FLASH_CTRL_ERRIE (1 << 10) /* Error interrupt enable */
#define FLASH_CTRL_ODFIE (1 << 12) /* Operation done flag interrupt enable */
#endif
/* Flash address Register(for bank1) */
#define FLASH_ADDR_FA_SHIFT (0) /* Flash address */
#define FLASH_ADDR_FA_MASK (0xffffffff << FLASH_ADDR_FA_SHIFT)
#define FLASH_ADDR_FA(X) ((X) << FLASH_ADDR_FA_SHIFT)
/* Flash continue read enable */
#define FLASH_CONTR_EN_SHIFT (31)
#define FLASH_CONTR_EN_MASK (1 << FLASH_CONTR_EN_SHIFT)
#define FLASH_CONTR_EN (1 << FLASH_CONTR_EN_SHIFT)
/* Flash divider */
#define FLASH_DIVR_FDIV_SHIFT (0) /* Flash divider */
#define FLASH_DIVR_FDIV_MASK (3 << FLASH_DIVR_FDIV_SHIFT)
#define FLASH_DIVR_FDIV_2 (0 << FLASH_DIVR_FDIV_SHIFT)
#define FLASH_DIVR_FDIV_3 (1 << FLASH_DIVR_FDIV_SHIFT)
#define FLASH_DIVR_FDIV_4 (2 << FLASH_DIVR_FDIV_SHIFT)
#define FLASH_DIVR_FDIV_STS_SHIFT (4) /* Flash divider status */
#define FLASH_DIVR_FDIV_STS_MASK (3 << FLASH_DIVR_FDIV_STS_SHIFT)
#define FLASH_DIVR_FDIV_STS_2 (0 << FLASH_DIVR_FDIV_STS_SHIFT)
#define FLASH_DIVR_FDIV_STS_3 (1 << FLASH_DIVR_FDIV_STS_SHIFT)
#define FLASH_DIVR_FDIV_STS_4 (2 << FLASH_DIVR_FDIV_STS_SHIFT)
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
int at32_flash_lock(void);
int at32_flash_unlock(void);
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_FLASH_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_I2C_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_I2C_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define AT32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define AT32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define AT32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define AT32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define AT32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
#define AT32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define AT32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
#define AT32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
#define AT32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
#define AT32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define AT32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses *******************************************************/
#if AT32_NI2C > 0
# define AT32_I2C1_CR1 (AT32_I2C1_BASE+AT32_I2C_CR1_OFFSET)
# define AT32_I2C1_CR2 (AT32_I2C1_BASE+AT32_I2C_CR2_OFFSET)
# define AT32_I2C1_OAR1 (AT32_I2C1_BASE+AT32_I2C_OAR1_OFFSET)
# define AT32_I2C1_OAR2 (AT32_I2C1_BASE+AT32_I2C_OAR2_OFFSET)
# define AT32_I2C1_TIMINGR (AT32_I2C1_BASE+AT32_I2C_TIMINGR_OFFSET)
# define AT32_I2C1_TIMEOUTR (AT32_I2C1_BASE+AT32_I2C_TIMEOUTR_OFFSET)
# define AT32_I2C1_ISR (AT32_I2C1_BASE+AT32_I2C_ISR_OFFSET)
# define AT32_I2C1_ICR (AT32_I2C1_BASE+AT32_I2C_ICR_OFFSET)
# define AT32_I2C1_PECR (AT32_I2C1_BASE+AT32_I2C_PECR_OFFSET)
# define AT32_I2C1_RXDR (AT32_I2C1_BASE+AT32_I2C_RXDR_OFFSET)
# define AT32_I2C1_TXDR (AT32_I2C1_BASE+AT32_I2C_TXDR_OFFSET)
#endif
#if AT32_NI2C > 1
# define AT32_I2C2_CR1 (AT32_I2C2_BASE+AT32_I2C_CR1_OFFSET)
# define AT32_I2C2_CR2 (AT32_I2C2_BASE+AT32_I2C_CR2_OFFSET)
# define AT32_I2C2_OAR1 (AT32_I2C2_BASE+AT32_I2C_OAR1_OFFSET)
# define AT32_I2C2_OAR2 (AT32_I2C2_BASE+AT32_I2C_OAR2_OFFSET)
# define AT32_I2C2_TIMINGR (AT32_I2C2_BASE+AT32_I2C_TIMINGR_OFFSET)
# define AT32_I2C2_TIMEOUTR (AT32_I2C2_BASE+AT32_I2C_TIMEOUTR_OFFSET)
# define AT32_I2C2_ISR (AT32_I2C2_BASE+AT32_I2C_ISR_OFFSET)
# define AT32_I2C2_ICR (AT32_I2C2_BASE+AT32_I2C_ICR_OFFSET)
# define AT32_I2C2_PECR (AT32_I2C2_BASE+AT32_I2C_PECR_OFFSET)
# define AT32_I2C2_RXDR (AT32_I2C2_BASE+AT32_I2C_RXDR_OFFSET)
# define AT32_I2C2_TXDR (AT32_I2C2_BASE+AT32_I2C_TXDR_OFFSET)
#endif
#if AT32_NI2C > 2
# define AT32_I2C3_CR1 (AT32_I2C3_BASE+AT32_I2C_CR1_OFFSET)
# define AT32_I2C3_CR2 (AT32_I2C3_BASE+AT32_I2C_CR2_OFFSET)
# define AT32_I2C3_OAR1 (AT32_I2C3_BASE+AT32_I2C_OAR1_OFFSET)
# define AT32_I2C3_OAR2 (AT32_I2C3_BASE+AT32_I2C_OAR2_OFFSET)
# define AT32_I2C3_TIMINGR (AT32_I2C3_BASE+AT32_I2C_TIMINGR_OFFSET)
# define AT32_I2C3_TIMEOUTR (AT32_I2C3_BASE+AT32_I2C_TIMEOUTR_OFFSET)
# define AT32_I2C3_ISR (AT32_I2C3_BASE+AT32_I2C_ISR_OFFSET)
# define AT32_I2C3_ICR (AT32_I2C3_BASE+AT32_I2C_ICR_OFFSET)
# define AT32_I2C3_PECR (AT32_I2C3_BASE+AT32_I2C_PECR_OFFSET)
# define AT32_I2C3_RXDR (AT32_I2C3_BASE+AT32_I2C_RXDR_OFFSET)
# define AT32_I2C3_TXDR (AT32_I2C3_BASE+AT32_I2C_TXDR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
/* Control register 2 */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
/* Own address register 1 */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_ONE (1 << 14) /* Bit 14: always keep on in software */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
/* Own address register 2 */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_PRESCH_SHIFT (24) /* Bits 24-27: Timing prescaler High*/
#define I2C_TIMINGR_PRESCH_MASK (15 << I2C_TIMINGR_PRESCH_SHIFT)
# define I2C_TIMINGR_PRESCH(n) (((n)-1) << I2C_TIMINGR_PRESCH_SHIFT) /* tPRESC = n x tI2CCLK */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler Low*/
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
/* Timeout register */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
/* Fields unique to the Interrupt and Status register */
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
/* Packet error checking register */
#define I2C_PECR_MASK (0xff)
/* Receive data register */
#define I2C_RXDR_MASK (0xff)
/* Transmit data register */
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_I2C_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_MEMORYMAP_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_memorymap.h"
#else
# error "Unsupported AT32 memory map"
#endif
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_PINMAP_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_AT32_AT32F43XX)
# include "hardware/at32f43xxx_pinmap.h"
#else
# error "No pinmap file for this AT32 chip"
#endif
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_PINMAP_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_PWR_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define AT32_PWC_CTRL_OFFSET 0x0000 /* Power control register */
#define AT32_PWC_CTRLSTS_OFFSET 0x0004 /* Power control/status register */
#define AT32_PWC_LDOOV_OFFSET 0x0010 /* Ldo output voltage select */
/* Register Addresses *******************************************************/
#define AT32_PWC_CTRL (AT32_PWC_BASE+AT32_PWC_CTRL_OFFSET)
#define AT32_PWC_CTRLSTS (AT32_PWC_BASE+AT32_PWC_CTRLSTS_OFFSET)
#define AT32_PWC_LDOOV (AT32_PWC_BASE+AT32_PWC_LDOOV_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Power control register */
#define PWC_CTRL_VRSEL (1 << 0) /* Voltage regulator state select when deepsleep mode */
#define PWC_CTRL_LPSEL (1 << 1) /* Low power mode select when Cortex™-M4F sleepdeep*/
#define PWC_CTRL_CLSWEF (1 << 2) /* Clear SWEF flag */
#define PWC_CTRL_CLSEF (1 << 3) /* Clear SEF flag */
#define PWC_CTRL_PVMEN (1 << 4) /* Power voltage monitoring enable */
#define PWC_CTRL_PVMSEL_SHIFT (5) /* Bits 7-5: PVD Level Selection */
#define PWC_CTRL_PVMSEL_MASK (7 << PWC_CTRL_PVMSEL_SHIFT) /* Power voltage monitoring boundary select */
# define PWC_CTRL_None (0 << PWC_CTRL_PVMSEL_SHIFT) /* 000: None */
# define PWC_CTRL_2p3V (1 << PWC_CTRL_PVMSEL_SHIFT) /* 001: 2.3V */
# define PWC_CTRL_2p4V (2 << PWC_CTRL_PVMSEL_SHIFT) /* 010: 2.4V */
# define PWC_CTRL_2p5V (3 << PWC_CTRL_PVMSEL_SHIFT) /* 011: 2.5V */
# define PWC_CTRL_2p6V (4 << PWC_CTRL_PVMSEL_SHIFT) /* 100: 2.6V */
# define PWC_CTRL_2p7V (5 << PWC_CTRL_PVMSEL_SHIFT) /* 101: 2.7V */
# define PWC_CTRL_2p8V (6 << PWC_CTRL_PVMSEL_SHIFT) /* 110: 2.8V */
# define PWC_CTRL_2p9V (7 << PWC_CTRL_PVMSEL_SHIFT) /* 111: 2.9V */
#define PWC_CTRL_BPWEN (1 << 8) /* Battery powered domain write enable */
/* Power control/status register */
#define PWC_CTRLSTS_SWEF (1 << 0) /* Standby wake-up event flag */
#define PWC_CTRLSTS_SEF (1 << 1) /* Standby mode entry flag */
#define PWC_CTRLSTS_PVMOF (1 << 2) /* Power voltage monitoring output flag */
#define PWC_CTRLSTS_SWPEN1 (1 << 8) /* Standby wake-up pin1 enable */
#define PWC_CTRLSTS_SWPEN2 (1 << 9) /* Standby wake-up pin2 enable */
/* Power ldo output register */
#define PWC_LDOOV_SEL_SHIFT (0)
#define PWC_LDOOV_SEL_MASK (7 << PWC_LDOOV_SEL_SHIFT) /* LDO output voltage select*/
# define PWC_LDOOV_1V0 (5 << PWC_LDOOV_SEL_SHIFT) /* 1.0V */
# define PWC_LDOOV_1V1 (4 << PWC_LDOOV_SEL_SHIFT) /* 1.1V */
# define PWC_LDOOV_1V3 (1 << PWC_LDOOV_SEL_SHIFT) /* 1.3V */
# define PWC_LDOOV_1V2 (0 << PWC_LDOOV_SEL_SHIFT) /* 1.2V */
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_PWR_H */

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/****************************************************************************
* arch/arm/src/at32/hardware/at32_rtcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AT32_HARDWARE_AT32_RTCC_H
#define __ARCH_ARM_SRC_AT32_HARDWARE_AT32_RTCC_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define AT32_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define AT32_RTC_DR_OFFSET 0x0004 /* RTC date register */
#define AT32_RTC_CR_OFFSET 0x0008 /* RTC control register */
#define AT32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
#define AT32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
#define AT32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
#define AT32_RTC_CALIBR_OFFSET 0x0018 /* RTC calibration register */
#define AT32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
#define AT32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
#define AT32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
#define AT32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
#define AT32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
#define AT32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
#define AT32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
#define AT32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
#define AT32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
#define AT32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */
#define AT32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
#define AT32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
#define AT32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
#define AT32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
#define AT32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
#define AT32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
#define AT32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
#define AT32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
#define AT32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
#define AT32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
#define AT32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
#define AT32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
#define AT32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
#define AT32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
#define AT32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
#define AT32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
#define AT32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
#define AT32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
#define AT32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
#define AT32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
#define AT32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
#define AT32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
#define AT32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
/* Register Addresses *******************************************************/
#define AT32_RTC_TR (AT32_ERTC_BASE+AT32_RTC_TR_OFFSET)
#define AT32_RTC_DR (AT32_ERTC_BASE+AT32_RTC_DR_OFFSET)
#define AT32_RTC_CR (AT32_ERTC_BASE+AT32_RTC_CR_OFFSET)
#define AT32_RTC_ISR (AT32_ERTC_BASE+AT32_RTC_ISR_OFFSET)
#define AT32_RTC_PRER (AT32_ERTC_BASE+AT32_RTC_PRER_OFFSET)
#define AT32_RTC_WUTR (AT32_ERTC_BASE+AT32_RTC_WUTR_OFFSET)
#define AT32_RTC_CALIBR (AT32_ERTC_BASE+AT32_RTC_CALIBR_OFFSET)
#define AT32_RTC_ALRMAR (AT32_ERTC_BASE+AT32_RTC_ALRMAR_OFFSET)
#define AT32_RTC_ALRMBR (AT32_ERTC_BASE+AT32_RTC_ALRMBR_OFFSET)
#define AT32_RTC_WPR (AT32_ERTC_BASE+AT32_RTC_WPR_OFFSET)
#define AT32_RTC_SSR (AT32_ERTC_BASE+AT32_RTC_SSR_OFFSET)
#define AT32_RTC_SHIFTR (AT32_ERTC_BASE+AT32_RTC_SHIFTR_OFFSET)
#define AT32_RTC_TSTR (AT32_ERTC_BASE+AT32_RTC_TSTR_OFFSET)
#define AT32_RTC_TSDR (AT32_ERTC_BASE+AT32_RTC_TSDR_OFFSET)
#define AT32_RTC_TSSSR (AT32_ERTC_BASE+AT32_RTC_TSSSR_OFFSET)
#define AT32_RTC_CALR (AT32_ERTC_BASE+AT32_RTC_CALR_OFFSET)
#define AT32_RTC_TAFCR (AT32_ERTC_BASE+AT32_RTC_TAFCR_OFFSET)
#define AT32_RTC_ALRMASSR (AT32_ERTC_BASE+AT32_RTC_ALRMASSR_OFFSET)
#define AT32_RTC_ALRMBSSR (AT32_ERTC_BASE+AT32_RTC_ALRMBSSR_OFFSET)
#define AT32_RTC_BKR(n) (AT32_ERTC_BASE+AT32_RTC_BKR_OFFSET(n))
#define AT32_RTC_BK0R (AT32_ERTC_BASE+AT32_RTC_BK0R_OFFSET)
#define AT32_RTC_BK1R (AT32_ERTC_BASE+AT32_RTC_BK1R_OFFSET)
#define AT32_RTC_BK2R (AT32_ERTC_BASE+AT32_RTC_BK2R_OFFSET)
#define AT32_RTC_BK3R (AT32_ERTC_BASE+AT32_RTC_BK3R_OFFSET)
#define AT32_RTC_BK4R (AT32_ERTC_BASE+AT32_RTC_BK4R_OFFSET)
#define AT32_RTC_BK5R (AT32_ERTC_BASE+AT32_RTC_BK5R_OFFSET)
#define AT32_RTC_BK6R (AT32_ERTC_BASE+AT32_RTC_BK6R_OFFSET)
#define AT32_RTC_BK7R (AT32_ERTC_BASE+AT32_RTC_BK7R_OFFSET)
#define AT32_RTC_BK8R (AT32_ERTC_BASE+AT32_RTC_BK8R_OFFSET)
#define AT32_RTC_BK9R (AT32_ERTC_BASE+AT32_RTC_BK9R_OFFSET)
#define AT32_RTC_BK10R (AT32_ERTC_BASE+AT32_RTC_BK10R_OFFSET)
#define AT32_RTC_BK11R (AT32_ERTC_BASE+AT32_RTC_BK11R_OFFSET)
#define AT32_RTC_BK12R (AT32_ERTC_BASE+AT32_RTC_BK12R_OFFSET)
#define AT32_RTC_BK13R (AT32_ERTC_BASE+AT32_RTC_BK13R_OFFSET)
#define AT32_RTC_BK14R (AT32_ERTC_BASE+AT32_RTC_BK14R_OFFSET)
#define AT32_RTC_BK15R (AT32_ERTC_BASE+AT32_RTC_BK15R_OFFSET)
#define AT32_RTC_BK16R (AT32_ERTC_BASE+AT32_RTC_BK16R_OFFSET)
#define AT32_RTC_BK17R (AT32_ERTC_BASE+AT32_RTC_BK17R_OFFSET)
#define AT32_RTC_BK18R (AT32_ERTC_BASE+AT32_RTC_BK18R_OFFSET)
#define AT32_RTC_BK19R (AT32_ERTC_BASE+AT32_RTC_BK19R_OFFSET)
#define AT32_RTC_BKCOUNT 20
/* Register Bitfield Definitions ********************************************/
/* RTC time register */
#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT)
#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)
#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT)
#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT)
#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */
#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT)
#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT)
#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
#define RTC_TR_RESERVED_BITS (0xff808080)
/* RTC date register */
#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT)
#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT)
#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT)
#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT)
#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */
#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT)
#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT)
#define RTC_DR_RESERVED_BITS (0xff0000c0)
/* RTC control register */
#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */
#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT)
# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */
#define RTC_CR_DCE (1 << 7) /* Bit 7: Coarse digital calibration enable */
#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */
#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */
#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */
#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */
#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */
#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */
#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */
#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */
#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */
#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */
#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */
#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */
#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */
#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */
#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT)
# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
/* RTC initialization and status register */
#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */
#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */
#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */
#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */
#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */
#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */
#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */
#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */
#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */
#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */
#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */
#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */
#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */
#define RTC_ISR_ALLFLAGS (0x00017fff)
/* RTC prescaler register */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
/* RTC wakeup timer register */
#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */
/* RTC calibration register */
#ifndef CONFIG_AT32_AT32F30XX
# define RTC_CALIBR_DCS (1 << 7) /* Bit 7 Digital calibration sign */
# define RTC_CALIBR_DC_SHIFT (0) /* Bits 4:0 0-4: Digital calibration */
# define RTC_CALIBR_DC_MASK (31 << RTC_CALIBR_DC_SHIFT)
# define RTC_CALIBR_DC(n) (((n) >> 2) << RTC_CALIBR_DC_SHIFT) /* n= 0, 4, 8, ... 126 */
#endif
/* RTC alarm A/B registers */
#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT)
#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT)
#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */
#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT)
#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT)
#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */
#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT)
#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT)
#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */
#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */
#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */
#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT)
#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */
#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT)
#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */
#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */
/* RTC write protection register */
#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */
/* RTC sub second register */
#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */
/* RTC shift control register */
#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */
#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT)
#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */
/* RTC time stamp time register */
#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT)
#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT)
#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT)
#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT)
#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT)
#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT)
#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */
/* RTC time stamp date register */
#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */
#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT)
#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT)
#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
#define RTC_TSDR_MU_MASK (15 << RTC_TSDR_MU_SHIFT)
#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT)
/* RTC timestamp sub second register */
#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */
/* RTC calibration register */
#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */
#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT)
#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */
#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */
#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */
/* RTC tamper and alternate function configuration register */
#define RTC_TAFCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */
#define RTC_TAFCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */
#define RTC_TAFCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */
#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT)
# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV8192 (2 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV4096 (3 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV2048 (4 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT)
#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
#define RTC_TAFCR_TAMPPRCH_MASK (3 << RTC_TAFCR_TAMPPRCH_SHIFT)
# define RTC_TAFCR_TAMPPRCH_1CYCLE (0 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */
# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */
#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */
#define RTC_TAFCR_PC14VALUE (1 << 20) /* Bit 20: PC14 value */
#define RTC_TAFCR_PC14MODE (1 << 21) /* Bit 21: PC14 mode */
#define RTC_TAFCR_PC15VALUE (1 << 22) /* Bit 22: PC15 value */
#define RTC_TAFCR_PC15MODE (1 << 23) /* Bit 23: PC15 mode */
/* RTC alarm A/B sub second register */
#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_AT32_HARDWARE_AT32_RTCC_H */

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