From 188a7ce990f3a12e94f2afc9ea6e09db72c65c54 Mon Sep 17 00:00:00 2001 From: hujun5 Date: Tue, 17 Dec 2024 09:48:01 +0800 Subject: [PATCH] gpio: use small lock to protect configgpio reason: We would like to replace the critical section with a small lock. Signed-off-by: hujun5 --- arch/arm/src/at32/at32_gpio.c | 11 +++++++++-- arch/arm/src/eoss3/eoss3_gpio.c | 11 +++++++---- arch/arm/src/nuc1xx/nuc_gpio.c | 11 +++++++++-- arch/arm/src/sam34/sam4l_gpio.c | 7 +++++-- arch/arm/src/sam34/sam_gpio.c | 11 +++++++---- arch/arm/src/samv7/sam_gpio.c | 7 +++++-- arch/arm/src/stm32/stm32_gpio.c | 19 +++++++++++++------ arch/arm/src/stm32f0l0g0/stm32_gpio.c | 11 +++++++++-- arch/arm/src/stm32f7/stm32_gpio.c | 11 +++++++++-- arch/arm/src/stm32h5/stm32_gpio.c | 11 +++++++++-- arch/arm/src/stm32h7/stm32_gpio.c | 11 +++++++++-- arch/arm/src/stm32l4/stm32l4_gpio.c | 10 ++++++++-- arch/arm/src/stm32l5/stm32l5_gpio.c | 11 +++++++++-- arch/arm/src/stm32u5/stm32_gpio.c | 11 +++++++++-- arch/arm/src/stm32wb/stm32wb_gpio.c | 12 ++++++++++-- arch/arm/src/stm32wl5/stm32wl5_gpio.c | 11 +++++++++-- arch/arm/src/tiva/cc13xx/cc13xx_gpio.c | 6 ++++-- arch/arm/src/tiva/lm/lm3s_gpio.c | 7 +++++-- arch/arm/src/tiva/lm/lm4f_gpio.c | 7 +++++-- arch/arm/src/tiva/tm4c/tm4c_gpio.c | 6 ++++-- arch/hc/src/m9s12/m9s12_gpio.c | 7 +++++-- arch/mips/src/pic32mx/pic32mx_gpio.c | 7 +++++-- arch/mips/src/pic32mz/pic32mz_gpio.c | 10 ++++++++-- arch/risc-v/src/bl602/bl602_gpio.c | 12 ++++++++++-- 24 files changed, 182 insertions(+), 56 deletions(-) diff --git a/arch/arm/src/at32/at32_gpio.c b/arch/arm/src/at32/at32_gpio.c index e667f251a6..639909335d 100644 --- a/arch/arm/src/at32/at32_gpio.c +++ b/arch/arm/src/at32/at32_gpio.c @@ -32,12 +32,19 @@ #include #include #include +#include #include "arm_internal.h" #include "chip.h" #include "at32_syscfg.h" #include "at32_gpio.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -199,7 +206,7 @@ int at32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Determine the alternate function (Only alternate function pins) */ @@ -355,7 +362,7 @@ int at32_configgpio(uint32_t cfgset) putreg32(regval, regaddr); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } #endif diff --git a/arch/arm/src/eoss3/eoss3_gpio.c b/arch/arm/src/eoss3/eoss3_gpio.c index 5db95cf575..163d10c5dd 100644 --- a/arch/arm/src/eoss3/eoss3_gpio.c +++ b/arch/arm/src/eoss3/eoss3_gpio.c @@ -29,6 +29,7 @@ #include #include +#include #include "arm_internal.h" #include "chip.h" @@ -57,6 +58,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -82,7 +85,7 @@ int eoss3_configgpio(gpio_pinset_t cfgset) uint16_t sel_idx = \ (input & EOSS3_PAD_SEL_IDX_MASK) >> EOSS3_PAD_SEL_IDX_SHIFT; - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(&g_configgpio_lock); /* Check select index, if it is 0 we are not working with an input */ @@ -111,7 +114,7 @@ int eoss3_configgpio(gpio_pinset_t cfgset) } putreg32(ctrl, EOSS3_PAD_X_CTRL(pad)); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } @@ -141,7 +144,7 @@ void eoss3_gpiowrite(gpio_pinset_t cfgset, bool value) uint8_t iobit = (cfgset & GPIO_REG_BIT_MASK) >> GPIO_REG_BIT_SHIFT; if (cfgset & GPIO_REG_EN_MASK) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(&g_configgpio_lock); if (value) { putreg32( @@ -155,7 +158,7 @@ void eoss3_gpiowrite(gpio_pinset_t cfgset, bool value) EOSS3_MISC_IO_OUTPUT); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); } } diff --git a/arch/arm/src/nuc1xx/nuc_gpio.c b/arch/arm/src/nuc1xx/nuc_gpio.c index ca0554b2bf..80fe7e302d 100644 --- a/arch/arm/src/nuc1xx/nuc_gpio.c +++ b/arch/arm/src/nuc1xx/nuc_gpio.c @@ -31,6 +31,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -43,6 +44,12 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -240,7 +247,7 @@ void nuc_gpiowrite(gpio_cfgset_t pinset, bool value) /* Disable interrupts -- the following operations must be atomic */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Allow writing only to the selected pin in the DOUT register */ @@ -249,7 +256,7 @@ void nuc_gpiowrite(gpio_cfgset_t pinset, bool value) /* Set the pin to the selected value and re-enable interrupts */ putreg32(((uint32_t)value << pin), base + NUC_GPIO_DOUT_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); #endif } diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c index 5a06ad87ad..7fc6e94bd1 100644 --- a/arch/arm/src/sam34/sam4l_gpio.c +++ b/arch/arm/src/sam34/sam4l_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -45,6 +46,8 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + static const char g_portchar[4] = { 'A', 'B', 'C', 'D' @@ -529,7 +532,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); @@ -559,7 +562,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET)); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } #endif diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c index 4e474235b5..3c5efa5d6d 100644 --- a/arch/arm/src/sam34/sam_gpio.c +++ b/arch/arm/src/sam34/sam_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -55,6 +56,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + #ifdef CONFIG_DEBUG_GPIO_INFO static const char g_portchar[4] = { @@ -476,7 +479,7 @@ int sam_configgpio(gpio_pinset_t cfgset) /* Disable interrupts to prohibit re-entrance. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Enable writing to GPIO registers */ @@ -511,7 +514,7 @@ int sam_configgpio(gpio_pinset_t cfgset) /* Disable writing to GPIO registers */ putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return ret; } @@ -588,7 +591,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); @@ -646,7 +649,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) #endif #endif - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } #endif diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c index bebe82a0fe..19b6708b74 100644 --- a/arch/arm/src/samv7/sam_gpio.c +++ b/arch/arm/src/samv7/sam_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -75,6 +76,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + #ifdef CONFIG_DEBUG_GPIO_INFO static const char g_portchar[SAMV7_NPIO] = { @@ -497,7 +500,7 @@ int sam_configgpio(gpio_pinset_t cfgset) /* Disable interrupts to prohibit re-entrance. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Enable writing to GPIO registers */ @@ -606,7 +609,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c index 4c02cd5535..05b6c4191f 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/stm32/stm32_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include "arm_internal.h" #include "chip.h" @@ -43,6 +44,12 @@ # pragma message "CONFIG_STM32_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -299,7 +306,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Decode the mode and configuration */ @@ -339,7 +346,7 @@ int stm32_configgpio(uint32_t cfgset) { /* Its an alternate function pin... we can return early */ - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } } @@ -366,7 +373,7 @@ int stm32_configgpio(uint32_t cfgset) { /* Neither... we can return early */ - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } } @@ -393,7 +400,7 @@ int stm32_configgpio(uint32_t cfgset) regval |= (1 << pin); putreg32(regval, regaddr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } #endif @@ -468,7 +475,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Determine the alternate function (Only alternate function pins) */ @@ -684,7 +691,7 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, regaddr); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c index ce864c3eef..0113510a03 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.c @@ -34,6 +34,7 @@ #include #include +#include #include "arm_internal.h" #include "chip.h" @@ -49,6 +50,12 @@ # pragma message "CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -178,7 +185,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -339,7 +346,7 @@ int stm32_configgpio(uint32_t cfgset) #endif } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 53cfe5b2f2..77ae862b1b 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -34,6 +34,7 @@ #include #include +#include #include "arm_internal.h" #include "hardware/stm32_syscfg.h" @@ -51,6 +52,12 @@ # pragma message "CONFIG_STM32F7_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -176,7 +183,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Determine the alternate function (Only alternate function pins) */ @@ -353,7 +360,7 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, regaddr); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32h5/stm32_gpio.c b/arch/arm/src/stm32h5/stm32_gpio.c index 1a2739745c..30fda52dbf 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.c +++ b/arch/arm/src/stm32h5/stm32_gpio.c @@ -34,11 +34,18 @@ #include #include +#include #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -177,7 +184,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -290,7 +297,7 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 81e2098368..ea6fc18ddc 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -34,6 +34,7 @@ #include #include +#include #include "arm_internal.h" #include "hardware/stm32_syscfg.h" @@ -52,6 +53,12 @@ # pragma message "CONFIG_STM32H7_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -208,7 +215,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Determine the alternate function (Only alternate function pins) */ @@ -386,7 +393,7 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, regaddr); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 9a1cba4837..13901fe587 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -44,6 +45,11 @@ #if defined(CONFIG_STM32L4_USE_LEGACY_PINMAP) # pragma message "CONFIG_STM32L4_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; /**************************************************************************** * Public Data @@ -195,7 +201,7 @@ int stm32l4_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -356,7 +362,7 @@ int stm32l4_configgpio(uint32_t cfgset) } #endif - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index ac33822c75..0bbaecf6fa 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -34,6 +34,7 @@ #include #include +#include #include "arm_internal.h" #include "chip.h" @@ -41,6 +42,12 @@ #include "hardware/stm32l5_syscfg.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -183,7 +190,7 @@ int stm32l5_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -296,7 +303,7 @@ int stm32l5_configgpio(uint32_t cfgset) putreg32(regval, base + STM32L5_GPIO_OTYPER_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32u5/stm32_gpio.c b/arch/arm/src/stm32u5/stm32_gpio.c index 300f1a7f4d..8150df48c0 100644 --- a/arch/arm/src/stm32u5/stm32_gpio.c +++ b/arch/arm/src/stm32u5/stm32_gpio.c @@ -34,6 +34,7 @@ #include #include +#include #include "arm_internal.h" #include "chip.h" @@ -41,6 +42,12 @@ #include "hardware/stm32_syscfg.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -182,7 +189,7 @@ int stm32_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -295,7 +302,7 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index 525a13dd8d..4f3eca1daf 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -32,6 +32,8 @@ #include #include +#include + #include "arm_internal.h" #include "chip.h" #include "stm32wb_gpio.h" @@ -42,6 +44,12 @@ # pragma message "CONFIG_STM32WB_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py" #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -160,7 +168,7 @@ int stm32wb_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -296,7 +304,7 @@ int stm32wb_configgpio(uint32_t cfgset) putreg32(regval, regaddr); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index acfd51ac8f..671ff89638 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -34,6 +34,7 @@ #include #include +#include #include "arm_internal.h" @@ -42,6 +43,12 @@ #include "hardware/stm32wl5_syscfg.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -168,7 +175,7 @@ int stm32wl5_configgpio(uint32_t cfgset) * exclusive access to all of the GPIO configuration registers. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Now apply the configuration to the mode register */ @@ -305,7 +312,7 @@ int stm32wl5_configgpio(uint32_t cfgset) putreg32(regval, regaddr); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_gpio.c b/arch/arm/src/tiva/cc13xx/cc13xx_gpio.c index fd7c3161e2..604b4f5323 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_gpio.c +++ b/arch/arm/src/tiva/cc13xx/cc13xx_gpio.c @@ -41,6 +41,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -64,7 +66,7 @@ int tiva_configgpio(pinconfig_t pinconfig) /* The following requires exclusive access to the GPIO registers */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_configgpio_lock); #ifdef CONFIG_TIVA_GPIO_IRQS /* Mask and clear any pending GPIO interrupt */ @@ -123,7 +125,7 @@ int tiva_configgpio(pinconfig_t pinconfig) putreg32(regval, TIVA_GPIO_DOE); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/tiva/lm/lm3s_gpio.c b/arch/arm/src/tiva/lm/lm3s_gpio.c index 41fa2f1fd4..4954892287 100644 --- a/arch/arm/src/tiva/lm/lm3s_gpio.c +++ b/arch/arm/src/tiva/lm/lm3s_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include "arm_internal.h" #include "tiva_enablepwr.h" @@ -120,6 +121,8 @@ struct gpio_func_s * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + static const struct gpio_func_s g_funcbits[] = { {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ @@ -717,7 +720,7 @@ int tiva_configgpio(pinconfig_t pinconfig) /* The following requires exclusive access to the GPIO registers */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Enable power and clocking for this GPIO peripheral. Applies both power * and clocking to the GPIO peripheral, bringing it a fully functional @@ -767,7 +770,7 @@ int tiva_configgpio(pinconfig_t pinconfig) } #endif - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/tiva/lm/lm4f_gpio.c b/arch/arm/src/tiva/lm/lm4f_gpio.c index 1b1735eb24..2efc584b70 100644 --- a/arch/arm/src/tiva/lm/lm4f_gpio.c +++ b/arch/arm/src/tiva/lm/lm4f_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include "arm_internal.h" #include "tiva_enablepwr.h" @@ -120,6 +121,8 @@ struct gpio_func_s * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + static const struct gpio_func_s g_funcbits[] = { {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ @@ -741,7 +744,7 @@ int tiva_configgpio(uint32_t pinconfig) /* The following requires exclusive access to the GPIO registers */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Enable power and clocking for this GPIO peripheral. Applies both power * and clocking to the GPIO peripheral, bringing it a fully functional @@ -787,7 +790,7 @@ int tiva_configgpio(uint32_t pinconfig) } #endif - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/arm/src/tiva/tm4c/tm4c_gpio.c b/arch/arm/src/tiva/tm4c/tm4c_gpio.c index b191566ec3..268278646f 100644 --- a/arch/arm/src/tiva/tm4c/tm4c_gpio.c +++ b/arch/arm/src/tiva/tm4c/tm4c_gpio.c @@ -120,6 +120,8 @@ struct gpio_func_s * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + static const struct gpio_func_s g_funcbits[] = { {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ @@ -788,7 +790,7 @@ int tiva_configgpio(pinconfig_t pinconfig) /* The following requires exclusive access to the GPIO registers */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Enable power and clocking for this GPIO peripheral. * @@ -839,7 +841,7 @@ int tiva_configgpio(pinconfig_t pinconfig) } #endif - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/hc/src/m9s12/m9s12_gpio.c b/arch/hc/src/m9s12/m9s12_gpio.c index bea9177010..4333ce8817 100644 --- a/arch/hc/src/m9s12/m9s12_gpio.c +++ b/arch/hc/src/m9s12/m9s12_gpio.c @@ -33,6 +33,7 @@ #include #include +#include #include "hc_internal.h" #include "m9s12.h" @@ -135,6 +136,8 @@ struct mebi_portaddr_s * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + static const struct mebi_portaddr_s mebi_portaddr[HCS12_MEBI_NPORTS] = { {HCS12_MEBI_PORTA, HCS12_MEBI_DDRA}, /* Port A */ @@ -443,7 +446,7 @@ void hcs12_gpiowrite(uint16_t pinset, bool value) { uint8_t portndx = HCS12_PORTNDX(pinset); uint8_t pin = HCS12_PIN(pinset); - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(&g_configgpio_lock); DEBUGASSERT((pinset & GPIO_DIRECTION) == GPIO_OUTPUT); if (HCS12_PIMPORT(pinset)) @@ -455,7 +458,7 @@ void hcs12_gpiowrite(uint16_t pinset, bool value) mebi_gpiowrite(portndx, pin, value); } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); } /**************************************************************************** diff --git a/arch/mips/src/pic32mx/pic32mx_gpio.c b/arch/mips/src/pic32mx/pic32mx_gpio.c index 864aa7982c..1aaa6721ca 100644 --- a/arch/mips/src/pic32mx/pic32mx_gpio.c +++ b/arch/mips/src/pic32mx/pic32mx_gpio.c @@ -32,6 +32,7 @@ #include #include +#include #include #include "mips_internal.h" @@ -51,6 +52,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + static const uintptr_t g_gpiobase[CHIP_NPORTS] = { PIC32MX_IOPORTA_K1BASE @@ -150,7 +153,7 @@ int pic32mx_configgpio(uint16_t cfgset) /* Is this an input or an output? */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); if (pic32mx_output(cfgset)) { /* Not analog */ @@ -206,7 +209,7 @@ int pic32mx_configgpio(uint16_t cfgset) #endif } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/mips/src/pic32mz/pic32mz_gpio.c b/arch/mips/src/pic32mz/pic32mz_gpio.c index 3086438d08..3baa81d68b 100644 --- a/arch/mips/src/pic32mz/pic32mz_gpio.c +++ b/arch/mips/src/pic32mz/pic32mz_gpio.c @@ -45,6 +45,12 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -173,7 +179,7 @@ int pic32mz_configgpio(pinset_t cfgset) base = g_gpiobase[port]; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_configgpio_lock); /* Is Slew Rate control enabled? */ @@ -243,7 +249,7 @@ int pic32mz_configgpio(pinset_t cfgset) } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } diff --git a/arch/risc-v/src/bl602/bl602_gpio.c b/arch/risc-v/src/bl602/bl602_gpio.c index 6bd074cb3f..e9b41b070e 100644 --- a/arch/risc-v/src/bl602/bl602_gpio.c +++ b/arch/risc-v/src/bl602/bl602_gpio.c @@ -26,10 +26,18 @@ #include +#include + #include "riscv_internal.h" #include "hardware/bl602_glb.h" #include "bl602_gpio.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -185,14 +193,14 @@ int bl602_config_uart_sel(gpio_pinset_t pinset, uint8_t sig_sel) } sel_idx = pin % 8; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_configgpio_lock); reg = getreg32(BL602_UART_SIG_SEL_0); reg &= ~(0xf << (sel_idx * 4)); reg |= sig_sel << (sel_idx * 4); putreg32(reg, BL602_UART_SIG_SEL_0); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; }