arch/arm/src/stm32l4: Add initial support to STM32L4+ chips
This commit is contained in:
Juha Niskanen
Gregory Nutt
parent
45e61f1138
commit
2589fc943e
36 changed files with 4059 additions and 63 deletions
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@ -78,7 +78,11 @@
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* selection.
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*/
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#if defined(CONFIG_STM32L4_STM32L496XX)
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \
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@ -99,6 +103,37 @@
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# error "Unsupported STM32L4 chip"
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#endif
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 0 /* No QuadSPI1 */
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# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NSWPMI 0 /* No SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4XR */
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#if defined(CONFIG_STM32L4_STM32L4X5)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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@ -82,6 +82,8 @@
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# include <arch/stm32l4/stm32l4x5xx_irq.h>
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#elif defined(CONFIG_STM32L4_STM32L4X6)
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# include <arch/stm32l4/stm32l4x6xx_irq.h>
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#elif defined(CONFIG_STM32L4_STM32L4XR)
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# include <arch/stm32l4/stm32l4xrxx_irq.h>
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#else
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# error "Unsupported STM32 L4 chip"
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#endif
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@ -55,7 +55,7 @@
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
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* nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
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*
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* External interrupts (vectors >= 16)
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*/
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@ -53,7 +53,7 @@
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
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* nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
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*
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* External interrupts (vectors >= 16)
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*/
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193
arch/arm/include/stm32l4/stm32l4xrxx_irq.h
Normal file
193
arch/arm/include/stm32l4/stm32l4xrxx_irq.h
Normal file
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@ -0,0 +1,193 @@
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/****************************************************************************************************
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* arch/arm/include/stm32l4/stm32l4xrxx_irq.h
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*
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* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
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* Author: Sebastien Lorquet <sebastien@lorquet.fr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
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#ifndef __ARCH_ARM_INCLUDE_STM32L4_STM32L4XRXX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32L4_STM32L4XRXX_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
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*
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* External interrupts (vectors >= 16)
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*/
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#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
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#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
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#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
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#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
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#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
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#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
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#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
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#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
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#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
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#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
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#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
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#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
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#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
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#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
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#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
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#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
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#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
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#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
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#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
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#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
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#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
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#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
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#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
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#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
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#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
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#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
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#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
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#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
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#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
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#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
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#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
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#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
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#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
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#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
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#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
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#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
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#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
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#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
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#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
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#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
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#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
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#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
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#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
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#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
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#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
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#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
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/* Reserved */ /* 47: ADC3 global interrupt */
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#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
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#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
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#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
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#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
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#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
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#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
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#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
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#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
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#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
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#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
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#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
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#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
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#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
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#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
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#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
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#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
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#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
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#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
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#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
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#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
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#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
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#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
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#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
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#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
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#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */
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#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
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#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
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#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
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#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
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#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */
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#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
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#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */
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#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
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#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
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#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
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#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
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#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
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#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
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#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
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/* Reserved */ /* 86-89: CAN2 */
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#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
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#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */
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#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */
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#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */
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#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
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#define STM32L4_IRQ_NEXTINTS 95
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/* EXTI interrupts (Do not use IRQ numbers) */
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#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32L4_STM32L4XRXX_IRQ_H */
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@ -420,6 +420,14 @@ config ARCH_CHIP_STM32L4A6AG
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---help---
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STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM
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config ARCH_CHIP_STM32L4R9AI
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bool "STM32L4R9AI"
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select STM32L4_STM32L4R9XX
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select STM32L4_FLASH_CONFIG_I
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select STM32L4_IO_CONFIG_A
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---help---
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STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM
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endchoice # STM32 L4 Chip Selection
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# Chip product lines
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|
|
@ -487,6 +495,7 @@ config STM32L4_STM32L4X5
|
|||
select STM32L4_HAVE_SDMMC1
|
||||
select STM32L4_HAVE_OTGFS
|
||||
select STM32L4_HAVE_DFSDM1
|
||||
select STM32L4_HAVE_QSPI
|
||||
|
||||
config STM32L4_STM32L4X6
|
||||
# STM32L4x6 (documented in RM0351)
|
||||
|
|
@ -516,6 +525,37 @@ config STM32L4_STM32L4X6
|
|||
select STM32L4_HAVE_SDMMC1
|
||||
select STM32L4_HAVE_OTGFS
|
||||
select STM32L4_HAVE_LCD
|
||||
select STM32L4_HAVE_QSPI
|
||||
|
||||
config STM32L4_STM32L4XR
|
||||
# STM32L4+ (documented in RM0432)
|
||||
bool
|
||||
default n
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32L4_HAVE_USART1
|
||||
select STM32L4_HAVE_USART2
|
||||
select STM32L4_HAVE_USART3
|
||||
select STM32L4_HAVE_UART4
|
||||
select STM32L4_HAVE_UART5
|
||||
select STM32L4_HAVE_ADC2
|
||||
select STM32L4_HAVE_DAC2
|
||||
select STM32L4_HAVE_FSMC
|
||||
select STM32L4_HAVE_TIM3
|
||||
select STM32L4_HAVE_TIM4
|
||||
select STM32L4_HAVE_TIM5
|
||||
select STM32L4_HAVE_TIM7
|
||||
select STM32L4_HAVE_TIM8
|
||||
select STM32L4_HAVE_TIM17
|
||||
select STM32L4_HAVE_LPTIM1
|
||||
select STM32L4_HAVE_LPTIM2
|
||||
select STM32L4_HAVE_COMP
|
||||
select STM32L4_HAVE_SAI1
|
||||
select STM32L4_HAVE_SAI2
|
||||
select STM32L4_HAVE_SDMMC1
|
||||
select STM32L4_HAVE_OTGFS
|
||||
select STM32L4_HAVE_I2C4
|
||||
select STM32L4_HAVE_DCMI
|
||||
select STM32L4_HAVE_DFSDM1
|
||||
|
||||
# Chip subfamilies:
|
||||
|
||||
|
|
@ -627,6 +667,48 @@ config STM32L4_STM32L4A6XX
|
|||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
config STM32L4_STM32L4R5XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
|
||||
config STM32L4_STM32L4S5XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
config STM32L4_STM32L4R7XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
|
||||
config STM32L4_STM32L4S7XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
config STM32L4_STM32L4R9XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
select STM32L4_HAVE_LTDC
|
||||
|
||||
config STM32L4_STM32L4S9XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
select STM32L4_HAVE_LTDC
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
choice
|
||||
prompt "Override Flash Size Designator"
|
||||
depends on ARCH_CHIP_STM32L4
|
||||
|
|
@ -640,6 +722,7 @@ choice
|
|||
C 256
|
||||
E 512
|
||||
G 1024
|
||||
I 2048
|
||||
|
||||
This configuration option defaults to using the configuration based on that designator
|
||||
or the default smaller size if there is no last character designator is present in the
|
||||
|
|
@ -668,6 +751,9 @@ config STM32L4_FLASH_OVERRIDE_E
|
|||
config STM32L4_FLASH_OVERRIDE_G
|
||||
bool "G 1024 KB"
|
||||
|
||||
config STM32L4_FLASH_OVERRIDE_I
|
||||
bool "I 2048 KB"
|
||||
|
||||
endchoice # "Override Flash Size Designator"
|
||||
|
||||
# Flash configurations
|
||||
|
|
@ -691,6 +777,11 @@ config STM32L4_FLASH_CONFIG_G
|
|||
default n
|
||||
depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6
|
||||
|
||||
config STM32L4_FLASH_CONFIG_I
|
||||
bool
|
||||
default n
|
||||
depends on STM32L4_STM32L4XR
|
||||
|
||||
# Pin/package configurations
|
||||
|
||||
config STM32L4_IO_CONFIG_K
|
||||
|
|
@ -893,6 +984,10 @@ config STM32L4_HAVE_UART5
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32L4_HAVE_QSPI
|
||||
bool
|
||||
default n
|
||||
|
||||
# These "hidden" settings are the OR of individual peripheral selections
|
||||
# indicating that the general capability is required.
|
||||
|
||||
|
|
@ -1024,6 +1119,7 @@ config STM32L4_FSMC
|
|||
config STM32L4_QSPI
|
||||
bool "QuadSPI"
|
||||
default n
|
||||
depends on STM32L4_HAVE_QSPI
|
||||
---help---
|
||||
The STM32L4 QSPI block is intended to support one serial NOR flash device
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Most code is copied and adapted from the STM32 and STM32F7 ports.
|
|||
|
||||
The various supported STM32L4 families are:
|
||||
|
||||
-------------------------------------------------------------
|
||||
-----------------------------------------------------------------
|
||||
| NuttX config | Manual | Chips
|
||||
|
|
||||
| Not supported | RM0392 | STM32L471xx
|
||||
|
|
@ -24,8 +24,8 @@ The various supported STM32L4 families are:
|
|||
| STM32L4_STM32L4X6 | RM0351 | STM32L476xx, STM32L486xx,
|
||||
| STM32L496xx, STM32L4A6xx
|
||||
|
|
||||
| Not supported | RM0432 | STM32L4Rxxx, STM32L4Sxxx
|
||||
-------------------------------------------------------------
|
||||
| STM32L4_STM32L4XR | RM0432 | STM32L4Rxxx, STM32L4Sxxx (STM32L4+)
|
||||
------------------------------------------------------------------
|
||||
|
||||
[*]: Please avoid depending on CONFIG_STM32L4_STM32L4X1 and
|
||||
CONFIG_STM32L4_STM32L4X2 as the MCUs are of the same subfamily
|
||||
|
|
@ -91,3 +91,13 @@ SAIPLL : works (PLL For Digital Audio interfaces, and other things)
|
|||
SAI : There is some code (Digital Audio interfaces, I2S, SPDIF, etc)
|
||||
HASH : TODO (SHA-1, SHA-224, SHA-256, HMAC)
|
||||
DCMI : TODO (Digital Camera interfaces)
|
||||
|
||||
New peripherals only in STM32L4+:
|
||||
|
||||
DMAMUX1 : TODO
|
||||
DSI : TODO
|
||||
GFXMMU : TODO
|
||||
LTDC : TODO
|
||||
OCTOSPI : TODO
|
||||
OCTOSPIIOM : TODO
|
||||
|
||||
|
|
|
|||
|
|
@ -67,10 +67,12 @@
|
|||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_G)
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_G) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_I)
|
||||
# define CONFIG_STM32L4_FLASH_OVERRIDE_E
|
||||
# warning "Flash size not defined defaulting to 512KiB (E)"
|
||||
#endif
|
||||
|
|
@ -82,6 +84,7 @@
|
|||
# undef CONFIG_STM32L4_FLASH_CONFIG_C
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_E
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_G
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_I
|
||||
# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_B
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C)
|
||||
|
|
@ -90,6 +93,8 @@
|
|||
# define CONFIG_STM32L4_FLASH_CONFIG_E
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_G
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_I)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_I
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
|
@ -107,6 +112,9 @@
|
|||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB */
|
||||
# define STM32L4_FLASH_NPAGES 256
|
||||
# define STM32L4_FLASH_PAGESIZE 8192
|
||||
#else
|
||||
# error "unknown flash configuration!"
|
||||
#endif
|
||||
|
|
@ -129,7 +137,7 @@
|
|||
#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c
|
||||
|
|
@ -150,7 +158,7 @@
|
|||
#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET)
|
||||
|
|
@ -205,7 +213,7 @@
|
|||
#define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT)
|
||||
#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */
|
||||
# define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */
|
||||
#endif
|
||||
|
|
@ -223,7 +231,7 @@
|
|||
|
||||
#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 8-15: Read protect */
|
||||
#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */
|
||||
#endif
|
||||
#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
|
||||
|
|
@ -240,14 +248,14 @@
|
|||
#define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
|
||||
#define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
|
||||
#define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */
|
||||
# define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */
|
||||
#endif
|
||||
#define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
|
||||
#define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
|
||||
#define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
|
||||
# define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@
|
|||
/* STM32L4XXX Address Blocks ********************************************************/
|
||||
|
||||
#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (96k or 256k) */
|
||||
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
|
|
@ -53,6 +53,8 @@
|
|||
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
|
||||
#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0000000-0xbfffffff: QSPI register block */
|
||||
#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
|
||||
#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xbfffffff: OCTOSPI2 register block */
|
||||
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
|
||||
#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
|
||||
|
|
@ -66,8 +68,9 @@
|
|||
/* 0x00100000-0x07ffffff: Reserved */
|
||||
#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
|
||||
/* 0x08100000-0x0fffffff: Reserved */
|
||||
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 32Kb or 64Kb SRAM2 */
|
||||
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */
|
||||
/* 0x10010000-0x1ffeffff: Reserved */
|
||||
#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */
|
||||
#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
|
||||
#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
|
|
@ -161,6 +164,8 @@
|
|||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32L4_DSI_BASE 0x40016c00
|
||||
#define STM32L4_LTDC_BASE 0x40016800
|
||||
#define STM32L4_DFSDM_BASE 0x40016000
|
||||
#define STM32L4_SAI2_BASE 0x40015800
|
||||
#define STM32L4_SAI1_BASE 0x40015400
|
||||
|
|
@ -171,7 +176,9 @@
|
|||
#define STM32L4_TIM8_BASE 0x40013400
|
||||
#define STM32L4_SPI1_BASE 0x40013000
|
||||
#define STM32L4_TIM1_BASE 0x40012c00
|
||||
#define STM32L4_SDMMC1_BASE 0x40012800
|
||||
#ifndef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x40012800
|
||||
#endif
|
||||
#define STM32L4_FIREWALL_BASE 0x40011c00
|
||||
#define STM32L4_EXTI_BASE 0x40010400
|
||||
#define STM32L4_COMP_BASE 0x40010200
|
||||
|
|
@ -180,16 +187,22 @@
|
|||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32L4_GFXMMU_BASE 0x4002c000
|
||||
#define STM32L4_DMA2D_BASE 0x4002b000
|
||||
#define STM32L4_TSC_BASE 0x40024000
|
||||
#define STM32L4_CRC_BASE 0x40023000
|
||||
#define STM32L4_FLASHIF_BASE 0x40022000
|
||||
#define STM32L4_RCC_BASE 0x40021000
|
||||
#define STM32L4_DMAMUX1_BASE 0x40020800
|
||||
#define STM32L4_DMA2_BASE 0x40020400
|
||||
#define STM32L4_DMA1_BASE 0x40020000
|
||||
|
||||
/* AHB2 Base Addresses **************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x50062400
|
||||
#endif
|
||||
#define STM32L4_OCTOSPIIOM_BASE 0x50061c00
|
||||
#define STM32L4_RNG_BASE 0x50060800
|
||||
#define STM32L4_HASH_BASE 0x50060400
|
||||
#define STM32L4_AES_BASE 0x50060000
|
||||
|
|
|
|||
|
|
@ -50,6 +50,8 @@
|
|||
# include "chip/stm32l4x5xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 L4 pin map"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -49,6 +49,8 @@
|
|||
# include "chip/stm32l4x5xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_syscfg.h"
|
||||
#else
|
||||
# error "Unsupported STM32 L4 chip"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@
|
|||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
|
|
@ -73,27 +73,27 @@
|
|||
|
||||
/* Code Segment Start Address */
|
||||
#define FIREWALL_CSSADD_SHIFT 8
|
||||
#define FIREWALL_CSSADD_MASK (0xFFFF << FIREWALL_CSSADD_SHIFT)
|
||||
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
|
||||
|
||||
/* Code Segment Length */
|
||||
#define FIREWALL_CSSLENG_SHIFT 8
|
||||
#define FIREWALL_CSSLENG_MASK (0x3FFF << FIREWALL_CSSLENG_SHIFT)
|
||||
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Start Address */
|
||||
#define FIREWALL_NVDSADD_SHIFT 8
|
||||
#define FIREWALL_NVDSADD_MASK (0xFFFF << FIREWALL_NVDSADD_SHIFT)
|
||||
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Length */
|
||||
#define FIREWALL_NVDSLENG_SHIFT 8
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3FFF << FIREWALL_NVDSLENG_SHIFT)
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Start Address */
|
||||
#define FIREWALL_VDSADD_SHIFT 6
|
||||
#define FIREWALL_VDSADD_MASK (0x07FF << FIREWALL_VDSADD_SHIFT)
|
||||
#define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Length */
|
||||
#define FIREWALL_VDSLENG_SHIFT 6
|
||||
#define FIREWALL_VDSLENG_MASK (0x07FF << FIREWALL_VDSLENG_SHIFT)
|
||||
#define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT)
|
||||
|
||||
/* Configuration Register */
|
||||
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
|
||||
|
|
|
|||
|
|
@ -243,14 +243,14 @@
|
|||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
|
|
@ -262,7 +262,7 @@
|
|||
|
||||
#define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21)
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21) /* Bits 21-22: Main PLL division factor for PLL48M1CLK (48 MHz clock) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
|
||||
|
|
@ -272,7 +272,7 @@
|
|||
|
||||
#define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25)
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25) /* Bits 25-26: Main PLL division factor for PLLCLK (system clock) */
|
||||
#define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
|
|
|
|||
|
|
@ -231,12 +231,12 @@
|
|||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLSAI3CLK output enable */
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@
|
|||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
|
|
@ -74,39 +74,39 @@
|
|||
/* Code Segment Start Address */
|
||||
|
||||
#define FIREWALL_CSSADD_SHIFT 8
|
||||
#define FIREWALL_CSSADD_MASK (0xFFFF << FIREWALL_CSSADD_SHIFT)
|
||||
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
|
||||
|
||||
/* Code Segment Length */
|
||||
|
||||
#define FIREWALL_CSSLENG_SHIFT 8
|
||||
#define FIREWALL_CSSLENG_MASK (0x3FFF << FIREWALL_CSSLENG_SHIFT)
|
||||
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_NVDSADD_SHIFT 8
|
||||
#define FIREWALL_NVDSADD_MASK (0xFFFF << FIREWALL_NVDSADD_SHIFT)
|
||||
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_NVDSLENG_SHIFT 8
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3FFF << FIREWALL_NVDSLENG_SHIFT)
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_VDSADD_SHIFT 6
|
||||
#if defined(CONFIG_STM32L4_STM32L496XX)
|
||||
#define FIREWALL_VDSADD_MASK (0x0FFF << FIREWALL_VDSADD_SHIFT)
|
||||
# define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT)
|
||||
#else
|
||||
#define FIREWALL_VDSADD_MASK (0x07FF << FIREWALL_VDSADD_SHIFT)
|
||||
# define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_VDSLENG_SHIFT 6
|
||||
#if defined(CONFIG_STM32L4_STM32L496XX)
|
||||
#define FIREWALL_VDSLENG_MASK (0x0FFF << FIREWALL_VDSLENG_SHIFT)
|
||||
# define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT)
|
||||
#else
|
||||
#define FIREWALL_VDSLENG_MASK (0x07FF << FIREWALL_VDSLENG_SHIFT)
|
||||
# define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Configuration Register */
|
||||
|
|
|
|||
|
|
@ -244,14 +244,14 @@
|
|||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
|
|
@ -263,7 +263,7 @@
|
|||
|
||||
#define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21)
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21) /* Bits 21-22: Main PLL division factor for PLL48M1CLK (48 MHz clock) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
|
||||
|
|
@ -273,7 +273,7 @@
|
|||
|
||||
#define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25)
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25) /* Bits 25-26: Main PLL division factor for PLLCLK (system clock) */
|
||||
#define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
|
|
@ -285,7 +285,7 @@
|
|||
|
||||
/* PLLSAI1 Configuration register */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI1 PLL (PLLSAI1) VCO multiplier */
|
||||
#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI1 PLL (PLLSAI1) VCO multiplier */
|
||||
#define RCC_PLLSAI1CFG_PLLN_MASK (0x7f << RCC_PLLSAI1CFG_PLLN_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLN(n) ((n) << RCC_PLLSAI1CFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
|
|
@ -317,7 +317,7 @@
|
|||
|
||||
/* PLLSAI2 Configuration register */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI2 PLL (PLLSAI2) VCO multiplier */
|
||||
#define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI2 PLL (PLLSAI2) VCO multiplier */
|
||||
#define RCC_PLLSAI2CFG_PLLN_MASK (0x7f << RCC_PLLSAI2CFG_PLLN_SHIFT)
|
||||
# define RCC_PLLSAI2CFG_PLLN(n) ((n) << RCC_PLLSAI2CFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
|
|
@ -754,7 +754,7 @@
|
|||
#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */
|
||||
#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */
|
||||
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 8-9: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
|
|
@ -800,7 +800,7 @@
|
|||
|
||||
/* Peripheral Independent Clock Configuration 2 register (only on STM32L496xx/4A6xx) */
|
||||
|
||||
#define RCC_CCIPR2_I2C4SEL_SHIFT (0)
|
||||
#define RCC_CCIPR2_I2C4SEL_SHIFT (0) /* Bits 0-1: I2C4 clock source selection */
|
||||
#define RCC_CCIPR2_I2C4SEL_MASK (3 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_PCLK (0 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
|
|
|
|||
113
arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
Normal file
113
arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DBGMCU_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DBGMCU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
|
||||
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
|
||||
#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
|
||||
#define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze register 2 */
|
||||
#define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* MCU identifier */
|
||||
|
||||
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
|
||||
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
|
||||
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
|
||||
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
|
||||
|
||||
/* MCU debug */
|
||||
|
||||
#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */
|
||||
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */
|
||||
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */
|
||||
#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */
|
||||
|
||||
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
|
||||
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
|
||||
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
|
||||
#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
|
||||
#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
|
||||
#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
|
||||
|
||||
/* Debug MCU APB1 freeze register */
|
||||
|
||||
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
|
||||
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
|
||||
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
|
||||
#define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */
|
||||
|
||||
/* Debug MCU APB1 freeze register 2 */
|
||||
|
||||
#define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopper when core is halted */
|
||||
|
||||
/* Debug MCU APB2 freeze register */
|
||||
|
||||
#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXXDBGMCU_H */
|
||||
507
arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h
Normal file
507
arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h
Normal file
|
|
@ -0,0 +1,507 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* 14 Channels Total: 7 DMA1 Channels(1-7) and 7 DMA2 channels (1-7) */
|
||||
|
||||
#define DMA1 0
|
||||
#define DMA2 1
|
||||
#define DMA3 2
|
||||
#define DMA4 3
|
||||
#define DMA5 4
|
||||
#define DMA6 5
|
||||
#define DMA7 6
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32L4_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32L4_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32L4_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32L4_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32L4_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32L4_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32L4_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_CHAN_SHIFT(n) ((n) << 2)
|
||||
#define DMA_CHAN_MASK 0x0f
|
||||
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
|
||||
/* DMA interrupt status register */
|
||||
|
||||
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
|
||||
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
|
||||
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
|
||||
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
|
||||
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
|
||||
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA channel configuration register */
|
||||
|
||||
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
|
||||
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
|
||||
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
|
||||
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
|
||||
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
|
||||
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
|
||||
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
|
||||
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
|
||||
|
||||
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
|
||||
|
||||
/* DMA channel number of data register */
|
||||
|
||||
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to one of several
|
||||
* possible sources/sinks of data. The requests from peripherals assigned to a
|
||||
* channel are multiplexed together before entering the DMA block. This means
|
||||
* that only one request on a given channel can be enabled at once.
|
||||
*
|
||||
* Alternative DMA channel selections are provided with a numeric suffix like _1,
|
||||
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32L4_DMA1_CHAN1 (0)
|
||||
#define STM32L4_DMA1_CHAN2 (1)
|
||||
#define STM32L4_DMA1_CHAN3 (2)
|
||||
#define STM32L4_DMA1_CHAN4 (3)
|
||||
#define STM32L4_DMA1_CHAN5 (4)
|
||||
#define STM32L4_DMA1_CHAN6 (5)
|
||||
#define STM32L4_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32L4_DMA2_CHAN1 (7)
|
||||
#define STM32L4_DMA2_CHAN2 (8)
|
||||
#define STM32L4_DMA2_CHAN3 (9)
|
||||
#define STM32L4_DMA2_CHAN4 (10)
|
||||
#define STM32L4_DMA2_CHAN5 (11)
|
||||
#define STM32L4_DMA2_CHAN6 (12)
|
||||
#define STM32L4_DMA2_CHAN7 (13)
|
||||
|
||||
/* DMA Channel settings include a channel and an alternative function.
|
||||
* Channel is in bits 0..7
|
||||
* Request number is in bits 8..15
|
||||
*
|
||||
* TODO: THIS IS WRONG! NEED TO USE DMAMUX_1!
|
||||
*/
|
||||
|
||||
#define DMACHAN_SETTING(chan, req) ((((req) & 0xff) << 8) | ((chan) & 0xff))
|
||||
#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF
|
||||
#define DMACHAN_SETTING_CHANNEL_SHIFT (0)
|
||||
#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00
|
||||
#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
|
||||
|
||||
/* ADC */
|
||||
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
|
||||
|
||||
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0)
|
||||
|
||||
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0)
|
||||
|
||||
/* AES */
|
||||
|
||||
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6)
|
||||
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6)
|
||||
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6)
|
||||
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
|
||||
/* DCMI */
|
||||
|
||||
#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4)
|
||||
#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0)
|
||||
|
||||
/* DFSDM */
|
||||
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0)
|
||||
|
||||
/* HASH */
|
||||
|
||||
#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 6)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
|
||||
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
|
||||
|
||||
#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0)
|
||||
#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0)
|
||||
|
||||
/* QUADSPI */
|
||||
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
|
||||
|
||||
/* SAI */
|
||||
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
|
||||
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
|
||||
|
||||
/* SDMMC */
|
||||
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
|
||||
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
|
||||
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
|
||||
|
||||
/* SWPMI */
|
||||
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
|
||||
|
||||
/* TIM */
|
||||
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
|
||||
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
|
||||
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
|
||||
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6)
|
||||
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6)
|
||||
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6)
|
||||
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6)
|
||||
|
||||
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5)
|
||||
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5)
|
||||
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
|
||||
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
|
||||
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7)
|
||||
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7)
|
||||
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
|
||||
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
|
||||
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
|
||||
|
||||
/* UART */
|
||||
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
|
||||
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
|
||||
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
|
||||
|
||||
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2)
|
||||
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2)
|
||||
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
|
||||
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DMA_H */
|
||||
110
arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
Normal file
110
arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
|
||||
*
|
||||
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
|
||||
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Code Segment Start Address */
|
||||
|
||||
#define FIREWALL_CSSADD_SHIFT 8
|
||||
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
|
||||
|
||||
/* Code Segment Length */
|
||||
|
||||
#define FIREWALL_CSSLENG_SHIFT 8
|
||||
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_NVDSADD_SHIFT 8
|
||||
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_NVDSLENG_SHIFT 8
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_VDSADD_SHIFT 6
|
||||
#define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_VDSLENG_SHIFT 6
|
||||
#define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT)
|
||||
|
||||
/* Configuration Register */
|
||||
|
||||
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
|
||||
#define FIREWALL_CR_VDS (1 << 1) /* Bit 1: Volatile data shared */
|
||||
#define FIREWALL_CR_VDE (1 << 2) /* Bit 2: Volatile data execution */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H */
|
||||
828
arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
Normal file
828
arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
Normal file
|
|
@ -0,0 +1,828 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
|
||||
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32l4_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions. All members of the STM32L4xxx family share the same
|
||||
* pin multiplexing (although they may differ in the pins physically available).
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* CAN1_RX connects vis PA11 on some board, then the following definitions should
|
||||
* appear inthe board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
*
|
||||
* The driver will then automatically configre PA11 as the CAN1 RX pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
* Additional effort is required to select specific GPIO options such as frequency,
|
||||
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
|
||||
* pins in this file.
|
||||
*/
|
||||
|
||||
/* ADC */
|
||||
|
||||
#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN16 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
|
||||
/* CAN */
|
||||
|
||||
#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN1)
|
||||
|
||||
/* Clocks outputs */
|
||||
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
/* Comparators */
|
||||
|
||||
#define GPIO_COMP1_INM_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_COMP1_INM_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_COMP1_INP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_COMP1_INP_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_COMP1_OUT_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_COMP1_OUT_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
|
||||
|
||||
#define GPIO_COMP2_INM_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_COMP2_INM_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_COMP2_INP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_COMP2_INP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_COMP2_OUT_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_COMP2_OUT_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
|
||||
/* Digital Camera Interface (DCMI) */
|
||||
|
||||
#define GPIO_DCMI_PIXCK_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_DCMI_PIXCK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_DCMI_HSYNC_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DCMI_HSYNC_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN5)
|
||||
|
||||
#define GPIO_DCMI_D0_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D1_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_DCMI_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_DCMI_D2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_DCMI_D3_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_DCMI_D4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_DCMI_D5_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_DCMI_D5_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D6_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_DCMI_D6_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_DCMI_D7_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D8_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D8_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D9_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_DCMI_D9_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_DCMI_D10_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D10_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_DCMI_D11_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_DCMI_D11_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D12_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_DCMI_D12_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D13_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D13_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN0)
|
||||
|
||||
/* Digital Filter for Sigma-Delta Modulators (DFSDM) */
|
||||
|
||||
#define GPIO_DFSDM_DATIN0_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_DFSDM_DATIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_DFSDM_DATIN1_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_DFSDM_DATIN1_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_DFSDM_DATIN2_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_DFSDM_DATIN2_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_DFSDM_DATIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_DFSDM_DATIN3_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_DFSDM_DATIN4_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_DFSDM_DATIN4_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_DFSDM_DATIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_DFSDM_DATIN5_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_DFSDM_DATIN6_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_DFSDM_DATIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_DFSDM_DATIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_DFSDM_DATIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN0)
|
||||
|
||||
#define GPIO_DFSDM_CKIN0_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_DFSDM_CKIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_DFSDM_CKIN1_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_DFSDM_CKIN1_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_DFSDM_CKIN2_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_DFSDM_CKIN2_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_DFSDM_CKIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_DFSDM_CKIN3_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_DFSDM_CKIN4_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_DFSDM_CKIN4_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_DFSDM_CKIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_DFSDM_CKIN5_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_DFSDM_CKIN6_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_DFSDM_CKIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_DFSDM_CKIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_DFSDM_CKIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN1)
|
||||
|
||||
#define GPIO_DFSDM_CKOUT_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_DFSDM_CKOUT_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN9)
|
||||
|
||||
/* Flexible Static Memory Controller (FSMC) */
|
||||
|
||||
#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_FMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_FMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_FMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_FMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_FMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_FMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN9)
|
||||
|
||||
#define GPIO_FMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_FMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_FMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_FMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_FMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_FMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_FMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_FMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_FMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_FMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_FMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_FMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN1)
|
||||
#define GPIO_FMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_FMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_FMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_FMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_FMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_FMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_FMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_FMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_FMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_FMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_FMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_FMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN14)
|
||||
|
||||
#define GPIO_FMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN10)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_I2C1_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTA|GPIO_PIN1)
|
||||
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_I2C3_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_I2C3_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTH|GPIO_PIN9)
|
||||
|
||||
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF2 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_I2C4_SDA_5 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF2 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN13)
|
||||
|
||||
/* JTAG */
|
||||
|
||||
#define GPIO_JTCK_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_JTMS_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_JTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
/* OTG FS */
|
||||
|
||||
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTGFS_NOE_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_OTGFS_NOE_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
/* OCTOSPI */
|
||||
|
||||
#define GPIO_OCTOSPIM_P1_DQS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_OCTOSPIM_P1_DQS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_OCTOSPIM_P1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OCTOSPIM_P1_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_OCTOSPIM_P1_CLK_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OCTOSPIM_P1_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_OCTOSPIM_1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OCTOSPIM_1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_OCTOSPIM_1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_OCTOSPIM_1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_OCTOSPIM_1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_OCTOSPIM_1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_OCTOSPIM_1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_OCTOSPIM_1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_OCTOSPIM_1_IO4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_OCTOSPIM_1_IO4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_OCTOSPIM_1_IO4_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_OCTOSPIM_1_IO5_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_OCTOSPIM_1_IO5_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_OCTOSPIM_1_IO5_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_OCTOSPIM_1_IO6_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_OCTOSPIM_1_IO6_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_OCTOSPIM_1_IO7_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_OCTOSPIM_1_IO7_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7)
|
||||
|
||||
#define GPIO_OCTOSPIM_P2_DQS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_OCTOSPIM_P2_DQS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_OCTOSPIM_P2_DQS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_OCTOSPIM_P2_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_OCTOSPIM_P2_NCS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_OCTOSPIM_P2_NCS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_OCTOSPIM_P2_CLK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_OCTOSPIM_P2_CLK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_OCTOSPIM_P2_CLK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN6)
|
||||
/* TODO: IO lines */
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define GPIO_RTC_OUT (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_RTC_REFIN (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
/* SAI */
|
||||
|
||||
#define GPIO_SAI1_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_SAI1_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN0)
|
||||
|
||||
#define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN2)
|
||||
|
||||
#define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_SAI1_FS_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_SAI1_FS_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_SAI1_SCK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_SAI1_SD_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_SAI1_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN7)
|
||||
|
||||
#define GPIO_SAI2_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_SAI2_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_SAI2_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SAI2_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_SAI2_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11)
|
||||
|
||||
#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN4)
|
||||
|
||||
/* SDIO */
|
||||
|
||||
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_SPI1_NSS_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SPI1_SCK_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_SPI1_MOSI_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SPI1_MISO_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN3)
|
||||
|
||||
#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN3)
|
||||
|
||||
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI3_NSS_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SPI3_MISO_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN10)
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_TIM1_BKIN_COMP1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_TIM1_BKIN_COMP2_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM1_BKIN_COMP2_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_TIM1_BKIN2_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_BKIN2_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_BKIN2_COMP1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_BKIN2_COMP2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN7)
|
||||
|
||||
#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1IN_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1OUT_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN2)
|
||||
|
||||
#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF1 |GPIO_PORTF|GPIO_PIN6)
|
||||
|
||||
#define GPIO_TIM8_CH1IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH2IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH3IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM8_CH4IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM8_BKIN_COMP1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM8_BKIN_COMP2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_BKIN2_COMP1 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_BKIN2_COMP2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM8_ETR (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_TIM15_CH1IN_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_TIM15_CH1OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_TIM15_CH2IN_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_TIM15_CH2OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_TIM16_CH1N (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_LPTIM1_IN1_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_LPTIM1_IN2_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_LPTIM1_IN2_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_LPTIM1_OUT_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_LPTIM1_ETR_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN12)
|
||||
|
||||
#define GPIO_LPTIM2_IN1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_LPTIM2_IN1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_LPTIM2_IN1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_LPTIM2_OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_LPTIM2_OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_LPTIM2_OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_LPTIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_LPTIM2_ETR_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_LPTIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN11)
|
||||
|
||||
/* Touch Sensing Controller */
|
||||
|
||||
#define GPIO_TSC_SYNC (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#define GPIO_TSC_G1_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_TSC_G1_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_TSC_G1_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TSC_G1_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
#define GPIO_TSC_G2_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_TSC_G2_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_TSC_G2_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TSC_G2_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN7)
|
||||
|
||||
#define GPIO_TSC_G3_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TSC_G3_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_TSC_G3_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_TSC_G3_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
#define GPIO_TSC_G4_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TSC_G4_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TSC_G4_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TSC_G4_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
#define GPIO_TSC_G5_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_TSC_G5_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TSC_G5_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_TSC_G5_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN13)
|
||||
|
||||
#define GPIO_TSC_G6_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_TSC_G6_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_TSC_G6_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TSC_G6_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN13)
|
||||
|
||||
#define GPIO_TSC_G7_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TSC_G7_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TSC_G7_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TSC_G7_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN5)
|
||||
|
||||
#define GPIO_TSC_G8_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_TSC_G8_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_TSC_G8_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_TSC_G8_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN1)
|
||||
|
||||
/* IR interface (with timers 16 and 17) */
|
||||
|
||||
#define GPIO_IR_OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_IR_OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN9)
|
||||
|
||||
/* Trace */
|
||||
|
||||
#define GPIO_TRACECK (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED1 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN6)
|
||||
|
||||
/* UARTs/USARTs */
|
||||
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_USART1_CK_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_USART1_CK_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_USART1_CK_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_USART1_CTS_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_CTS_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_USART1_CTS_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS_DE_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_RTS_DE_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_USART1_RTS_DE_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN12)
|
||||
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_USART2_RTS_DE_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_USART2_RTS_DE_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN4)
|
||||
|
||||
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_USART3_CTS_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_USART3_RTS_DE_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_USART3_RTS_DE_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_USART3_RTS_DE_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_USART3_RTS_DE_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN12)
|
||||
|
||||
#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_CTS (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_UART4_RTS_DE (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8 |GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_UART5_RTS_DE (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
#define GPIO_LPUART1_TX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_LPUART1_TX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_LPUART1_TX_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_LPUART1_RX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_LPUART1_RX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_LPUART1_RX_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_LPUART1_CTS_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN6)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_PINMAP_H */
|
||||
866
arch/arm/src/stm32l4/chip/stm32l4xrxx_rcc.h
Normal file
866
arch/arm/src/stm32l4/chip/stm32l4xrxx_rcc.h
Normal file
|
|
@ -0,0 +1,866 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
|
||||
* Author: Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Multi Speed clock enable */
|
||||
#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Multi Speed clock ready flag */
|
||||
#define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */
|
||||
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 3: MSI clock range selection */
|
||||
#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */
|
||||
#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT)
|
||||
# define RCC_CR_MSIRANGE_100K (0 << RCC_CR_MSIRANGE_SHIFT) /* 0000: around 100 kHz */
|
||||
# define RCC_CR_MSIRANGE_200K (1 << RCC_CR_MSIRANGE_SHIFT) /* 0001: around 200 kHz */
|
||||
# define RCC_CR_MSIRANGE_400K (2 << RCC_CR_MSIRANGE_SHIFT) /* 0010: around 400 kHz */
|
||||
# define RCC_CR_MSIRANGE_800K (3 << RCC_CR_MSIRANGE_SHIFT) /* 0011: around 800 kHz */
|
||||
# define RCC_CR_MSIRANGE_1M (4 << RCC_CR_MSIRANGE_SHIFT) /* 0100: around 1 MHz */
|
||||
# define RCC_CR_MSIRANGE_2M (5 << RCC_CR_MSIRANGE_SHIFT) /* 0101: around 2 MHz */
|
||||
# define RCC_CR_MSIRANGE_4M (6 << RCC_CR_MSIRANGE_SHIFT) /* 0110: around 4 MHz */
|
||||
# define RCC_CR_MSIRANGE_8M (7 << RCC_CR_MSIRANGE_SHIFT) /* 0111: around 8 MHz */
|
||||
# define RCC_CR_MSIRANGE_16M (8 << RCC_CR_MSIRANGE_SHIFT) /* 1000: around 16 MHz */
|
||||
# define RCC_CR_MSIRANGE_24M (9 << RCC_CR_MSIRANGE_SHIFT) /* 1001: around 24 MHz */
|
||||
# define RCC_CR_MSIRANGE_32M (10 << RCC_CR_MSIRANGE_SHIFT) /* 1010: around 32 MHz */
|
||||
# define RCC_CR_MSIRANGE_48M (11 << RCC_CR_MSIRANGE_SHIFT) /* 1011: around 48 MHz */
|
||||
|
||||
#define RCC_CR_HSION (1 << 8) /* Bit 8: Internal High Speed clock enable */
|
||||
#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 always enable for peripheral kernels */
|
||||
#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: Internal High Speed clock ready flag */
|
||||
#define RCC_CR_HSIASFS (1 << 11) /* Bit 11: HSI automatic start from stop */
|
||||
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
#define RCC_CR_PLLSAI1ON (1 << 26) /* Bit 26: PLLSAI1 enable */
|
||||
#define RCC_CR_PLLSAI1RDY (1 << 27) /* Bit 27: PLLSAI1 clock ready flag */
|
||||
#define RCC_CR_PLLSAI2ON (1 << 28) /* Bit 28: PLLSAI2 enable */
|
||||
#define RCC_CR_PLLSAI2RDY (1 << 29) /* Bit 29: PLLSAI2 clock ready flag */
|
||||
|
||||
/* Internal Clock Sources Calibration */
|
||||
|
||||
#define RCC_CR_HSITRIM_SHIFT (24) /* Bits 30-24: Internal High Speed clock trimming */
|
||||
#define RCC_CR_HSITRIM_MASK (0x7f << RCC_CR_HSITRIM_SHIFT)
|
||||
#define RCC_CR_HSICAL_SHIFT (16) /* Bits 23-16: Internal High Speed clock Calibration */
|
||||
#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
|
||||
#define RCC_CR_MSITRIM_SHIFT (8) /* Bits 15-8: Internal Multi Speed clock trimming */
|
||||
#define RCC_CR_MSITRIM_MASK (0xff << RCC_CR_MSITRIM_SHIFT)
|
||||
#define RCC_CR_MSICAL_SHIFT (0) /* Bits 7-0: Internal Multi Speed clock Calibration */
|
||||
#define RCC_CR_MSICAL_MASK (0xff << RCC_CR_MSICAL_SHIFT)
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_MSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
|
||||
|
||||
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
|
||||
|
||||
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
|
||||
#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
|
||||
#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
|
||||
|
||||
#define RCC_CFGR_STOPWUCK (1 << 15) /* Bit 15: Wakeup from Stop and CSS backup clock selection */
|
||||
# define RCC_CFGR_STOPWUCK_MSI (0 << 15) /* 0: MSI */
|
||||
# define RCC_CFGR_STOPWUCK_HSI (1 << 15) /* 0: HSI */
|
||||
|
||||
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 24-27: Microcontroller Clock Output */
|
||||
#define RCC_CFGR_MCO_MASK (0xf << RCC_CFGR_MCO_SHIFT)
|
||||
# define RCC_CFGR_MCO_NONE (0 << RCC_CFGR_MCO_SHIFT) /* 0000: Disabled */
|
||||
# define RCC_CFGR_MCO_SYSCLK (1 << RCC_CFGR_MCO_SHIFT) /* 0001: SYSCLK system clock selected */
|
||||
# define RCC_CFGR_MCO_MSI (2 << RCC_CFGR_MCO_SHIFT) /* 0010: MSI clock selected */
|
||||
# define RCC_CFGR_MCO_HSI (3 << RCC_CFGR_MCO_SHIFT) /* 0011: HSI clock selected */
|
||||
# define RCC_CFGR_MCO_HSE (4 << RCC_CFGR_MCO_SHIFT) /* 0100: HSE clock selected */
|
||||
# define RCC_CFGR_MCO_PLL (5 << RCC_CFGR_MCO_SHIFT) /* 0101: Main PLL selected */
|
||||
# define RCC_CFGR_MCO_LSI (6 << RCC_CFGR_MCO_SHIFT) /* 0110: LSI clock selected */
|
||||
# define RCC_CFGR_MCO_LSE (7 << RCC_CFGR_MCO_SHIFT) /* 0111: LSE clock selected */
|
||||
# define RCC_CFGR_MCO_HSI48 (8 << RCC_CFGR_MCO_SHIFT) /* 1000: HSI48 clock selected */
|
||||
|
||||
#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: MCO prescaler */
|
||||
#define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
# define RCC_CFGR_MCOPRE_NONE (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: no division */
|
||||
# define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: division by 2 */
|
||||
# define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: division by 4 */
|
||||
# define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: division by 8 */
|
||||
# define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: division by 16 */
|
||||
|
||||
/* PLL configuration register */
|
||||
|
||||
#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLL(PLL) and audio PLLs (PLLSAIx)
|
||||
* entry clock source */
|
||||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..127 */
|
||||
|
||||
#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLSAI3CLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI3CLK */
|
||||
# define RCC_PLLCFG_PLLP_7 0 /* 0: PLLP = 7 */
|
||||
# define RCC_PLLCFG_PLLP_17 RCC_PLLCFG_PLLP /* 1: PLLP = 17 */
|
||||
|
||||
#define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21) /* Bits 21-22: Main PLL division factor for PLL48M1CLK (48 MHz clock) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
|
||||
# define RCC_PLLCFG_PLLQ_4 (1 << RCC_PLLCFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */
|
||||
# define RCC_PLLCFG_PLLQ_6 (2 << RCC_PLLCFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */
|
||||
# define RCC_PLLCFG_PLLQ_8 (3 << RCC_PLLCFG_PLLQ_SHIFT) /* 11: PLLQ = 8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25) /* Bits 25-26: Main PLL division factor for PLLCLK (system clock) */
|
||||
#define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
# define RCC_PLLCFG_PLLR_4 (1 << RCC_PLLCFG_PLLR_SHIFT) /* 01: PLLR = 4 */
|
||||
# define RCC_PLLCFG_PLLR_6 (2 << RCC_PLLCFG_PLLR_SHIFT) /* 10: PLLR = 6 */
|
||||
# define RCC_PLLCFG_PLLR_8 (3 << RCC_PLLCFG_PLLR_SHIFT) /* 11: PLLR = 8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLPDIV_SHIFT (27) /* Bits 27-31: Main PLL division factor for PLLSAI3CLK */
|
||||
#define RCC_PLLCFG_PLLPDIV_MASK (0x1f << RCC_PLLCFG_PLLPDIV_SHIFT)
|
||||
# define RCC_PLLCFG_PLLPDIV(n) ((n)<< RCC_PLLCFG_PLLPDIV_SHIFT) /* n=2..31 */
|
||||
# define RCC_PLLCFG_PLLPDIV_0 (0 << RCC_PLLCFG_PLLPDIV_SHIFT) /* 00: PLLSAI3CLK is controlled by the bit PLLP */
|
||||
# define RCC_PLLCFG_PLLPDIV_2 (2 << RCC_PLLCFG_PLLPDIV_SHIFT) /* 10: PLLSAI3CLK = VCO / 2 */
|
||||
|
||||
#define RCC_PLLCFG_RESET (0x00001000) /* PLLCFG reset value */
|
||||
|
||||
/* PLLSAI1 Configuration register */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLM_SHIFT (4) /* Bits 4-7: Division factor for PLLSAI1 input clock */
|
||||
#define RCC_PLLSAI1CFG_PLLM_MASK (0xf << RCC_PLLSAI1CFG_PLLM_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLM(n) (((n)-1) << RCC_PLLSAI1CFG_PLLM_SHIFT) /* n = 1..16 */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI1 PLL (PLLSAI1) VCO multiplier */
|
||||
#define RCC_PLLSAI1CFG_PLLN_MASK (0x7f << RCC_PLLSAI1CFG_PLLN_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLN(n) ((n) << RCC_PLLSAI1CFG_PLLN_SHIFT) /* n = 8..127 */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI1CLK output enable */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI1CLK */
|
||||
# define RCC_PLLSAI1CFG_PLLP_7 0 /* 0: PLLP = 7 */
|
||||
# define RCC_PLLSAI1CFG_PLLP_17 RCC_PLLSAI1CFG_PLLP /* 1: PLLP = 17 */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M2CLK output enable */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLQ_SHIFT (21) /* Bits 21-22: PLLSAI1 division factor for PLL48M2CLK (48 MHz clock) */
|
||||
#define RCC_PLLSAI1CFG_PLLQ_MASK (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLQ_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLSAI1CFG_PLLQ_2 (0 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
|
||||
# define RCC_PLLSAI1CFG_PLLQ_4 (1 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */
|
||||
# define RCC_PLLSAI1CFG_PLLQ_6 (2 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */
|
||||
# define RCC_PLLSAI1CFG_PLLQ_8 (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 11: PLLQ = 8 */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLREN (1 << 24) /* Bit 24: SAI1 PLL PLLADC1CLK output enable */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLR_SHIFT (25) /* Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock) */
|
||||
#define RCC_PLLSAI1CFG_PLLR_MASK (3 << RCC_PLLSAI1CFG_PLLR_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLSAI1CFG_PLLR_2 (0 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
# define RCC_PLLSAI1CFG_PLLR_4 (1 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 01: PLLR = 4 */
|
||||
# define RCC_PLLSAI1CFG_PLLR_6 (2 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 10: PLLR = 6 */
|
||||
# define RCC_PLLSAI1CFG_PLLR_8 (3 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 11: PLLR = 8 */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLPDIV_SHIFT (27) /* Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK */
|
||||
#define RCC_PLLSAI1CFG_PLLPDIV_MASK (0x1f << RCC_PLLSAI1CFG_PLLPDIV_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLPDIV(n) ((n)<< RCC_PLLSAI1CFG_PLLPDIV_SHIFT) /* n=2..31 */
|
||||
# define RCC_PLLSAI1CFG_PLLPDIV_0 (0 << RCC_PLLSAI1CFG_PLLPDIV_SHIFT) /* 00: PLLSAI1CLK is controlled by the bit PLLSAI1P */
|
||||
# define RCC_PLLSAI1CFG_PLLPDIV_2 (2 << RCC_PLLSAI1CFG_PLLPDIV_SHIFT) /* 10: PLLSAI1CLK = VCOSAI1 / 2 */
|
||||
|
||||
/* PLLSAI2 Configuration register */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLM_SHIFT (4) /* Bits 4-7: Division factor for PLLSAI2 input clock */
|
||||
#define RCC_PLLSAI2CFG_PLLM_MASK (0xf << RCC_PLLSAI2CFG_PLLM_SHIFT)
|
||||
# define RCC_PLLSAI2CFG_PLLM(n) (((n)-1) << RCC_PLLSAI2CFG_PLLM_SHIFT) /* n = 1..16 */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI2 PLL (PLLSAI2) VCO multiplier */
|
||||
#define RCC_PLLSAI2CFG_PLLN_MASK (0x7f << RCC_PLLSAI2CFG_PLLN_SHIFT)
|
||||
# define RCC_PLLSAI2CFG_PLLN(n) ((n) << RCC_PLLSAI2CFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI2CLK output enable */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI2CLK */
|
||||
# define RCC_PLLSAI2CFG_PLLP_7 0 /* 0: PLLP = 7 */
|
||||
# define RCC_PLLSAI2CFG_PLLP_17 RCC_PLLSAI2CFG_PLLP /* 1: PLLP = 17 */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLREN (1 << 24) /* Bit 24: SAI2 PLL PLLADC2CLK output enable */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLR_SHIFT (25) /* Bits 25-26: PLLSAI2 division factor for PLLADC1CLK (ADC clock) */
|
||||
#define RCC_PLLSAI2CFG_PLLR_MASK (3 << RCC_PLLSAI2CFG_PLLR_SHIFT)
|
||||
# define RCC_PLLSAI2CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI2CFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLSAI2CFG_PLLR_2 (0 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
# define RCC_PLLSAI2CFG_PLLR_4 (1 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 01: PLLR = 4 */
|
||||
# define RCC_PLLSAI2CFG_PLLR_6 (2 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 10: PLLR = 6 */
|
||||
# define RCC_PLLSAI2CFG_PLLR_8 (3 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 11: PLLR = 8 */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLPDIV_SHIFT (27) /* Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK */
|
||||
#define RCC_PLLSAI2CFG_PLLPDIV_MASK (0x1f << RCC_PLLSAI2CFG_PLLPDIV_SHIFT)
|
||||
# define RCC_PLLSAI2CFG_PLLPDIV(n) ((n)<< RCC_PLLSAI2CFG_PLLPDIV_SHIFT) /* n=2..31 */
|
||||
# define RCC_PLLSAI2CFG_PLLPDIV_0 (0 << RCC_PLLSAI2CFG_PLLPDIV_SHIFT) /* 00: PLLSAI2CLK is controlled by the bit PLLSAI2P */
|
||||
# define RCC_PLLSAI2CFG_PLLPDIV_2 (2 << RCC_PLLSAI2CFG_PLLPDIV_SHIFT) /* 10: PLLSAI2CLK = VCOSAI2 / 2 */
|
||||
|
||||
/* Clock interrupt enable register */
|
||||
|
||||
#define RCC_CIR_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_MSIRDYIE (1 << 2) /* Bit 2: MSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLRDYIE (1 << 5) /* Bit 5: PLL Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLSAI1RDYIE (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt enable */
|
||||
#define RCC_CIR_PLLSAI2RDYIE (1 << 7) /* Bit 7: PLLSAI2 Ready Interrupt enable */
|
||||
#define RCC_CIR_LSECSSIE (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Enable */
|
||||
#define RCC_CIR_HSI48RDYIE (1 << 10) /* Bit 10: HSI48 Ready Interrupt Enable */
|
||||
|
||||
/* Clock interrupt flag register */
|
||||
|
||||
#define RCC_CIR_LSIRDYIF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */
|
||||
#define RCC_CIR_LSERDYIF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */
|
||||
#define RCC_CIR_MSIRDYIF (1 << 2) /* Bit 2: MSI Ready Interrupt Flag */
|
||||
#define RCC_CIR_HSIRDYIF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */
|
||||
#define RCC_CIR_HSERDYIF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */
|
||||
#define RCC_CIR_PLLRDYIF (1 << 5) /* Bit 5: PLL Ready Interrupt Flag */
|
||||
#define RCC_CIR_PLLSAI1RDYIF (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt Flag */
|
||||
#define RCC_CIR_PLLSAI2RDYIF (1 << 7) /* Bit 7: PLLSAI2 Ready Interrupt Flag */
|
||||
#define RCC_CIR_CSSF (1 << 8) /* Bit 8: Clock Security System Interrupt Flag */
|
||||
#define RCC_CIR_LSECSSIF (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Flag */
|
||||
#define RCC_CIR_HSI48RDYIF (1 << 10) /* Bit 10: HSI48 Ready Interrupt Flag */
|
||||
|
||||
/* Clock interrupt clear register */
|
||||
|
||||
#define RCC_CIR_LSIRDYIC (1 << 0) /* Bit 0: LSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_LSERDYIC (1 << 1) /* Bit 1: LSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_MSIRDYIC (1 << 2) /* Bit 2: MSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSIRDYIC (1 << 3) /* Bit 3: HSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSERDYIC (1 << 4) /* Bit 4: HSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLRDYIC (1 << 5) /* Bit 5: PLL Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLSAI1RDYIC (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLSAI2RDYIC (1 << 7) /* Bit 7: PLLSAI2 Ready Interrupt Clear */
|
||||
#define RCC_CIR_CSSC (1 << 8) /* Bit 8: Clock Security System Interrupt Clear */
|
||||
#define RCC_CIR_LSECSSIC (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Clear */
|
||||
#define RCC_CIR_HSI48RDYIC (1 << 10) /* Bit 10: HSI48 Oscillator Ready Interrupt Clear */
|
||||
|
||||
/* AHB1 peripheral reset register */
|
||||
|
||||
#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* Bit 0: DMA1 reset */
|
||||
#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* Bit 1: DMA2 reset */
|
||||
#define RCC_AHB1RSTR_DMAMUX1RST (1 << 2) /* Bit 2: DMAMUX1 reset */
|
||||
#define RCC_AHB1RSTR_FLASHRST (1 << 8) /* Bit 8: Flash memory interface reset */
|
||||
#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */
|
||||
#define RCC_AHB1RSTR_TSCRST (1 << 16) /* Bit 16: Touch Sensing Controller reset */
|
||||
#define RCC_AHB1RSTR_DMA2DRST (1 << 17) /* Bit 17: DMA2D reset */
|
||||
#define RCC_AHB1RSTR_GFXMMURST (1 << 18) /* Bit 18: GFXMMU reset */
|
||||
|
||||
/* AHB2 peripheral reset register */
|
||||
|
||||
#define RCC_AHB1ENR_GPIOEN(port) (1 << (port))
|
||||
#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
|
||||
#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
|
||||
#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
|
||||
#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */
|
||||
#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */
|
||||
#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */
|
||||
#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */
|
||||
#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
|
||||
#define RCC_AHB2RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */
|
||||
#define RCC_AHB2RSTR_OTGFSRST (1 << 12) /* Bit 12: USB OTG FS module reset */
|
||||
#define RCC_AHB2RSTR_ADCRST (1 << 13) /* Bit 13: ADC interface reset (common to all ADCs) */
|
||||
#define RCC_AHB2RSTR_DCMIRST (1 << 14) /* Bit 14: DCMI interface reset */
|
||||
#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES Cryptographic module reset */
|
||||
#define RCC_AHB2RSTR_HASHRST (1 << 17) /* Bit 17: HASH module reset */
|
||||
#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */
|
||||
#define RCC_AHB2RSTR_OSPIMRST (1 << 20) /* Bit 20: OctoSPI IO manager reset */
|
||||
#define RCC_AHB2RSTR_SDMMC1RST (1 << 22) /* Bit 22: SDMMC1 reset */
|
||||
|
||||
/* AHB3 peripheral reset register */
|
||||
|
||||
#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */
|
||||
#define RCC_AHB3RSTR_OSPI1RST (1 << 8) /* Bit 8: OctoSPI1 memory interface reset */
|
||||
#define RCC_AHB3RSTR_OSPI2RST (1 << 9) /* Bit 9: OctoSPI2 memory interface reset */
|
||||
|
||||
/* APB1 Peripheral reset register 1 */
|
||||
|
||||
#define RCC_APB1RSTR1_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */
|
||||
#define RCC_APB1RSTR1_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */
|
||||
#define RCC_APB1RSTR1_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */
|
||||
#define RCC_APB1RSTR1_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */
|
||||
#define RCC_APB1RSTR1_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */
|
||||
#define RCC_APB1RSTR1_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */
|
||||
#define RCC_APB1RSTR1_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */
|
||||
#define RCC_APB1RSTR1_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */
|
||||
#define RCC_APB1RSTR1_USART2RST (1 << 17) /* Bit 17: USART2 reset */
|
||||
#define RCC_APB1RSTR1_USART3RST (1 << 18) /* Bit 18: USART3 reset */
|
||||
#define RCC_APB1RSTR1_UART4RST (1 << 19) /* Bit 19: USART4 reset */
|
||||
#define RCC_APB1RSTR1_UART5RST (1 << 20) /* Bit 20: USART5 reset */
|
||||
#define RCC_APB1RSTR1_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */
|
||||
#define RCC_APB1RSTR1_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */
|
||||
#define RCC_APB1RSTR1_I2C3RST (1 << 23) /* Bit 23: I2C3 reset */
|
||||
#define RCC_APB1RSTR1_CRSRST (1 << 24) /* Bit 24: CRS reset */
|
||||
#define RCC_APB1RSTR1_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
|
||||
#define RCC_APB1RSTR1_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR1_DAC1RST (1 << 29) /* Bit 29: DAC1 reset */
|
||||
#define RCC_APB1RSTR1_OPAMPRST (1 << 30) /* Bit 30: OPAMP reset */
|
||||
#define RCC_APB1RSTR1_LPTIM1RST (1 << 31) /* Bit 31: Low-power Timer 1 reset */
|
||||
|
||||
/* APB1 Peripheral reset register 2 */
|
||||
|
||||
#define RCC_APB1RSTR2_LPUART1RST (1 << 0) /* Bit 0: Low-power UART 1 reset */
|
||||
#define RCC_APB1RSTR2_I2C4RST (1 << 1) /* Bit 1: I2C4 reset */
|
||||
#define RCC_APB1RSTR2_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: System configuration controller reset */
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
|
||||
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
|
||||
#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */
|
||||
#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */
|
||||
#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */
|
||||
#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */
|
||||
#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */
|
||||
#define RCC_APB2RSTR_DFSDMRST (1 << 24) /* Bit 24: DFSDM reset */
|
||||
#define RCC_APB2RSTR_LTDCRSTT (1 << 26) /* Bit 26: LCD-TFT reset */
|
||||
#define RCC_APB2RSTR_DSIRST (1 << 27) /* Bit 27: DSI reset */
|
||||
|
||||
/* AHB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB1ENR_DMA1EN (1 << 0) /* Bit 0: DMA1 enable */
|
||||
#define RCC_AHB1ENR_DMA2EN (1 << 1) /* Bit 1: DMA2 enable */
|
||||
#define RCC_AHB1ENR_DMAMUX1EN (1 << 2) /* Bit 2: DMAMUX1 enable */
|
||||
#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash memory interface enable */
|
||||
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC enable */
|
||||
#define RCC_AHB1ENR_TSCEN (1 << 16) /* Bit 16: Touch Sensing Controller enable */
|
||||
#define RCC_AHB1ENR_DMA2DEN (1 << 17) /* Bit 17: DMA2D enable */
|
||||
#define RCC_AHB1ENR_GFXMMUEN (1 << 18) /* Bit 18: Graphic MMU enable */
|
||||
|
||||
/* AHB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */
|
||||
#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */
|
||||
#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */
|
||||
#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */
|
||||
#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */
|
||||
#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */
|
||||
#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */
|
||||
#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */
|
||||
#define RCC_AHB2ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I enable */
|
||||
#define RCC_AHB2ENR_OTGFSEN (1 << 12) /* Bit 12: USB OTG FS module enable */
|
||||
#define RCC_AHB2ENR_ADCEN (1 << 13) /* Bit 13: ADC interface enable (common to all ADCs) */
|
||||
#define RCC_AHB2ENR_DCMIEN (1 << 14) /* Bit 14: DCMI interface enable */
|
||||
#define RCC_AHB2ENR_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */
|
||||
#define RCC_AHB2ENR_HASHEN (1 << 17) /* Bit 17: HASH module enable */
|
||||
#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */
|
||||
#define RCC_AHB2ENR_OSPIMEN (1 << 20) /* Bit 20: OctoSPI IO manager enable */
|
||||
#define RCC_AHB2ENR_SDMMC1EN (1 << 22) /* Bit 22: SDMMC1 enable */
|
||||
|
||||
/* AHB3 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module enable */
|
||||
#define RCC_AHB3ENR_OSPI1EN (1 << 8) /* Bit 8: OctoSPI1 memory interface enable */
|
||||
#define RCC_AHB3ENR_OSPI2EN (1 << 9) /* Bit 9: OctoSPI2 memory interface enable */
|
||||
|
||||
/* APB1 Peripheral Clock enable register 1 */
|
||||
|
||||
#define RCC_APB1ENR1_TIM2EN (1 << 0) /* Bit 0: TIM2 enable */
|
||||
#define RCC_APB1ENR1_TIM3EN (1 << 1) /* Bit 1: TIM3 enable */
|
||||
#define RCC_APB1ENR1_TIM4EN (1 << 2) /* Bit 2: TIM4 enable */
|
||||
#define RCC_APB1ENR1_TIM5EN (1 << 3) /* Bit 3: TIM5 enable */
|
||||
#define RCC_APB1ENR1_TIM6EN (1 << 4) /* Bit 4: TIM6 enable */
|
||||
#define RCC_APB1ENR1_TIM7EN (1 << 5) /* Bit 5: TIM7 enable */
|
||||
#define RCC_APB1ENR1_RTCAPBEN (1 << 10) /* Bit 10: RTC APB clock enable */
|
||||
#define RCC_APB1ENR1_WWDGEN (1 << 11) /* Bit 11: Windowed Watchdog enable */
|
||||
#define RCC_APB1ENR1_SPI2EN (1 << 14) /* Bit 14: SPI2 enable */
|
||||
#define RCC_APB1ENR1_SPI3EN (1 << 15) /* Bit 15: SPI3 enable */
|
||||
#define RCC_APB1ENR1_USART2EN (1 << 17) /* Bit 17: USART2 enable */
|
||||
#define RCC_APB1ENR1_USART3EN (1 << 18) /* Bit 18: USART3 enable */
|
||||
#define RCC_APB1ENR1_UART4EN (1 << 19) /* Bit 19: USART4 enable */
|
||||
#define RCC_APB1ENR1_UART5EN (1 << 20) /* Bit 20: USART5 enable */
|
||||
#define RCC_APB1ENR1_I2C1EN (1 << 21) /* Bit 21: I2C1 enable */
|
||||
#define RCC_APB1ENR1_I2C2EN (1 << 22) /* Bit 22: I2C2 enable */
|
||||
#define RCC_APB1ENR1_I2C3EN (1 << 23) /* Bit 23: I2C3 enable */
|
||||
#define RCC_APB1ENR1_CRSEN (1 << 24) /* Bit 24: CRSEN enable */
|
||||
#define RCC_APB1ENR1_CAN1EN (1 << 25) /* Bit 25: CAN1 enable */
|
||||
#define RCC_APB1ENR1_PWREN (1 << 28) /* Bit 28: Power interface enable */
|
||||
#define RCC_APB1ENR1_DAC1EN (1 << 29) /* Bit 29: DAC1 enable */
|
||||
#define RCC_APB1ENR1_OPAMPEN (1 << 30) /* Bit 30: OPAMP enable */
|
||||
#define RCC_APB1ENR1_LPTIM1EN (1 << 31) /* Bit 31: Low-power Timer 1 enable */
|
||||
|
||||
/* APB1 Peripheral Clock enable register 2 */
|
||||
|
||||
#define RCC_APB1ENR2_LPUART1EN (1 << 0) /* Bit 0: Low-power UART 1 enable */
|
||||
#define RCC_APB1ENR2_I2C4EN (1 << 1) /* Bit 1: I2C4 enable */
|
||||
#define RCC_APB1ENR2_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 enable */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
|
||||
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 enable */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 enable */
|
||||
#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 enable */
|
||||
#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 enable */
|
||||
#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 enable */
|
||||
#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 enable */
|
||||
#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 enable */
|
||||
#define RCC_APB2ENR_DFSDMEN (1 << 24) /* Bit 24: DFSDM enable */
|
||||
#define RCC_APB2ENR_LTDCEN (1 << 26) /* Bit 26: LCD-TFT enable */
|
||||
#define RCC_APB2ENR_DSIEN (1 << 27) /* Bit 27: DSI enable */
|
||||
|
||||
/* RCC AHB1 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB1SMENR_DMA1LPSMEN (1 << 0) /* Bit 0: DMA1 enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_DMA2LPSMEN (1 << 1) /* Bit 1: DMA2 enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_DMAMUX1SMEN (1 << 2) /* Bit 2: DMAMUX1 clock enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_FLASHLPSMEN (1 << 8) /* Bit 8: Flash memory interface enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9) /* Bit 9: SRAM1 enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_CRCLPSMEN (1 << 12) /* Bit 12: CRC enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_TSCLPSMEN (1 << 16) /* Bit 16: Touch Sensing Controller enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_DMA2DSMEN (1 << 17) /* Bit 17: DMA2D enable during Sleep mode */
|
||||
#define RCC_AHB1SMENR_GFXMMUSMEN (1 << 18) /* Bit 18: GFXMMU enable during Sleep mode */
|
||||
|
||||
/* RCC AHB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB2SMENR_GPIOASMEN (1 << 0) /* Bit 0: IO port A enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1) /* Bit 1: IO port B enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2) /* Bit 2: IO port C enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIODSMEN (1 << 3) /* Bit 3: IO port D enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOESMEN (1 << 4) /* Bit 4: IO port E enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOFSMEN (1 << 5) /* Bit 5: IO port F enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOGSMEN (1 << 6) /* Bit 6: IO port G enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOHSMEN (1 << 7) /* Bit 7: IO port H enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_GPIOISMEN (1 << 8) /* Bit 8: IO port I enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_SRAM2SMEN (1 << 9) /* Bit 9: SRAM2 enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_OTGFSSMEN (1 << 12) /* Bit 12: USB OTG FS module enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_ADCSMEN (1 << 13) /* Bit 13: ADC interface enable during Sleep mode (common to all ADCs) */
|
||||
#define RCC_AHB2SMENR_DCMISMEN (1 << 14) /* Bit 14: DCMI interface enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_AESSMEN (1 << 16) /* Bit 16: AES Cryptographic module enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_HASHSMEN (1 << 17) /* Bit 17: HASH module enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_RNGSMEN (1 << 18) /* Bit 18: Random number generator module enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_OSPIMSMEN (1 << 20) /* Bit 20: OctoSPI IO manager enable during Sleep mode */
|
||||
#define RCC_AHB2SMENR_SDMMC1SMEN (1 << 22) /* Bit 22: SDMMC1 enable during Sleep mode */
|
||||
|
||||
/* RCC AHB3 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB3SMENR_FSMCSMEN (1 << 0) /* Bit 0: Flexible static memory controller module enable during Sleep mode */
|
||||
#define RCC_AHB3SMENR_OSPI1SMEN (1 << 8) /* Bit 8: OctoSPI1 memory interface enable during Sleep mode */
|
||||
#define RCC_AHB3SMENR_OSPI2SMEN (1 << 9) /* Bit 9: OctoSPI2 memory interface enable during Sleep mode */
|
||||
|
||||
/* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
|
||||
#define RCC_APB1SMENR1_TIM2SMEN (1 << 0) /* Bit 0: TIM2 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_TIM3SMEN (1 << 1) /* Bit 1: TIM3 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_TIM4SMEN (1 << 2) /* Bit 2: TIM4 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_TIM5SMEN (1 << 3) /* Bit 3: TIM5 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_TIM6SMEN (1 << 4) /* Bit 4: TIM6 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_TIM7SMEN (1 << 5) /* Bit 5: TIM7 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_RTCAPBSMEN (1 << 10) /* Bit 10: RTC APB clock enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_WWDGSMEN (1 << 11) /* Bit 11: Windowed Watchdog enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_SPI2SMEN (1 << 14) /* Bit 14: SPI2 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_SPI3SMEN (1 << 15) /* Bit 15: SPI3 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_USART2SMEN (1 << 17) /* Bit 17: USART2 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_USART3SMEN (1 << 18) /* Bit 18: USART3 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_UART4SMEN (1 << 19) /* Bit 19: USART4 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_UART5SMEN (1 << 20) /* Bit 20: USART5 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_I2C1SMEN (1 << 21) /* Bit 21: I2C1 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_I2C2SMEN (1 << 22) /* Bit 22: I2C2 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_I2C3SMEN (1 << 23) /* Bit 23: I2C3 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_CRSSMEN (1 << 24) /* Bit 24: CRS enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_CAN1SMEN (1 << 25) /* Bit 25: CAN1 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_PWRSMEN (1 << 28) /* Bit 28: Power interface enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_DAC1SMEN (1 << 29) /* Bit 29: DAC1 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_OPAMPSMEN (1 << 30) /* Bit 30: OPAMP enable during Sleep mode */
|
||||
#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31) /* Bit 31: Low-power Timer 1 enable during Sleep mode */
|
||||
|
||||
/* RCC APB1 low power modeperipheral clock enable register 2 */
|
||||
|
||||
#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0) /* Bit 0: Low-power UART 1 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR2_I2C4SMEN (1 << 1) /* Bit 1: I2C4 enable during Sleep mode */
|
||||
#define RCC_APB1SMENR2_LPTIM2SMEN (1 << 5) /* Bit 5: Low-power Timer 2 enable during Sleep mode */
|
||||
|
||||
/* RCC APB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) /* Bit 0: System configuration controller enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_TIM1SMEN (1 << 11) /* Bit 11: TIM1 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_SPI1SMEN (1 << 12) /* Bit 12: SPI1 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_TIM8SMEN (1 << 13) /* Bit 13: TIM8 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_USART1SMEN (1 << 14) /* Bit 14: USART1 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_TIM15SMEN (1 << 16) /* Bit 16: TIM15 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_TIM16SMEN (1 << 17) /* Bit 17: TIM16 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_TIM17SMEN (1 << 18) /* Bit 18: TIM17 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_SAI1SMEN (1 << 21) /* Bit 21: SAI1 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_SAI2SMEN (1 << 22) /* Bit 22: SAI2 enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_DFSDMSMEN (1 << 24) /* Bit 24: DFSDM enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_LTDCSMEN (1 << 26) /* Bit 26: LCD-TFT timer enable during Sleep mode */
|
||||
#define RCC_APB2SMENR_DSISMEN (1 << 27) /* Bit 27: DSI enable during Sleep mode */
|
||||
|
||||
/* Peripheral Independent Clock Configuration register */
|
||||
|
||||
#define RCC_CCIPR_USART1SEL_SHIFT (0)
|
||||
#define RCC_CCIPR_USART1SEL_MASK (3 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_PCLK (0 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_SYSCLK (1 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_HSI (2 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_LSE (3 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_USART2SEL_SHIFT (2)
|
||||
#define RCC_CCIPR_USART2SEL_MASK (3 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_PCLK (0 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_SYSCLK (1 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_HSI (2 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_LSE (3 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_USART3SEL_SHIFT (4)
|
||||
#define RCC_CCIPR_USART3SEL_MASK (3 << RCC_CCIPR_USART3SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART3SEL_PCLK (0 << RCC_CCIPR_USART3SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART3SEL_SYSCLK (1 << RCC_CCIPR_USART3SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART3SEL_HSI (2 << RCC_CCIPR_USART3SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART3SEL_LSE (3 << RCC_CCIPR_USART3SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_UART4SEL_SHIFT (6)
|
||||
#define RCC_CCIPR_UART4SEL_MASK (3 << RCC_CCIPR_UART4SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART4SEL_PCLK (0 << RCC_CCIPR_UART4SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART4SEL_SYSCLK (1 << RCC_CCIPR_UART4SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART4SEL_HSI (2 << RCC_CCIPR_UART4SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART4SEL_LSE (3 << RCC_CCIPR_UART4SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_UART5SEL_SHIFT (8)
|
||||
#define RCC_CCIPR_UART5SEL_MASK (3 << RCC_CCIPR_UART5SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART5SEL_PCLK (0 << RCC_CCIPR_UART5SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART5SEL_SYSCLK (1 << RCC_CCIPR_UART5SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART5SEL_HSI (2 << RCC_CCIPR_UART5SEL_SHIFT)
|
||||
# define RCC_CCIPR_UART5SEL_LSE (3 << RCC_CCIPR_UART5SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_LPUART1SEL_SHIFT (10)
|
||||
#define RCC_CCIPR_LPUART1SEL_MASK (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_PCLK (0 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_SYSCLK (1 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_HSI (2 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_LSE (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_I2C1SEL_SHIFT (12)
|
||||
#define RCC_CCIPR_I2C1SEL_MASK (3 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C1SEL_PCLK (0 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C1SEL_SYSCLK (1 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C1SEL_HSI (2 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_I2C2SEL_SHIFT (14)
|
||||
#define RCC_CCIPR_I2C2SEL_MASK (3 << RCC_CCIPR_I2C2SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C2SEL_PCLK (0 << RCC_CCIPR_I2C2SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C2SEL_SYSCLK (1 << RCC_CCIPR_I2C2SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C2SEL_HSI (2 << RCC_CCIPR_I2C2SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_I2C3SEL_SHIFT (16)
|
||||
#define RCC_CCIPR_I2C3SEL_MASK (3 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C3SEL_PCLK (0 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C3SEL_SYSCLK (1 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C3SEL_HSI (2 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_LPTIM1SEL_SHIFT (18)
|
||||
#define RCC_CCIPR_LPTIM1SEL_MASK (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_PCLK (0 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_LSI (1 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_HSI (2 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_LSE (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_LPTIM2SEL_SHIFT (20)
|
||||
#define RCC_CCIPR_LPTIM2SEL_MASK (3 << RCC_CCIPR_LPTIM2SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM2SEL_PCLK (0 << RCC_CCIPR_LPTIM2SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM2SEL_LSI (1 << RCC_CCIPR_LPTIM2SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM2SEL_HSI (2 << RCC_CCIPR_LPTIM2SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM2SEL_LSE (3 << RCC_CCIPR_LPTIM2SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_SAI1SEL_SHIFT (22)
|
||||
#define RCC_CCIPR_SAI1SEL_MASK (3 << RCC_CCIPR_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI1SEL_PLLSAI1 (0 << RCC_CCIPR_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI1SEL_PLLSAI2 (1 << RCC_CCIPR_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI1SEL_PLLMAIN (2 << RCC_CCIPR_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI1SEL_EXTCLK (3 << RCC_CCIPR_SAI1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_SAI2SEL_SHIFT (24)
|
||||
#define RCC_CCIPR_SAI2SEL_MASK (3 << RCC_CCIPR_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI2SEL_PLLSAI1 (0 << RCC_CCIPR_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI2SEL_PLLSAI2 (1 << RCC_CCIPR_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI2SEL_PLLMAIN (2 << RCC_CCIPR_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR_SAI2SEL_EXTCLK (3 << RCC_CCIPR_SAI2SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_CLK48SEL_SHIFT (26)
|
||||
#define RCC_CCIPR_CLK48SEL_MASK (3 << RCC_CCIPR_CLK48SEL_SHIFT)
|
||||
# define RCC_CCIPR_CLK48SEL_NONE (0 << RCC_CCIPR_CLK48SEL_SHIFT)
|
||||
# define RCC_CCIPR_CLK48SEL_PLLSAI1 (1 << RCC_CCIPR_CLK48SEL_SHIFT)
|
||||
# define RCC_CCIPR_CLK48SEL_PLLMAIN (2 << RCC_CCIPR_CLK48SEL_SHIFT)
|
||||
# define RCC_CCIPR_CLK48SEL_MSI (3 << RCC_CCIPR_CLK48SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR_ADCSEL_SHIFT (28)
|
||||
#define RCC_CCIPR_ADCSEL_MASK (3 << RCC_CCIPR_ADCSEL_SHIFT)
|
||||
# define RCC_CCIPR_ADCSEL_NONE (0 << RCC_CCIPR_ADCSEL_SHIFT)
|
||||
# define RCC_CCIPR_ADCSEL_PLLSAI1 (1 << RCC_CCIPR_ADCSEL_SHIFT)
|
||||
# define RCC_CCIPR_ADCSEL_PLLSAI2 (2 << RCC_CCIPR_ADCSEL_SHIFT)
|
||||
# define RCC_CCIPR_ADCSEL_SYSCLK (3 << RCC_CCIPR_ADCSEL_SHIFT)
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
|
||||
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
|
||||
|
||||
#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */
|
||||
#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT)
|
||||
# define RCC_BDCR_LSEDRV_LOWER (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */
|
||||
# define RCC_BDCR_LSEDRV_MIDLOW (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */
|
||||
# define RCC_BDCR_LSEDRV_MIDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/
|
||||
# define RCC_BDCR_LSEDRV_HIGER (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */
|
||||
|
||||
#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */
|
||||
#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */
|
||||
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 8-9: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */
|
||||
|
||||
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
|
||||
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
|
||||
#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */
|
||||
#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */
|
||||
# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */
|
||||
# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */
|
||||
|
||||
#define RCC_CSR_MSISRANGE_SHIFT 8
|
||||
# define RCC_CSR_MSISRANGE_MASK (0x0f << RCC_CSR_MSISRANGE_SHIFT) /* MSI range after Standby mode */
|
||||
# define RCC_CSR_MSISRANGE_1M (4 << RCC_CSR_MSISRANGE_SHIFT) /* 0100: around 1 MHz */
|
||||
# define RCC_CSR_MSISRANGE_2M (5 << RCC_CSR_MSISRANGE_SHIFT) /* 0101: around 2 MHz */
|
||||
# define RCC_CSR_MSISRANGE_4M (6 << RCC_CSR_MSISRANGE_SHIFT) /* 0110: around 4 MHz */
|
||||
# define RCC_CSR_MSISRANGE_8M (7 << RCC_CSR_MSISRANGE_SHIFT) /* 0111: around 8 MHz */
|
||||
|
||||
#define RCC_CSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */
|
||||
#define RCC_CSR_FWRSTF (1 << 24) /* Bit 24: Firewall reset flag */
|
||||
#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */
|
||||
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
|
||||
|
||||
/* Clock recovery RC register */
|
||||
|
||||
#define RCC_CRRCR_HSI48CAL_SHIFT 7
|
||||
# define RCC_CRRCR_HSI48CAL_MASK (0x01ff << RCC_CRRCR_HSI48CAL_SHIFT) /* HSI48 clock calibration */
|
||||
|
||||
#define RCC_CRRCR_HSI48ON (1 << 0) /* Bit 0: HSI48 clock enable */
|
||||
#define RCC_CRRCR_HSI48RDY (1 << 1) /* Bit 1: HSI48 clock ready flag */
|
||||
|
||||
/* Peripheral Independent Clock Configuration 2 register */
|
||||
|
||||
#define RCC_CCIPR2_I2C4SEL_SHIFT (0) /* Bits 0-1: I2C4 clock source selection */
|
||||
#define RCC_CCIPR2_I2C4SEL_MASK (3 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_PCLK (0 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR2_DFSDMSEL (1 << 2) /* Bit 2: Digital filter for sigma delta modulator kernel clock source */
|
||||
# define RCC_CCIPR2_DFSDMSEL_APB2 0 /* APB2 clock (PCLK2) selected */
|
||||
# define RCC_CCIPR2_DFSDMSEL_PCLK RCC_CCIPR2_DFSDMSEL /* System clock selected */
|
||||
|
||||
#define RCC_CCIPR2_ADFSDMSEL_SHIFT (3) /* Bits 3-4: Digital filter for sigma delta modulator audio clock source */
|
||||
#define RCC_CCIPR2_ADFSDMSEL_MASK (3 << RCC_CCIPR2_ADFSDMSEL_SHIFT)
|
||||
# define RCC_CCIPR2_ADFSDMSEL_SAI1 (0 << RCC_CCIPR2_ADFSDMSEL_SHIFT)
|
||||
# define RCC_CCIPR2_ADFSDMSEL_HSI (1 << RCC_CCIPR2_ADFSDMSEL_SHIFT)
|
||||
# define RCC_CCIPR2_ADFSDMSEL_MSI (2 << RCC_CCIPR2_ADFSDMSEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR2_SAI1SEL_SHIFT (5) /* Bits 5-7: SAI1 clock source selection */
|
||||
#define RCC_CCIPR2_SAI1SEL_MASK (7 << RCC_CCIPR2_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI1SEL_PLLSAI1 (0 << RCC_CCIPR2_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI1SEL_PLLSAI2 (1 << RCC_CCIPR2_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI1SEL_PLLSAI3 (2 << RCC_CCIPR2_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI1SEL_SAI1_EXT (3 << RCC_CCIPR2_SAI1SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI1SEL_HSI (4 << RCC_CCIPR2_SAI1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR2_SAI2SEL_SHIFT (8) /* Bits 8-10: SAI2 clock source selection */
|
||||
#define RCC_CCIPR2_SAI2SEL_MASK (7 << RCC_CCIPR2_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI2SEL_PLLSAI1 (0 << RCC_CCIPR2_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI2SEL_PLLSAI2 (1 << RCC_CCIPR2_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI2SEL_PLLSAI3 (2 << RCC_CCIPR2_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI2SEL_SAI2_EXT (3 << RCC_CCIPR2_SAI2SEL_SHIFT)
|
||||
# define RCC_CCIPR2_SAI2SEL_HSI (4 << RCC_CCIPR2_SAI2SEL_SHIFT)
|
||||
|
||||
|
||||
#endif /* CONFIG_STM32L4_STM32L4XR */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_RCC_H */
|
||||
193
arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
Normal file
193
arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2014-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_MEMRMP_MASK (7 << SYSCFG_MEMRMP_SHIFT)
|
||||
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_FMC (2 << SYSCFG_MEMRMP_SHIFT) /* 010: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_OCTOSPI1 (4 << SYSCFG_MEMRMP_SHIFT) /* 100: OCTOSPI1 mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_OCTOSPI2 (5 << SYSCFG_MEMRMP_SHIFT) /* 101: OCTOSPI2 mapped at 0x0000 0000 */
|
||||
#define SYSCFG_FBMODE (1 << 8) /* Bit 8: Flash Bank mode selection */
|
||||
|
||||
/* SYSCFG configuration register 1 */
|
||||
|
||||
#define SYSCFG_CFGR1_FWDIS (1 << 0) /* Bit 0: Firewall disable */
|
||||
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
|
||||
#define SYSCFG_CFGR1_ANASWVDD (1 << 9) /* Bit 9: GPIO analog switch control voltage selection */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
|
||||
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
|
||||
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* SYSCFG SRAM2 control and status register */
|
||||
|
||||
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
|
||||
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
|
||||
|
||||
/* SYSCFG configuration register 2 */
|
||||
|
||||
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
|
||||
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable (same) */
|
||||
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable (same) */
|
||||
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */
|
||||
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
|
||||
|
||||
/* SYSCFG SRAM2 write protection register */
|
||||
/* There is one bit per SRAM2 page (0 to 31) */
|
||||
|
||||
/* SYSCFG SRAM2 key register */
|
||||
|
||||
#define SYSCFG_SKR_SHIFT 0
|
||||
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
|
||||
|
||||
/* SYSCFG SRAM2 write protection register 2 */
|
||||
/* There is one bit per SRAM2 page (32 to 63) */
|
||||
|
||||
#endif /* CONFIG_STM32L4_STM32L4XR */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H */
|
||||
|
|
@ -76,12 +76,12 @@
|
|||
#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \
|
||||
defined(CONFIG_STM32L4_ADC3)
|
||||
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6))
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR))
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# if defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3)
|
||||
# error "Using non-existent ADC"
|
||||
# endif
|
||||
|
|
@ -105,7 +105,7 @@
|
|||
|
||||
/* ADC interrupts ***********************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -98,6 +98,12 @@
|
|||
* 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000
|
||||
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
|
||||
*
|
||||
* STM32L4Rxxx have 640 Kib in three banks:
|
||||
*
|
||||
* 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000
|
||||
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
|
||||
* 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000
|
||||
*
|
||||
* In addition, external FSMC SRAM may be available.
|
||||
*/
|
||||
|
||||
|
|
@ -111,6 +117,21 @@
|
|||
#define SRAM2_START STM32L4_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE)
|
||||
|
||||
/* Set the range of SRAM3, requiring a third memory region */
|
||||
|
||||
#ifdef STM32L4_SRAM3_SIZE
|
||||
# define SRAM3_START STM32L4_SRAM3_BASE
|
||||
# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE)
|
||||
# define CONFIG_STM32L4_SRAM3_HEAP
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SRAM3_HEAP)
|
||||
/* TODO: better check here */
|
||||
# if CONFIG_MM_REGIONS < 3
|
||||
# error you need at least 3 memory manager regions to support SRAM2 and SRAM3
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP)
|
||||
# if CONFIG_MM_REGIONS < 3
|
||||
# error you need at least 3 memory manager regions to support SRAM2 and FSMC
|
||||
|
|
@ -328,8 +349,28 @@ void up_addregion(void)
|
|||
|
||||
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
|
||||
|
||||
#endif /* SRAM2 */
|
||||
|
||||
#ifdef CONFIG_STM32L4_SRAM3_HEAP
|
||||
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the SRAM3 heap */
|
||||
|
||||
stm32l4_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END-SRAM3_START);
|
||||
|
||||
#endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)SRAM3_START, SRAM3_END-SRAM3_START);
|
||||
|
||||
/* Add the SRAM2 user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)SRAM3_START, SRAM3_END-SRAM3_START);
|
||||
|
||||
#endif /* SRAM3 */
|
||||
|
||||
#ifdef CONFIG_STM32L4_FSMC_SRAM_HEAP
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@
|
|||
# else
|
||||
# error "No DMA channel for DAC1"
|
||||
# endif
|
||||
# define HAVE_DMA
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_DAC2_DMA
|
||||
# if defined(CONFIG_STM32L4_DMA1)
|
||||
|
|
@ -149,8 +150,8 @@
|
|||
# else
|
||||
# error "No DMA channel for DAC2"
|
||||
# endif
|
||||
# define HAVE_DMA
|
||||
#endif
|
||||
#define HAVE_DMA
|
||||
|
||||
/* Timer configuration. The STM32L4 supports 8 different trigger for DAC
|
||||
* output:
|
||||
|
|
|
|||
|
|
@ -51,6 +51,8 @@
|
|||
# include "chip/stm32l4x5xx_dbgmcu.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_dbgmcu.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_dbgmcu.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -49,8 +49,8 @@
|
|||
* TODO: do we need separate implementation for STM32L4X3?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
#include "stm32l4x6xx_dma.c"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
|
|
|
|||
|
|
@ -55,6 +55,8 @@
|
|||
# include "chip/stm32l4x5xx_dma.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_dma.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_dma.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -53,6 +53,8 @@
|
|||
# include "chip/stm32l4x5xx_firewall.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_firewall.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_firewall.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -63,8 +63,8 @@
|
|||
|
||||
#include "up_arch.h"
|
||||
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6))
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR))
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
|
||||
|
|
@ -85,7 +85,13 @@
|
|||
#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4)
|
||||
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
|
||||
#define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
|
||||
#if FLASH_PAGE_SIZE == 2048
|
||||
# define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
|
||||
#elif FLASH_PAGE_SIZE == 8192
|
||||
# define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */
|
||||
#else
|
||||
# error Unsupported STM32L4_FLASH_PAGESIZE
|
||||
#endif
|
||||
#define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT)
|
||||
|
||||
#define FLASH_CR_PAGE_ERASE FLASH_CR_PER
|
||||
|
|
|
|||
|
|
@ -54,8 +54,8 @@
|
|||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4_gpio.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
|
|
|
|||
|
|
@ -85,6 +85,8 @@
|
|||
# include "stm32l4x5xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "stm32l4x6xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "stm32l4xrxx_rcc.c"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -51,6 +51,8 @@
|
|||
# include "chip/stm32l4x5xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@
|
|||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6)
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
|
|
|
|||
960
arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
Normal file
960
arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
Normal file
|
|
@ -0,0 +1,960 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Sebastien Lorquet <sebastien@lorquet.fr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/stm32l4/chip.h>
|
||||
|
||||
#include "stm32l4_pwr.h"
|
||||
#include "stm32l4_flash.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Allow up to 100 milliseconds for the high speed clock to become ready.
|
||||
* that is a very long delay, but if the clock does not become ready we are
|
||||
* hosed anyway. Normally this is very fast, but I have seen at least one
|
||||
* board that required this long, long timeout for the HSE to be ready.
|
||||
*/
|
||||
|
||||
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
/* Same for HSI and MSI */
|
||||
|
||||
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
|
||||
#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
|
||||
|
||||
/* HSE divisor to yield ~1MHz RTC clock */
|
||||
|
||||
#define HSE_DIVISOR (STM32L4_HSE_FREQUENCY + 500000) / 1000000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_reset
|
||||
*
|
||||
* Description:
|
||||
* Reset the RCC clock configuration to the default reset state
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_reset(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable the Internal High Speed clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_HSION;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Reset CFGR register */
|
||||
|
||||
putreg32(0x00000000, STM32L4_RCC_CFGR);
|
||||
|
||||
/* Reset HSION, HSEON, CSSON and PLLON bits */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Reset PLLCFGR register to reset default */
|
||||
|
||||
putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG);
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval &= ~RCC_CR_HSEBYP;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0x00000000, STM32L4_RCC_CIER);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB1ENR register to enable the
|
||||
* selected AHB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_AHB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32L4_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DMA2
|
||||
/* DMA 2 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_CRC
|
||||
/* CRC clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_CRCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TSC
|
||||
/* TSC clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_TSCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DMA2D
|
||||
/* DMA2D clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA2DEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB2ENR register to enabled the
|
||||
* selected AHB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_AHB2ENR);
|
||||
|
||||
/* Enable GPIOA, GPIOB, .... GPIOI */
|
||||
|
||||
#if STM32L4_NPORTS > 0
|
||||
regval |= (RCC_AHB2ENR_GPIOAEN
|
||||
#if STM32L4_NPORTS > 1
|
||||
| RCC_AHB2ENR_GPIOBEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 2
|
||||
| RCC_AHB2ENR_GPIOCEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 3
|
||||
| RCC_AHB2ENR_GPIODEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 4
|
||||
| RCC_AHB2ENR_GPIOEEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 5
|
||||
| RCC_AHB2ENR_GPIOFEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 6
|
||||
| RCC_AHB2ENR_GPIOGEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 7
|
||||
| RCC_AHB2ENR_GPIOHEN
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 8
|
||||
| RCC_AHB2ENR_GPIOIEN
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_OTGFS
|
||||
/* USB OTG FS clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_OTGFSEN;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_ADC1)
|
||||
/* ADC clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_ADCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DCMI
|
||||
/* Digital Camera interfaces clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_DCMIEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_AES
|
||||
/* Cryptographic modules clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_AESEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_HASH
|
||||
/* HASH module clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_HASHEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_RNG
|
||||
/* Random number generator clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_RNGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SDMMC
|
||||
/* SDMMC clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb3
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB3 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb3(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB3ENR register to enabled the
|
||||
* selected AHB3 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_AHB3ENR);
|
||||
|
||||
#ifdef CONFIG_STM32L4_FSMC
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB1ENR register to enabled the
|
||||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR1);
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM2
|
||||
/* TIM2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_TIM2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM3
|
||||
/* TIM3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_TIM3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM4
|
||||
/* TIM4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_TIM4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM5
|
||||
/* TIM5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_TIM5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM6
|
||||
/* TIM6 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_TIM6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM7
|
||||
/* TIM7 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_TIM7EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_LCD
|
||||
/* LCD clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_LCDEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SPI2
|
||||
/* SPI2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SPI3
|
||||
/* SPI3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_SPI3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART2
|
||||
/* USART 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_USART2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART3
|
||||
/* USART3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_USART3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_UART4
|
||||
/* UART4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_UART4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_UART5
|
||||
/* UART5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_UART5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_I2C1
|
||||
/* I2C1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_I2C1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_I2C2
|
||||
/* I2C2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_I2C2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_I2C3
|
||||
/* I2C3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_I2C3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_CAN1
|
||||
/* CAN 1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_CAN1EN;
|
||||
#endif
|
||||
|
||||
/* Power interface clock enable. The PWR block is always enabled so that
|
||||
* we can set the internal voltage regulator as required.
|
||||
*/
|
||||
|
||||
regval |= RCC_APB1ENR1_PWREN;
|
||||
|
||||
#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2)
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_DAC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_OPAMP
|
||||
/* OPAMP clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_OPAMPEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_LPTIM1
|
||||
/* Low power timer 1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR1_LPTIM1EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
|
||||
|
||||
/* Second APB1 register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR2);
|
||||
|
||||
#ifdef CONFIG_STM32L4_LPUART1
|
||||
/* Low power uart clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR2_LPUART1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_I2C4
|
||||
/* I2C4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR2_I2C4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_LPTIM2
|
||||
/* Low power timer 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR2_LPTIM2EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB2ENR);
|
||||
|
||||
#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP)
|
||||
/* System configuration controller, comparators, and voltage reference buffer
|
||||
* clock enable
|
||||
*/
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_FIREWALL
|
||||
/* Firewall clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_FWEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM1
|
||||
/* TIM1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SPI1
|
||||
/* SPI1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM8
|
||||
/* TIM8 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM8EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART1
|
||||
/* USART1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM15
|
||||
/* TIM15 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM15EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM16
|
||||
/* TIM16 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM16EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_TIM17
|
||||
/* TIM17 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM17EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SAI1
|
||||
/* SAI1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SAI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SAI2
|
||||
/* SAI2 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SAI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DFSDM1
|
||||
/* DFSDM clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_DFSDMEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableccip
|
||||
*
|
||||
* Description:
|
||||
* Set peripherals independent clock configuration.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableccip(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Certain peripherals have no clock selected even when their enable bit is
|
||||
* set. Set some defaults in the CCIPR register so those peripherals
|
||||
* will at least have a clock.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CCIPR);
|
||||
|
||||
#if defined(STM32L4_USE_CLK48)
|
||||
/* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
|
||||
* and then we can also do away with STM32L4_USE_CLK48, and give better
|
||||
* warning messages.
|
||||
*/
|
||||
|
||||
regval |= STM32L4_CLK48_SEL;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_ADC1)
|
||||
/* Select SYSCLK as ADC clock source */
|
||||
|
||||
regval |= RCC_CCIPR_ADCSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_CCIPR);
|
||||
|
||||
/* Some peripherals have their clock selection in CCIPR2 register. */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CCIPR2);
|
||||
|
||||
#ifdef CONFIG_STM32L4_DFSDM1
|
||||
/* Select SAI1 as DFSDM audio clock source. */
|
||||
|
||||
regval |= RCC_CCIPR2_ADFSDMSEL_SAI1;
|
||||
|
||||
/* Select SYSCLK as DFSDM kernel clock source. */
|
||||
|
||||
regval |= RCC_CCIPR2_DFSDMSEL_PCLK;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_CCIPR2);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
* NOTE: This logic would need to be extended if you need to select low-
|
||||
* power clocking modes!
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG
|
||||
static void stm32l4_stdclockconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
|
||||
#ifdef STM32L4_BOARD_USEHSI
|
||||
/* Enable Internal High-Speed Clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_HSION; /* Enable HSI */
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the HSI is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined(STM32L4_BOARD_USEMSI)
|
||||
/* Enable Internal Multi-Speed Clock (MSI) */
|
||||
|
||||
/* Wait until the MSI is either off or ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* setting MSIRANGE */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the MSI is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the MSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined(STM32L4_BOARD_USEHSE)
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSERDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
|
||||
# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined
|
||||
|
||||
#endif
|
||||
|
||||
/* Check for a timeout. If this timeout occurs, then we are hosed. We
|
||||
* have no real back-up plan, although the following logic makes it look
|
||||
* as though we do.
|
||||
*/
|
||||
|
||||
if (timeout > 0)
|
||||
{
|
||||
#warning todo: regulator voltage according to clock freq
|
||||
#if 0
|
||||
/* Ensure Power control is enabled before modifying it. */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR);
|
||||
|
||||
/* Select regulator voltage output Scale 1 mode to support system
|
||||
* frequencies up to 168 MHz.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_PWR_CR);
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
putreg32(regval, STM32L4_PWR_CR);
|
||||
#endif
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32L4_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32L4_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32L4_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_STM32L4_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
||||
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
#endif
|
||||
|
||||
/* Set the PLL source and main divider */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_PLLCFG);
|
||||
|
||||
/* Configure Main PLL */
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP
|
||||
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLPEN;
|
||||
#endif
|
||||
#ifdef STM32L4_PLLCFG_PLLQ_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLQEN;
|
||||
#endif
|
||||
#ifdef STM32L4_PLLCFG_PLLR_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLREN;
|
||||
#endif
|
||||
|
||||
/* XXX The choice of clock source to PLL (all three) is independent
|
||||
* of the sys clock source choice, review the STM32L4_BOARD_USEHSI
|
||||
* name; probably split it into two, one for PLL source and one
|
||||
* for sys clock source.
|
||||
*/
|
||||
|
||||
#ifdef STM32L4_BOARD_USEHSI
|
||||
regval |= RCC_PLLCFG_PLLSRC_HSI;
|
||||
#elif defined(STM32L4_BOARD_USEMSI)
|
||||
regval |= RCC_PLLCFG_PLLSRC_MSI;
|
||||
#else /* if STM32L4_BOARD_USEHSE */
|
||||
regval |= RCC_PLLCFG_PLLSRC_HSE;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_PLLCFG);
|
||||
|
||||
/* Enable the main PLL */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32L4_SAI1PLL
|
||||
/* Configure SAI1 PLL */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_PLLSAI1CFG);
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the SAI1 PLL */
|
||||
|
||||
regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP
|
||||
| STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLSAI1CFG_PLLPEN;
|
||||
#endif
|
||||
#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
|
||||
regval |= RCC_PLLSAI1CFG_PLLQEN;
|
||||
#endif
|
||||
#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED
|
||||
regval |= RCC_PLLSAI1CFG_PLLREN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_PLLSAI1CFG);
|
||||
|
||||
/* Enable the SAI1 PLL */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAI1ON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_SAI2PLL
|
||||
/* Configure SAI2 PLL */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_PLLSAI2CFG);
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the SAI2 PLL */
|
||||
|
||||
regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP |
|
||||
STM32L4_PLLSAI2CFG_PLLR);
|
||||
|
||||
#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLSAI2CFG_PLLPEN;
|
||||
#endif
|
||||
#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
||||
regval |= RCC_PLLSAI2CFG_PLLREN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_PLLSAI2CFG);
|
||||
|
||||
/* Enable the SAI2 PLL */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAI2ON;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32L4_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
putreg32(regval, STM32L4_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= RCC_CFGR_SW_PLL;
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
stm32l4_rcc_enablelsi();
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4_USE_LSE)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if the MCO1 pin selects LSE as source.
|
||||
* XXX and other cases, like automatic trimming of MSI for USB use
|
||||
*/
|
||||
|
||||
/* ensure Power control is enabled since it is indirectly required
|
||||
* to alter the LSE parameters.
|
||||
*/
|
||||
stm32l4_pwr_enableclk(true);
|
||||
|
||||
/* XXX other LSE settings must be made before turning on the oscillator
|
||||
* and we need to ensure it is first off before doing so.
|
||||
*/
|
||||
|
||||
/* Turn on the LSE oscillator
|
||||
* XXX this will almost surely get moved since we also want to use
|
||||
* this for automatically trimming MSI, etc.
|
||||
*/
|
||||
|
||||
stm32l4_rcc_enablelse();
|
||||
|
||||
# if defined(STM32L4_BOARD_USEMSI)
|
||||
/* Now that LSE is up, auto trim the MSI */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval |= RCC_CR_MSIPLLEN;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
# endif
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableperipherals
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableperipherals(void)
|
||||
{
|
||||
rcc_enableccip();
|
||||
rcc_enableahb1();
|
||||
rcc_enableahb2();
|
||||
rcc_enableahb3();
|
||||
rcc_enableapb1();
|
||||
rcc_enableapb2();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
Loading…
Reference in a new issue