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Adding STM32H5 arch files. With comments addressed.

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Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.

Remove board/docs changes for PR update.

Squash commits into one for PR guideline conformity.

trying to fix build issues

Fix format from review
This commit is contained in:
parallels 2024-10-07 14:57:06 -05:00 committed by Xiang Xiao
parent 6a0c239c8e
commit 2b110ab64e
28 changed files with 5355 additions and 0 deletions
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20
arch/arm/Kconfig
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@ -524,6 +524,22 @@ config ARCH_CHIP_STM32L4
---help---
STMicro STM32 architectures (ARM Cortex-M4).
config ARCH_CHIP_STM32H5
bool "STMicro STM32 H5"
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_TRUSTZONE
select ARM_HAVE_MPU_UNIFIED
select ARMV8M_HAVE_STACKCHECK
---help---
STMicro STM32 H5 architectures (ARM Cortex-M33).
config ARCH_CHIP_STM32L5
bool "STMicro STM32 L5"
select ARCH_CORTEXM33
@ -1123,6 +1139,7 @@ config ARCH_CHIP
default "stm32f7" if ARCH_CHIP_STM32F7
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
default "stm32h5" if ARCH_CHIP_STM32H5
default "stm32l5" if ARCH_CHIP_STM32L5
default "stm32u5" if ARCH_CHIP_STM32U5
default "stm32wb" if ARCH_CHIP_STM32WB
@ -1593,6 +1610,9 @@ endif
if ARCH_CHIP_STM32L4
source "arch/arm/src/stm32l4/Kconfig"
endif
if ARCH_CHIP_STM32H5
source "arch/arm/src/stm32h5/Kconfig"
endif
if ARCH_CHIP_STM32L5
source "arch/arm/src/stm32l5/Kconfig"
endif

104
arch/arm/include/stm32h5/chip.h Normal file
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@ -0,0 +1,104 @@
/****************************************************************************
* arch/arm/include/stm32h5/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32H5_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32H5_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
#else
# error "Unsupported STM32H5 chip"
#endif
#define STM32H5_NFSMC (1) /* Have FSMC memory controller */
#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */
#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */
#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */
#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */
#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */
#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
#define STM32H5_NRNG (1) /* Random number generator (RNG) */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NUART (2) /* UART 4-5 */
# define STM32H5_NUSART (4) /* USART 1-3, 6*/
#endif
#define STM32H5_NLPUART (1) /* LPUART 1 */
#define STM32H5_QSPI (0) /* No QuadSPI1 */
#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NSPI (6) /* SPI1-SPI6 */
# define STM32H5_NI2C (4) /* I2C1-4 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NSPI (3) /* SPI1-SPI3 */
# define STM32H5_NI2C (3) /* I2C1-3 */
#endif
#define STM32H5_NSWPMI (0) /* No SWPMI1 */
#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */
#define STM32H5_NUSBFS (1) /* No USB FS */
#define STM32H5_NCAN (2) /* CAN1 */
#define STM32H5_NSAI (2) /* SAI1-2 */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NSDMMC (2) /* SDMMC interface */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NSDMMC (1) /* SDMMC interface */
#endif
#define STM32H5_NDMA (2) /* DMA1-2 */
#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */
#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */
#define STM32H5_NDAC (1) /* 12-bit DAC1 */
#define STM32H5_NCRC (1) /* CRC */
#define STM32H5_NCOMP (0) /* Comparators */
#define STM32H5_NOPAMP (0) /* Operational Amplifiers */
/* NVIC priority levels *****************************************************/
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */

100
arch/arm/include/stm32h5/irq.h Normal file
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@ -0,0 +1,100 @@
/****************************************************************************
* arch/arm/include/stm32h5/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32H5_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32H5_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are
* chip-specific
*/
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include <arch/stm32h5/stm32h5xx_irq.h>
#else
# error "Unsupported STM32 H5 chip"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32H5_IRQ_H */

208
arch/arm/include/stm32h5/stm32h5xx_irq.h Normal file
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@ -0,0 +1,208 @@
/****************************************************************************
* arch/arm/include/stm32h5/stm32h5xx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32H5_STM32H5XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32H5_STM32H5XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in arch/arm/include/stm32h5/irq.h.
*
* External interrupts (vectors >= 16)
*
* These interrupts vectors was implemented based on RM0481 Table 145
* (STM32H53xxx and STM32H53xxx vector table)
*
*/
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD_AVD (STM32_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */
# define STM32_IRQ_RTC (STM32_IRQ_FIRST + 2) /* 2: RTC global interrupts */
# define STM32_IRQ_RTC_S (STM32_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */
# define STM32_IRQ_TAMP (STM32_IRQ_FIRST + 4) /* 4: Tamper global interrupt */
# define STM32_IRQ_RAMCFG (STM32_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */
# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */
# define STM32_IRQ_FLASH_S (STM32_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */
# define STM32_IRQ_GTZC (STM32_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */
# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 9) /* 9: RCC global interrupt */
# define STM32_IRQ_RCC_S (STM32_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */
# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */
# define STM32_IRQ_EXTI5 (STM32_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */
# define STM32_IRQ_EXTI6 (STM32_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */
# define STM32_IRQ_EXTI7 (STM32_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */
# define STM32_IRQ_EXTI8 (STM32_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */
# define STM32_IRQ_EXTI9 (STM32_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */
# define STM32_IRQ_EXTI10 (STM32_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */
# define STM32_IRQ_EXTI11 (STM32_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */
# define STM32_IRQ_EXTI12 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */
# define STM32_IRQ_EXTI13 (STM32_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */
# define STM32_IRQ_EXTI14 (STM32_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */
# define STM32_IRQ_EXTI15 (STM32_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */
# define STM32_IRQ_GPDMA1_CH0 (STM32_IRQ_FIRST + 27) /* 27: GPDMA1_CH0 global interrupt */
# define STM32_IRQ_GPDMA1_CH1 (STM32_IRQ_FIRST + 28) /* 28: GPDMA1_CH1 global interrupt */
# define STM32_IRQ_GPDMA1_CH2 (STM32_IRQ_FIRST + 29) /* 29: GPDMA1_CH2 global interrupt */
# define STM32_IRQ_GPDMA1_CH3 (STM32_IRQ_FIRST + 30) /* 30: GPDMA1_CH3 global interrupt */
# define STM32_IRQ_GPDMA1_CH4 (STM32_IRQ_FIRST + 31) /* 31: GPDMA1_CH4 global interrupt */
# define STM32_IRQ_GPDMA1_CH5 (STM32_IRQ_FIRST + 32) /* 32: GPDMA1_CH5 global interrupt */
# define STM32_IRQ_GPDMA1_CH6 (STM32_IRQ_FIRST + 33) /* 33: GPDMA1_CH6 global interrupt */
# define STM32_IRQ_GPDMA1_CH7 (STM32_IRQ_FIRST + 34) /* 34: GPDMA1_CH7 global interrupt */
# define STM32_IRQ_IWDG (STM32_IRQ_FIRST + 35) /* 35: IWDG global interrupt */
# define STM32_IRQ_SAES (STM32_IRQ_FIRST + 36) /* 36: SAES global interrupt */
# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */
# define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */
# define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */
# define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */
# define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
# define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
# define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
# define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */
# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */
# define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 51) /* 51: I2C1 Event */
# define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 52) /* 52: I2C1 Error */
# define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 53) /* 53: I2C2 Event */
# define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 54) /* 54: I2C2 Error */
# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 55) /* 55: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 56) /* 56: SPI2 global interrupt */
# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 57) /* 57: SPI3 global interrupt */
# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 58) /* 58: USART1 error interrupt */
# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 59) /* 59: USART2 global interrupt */
# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 60) /* 60: USART3 global interrupt */
# define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 61) /* 61: UART4 global interrupt */
# define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 62) /* 62: UART5 global interrupt */
# define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */
# define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */
# define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */
# define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */
# define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */
# define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */
# define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */
# define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */
# define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */
# define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */
#endif
# define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 74) /* 74: USB_FS global interrupt */
# define STM32_IRQ_CRS (STM32_IRQ_FIRST + 75) /* 75: CRS global interrupt */
# define STM32_IRQ_UCPD1 (STM32_IRQ_FIRST + 76) /* 76: UCPD1 global interrupt */
# define STM32_IRQ_FMC (STM32_IRQ_FIRST + 77) /* 77: FMC global interrupt */
# define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 78) /* 78: OCTOSPI1 global interrupt */
# define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 79) /* 79: SDMMC1 global interrupt */
# define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */
# define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */
# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */
# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */
#endif
# define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 85) /* 85: USART6 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 86) /* 86: USART10 global interrupt */
# define STM32_IRQ_USART11 (STM32_IRQ_FIRST + 87) /* 87: USART11 global interrupt */
# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */
# define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 89) /* 89: SAI2 global interrupt */
#endif
# define STM32_IRQ_GPDMA2_CH0 (STM32_IRQ_FIRST + 90) /* 90: GPDMA2_CH0 global interrupt */
# define STM32_IRQ_GPDMA2_CH1 (STM32_IRQ_FIRST + 91) /* 91: GPDMA2_CH1 global interrupt */
# define STM32_IRQ_GPDMA2_CH2 (STM32_IRQ_FIRST + 92) /* 92: GPDMA2_CH2 global interrupt */
# define STM32_IRQ_GPDMA2_CH3 (STM32_IRQ_FIRST + 93) /* 93: GPDMA2_CH3 global interrupt */
# define STM32_IRQ_GPDMA2_CH4 (STM32_IRQ_FIRST + 94) /* 94: GPDMA2_CH4 global interrupt */
# define STM32_IRQ_GPDMA2_CH5 (STM32_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */
# define STM32_IRQ_GPDMA2_CH6 (STM32_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */
# define STM32_IRQ_GPDMA2_CH7 (STM32_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 98) /* 98: UART7 global interrupt */
# define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 99) /* 99: UART8 global interrupt */
# define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 100) /* 100: UART9 global interrupt */
# define STM32_IRQ_UART12 (STM32_IRQ_FIRST + 101) /* 101: UART12 global interrupt */
# define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 102) /* 102: SDMMC2 global interrupt */
#endif
# define STM32_IRQ_FPU (STM32_IRQ_FIRST + 103) /* 103: FPU global interrupt */
# define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */
# define STM32_IRQ_DCACHE (STM32_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_ETH (STM32_IRQ_FIRST + 106) /* 106: ETH global interrupt */
# define STM32_IRQ_ETH_WKUP (STM32_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */
#endif
# define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */
# define STM32_IRQ_FDCAN2_IT0 (STM32_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */
# define STM32_IRQ_FDCAN2_IT1 (STM32_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */
# define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 112) /* 112: FMAC global interrupt */
#endif
# define STM32_IRQ_DTS (STM32_IRQ_FIRST + 113) /* 113: DTS global interrupt */
# define STM32_IRQ_RNG (STM32_IRQ_FIRST + 114) /* 114: RNG global interrupt */
# define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 115) /* 115: OTFDEC1 global interrupt */
# define STM32_IRQ_AES (STM32_IRQ_FIRST + 116) /* 116: AES global interrupt */
# define STM32_IRQ_HASH (STM32_IRQ_FIRST + 117) /* 117: HASH global interrupt */
# define STM32_IRQ_PKA (STM32_IRQ_FIRST + 118) /* 118: PKA global interrupt */
# define STM32_IRQ_CEC (STM32_IRQ_FIRST + 119) /* 119: CEC global interrupt */
# define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */
# define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */
#endif
# define STM32_IRQ_I3C1_EV (STM32_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */
# define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */
# define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */
# define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */
# define STM32_IRQ_LPTIM4 (STM32_IRQ_FIRST + 128) /* 128: LPTIM4 global interrupt */
# define STM32_IRQ_LPTIM5 (STM32_IRQ_FIRST + 129) /* 129: LPTIM5 global interrupt */
# define STM32_IRQ_LPTIM6 (STM32_IRQ_FIRST + 130) /* 130: LPTIM6 global interrupt */
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 131) /* 131: I3C2_EV global interrupt */
# define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 132) /* 132: I3C2_ER global interrupt */
#endif
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_NEXTINTS 131
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32_IRQ_NEXTINTS 133
#endif
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
#endif /* __ARCH_ARM_INCLUDE_STM32H5_STM32H5XX_IRQ_H */

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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

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##############################################################################
# arch/arm/src/stm32h5/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
##############################################################################
# The start-up, "head", file. Only common vectors are support so there
# isn't one.
HEAD_ASRC =
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
include armv8-m/Make.defs

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/****************************************************************************
* arch/arm/src/stm32h5/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_CHIP_H
#define __ARCH_ARM_SRC_STM32H5_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware
* files should then include this file for the proper setup.
*/
#include <arch/irq.h>
#include <arch/stm32h5/chip.h>
#include "hardware/stm32_pinmap.h"
#include "hardware/stm32_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If the common ARMv8-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/stm32h5/chip.h header file.
*/
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
#endif /* __ARCH_ARM_SRC_STM32H5_CHIP_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_crs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_CRS_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */
#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
/* Register Addresses *******************************************************/
#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET)
#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET)
#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET)
#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* CRS control register */
#define CRS_CR_SYNCOKIE (1 << 0) /* Bit 0: SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE (1 << 1) /* Bit 1: SYNC warning interrupt enable */
#define CRS_CR_ERRIE (1 << 2) /* Bit 2: Synchronization or Trimming error interrupt enabled */
#define CRS_CR_ESYNCIE (1 << 3) /* Bit 3: Expected SYNC interrupt enable */
#define CRS_CR_CEN (1 << 5) /* Bit 5: Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN (1 << 6) /* Bit 6: Automatic trimming enabled */
#define CRS_CR_SWSYNC (1 << 7) /* Bit 7: Generate software SYNC event */
#define CRS_CR_TRIM_SHIFT 8 /* Bits 8-13: HSI48 oscillator smooth trimming */
#define CRS_CR_TRIM_MASK (0x3f << CRS_CR_TRIM_SHIFT)
/* CRS configuration register */
#define CRS_CFGR_RELOAD_SHIFT 0 /* Bits 0-15: Counter reload value */
#define CRS_CFGR_RELOAD_MASK (0xffff << CRS_CFGR_RELOAD_SHIFT)
#define CRS_CFGR_FELIM_SHIFT 16 /* Bits 16-23: Frequency error limit */
#define CRS_CFGR_FELIM_MASK (0xff << CRS_CFGR_FELIM_SHIFT)
#define CRS_CFGR_SYNCDIV_SHIFT 24 /* Bits 24-26: SYNC divider */
#define CRS_CFGR_SYNCDIV_MASK (7 << CRS_CFGR_SYNCDIV_SHIFT)
# define CRS_CFGR_SYNCDIV_d1 (0 << CRS_CFGR_SYNCDIV_SHIFT) /* Not divided */
# define CRS_CFGR_SYNCDIV_d2 (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2 */
# define CRS_CFGR_SYNCDIV_d4 (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4 */
# define CRS_CFGR_SYNCDIV_d8 (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8 */
# define CRS_CFGR_SYNCDIV_d16 (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16 */
# define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */
# define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */
# define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */
#define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT)
# define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */
# define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */
# define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */
#define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */
/* CRS interrupt and status register */
#define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */
#define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */
#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Errot flag */
#define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */
#define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */
#define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */
#define CRS_ISR_TRIMOVF (1 << 10) /* Bit 10: Trimming overflow or underflow */
#define CRS_ISR_FEDIR (1 << 15) /* Bit 15: Frequency error direction */
#define CRS_ISR_FECAP_SHIFT 16 /* Bits 16-31: Frequency error capture */
#define CRS_ISR_FECAP_MASK (0xffff << CRS_ISR_FECAP_SHIFT)
/* CRS interrupt flag clear register */
#define CRS_ICR_SYNCOKC (1 << 0) /* Bit 0: SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC (1 << 1) /* Bit 1: SYNC warning clear flag */
#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */
#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_CRS_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DBGMCU_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Addresses *******************************************************/
#define STM32_DBGMCU_IDCODE 0xe0044000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0044004 /* MCU debug */
#define STM32_DBGMCU_APB1L_FZ 0xe0044008 /* Debug MCU APB1L freeze register */
#define STM32_DBGMCU_APB1H_FZ 0xe004400c /* Debug MCU APB1H freeze register */
#define STM32_DBGMCU_APB2_FZ 0xe0044010 /* Debug MCU APB2 freeze register */
#define STM32_DBGMCU_APB3_FZ 0xe0044014 /* Debug MCU APB3 freeze register */
#define STM32_DBGMCU_AHB1_FZ 0xe0044020 /* Debug MCU AHB1 freeze register */
#define STM32_DBGMCU_SR 0xe00440fc /* Debug MCU Status Register */
#define STM32_DBGMCU_DBG_AUTH_HOST 0xe0044100 /* Debug MCU Authorization Host Register */
#define STM32_DBGMCU_DBG_AUTH_DEVICE 0xe0044104 /* Debug MCU Authorization Device Register */
#define STM32_DBGMCU_DBG_AUTH_ACK 0xe0044108 /* Debug MCU Authorization Acknowledge Register */
#define STM32_DBGMCU_PIDR4 0xe0044fd0 /* Debug MCU CoreSight Peripheral Identity Register 4 */
#define STM32_DBGMCU_PIDR0 0xe0044fe0 /* Debug MCU CoreSight Peripheral Identity Register 0 */
#define STM32_DBGMCU_PIDR1 0xe0044fe4 /* Debug MCU CoreSight Peripheral Identity Register 1 */
#define STM32_DBGMCU_PIDR2 0xe0044fe8 /* Debug MCU CoreSight Peripheral Identity Register 2 */
#define STM32_DBGMCU_PIDR3 0xe0044fec /* Debug MCU CoreSight Peripheral Identity Register 3 */
#define STM32_DBGMCU_CIDR0 0xe0044ff0 /* Debug MCU CoreSight Component Identity Register 0 */
#define STM32_DBGMCU_CIDR1 0xe0044ff4 /* Debug MCU CoreSight Component Identity Register 1 */
#define STM32_DBGMCU_CIDR2 0xe0044ff8 /* Debug MCU CoreSight Component Identity Register 2 */
#define STM32_DBGMCU_CIDR3 0xe0044ffc /* Debug MCU CoreSight Component Identity Register 3 */
/* Register Bitfield Definitions ********************************************/
/* MCU identifier */
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
/* MCU debug */
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Allows debug in Stop mode */
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Allows debug in Standby mode */
#define DBGMCU_CR_TRACEIOEN (1 << 4) /* Bit 4: Trace pin enable */
#define DBGMCU_CR_TRACEEN (1 << 5) /* Bit 5: Trace port and clock enable */
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
#define DBGMCU_CR_DCRT (1 << 16) /* Bit 16: Debug credentials reset type */
/* Debug MCU APB1L freeze register */
#define DBGMCU_APB1L_TIM2_STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
#define DBGMCU_APB1L_TIM3_STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
#define DBGMCU_APB1L_TIM4_STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
#define DBGMCU_APB1L_TIM5_STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
#define DBGMCU_APB1L_TIM6_STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
#define DBGMCU_APB1L_TIM7_STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
#define DBGMCU_APB1L_TIM12_STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */
#define DBGMCU_APB1L_TIM13_STOP (1 << 7) /* Bit 6: TIM12 stopped when core is halted */
#define DBGMCU_APB1L_TIM14_STOP (1 << 8) /* Bit 6: TIM12 stopped when core is halted */
#define DBGMCU_APB1L_WWDG_STOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
#define DBGMCU_APB1L_IWDG_STOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
#define DBGMCU_APB1L_I2C1_STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1L_I2C2_STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1L_I3C1_STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
/* Debug MCU APB1H freeze register */
#define DBGMCU_APB1H_LPTIM2_STOP (1 << 5) /* Bit 5: LPTIM2 stopped when core is halted */
/* Debug MCU APB2 freeze register */
#define DBGMCU_APB2_TIM1_STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
#define DBGMCU_APB2_TIM8_STOP (1 << 13) /* Bit 13: TIM8 stopped when core is halted */
#define DBGMCU_APB2_TIM15_STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
#define DBGMCU_APB2_TIM16_STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
#define DBGMCU_APB2_TIM17_STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
/* Debug MCU APB3 freeze register */
#define DBGMCU_APB3_I2C3_STOP (1 << 10) /* Bit 10: I2C3 SMBUS stop in debug */
#define DBGMCU_APB3_I2C4_STOP (1 << 11) /* Bit 11: I2C4 SMBUS stop in debug */
#define DBGMCU_APB3_LPTIM1_STOP (1 << 17) /* Bit 17: LPTIM1 stopped in debug */
#define DBGMCU_APB3_LPTIM3_STOP (1 << 18) /* Bit 18: LPTIM3 stopped in debug */
#define DBGMCU_APB3_LPTIM4_STOP (1 << 19) /* Bit 19: LPTIM4 stopped in debug */
#define DBGMCU_APB3_LPTIM5_STOP (1 << 20) /* Bit 20: LPTIM5 stopped in debug */
#define DBGMCU_APB3_LPTIM6_STOP (1 << 21) /* Bit 21: LPTIM6 stopped in debug */
#define DBGMCU_APB3_DBG_RTC_STOP (1 << 30) /* Bit 30: RTC stopped in debug */
/* Debug MCU AHB1 freeze register */
#define DBGMCU_AHB1_GPDMA1_0_STOP (1 << 0) /* Bit 0: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_1_STOP (1 << 1) /* Bit 1: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_2_STOP (1 << 2) /* Bit 2: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_3_STOP (1 << 3) /* Bit 3: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_4_STOP (1 << 4) /* Bit 4: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_5_STOP (1 << 5) /* Bit 5: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_6_STOP (1 << 6) /* Bit 6: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA1_7_STOP (1 << 7) /* Bit 7: GPDMA1 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA2_0_STOP (1 << 16) /* Bit 16: GPDMA2 Channel 0 stop in debug */
#define DBGMCU_AHB1_GPDMA2_1_STOP (1 << 17) /* Bit 17: GPDMA2 Channel 1 stop in debug */
#define DBGMCU_AHB1_GPDMA2_2_STOP (1 << 18) /* Bit 18: GPDMA2 Channel 2 stop in debug */
#define DBGMCU_AHB1_GPDMA2_3_STOP (1 << 19) /* Bit 19: GPDMA2 Channel 3 stop in debug */
#define DBGMCU_AHB1_GPDMA2_4_STOP (1 << 20) /* Bit 20: GPDMA2 Channel 4 stop in debug */
#define DBGMCU_AHB1_GPDMA2_5_STOP (1 << 21) /* Bit 21: GPDMA2 Channel 5 stop in debug */
#define DBGMCU_AHB1_GPDMA2_6_STOP (1 << 22) /* Bit 22: GPDMA2 Channel 6 stop in debug */
#define DBGMCU_AHB1_GPDMA2_7_STOP (1 << 23) /* Bit 23: GPDMA2 Channel 7 stop in debug */
/* Debug MCU Status Register */
#define DBGMCU_SR_AP_PRESENT_SHIFT (0)
#define DBGMCU_SR_AP_PRESENT_MASK (0xffff << DBGMCU_SR_AP_PRESENT_SHIFT)
#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_MASK
#define DBGMCU_SR_AP_ENABLED_SHIFT (16)
#define DBGMCU_SR_AP_ENABLED_MASK (0xffff << DBGMCU_SR_AP_ENABLED_SHIFT)
#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_MASK
/* Debug MCU Authorization Acknowledge Register */
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT (0)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT (1)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK
/* Debug MCU CoreSight Peripheral Identity Register 4 */
#define DBGMCU_PIDR4_JEP106CON_SHIFT (0)
#define DBGMCU_PIDR4_JEP106CON_MASK (0xf << DBGMCU_PIDR4_JEP106CON_SHIFT)
#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_MASK
#define DBGMCU_PIDR4_SIZE_SHIFT (0)
#define DBGMCU_PIDR4_SIZE_MASK (0xf << DBGMCU_PIDR4_SIZE_SHIFT)
#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_MASK
/* Debug MCU CoreSight Peripheral Identity Register 0 */
#define DBGMCU_PIDR0_PARTNUM_SHIFT (0)
#define DBGMCU_PIDR0_PARTNUM_MASK (0xff << DBGMCU_PIDR0_PARTNUM_SHIFT)
#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_MASK
/* Debug MCU CoreSight Peripheral Identity Register 1 */
#define DBGMCU_PIDR1_PARTNUM_SHIFT (0)
#define DBGMCU_PIDR1_PARTNUM_MASK (0xf << DBGMCU_PIDR1_PARTNUM_SHIFT)
#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_MASK
#define DBGMCU_PIDR1_JEP106ID_SHIFT (4)
#define DBGMCU_PIDR1_JEP106ID_MASK (0xf << DBGMCU_PIDR1_JEP106ID_SHIFT)
#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_MASK
/* Debug MCU CoreSight Peripheral Identity Register 2 */
#define DBGMCU_PIDR2_JEP106ID_SHIFT (0)
#define DBGMCU_PIDR2_JEP106ID_MASK (0x7 << DBGMCU_PIDR2_JEP106ID_SHIFT)
#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_MASK
#define DBGMCU_PIDR2_JEDEC_SHIFT (3)
#define DBGMCU_PIDR2_JEDEC_MASK (0x1 << DBGMCU_PIDR2_JEDEC_SHIFT)
#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_MASK
#define DBGMCU_PIDR2_REVISION_SHIFT (4)
#define DBGMCU_PIDR2_REVISION_MASK (0xf << DBGMCU_PIDR2_REVISION_SHIFT)
#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_MASK
/* Debug MCU CoreSight Peripheral Identity Register 3 */
#define DBGMCU_PIDR3_CMOD_SHIFT (0)
#define DBGMCU_PIDR3_CMOD_MASK (0xf << DBGMCU_PIDR3_CMOD_SHIFT)
#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_MASK
#define DBGMCU_PIDR3_REVAND_SHIFT (4)
#define DBGMCU_PIDR3_REVAND_MASK (0xf << DBGMCU_PIDR3_REVAND_SHIFT)
#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_MASK
/* Debug MCU CoreSight Component Identity Register 0 */
#define DBGMCU_CIDR0_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR0_PREAMBLE_MASK (0xff << DBGMCU_CIDR0_PREAMBLE_SHIFT)
#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_MASK
/* Debug MCU CoreSight Component Identity Register 1 */
#define DBGMCU_CIDR1_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR1_PREAMBLE_MASK (0xf << DBGMCU_CIDR1_PREAMBLE_SHIFT)
#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_MASK
#define DBGMCU_CIDR1_CLASS_SHIFT (4)
#define DBGMCU_CIDR1_CLASS_MASK (0xf << DBGMCU_CIDR1_CLASS_SHIFT)
#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_MASK
/* Debug MCU CoreSight Component Identity Register 2 */
#define DBGMCU_CIDR2_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR2_PREAMBLE_MASK (0xff << DBGMCU_CIDR2_PREAMBLE_SHIFT)
#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_MASK
/* Debug MCU CoreSight Component Identity Register 3 */
#define DBGMCU_CIDR3_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR3_PREAMBLE_MASK (0xff << DBGMCU_CIDR3_PREAMBLE_SHIFT)
#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_MASK
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DBGMCU_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H56XXX)
# include "hardware/stm32h5xxx_flash.h"
#else
# error "Unsupported STM32 H5 flash"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_FLASH_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_gpio.h"
#else
# error "Unsupported STM32 H5 PWR"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPIO_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_i2c.h"
#else
# error "Unsupported STM32 H5 I2C"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_I2C_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_memorymap.h"
#else
# error "Unsupported STM32 H5 memory map"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_PINMAP_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H56XXX)
# include "hardware/stm32h56xxx_pinmap.h"
#else
# error "Unsupported STM32 H5 pin map"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_PINMAP_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_pwr.h"
#else
# error "Unsupported STM32 H5 PWR"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_PWR_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_rcc.h"
#else
# error "Unsupported STM32 H5 rcc"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_uart.h"
#else
# error "Unsupported STM32 H5 uart"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_UART_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Alternate Pin Functions. All members of the STM32H552xx and STM32H562xx
* families share the same pin multiplexing (although they may differ in the
* pins physically available). See DS12736, Table 22 "Alternate Function AF0
* to AF7" and Table 23 "Alternate Function AF8 to AF15".
*
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if FDCAN1_RX connects via PA11 on some board, then the following
* definitions should appear inthe board.h header file for that board:
*
* #define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_1
*
* The driver will then automatically configure PA11 as the FDCAN1 RX pin.
*/
/* ADC */
/* TODO
#define GPIO_ADC12_IN1_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC12_IN2_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
#define GPIO_ADC12_IN3_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
#define GPIO_ADC12_IN4_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
#define GPIO_ADC12_IN5_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
#define GPIO_ADC12_IN6_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ADC12_IN7_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
#define GPIO_ADC12_IN8_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
#define GPIO_ADC12_IN9_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_ADC12_IN10_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_ADC12_IN11_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
#define GPIO_ADC12_IN12_0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ADC12_IN13_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ADC12_IN14_0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
#define GPIO_ADC12_IN15_0 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_ADC12_IN16_0 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
*/
/* FDCAN */
/* TODO
#define GPIO_FDCAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN11)
#define GPIO_FDCAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN8)
#define GPIO_FDCAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN0)
#define GPIO_FDCAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN12)
#define GPIO_FDCAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN9)
#define GPIO_FDCAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN1)
*/
/* Clocks outputs */
#define GPIO_MCO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8)
/* DAC */
/* TODO
#define GPIO_DAC1_OUT_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT_2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
*/
/* I2C */
/* TODO
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1)
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN14)
#define GPIO_I2C1_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTG|GPIO_PIN15)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN8)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN7)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN7)
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN2)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTG|GPIO_PIN6)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN14)
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN11)
#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTF|GPIO_PIN14)
*/
/* JTAG */
#define GPIO_JTCK_SWCLK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
#define GPIO_JTDI_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
#define GPIO_JTDO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
#define GPIO_JTMS_SWDAT_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
#define GPIO_JTRST_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
/* OCTOSPI */
/* TODO
#define GPIO_OSPI_NCS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN4)
#define GPIO_OSPI_NCS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN11)
#define GPIO_OSPI_NCS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN2)
#define GPIO_OSPI_NCS_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
#define GPIO_OSPI_NCS_5 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
#define GPIO_OSPI_NCLK_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN5)
#define GPIO_OSPI_NCLK_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN11)
#define GPIO_OSPI_NCLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
#define GPIO_OSPI_NCLK_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9)
#define GPIO_OSPI_CLK_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN10)
#define GPIO_OSPI_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
#define GPIO_OSPI_CLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
#define GPIO_OSPI_CLK_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
#define GPIO_OSPI_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
#define GPIO_OSPI_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
#define GPIO_OSPI_IO0_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8)
#define GPIO_OSPI_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
#define GPIO_OSPI_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
#define GPIO_OSPI_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
#define GPIO_OSPI_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
#define GPIO_OSPI_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN7)
#define GPIO_OSPI_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
#define GPIO_OSPI_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
#define GPIO_OSPI_IO3_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN6)
#define GPIO_OSPI_IO4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
#define GPIO_OSPI_IO4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
#define GPIO_OSPI_IO4_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4)
#define GPIO_OSPI_IO5_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN11)
#define GPIO_OSPI_IO5_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
#define GPIO_OSPI_IO5_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5)
#define GPIO_OSPI_IO6_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
#define GPIO_OSPI_IO6_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6)
#define GPIO_OSPI_IO7_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN0)
#define GPIO_OSPI_IO7_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
#define GPIO_OSPI_IO7_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7)
#define GPIO_OSPI_DQS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN3)
#define GPIO_OSPI_DQS_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN6)
#define GPIO_OSPI_DQS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1)
#define GPIO_OSPI_DQS_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
*/
/* RTC */
/* TODO
#define GPIO_RTC_REFIN_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15)
*/
/* SAI */
/* TODO
#define GPIO_SAI1_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN0)
#define GPIO_SAI1_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN0)
#define GPIO_SAI1_D1_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN6)
#define GPIO_SAI1_D1_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10)
#define GPIO_SAI1_D1_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN3)
#define GPIO_SAI1_D1_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SAI1_D1_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN6)
#define GPIO_SAI1_D2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN4)
#define GPIO_SAI1_D2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SAI1_D2_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN4)
#define GPIO_SAI1_D3_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN10)
#define GPIO_SAI1_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN5)
#define GPIO_SAI1_CK1_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3)
#define GPIO_SAI1_CK1_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SAI1_CK1_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN2)
#define GPIO_SAI1_CK1_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN7)
#define GPIO_SAI1_CK2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN8)
#define GPIO_SAI1_CK2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN5)
#define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9)
#define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SAI1_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4)
#define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN8)
#define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10)
#define GPIO_SAI1_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5)
#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10)
#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN1)
#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN3)
#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SAI1_SD_A_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6)
#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN3)
#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SAI1_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN2)
#define GPIO_SAI1_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN7)
#define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
#define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN14)
#define GPIO_SAI1_FS_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
#define GPIO_SAI1_FS_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN9)
#define GPIO_SAI1_FS_B_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN9)
#define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN8)
#define GPIO_SAI1_SCK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN8)
#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN13)
#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN3)
#define GPIO_SAI1_SD_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7)
#define GPIO_SAI1_SD_B_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN6)
#define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN10)
#define GPIO_SAI1_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN7)
#define GPIO_SAI2_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN2)
#define GPIO_SAI2_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12)
#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN0)
#define GPIO_SAI2_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN12)
#define GPIO_SAI2_FS_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10)
#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN11)
#define GPIO_SAI2_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9)
#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15)
#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11)
#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SAI2_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN9)
#define GPIO_SAI2_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11)
#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15)
#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN3)
#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN2)
#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN5)
#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN4)
*/
/* SDIO */
/* TODO
#define GPIO_SDMMC1_CKIN_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDMMC1_CDIR_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDMMC1_D0DIR_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDMMC1_D123DIR_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SDMMC1_D0_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDMMC1_D1_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SDMMC1_D2_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SDMMC1_D3_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SDMMC1_D4_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDMMC1_D5_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDMMC1_D5_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN0)
#define GPIO_SDMMC1_D6_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDMMC1_D7_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SDMMC1_CK_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CMD_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2)
*/
/* SPI */
/* TODO
#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4)
#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15)
#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN0)
#define GPIO_SPI1_NSS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN12)
#define GPIO_SPI1_NSS_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN5)
#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN1)
#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5)
#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SPI1_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN13)
#define GPIO_SPI1_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN2)
#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7)
#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN12)
#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI1_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN15)
#define GPIO_SPI1_MOSI_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN4)
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN6)
#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN11)
#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SPI1_MISO_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN14)
#define GPIO_SPI1_MISO_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN3)
#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12)
#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN0)
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN10)
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN1)
#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN3)
#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15)
#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN1)
#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3)
#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN4)
#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN2)
#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
#define GPIO_SPI3_NSS_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN12)
#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN9)
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN11)
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SPI3_MISO_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN10)
*/
/* Timers */
/* TODO
#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10)
#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12)
#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN12)
#define GPIO_TIM1_BKIN_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15)
#define GPIO_TIM1_BKIN_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN15)
#define GPIO_TIM1_BKIN_6 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM1_BKIN2_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_BKIN2_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_BKIN2_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_BKIN2_4 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN12)
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN7)
#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM3_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3)
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM3_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3)
#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4)
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
#define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN2)
#define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN2)
#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
#define GPIO_TIM4_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM8_BKIN_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM8_BKIN_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_BKIN2_3 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM8_BKIN2_4 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
#define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM15_CH1IN_4 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN10)
#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM15_CH1OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
#define GPIO_TIM15_CH2IN_4 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN11)
#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
#define GPIO_TIM15_CH2OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
#define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN12)
#define GPIO_TIM16_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM16_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM17_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1)
#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4)
#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN5)
#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN0)
#define GPIO_LPTIM1_IN1_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN10)
#define GPIO_LPTIM1_IN2_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7)
#define GPIO_LPTIM1_IN2_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN2)
#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN11)
#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN14)
#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN2)
#define GPIO_LPTIM1_OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN1)
#define GPIO_LPTIM1_OUT_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN15)
#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6)
#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN3)
#define GPIO_LPTIM1_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN12)
#define GPIO_LPTIM2_IN1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN1)
#define GPIO_LPTIM2_IN1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN0)
#define GPIO_LPTIM2_IN1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN12)
#define GPIO_LPTIM2_OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN4)
#define GPIO_LPTIM2_OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN8)
#define GPIO_LPTIM2_OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN13)
#define GPIO_LPTIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN5)
#define GPIO_LPTIM2_ETR_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN3)
#define GPIO_LPTIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN11)
#define GPIO_LPTIM3_IN1_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN13)
#define GPIO_LPTIM3_IN1_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN11)
#define GPIO_LPTIM3_IN1_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN3)
#define GPIO_LPTIM3_OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN10)
#define GPIO_LPTIM3_OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN3)
#define GPIO_LPTIM3_OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN5)
#define GPIO_LPTIM3_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN14)
#define GPIO_LPTIM3_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN10)
#define GPIO_LPTIM3_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN4)
*/
/* Trace */
#define GPIO_TRACECK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
#define GPIO_TRACED0_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN1)
#define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
#define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN13)
#define GPIO_TRACED1_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
#define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN14)
#define GPIO_TRACED2_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN2)
#define GPIO_TRACED2_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TRACED3_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN12)
#define GPIO_TRACED3_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
/* UARTs/USARTs */
/* #define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN9)
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN6)
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN10)
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN7)
#define GPIO_USART1_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
#define GPIO_USART1_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5)
#define GPIO_USART1_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
#define GPIO_USART1_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
#define GPIO_USART1_RTS_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
#define GPIO_USART1_RTS_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN3)
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN2)
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN5)
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN3)
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN15)
#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN6)
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7)
#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
#define GPIO_USART2_RTS_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
#define GPIO_USART2_RTS_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
*/
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN10)
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN4)
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN10)
#define GPIO_USART3_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN8)
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN11)
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN5)
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN11)
#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN9)
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN0)
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
#define GPIO_USART3_CK_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10)
#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN6)
#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13)
#define GPIO_USART3_CTS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
#define GPIO_USART3_RTS_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN15)
#define GPIO_USART3_RTS_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN1)
#define GPIO_USART3_RTS_DE_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
#define GPIO_USART3_RTS_DE_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN2)
#define GPIO_USART3_RTS_DE_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
/* #define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN0)
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN10)
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN1)
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN11)
#define GPIO_UART4_CTS_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7)
#define GPIO_UART4_RTS_DE_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15)
#define GPIO_UART5_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN12)
#define GPIO_UART5_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN2)
#define GPIO_UART5_CTS_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN5)
#define GPIO_UART5_RTS_DE_0 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN4)
*/
#define GPIO_LPUART1_TX_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN9)
#define GPIO_LPUART1_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN6)
#define GPIO_LPUART1_RX_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10)
#define GPIO_LPUART1_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7)
#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN11)
#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN12)
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_FLASH_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32H5_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number. This value can be overridden with
* CONFIG_STM32H5_FLASH_OVERRIDE_x
*
* Parts STM32H552xC and STM32H562xC have 256Kb of FLASH
* Parts STM32H552xE and STM32H562xE have 512Kb of FLASH
*
* N.B. Only Single bank mode is supported
*/
#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_I)
# define CONFIG_STM32H5_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32H5_FLASH_CONFIG_C
# undef CONFIG_STM32H5_FLASH_CONFIG_E
# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C)
# define CONFIG_STM32H5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E)
# define CONFIG_STM32H5_FLASH_CONFIG_E
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32H5_FLASH_CONFIG_B) /* 128 kB */
# define STM32_FLASH_NPAGES 32
# define STM32_FLASH_PAGESIZE 4096
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C) /* 256 kB */
# define STM32_FLASH_NPAGES 64
# define STM32_FLASH_PAGESIZE 4096
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E) /* 512 kB */
# define STM32_FLASH_NPAGES 128
# define STM32_FLASH_PAGESIZE 4096
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G) /* 1 MB */
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 4096
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_I) /* 2 MB */
# define STM32_FLASH_NPAGES 512
# define STM32_FLASH_PAGESIZE 4096
#else
# error "unknown flash configuration!"
#endif
#ifdef STM32_FLASH_PAGESIZE
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
#endif
/* Register Offsets *********************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000
#define STM32_FLASH_NSKEYR_OFFSET 0x0004
#define STM32_FLASH_SECKEYR_OFFSET 0x0008
#define STM32_FLASH_OPTKEYR_OFFSET 0x000c
#define STM32_FLASH_NSOBKKEYR_OFFSET 0x0010
#define STM32_FLASH_SECOBKKEYR_OFFSET 0x0014
#define STM32_FLASH_OPSR_OFFSET 0x0018
#define STM32_FLASH_OPTCR_OFFSET 0x001c
#define STM32_FLASH_NSSR_OFFSET 0x0020
#define STM32_FLASH_SECSR_OFFSET 0x0024
#define STM32_FLASH_NSCR_OFFSET 0x0028
#define STM32_FLASH_SECCR_OFFSET 0x002c
#define STM32_FLASH_NSCCR_OFFSET 0x0030
#define STM32_FLASH_SECCCR_OFFSET 0x0034
#define STM32_FLASH_PRIVCFGR_OFFSET 0x003c
#define STM32_FLASH_NSOBKCFGR_OFFSET 0x0040
#define STM32_FLASH_SECOBKCFGR_OFFSET 0x0044
#define STM32_FLASH_HDPEXTR_OFFSET 0x0048
#define STM32_FLASH_OPTSR_CUR_OFFSET 0x0050
#define STM32_FLASH_OPTSR_PRG_OFFSET 0x0054
#define STM32_FLASH_NSEPOCHR_CUR_OFFSET 0x0060
#define STM32_FLASH_NSEPOCHR_PRG_OFFSET 0x0064
#define STM32_FLASH_SECEPOCHR_CUR_OFFSET 0x0068
#define STM32_FLASH_SECEPOCHR_PRG_OFFSET 0x006c
#define STM32_FLASH_OPTSR2_CUR_OFFSET 0x0070
#define STM32_FLASH_OPTSR2_PRG_OFFSET 0x0074
#define STM32_FLASH_NSBOOTR_CUR_OFFSET 0x0080
#define STM32_FLASH_NSBOOTR_PRG_OFFSET 0x0084
#define STM32_FLASH_SECBOOTR_CUR_OFFSET 0x0088
#define STM32_FLASH_SECBOOTR_PRG_OFFSET 0x008c
#define STM32_FLASH_OTBPBLR_CUR_OFFSET 0x0090
#define STM32_FLASH_OTBPBLR_PRG_OFFSET 0x0094
#define STM32_FLASH_SECBB1R_1_OFFSET 0x00a0
#define STM32_FLASH_SECBB1R_2_OFFSET 0x00a4
#define STM32_FLASH_SECBB1R_3_OFFSET 0x00a8
#define STM32_FLASH_SECBB1R_4_OFFSET 0x00ac
#define STM32_FLASH_PRIVBB1R_1_OFFSET 0x00c0
#define STM32_FLASH_PRIVBB1R_2_OFFSET 0x00c4
#define STM32_FLASH_PRIVBB1R_3_OFFSET 0x00c8
#define STM32_FLASH_PRIVBB1R_4_OFFSET 0x00cc
#define STM32_FLASH_SECWM1R_CUR_OFFSET 0x00e0
#define STM32_FLASH_SECWM1R_PRG_OFFSET 0x00e4
#define STM32_FLASH_WRP1R_CUR_OFFSET 0x00e8
#define STM32_FLASH_WRP1R_PRG_OFFSET 0x00ec
#define STM32_FLASH_EDATA1R_CUR_OFFSET 0x00f0
#define STM32_FLASH_EDATA1R_PRG_OFFSET 0x00f4
#define STM32_FLASH_HDP1R_CUR_OFFSET 0x00f8
#define STM32_FLASH_HDP1R_PRG_OFFSET 0x00fc
#define STM32_FLASH_ECCCORR_OFFSET 0x0100
#define STM32_FLASH_ECCDETR_OFFSET 0x0104
#define STM32_FLASH_ECCDR_OFFSET 0x0108
#define STM32_FLASH_SECBB2R_1_OFFSET 0x01a0
#define STM32_FLASH_SECBB2R_2_OFFSET 0x01a4
#define STM32_FLASH_SECBB2R_3_OFFSET 0x01a8
#define STM32_FLASH_SECBB2R_4_OFFSET 0x01ac
#define STM32_FLASH_PRIVBB2R_1_OFFSET 0x01c0
#define STM32_FLASH_PRIVBB2R_2_OFFSET 0x01c4
#define STM32_FLASH_PRIVBB2R_3_OFFSET 0x01c8
#define STM32_FLASH_PRIVBB2R_4_OFFSET 0x01cc
#define STM32_FLASH_SECWM2R_CUR_OFFSET 0x01e0
#define STM32_FLASH_SECWM2R_PRG_OFFSET 0x01e4
#define STM32_FLASH_WRP2R_CUR_OFFSET 0x01e8
#define STM32_FLASH_WRP2R_PRG_OFFSET 0x01ec
#define STM32_FLASH_EDATA2R_CUR_OFFSET 0x01f0
#define STM32_FLASH_EDATA2R_PRG_OFFSET 0x01f4
#define STM32_FLASH_HDP2R_CUR_OFFSET 0x01f8
#define STM32_FLASH_HDP2R_PRG_OFFSET 0x01fc
/* Register Addresses *******************************************************/
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET)
#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_NSOBKKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSOBKKEYR_OFFSET)
#define STM32_FLASH_SECOBKKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECOBKKEYR_OFFSET)
#define STM32_FLASH_OPSR (STM32_FLASHIF_BASE + STM32_FLASH_OPSR_OFFSET)
#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCR_OFFSET)
#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET)
#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET)
#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET)
#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET)
#define STM32_FLASH_NSCCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCCR_OFFSET)
#define STM32_FLASH_SECCCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCCR_OFFSET)
#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET)
#define STM32_FLASH_NSOBKCFGR (STM32_FLASHIF_BASE + STM32_FLASH_NSOBKCFGR_OFFSET)
#define STM32_FLASH_SECOBKCFGR (STM32_FLASHIF_BASE + STM32_FLASH_SECOBKCFGR_OFFSET)
#define STM32_FLASH_HDPEXTR (STM32_FLASHIF_BASE + STM32_FLASH_HDPEXTR_OFFSET)
#define STM32_FLASH_OPTSR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_CUR_OFFSET)
#define STM32_FLASH_OPTSR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_PRG_OFFSET)
#define STM32_FLASH_NSEPOCHR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_NSEPOCHR_CUR_OFFSET)
#define STM32_FLASH_NSEPOCHR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_NSEPOCHR_PRG_OFFSET)
#define STM32_FLASH_SECEPOCHR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECEPOCHR_CUR_OFFSET)
#define STM32_FLASH_SECEPOCHR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECEPOCHR_PRG_OFFSET)
#define STM32_FLASH_OPTSR2_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR2_CUR_OFFSET)
#define STM32_FLASH_OPTSR2_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR2_PRG_OFFSET)
#define STM32_FLASH_NSBOOTR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTR_CUR_OFFSET)
#define STM32_FLASH_NSBOOTR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTR_PRG_OFFSET)
#define STM32_FLASH_SECBOOTR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTR_CUR_OFFSET)
#define STM32_FLASH_SECBOOTR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTR_PRG_OFFSET)
#define STM32_FLASH_OTBPBLR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OTBPBLR_CUR_OFFSET)
#define STM32_FLASH_OTBPBLR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OTBPBLR_PRG_OFFSET)
#define STM32_FLASH_SECBB1R_1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_1_OFFSET)
#define STM32_FLASH_SECBB1R_2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_2_OFFSET)
#define STM32_FLASH_SECBB1R_3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_3_OFFSET)
#define STM32_FLASH_SECBB1R_4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_4_OFFSET)
#define STM32_FLASH_PRIVBB1R_1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_1_OFFSET)
#define STM32_FLASH_PRIVBB1R_2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_2_OFFSET)
#define STM32_FLASH_PRIVBB1R_3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_3_OFFSET)
#define STM32_FLASH_PRIVBB1R_4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_4_OFFSET)
#define STM32_FLASH_SECWM1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R_CUR_OFFSET)
#define STM32_FLASH_SECWM1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R_PRG_OFFSET)
#define STM32_FLASH_WRP1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1R_CUR_OFFSET)
#define STM32_FLASH_WRP1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_WRP1R_PRG_OFFSET)
#define STM32_FLASH_EDATA1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_EDATA1R_CUR_OFFSET)
#define STM32_FLASH_EDATA1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_EDATA1R_PRG_OFFSET)
#define STM32_FLASH_HDP1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_HDP1R_CUR_OFFSET)
#define STM32_FLASH_HDP1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_HDP1R_PRG_OFFSET)
#define STM32_FLASH_ECCCORR (STM32_FLASHIF_BASE + STM32_FLASH_ECCCORR_OFFSET)
#define STM32_FLASH_ECCDETR (STM32_FLASHIF_BASE + STM32_FLASH_ECCDETR_OFFSET)
#define STM32_FLASH_ECCDR (STM32_FLASHIF_BASE + STM32_FLASH_ECCDR_OFFSET)
#define STM32_FLASH_SECBB2R_1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_1_OFFSET)
#define STM32_FLASH_SECBB2R_2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_2_OFFSET)
#define STM32_FLASH_SECBB2R_3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_3_OFFSET)
#define STM32_FLASH_SECBB2R_4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_4_OFFSET)
#define STM32_FLASH_PRIVBB2R_1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_1_OFFSET)
#define STM32_FLASH_PRIVBB2R_2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_2_OFFSET)
#define STM32_FLASH_PRIVBB2R_3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_3_OFFSET)
#define STM32_FLASH_PRIVBB2R_4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_4_OFFSET)
#define STM32_FLASH_SECWM2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R_CUR_OFFSET)
#define STM32_FLASH_SECWM2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R_PRG_OFFSET)
#define STM32_FLASH_WRP2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2R_CUR_OFFSET)
#define STM32_FLASH_WRP2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_WRP2R_PRG_OFFSET)
#define STM32_FLASH_EDATA2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_EDATA2R_CUR_OFFSET)
#define STM32_FLASH_EDATA2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_EDATA2R_PRG_OFFSET)
#define STM32_FLASH_HDP2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_HDP2R_CUR_OFFSET)
#define STM32_FLASH_HDP2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_HDP2R_PRG_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Flash Access Control Register (ACR) */
#define FLASH_ACR_LATENCY_SHIFT (0)
#define FLASH_ACR_LATENCY_MASK (0xF << FLASH_ACR_LATENCY_SHIFT)
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 0-3. */
#define FLASH_ACR_WRHIGHFREQ_SHIFT (4)
#define FLASH_ACR_WRHIGHFREQ_MASK (0x3 << FLASH_ACR_WRHIGHFREQ_SHIFT)
# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT) /* Used to control the delay between NVM
* signals during programming operations
*/
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch Enable */
/* Flash Operation Status Register (OPSR) */
#define FLASH_OPSR_ADDR_OP_SHIFT (0)
#define FLASH_OPSR_ADDR_OP_MASK (0xfffff << FLASH_OPSR_ADDR_OP_SHIFT)
#define FLASH_OPSR_DATA_OP (1 << 21)
#define FLASH_OPSR_BK_OP (1 << 22)
#define FLASH_OPSR_SYSF_OP (1 << 23)
#define FLASH_OPSR_OTP_OP (1 << 24)
#define FLASH_OPSR_CODE_OP_SHIFT (29)
#define FLASH_OPSR_CODE_OP_MASK (0x7 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_NO_FLSH (0 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_SNGL_WRT (1 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_OBK_ALT (2 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_SEC_ERS (3 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_BNK_ERS (4 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_MASS_ERS (5 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_OPT_CNG (6 << FLASH_OPSR_CODE_OP_SHIFT)
#define FLASH_OPSR_CODE_OP_OBK_SWP (7 << FLASH_OPSR_CODE_OP_SHIFT)
/* Flash Option Control Register (OPTCR) */
#define FLASH_OPTCR_OPTLOCK (1 << 0)
#define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTCR_SWAP_BANK (1 << 31)
/* Flash Non-Secure Status Register (NSSR) */
#define FLASH_NSSR_BSY (1 << 0)
#define FLASH_NSSR_WBNE (1 << 1)
#define FLASH_NSSR_DBNE (1 << 3)
#define FLASH_NSSR_EOP (1 << 16)
#define FLASH_NSSR_WRPERR (1 << 17)
#define FLASH_NSSR_PGSERR (1 << 18)
#define FLASH_NSSR_STRBERR (1 << 19)
#define FLASH_NSSR_INCERR (1 << 20)
#define FLASH_NSSR_OBKERR (1 << 21)
#define FLASH_NSSR_OBKWERR (1 << 22)
#define FLASH_NSSR_OPTCHANGERR (1 << 23)
/* Flash Secure Status Register (SECSR) */
#define FLASH_NSSR_BSY (1 << 0)
#define FLASH_NSSR_WBNE (1 << 1)
#define FLASH_NSSR_DBNE (1 << 3)
#define FLASH_NSSR_EOP (1 << 16)
#define FLASH_NSSR_WRPERR (1 << 17)
#define FLASH_NSSR_PGSERR (1 << 18)
#define FLASH_NSSR_STRBERR (1 << 19)
#define FLASH_NSSR_INCERR (1 << 20)
#define FLASH_NSSR_OBKERR (1 << 21)
#define FLASH_NSSR_OBKWERR (1 << 22)
/* Flash Non-Secure Control Register (NSCR) */
#define FLASH_NSCR_LOCK (1 << 0)
#define FLASH_NSCR_PG (1 << 1)
#define FLASH_NSCR_SER (1 << 2)
#define FLASH_NSCR_BER (1 << 3)
#define FLASH_NSCR_FW (1 << 4)
#define FLASH_NSCR_STRT (1 << 5)
#define FLASH_NSCR_SNB_SHIFT (1 << 6)
#define FLASH_NSCR_SNB_MASK (0x7f << FLASH_NSCR_SNB_SHIFT)
# define FLASH_NSCR_SNB(n) ((n) << FLASH_NSCR_SNB_SHIFT)
#define FLASH_NSCR_MER (1 << 15)
#define FLASH_NSCR_EOPIE (1 << 16)
#define FLASH_NSCR_WRPERRIE (1 << 17)
#define FLASH_NSCR_PGSERRIE (1 << 18)
#define FLASH_NSCR_STRBERRIE (1 << 19)
#define FLASH_NSCR_INCERRIE (1 << 20)
#define FLASH_NSCR_OBKERRIE (1 << 21)
#define FLASH_NSCR_OBKWERRIE (1 << 22)
#define FLASH_NSCR_OPTCHANGEERRIE (1 << 23)
#define FLASH_NSCR_BKSEL (1 << 31)
/* Flash Secure Control Register (NSCR) */
#define FLASH_SECCR_LOCK (1 << 0)
#define FLASH_SECCR_PG (1 << 1)
#define FLASH_SECCR_SER (1 << 2)
#define FLASH_SECCR_BER (1 << 3)
#define FLASH_SECCR_FW (1 << 4)
#define FLASH_SECCR_STRT (1 << 5)
#define FLASH_SECCR_SNB_SHIFT (1 << 6)
#define FLASH_SECCR_SNB_MASK (0x7f << FLASH_SECCR_SNB_SHIFT)
# define FLASH_SECCR_SNB(n) ((n) << FLASH_SECCR_SNB_SHIFT)
#define FLASH_SECCR_MER (1 << 15)
#define FLASH_SECCR_EOPIE (1 << 16)
#define FLASH_SECCR_WRPERRIE (1 << 17)
#define FLASH_SECCR_PGSERRIE (1 << 18)
#define FLASH_SECCR_STRBERRIE (1 << 19)
#define FLASH_SECCR_INCERRIE (1 << 20)
#define FLASH_SECCR_OBKERRIE (1 << 21)
#define FLASH_SECCR_OBKWERRIE (1 << 22)
#define FLASH_SECCR_INV (1 << 29)
#define FLASH_SECCR_BKSEL (1 << 31)
/* Flash Non-Secure Clear Control Register (NSCCR) */
#define FLASH_NSCCR_CLR_EOP (1 << 16)
#define FLASH_NSCCR_CLR_WRPERR (1 << 17)
#define FLASH_NSCCR_CLR_PGSERR (1 << 18)
#define FLASH_NSCCR_CLR_STRBERR (1 << 19)
#define FLASH_NSCCR_CLR_INCERR (1 << 20)
#define FLASH_NSCCR_CLR_OBKERR (1 << 21)
#define FLASH_NSCCR_CLR_OBKWERR (1 << 22)
#define FLASH_NSCCR_CLR_OPTCHANGEERR (1 << 23)
/* Flash Secure Clear Control Register (SECCCR) */
#define FLASH_SECCCR_CLR_EOP (1 << 16)
#define FLASH_SECCCR_CLR_WRPERR (1 << 17)
#define FLASH_SECCCR_CLR_PGSERR (1 << 18)
#define FLASH_SECCCR_CLR_STRBERR (1 << 19)
#define FLASH_SECCCR_CLR_INCERR (1 << 20)
#define FLASH_SECCCR_CLR_OBKERR (1 << 21)
#define FLASH_SECCCR_CLR_OBKWERR (1 << 22)
/* Flash Privilege Configuration Register (PRIVCFGR) */
#define FLASH_PRIVCFGR_SPRIV (1 << 0)
#define FLASH_PRIVCFGR_NSPRIV (1 << 1)
/* Flash Non-Secure OBK Configuration Register (NSOBKCFGR) */
#define FLASH_NSOBKCFGR_LOCK (1 << 0)
#define FLASH_NSOBKCFGR_SWAP_SECT_REQ (1 << 1)
#define FLASH_NSOBKCFGR_ALT_SECT (1 << 2)
#define FLASH_NSOBKCFGR_ALT_SECT_ERASE (1 << 3)
#define FLASH_NSOBKCFGR_SWAP_OFFSET_SHIFT (16)
#define FLASH_NSOBKCFGR_SWAP_OFFSET_MASK (0x1ff << FLASH_NSOBKCFGR_SWAP_OFFSET_SHIFT)
/* Flash Non-Secure OBK Configuration Register (SECOBKCFGR) */
#define FLASH_SECOBKCFGR_LOCK (1 << 0)
#define FLASH_SECOBKCFGR_SWAP_SECT_REQ (1 << 1)
#define FLASH_SECOBKCFGR_ALT_SECT (1 << 2)
#define FLASH_SECOBKCFGR_ALT_SECT_ERASE (1 << 3)
#define FLASH_SECOBKCFGR_SWAP_OFFSET_SHIFT (16)
#define FLASH_SECOBKCFGR_SWAP_OFFSET_MASK (0x1ff << FLASH_SECOBKCFGR_SWAP_OFFSET_SHIFT)
/* Flash HDP Extension Register (HDPEXTR) */
#define FLASH_HDPEXTR_HDP1_EXT_SHIFT (0)
#define FLASH_HDPEXTR_HDP1_EXT_MASK (0x7f << FLASH_HDPEXTR_HDP1_EXT_SHIFT)
# define FLASH_HDPEXTR_HDP1_EXT(n) ((n) << FLASH_HDPEXTR_HDP1_SHIFT)
#define FLASH_HDPEXTR_HDP2_EXT_SHIFT (0)
#define FLASH_HDPEXTR_HDP2_EXT_MASK (0x7f << FLASH_HDPEXTR_HDP2_EXT_SHIFT)
# define FLASH_HDPEXTR_HDP2_EXT(n) ((n) << FLASH_HDPEXTR_HDP2_SHIFT)
/* Flash Option Status (Current) Register (OPTSR_CUR) */
#define FLASH_OPTSR_CUR_BOR_LEV_SHIFT (0)
#define FLASH_OPTSR_CUR_BOR_LEV_MASK (3 << FLASH_OPTSR_CUR_BOR_LEV_SHIFT)
#define FLASH_OPTSR_CUR_BOR_LEV_1 (0 << FLASH_OPTSR_CUR_BOR_LEV_SHIFT)
#define FLASH_OPTSR_CUR_BOR_LEV_2 (1 << FLASH_OPTSR_CUR_BOR_LEV_SHIFT)
#define FLASH_OPTSR_CUR_BOR_LEV_3 (2 << FLASH_OPTSR_CUR_BOR_LEV_SHIFT)
#define FLASH_OPTSR_CUR_BORH_EN (1 << 2)
#define FLASH_OPTSR_CUR_IWDG_SW (1 << 3)
#define FLASH_OPTSR_CUR_WWDG_SW (1 << 4)
#define FLASH_OPTSR_CUR_NRST_STOP (1 << 6)
#define FLASH_OPTSR_CUR_NRST_STDBY (1 << 7)
#define FLASH_OPTSR_CUR_PRODUCT_STATE_SHIFT (8)
#define FLASH_OPTSR_CUR_PRODUCT_STATE_MASK (0xff << FLASH_OPTSR_CUR_PRODUCT_STATE_SHIFT)
#define FLASH_OPTSR_CUR_IO_VDD_HSLV (1 << 16)
#define FLASH_OPTSR_CUR_IO_VDDIO2_HSLV (1 << 17)
#define FLASH_OPTSR_CUR_IWDG_STOP (1 << 20)
#define FLASH_OPTSR_CUR_IWDG_STDBY (1 << 21)
#define FLASH_OPTSR_CUR_BOOT_UBE_SHIFT (22)
#define FLASH_OPTSR_CUR_BOOT_UBE_MASK (0xff << FLASH_OPTSR_CUR_BOOT_UBE_SHIFT)
#define FLASH_OPTSR_CUR_SWAP_BANK (1 << 31)
/* Flash Option Status (Program) Register (OPTSR_PRG) */
#define FLASH_OPTSR_PRG_BOR_LEV_SHIFT (0)
#define FLASH_OPTSR_PRG_BOR_LEV_MASK (3 << FLASH_OPTSR_PRG_BOR_LEV_SHIFT)
#define FLASH_OPTSR_PRG_BOR_LEV_1 (0 << FLASH_OPTSR_PRG_BOR_LEV_SHIFT)
#define FLASH_OPTSR_PRG_BOR_LEV_2 (1 << FLASH_OPTSR_PRG_BOR_LEV_SHIFT)
#define FLASH_OPTSR_PRG_BOR_LEV_3 (2 << FLASH_OPTSR_PRG_BOR_LEV_SHIFT)
#define FLASH_OPTSR_PRG_BORH_EN (1 << 2)
#define FLASH_OPTSR_PRG_IWDG_SW (1 << 3)
#define FLASH_OPTSR_PRG_WWDG_SW (1 << 4)
#define FLASH_OPTSR_PRG_NRST_STOP (1 << 6)
#define FLASH_OPTSR_PRG_NRST_STDBY (1 << 7)
#define FLASH_OPTSR_PRG_PRODUCT_STATE_SHIFT (8)
#define FLASH_OPTSR_PRG_PRODUCT_STATE_MASK (0xff << FLASH_OPTSR_PRG_PRODUCT_STATE_SHIFT)
#define FLASH_OPTSR_PRG_IO_VDD_HSLV (1 << 16)
#define FLASH_OPTSR_PRG_IO_VDDIO2_HSLV (1 << 17)
#define FLASH_OPTSR_PRG_IWDG_STOP (1 << 20)
#define FLASH_OPTSR_PRG_IWDG_STDBY (1 << 21)
#define FLASH_OPTSR_PRG_BOOT_UBE_SHIFT (22)
#define FLASH_OPTSR_PRG_BOOT_UBE_MASK (0xff << FLASH_OPTSR_PRG_BOOT_UBE_SHIFT)
#define FLASH_OPTSR_PRG_SWAP_BANK (1 << 31)
/* Flash Non-Secure EPOCH Register (NSEPOCHR_CUR) */
#define FLASH_NSEPOCHR_CUR_MASK (0xffffff)
/* Flash Secure EPOCH Register (SECEPOCHR_CUR) */
#define FLASH_SECEPOCHR_CUR_MASK (0xffffff)
/* Flash Option Status (Current) Register (OPTSR2_CUR) */
#define FLASH_OPTSR2_CUR_SRAM13_RST (1 << 2)
#define FLASH_OPTSR2_CUR_SRAM2_RST (1 << 3)
#define FLASH_OPTSR2_CUR_BKPRAM_ECC (1 << 4)
#define FLASH_OPTSR2_CUR_SRAM3_ECC (1 << 5)
#define FLASH_OPTSR2_CUR_SRAM2_ECC (1 << 6)
#define FLASH_OPTSR2_CUR_USBPD_DIS (1 << 8)
#define FLASH_OPTSR2_CUR_TZEN_SHIFT (24)
#define FLASH_OPTSR2_CUR_TZEN_MASK (0xff << FLASH_OPTSR2_CUR_TZEN_SHIFT)
#define FLASH_OPTSR2_CUR_TZEN_EN (0xb4 << FLASH_OPTSR2_CUR_TZEN_SHIFT)
#define FLASH_OPTSR2_CUR_TZEN_DIS (0xb4 << FLASH_OPTSR2_CUR_TZEN_SHIFT)
/* Flash Option Status (Program) Register (OPTSR2_PRG) */
#define FLASH_OPTSR2_PRG_SRAM13_RST (1 << 2)
#define FLASH_OPTSR2_PRG_SRAM2_RST (1 << 3)
#define FLASH_OPTSR2_PRG_BKPRAM_ECC (1 << 4)
#define FLASH_OPTSR2_PRG_SRAM3_ECC (1 << 5)
#define FLASH_OPTSR2_PRG_SRAM2_ECC (1 << 6)
#define FLASH_OPTSR2_PRG_USBPD_DIS (1 << 8)
#define FLASH_OPTSR2_PRG_TZEN_SHIFT (24)
#define FLASH_OPTSR2_PRG_TZEN_MASK (0xff << FLASH_OPTSR2_PRG_TZEN_SHIFT)
#define FLASH_OPTSR2_PRG_TZEN_EN (0xb4 << FLASH_OPTSR2_PRG_TZEN_SHIFT)
#define FLASH_OPTSR2_PRG_TZEN_DIS (0xc3 << FLASH_OPTSR2_PRG_TZEN_SHIFT)
/* Flash Non-Secure Boot (Current) Register (NSBOOTR_CUR) */
#define FLASH_NSBOOTR_CUR_NSBOOT_LOCK_SHIFT (0)
#define FLASH_NSBOOTR_CUR_NSBOOT_LOCK_MASK (0xff << FLASH_NSBOOTR_CUR_NSBOOT_LOCK_SHIFT)
#define FLASH_NSBOOTR_CUR_NSBOOT_LOCK_MOD (0xc3 << FLASH_NSBOOTR_CUR_NSBOOT_LOCK_SHIFT)
#define FLASH_NSBOOTR_CUR_NSBOOT_LOCK_FRZN (0xb4 << FLASH_NSBOOTR_CUR_NSBOOT_LOCK_SHIFT)
#define FLASH_NSBOOTR_CUR_NSBOOTADD_SHIFT (8)
#define FLASH_NSBOOTR_CUR_NSBOOTADD_MASK (0xffffff << FLASH_NSBOOTR_CUR_NSBOOTADD_SHIFT)
/* Flash Non-Secure Boot (Program) Register (NSBOOTR_PRG) */
#define FLASH_NSBOOTR_PRG_NSBOOT_LOCK_SHIFT (0)
#define FLASH_NSBOOTR_PRG_NSBOOT_LOCK_MASK (0xff << FLASH_NSBOOTR_PRG_NSBOOT_LOCK_SHIFT)
#define FLASH_NSBOOTR_PRG_NSBOOT_LOCK_MOD (0xc3 << FLASH_NSBOOTR_PRG_NSBOOT_LOCK_SHIFT)
#define FLASH_NSBOOTR_PRG_NSBOOT_LOCK_FRZN (0xb4 << FLASH_NSBOOTR_PRG_NSBOOT_LOCK_SHIFT)
#define FLASH_NSBOOTR_PRG_NSBOOTADD_SHIFT (8)
#define FLASH_NSBOOTR_PRG_NSBOOTADD_MASK (0xffffff << FLASH_NSBOOTR_PRG_NSBOOTADD_SHIFT)
/* Flash Secure Boot (Current) Register (SECBOOTR_CUR) */
#define FLASH_SECBOOTR_CUR_SECBOOT_LOCK_SHIFT (0)
#define FLASH_SECBOOTR_CUR_SECBOOT_LOCK_MASK (0xff << FLASH_SECBOOTR_CUR_SECBOOT_LOCK_SHIFT)
#define FLASH_SECBOOTR_CUR_SECBOOT_LOCK_MOD (0xc3 << FLASH_SECBOOTR_CUR_SECBOOT_LOCK_SHIFT)
#define FLASH_SECBOOTR_CUR_SECBOOT_LOCK_FRZN (0xb4 << FLASH_SECBOOTR_CUR_SECBOOT_LOCK_SHIFT)
#define FLASH_SECBOOTR_CUR_SECBOOTADD_SHIFT (8)
#define FLASH_SECBOOTR_CUR_SECBOOTADD_MASK (0xffffff << FLASH_SECBOOTR_CUR_SECBOOTADD_SHIFT)
/* Flash Secure Boot Register (BOOTR_PRG) */
#define FLASH_BOOTR_PRG_SECBOOT_LOCK_SHIFT (0)
#define FLASH_BOOTR_PRG_SECBOOT_LOCK_MASK (0xff << FLASH_BOOTR_PRG_SECBOOT_LOCK_SHIFT)
#define FLASH_BOOTR_PRG_SECBOOT_LOCK_MOD (0xc3 << FLASH_BOOTR_PRG_SECBOOT_LOCK_SHIFT)
#define FLASH_BOOTR_PRG_SECBOOT_LOCK_FRZN (0xb4 << FLASH_BOOTR_PRG_SECBOOT_LOCK_SHIFT)
#define FLASH_BOOTR_PRG_SECBOOTADD_SHIFT (8)
#define FLASH_BOOTR_PRG_SECBOOTADD_MASK (0xffffff << FLASH_BOOTR_PRG_SECBOOTADD_SHIFT)
/* Flash Security Watermark for Bank1 (Current) Register (SECWM1R_CUR) */
#define FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT (0)
#define FLASH_SECWM1R_CUR_SECWM1_END_SHIFT (16)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT)
# define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT)
# define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT)
#endif
/* Flash Security Watermark for Bank1 (Program) Register (SECWM1R_PRG) */
#define FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT (0)
#define FLASH_SECWM1R_PRG_SECWM1_END_SHIFT (16)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT)
# define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT)
# define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT)
#endif
/* Flash Data Sector Configuration Bank 1 (Current) Register (EDATA1R_CUR) */
#define FLASH_EDATA1R_CUR_EDATA1_STRT_SHIFT (0)
#define FLASH_EDATA1R_CUR_EDATA1_STRT_MASK (3 << FLASH_EDATA1R_CUR_EDATA1_STRT_SHIFT)
#define FLASH_EDATA1R_CUR_EDATA1_STRT(n) ((n-1) << FLASH_EDATA1R_CUR_EDATA1_STRT_SHIFT) /* n = 1..8 */
#define FLASH_EDATA1R_CUR_EDATA1_EN (1 << 15)
/* Flash Data Sector Configuration Bank 1 (Program) Register (EDATA1R_PRG) */
#define FLASH_EDATA1R_PRG_EDATA1_STRT_SHIFT (0)
#define FLASH_EDATA1R_PRG_EDATA1_STRT_MASK (3 << FLASH_EDATA1R_PRG_EDATA1_STRT_SHIFT)
#define FLASH_EDATA1R_PRG_EDATA1_STRT(n) ((n-1) << FLASH_EDATA1R_PRG_EDATA1_STRT_SHIFT) /* n = 1..8 */
#define FLASH_EDATA1R_PRG_EDATA1_EN (1 << 15)
/* Flash HDP Bank 1 Configuration (Current) Register (HDP1R_CUR) */
#define FLASH_HDP1R_CUR_HDP1_STRT_SHIFT (0)
#define FLASH_HDP1R_CUR_HDP1_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT)
# define FLASH_HDP1R_CUR_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT)
# define FLASH_HDP1R_CUR_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT)
#endif
/* Flash HDP Bank 1 Configuration (Program) Register (HDP1R_PRG) */
#define FLASH_HDP1R_PRG_HDP1_STRT_SHIFT (0)
#define FLASH_HDP1R_PRG_HDP1_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT)
# define FLASH_HDP1R_PRG_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT)
# define FLASH_HDP1R_PRG_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT)
#endif
/* Flash ECC Correction Register (ECCCORR) */
#define FLASH_ECCCORR_ADDR_ECC_SHIFT (0)
#define FLASH_ECCCORR_ADDR_ECC_MASK (0xffff << FLASH_ECCCORR_ADDR_ECC_SHIFT)
#define FLASH_ECCCORR_OBK_ECC (1 << 20)
#define FLASH_ECCCORR_EDATA_ECC (1 << 21)
#define FLASH_ECCCORR_BK_ECC (1 << 22)
#define FLASH_ECCCORR_SYSF_ECC (1 << 23)
#define FLASH_ECCCORR_OTP_ECC (1 << 24)
#define FLASH_ECCCORR_ECCCIE (1 << 25)
#define FLASH_ECCCORR_ECCC (1 << 30)
/* Flash ECC Detection Register (ECCDETR) */
#define FLASH_ECCDETR_ADDR_ECC_SHIFT (0)
#define FLASH_ECCDETR_ADDR_ECC_MASK (0xffff << FLASH_ECCDETR_ADDR_ECC_SHIFT)
#define FLASH_ECCDETR_OBK_ECC (1 << 20)
#define FLASH_ECCDETR_EDATA_ECC (1 << 21)
#define FLASH_ECCDETR_BK_ECC (1 << 22)
#define FLASH_ECCDETR_SYSF_ECC (1 << 23)
#define FLASH_ECCDETR_OTP_ECC (1 << 24)
#define FLASH_ECCDETR_ECCD (1 << 31)
/* Flash ECC Data Register (ECCDR) */
#define FLASH_ECCDR_DATA_ECC_SHIFT (0)
#define FLASH_ECCDR_DATA_ECC_MASK (0xffff << FLASH_ECCDR_DATA_ECC_SHIFT)
/* Flash Security Watermark for Bank2 (Program) Register (SECWM2R_PRG) */
#define FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT (0)
#define FLASH_SECWM2R_PRG_SECWM2_END_SHIFT (16)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT)
# define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT)
# define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT)
#endif
/* Flash Data Sector Configuration Bank 2 (Current) Register (EDATA2R_CUR) */
#define FLASH_EDATA2R_CUR_EDATA2_STRT_SHIFT (0)
#define FLASH_EDATA2R_CUR_EDATA2_STRT_MASK (3 << FLASH_EDATA2R_CUR_EDATA2_STRT_SHIFT)
#define FLASH_EDATA2R_CUR_EDATA2_STRT(n) ((n-1) << FLASH_EDATA2R_CUR_EDATA2_STRT_SHIFT) /* n = 1..8 */
#define FLASH_EDATA2R_CUR_EDATA2_EN (1 << 15)
/* Flash Data Sector Configuration Bank 2 (Program) Register (EDATA2R_PRG) */
#define FLASH_EDATA2R_PRG_EDATA2_STRT_SHIFT (0)
#define FLASH_EDATA2R_PRG_EDATA2_STRT_MASK (3 << FLASH_EDATA2R_PRG_EDATA2_STRT_SHIFT)
#define FLASH_EDATA2R_PRG_EDATA2_STRT(n) ((n-1) << FLASH_EDATA2R_PRG_EDATA2_STRT_SHIFT) /* n = 1..8 */
#define FLASH_EDATA2R_PRG_EDATA2_EN (1 << 15)
/* Flash HDP Bank 2 Configuration (Current) Register (HDP1R_CUR) */
#define FLASH_HDP2R_CUR_HDP2_STRT_SHIFT (0)
#define FLASH_HDP2R_CUR_HDP2_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT)
# define FLASH_HDP2R_CUR_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT)
# define FLASH_HDP2R_CUR_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT)
#endif
/* Flash HDP Bank 2 Configuration (Program) Register (HDP2R_PRG) */
#define FLASH_HDP2R_PRG_HDP2_STRT_SHIFT (0)
#define FLASH_HDP2R_PRG_HDP2_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT)
# define FLASH_HDP2R_PRG_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT)
#endif
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT)
# define FLASH_HDP2R_PRG_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT)
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_FLASH_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_GPIO_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32h5/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
#define STM32_GPIO_HSLVR_OFFSET 0x002c /* GPIO high-speed low-voltage register */
#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */
/* Register Addresses *******************************************************/
#if STM32H5_NPORTS > 0
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 1
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 2
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 3
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 4
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 5
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 6
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 7
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOH_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 8
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOI_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET)
# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* GPIO port mode register */
#define GPIO_MODER_INPUT (0) /* Input */
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
#define GPIO_MODER_ALT (2) /* Alternate mode */
#define GPIO_MODER_ANALOG (3) /* Analog mode */
#define GPIO_MODER_SHIFT(n) ((n) << 1)
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
#define GPIO_MODER0_SHIFT (0)
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
#define GPIO_MODER1_SHIFT (2)
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
#define GPIO_MODER2_SHIFT (4)
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
#define GPIO_MODER3_SHIFT (6)
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
#define GPIO_MODER4_SHIFT (8)
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
#define GPIO_MODER5_SHIFT (10)
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
#define GPIO_MODER6_SHIFT (12)
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
#define GPIO_MODER7_SHIFT (14)
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
#define GPIO_MODER8_SHIFT (16)
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
#define GPIO_MODER9_SHIFT (18)
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
#define GPIO_MODER10_SHIFT (20)
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
#define GPIO_MODER11_SHIFT (22)
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
#define GPIO_MODER12_SHIFT (24)
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
#define GPIO_MODER13_SHIFT (26)
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
#define GPIO_MODER14_SHIFT (28)
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
#define GPIO_MODER15_SHIFT (30)
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
/* GPIO port output type register */
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */
/* GPIO port output speed register */
#define GPIO_OSPEED_2MHZ (0) /* 2 MHz Low speed */
#define GPIO_OSPEED_25MHZ (1) /* 25 MHz Medium speed */
#define GPIO_OSPEED_50MHZ (2) /* 50 MHz High speed */
#define GPIO_OSPEED_100MHZ (3) /* 100 MHz Very High speed on 30 pF (80 MHz Output max speed on 15 pF) */
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
#define GPIO_OSPEED0_SHIFT (0)
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
#define GPIO_OSPEED1_SHIFT (2)
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
#define GPIO_OSPEED2_SHIFT (4)
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
#define GPIO_OSPEED3_SHIFT (6)
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
#define GPIO_OSPEED4_SHIFT (8)
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
#define GPIO_OSPEED5_SHIFT (10)
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
#define GPIO_OSPEED6_SHIFT (12)
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
#define GPIO_OSPEED7_SHIFT (14)
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
#define GPIO_OSPEED8_SHIFT (16)
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
#define GPIO_OSPEED9_SHIFT (18)
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
#define GPIO_OSPEED10_SHIFT (20)
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
#define GPIO_OSPEED11_SHIFT (22)
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
#define GPIO_OSPEED12_SHIFT (24)
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
#define GPIO_OSPEED13_SHIFT (26)
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
#define GPIO_OSPEED14_SHIFT (28)
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
#define GPIO_OSPEED15_SHIFT (30)
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
/* GPIO port pull-up/pull-down register */
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
#define GPIO_PUPDR0_SHIFT (0)
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
#define GPIO_PUPDR1_SHIFT (2)
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
#define GPIO_PUPDR2_SHIFT (4)
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
#define GPIO_PUPDR3_SHIFT (6)
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
#define GPIO_PUPDR4_SHIFT (8)
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
#define GPIO_PUPDR5_SHIFT (10)
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
#define GPIO_PUPDR6_SHIFT (12)
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
#define GPIO_PUPDR7_SHIFT (14)
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
#define GPIO_PUPDR8_SHIFT (16)
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
#define GPIO_PUPDR9_SHIFT (18)
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
#define GPIO_PUPDR10_SHIFT (20)
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
#define GPIO_PUPDR11_SHIFT (22)
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
#define GPIO_PUPDR12_SHIFT (24)
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
#define GPIO_PUPDR13_SHIFT (26)
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
#define GPIO_PUPDR14_SHIFT (28)
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
#define GPIO_PUPDR15_SHIFT (30)
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
/* GPIO port input data register */
#define GPIO_IDR(n) (1 << (n))
/* GPIO port output data register */
#define GPIO_ODR(n) (1 << (n))
/* GPIO port bit set/reset register */
#define GPIO_BSRR_SET(n) (1 << (n))
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
/* GPIO port configuration lock register */
#define GPIO_LCKR(n) (1 << (n))
#define GPIO_LCKK (1 << 16) /* Lock key */
/* GPIO alternate function low/high register */
#define GPIO_AFR_SHIFT(n) ((n) << 2)
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
#define GPIO_AFRL0_SHIFT (0)
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
#define GPIO_AFRL1_SHIFT (4)
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
#define GPIO_AFRL2_SHIFT (8)
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
#define GPIO_AFRL3_SHIFT (12)
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
#define GPIO_AFRL4_SHIFT (16)
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
#define GPIO_AFRL5_SHIFT (20)
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
#define GPIO_AFRL6_SHIFT (24)
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
#define GPIO_AFRL7_SHIFT (28)
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
#define GPIO_AFRH8_SHIFT (0)
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
#define GPIO_AFRH9_SHIFT (4)
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
#define GPIO_AFRH10_SHIFT (8)
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
#define GPIO_AFRH11_SHIFT (12)
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
#define GPIO_AFRH12_SHIFT (16)
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
#define GPIO_AFRH13_SHIFT (20)
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
#define GPIO_AFRH14_SHIFT (24)
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
/* GPIO port bit reset register */
#define GPIO_BRR_SET(n) (1 << (n))
/* GPIO high-speed low-voltage register */
#define GPIO_HSLV_SET(n) (1 << (n))
/* GPIO port secure configuration register */
#define GPIO_SECCFGR_SET(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_GPIO_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_I2C_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_I2C_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_I2CCR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32_I2CCR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define STM32_I2COAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define STM32_I2COAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define STM32_I2CTIMINGR_OFFSET 0x0010 /* Timing register */
#define STM32_I2CTIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define STM32_I2CISR_OFFSET 0x0018 /* Interrupt and Status register */
#define STM32_I2CICR_OFFSET 0x001c /* Interrupt clear register */
#define STM32_I2CPECR_OFFSET 0x0020 /* Packet error checking register */
#define STM32_I2CRXDR_OFFSET 0x0024 /* Receive data register */
#define STM32_I2CTXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses *******************************************************/
#if STM32H5_NI2C > 0
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2CCR1_OFFSET)
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2CCR2_OFFSET)
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2COAR1_OFFSET)
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2COAR2_OFFSET)
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2CTIMINGR_OFFSET)
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2CTIMEOUTR_OFFSET)
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2CISR_OFFSET)
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2CICR_OFFSET)
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2CPECR_OFFSET)
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2CRXDR_OFFSET)
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2CTXDR_OFFSET)
#endif
#if STM32H5_NI2C > 1
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2CCR1_OFFSET)
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2CCR2_OFFSET)
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2COAR1_OFFSET)
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2COAR2_OFFSET)
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2CTIMINGR_OFFSET)
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2CTIMEOUTR_OFFSET)
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2CISR_OFFSET)
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2CICR_OFFSET)
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2CPECR_OFFSET)
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2CRXDR_OFFSET)
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2CTXDR_OFFSET)
#endif
#if STM32H5_NI2C > 2
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2CCR1_OFFSET)
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2CCR2_OFFSET)
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2COAR1_OFFSET)
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2COAR2_OFFSET)
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2CTIMINGR_OFFSET)
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2CTIMEOUTR_OFFSET)
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2CISR_OFFSET)
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2CICR_OFFSET)
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2CPECR_OFFSET)
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2CRXDR_OFFSET)
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2CTXDR_OFFSET)
#endif
#if STM32H5_NI2C > 3
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2CCR1_OFFSET)
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2CCR2_OFFSET)
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2COAR1_OFFSET)
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2COAR2_OFFSET)
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2CTIMINGR_OFFSET)
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2CTIMEOUTR_OFFSET)
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2CISR_OFFSET)
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2CICR_OFFSET)
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2CPECR_OFFSET)
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2CRXDR_OFFSET)
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2CTXDR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
/* Control register 2 */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
/* Own address register 1 */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
/* Own address register 2 */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
/* Timeout register */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
/* Fields unique to the Interrupt and Status register */
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
/* Packet error checking register */
#define I2C_PECR_MASK (0xff)
/* Receive data register */
#define I2C_RXDR_MASK (0xff)
/* Transmit data register */
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_I2C_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_MEMORYMAP_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* STM32H5XXX Address Blocks ************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
#define STM32_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
#define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0xF0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1)
/* Code Base Addresses ******************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */
#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
#define STM32_SRAM2_BASE 0x20040000 /* 0x20040000-0x2004ffff: 64k SRAM2 */
#define STM32_SRAM3_BASE 0x20050000 /* 0x20050000-0x2008ffff: 320k SRAM3 */
/* 0x20090000-0x2009ffff: Reserved for ECC */
/* System Memory Addresses **************************************************/
#define STM32_SYSMEM_UID 0x08FFF800 /* The 96-bit unique device identifier */
#define STM32_SYSMEM_FSIZE 0x08FFF80C /* Size of Flash memory in Kbytes. */
#define STM32_SYSMEM_PACKAGE 0x08FFF80E /* Indicates the device's package type. */
/* Peripheral Base Addresses ************************************************/
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000fbff: APB1 */
#define STM32_APB2_BASE 0x40012C00 /* 0x40012c00-0x40016bff: APB2 */
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400373ff: AHB1 */
#define STM32_AHB2_BASE 0x42020000 /* 0x42020000-0x420c3fff: AHB2 */
#define STM32_APB3_BASE 0x44000400 /* 0x44000400-0x44007fff: APB3 */
#define STM32_AHB3_BASE 0x44020800 /* 0x44020800-0x440243ff: AHB3 */
#define STM32_AHB4_BASE 0x46005000 /* 0x46005000-0x470017ff: AHB4 */
/* APB1 Base Addresses ******************************************************/
#define STM32_UCPD1_BASE 0x4000dc00
#define STM32_FDCAN_SRAM_BASE 0x4000ac00
#define STM32_FDCAN2_BASE 0x4000a800
#define STM32_FDCAN1_BASE 0x4000a400
#define STM32_LPTIM2 0x40009400
#define STM32_DTS_BASE 0x40008c00
#define STM32_UART12_BASE 0x40008400
#define STM32_UART9_BASE 0x40008000
#define STM32_UART8_BASE 0x40007c00
#define STM32_UART7_BASE 0x40007800
#define STM32_HDMICEC_BASE 0x40007000
#define STM32_USART11_BASE 0x40006c00
#define STM32_USART10_BASE 0x40006800
#define STM32_USART6_BASE 0x40006400
#define STM32_CRS_BASE 0x40006000
#define STM32_I3C1_BASE 0x40005c00
#define STM32_I2C2_BASE 0x40005800
#define STM32_I2C1_BASE 0x40005400
#define STM32_UART5_BASE 0x40005000
#define STM32_UART4_BASE 0x40004c00
#define STM32_USART3_BASE 0x40004800
#define STM32_USART2_BASE 0x40004400
#define STM32_SPI3_BASE 0x40003c00
#define STM32_SPI2_BASE 0x40003800
#define STM32_IWDG_BASE 0x40003000
#define STM32_WWDG_BASE 0x40002c00
#define STM32_TIM14_BASE 0x40002000
#define STM32_TIM13_BASE 0x40001c00
#define STM32_TIM12_BASE 0x40001800
#define STM32_TIM7_BASE 0x40001400
#define STM32_TIM6_BASE 0x40001000
#define STM32_TIM5_BASE 0x40000c00
#define STM32_TIM4_BASE 0x40000800
#define STM32_TIM3_BASE 0x40000400
#define STM32_TIM2_BASE 0x40000000
/* APB2 Base Addresses ******************************************************/
#define STM32_USB_FS_RAM_BASE 0x40016400
#define STM32_USB_FS_BASE 0x40016000
#define STM32_SAI2_BASE 0x40015800
#define STM32_SAI1_BASE 0x40015400
#define STM32_SPI6_BASE 0x40015000
#define STM32_SPI4_BASE 0x40014c00
#define STM32_TIM17_BASE 0x40014800
#define STM32_TIM16_BASE 0x40014400
#define STM32_TIM15_BASE 0x40014000
#define STM32_USART1_BASE 0x40013800
#define STM32_TIM8_BASE 0x40013400
#define STM32_SPI1_BASE 0x40013000
#define STM32_TIM1_BASE 0x40012C00
/* AHB1 Base Addresses ******************************************************/
#define STM32_MPC_WM_BKPRAM_BASE 0x40036400
#define STM32_GTZC1_BASE 0x40032400
#define STM32_DCACHE_BASE 0x40030400
#define STM32_ICACHE_BASE 0x40031400
#define STM32_EMAC_BASE 0x40030400
#define STM32_RAMCFG_BASE 0x40026000
#define STM32_FMAC_BASE 0x40023c00
#define STM32_CORDIC_BASE 0x40023800
#define STM32_CRC_BASE 0x40023000
#define STM32_FLASHIF_BASE 0x40022000
#define STM32_DMA2_BASE 0x40021000
#define STM32_DMA1_BASE 0x40020000
/* AHB2 Base Addresses ******************************************************/
#define STM32_PKA_BASE 0x420c2000
#define STM32_SAES_BASE 0x420c0C00
#define STM32_RNG_BASE 0x420c0800
#define STM32_HASH_BASE 0x420c0400
#define STM32_AES_BASE 0x420c0000
#define STM32_PSSI_BASE 0x4202c400
#define STM32_DCMI_BASE 0x4202c000
#define STM32_DAC1_BASE 0x42028400
#define STM32_ADC12_BASE 0x42028000
#define STM32_GPIOI_BASE 0x42022000
#define STM32_GPIOH_BASE 0x42021c00
#define STM32_GPIOG_BASE 0x42021800
#define STM32_GPIOF_BASE 0x42021400
#define STM32_GPIOE_BASE 0x42021000
#define STM32_GPIOD_BASE 0x42020c00
#define STM32_GPIOC_BASE 0x42020800
#define STM32_GPIOB_BASE 0x42020400
#define STM32_GPIOA_BASE 0x42020000
/* APB3 Base Addresses ******************************************************/
#define STM32_TAMP_BASE 0x44007c00
#define STM32_RTC_BASE 0x44007800
#define STM32_VREFBUF_BASE 0x44007400
#define STM32_LPTIM6_BASE 0x44005400
#define STM32_LPTIM5_BASE 0x44005000
#define STM32_LPTIM4_BASE 0x44004c00
#define STM32_LPTIM3_BASE 0x44004800
#define STM32_LPTIM1_BASE 0x44004400
#define STM32_I2C4_BASE 0x44002c00
#define STM32_I2C3_BASE 0x44002800
#define STM32_LPUART1_BASE 0x44002400
#define STM32_SPI5_BASE 0x44002000
#define STM32_SBS_BASE 0x44000400
/* AHB3 Base Addresses ******************************************************/
#define STM32_DEBUG_BASE 0x44024000
#define STM32_EXTI_BASE 0x44022000
#define STM32_RCC_BASE 0x44020C00
#define STM32_PWR_BASE 0x44020800
/* AHB4 Base Addresses ******************************************************/
#define STM32_OCTOSPI1_BASE 0x47001400
#define STM32_FMC_BASE 0x47000400
#define STM32_DLYBOS1_BASE 0x4600f000
#define STM32_SDMMC2_BASE 0x46008c00
#define STM32_DLYBSD2_BASE 0x46008800
#define STM32_DLYBSD1_BASE 0x46008400
#define STM32_SDMMC1_BASE 0x46008000
#define STM32_OTFDEC1_BASE 0x46005000
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_PWR_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_PWR_PMCR_OFFSET 0x0000 /* Power Mode Control */
#define STM32_PWR_PMSR_OFFSET 0x0004 /* Power Mode Status */
#define STM32_PWR_VOSCR_OFFSET 0x0010 /* Voltage Scaling Control */
#define STM32_PWR_VOSSR_OFFSET 0x0014 /* Voltage Scaling Status */
#define STM32_PWR_BDCR_OFFSET 0x0020 /* Backup Domain Control */
#define STM32_PWR_DBPCR_OFFSET 0x0024 /* Backup Domain Protection Control */
#define STM32_PWR_BDSR_OFFSET 0x0028 /* Backup Domain Status */
#define STM32_PWR_UCPDR_OFFSET 0x002c /* USB-C Power Delivery */
#define STM32_PWR_SCCR_OFFSET 0x0030 /* Supply Configuration Control */
#define STM32_PWR_VMCR_OFFSET 0x0034 /* Voltage Monitor Control */
#define STM32_PWR_USBSCR_OFFSET 0x0038 /* USB Supply Control */
#define STM32_PWR_VMSR_OFFSET 0x003c /* Voltage Monitor Status */
#define STM32_PWR_WUSCR_OFFSET 0x0040 /* Wake-Up Status Clear */
#define STM32_PWR_WUSR_OFFSET 0x0044 /* Wake-Up Status */
#define STM32_PWR_WUCR_OFFSET 0x0048 /* Wake-Up Configuration */
#define STM32_PWR_IORETR_OFFSET 0x0050 /* I/O Retention */
#define STM32_PWR_SECCFGR_OFFSET 0x0100 /* Power secure configuration register */
#define STM32_PWR_PRIVCFGR_OFFSET 0x0104 /* Power privilege configuration register */
/* Register Addresses *******************************************************/
#define STM32_PWR_PMCR (STM32_PWR_BASE + STM32_PWR_PMCR_OFFSET)
#define STM32_PWR_PMSR (STM32_PWR_BASE + STM32_PWR_PMSR_OFFSET)
#define STM32_PWR_VOSCR (STM32_PWR_BASE + STM32_PWR_VOSCR_OFFSET)
#define STM32_PWR_VOSSR (STM32_PWR_BASE + STM32_PWR_VOSSR_OFFSET)
#define STM32_PWR_BDCR (STM32_PWR_BASE + STM32_PWR_BDCR_OFFSET)
#define STM32_PWR_DBPCR (STM32_PWR_BASE + STM32_PWR_DBPCR_OFFSET)
#define STM32_PWR_BDSR (STM32_PWR_BASE + STM32_PWR_BDSR_OFFSET)
#define STM32_PWR_UCPDR (STM32_PWR_BASE + STM32_PWR_UCPDR_OFFSET)
#define STM32_PWR_SCCR (STM32_PWR_BASE + STM32_PWR_SCCR_OFFSET)
#define STM32_PWR_VMCR (STM32_PWR_BASE + STM32_PWR_VMCR_OFFSET)
#define STM32_PWR_USBSCR (STM32_PWR_BASE + STM32_PWR_USBSCR_OFFSET)
#define STM32_PWR_VMSR (STM32_PWR_BASE + STM32_PWR_VMSR_OFFSET)
#define STM32_PWR_WUSCR (STM32_PWR_BASE + STM32_PWR_WUSCR_OFFSET)
#define STM32_PWR_WUSR (STM32_PWR_BASE + STM32_PWR_WUSR_OFFSET)
#define STM32_PWR_WUCR (STM32_PWR_BASE + STM32_PWR_WUCR_OFFSET)
#define STM32_PWR_IORETR (STM32_PWR_BASE + STM32_PWR_IORETR_OFFSET)
#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET)
#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Power Mode Control Register */
#define PWR_PMCR_LPMS (1 << 0) /* Low-Power Mode */
#define PWR_PMCR_SVOS_SHIFT (2) /* System Stop Mode Voltage Scaling */
#define PWR_PMCR_SVOS_MASK (0x3 << PWR_PMCR_SVOS_SHIFT)
# define PWR_PMCR_SVOS_SVOS5 (1 << PWR_PMCR_SVOS_SHIFT)
# define PWR_PMCR_SVOS_SVOS4 (2 << PWR_PMCR_SVOS_SHIFT)
# define PWR_PMCR_SVOS_SVOS3 (3 << PWR_PMCR_SVOS_SHIFT)
#define PWR_PMCR_CSSF (1 << 7) /* Clear Standby and Stop Flags */
#define PWR_PMCR_FLPS (1 << 9) /* Flash Memory Low-Power Mode in Stop Mode */
#define PWR_PMCR_BOOSTE (1 << 12) /* Analog Switch Vboost Control */
#define PWR_PMCR_AVD_READY (1 << 13) /* Analog Voltage Ready */
#define PWR_PMCR_ETHERNETSO (1 << 16) /* Ethernet RAM shut-off in Stop Mode */
#define PWR_PMCR_SRAM3SO (1 << 23) /* AHB SRAM3 shut-off in Stop mode */
#if defined(CONFIG_STM32H5_STM32H56X) || defined(CONFIG_STM32H5_STM32H7X)
#define PWR_PMCR_SRAM2_16SO (1 << 24) /* AHB SRAM3 16-Kbyte shut-off in Stop mode **/
#define PWR_PMCR_SRAM2_48SO (1 << 25) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/
#define PWR_PMCR_SRAM1SO (1 << 26) /* AHB SRAM1 shut-off in Stop mode * */
#elif defined(CONFIG_STM32H5_STM32H2X) || defined(CONFIG_STM32H5_STM32H3X)
#define PWR_PMCR_SRAM2_16LSO (1 << 24) /* AHB SRAM3 16-Kbyte Low shut-off in Stop mode **/
#define PWR_PMCR_SRAM2_16HSO (1 << 25) /* AHB SRAM3 16-Kbyte High shut-off in Stop mode **/
#define PWR_PMCR_SRAM2_48SO (1 << 26) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/
#define PWR_PMCR_SRAM1SO (1 << 27) /* AHB SRAM1 shut-off in Stop mode */
#endif
/* Status Register */
#define PWR_PMSR_STOPF (1 << 5) /* Stop Flag */
#define PWR_PMSR_SBF (1 << 6) /* System Standby Flag */
/* Voltage Scaling Control Register */
#define PWR_VOSCR_VOS_SHIFT (4)
#define PWR_VOSCR_VOS_MASK (3 << PWR_VOSCR_VOS_SHIFT)
# define PWR_VOSCR_VOS_RANGE3 (0 << PWR_VOSCR_VOS_SHIFT)
# define PWR_VOSCR_VOS_RANGE2 (1 << PWR_VOSCR_VOS_SHIFT)
# define PWR_VOSCR_VOS_RANGE1 (2 << PWR_VOSCR_VOS_SHIFT)
# define PWR_VOSCR_VOS_RANGE0 (3 << PWR_VOSCR_VOS_SHIFT)
/* Voltage Scaling Status Register */
#define PWR_VOSSR_VOSRDY (1 << 3)
#define PWR_VOSSR_ACTVOSRDY (1 << 13)
#define PWR_VOSSR_ACTVOS_SHIFT (14)
#define PWR_VOSSR_ACTVOS_MASK (3 << PWR_VOSSR_ACTVOS_SHIFT)
# define PWR_VOSSR_ACTVOS_VOS3 (0 << PWR_VOSSR_ACTVOS_SHIFT)
# define PWR_VOSSR_ACTVOS_VOS2 (1 << PWR_VOSSR_ACTVOS_SHIFT)
# define PWR_VOSSR_ACTVOS_VOS1 (2 << PWR_VOSSR_ACTVOS_SHIFT)
# define PWR_VOSSR_ACTVOS_VOS0 (3 << PWR_VOSSR_ACTVOS_SHIFT)
/* Backup Domain Control Register */
#define PWR_BDCR_BREN (1 << 0) /* Backup RAM Retention in Sby and VBAT modes */
#define PWR_BDCR_MONEN (1 << 1) /* Backup Domain Voltage and Temperature Monitoring Enable */
#define PWR_BDCR_VBE (1 << 8) /* Vbat Charging Enable */
#define PWR_BDCR_VBRS (1 << 9) /* Vbat Charging Resistor Selection: 0=5k, 1=1.5k */
/* Backup Domain Protected Control Register */
#define PWR_DBPCR_DBP (1 << 0)
/* Backup Domain Status Register */
#define PWR_BDSR_BRRDY (1 << 16) /* Backup Regulator Ready */
#define PWR_BDSR_VBATL (1 << 20) /* Vbat Level Monitoring vs Low Threshold */
#define PWR_BDSR_VBATH (1 << 21) /* Vbat Level Monitoring vs High Threshold */
#define PWR_BDSR_TEMPL (1 << 22) /* Temperature Level Monitoring vs Low Threshold */
#define PWR_BDSR_TEMPH (1 << 23) /* Temperature Level Monitoring vs High Threshold */
/* USB Type-C Power Delivery Register */
#define PWR_UCPDR_UCPD_DBDIS (1 << 0) /* USB-C Power Delivery and Dead Battery Disable */
#define PWR_UCPDR_UCPD_STBY (1 << 1) /* USB-C and Power Delivery Standby Mode */
/* Supply Configuration Control Register */
#define PWR_SCCR_BYPASS (1 << 0) /* Power Management Unit Bypass
* 0: Normal Operation: Use Internal Regulator
* 1: Bypassed: Use External Power (Monitoring still active)
*/
#define PWR_SCCR_LDOEN (1 << 8) /* Low Dropout Regulator Enable */
#define PWR_SCCR_SMPSEN (1 << 9) /* Switch-Mode Power Supply Enable */
/* Voltage Monitor Control Register */
#define PWR_VMCR_PVDE (1 << 0) /* Programmable Voltage Detector (PVD) Enable */
#define PWR_VMCR_PLS_SHIFT (1)
#define PWR_VMCR_PLS_MASK (3 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD0 (0 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD1 (1 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD2 (2 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD3 (3 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD4 (4 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD5 (5 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVD6 (6 << PWR_VMCR_PLS_SHIFT)
# define PWR_VMCR_PLS_PVDIN (7 << PWR_VMCR_PLS_SHIFT)
#define PWR_VMCR_AVDEN (1 << 8) /* Peripheral Voltage Monitor on Vdda enable */
#define PWR_VMCR_ALS_SHIFT (9)
#define PWR_VMCR_ALS_MASK (3 << PWR_VMCR_ALS_SHIFT)
# define PWR_VMCR_ALS_AVD0 (0 << PWR_VMCR_ALS_SHIFT)
# define PWR_VMCR_ALS_AVD1 (1 << PWR_VMCR_ALS_SHIFT)
# define PWR_VMCR_ALS_AVD2 (2 << PWR_VMCR_ALS_SHIFT)
# define PWR_VMCR_ALS_AVD3 (3 << PWR_VMCR_ALS_SHIFT)
/* USB Supply Control Register */
#define PWR_USBSCR_USB33DEN (1 << 24) /* Vddusb voltage level detector enable */
#define PWR_USBSCR_USB33SV (1 << 25) /* Independent USB Supply Valid */
/* Voltage Monitor Status Register */
#define PWR_VMSR_AVDO (1 << 19) /* Analog Voltage Detector Output on Vdda */
#define PWR_VMSR_VDDIO2RDY (1 << 20) /* Voltage Detector Output on Vddio2 */
#define PWR_VMSR_PVDO (1 << 22) /* Programmable Voltage Detect Output */
#define PWR_VMSR_USB33RDY (1 << 24) /* Vddusb Ready */
/* Wake-up Status Clear Register */
#define PWR_WUSCR_CWUF1 (1 << 0) /* Clear wake-up pin flag for WUF1 */
#define PWR_WUSCR_CWUF2 (1 << 1) /* Clear wake-up pin flag for WUF2 */
#define PWR_WUSCR_CWUF3 (1 << 2) /* Clear wake-up pin flag for WUF3 */
#define PWR_WUSCR_CWUF4 (1 << 3) /* Clear wake-up pin flag for WUF4 */
#define PWR_WUSCR_CWUF5 (1 << 4) /* Clear wake-up pin flag for WUF5 */
#define PWR_WUSCR_CWUF6 (1 << 5) /* Clear wake-up pin flag for WUF6 */
#define PWR_WUSCR_CWUF7 (1 << 6) /* Clear wake-up pin flag for WUF7 */
#define PWR_WUSCR_CWUF8 (1 << 7) /* Clear wake-up pin flag for WUF8 */
/* Wake-up Status Register */
#define PWR_WUSR_WUF1 (1 << 0) /* Wake-up event received for WUF1 */
#define PWR_WUSR_WUF2 (1 << 1) /* Wake-up event received for WUF2 */
#define PWR_WUSR_WUF3 (1 << 2) /* Wake-up event received for WUF3 */
#define PWR_WUSR_WUF4 (1 << 3) /* Wake-up event received for WUF4 */
#define PWR_WUSR_WUF5 (1 << 4) /* Wake-up event received for WUF5 */
#define PWR_WUSR_WUF6 (1 << 5) /* Wake-up event received for WUF6 */
#define PWR_WUSR_WUF7 (1 << 6) /* Wake-up event received for WUF7 */
#define PWR_WUSR_WUF8 (1 << 7) /* Wake-up event received for WUF8 */
/* Wake-up Configuration Register */
#define PWR_WUCR_WUPEN(n) (1 << (n-1)) /* Enable wake-up pin WUPn. n = 1..8 */
#define PWR_WUCR_WUPP(n) (1 << (n+7)) /* Wake-up Pin Polarity bit for WUPn */
#define PWR_WUCR_MASK_WUPPUPD(n) (3 << (((n-1) * 2) + 16)) /* Wake-up pin pull configuration */
#define PWR_WUCR_NOPU_WUPPUPD(n) (0 << (((n-1) * 2) + 16))
#define PWR_WUCR_PU_WUPPUPD(n) (1 << (((n-1) * 2) + 16))
#define PWR_WUCR_PD_WUPPUPD(n) (2 << (((n-1) * 2) + 16))
/* IO Retention Register */
#define PWR_IORETR_IORETEN (1 << 0) /* IO Retention Enable */
#define PWR_IORETR_JTAGIORETEN (1 << 16) /* IO Retention Enable for JTAG IOs */
/* Power secure configuration register */
#define PWR_SECCFGR_WUP_SEC(n) (1 << (n-1)) /* WUP(n) Secure Protection */
#define PWR_SECCFGR_RETSEC (1 << 11) /* Retention Secure Protection */
#define PWR_SECCFGR_LPMSEC (1 << 12) /* Low-power Modes Secure Protection */
#define PWR_SECCFGR_SCMSEC (1 << 13) /* Supply Configuration and Monitoring Secure Protection */
#define PWR_SECCFGR_VBSEC (1 << 14) /* Backup Domain Secure Protection */
#define PWR_SECCFGR_VUSBSEC (1 << 15) /* Voltage USB Secure Protection */
/* Power privilege configuration register */
#define PWR_PRIVCFGR_SPRIV (1 << 0) /* Bit 0: Power Secure Privilege protection */
#define PWR_PRIVCFGR_NSPRIV (1 << 1) /* Bit 0: Power Non-secure Privilege protection */
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_PWR_H */

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/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_UART_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */
/* Register Addresses *******************************************************/
#if STM32H5_NLPUART > 0
# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_LPUART1_GTPR (STM32_LPUART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_LPUART1_RTOR (STM32_LPUART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 1
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 2
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 4
# define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART6_BRR (STM32_USART6_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART6_GTPR (STM32_USART6_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART6_RTOR (STM32_USART6_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART6_RQR (STM32_USART6_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART6_ISR (STM32_USART6_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART6_ICR (STM32_USART6_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART6_RDR (STM32_USART6_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART6_TDR (STM32_USART6_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 5
# define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART10_BRR (STM32_USART10_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART10_GTPR (STM32_USART10_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART10_RTOR (STM32_USART10_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART10_RQR (STM32_USART10_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART10_ISR (STM32_USART10_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART10_ICR (STM32_USART10_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART10_RDR (STM32_USART10_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART10_TDR (STM32_USART10_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 6
# define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART11_BRR (STM32_USART11_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART11_GTPR (STM32_USART11_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART11_RTOR (STM32_USART11_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART11_RQR (STM32_USART11_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART11_ISR (STM32_USART11_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART11_ICR (STM32_USART11_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART11_RDR (STM32_USART11_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART11_TDR (STM32_USART11_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 0
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 1
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 2
# define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART7_BRR (STM32_UART7_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART7_GTPR (STM32_UART7_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART7_RTOR (STM32_UART7_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART7_RQR (STM32_UART7_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART7_ISR (STM32_UART7_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART7_ICR (STM32_UART7_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART7_RDR (STM32_UART7_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 3
# define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART8_BRR (STM32_UART8_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART8_GTPR (STM32_UART8_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART8_RTOR (STM32_UART8_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART8_RQR (STM32_UART8_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART8_ISR (STM32_UART8_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART8_ICR (STM32_UART8_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART8_RDR (STM32_UART8_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART8_TDR (STM32_UART8_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 4
# define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART9_BRR (STM32_UART9_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART9_GTPR (STM32_UART9_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART9_RTOR (STM32_UART9_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART9_RQR (STM32_UART9_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART9_ISR (STM32_UART9_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART9_ICR (STM32_UART9_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART9_RDR (STM32_UART9_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART9_TDR (STM32_UART9_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 5
# define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART12_BRR (STM32_UART12_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART12_GTPR (STM32_UART12_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART12_RTOR (STM32_UART12_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART12_RQR (STM32_UART12_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART12_ISR (STM32_UART12_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART12_ICR (STM32_UART12_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART12_RDR (STM32_UART12_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART12_TDR (STM32_UART12_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART12_PRESC (STM32_UART12_BASE + STM32_USART_PRESC_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
USART_CR1_TCIE|USART_CR1_TXEIE| \
USART_CR1_PEIE|USART_CR1_CMIE| \
USART_CR1_RTOIE|USART_CR1_EOBIE)
#define LPUART_CR1_ALLINTS \
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \
USART_CR1_TXFEIE | USART_CR1_RXFFIE)
/* Control register 2 */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Receiver timeout register */
/* Request Register */
#define USART_CR1_SBRKQ (1 << 1) /* Bit 1: Send Break */
/* Interrupt and Status register */
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt Flag */
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS Flag */
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout Flag */
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block Flag */
#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate Error */
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate Flag */
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy Flag */
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match Flag */
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break Flag */
#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode Flag */
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge Flag */
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge Flag */
/* ICR */
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
/* Receive Data register */
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
/* Transmit Data register */
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_UART_H */

40
arch/arm/src/stm32h5/stm32.h Normal file
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@ -0,0 +1,40 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_H
#define __ARCH_ARM_SRC_STM32H5_STM32_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals **************************************************************/
#include "chip.h"
#include "stm32_flash.h"
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_H */

35
arch/arm/src/stm32h5/stm32_flash.h Normal file
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@ -0,0 +1,35 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32H5_STM32_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/stm32_flash.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_FLASH_H */

2
boards/Kconfig
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@ -2795,6 +2795,7 @@ config ARCH_BOARD_STM32L476_MDK
The STM32L476ME is a Cortex-M4 optimised for low-power operation
at up to 80MHz operation with 1024Kb Flash memory and 96+32Kb SRAM.
config ARCH_BOARD_STM32L562E_DK
bool "STM32L562E-DK"
depends on ARCH_CHIP_STM32L562QE
@ -3512,6 +3513,7 @@ config ARCH_BOARD
default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1
default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A
default "b-u585i-iot02a" if ARCH_BOARD_B_U585I_IOT02A
default "nucleo-h563zi" if ARCH_BOARD_NUCLEO_H563ZI
default "nucleo-u5a5zj-q" if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
default "stm32l476vg-disco" if ARCH_BOARD_STM32L476VG_DISCO
default "stm32l476-mdk" if ARCH_BOARD_STM32L476_MDK