Merged in david_s5/nuttx/master_k66_ethernet (pull request #1064)
NXP k66 Ethernet
* Kinetis:Add TJA1100 Phy
* Kinetis:enet.c formated with nxstyle
* net:mii Cleanup TJA1100 Support
Formating and adding mask and shifts
* net:Kconfig Cleanup formatting
Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane
Gregory Nutt
parent
e3665c1fb4
commit
43a3a0f400
3 changed files with 263 additions and 41 deletions
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@ -169,12 +169,20 @@
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# define BOARD_PHY_10BASET(s) (((s) & MII_PHYCTRL1_MODE_10HDX) != 0)
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# define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL1_MODE_100HDX) != 0)
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# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL1_MODE_DUPLEX) != 0)
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#elif defined(CONFIG_ETH0_PHY_TJA1100)
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# define BOARD_PHY_NAME "TJA1100"
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# define BOARD_PHYID1 MII_PHYID1_TJA1100
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# define BOARD_PHYID2 MII_PHYID2_TJA1100
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# define BOARD_PHY_STATUS MII_TJA1100_BSR
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# define BOARD_PHY_10BASET(s) 0 /* PHY only supports 100BASE-T1 */
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# define BOARD_PHY_100BASET(s) 1 /* PHY only supports 100BASE-T1 */
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# define BOARD_PHY_ISDUPLEX(s) 1 /* PHY only supports fullduplex */
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#else
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# error "Unrecognized or missing PHY selection"
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#endif
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/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz,
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based on the internal module (ENET) clock:
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* based on the internal module (ENET) clock:
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*
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* MII_SPEED = ENET_FREQ/5000000 -1
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*
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@ -261,6 +269,7 @@ static struct kinetis_driver_s g_enet[CONFIG_KINETIS_ENETNETHIFS];
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Utility functions */
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#ifndef KINETIS_BUFFERS_SWAP
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@ -481,20 +490,20 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
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#endif
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txdesc->status1 |= (TXDESC_R | TXDESC_L | TXDESC_TC);
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buf = (uint8_t*)kinesis_swap32((uint32_t)priv->dev.d_buf);
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buf = (uint8_t *)kinesis_swap32((uint32_t) priv->dev.d_buf);
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if (priv->rxdesc[priv->rxtail].data == buf)
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{
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struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
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struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
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/* Data was written into the RX buffer, so swap the TX and RX buffers */
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/* Data was written into the RX buffer, so swap the TX and RX buffers */
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DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
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rxdesc->data = txdesc->data;
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txdesc->data = buf;
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DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
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rxdesc->data = txdesc->data;
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txdesc->data = buf;
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}
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else
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{
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DEBUGASSERT(txdesc->data == buf);
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DEBUGASSERT(txdesc->data == buf);
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}
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/* Start the TX transfer (if it was not already waiting for buffers) */
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@ -509,8 +518,8 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
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/* Setup the TX timeout watchdog (perhaps restarting the timer) */
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(void)wd_start(priv->txtimeout, KINETIS_TXTIMEOUT, kinetis_txtimeout_expiry, 1,
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(wdparm_t)priv);
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(void)wd_start(priv->txtimeout, KINETIS_TXTIMEOUT, kinetis_txtimeout_expiry,
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1, (wdparm_t)priv);
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return OK;
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}
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@ -518,8 +527,9 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
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* Function: kinetis_txpoll
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*
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* Description:
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* The transmitter is available, check if the network has any outgoing packets ready
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* to send. This is a callback from devif_poll(). devif_poll() may be called:
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* The transmitter is available, check if the network has any outgoing
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* packets ready to send. This is a callback from devif_poll().
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* devif_poll() may be called:
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*
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* 1. When the preceding TX packet send is complete,
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* 2. When the preceding TX packet send timesout and the interface is reset
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@ -576,11 +586,11 @@ static int kinetis_txpoll(struct net_driver_s *dev)
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/* Send the packet */
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kinetis_transmit(priv);
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priv->dev.d_buf =
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(uint8_t*)kinesis_swap32((uint32_t)priv->txdesc[priv->txhead].data);
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priv->dev.d_buf = (uint8_t *)
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kinesis_swap32((uint32_t)priv->txdesc[priv->txhead].data);
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/* Check if there is room in the device to hold another packet. If not,
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* return a non-zero value to terminate the poll.
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/* Check if there is room in the device to hold another packet.
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* If not, return a non-zero value to terminate the poll.
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*/
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if (kinetis_txringfull(priv))
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@ -741,14 +751,14 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
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NETDEV_RXDROPPED(&priv->dev);
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}
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/* Point the packet buffer back to the next TX buffer, which will be used during
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* the next write. If the write queue is full, then this will point at an active
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* buffer, which must not be written to. This is OK because devif_poll won't be
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* called unless the queue is not full.
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/* Point the packet buffer back to the next TX buffer, which will be used
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* during the next write. If the write queue is full, then this will
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* point at an active buffer, which must not be written to. This is OK
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* because devif_poll won't be called unless the queue is not full.
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*/
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priv->dev.d_buf =
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(uint8_t*)kinesis_swap32((uint32_t)priv->txdesc[priv->txhead].data);
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(uint8_t *)kinesis_swap32((uint32_t)priv->txdesc[priv->txhead].data);
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priv->rxdesc[priv->rxtail].status1 |= RXDESC_E;
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/* Update the index to the next descriptor */
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@ -817,8 +827,8 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
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putreg32(regval, KINETIS_ENET_EIMR);
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}
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/* There should be space for a new TX in any event. Poll the network for new XMIT
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* data
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/* There should be space for a new TX in any event. Poll the network for
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* new XMIT data
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*/
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(void)devif_poll(&priv->dev, kinetis_txpoll);
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@ -1068,9 +1078,9 @@ static void kinetis_poll_work(FAR void *arg)
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net_lock();
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if (!kinetis_txringfull(priv))
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{
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/* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
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* might be bug here. Does this mean if there is a transmit in progress,
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* we will missing TCP time state updates?
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/* If so, update TCP timing states and poll the network for new XMIT
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* data. Hmmm..might be bug here. Does this mean if there is a transmit
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* in progress, we will missing TCP time state updates?
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*/
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(void)devif_timer(&priv->dev, kinetis_txpoll);
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@ -1139,6 +1149,10 @@ static int kinetis_ifup(struct net_driver_s *dev)
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
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#if defined(PIN_ENET_PHY_EN)
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kinetis_gpiowrite(PIN_ENET_PHY_EN, true);
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#endif
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/* Initialize ENET buffers */
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kinetis_initbuffers(priv);
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@ -1286,6 +1300,10 @@ static int kinetis_ifdown(struct net_driver_s *dev)
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kinetis_reset(priv);
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#if defined(PIN_ENET_PHY_EN)
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kinetis_gpiowrite(PIN_ENET_PHY_EN, false);
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#endif
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/* Mark the device "down" */
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priv->bifup = false;
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@ -1409,8 +1427,8 @@ static int kinetis_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
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* Function: kinetis_rmmac
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*
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* Description:
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* NuttX Callback: Remove the specified MAC address from the hardware multicast
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* address filtering
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* NuttX Callback: Remove the specified MAC address from the hardware
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* multicast address filtering
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*
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* Input Parameters:
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* dev - Reference to the NuttX driver state structure
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@ -1779,9 +1797,11 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
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}
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else
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{
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/* TODO: Autonegotitation has right now failed. Maybe the Eth cable is not connected.
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PHY chip have mechanisms to configure link OK. We should leave autconf on,
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and find a way to re-configure MCU whenever the link is ready. */
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/* TODO: Autonegotitation has right now failed. Maybe the Eth cable is
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* not connected. PHY chip have mechanisms to configure link OK.
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* We should leave autconf on, and find a way to re-configure the
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* MCU whenever the link is ready.
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*/
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ninfo("%s: Autonegotiation failed [%d] (is cable plugged-in ?), default to 10Mbs mode\n", \
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BOARD_PHY_NAME, retries);
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@ -1800,7 +1820,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
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nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n",
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BOARD_PHY_NAME, BOARD_PHY_STATUS, ret);
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return ret;
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}
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}
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ninfo("%s: BOARD_PHY_STATUS: %04x\n", BOARD_PHY_NAME, phydata);
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@ -1861,6 +1881,44 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
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return -EIO;
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}
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#if defined(CONFIG_ETH0_PHY_TJA1100)
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/* The NXP TJA1100 PHY is an automotive 100BASE-T1 PHY
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* Which requires additional initialization
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*/
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/* select mode TJA1100 */
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kinetis_writemii(priv, phyaddr, MII_TJA1100_EXT_CNTRL,
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(MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_EN |
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MII_EXT_CNTRL_CONFIG_INH));
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# if defined(CONFIG_PHY_100BASE_T1_MASTER)
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/* Set TJA1100 in master mode */
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kinetis_writemii(priv, phyaddr, MII_TJA1100_CONFIG1,
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(MII_CONFIG1_MASTER | MII_CONFIG1_TX_1250MV |
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MII_CONFIG1_RMII_25MHZ | MII_CONFIG1_LED_EN));
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# else
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/* Set TJA1100 in slave mode */
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kinetis_writemii(priv, phyaddr, MII_TJA1100_CONFIG1,
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(MII_CONFIG1_TX_1250MV | MII_CONFIG1_RMII_25MHZ |
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MII_CONFIG1_LED_EN));
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# endif
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kinetis_writemii(priv, phyaddr, MII_TJA1100_CONFIG2,
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(MII_CONFIG2_SNR_AV64 | MII_CONFIG2_WLIM_D |
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MII_CONFIG2_SNR_F_NL | MII_CONFIG2_SLP_T_1));
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/* Select normal mode TJA1100 */
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kinetis_writemii(priv, phyaddr, MII_TJA1100_EXT_CNTRL,
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(MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_INH));
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kinetis_writemii(priv, phyaddr, MII_TJA1100_EXT_CNTRL,
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(MII_EXT_CNTRL_LINK_CNTRL | MII_EXT_CNTRL_NORMAL |
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MII_EXT_CNTRL_CONFIG_INH));
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#endif
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putreg32(rcr, KINETIS_ENET_RCR);
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putreg32(tcr, KINETIS_ENET_TCR);
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return OK;
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@ -1930,8 +1988,8 @@ static void kinetis_initbuffers(struct kinetis_driver_s *priv)
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/* Set the wrap bit in the last descriptors to form a ring */
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priv->txdesc[CONFIG_KINETIS_ENETNTXBUFFERS-1].status1 |= TXDESC_W;
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priv->rxdesc[CONFIG_KINETIS_ENETNRXBUFFERS-1].status1 |= RXDESC_W;
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priv->txdesc[CONFIG_KINETIS_ENETNTXBUFFERS - 1].status1 |= TXDESC_W;
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priv->rxdesc[CONFIG_KINETIS_ENETNRXBUFFERS - 1].status1 |= RXDESC_W;
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/* We start with RX descriptor 0 and with no TX descriptors in use */
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@ -1942,7 +2000,7 @@ static void kinetis_initbuffers(struct kinetis_driver_s *priv)
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/* Initialize the packet buffer, which is used when sending */
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priv->dev.d_buf =
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(uint8_t*)kinesis_swap32((uint32_t)priv->txdesc[priv->txhead].data);
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(uint8_t *)kinesis_swap32((uint32_t)priv->txdesc[priv->txhead].data);
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}
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/****************************************************************************
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@ -1969,12 +2027,23 @@ static void kinetis_reset(struct kinetis_driver_s *priv)
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putreg32(ENET_ECR_RESET, KINETIS_ENET_ECR);
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#ifdef PIN_ENET_PHY_RST
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kinetis_gpiowrite(PIN_ENET_PHY_RST, false);
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#endif
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/* Wait at least 8 clock cycles */
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for (i = 0; i < 10; i++)
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{
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asm volatile ("nop");
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}
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#ifdef PIN_ENET_PHY_RST
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/* Wait at least 20us */
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up_udelay(21);
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kinetis_gpiowrite(PIN_ENET_PHY_RST, true);
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#endif
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}
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/****************************************************************************
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@ -2075,6 +2144,14 @@ int kinetis_netinitialize(int intf)
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kinetis_pinconfig(PIN_RMII0_TXEN);
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#endif
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#ifdef PIN_ENET_PHY_EN
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kinetis_pinconfig(PIN_ENET_PHY_EN);
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#endif
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#ifdef PIN_ENET_PHY_RST
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kinetis_pinconfig(PIN_ENET_PHY_RST);
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#endif
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/* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */
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#if 0
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@ -2138,18 +2215,18 @@ int kinetis_netinitialize(int intf)
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priv->txtimeout = wd_create(); /* Create TX timeout timer */
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#ifdef CONFIG_NET_ETHERNET
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/* Determine a semi-unique MAC address from MCU UID
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* We use UID Low and Mid Low registers to get 64 bits, from which we keep
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* 48 bits. We then force unicast and locally administered bits (b0 and b1,
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* 1st octet)
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*/
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/* Determine a semi-unique MAC address from MCU UID
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* We use UID Low and Mid Low registers to get 64 bits, from which we keep
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* 48 bits. We then force unicast and locally administered bits (b0 and b1,
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* 1st octet)
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*/
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uidl = getreg32(KINETIS_SIM_UIDL);
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uidml = getreg32(KINETIS_SIM_UIDML);
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mac = priv->dev.d_mac.ether.ether_addr_octet;
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uidml |= 0x00000200;
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uidml &= 0x0000FEFF;
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uidml &= 0x0000feff;
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mac[0] = (uidml & 0x0000ff00) >> 8;
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mac[1] = (uidml & 0x000000ff);
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@ -396,6 +396,9 @@ config ETH0_PHY_KSZ90x1
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config ETH0_PHY_DP83848C
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bool "National Semiconductor DP83848C PHY"
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config ETH0_PHY_TJA1100
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bool "NXP TJA1100 PHY"
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config ETH0_PHY_LAN8720
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bool "SMSC LAN8720 PHY"
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@ -444,6 +447,9 @@ config ETH1_PHY_KSZ90x1
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config ETH1_PHY_DP83848C
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bool "National Semiconductor DP83848C PHY"
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config ETH1_PHY_TJA1100
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bool "NXP TJA1100 PHY"
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config ETH1_PHY_LAN8720
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bool "SMSC LAN8720 PHY"
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@ -452,6 +458,25 @@ config ETH1_PHY_DM9161
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endchoice
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if (ETH0_PHY_TJA1100 || ETH1_PHY_TJA1100)
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choice
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prompt "Automotive Ethernet 100BASE-T1 master/slave mode"
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default PHY_100BASE_T1_SLAVE
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---help---
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Automotive Ethernet 100BASE-T1 requires the PHY to be configured
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in either master or slave mode.
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config PHY_100BASE_T1_MASTER
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bool "Master"
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config PHY_100BASE_T1_SLAVE
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bool "Slave"
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endchoice # 100BASE-T1 master/slave mode
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endif
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config NETDEV_PHY_DEBUG
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bool "PHY debug"
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default n
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@ -220,6 +220,7 @@
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#define MII_MSR_100BASET4 (1 << 15) /* Bit 15: 100BASE-T4 able */
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/* MII ID1 register bits: Bits 3-18 of the Organizationally Unique identifier (OUI) */
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/* MII ID2 register bits */
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#define MII_PHYID2_REV_SHIFT (0) /* Bits 0-3: Revision number mask */
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@ -329,6 +330,7 @@
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#define DP83840_PHYADDR_SPEED (1 << 6)
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/* National Semiconductor DP83848C ******************************************/
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/* DP83848C MII ID1/2 register bits */
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#define MII_PHYID1_DP83848C 0x2000 /* ID1 value for DP83848C */
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@ -347,6 +349,7 @@
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#define MII_RBR_RMIIMODE (1 << 5) /* Bit 5: 0=MII mode 1=RMII mode */
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/* SMSC LAN8720 *************************************************************/
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/* SMSC LAN8720 MII ID1/2 register bits */
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#define MII_PHYID1_LAN8720 0x0007 /* ID1 value for LAN8720 */
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@ -404,6 +407,7 @@
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#define MII_PHYID2_LAN8742A 0xc130 /* ID2 value for LAN8742A */
|
||||
|
||||
/* Am79c874-specific register bit settings **********************************/
|
||||
|
||||
/* Am79c874 MII ID1/2 register bits */
|
||||
|
||||
#define MII_PHYID1_AM79C874 0x0022 /* ID1 value for Am79c874 */
|
||||
|
|
@ -417,6 +421,7 @@
|
|||
#define AM79C874_DIAG_FULLDPLX (1 << 11) /* Bit 11: 1=ANEG result is full duplex */
|
||||
|
||||
/* LM3S6918-specific register bit settings **********************************/
|
||||
|
||||
/* LM3S6918 Vendor-Specific, address 0x10 */
|
||||
|
||||
#define LM_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/
|
||||
|
|
@ -494,6 +499,7 @@
|
|||
#define LM_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */
|
||||
|
||||
/* KS8921-specific register bit settings ************************************/
|
||||
|
||||
/* KS8921 MII Control register bit definitions (not in 802.3) */
|
||||
|
||||
#define KS8721_MCR_DISABXMT (1 << 0) /* Bit 0: Disable Transmitter */
|
||||
|
|
@ -548,6 +554,7 @@
|
|||
#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */
|
||||
|
||||
/* KSZ8051/81-specific register bit settings ********************************/
|
||||
|
||||
/* KSZ8041/51/81 MII ID1/2 register bits */
|
||||
|
||||
#define MII_PHYID1_KSZ8041 0x0022 /* ID1 value for Micrel KSZ8041 */
|
||||
|
|
@ -584,6 +591,7 @@
|
|||
#define MII_KSZ80X1_INT_LU (1 << 0) /* Link up interrupt */
|
||||
|
||||
/* KSZ8041 Register 0x1e: PHY Control 1 -- To be provided */
|
||||
|
||||
/* KSZ8041 Register 0x1f: PHY Control 2 */
|
||||
|
||||
#define MII_PHYCTRL2_MDIX (1 << 15) /* Bit 15: Micrel/HP MDI/MDI-X state */
|
||||
|
|
@ -626,6 +634,118 @@
|
|||
# define MII_PHYCTRL1_MODE_10FDX (5 << MII_PHYCTRL1_MODE_SHIFT) /* 10Base-T full-duplex */
|
||||
# define MII_PHYCTRL1_MODE_100FDX (6 << MII_PHYCTRL1_MODE_SHIFT) /* 100Base-T full-duplex */
|
||||
|
||||
/* TJA1100 register bit settings *************************************************************/
|
||||
|
||||
/* TJA1100 MII ID1/2 register bits */
|
||||
|
||||
#define MII_PHYID1_TJA1100 0x0180 /* ID1 value for NXP TJA1100 */
|
||||
#define MII_PHYID2_TJA1100 0xdc40 /* ID2 value for NXP TJA1100 */
|
||||
|
||||
#define MII_TJA1100_BCR 0x0 /* Basic Control register */
|
||||
#define MII_TJA1100_BSR 0x1 /* Basic Status register */
|
||||
#define MII_TJA1100_EXT_CNTRL 0x11 /* Extra control register */
|
||||
#define MII_TJA1100_CONFIG1 0x12 /* CONFIG 1 register */
|
||||
#define MII_TJA1100_CONFIG2 0x13 /* CONFIG 2 register */
|
||||
|
||||
/* MII_TJA1100_EXT_CNTRL */
|
||||
|
||||
#define MII_EXT_CNTRL_LINK_CNTRL (1 << 15)
|
||||
#define MII_EXT_CNTRL_POWER_MODE_SHIFT (11)
|
||||
#define MII_EXT_CNTRL_POWER_MODE_MASK (0xf << MII_EXT_CNTRL_POWER_MODE_SHIFT)
|
||||
# define MII_EXT_CNTRL_NOCHANGE (0x0 << MII_EXT_CNTRL_POWER_MODE_SHIFT)
|
||||
# define MII_EXT_CNTRL_NORMAL (0x3 << MII_EXT_CNTRL_POWER_MODE_SHIFT)
|
||||
# define MII_EXT_CNTRL_STBY (0xc << MII_EXT_CNTRL_POWER_MODE_SHIFT)
|
||||
# define MII_EXT_CNTRL_SLEEP_REQ (0xb << MII_EXT_CNTRL_POWER_MODE_SHIFT)
|
||||
# define MII_EXT_CNTRL_PWR_MASK (0xf << MII_EXT_CNTRL_POWER_MODE_SHIFT)
|
||||
#define MII_EXT_CNTRL_SLAVE_JITTER_TEST (1 << 10)
|
||||
#define MII_EXT_CNTRL_TRAIN (1 << 9)
|
||||
|
||||
#define MII_EXT_CNTRL_TEST_SHIFT (6)
|
||||
#define MII_EXT_CNTRL_TEST_MASK (7 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST1 (1 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST2 (2 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST3 (3 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST4 (4 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST5 (5 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST6 (6 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
# define MII_EXT_CNTRL_TEST7 (7 << MII_EXT_CNTRL_TEST_SHIFT)
|
||||
#define MII_EXT_CNTRL_CABLE_TST (1 << 5)
|
||||
#define MII_EXT_CNTRL_LOOPBACK_MODE_SHIFT (3)
|
||||
#define MII_EXT_CNTRL_LOOPBACK_MODE_MASK (3 << MII_EXT_CNTRL_LOOPBACK_MODE_SHIFT)
|
||||
#define MII_EXT_CNTRL_INT_LPB (0 << MII_EXT_CNTRL_LOOPBACK_MODE_SHIFT)
|
||||
#define MII_EXT_CNTRL_EXT1_LPB (1 << MII_EXT_CNTRL_LOOPBACK_MODE_SHIFT)
|
||||
#define MII_EXT_CNTRL_EXT2_LPB (2 << MII_EXT_CNTRL_LOOPBACK_MODE_SHIFT)
|
||||
#define MII_EXT_CNTRL_REM_LPB (3 << MII_EXT_CNTRL_LOOPBACK_MODE_SHIFT)
|
||||
#define MII_EXT_CNTRL_CONFIG_EN (1 << 2)
|
||||
#define MII_EXT_CNTRL_CONFIG_INH (1 << 1)
|
||||
#define MII_EXT_CNTRL_WAKE_REQ (1 << 0) /* transmit idle symbols as bus wake-up request */
|
||||
|
||||
/* MII_TJA1100_CONFIG1 */
|
||||
|
||||
#define MII_CONFIG1_MASTER (1 << 15)
|
||||
#define MII_CONFIG1_AUTO_OP (1 << 14)
|
||||
#define MII_CONFIG1_LINK_15M (1 << 13) /* cable length > 15 m */
|
||||
#define MII_CONFIG1_TX_AMPLITUDE_SHIFT (10)
|
||||
#define MII_CONFIG1_TX_AMPLITUDE_MASK (3 << MII_CONFIG1_TX_AMPLITUDE_SHIFT)
|
||||
# define MII_CONFIG1_TX_500MV (0 << MII_CONFIG1_TX_AMPLITUDE_SHIFT)
|
||||
# define MII_CONFIG1_TX_750MV (1 << MII_CONFIG1_TX_AMPLITUDE_SHIFT)
|
||||
# define MII_CONFIG1_TX_1000MV (2 << MII_CONFIG1_TX_AMPLITUDE_SHIFT)
|
||||
# define MII_CONFIG1_TX_1250MV (3 << MII_CONFIG1_TX_AMPLITUDE_SHIFT)
|
||||
#define MII_CONFIG1_MII_MODE_SHIFT (8)
|
||||
#define MII_CONFIG1_MII_MODE_MASK (3 << MII_CONFIG1_MII_MODE_SHIFT)
|
||||
# define MII_CONFIG1_MII_MODE (0 << MII_CONFIG1_MII_MODE_SHIFT)
|
||||
# define MII_CONFIG1_RMII_50MHZ (1 << MII_CONFIG1_MII_MODE_SHIFT)
|
||||
# define MII_CONFIG1_RMII_25MHZ (2 << MII_CONFIG1_MII_MODE_SHIFT)
|
||||
# define MII_CONFIG1_REV_MII (3 << MII_CONFIG1_MII_MODE_SHIFT)
|
||||
#define MII_CONFIG1_MII_DRV_RED (1 << 7) /* reduced strength MII output driver */
|
||||
#define MII_CONFIG1_LEDLINK_SHIFT (4)
|
||||
#define MII_CONFIG1_LEDLINK_MASK (3 << MII_CONFIG1_LEDLINK_SHIFT)
|
||||
# define MII_CONFIG1_LEDLINK (0 << MII_CONFIG1_LEDLINK_SHIFT)
|
||||
# define MII_CONFIG1_LEDFRAME (1 << MII_CONFIG1_LEDLINK_SHIFT)
|
||||
# define MII_CONFIG1_LEDSYMERR (2 << MII_CONFIG1_LEDLINK_SHIFT)
|
||||
# define MII_CONFIG1_LEDCRS (3 << MII_CONFIG1_LEDLINK_SHIFT)
|
||||
#define MII_CONFIG1_LED_EN (1 << 3)
|
||||
#define MII_CONFIG1_CNFG_WAKE (1 << 2) /* ratiometric input threshold, absolute if zero */
|
||||
#define MII_CONFIG1_AUTO_PWD (1 << 1) /* autonomous power-down enabled */
|
||||
|
||||
/* MII_TJA1100_CONFIG2 */
|
||||
|
||||
#define MII_CONFIG2_PHYAD_SHIFT (11) /* readback of scrambler key */
|
||||
#define MII_CONFIG2_PHYAD_MASK (0x1f << MII_CONFIG2_PHYAD_SHIFT)
|
||||
#define MII_CONFIG2_SNR_SHIFT (9) /* signal to noise ratio averaging */
|
||||
#define MII_CONFIG2_SNR_MASK (3 << MII_CONFIG2_SNR_SHIFT)
|
||||
# define MII_CONFIG2_SNR_AV32 (0 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 32 symbols */
|
||||
# define MII_CONFIG2_SNR_AV64 (1 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 64 symbols */
|
||||
# define MII_CONFIG2_SNR_AV128 (2 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 128 symbols */
|
||||
# define MII_CONFIG2_SNR_AV256 (3 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 256 symbols */
|
||||
#define MII_CONFIG2_WLIM_SHIFT (6) /* SQI warning limit */
|
||||
#define MII_CONFIG2_WLIM_MASK (7 << MII_CONFIG2_WLIM_SHIFT)
|
||||
# define MII_CONFIG2_WLIM_NO (0 << MII_CONFIG2_WLIM_SHIFT) /* no warning */
|
||||
# define MII_CONFIG2_WLIM_A (1 << MII_CONFIG2_WLIM_SHIFT) /* Class A SNR warning limit */
|
||||
# define MII_CONFIG2_WLIM_B (2 << MII_CONFIG2_WLIM_SHIFT) /* Class B SNR warning limit */
|
||||
# define MII_CONFIG2_WLIM_C (3 << MII_CONFIG2_WLIM_SHIFT) /* Class C SNR warning limit */
|
||||
# define MII_CONFIG2_WLIM_D (4 << MII_CONFIG2_WLIM_SHIFT) /* Class D SNR warning limit */
|
||||
# define MII_CONFIG2_WLIM_E (5 << MII_CONFIG2_WLIM_SHIFT) /* Class E SNR warning limit */
|
||||
# define MII_CONFIG2_WLIM_F (6 << MII_CONFIG2_WLIM_SHIFT) /* Class F SNR warning limit */
|
||||
# define MII_CONFIG2_WLIM_G (7 << MII_CONFIG2_WLIM_SHIFT) /* Class G SNR warning limit */
|
||||
#define MII_CONFIG2_SNR_F_SHIFT (3) /* signal to noise ratio fail limit */
|
||||
#define MII_CONFIG2_SNR_F_MASK (7 << MII_CONFIG2_SNR_F_SHIFT))
|
||||
# define MII_CONFIG2_SNR_F_NL (0 << MII_CONFIG2_SNR_F_SHIFT) /* no limit */
|
||||
# define MII_CONFIG2_SNR_F_CLA (1 << MII_CONFIG2_SNR_F_SHIFT) /* Class A */
|
||||
# define MII_CONFIG2_SNR_F_CLB (2 << MII_CONFIG2_SNR_F_SHIFT) /* Class B */
|
||||
# define MII_CONFIG2_SNR_F_CLC (3 << MII_CONFIG2_SNR_F_SHIFT) /* Class C */
|
||||
# define MII_CONFIG2_SNR_F_CLD (4 << MII_CONFIG2_SNR_F_SHIFT) /* Class D */
|
||||
# define MII_CONFIG2_SNR_F_CLE (5 << MII_CONFIG2_SNR_F_SHIFT) /* Class E */
|
||||
# define MII_CONFIG2_SNR_F_CLF (6 << MII_CONFIG2_SNR_F_SHIFT) /* Class F */
|
||||
# define MII_CONFIG2_SNR_F_CLG (7 << MII_CONFIG2_SNR_F_SHIFT) /* Class G */
|
||||
#define MII_CONFIG2_JUMBO_EN (1 << 2) /* enable packets up to 16 kB instead of 4 kB */
|
||||
#define MII_CONFIG2_SLP_T_SHIFT (0) /* sleep request timeout */
|
||||
#define MII_CONFIG2_SLP_T_MASK (3 << MII_CONFIG2_SLP_T_SHIFT)
|
||||
# define MII_CONFIG2_SLP_T_04 (0 << MII_CONFIG2_SLP_T_SHIFT) /* sleep request timeout 0.4 ms */
|
||||
# define MII_CONFIG2_SLP_T_1 (1 << MII_CONFIG2_SLP_T_SHIFT) /* sleep request timeout 1 ms */
|
||||
# define MII_CONFIG2_SLP_T_4 (2 << MII_CONFIG2_SLP_T_SHIFT) /* sleep request timeout 4 ms */
|
||||
# define MII_CONFIG2_SLP_T_16 (3 << MII_CONFIG2_SLP_T_SHIFT) /* sleep request timeout 16 ms */
|
||||
|
||||
/****************************************************************************
|
||||
* Type Definitions
|
||||
****************************************************************************/
|
||||
|
|
|
|||
Loading…
Reference in a new issue