esp32[c3]: Add RTC IRQ support
This commit is contained in:
parent
07f0e0c166
commit
44e118eaf2
5 changed files with 391 additions and 2 deletions
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@ -302,6 +302,13 @@ config ESPRESSIF_GPIO_IRQ
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---help---
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Enable support for interrupting GPIO pins
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config ESPRESSIF_RTCIO_IRQ
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bool "RTC IO interrupts"
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default n
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depends on !ARCH_CHIP_ESP32H2 && !ARCH_CHIP_ESP32C6
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---help---
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Enable support for RTC peripherals interrupts.
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config ESPRESSIF_LEDC
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bool "LEDC (PWM)"
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default n
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@ -31,7 +31,7 @@ CHIP_ASRCS = esp_vectors.S
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# Required Espressif chip's files (arch/risc-v/src/common/espressif)
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CHIP_CSRCS = esp_allocateheap.c esp_start.c esp_idle.c
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CHIP_CSRCS += esp_irq.c esp_gpio.c esp_libc_stubs.c
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CHIP_CSRCS += esp_irq.c esp_gpio.c esp_rtc_gpio.c esp_libc_stubs.c
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CHIP_CSRCS += esp_lowputc.c esp_serial.c
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CHIP_CSRCS += esp_systemreset.c
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@ -107,7 +107,7 @@ endif
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ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
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ifndef ESP_HAL_3RDPARTY_VERSION
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ESP_HAL_3RDPARTY_VERSION = 581540ed0a5ce9674da44f9ece6a63d052058985
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ESP_HAL_3RDPARTY_VERSION = ee8c7b0ad6a117465312d4c9a6e654cb7b2b9469
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endif
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ifndef ESP_HAL_3RDPARTY_URL
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@ -37,6 +37,7 @@
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#include "esp_gpio.h"
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#include "esp_irq.h"
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#include "esp_rtc_gpio.h"
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#include "esp_attr.h"
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#include "esp_bit_defs.h"
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@ -320,6 +321,10 @@ void up_irqinitialize(void)
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esp_gpioirqinitialize();
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#endif
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/* Initialize RTCIO interrupt support */
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esp_rtcioirqinitialize();
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/* Attach the common interrupt handler */
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riscv_exception_attach();
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264
arch/risc-v/src/common/espressif/esp_rtc_gpio.c
Normal file
264
arch/risc-v/src/common/espressif/esp_rtc_gpio.c
Normal file
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@ -0,0 +1,264 @@
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/****************************************************************************
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* arch/risc-v/src/common/espressif/esp_rtc_gpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <debug.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <sys/types.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "irq.h"
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#include "riscv_internal.h"
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#include "esp_irq.h"
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#include "esp_rtc_gpio.h"
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#include "soc/rtc_io_periph.h"
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#include "hal/rtc_io_hal.h"
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#include "soc/rtc_cntl_periph.h"
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#include "soc/periph_defs.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_ARCH_CHIP_ESP32C3_GENERIC
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#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ
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static int g_rtcio_cpuint;
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static uint32_t last_status;
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#ifdef CONFIG_ARCH_CHIP_ESP32C3_GENERIC
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static const int rtc_irq_reg_shift[ESP_NIRQ_RTCIO] =
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{
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RTC_CNTL_SLP_WAKEUP_INT_ENA_S,
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RTC_CNTL_SLP_REJECT_INT_ENA_S,
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RTC_CNTL_WDT_INT_ENA_S,
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RTC_CNTL_BROWN_OUT_INT_ENA_S,
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RTC_CNTL_MAIN_TIMER_INT_ENA_S,
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RTC_CNTL_SWD_INT_ENA_S,
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RTC_CNTL_XTAL32K_DEAD_INT_ENA_S,
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RTC_CNTL_GLITCH_DET_INT_ENA_S,
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RTC_CNTL_BBPLL_CAL_INT_ENA_S
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};
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#define RTC_IRQ_REG_SHIFT(x) rtc_irq_reg_shift[x]
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#endif /* CONFIG_ARCH_CHIP_ESP32C3 */
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#endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rtcio_dispatch
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*
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* Description:
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* Second level dispatch for the RTC interrupt.
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*
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* Input Parameters:
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* irq - The IRQ number;
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* reg_status - Pointer to a copy of the interrupt status register.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ
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static void rtcio_dispatch(int irq, uint32_t *reg_status)
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{
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uint32_t status = *reg_status;
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uint32_t mask;
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int i;
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/* Check each bit in the status register */
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for (i = 0; i < ESP_NIRQ_RTCIO && status != 0; i++)
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{
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/* Check if there is an interrupt pending for this type */
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mask = (UINT32_C(1) << RTC_IRQ_REG_SHIFT(i));
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if ((status & mask) != 0)
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{
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/* Yes... perform the second level dispatch. The IRQ context will
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* contain the contents of the status register.
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*/
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irq_dispatch(irq + i, (void *)reg_status);
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/* Clear the bit in the status so that we might execute this loop
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* sooner.
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*/
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status &= ~mask;
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}
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}
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}
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/****************************************************************************
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* Name: rtcio_interrupt
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*
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* Description:
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* RTC interrupt handler.
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*
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* Input Parameters:
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* irq - The IRQ number;
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* context - The interrupt context;
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* args - The arguments passed to the handler.
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*
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* Returned Value:
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* Zero (OK).
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*
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****************************************************************************/
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static int rtcio_interrupt(int irq, void *context, void *arg)
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{
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/* Read and clear the lower RTC interrupt status */
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last_status = getreg32(RTC_CNTL_INT_ST_REG);
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putreg32(last_status, RTC_CNTL_INT_CLR_REG);
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/* Dispatch pending interrupts in the RTC status register */
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rtcio_dispatch(ESP_FIRST_RTCIOIRQ, &last_status);
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return OK;
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}
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#endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: esp_rtcioirqinitialize
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*
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* Description:
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* Initialize logic to support a second level of interrupt decoding for
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* RTC IRQs.
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*
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* Input Parameters:
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* None.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ
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void esp_rtcioirqinitialize(void)
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{
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/* Setup the RTCIO interrupt. */
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g_rtcio_cpuint = esp_setup_irq(ETS_RTC_CORE_INTR_SOURCE,
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1, ESP_IRQ_TRIGGER_LEVEL);
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DEBUGASSERT(g_rtcio_cpuint >= 0);
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/* Attach and enable the interrupt handler */
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DEBUGVERIFY(irq_attach(ESP_IRQ_RTC_CORE, rtcio_interrupt, NULL));
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up_enable_irq(ESP_IRQ_RTC_CORE);
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}
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/****************************************************************************
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* Name: esp_rtcioirqenable
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*
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* Description:
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* Enable the interrupt for the specified RTC peripheral IRQ.
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*
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* Input Parameters:
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* irq - The IRQ number.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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void esp_rtcioirqenable(int irq)
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{
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uintptr_t regaddr = RTC_CNTL_INT_ENA_REG;
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uint32_t regval;
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int bit;
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DEBUGASSERT(irq >= ESP_FIRST_RTCIOIRQ &&
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irq <= ESP_LAST_RTCIOIRQ);
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/* Convert the IRQ number to the corresponding bit */
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bit = RTC_IRQ_REG_SHIFT(irq - ESP_FIRST_RTCIOIRQ);
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/* Get the address of the GPIO PIN register for this pin */
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up_disable_irq(ESP_IRQ_RTC_CORE);
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regval = getreg32(regaddr) | (UINT32_C(1) << bit);
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putreg32(regval, regaddr);
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up_enable_irq(ESP_IRQ_RTC_CORE);
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}
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/****************************************************************************
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* Name: esp_rtcioirqdisable
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*
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* Description:
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* Disable the interrupt for the specified RTC peripheral IRQ.
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*
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* Input Parameters:
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* irq - The IRQ number.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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void esp_rtcioirqdisable(int irq)
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{
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uintptr_t regaddr = RTC_CNTL_INT_ENA_REG;
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uint32_t regval;
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int bit;
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DEBUGASSERT(irq >= ESP_FIRST_RTCIOIRQ &&
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irq <= ESP_LAST_RTCIOIRQ);
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/* Convert the IRQ number to the corresponding bit */
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bit = RTC_IRQ_REG_SHIFT(irq - ESP_FIRST_RTCIOIRQ);
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/* Disable IRQ */
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up_disable_irq(ESP_IRQ_RTC_CORE);
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regval = getreg32(regaddr) & (~(UINT32_C(1) << bit));
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putreg32(regval, regaddr);
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up_enable_irq(ESP_IRQ_RTC_CORE);
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}
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#endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */
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#endif /* CONFIG_ARCH_CHIP_ESP32C3_GENERIC */
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113
arch/risc-v/src/common/espressif/esp_rtc_gpio.h
Normal file
113
arch/risc-v/src/common/espressif/esp_rtc_gpio.h
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/****************************************************************************
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* arch/risc-v/src/common/espressif/esp_rtc_gpio.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H
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#define __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include <stdint.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp_rtcioirqinitialize
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*
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* Description:
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* Initialize logic to support a second level of interrupt decoding for
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* RTC IRQs.
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*
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* Input Parameters:
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* None.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ
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void esp_rtcioirqinitialize(void);
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#else
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# define esp_rtcioirqinitialize()
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#endif
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/****************************************************************************
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* Name: esp_rtcioirqenable
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*
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* Description:
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* Enable the interrupt for the specified RTC peripheral IRQ.
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*
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* Input Parameters:
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* irq - The IRQ number.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ
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void esp_rtcioirqenable(int irq);
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#else
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# define esp_rtcioirqenable(irq)
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#endif
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/****************************************************************************
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* Name: esp_rtcioirqdisable
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*
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* Description:
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* Disable the interrupt for the specified RTC peripheral IRQ.
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*
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* Input Parameters:
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* irq - The IRQ number.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ
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void esp_rtcioirqdisable(int irq);
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#else
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# define esp_rtcioirqdisable(irq)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H */
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