Add Timer Support to STM32H5 ADC Driver
Added support for using timers with ADCs. Updated Kconfig to support TRGO2, although driver support for TRGO and TRGO2 not developed yet. Updated hardware/stm32_tim.h with missing CCER bits needed for compilation.
This commit is contained in:
Kyle Wilson
Xiang Xiao
parent
7c7a64c84c
commit
558fe83f6d
4 changed files with 1038 additions and 6 deletions
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@ -2920,10 +2920,10 @@ config STM32H5_ADC1_SAMPLE_FREQUENCY
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config STM32H5_ADC1_TIMTRIG
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int "ADC1 Timer Trigger"
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default 0
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range 0 4
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range 0 5
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depends on STM32H5_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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config STM32H5_ADC2_SAMPLE_FREQUENCY
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int "ADC2 Sampling Frequency"
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@ -2935,10 +2935,10 @@ config STM32H5_ADC2_SAMPLE_FREQUENCY
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config STM32H5_ADC2_TIMTRIG
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int "ADC2 Timer Trigger"
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default 0
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range 0 4
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range 0 5
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depends on STM32H5_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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config STM32H5_TIM1_CAP
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bool "TIM1 Capture"
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@ -363,6 +363,26 @@
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#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
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#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
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#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
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#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
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#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
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#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
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#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
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#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
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#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
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#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
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#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
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#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
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#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
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#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
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#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
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#define STM32_TIM17_DTR2 (STM32_TIM17_BASE+STM32_GTIM_DTR2_OFFSET)
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#define STM32_TIM17_TISEL (STM32_TIM17_BASE+STM32_GTIM_TISEL_OFFSET)
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#define STM32_TIM17_AF1 (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET)
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#define STM32_TIM17_AF2 (STM32_TIM17_BASE+STM32_GTIM_AF2_OFFSET)
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#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
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#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* Basic Timers - TIM6 and TIM7 */
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@ -764,6 +784,12 @@
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#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
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#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
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#define ATIM_CCER_CC4NE (1 << 14) /* Bit 14: Capture/compare 4 Complementary output enable */
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#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
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#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
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#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
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#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
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#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
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#define ATIM_CCER_CCXBASE(ch) ((ch) << 2) /* Each channel uses 4-bits */
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/* Counter Register */
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@ -47,6 +47,7 @@
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#include "chip.h"
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#include "stm32_adc.h"
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#include "stm32_tim.h"
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#include "stm32_rcc.h"
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#ifdef CONFIG_ADC
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@ -166,6 +167,16 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value);
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static void adc_modifyreg(struct stm32_dev_s *priv, int offset,
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uint32_t clrbits, uint32_t setbits);
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#ifdef ADC_HAVE_TIMER
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static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset);
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static void tim_putreg(struct stm32_dev_s *priv, int offset,
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uint16_t value);
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static void tim_modifyreg(struct stm32_dev_s *priv, int offset,
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uint16_t clrbits, uint16_t setbits);
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static void tim_dumpregs(struct stm32_dev_s *priv,
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const char *msg);
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#endif
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/* ADC Miscellaneous Helpers */
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static void adc_rccreset(struct stm32_dev_s *priv, bool reset);
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@ -178,6 +189,11 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr);
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static void adc_startconv(struct stm32_dev_s *priv, bool enable);
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static void adc_wdog_enable(struct stm32_dev_s *priv);
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#ifdef ADC_HAVE_TIMER
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static void adc_timstart(struct stm32_dev_s *priv, bool enable);
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static int adc_timinit(struct stm32_dev_s *priv);
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#endif
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/* ADC Interrupt Handler */
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static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval);
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@ -220,6 +236,15 @@ static struct stm32_dev_s g_adcpriv1 =
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.base = STM32_ADC1_BASE,
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.mbase = STM32_ADC1_BASE,
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.initialized = false,
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#ifdef ADC1_HAVE_TIMER
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.trigger = CONFIG_STM32H5_ADC1_TIMTRIG,
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.tbase = ADC1_TIMER_BASE,
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.trcc_enr = ADC1_TIMER_RCC_ENR,
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.trcc_en = ADC1_TIMER_RCC_EN,
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.extsel = ADC1_EXTSEL_VALUE,
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.pclck = ADC1_TIMER_PCLK_FREQUENCY,
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.freq = CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY,
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#endif
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};
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static struct adc_dev_s g_adcdev1 =
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@ -240,6 +265,15 @@ static struct stm32_dev_s g_adcpriv2 =
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.base = STM32_ADC2_BASE,
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.mbase = STM32_ADC2_BASE,
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.initialized = false,
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#ifdef ADC2_HAVE_TIMER
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.trigger = CONFIG_STM32H5_ADC2_TIMTRIG,
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.tbase = ADC2_TIMER_BASE,
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.trcc_enr = ADC2_TIMER_RCC_ENR,
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.trcc_en = ADC2_TIMER_RCC_EN,
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.extsel = ADC2_EXTSEL_VALUE,
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.pclck = ADC2_TIMER_PCLK_FREQUENCY,
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.freq = CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY,
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#endif
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};
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static struct adc_dev_s g_adcdev2 =
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@ -1212,7 +1246,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
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if ((adcisr & ADC_INT_EOC) != 0)
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{
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/* Read from the ADC_DR register until 8 stage FIFO is empty.
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* The FIFO is first mentioned in STM32H7 Reference Manual
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* The FIFO is first mentioned in STM32H5 Reference Manual
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* rev. 7, though, not yet indicated in the block diagram!
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*/
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@ -1307,6 +1341,521 @@ static int adc12_interrupt(int irq, void *context, void *arg)
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}
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#endif
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/****************************************************************************
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* Name: tim_getreg
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*
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* Description:
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* Read the value of an ADC timer register.
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* The current contents of the specified register
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset)
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{
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return getreg16(priv->tbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: tim_putreg
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*
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* Description:
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* Write a value to an ADC timer register.
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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* offset - The offset to the register to write to
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* value - The value to write to the register
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void tim_putreg(struct stm32_dev_s *priv, int offset,
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uint16_t value)
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{
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putreg16(value, priv->tbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: tim_modifyreg
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*
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* Description:
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* Modify the value of an ADC timer register (not atomic).
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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* offset - The offset to the register to modify
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* clrbits - The bits to clear
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* setbits - The bits to set
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void tim_modifyreg(struct stm32_dev_s *priv, int offset,
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uint16_t clrbits, uint16_t setbits)
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{
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tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits);
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}
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#endif
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/****************************************************************************
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* Name: tim_dumpregs
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*
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* Description:
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* Dump all timer registers.
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg)
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{
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ainfo("%s:\n", msg);
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ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
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tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
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tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
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tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
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tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
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ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
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tim_getreg(priv, STM32_GTIM_SR_OFFSET),
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tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
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tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
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ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
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tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
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tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
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tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
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tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
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ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
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tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
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tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
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tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
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tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
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if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
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{
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ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
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tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
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tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
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tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
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tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
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}
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else
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{
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ainfo(" DCR: %04x DMAR: %04x\n",
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tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
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tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
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}
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}
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#endif
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/****************************************************************************
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* Name: adc_timstart
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*
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* Description:
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* Start (or stop) the timer counter
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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* enable - True: Start conversion
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*
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* Returned Value:
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void adc_timstart(struct stm32_dev_s *priv, bool enable)
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{
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ainfo("enable: %d\n", enable ? 1 : 0);
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if (enable)
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{
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/* Start the counter */
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tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
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}
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else
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{
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/* Disable the counter */
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tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
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}
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}
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#endif
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/****************************************************************************
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* Name: adc_timinit
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*
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* Description:
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* Initialize the timer that drivers the ADC sampling for this channel
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* using the pre-calculated timer divider definitions.
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static int adc_timinit(struct stm32_dev_s *priv)
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{
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uint32_t prescaler;
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uint32_t reload;
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uint32_t timclk;
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uint16_t clrbits = 0;
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uint16_t setbits = 0;
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uint16_t cr2;
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uint16_t ccmr1;
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uint16_t ccmr2;
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uint16_t ocmode1;
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uint16_t ocmode2;
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uint16_t ccenable;
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uint16_t ccer;
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uint16_t egr;
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/* If the timer base address is zero, then this ADC was not configured to
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* use a timer.
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*/
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if (priv->tbase == 0)
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{
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return ERROR;
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}
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/* EXTSEL selection: These bits select the external event used to trigger
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* the start of conversion of a regular group. NOTE:
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*
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* - The position with of the EXTSEL field varies from one STM32 MCU
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* to another.
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* - The width of the EXTSEL field varies from one STM32 MCU to another.
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* - The value in priv->extsel is already shifted into the correct bit
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* position.
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*/
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ainfo("Initializing timers extsel = 0x%08" PRIx32 "\n", priv->extsel);
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adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET,
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ADC_CFGR_EXTEN_MASK | ADC_CFGR_EXTSEL_MASK,
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ADC_CFGR_EXTEN_RISING | priv->extsel);
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/* Configure the timer channel to drive the ADC */
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/* Enable Timer clocking */
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modifyreg32(priv->trcc_enr, 0, priv->trcc_en);
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/* Calculate optimal values for the timer prescaler and for the timer
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* reload register. If freq is the desired frequency, then
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*
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* reload = timclk / freq
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* reload = (pclck / prescaler) / freq
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*
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* There are many solutions to do this, but the best solution will be the
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* one that has the largest reload value and the smallest prescaler value.
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* That is the solution that should give us the most accuracy in the timer
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* control. Subject to:
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*
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* 0 <= prescaler <= 65536
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* 1 <= reload <= 65535
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*
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* So ( prescaler = pclck / 65535 / freq ) would be optimal.
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*/
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prescaler = (priv->pclck / priv->freq + 65534) / 65535;
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/* We need to decrement the prescaler value by one, but only, the value
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* does not underflow.
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*/
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if (prescaler < 1)
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{
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awarn("WARNING: Prescaler underflowed.\n");
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prescaler = 1;
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}
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/* Check for overflow */
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else if (prescaler > 65536)
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{
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awarn("WARNING: Prescaler overflowed.\n");
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prescaler = 65536;
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}
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timclk = priv->pclck / prescaler;
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reload = timclk / priv->freq;
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if (reload < 1)
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{
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awarn("WARNING: Reload value underflowed.\n");
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reload = 1;
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}
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else if (reload > 65535)
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{
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awarn("WARNING: Reload value overflowed.\n");
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reload = 65535;
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}
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|
||||
/* Disable the timer until we get it configured */
|
||||
|
||||
adc_timstart(priv, false);
|
||||
|
||||
/* Set up the timer CR1 register.
|
||||
*
|
||||
* Select the Counter Mode == count up:
|
||||
*
|
||||
* ATIM_CR1_EDGE: The counter counts up or down depending on the
|
||||
* direction bit(DIR).
|
||||
* ATIM_CR1_DIR: 0: count up, 1: count down
|
||||
*
|
||||
* Set the clock division to zero for all
|
||||
*/
|
||||
|
||||
clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK;
|
||||
setbits = GTIM_CR1_EDGE;
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits);
|
||||
|
||||
/* Set the reload and prescaler values */
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1);
|
||||
tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
|
||||
|
||||
/* Clear the advanced timers repetition counter in TIM1 */
|
||||
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
|
||||
tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
|
||||
}
|
||||
|
||||
/* TIMx event generation: Bit 0 UG: Update generation */
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
|
||||
/* Handle channel specific setup */
|
||||
|
||||
ocmode1 = 0;
|
||||
ocmode2 = 0;
|
||||
|
||||
switch (priv->trigger)
|
||||
{
|
||||
case 0: /* TimerX CC1 event */
|
||||
{
|
||||
ccenable = ATIM_CCER_CC1E;
|
||||
ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) |
|
||||
ATIM_CCMR1_OC1PE;
|
||||
|
||||
/* Set the event CC1 */
|
||||
|
||||
egr = ATIM_EGR_CC1G;
|
||||
|
||||
/* Set the duty cycle by writing to the CCR register for this
|
||||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: /* TimerX CC2 event */
|
||||
{
|
||||
ccenable = ATIM_CCER_CC2E;
|
||||
ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) |
|
||||
ATIM_CCMR1_OC2PE;
|
||||
|
||||
/* Set the event CC2 */
|
||||
|
||||
egr = ATIM_EGR_CC2G;
|
||||
|
||||
/* Set the duty cycle by writing to the CCR register for this
|
||||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* TimerX CC3 event */
|
||||
{
|
||||
ccenable = ATIM_CCER_CC3E;
|
||||
ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) |
|
||||
ATIM_CCMR2_OC3PE;
|
||||
|
||||
/* Set the event CC3 */
|
||||
|
||||
egr = ATIM_EGR_CC3G;
|
||||
|
||||
/* Set the duty cycle by writing to the CCR register for this
|
||||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: /* TimerX CC4 event */
|
||||
{
|
||||
ccenable = ATIM_CCER_CC4E;
|
||||
ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) |
|
||||
ATIM_CCMR2_OC4PE;
|
||||
|
||||
/* Set the event CC4 */
|
||||
|
||||
egr = ATIM_EGR_CC4G;
|
||||
|
||||
/* Set the duty cycle by writing to the CCR register for this
|
||||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 4: /* TimerX TRGO event */
|
||||
{
|
||||
/* TODO: TRGO support not yet implemented */
|
||||
|
||||
/* Set the event TRGO */
|
||||
|
||||
ccenable = 0;
|
||||
egr = GTIM_EGR_TG;
|
||||
|
||||
/* Set the duty cycle by writing to the CCR register for this
|
||||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 5: /* TimerX TRGO2 event */
|
||||
{
|
||||
/* TODO: TRGO2 support not yet implemented */
|
||||
|
||||
/* Set the event TRGO2 */
|
||||
|
||||
ccenable = 0;
|
||||
egr = GTIM_EGR_TG;
|
||||
|
||||
/* Set the duty cycle by writing to the CCR register for this
|
||||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
aerr("ERROR: No such trigger: %d\n", priv->trigger);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Disable the Channel by resetting the CCxE Bit in the CCER register */
|
||||
|
||||
ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET);
|
||||
ccer &= ~ccenable;
|
||||
tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
/* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */
|
||||
|
||||
cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET);
|
||||
ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
|
||||
ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
|
||||
|
||||
/* Reset the Output Compare Mode Bits and set the select output compare
|
||||
* mode
|
||||
*/
|
||||
|
||||
ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE |
|
||||
ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE);
|
||||
ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE |
|
||||
ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE);
|
||||
ccmr1 |= ocmode1;
|
||||
ccmr2 |= ocmode2;
|
||||
|
||||
/* Reset the output polarity level of all channels (selects high
|
||||
* polarity)
|
||||
*/
|
||||
|
||||
ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P |
|
||||
ATIM_CCER_CC3P | ATIM_CCER_CC4P);
|
||||
|
||||
/* Enable the output state of the selected channel (only) */
|
||||
|
||||
ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E |
|
||||
ATIM_CCER_CC3E | ATIM_CCER_CC4E);
|
||||
ccer |= ccenable;
|
||||
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
/* Reset output N polarity level, output N state, output compare state,
|
||||
* output compare N idle state.
|
||||
*/
|
||||
|
||||
ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP |
|
||||
ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
|
||||
ATIM_CCER_CC3NE | ATIM_CCER_CC3NP |
|
||||
ATIM_CCER_CC4NP);
|
||||
|
||||
/* Reset the output compare and output compare N IDLE State */
|
||||
|
||||
cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N |
|
||||
ATIM_CR2_OIS2 | ATIM_CR2_OIS2N |
|
||||
ATIM_CR2_OIS3 | ATIM_CR2_OIS3N |
|
||||
ATIM_CR2_OIS4);
|
||||
}
|
||||
else
|
||||
{
|
||||
ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP);
|
||||
}
|
||||
|
||||
/* Save the modified register values */
|
||||
|
||||
tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2);
|
||||
tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2);
|
||||
tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr);
|
||||
|
||||
/* Set the ARR Preload Bit */
|
||||
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
||||
adc_timstart(priv, true);
|
||||
|
||||
tim_dumpregs(priv, "After starting timers");
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -1369,3 +1918,4 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf,
|
|||
}
|
||||
#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */
|
||||
#endif /* CONFIG_ADC */
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,462 @@
|
|||
|
||||
#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* Timer devices may be used for different purposes. One special purpose is
|
||||
* to control periodic ADC sampling. If CONFIG_STM32H5_TIMn is defined then
|
||||
* CONFIG_STM32H5_TIMn_ADC must also be defined to indicate that timer "n"
|
||||
* is intended to be used for that purpose. Timers 1,2,3,6 and 15 may be
|
||||
* used on STM32H5X3, while STM32H5X6 adds support for timers 4 and 8 as
|
||||
* well.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_STM32H5_TIM1
|
||||
# undef CONFIG_STM32H5_TIM1_ADC
|
||||
# undef CONFIG_STM32H5_TIM1_ADC1
|
||||
# undef CONFIG_STM32H5_TIM1_ADC2
|
||||
# undef CONFIG_STM32H5_TIM1_ADC3
|
||||
#endif
|
||||
#ifndef CONFIG_STM32H5_TIM2
|
||||
# undef CONFIG_STM32H5_TIM2_ADC
|
||||
# undef CONFIG_STM32H5_TIM2_ADC1
|
||||
# undef CONFIG_STM32H5_TIM2_ADC2
|
||||
# undef CONFIG_STM32H5_TIM2_ADC3
|
||||
#endif
|
||||
#ifndef CONFIG_STM32H5_TIM3
|
||||
# undef CONFIG_STM32H5_TIM3_ADC
|
||||
# undef CONFIG_STM32H5_TIM3_ADC1
|
||||
# undef CONFIG_STM32H5_TIM3_ADC2
|
||||
# undef CONFIG_STM32H5_TIM3_ADC3
|
||||
#endif
|
||||
#ifndef CONFIG_STM32H5_TIM4
|
||||
# undef CONFIG_STM32H5_TIM4_ADC
|
||||
# undef CONFIG_STM32H5_TIM4_ADC1
|
||||
# undef CONFIG_STM32H5_TIM4_ADC2
|
||||
# undef CONFIG_STM32H5_TIM4_ADC3
|
||||
#endif
|
||||
#ifndef CONFIG_STM32H5_TIM6
|
||||
# undef CONFIG_STM32H5_TIM6_ADC
|
||||
# undef CONFIG_STM32H5_TIM6_ADC1
|
||||
# undef CONFIG_STM32H5_TIM6_ADC2
|
||||
# undef CONFIG_STM32H5_TIM6_ADC3
|
||||
#endif
|
||||
#ifndef CONFIG_STM32H5_TIM8
|
||||
# undef CONFIG_STM32H5_TIM8_ADC
|
||||
# undef CONFIG_STM32H5_TIM8_ADC1
|
||||
# undef CONFIG_STM32H5_TIM8_ADC2
|
||||
# undef CONFIG_STM32H5_TIM8_ADC3
|
||||
#endif
|
||||
#ifndef CONFIG_STM32H5_TIM15
|
||||
# undef CONFIG_STM32H5_TIM15_ADC
|
||||
# undef CONFIG_STM32H5_TIM15_ADC1
|
||||
# undef CONFIG_STM32H5_TIM15_ADC2
|
||||
# undef CONFIG_STM32H5_TIM15_ADC3
|
||||
#endif
|
||||
|
||||
/* Timer configuration: If a timer trigger is specified, then get
|
||||
* information about the timer.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32H5_TIM1_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN
|
||||
#elif defined(CONFIG_STM32H5_TIM2_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN
|
||||
#elif defined(CONFIG_STM32H5_TIM3_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN
|
||||
#elif defined(CONFIG_STM32H5_TIM4_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN
|
||||
#elif defined(CONFIG_STM32H5_TIM6_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM6_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN
|
||||
#elif defined(CONFIG_STM32H5_TIM8_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN
|
||||
#elif defined(CONFIG_STM32H5_TIM15_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM15_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
|
||||
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
|
||||
# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM15EN
|
||||
#else
|
||||
# undef ADC1_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#ifdef ADC1_HAVE_TIMER
|
||||
# ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY
|
||||
# error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined"
|
||||
# endif
|
||||
# ifndef CONFIG_STM32H5_ADC1_TIMTRIG
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG not defined"
|
||||
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H5_TIM1_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN
|
||||
#elif defined(CONFIG_STM32H5_TIM2_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN
|
||||
#elif defined(CONFIG_STM32H5_TIM3_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN
|
||||
#elif defined(CONFIG_STM32H5_TIM4_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN
|
||||
#elif defined(CONFIG_STM32H5_TIM6_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM6_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN
|
||||
#elif defined(CONFIG_STM32H5_TIM8_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN
|
||||
#elif defined(CONFIG_STM32H5_TIM15_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM15_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
|
||||
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
|
||||
# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM15EN
|
||||
#else
|
||||
# undef ADC2_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#ifdef ADC2_HAVE_TIMER
|
||||
# ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY
|
||||
# error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined"
|
||||
# endif
|
||||
# ifndef CONFIG_STM32H5_ADC2_TIMTRIG
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG not defined"
|
||||
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER)
|
||||
# define ADC_HAVE_TIMER 1
|
||||
#else
|
||||
# undef ADC_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
/* Timer 1 */
|
||||
|
||||
#define ADC1_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
|
||||
#define ADC1_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
|
||||
#define ADC1_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
|
||||
#define ADC1_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
|
||||
#define ADC1_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
|
||||
#define ADC1_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
|
||||
#define ADC2_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
|
||||
#define ADC2_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
|
||||
#define ADC2_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
|
||||
#define ADC2_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
|
||||
#define ADC2_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
|
||||
#define ADC2_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
|
||||
|
||||
/* Timer 2 */
|
||||
|
||||
#define ADC1_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
|
||||
#define ADC1_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
|
||||
#define ADC2_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
|
||||
#define ADC2_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
|
||||
|
||||
/* Timer 3 */
|
||||
|
||||
#define ADC1_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
|
||||
#define ADC1_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
|
||||
#define ADC2_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
|
||||
#define ADC2_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
|
||||
|
||||
/* Timer 4 */
|
||||
|
||||
#define ADC1_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
|
||||
#define ADC1_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
|
||||
#define ADC2_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
|
||||
#define ADC2_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
|
||||
|
||||
/* Timer 6 */
|
||||
|
||||
#define ADC1_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
|
||||
#define ADC2_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
|
||||
|
||||
/* Timer 8 */
|
||||
|
||||
#define ADC1_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
|
||||
#define ADC1_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
|
||||
#define ADC2_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
|
||||
#define ADC2_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
|
||||
|
||||
/* Timer 15 */
|
||||
|
||||
#define ADC1_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
|
||||
#define ADC2_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
|
||||
|
||||
#if defined(CONFIG_STM32H5_TIM1_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM2_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM3_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM4_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM6_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM8_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM15_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H5_TIM1_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM2_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM3_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM4_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM6_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM8_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM15_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
|
|
|||
Loading…
Reference in a new issue