risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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5792d851e5
commit
56a95ad0b5
3 changed files with 10 additions and 25 deletions
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@ -44,8 +44,8 @@ config ARCH_CHIP_BL602
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_F
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_RESET
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---help---
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BouffaloLab BL602(rv32imfc)
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@ -80,9 +80,9 @@ config ARCH_CHIP_C906
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_F
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select ARCH_RV_ISA_D
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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---help---
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THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
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@ -92,9 +92,9 @@ config ARCH_CHIP_MPFS
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_F
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select ARCH_RV_ISA_D
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SPI_CS_CONTROL
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@ -112,8 +112,8 @@ config ARCH_CHIP_RV32M1
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config ARCH_CHIP_QEMU_RV
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bool "QEMU RV"
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select ARCH_RV_ISA_F
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select ARCH_RV_ISA_D
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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---help---
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QEMU Generic RV32 processor
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@ -149,17 +149,6 @@ config ARCH_RV_ISA_C
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bool
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default n
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config ARCH_RV_ISA_F
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bool
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default n
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select ARCH_HAVE_FPU
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config ARCH_RV_ISA_D
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bool
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default n
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depends on ARCH_RV_ISA_F
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select ARCH_HAVE_DPFPU
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config ARCH_FAMILY
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string
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default "rv32" if ARCH_RV32
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@ -81,14 +81,10 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
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ARCHRVISAC = c
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endif
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# ARCH_FPU depends on ARCH_RV_ISA_F
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ifeq ($(CONFIG_ARCH_FPU),y)
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ARCHRVISAF = f
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endif
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# ARCH_DPFPU depends on ARCH_RV_ISA_D and ARCH_FPU
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ifeq ($(CONFIG_ARCH_DPFPU),y)
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ARCHRVISAD = d
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endif
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@ -22,17 +22,17 @@ endchoice
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config ARCH_CHIP_QEMU_RV_ISA_M
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bool "Standard Extension for Integer Multiplication and Division"
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default y
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default n
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select ARCH_RV_ISA_M
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config ARCH_CHIP_QEMU_RV_ISA_A
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bool "Standard Extension for Atomic Instructions"
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default y
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default n
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select ARCH_RV_ISA_A
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config ARCH_CHIP_QEMU_RV_ISA_C
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bool "Standard Extension for Compressed Instructions"
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default y
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default n
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select ARCH_RV_ISA_C
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endif
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