boards/arm/stm32f7: move SPI test logic to common
move STM32F7 SPI test logic to common
This commit is contained in:
raiden00pl
Xiang Xiao
parent
56e07b0606
commit
6f8953ed0b
15 changed files with 427 additions and 838 deletions
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@ -25,3 +25,156 @@ config STM32F7_ROMFS_IMAGEFILE
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depends on STM32F7_ROMFS
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default "../../../rom.img"
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config STM32F7_SPI_TEST
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bool "Enable SPI test"
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default n
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---help---
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Enable Spi test - initialize and configure SPI to send
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STM32F7_SPI_TEST_MESSAGE text. The text is sent on the
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selected SPI Buses with the configured parameters.
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Note the CS lines will not be asserted.
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if STM32F7_SPI_TEST
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config STM32F7_SPI_TEST_MESSAGE
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string "Text to Send on SPI Bus(es)"
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default "Hello World"
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depends on STM32F7_SPI_TEST
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---help---
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Text to sent on SPI bus(es)
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config STM32F7_SPI1_TEST
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bool "Test SPI bus 1"
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default n
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depends on STM32F7_SPI_TEST
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---help---
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Enable Spi test - on SPI BUS 1
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if STM32F7_SPI1_TEST
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config STM32F7_SPI1_TEST_FREQ
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int "SPI 1 Clock Freq in Hz"
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default 1000000
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depends on STM32F7_SPI1_TEST
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---help---
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Sets SPI 1 Clock Freq
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config STM32F7_SPI1_TEST_BITS
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int "SPI 1 number of bits"
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default 8
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depends on STM32F7_SPI1_TEST
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---help---
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Sets SPI 1 bit length
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choice
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prompt "SPI BUS 1 Clock Mode"
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default STM32F7_SPI1_TEST_MODE3
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---help---
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Sets SPI 1 clock mode
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config STM32F7_SPI1_TEST_MODE0
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bool "CPOL=0 CPHA=0"
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config STM32F7_SPI1_TEST_MODE1
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bool "CPOL=0 CPHA=1"
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config STM32F7_SPI1_TEST_MODE2
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bool "CPOL=1 CPHA=0"
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config STM32F7_SPI1_TEST_MODE3
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bool "CPOL=1 CPHA=1"
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endchoice # "SPI BUS 1 Clock Mode"
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endif # STM32F7_SPI1_TEST
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config STM32F7_SPI2_TEST
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bool "Test SPI bus 2"
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default n
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depends on STM32F7_SPI_TEST
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---help---
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Enable Spi test - on SPI BUS 2
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if STM32F7_SPI2_TEST
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config STM32F7_SPI2_TEST_FREQ
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int "SPI 2 Clock Freq in Hz"
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default 12000000
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depends on STM32F7_SPI2_TEST
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---help---
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Sets SPI 2 Clock Freq
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config STM32F7_SPI2_TEST_BITS
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int "SPI 2 number of bits"
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default 8
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depends on STM32F7_SPI2_TEST
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---help---
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Sets SPI 2 bit length
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choice
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prompt "SPI BUS 2 Clock Mode"
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default STM32F7_SPI2_TEST_MODE3
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---help---
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Sets SPI 2 clock mode
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config STM32F7_SPI2_TEST_MODE0
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bool "CPOL=0 CPHA=0"
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config STM32F7_SPI2_TEST_MODE1
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bool "CPOL=0 CPHA=1"
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config STM32F7_SPI2_TEST_MODE2
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bool "CPOL=1 CPHA=0"
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config STM32F7_SPI2_TEST_MODE3
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bool "CPOL=1 CPHA=1"
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endchoice # "SPI BUS 2 Clock Mode"
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endif # STM32F7_SPI2_TEST
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config STM32F7_SPI3_TEST
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bool "Test SPI bus 3"
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default n
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depends on STM32F7_SPI_TEST
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---help---
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Enable Spi test - on SPI BUS 3
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if STM32F7_SPI3_TEST
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config STM32F7_SPI3_TEST_FREQ
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int "SPI 3 Clock Freq in Hz"
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default 40000000
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depends on STM32F7_SPI3_TEST
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---help---
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Sets SPI 3 Clock Freq
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config STM32F7_SPI3_TEST_BITS
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int "SPI 3 number of bits"
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default 8
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depends on STM32F7_SPI3_TEST
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---help---
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Sets SPI 3 bit length
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choice
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prompt "SPI BUS 3 Clock Mode"
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default STM32F7_SPI3_TEST_MODE3
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---help---
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Sets SPI 3 clock mode
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config STM32F7_SPI3_TEST_MODE0
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bool "CPOL=0 CPHA=0"
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config STM32F7_SPI3_TEST_MODE1
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bool "CPOL=0 CPHA=1"
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config STM32F7_SPI3_TEST_MODE2
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bool "CPOL=1 CPHA=0"
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config STM32F7_SPI3_TEST_MODE3
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bool "CPOL=1 CPHA=1"
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endchoice # "SPI BUS 3 Clock Mode"
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endif # STM32F7_SPI3_TEST
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endif # STM32F7_SPI_TEST
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74
boards/arm/stm32f7/common/include/stm32_spitest.h
Normal file
74
boards/arm/stm32f7/common/include/stm32_spitest.h
Normal file
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@ -0,0 +1,74 @@
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/****************************************************************************
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* boards/arm/stm32f7/common/include/stm32_spitest.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H
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#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_spidev_bus_test
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*
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* Description:
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* Called to create the defined SPI buses and test them by initializing
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* them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select).
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*
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****************************************************************************/
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int stm32_spidev_bus_test(void);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H */
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@ -49,4 +49,8 @@ if(CONFIG_BOARDCTL_RESET)
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list(APPEND SRCS stm32_reset.c)
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endif()
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if(CONFIG_STM32F7_SPI_TEST)
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list(APPEND SRCS stm32_spitest.c)
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endif()
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target_sources(board PRIVATE ${SRCS})
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@ -49,6 +49,10 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y)
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CSRCS += stm32_reset.c
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endif
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ifeq ($(CONFIG_STM32F7_SPI_TEST),y)
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CSRCS += stm32_spitest.c
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endif
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DEPPATH += --dep-path src
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VPATH += :src
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CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src
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174
boards/arm/stm32f7/common/src/stm32_spitest.c
Normal file
174
boards/arm/stm32f7/common/src/stm32_spitest.c
Normal file
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@ -0,0 +1,174 @@
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/****************************************************************************
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* boards/arm/stm32f7/common/src/stm32_spitest.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <errno.h>
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#include <debug.h>
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#include <sys/param.h>
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#include <nuttx/spi/spi.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "stm32_spi.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if defined(CONFIG_STM32F7_SPI1_TEST)
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# if defined(CONFIG_STM32F7_SPI1_TEST_MODE0)
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# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0
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# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE1)
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# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1
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# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE2)
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# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2
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# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE3)
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# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3
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# else
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# error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined"
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# endif
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#endif
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#if defined(CONFIG_STM32F7_SPI2_TEST)
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# if defined(CONFIG_STM32F7_SPI2_TEST_MODE0)
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# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0
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# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE1)
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# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1
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# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE2)
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# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2
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# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE3)
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# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3
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# else
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# error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined"
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# endif
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#endif
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#if defined(CONFIG_STM32F7_SPI3_TEST)
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# if defined(CONFIG_STM32F7_SPI3_TEST_MODE0)
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# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0
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# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE1)
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# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1
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# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE2)
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# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2
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# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE3)
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# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3
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# else
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# error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined"
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# endif
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#if defined(CONFIG_STM32F7_SPI1)
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struct spi_dev_s *g_spi1;
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#endif
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#if defined(CONFIG_STM32F7_SPI2)
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struct spi_dev_s *g_spi2;
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#endif
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#if defined(CONFIG_STM32F7_SPI3)
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struct spi_dev_s *g_spi3;
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_spidev_bus_test
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*
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* Description:
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* Called to create the defined SPI buses and test them by initializing
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* them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select).
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*
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****************************************************************************/
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int stm32_spidev_bus_test(void)
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{
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/* Configure and test SPI- */
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uint8_t *tx = (uint8_t *)CONFIG_STM32F7_SPI_TEST_MESSAGE;
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#if defined(CONFIG_STM32F7_SPI1_TEST)
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g_spi1 = stm32_spibus_initialize(1);
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if (!g_spi1)
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{
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syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n");
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return -ENODEV;
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}
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/* Default SPI1 to STM32F7_SPI1_FREQ and mode */
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SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ);
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SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS);
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SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE);
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SPI_EXCHANGE(g_spi1, tx, NULL,
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nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE));
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#endif
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#if defined(CONFIG_STM32F7_SPI2_TEST)
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g_spi2 = stm32_spibus_initialize(2);
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if (!g_spi2)
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{
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syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
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return -ENODEV;
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}
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/* Default SPI2 to STM32F7_SPI2_FREQ and mode */
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SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ);
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SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS);
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SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE);
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SPI_EXCHANGE(g_spi2, tx, NULL,
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nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE));
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#endif
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#if defined(CONFIG_STM32F7_SPI3_TEST)
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g_spi3 = stm32_spibus_initialize(3);
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if (!g_spi3)
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{
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syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
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return -ENODEV;
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}
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/* Default SPI3 to STM32F7_SPI3_FREQ and mode */
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SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ);
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SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS);
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SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE);
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SPI_EXCHANGE(g_spi3, tx, NULL,
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nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE));
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#endif
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return OK;
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}
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@ -80,160 +80,6 @@ config NUCLEO_F722ZE_CONSOLE_NONE
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endchoice # "Select Console wiring"
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config NUCLEO_F722ZE_SPI_TEST
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bool "Enable SPI test"
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default n
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---help---
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Enable Spi test - initialize and configure SPI to send
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NUCLEO_F722ZE_SPI_TEST_MESSAGE text. The text is sent on the
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selected SPI Buses with the configured parameters.
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Note the CS lines will not be asserted.
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if NUCLEO_F722ZE_SPI_TEST
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config NUCLEO_F722ZE_SPI_TEST_MESSAGE
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string "Text to Send on SPI Bus(es)"
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default "Hello World"
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depends on NUCLEO_F722ZE_SPI_TEST
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---help---
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Text to sent on SPI bus(es)
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config NUCLEO_F722ZE_SPI1_TEST
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bool "Test SPI bus 1"
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default n
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depends on NUCLEO_F722ZE_SPI_TEST
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---help---
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Enable Spi test - on SPI BUS 1
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if NUCLEO_F722ZE_SPI1_TEST
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config NUCLEO_F722ZE_SPI1_TEST_FREQ
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int "SPI 1 Clock Freq in Hz"
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default 1000000
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depends on NUCLEO_F722ZE_SPI1_TEST
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---help---
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Sets SPI 1 Clock Freq
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config NUCLEO_F722ZE_SPI1_TEST_BITS
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int "SPI 1 number of bits"
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default 8
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depends on NUCLEO_F722ZE_SPI1_TEST
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---help---
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Sets SPI 1 bit length
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choice
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prompt "SPI BUS 1 Clock Mode"
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default NUCLEO_F722ZE_SPI1_TEST_MODE3
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---help---
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Sets SPI 1 clock mode
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|
||||
config NUCLEO_F722ZE_SPI1_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F722ZE_SPI1_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F722ZE_SPI1_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F722ZE_SPI1_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 1 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F722ZE_SPI1_TEST
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST
|
||||
bool "Test SPI bus 2"
|
||||
default n
|
||||
depends on NUCLEO_F722ZE_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 2
|
||||
|
||||
if NUCLEO_F722ZE_SPI2_TEST
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST_FREQ
|
||||
int "SPI 2 Clock Freq in Hz"
|
||||
default 12000000
|
||||
depends on NUCLEO_F722ZE_SPI2_TEST
|
||||
---help---
|
||||
Sets SPI 2 Clock Freq
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST_BITS
|
||||
int "SPI 2 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F722ZE_SPI2_TEST
|
||||
---help---
|
||||
Sets SPI 2 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 2 Clock Mode"
|
||||
default NUCLEO_F722ZE_SPI2_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 2 clock mode
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F722ZE_SPI2_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 2 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F722ZE_SPI2_TEST
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST
|
||||
bool "Test SPI bus 3"
|
||||
default n
|
||||
depends on NUCLEO_F722ZE_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 3
|
||||
|
||||
if NUCLEO_F722ZE_SPI3_TEST
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST_FREQ
|
||||
int "SPI 3 Clock Freq in Hz"
|
||||
default 40000000
|
||||
depends on NUCLEO_F722ZE_SPI3_TEST
|
||||
---help---
|
||||
Sets SPI 3 Clock Freq
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST_BITS
|
||||
int "SPI 3 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F722ZE_SPI3_TEST
|
||||
---help---
|
||||
Sets SPI 3 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 3 Clock Mode"
|
||||
default NUCLEO_F722ZE_SPI3_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 3 clock mode
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F722ZE_SPI3_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 3 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F722ZE_SPI3_TEST
|
||||
endif # NUCLEO_F722ZE_SPI_TEST
|
||||
|
||||
choice
|
||||
prompt "CAN1 pins selection"
|
||||
default NUCLEO_F722ZE_CAN1_MAP_PD0PD1
|
||||
|
|
|
|||
|
|
@ -229,19 +229,6 @@ int stm32_bringup(void);
|
|||
void stm32_spidev_initialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spidev_bus_test
|
||||
*
|
||||
* Description:
|
||||
* Called to create the defined SPI buses and test them by initializing
|
||||
* them and sending the NUCLEO_SPI_TEST (no chip select).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
|
||||
int stm32_spidev_bus_test(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dma_alloc_init
|
||||
*
|
||||
|
|
|
|||
|
|
@ -50,8 +50,12 @@
|
|||
# include "stm32_romfs.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI_TEST
|
||||
# include "stm32_spitest.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYSTEMTICK_HOOK
|
||||
#include <semaphore.h>
|
||||
# include <semaphore.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -149,7 +153,7 @@ int stm32_bringup(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
|
||||
#ifdef CONFIG_STM32F7_SPI_TEST
|
||||
/* Create SPI interfaces */
|
||||
|
||||
ret = stm32_spidev_bus_test();
|
||||
|
|
|
|||
|
|
@ -47,48 +47,6 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
|
@ -171,18 +129,6 @@ static const uint32_t g_spi3gpio[] =
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
|
||||
# if defined(CONFIG_STM32F7_SPI1)
|
||||
struct spi_dev_s *spi1;
|
||||
# endif
|
||||
# if defined(CONFIG_STM32F7_SPI2)
|
||||
struct spi_dev_s *spi2;
|
||||
# endif
|
||||
# if defined(CONFIG_STM32F7_SPI3)
|
||||
struct spi_dev_s *spi3;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -430,69 +376,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
|||
#endif
|
||||
|
||||
#endif /* CONFIG_SPI_CMDDATA */
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
|
||||
int stm32_spidev_bus_test(void)
|
||||
{
|
||||
/* Configure and test SPI- */
|
||||
|
||||
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE;
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST)
|
||||
spi1 = stm32_spibus_initialize(1);
|
||||
|
||||
if (!spi1)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI1 to NUCLEO_SPI1_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_FREQ);
|
||||
SPI_SETBITS(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_BITS);
|
||||
SPI_SETMODE(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE);
|
||||
SPI_EXCHANGE(spi1, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST)
|
||||
spi2 = stm32_spibus_initialize(2);
|
||||
|
||||
if (!spi2)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI2 to NUCLEO_SPI2_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_FREQ);
|
||||
SPI_SETBITS(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_BITS);
|
||||
SPI_SETMODE(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE);
|
||||
SPI_EXCHANGE(spi2, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST)
|
||||
spi3 = stm32_spibus_initialize(3);
|
||||
|
||||
if (!spi3)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI3 to NUCLEO_SPI3_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_FREQ);
|
||||
SPI_SETBITS(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_BITS);
|
||||
SPI_SETMODE(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE);
|
||||
SPI_EXCHANGE(spi3, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif /* NUCLEO_SPI_TEST */
|
||||
#endif /* defined(CONFIG_SPI) */
|
||||
|
|
|
|||
|
|
@ -80,160 +80,6 @@ config NUCLEO_F746ZG_CONSOLE_NONE
|
|||
|
||||
endchoice # "Select Console wiring"
|
||||
|
||||
config NUCLEO_F746ZG_SPI_TEST
|
||||
bool "Enable SPI test"
|
||||
default n
|
||||
---help---
|
||||
Enable Spi test - initialize and configure SPI to send
|
||||
NUCLEO_F746ZG_SPI_TEST_MESSAGE text. The text is sent on the
|
||||
selected SPI Buses with the configured parameters.
|
||||
Note the CS lines will not be asserted.
|
||||
|
||||
if NUCLEO_F746ZG_SPI_TEST
|
||||
|
||||
config NUCLEO_F746ZG_SPI_TEST_MESSAGE
|
||||
string "Text to Send on SPI Bus(es)"
|
||||
default "Hello World"
|
||||
depends on NUCLEO_F746ZG_SPI_TEST
|
||||
---help---
|
||||
Text to sent on SPI bus(es)
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST
|
||||
bool "Test SPI bus 1"
|
||||
default n
|
||||
depends on NUCLEO_F746ZG_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 1
|
||||
|
||||
if NUCLEO_F746ZG_SPI1_TEST
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST_FREQ
|
||||
int "SPI 1 Clock Freq in Hz"
|
||||
default 1000000
|
||||
depends on NUCLEO_F746ZG_SPI1_TEST
|
||||
---help---
|
||||
Sets SPI 1 Clock Freq
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST_BITS
|
||||
int "SPI 1 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F746ZG_SPI1_TEST
|
||||
---help---
|
||||
Sets SPI 1 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 1 Clock Mode"
|
||||
default NUCLEO_F746ZG_SPI1_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 1 clock mode
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F746ZG_SPI1_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 1 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F746ZG_SPI1_TEST
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST
|
||||
bool "Test SPI bus 2"
|
||||
default n
|
||||
depends on NUCLEO_F746ZG_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 2
|
||||
|
||||
if NUCLEO_F746ZG_SPI2_TEST
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST_FREQ
|
||||
int "SPI 2 Clock Freq in Hz"
|
||||
default 12000000
|
||||
depends on NUCLEO_F746ZG_SPI2_TEST
|
||||
---help---
|
||||
Sets SPI 2 Clock Freq
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST_BITS
|
||||
int "SPI 2 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F746ZG_SPI2_TEST
|
||||
---help---
|
||||
Sets SPI 2 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 2 Clock Mode"
|
||||
default NUCLEO_F746ZG_SPI2_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 2 clock mode
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F746ZG_SPI2_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 2 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F746ZG_SPI2_TEST
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST
|
||||
bool "Test SPI bus 3"
|
||||
default n
|
||||
depends on NUCLEO_F746ZG_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 3
|
||||
|
||||
if NUCLEO_F746ZG_SPI3_TEST
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST_FREQ
|
||||
int "SPI 3 Clock Freq in Hz"
|
||||
default 40000000
|
||||
depends on NUCLEO_F746ZG_SPI3_TEST
|
||||
---help---
|
||||
Sets SPI 3 Clock Freq
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST_BITS
|
||||
int "SPI 3 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F746ZG_SPI3_TEST
|
||||
---help---
|
||||
Sets SPI 3 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 3 Clock Mode"
|
||||
default NUCLEO_F746ZG_SPI3_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 3 clock mode
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F746ZG_SPI3_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 3 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F746ZG_SPI3_TEST
|
||||
endif # NUCLEO_F746ZG_SPI_TEST
|
||||
|
||||
choice
|
||||
prompt "CAN1 pins selection"
|
||||
default NUCLEO_F746ZG_CAN1_MAP_PD0PD1
|
||||
|
|
|
|||
|
|
@ -50,8 +50,12 @@
|
|||
# include "stm32_romfs.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI_TEST
|
||||
# include "stm32_spitest.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYSTEMTICK_HOOK
|
||||
#include <semaphore.h>
|
||||
# include <semaphore.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -149,7 +153,7 @@ int stm32_bringup(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST)
|
||||
#ifdef CONFIG_STM32F7_SPI_TEST
|
||||
/* Create SPI interfaces */
|
||||
|
||||
ret = stm32_spidev_bus_test();
|
||||
|
|
|
|||
|
|
@ -47,48 +47,6 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
|
@ -171,18 +129,6 @@ static const uint32_t g_spi3gpio[] =
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST)
|
||||
# if defined(CONFIG_STM32F7_SPI1)
|
||||
struct spi_dev_s *spi1;
|
||||
# endif
|
||||
# if defined(CONFIG_STM32F7_SPI2)
|
||||
struct spi_dev_s *spi2;
|
||||
# endif
|
||||
# if defined(CONFIG_STM32F7_SPI3)
|
||||
struct spi_dev_s *spi3;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -430,69 +376,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
|||
#endif
|
||||
|
||||
#endif /* CONFIG_SPI_CMDDATA */
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST)
|
||||
int stm32_spidev_bus_test(void)
|
||||
{
|
||||
/* Configure and test SPI- */
|
||||
|
||||
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE;
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST)
|
||||
spi1 = stm32_spibus_initialize(1);
|
||||
|
||||
if (!spi1)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI1 to NUCLEO_F746ZG_SPI1_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_FREQ);
|
||||
SPI_SETBITS(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_BITS);
|
||||
SPI_SETMODE(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE);
|
||||
SPI_EXCHANGE(spi1, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST)
|
||||
spi2 = stm32_spibus_initialize(2);
|
||||
|
||||
if (!spi2)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI2 to NUCLEO_F746ZG_SPI2_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_FREQ);
|
||||
SPI_SETBITS(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_BITS);
|
||||
SPI_SETMODE(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE);
|
||||
SPI_EXCHANGE(spi2, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST)
|
||||
spi3 = stm32_spibus_initialize(3);
|
||||
|
||||
if (!spi3)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI3 to NUCLEO_F746ZG_SPI3_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_FREQ);
|
||||
SPI_SETBITS(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_BITS);
|
||||
SPI_SETMODE(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE);
|
||||
SPI_EXCHANGE(spi3, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif /* NUCLEO_F746ZG_SPI_TEST */
|
||||
#endif /* defined(CONFIG_SPI) */
|
||||
|
|
|
|||
|
|
@ -80,160 +80,6 @@ config NUCLEO_F767ZI_CONSOLE_NONE
|
|||
|
||||
endchoice # "Select Console wiring"
|
||||
|
||||
config NUCLEO_F767ZI_SPI_TEST
|
||||
bool "Enable SPI test"
|
||||
default n
|
||||
---help---
|
||||
Enable Spi test - initialize and configure SPI to send
|
||||
NUCLEO_F767ZI_SPI_TEST_MESSAGE text. The text is sent on the
|
||||
selected SPI Buses with the configured parameters.
|
||||
Note the CS lines will not be asserted.
|
||||
|
||||
if NUCLEO_F767ZI_SPI_TEST
|
||||
|
||||
config NUCLEO_F767ZI_SPI_TEST_MESSAGE
|
||||
string "Text to Send on SPI Bus(es)"
|
||||
default "Hello World"
|
||||
depends on NUCLEO_F767ZI_SPI_TEST
|
||||
---help---
|
||||
Text to sent on SPI bus(es)
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST
|
||||
bool "Test SPI bus 1"
|
||||
default n
|
||||
depends on NUCLEO_F767ZI_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 1
|
||||
|
||||
if NUCLEO_F767ZI_SPI1_TEST
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST_FREQ
|
||||
int "SPI 1 Clock Freq in Hz"
|
||||
default 1000000
|
||||
depends on NUCLEO_F767ZI_SPI1_TEST
|
||||
---help---
|
||||
Sets SPI 1 Clock Freq
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST_BITS
|
||||
int "SPI 1 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F767ZI_SPI1_TEST
|
||||
---help---
|
||||
Sets SPI 1 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 1 Clock Mode"
|
||||
default NUCLEO_F767ZI_SPI1_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 1 clock mode
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F767ZI_SPI1_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 1 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F767ZI_SPI1_TEST
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST
|
||||
bool "Test SPI bus 2"
|
||||
default n
|
||||
depends on NUCLEO_F767ZI_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 2
|
||||
|
||||
if NUCLEO_F767ZI_SPI2_TEST
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST_FREQ
|
||||
int "SPI 2 Clock Freq in Hz"
|
||||
default 12000000
|
||||
depends on NUCLEO_F767ZI_SPI2_TEST
|
||||
---help---
|
||||
Sets SPI 2 Clock Freq
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST_BITS
|
||||
int "SPI 2 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F767ZI_SPI2_TEST
|
||||
---help---
|
||||
Sets SPI 2 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 2 Clock Mode"
|
||||
default NUCLEO_F767ZI_SPI2_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 2 clock mode
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F767ZI_SPI2_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 2 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F767ZI_SPI2_TEST
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST
|
||||
bool "Test SPI bus 3"
|
||||
default n
|
||||
depends on NUCLEO_F767ZI_SPI_TEST
|
||||
---help---
|
||||
Enable Spi test - on SPI BUS 3
|
||||
|
||||
if NUCLEO_F767ZI_SPI3_TEST
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST_FREQ
|
||||
int "SPI 3 Clock Freq in Hz"
|
||||
default 40000000
|
||||
depends on NUCLEO_F767ZI_SPI3_TEST
|
||||
---help---
|
||||
Sets SPI 3 Clock Freq
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST_BITS
|
||||
int "SPI 3 number of bits"
|
||||
default 8
|
||||
depends on NUCLEO_F767ZI_SPI3_TEST
|
||||
---help---
|
||||
Sets SPI 3 bit length
|
||||
|
||||
choice
|
||||
prompt "SPI BUS 3 Clock Mode"
|
||||
default NUCLEO_F767ZI_SPI3_TEST_MODE3
|
||||
---help---
|
||||
Sets SPI 3 clock mode
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST_MODE0
|
||||
bool "CPOL=0 CPHA=0"
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST_MODE1
|
||||
bool "CPOL=0 CPHA=1"
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST_MODE2
|
||||
bool "CPOL=1 CPHA=0"
|
||||
|
||||
config NUCLEO_F767ZI_SPI3_TEST_MODE3
|
||||
bool "CPOL=1 CPHA=1"
|
||||
|
||||
endchoice # "SPI BUS 3 Clock Mode"
|
||||
|
||||
endif # NUCLEO_F767ZI_SPI3_TEST
|
||||
endif # NUCLEO_F767ZI_SPI_TEST
|
||||
|
||||
choice
|
||||
prompt "CAN1 pins selection"
|
||||
default NUCLEO_F767ZI_CAN1_MAP_PD0PD1
|
||||
|
|
|
|||
|
|
@ -50,8 +50,12 @@
|
|||
# include "stm32_romfs.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI_TEST
|
||||
# include "stm32_spitest.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYSTEMTICK_HOOK
|
||||
#include <semaphore.h>
|
||||
# include <semaphore.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -149,7 +153,7 @@ int stm32_bringup(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
|
||||
#ifdef CONFIG_STM32F7_SPI_TEST
|
||||
/* Create SPI interfaces */
|
||||
|
||||
ret = stm32_spidev_bus_test();
|
||||
|
|
|
|||
|
|
@ -47,48 +47,6 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST)
|
||||
# if defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE0)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE0
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE1)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE1
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE2)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE2
|
||||
# elif defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE3)
|
||||
# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE3
|
||||
# else
|
||||
# error "No CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODEx defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
|
@ -171,18 +129,6 @@ static const uint32_t g_spi3gpio[] =
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI_TEST)
|
||||
# if defined(CONFIG_STM32F7_SPI1)
|
||||
struct spi_dev_s *spi1;
|
||||
# endif
|
||||
# if defined(CONFIG_STM32F7_SPI2)
|
||||
struct spi_dev_s *spi2;
|
||||
# endif
|
||||
# if defined(CONFIG_STM32F7_SPI3)
|
||||
struct spi_dev_s *spi3;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -430,69 +376,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
|||
#endif
|
||||
|
||||
#endif /* CONFIG_SPI_CMDDATA */
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI_TEST)
|
||||
int stm32_spidev_bus_test(void)
|
||||
{
|
||||
/* Configure and test SPI- */
|
||||
|
||||
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE;
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST)
|
||||
spi1 = stm32_spibus_initialize(1);
|
||||
|
||||
if (!spi1)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI1 to NUCLEO_F767ZI_SPI1_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F767ZI_SPI1_TEST_FREQ);
|
||||
SPI_SETBITS(spi1, CONFIG_NUCLEO_F767ZI_SPI1_TEST_BITS);
|
||||
SPI_SETMODE(spi1, CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE);
|
||||
SPI_EXCHANGE(spi1, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST)
|
||||
spi2 = stm32_spibus_initialize(2);
|
||||
|
||||
if (!spi2)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI2 to NUCLEO_F767ZI_SPI2_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F767ZI_SPI2_TEST_FREQ);
|
||||
SPI_SETBITS(spi2, CONFIG_NUCLEO_F767ZI_SPI2_TEST_BITS);
|
||||
SPI_SETMODE(spi2, CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE);
|
||||
SPI_EXCHANGE(spi2, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST)
|
||||
spi3 = stm32_spibus_initialize(3);
|
||||
|
||||
if (!spi3)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default SPI3 to NUCLEO_F767ZI_SPI3_FREQ and mode */
|
||||
|
||||
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F767ZI_SPI3_TEST_FREQ);
|
||||
SPI_SETBITS(spi3, CONFIG_NUCLEO_F767ZI_SPI3_TEST_BITS);
|
||||
SPI_SETMODE(spi3, CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE);
|
||||
SPI_EXCHANGE(spi3, tx, NULL,
|
||||
nitems(CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE));
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif /* NUCLEO_F767ZI_SPI_TEST */
|
||||
#endif /* defined(CONFIG_SPI) */
|
||||
|
|
|
|||
Loading…
Reference in a new issue