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stm32/stm32h7: fix the configuration of PWM outputs when subsequent channels are not enabled (eg. CH1 and CH2 disabled, CH3 enabled)

Browse source 
Resolves issue #2446
This commit is contained in:
raiden00pl 2020-11-30 15:53:56 +01:00 committed by Xiang Xiao
parent 2937ebde96
commit 756cb41a6c
2 changed files with 26 additions and 16 deletions
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21
arch/arm/src/stm32/stm32_pwm.c
View file

@ -448,7 +448,7 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev,
uint8_t channel, uint32_t mode);
static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv);
static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t channel);
FAR struct stm32_pwmchan_s *chan);
static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
uint16_t outputs, bool state);
static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev);
@ -2801,10 +2801,15 @@ errout:
****************************************************************************/
static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t channel)
FAR struct stm32_pwmchan_s *chan)
{
uint32_t cr2 = 0;
uint32_t ccer = 0;
uint8_t channel = 0;
/* Get channel */
channel = chan->channel;
/* Get current registers state */
@ -2817,7 +2822,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
/* Configure output polarity (all PWM timers) */
if (priv->channels[channel - 1].out1.pol == STM32_POL_NEG)
if (chan->out1.pol == STM32_POL_NEG)
{
ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4));
}
@ -2832,7 +2837,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
{
/* Configure output IDLE State */
if (priv->channels[channel - 1].out1.idle == STM32_IDLE_ACTIVE)
if (chan->out1.idle == STM32_IDLE_ACTIVE)
{
cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2));
}
@ -2844,7 +2849,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
#ifdef HAVE_PWM_COMPLEMENTARY
/* Configure complementary output IDLE state */
if (priv->channels[channel - 1].out2.idle == STM32_IDLE_ACTIVE)
if (chan->out2.idle == STM32_IDLE_ACTIVE)
{
cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2));
}
@ -2855,7 +2860,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
/* Configure complementary output polarity */
if (priv->channels[channel - 1].out2.pol == STM32_POL_NEG)
if (chan->out2.pol == STM32_POL_NEG)
{
ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4));
}
@ -3298,7 +3303,7 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev)
/* PWM outputs configuration */
pwm_output_configure(priv, priv->channels[j].channel);
pwm_output_configure(priv, &priv->channels[j]);
}
}
@ -3545,7 +3550,7 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev)
/* PWM outputs configuration */
ret = pwm_output_configure(priv, priv->channels[j].channel);
ret = pwm_output_configure(priv, &priv->channels[j]);
if (ret < 0)
{
goto errout;

21
arch/arm/src/stm32h7/stm32_pwm.c
View file

@ -335,7 +335,7 @@ static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev,
uint8_t channel, uint32_t mode);
static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv);
static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t channel);
FAR struct stm32_pwmchan_s *chan);
static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
uint16_t outputs, bool state);
static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev);
@ -2519,10 +2519,15 @@ errout:
****************************************************************************/
static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t channel)
FAR struct stm32_pwmchan_s *chan)
{
uint32_t cr2 = 0;
uint32_t ccer = 0;
uint8_t channel = 0;
/* Get channel */
channel = chan->channel;
/* Get current registers state */
@ -2535,7 +2540,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
/* Configure output polarity (all PWM timers) */
if (priv->channels[channel - 1].out1.pol == STM32_POL_NEG)
if (chan->out1.pol == STM32_POL_NEG)
{
ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4));
}
@ -2550,7 +2555,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
{
/* Configure output IDLE State */
if (priv->channels[channel - 1].out1.idle == STM32_IDLE_ACTIVE)
if (chan->out1.idle == STM32_IDLE_ACTIVE)
{
cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2));
}
@ -2562,7 +2567,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
#ifdef HAVE_PWM_COMPLEMENTARY
/* Configure complementary output IDLE state */
if (priv->channels[channel - 1].out2.idle == STM32_IDLE_ACTIVE)
if (chan->out2.idle == STM32_IDLE_ACTIVE)
{
cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2));
}
@ -2573,7 +2578,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
/* Configure complementary output polarity */
if (priv->channels[channel - 1].out2.pol == STM32_POL_NEG)
if (chan->out2.pol == STM32_POL_NEG)
{
ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4));
}
@ -3018,7 +3023,7 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev)
/* PWM outputs configuration */
pwm_output_configure(priv, priv->channels[j].channel);
pwm_output_configure(priv, &priv->channels[j]);
}
}
@ -3265,7 +3270,7 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev)
/* PWM outputs configuration */
ret = pwm_output_configure(priv, priv->channels[j].channel);
ret = pwm_output_configure(priv, &priv->channels[j]);
if (ret < 0)
{
goto errout;