More Cortex-M0/NUC120 progress

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5669 42af7a65-404d-4744-a932-0658087f49c3

configs/nutiny-nuc120/README.txt

@@ -100,8 +100,8 @@ is provided as an LQFP48 package and, for this case, the UART1 RX signal
 (RXD1) is on PB.4, pin 8, and the TX signal (TXD1) is on PB.5, pin 9.
 These pins are available on the NuTiny-SDC-NUC120 JP5.
 
-  NOTE: The TX vs RX terminology is confusing.  On my RS-232 driver board,
-  I need to connect the NUC120 TXD0 pin to the driver boards RXD pin.  How
+  NOTE: The TX vs RX labeling may be confusing.  On one RS-232 driver board,
+  I had to connect the NUC120 TXD0 pin to the driver boards RXD pin.  How
   confusing!
 
 UART0 is an alternative that can be selected by modifying the default

configs/nutiny-nuc120/include/board.h

@@ -53,8 +53,8 @@
 /* Clocking *************************************************************************/
 /* Crystal frequencies */
 
-#define BOARD_HIGHSPEED_XTAL_FREQUENCY 12000000
-#define BOARD_LOWSPEED_XTAL_FREQUENCY  32768
+#define BOARD_XTALHI_FREQUENCY 12000000
+#define BOARD_XTALLO_FREQUENCY 32768
 
 /* PLL: The PLL must be 48MHz x N times when using USB
  *
@@ -72,7 +72,7 @@
  *      = 48MHz
  */
 
-#define BOARD_PLL_FIN    BOARD_HIGHSPEED_XTAL_FREQUENCY
+#define BOARD_PLL_FIN    BOARD_XTALHI_FREQUENCY
 #define BOARD_PLL_FB_DV  46
 #define BOARD_PLL_NF     (BOARD_PLL_FB_DV+2)
 #define BOARD_PLL_IN_DV  1

configs/nutiny-nuc120/ostest/defconfig

@@ -163,6 +163,15 @@ CONFIG_NUC_UART1=y
 # CONFIG_NUC_ADC is not set
 # CONFIG_NUC_PS2 is not set
 # CONFIG_NUC_I2S is not set
+CONFIG_NUC_INTHI=y
+CONFIG_NUC_SYSTICK_XTALHI=y
+# CONFIG_NUC_SYSTICK_XTALLO is not set
+# CONFIG_NUC_SYSTICK_XTALHId2 is not set
+# CONFIG_NUC_SYSTICK_HCLKd2 is not set
+# CONFIG_NUC_SYSTICK_INTHId2 is not set
+# CONFIG_NUC_UARTCLK_XTALHI is not set
+# CONFIG_NUC_UARTCLK_PLL is not set
+CONFIG_NUC_UARTCLK_INTHI=y
 
 #
 # External Memory Configuration