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Initial STM32H5 Timers Commit

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Used the STM32H7 as a reference.

Removed APB enabling from stm32h5xx_rcc.c. This is done in timer initialization, like STM32H7.

Also removed LPTIM. Will add later.

tim_lowerhalf: Timers 9, 10, and 11 removed. Timers 15,16, and 17 added.

Removed low-power timers from Kconfig. Not implemented yet.

Style Updates

Added stm32_tim_enable and stm32_tim_disable to Timer operations.
This commit is contained in:
Kyle Wilson 2025-01-03 10:35:43 -06:00 committed by Mateusz Szafoni
parent e5e9032ea0
commit 9783c88425
6 changed files with 5477 additions and 86 deletions
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3111
arch/arm/src/stm32h5/Kconfig
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6
arch/arm/src/stm32h5/Make.defs
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@ -43,7 +43,7 @@ CHIP_CSRCS += stm32_idle.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32h5_tim_lowerhalf.c
CHIP_CSRCS += stm32_tim_lowerhalf.c
endif
ifeq ($(CONFIG_STM32H5_I2C),y)
@ -66,6 +66,10 @@ ifeq ($(CONFIG_STM32H5_QSPI1),y)
CHIP_CSRCS += stm32_qspi.c
endif
ifeq ($(CONFIG_STM32H5_TIM),y)
CHIP_CSRCS += stm32_tim.c
endif
# Required chip type specific files
ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)

1553
arch/arm/src/stm32h5/stm32_tim.c Normal file
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223
arch/arm/src/stm32h5/stm32_tim.h Normal file
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@ -0,0 +1,223 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_tim.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32H5_STM32_TIM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/stm32_tim.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Helpers ******************************************************************/
#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d))
#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d))
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c))
#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* TIM Device Structure */
struct stm32_tim_dev_s
{
struct stm32_tim_ops_s *ops;
};
/* TIM Modes of Operation */
typedef enum
{
STM32_TIM_MODE_UNUSED = -1,
/* One of the following */
STM32_TIM_MODE_MASK = 0x0310,
STM32_TIM_MODE_DISABLED = 0x0000,
STM32_TIM_MODE_UP = 0x0100,
STM32_TIM_MODE_DOWN = 0x0110,
STM32_TIM_MODE_UPDOWN = 0x0200,
STM32_TIM_MODE_PULSE = 0x0300,
/* One of the following */
STM32_TIM_MODE_CK_INT = 0x0000,
#if 0
STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
STM32_TIM_MODE_CK_EXT = 0x0800,
STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00,
/* Clock sources, OR'ed with CK_EXT */
STM32_TIM_MODE_CK_CHINVALID = 0x0000,
STM32_TIM_MODE_CK_CH1 = 0x0001,
STM32_TIM_MODE_CK_CH2 = 0x0002,
STM32_TIM_MODE_CK_CH3 = 0x0003,
STM32_TIM_MODE_CK_CH4 = 0x0004
#endif
/* Todo: external trigger block */
} stm32_tim_mode_t;
/* TIM Channel Modes */
typedef enum
{
STM32_TIM_CH_DISABLED = 0x00,
/* Common configuration */
STM32_TIM_CH_POLARITY_POS = 0x00,
STM32_TIM_CH_POLARITY_NEG = 0x01,
/* MODES: */
STM32_TIM_CH_MODE_MASK = 0x0e,
/* Output Compare Modes */
/* Enable standard PWM mode, active high when counter < compare */
STM32_TIM_CH_OUTPWM = 0x04,
/* Toggle TIM_CHx output on UEV */
STM32_TIM_CH_OUTTOGGLE = 0x08,
#if 0
STM32_TIM_CH_OUTCOMPARE = 0x06,
/* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */
STM32_TIM_CH_INCAPTURE = 0x10,
STM32_TIM_CH_INPWM = 0x20
STM32_TIM_CH_DRIVE_OC - open collector mode
#endif
} stm32_tim_channel_t;
/* TIM Operations */
struct stm32_tim_ops_s
{
/* Basic Timers */
void (*enable)(struct stm32_tim_dev_s *dev);
void (*disable)(struct stm32_tim_dev_s *dev);
int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq);
void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period);
uint32_t (*getcounter)(struct stm32_tim_dev_s *dev);
void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count);
/* General and Advanced Timers Adds */
int (*getwidth)(struct stm32_tim_dev_s *dev);
int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel,
stm32_tim_channel_t mode);
int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel);
/* Timer interrupts */
int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg,
int source);
void (*enableint)(struct stm32_tim_dev_s *dev, int source);
void (*disableint)(struct stm32_tim_dev_s *dev, int source);
void (*ackint)(struct stm32_tim_dev_s *dev, int source);
int (*checkint)(struct stm32_tim_dev_s *dev, int source);
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Power-up timer and get its structure */
struct stm32_tim_dev_s *stm32_tim_init(int timer);
/* Power-down timer, mark it as unused */
int stm32_tim_deinit(struct stm32_tim_dev_s *dev);
/****************************************************************************
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the
* form /dev/timer0
* timer - the timer number.
*
* Returned Values:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_TIMER
int stm32_timer_initialize(const char *devpath, int timer);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_TIM_H */

586
arch/arm/src/stm32h5/stm32_tim_lowerhalf.c Normal file
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@ -0,0 +1,586 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_tim_lowerhalf.c
*
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-FileCopyrightText: 2023 Max Kriegleder. All rights reserved.
* SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved.
* SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved.
* SPDX-FileContributor: Wail Khemir <khemirwail@gmail.com>
* SPDX-FileContributor: Paul Alexander Patience <paul-a.patience@polymtl.ca>
* SPDX-FileContributor: Max Kriegleder <max.kriegleder@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/timers/timer.h>
#include <arch/board/board.h>
#include "stm32_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \
defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \
defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \
defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \
defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \
defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \
defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_TIM1_RES 16
#define STM32_TIM2_RES 32
#define STM32_TIM3_RES 16
#define STM32_TIM4_RES 16
#define STM32_TIM5_RES 32
#define STM32_TIM6_RES 16
#define STM32_TIM7_RES 16
#define STM32_TIM8_RES 16
#define STM32_TIM12_RES 16
#define STM32_TIM13_RES 16
#define STM32_TIM14_RES 16
#define STM32_TIM15_RES 16
#define STM32_TIM16_RES 16
#define STM32_TIM17_RES 16
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* timer_lowerhalf_s structure.
*/
struct stm32_lowerhalf_s
{
const struct timer_ops_s *ops; /* Lower half operations */
struct stm32_tim_dev_s *tim; /* stm32 timer driver */
tccb_t callback; /* Current user interrupt callback */
void *arg; /* Argument passed to upper half callback */
bool started; /* True: Timer has been started */
const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int stm32_timer_handler(int irq, void * context, void * arg);
/* "Lower half" driver methods **********************************************/
static int stm32_start(struct timer_lowerhalf_s *lower);
static int stm32_stop(struct timer_lowerhalf_s *lower);
static int stm32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout);
static void stm32_setcallback(struct timer_lowerhalf_s *lower,
tccb_t callback, void *arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct timer_ops_s g_timer_ops =
{
.start = stm32_start,
.stop = stm32_stop,
.getstatus = NULL,
.settimeout = stm32_settimeout,
.setcallback = stm32_setcallback,
.ioctl = NULL,
};
#ifdef CONFIG_STM32H5_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM1_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM2_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM3_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM4_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM5_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM6_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM7_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM8_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM12
static struct stm32_lowerhalf_s g_tim12_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM12_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM13
static struct stm32_lowerhalf_s g_tim13_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM13_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM14
static struct stm32_lowerhalf_s g_tim14_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM14_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM15_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM16_RES,
};
#endif
#ifdef CONFIG_STM32H5_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM17_RES,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_timer_handler
*
* Description:
* timer interrupt handler
*
* Input Parameters:
*
* Returned Value:
*
****************************************************************************/
static int stm32_timer_handler(int irq, void * context, void * arg)
{
struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg;
uint32_t next_interval_us = 0;
STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE);
if (lower->callback(&next_interval_us, lower->arg))
{
if (next_interval_us > 0)
{
STM32_TIM_SETPERIOD(lower->tim, next_interval_us);
}
}
else
{
stm32_stop((struct timer_lowerhalf_s *)lower);
}
return OK;
}
/****************************************************************************
* Name: stm32_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_start(struct timer_lowerhalf_s *lower)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
if (!priv->started)
{
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP);
if (priv->callback != NULL)
{
STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0);
STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE);
}
priv->started = true;
return OK;
}
/* Return EBUSY to indicate that the timer was already running */
return -EBUSY;
}
/****************************************************************************
* Name: stm32_stop
*
* Description:
* Stop the timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_stop(struct timer_lowerhalf_s *lower)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
if (priv->started)
{
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED);
STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE);
STM32_TIM_SETISR(priv->tim, NULL, NULL, 0);
priv->started = false;
return OK;
}
/* Return ENODEV to indicate that the timer was not running */
return -ENODEV;
}
/****************************************************************************
* Name: stm32_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in microseconds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
uint64_t maxtimeout;
if (priv->started)
{
return -EPERM;
}
maxtimeout = (1 << priv->resolution) - 1;
if (timeout > maxtimeout)
{
uint64_t freq = (maxtimeout * 1000000) / timeout;
STM32_TIM_SETCLOCK(priv->tim, freq);
STM32_TIM_SETPERIOD(priv->tim, maxtimeout);
}
else
{
STM32_TIM_SETCLOCK(priv->tim, 1000000);
STM32_TIM_SETPERIOD(priv->tim, timeout);
}
return OK;
}
/****************************************************************************
* Name: stm32_setcallback
*
* Description:
* Call this user provided timeout callback.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* callback - The new timer expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
* arg - Argument that will be provided in the callback
*
* Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
****************************************************************************/
static void stm32_setcallback(struct timer_lowerhalf_s *lower,
tccb_t callback, void *arg)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
irqstate_t flags = enter_critical_section();
/* Save the new callback */
priv->callback = callback;
priv->arg = arg;
if (callback != NULL && priv->started)
{
STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0);
STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE);
}
else
{
STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE);
STM32_TIM_SETISR(priv->tim, NULL, NULL, 0);
}
leave_critical_section(flags);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the
* form /dev/timer0
* timer - the timer's number.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int stm32_timer_initialize(const char *devpath, int timer)
{
struct stm32_lowerhalf_s *lower;
switch (timer)
{
#ifdef CONFIG_STM32H5_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
case 12:
lower = &g_tim12_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
case 13:
lower = &g_tim13_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
case 14:
lower = &g_tim14_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;
#endif
default:
return -ENODEV;
}
/* Initialize the elements of lower half state structure */
lower->started = false;
lower->callback = NULL;
lower->tim = stm32_tim_init(timer);
if (lower->tim == NULL)
{
return -EINVAL;
}
/* Register the timer driver as /dev/timerX. The returned value from
* timer_register is a handle that could be used with timer_unregister().
* REVISIT: The returned handle is discard here.
*/
void *drvr = timer_register(devpath,
(struct timer_lowerhalf_s *)lower);
if (drvr == NULL)
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
return OK;
}
#endif /* CONFIG_TIMER */

84
arch/arm/src/stm32h5/stm32h5xx_rcc.c
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@ -355,60 +355,6 @@ static inline void rcc_enableapb1l(void)
regval = getreg32(STM32_RCC_APB1LENR);
#ifdef CONFIG_STM32H5_TIM2
/* Bit 0: TIM2 clock enable */
regval |= RCC_APB1LENR_TIM2EN;
#endif
#ifdef CONFIG_STM32H5_TIM3
/* Bit 1: TIM3 clock enable */
regval |= RCC_APB1LENR_TIM3EN;
#endif
#ifdef CONFIG_STM32H5_TIM4
/* Bit 2: TIM4 clock enable */
regval |= RCC_APB1LENR_TIM4EN;
#endif
#ifdef CONFIG_STM32H5_TIM5
/* Bit 3: TIM5 clock enable */
regval |= RCC_APB1LENR_TIM5EN;
#endif
#ifdef CONFIG_STM32H5_TIM6
/* Bit 4: TIM6 clock enable */
regval |= RCC_APB1LENR_TIM6EN;
#endif
#ifdef CONFIG_STM32H5_TIM7
/* Bit 5: TIM7 clock enable */
regval |= RCC_APB1LENR_TIM7EN;
#endif
#ifdef CONFIG_STM32H5_TIM12
/* Bit 5: TIM12 clock enable */
regval |= RCC_APB1LENR_TIM12EN;
#endif
#ifdef CONFIG_STM32H5_TIM13
/* Bit 5: TIM13 clock enable */
regval |= RCC_APB1LENR_TIM13EN;
#endif
#ifdef CONFIG_STM32H5_TIM14
/* Bit 5: TIM14 clock enable */
regval |= RCC_APB1LENR_TIM14EN;
#endif
#ifdef CONFIG_STM32H5_SPI2
/* Bit 14: SPI2 clock enable */
@ -588,48 +534,18 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32H5_TIM1
/* TIM1 clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32H5_SPI1
/* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32H5_TIM8
/* TIM8 clock enable */
regval |= RCC_APB2ENR_TIM8EN;
#endif
#ifdef CONFIG_STM32H5_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32H5_TIM15
/* TIM15 clock enable */
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32H5_TIM16
/* TIM16 clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32H5_TIM17
/* TIM17 clock enable */
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32H5_SPI4
/* SPI4 clock enable */