mpfs_pmpcfg: Move PMPCFG registers to common location
This commit is contained in:
Ville Juven
Xiang Xiao
parent
baea0012e7
commit
986a79b231
7 changed files with 105 additions and 55 deletions
98
arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h
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98
arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h
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/****************************************************************************
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* arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_MPUCFG_H
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#define __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_MPUCFG_H
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/* FIC1 (FPGA) PMP configurations - for fabric memory transfers */
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#define MPFS_PMPCFG_FIC1_0 (MPFS_MPUCFG_BASE + 0x100)
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#define MPFS_PMPCFG_FIC1_1 (MPFS_MPUCFG_BASE + 0x108)
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#define MPFS_PMPCFG_FIC1_2 (MPFS_MPUCFG_BASE + 0x110)
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#define MPFS_PMPCFG_FIC1_3 (MPFS_MPUCFG_BASE + 0x118)
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#define MPFS_PMPCFG_FIC1_4 (MPFS_MPUCFG_BASE + 0x120)
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#define MPFS_PMPCFG_FIC1_5 (MPFS_MPUCFG_BASE + 0x128)
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#define MPFS_PMPCFG_FIC1_6 (MPFS_MPUCFG_BASE + 0x130)
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#define MPFS_PMPCFG_FIC1_7 (MPFS_MPUCFG_BASE + 0x138)
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#define MPFS_PMPCFG_FIC1_8 (MPFS_MPUCFG_BASE + 0x140)
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#define MPFS_PMPCFG_FIC1_9 (MPFS_MPUCFG_BASE + 0x148)
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#define MPFS_PMPCFG_FIC1_10 (MPFS_MPUCFG_BASE + 0x150)
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#define MPFS_PMPCFG_FIC1_11 (MPFS_MPUCFG_BASE + 0x158)
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#define MPFS_PMPCFG_FIC1_12 (MPFS_MPUCFG_BASE + 0x160)
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#define MPFS_PMPCFG_FIC1_13 (MPFS_MPUCFG_BASE + 0x168)
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#define MPFS_PMPCFG_FIC1_14 (MPFS_MPUCFG_BASE + 0x170)
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#define MPFS_PMPCFG_FIC1_15 (MPFS_MPUCFG_BASE + 0x178)
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/* Crpyto PMP configurations - for DMA transfers */
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#define MPFS_PMPCFG_CRYPTO_0 (MPFS_MPUCFG_BASE + 0x300)
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#define MPFS_PMPCFG_CRYPTO_1 (MPFS_MPUCFG_BASE + 0x308)
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#define MPFS_PMPCFG_CRYPTO_2 (MPFS_MPUCFG_BASE + 0x310)
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#define MPFS_PMPCFG_CRYPTO_3 (MPFS_MPUCFG_BASE + 0x318)
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/* Ethernet PMP configurations - for DMA transfers */
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#define MPFS_PMPCFG_ETH0_0 (MPFS_MPUCFG_BASE + 0x400)
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#define MPFS_PMPCFG_ETH0_1 (MPFS_MPUCFG_BASE + 0x408)
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#define MPFS_PMPCFG_ETH0_2 (MPFS_MPUCFG_BASE + 0x410)
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#define MPFS_PMPCFG_ETH0_3 (MPFS_MPUCFG_BASE + 0x418)
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#define MPFS_PMPCFG_ETH1_0 (MPFS_MPUCFG_BASE + 0x500)
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#define MPFS_PMPCFG_ETH1_1 (MPFS_MPUCFG_BASE + 0x508)
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#define MPFS_PMPCFG_ETH1_2 (MPFS_MPUCFG_BASE + 0x510)
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#define MPFS_PMPCFG_ETH1_3 (MPFS_MPUCFG_BASE + 0x518)
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/* USB PMP configurations - for DMA transfers */
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#define MPFS_PMPCFG_USB_0 (MPFS_MPUCFG_BASE + 0x600)
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#define MPFS_PMPCFG_USB_1 (MPFS_MPUCFG_BASE + 0x608)
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#define MPFS_PMPCFG_USB_2 (MPFS_MPUCFG_BASE + 0x610)
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#define MPFS_PMPCFG_USB_3 (MPFS_MPUCFG_BASE + 0x618)
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/* MMC PMP configurations - for DMA transfers */
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#define MPFS_PMPCFG_MMC_0 (MPFS_MPUCFG_BASE + 0x700)
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#define MPFS_PMPCFG_MMC_1 (MPFS_MPUCFG_BASE + 0x708)
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#define MPFS_PMPCFG_MMC_2 (MPFS_MPUCFG_BASE + 0x710)
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#define MPFS_PMPCFG_MMC_3 (MPFS_MPUCFG_BASE + 0x718)
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/* DDR segments - set up by mpfs_ddr.c */
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#define MPFS_MPUCFG_SEG0_REG0 (MPFS_MPUCFG_BASE + 0xd00)
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#define MPFS_MPUCFG_SEG0_REG1 (MPFS_MPUCFG_BASE + 0xd08)
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#define MPFS_MPUCFG_SEG0_REG2 (MPFS_MPUCFG_BASE + 0xd10)
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#define MPFS_MPUCFG_SEG0_REG3 (MPFS_MPUCFG_BASE + 0xd18)
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#define MPFS_MPUCFG_SEG0_REG4 (MPFS_MPUCFG_BASE + 0xd20)
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#define MPFS_MPUCFG_SEG0_REG5 (MPFS_MPUCFG_BASE + 0xd28)
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#define MPFS_MPUCFG_SEG0_REG6 (MPFS_MPUCFG_BASE + 0xd30)
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#define MPFS_MPUCFG_SEG1_REG0 (MPFS_MPUCFG_BASE + 0xe00)
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#define MPFS_MPUCFG_SEG1_REG1 (MPFS_MPUCFG_BASE + 0xe08)
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#define MPFS_MPUCFG_SEG1_REG2 (MPFS_MPUCFG_BASE + 0xe10)
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#define MPFS_MPUCFG_SEG1_REG3 (MPFS_MPUCFG_BASE + 0xe18)
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#define MPFS_MPUCFG_SEG1_REG4 (MPFS_MPUCFG_BASE + 0xe20)
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#define MPFS_MPUCFG_SEG1_REG5 (MPFS_MPUCFG_BASE + 0xe28)
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#define MPFS_MPUCFG_SEG1_REG6 (MPFS_MPUCFG_BASE + 0xe30)
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/* Size of the register area, which is 4K */
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#define MPFS_MPUCFG_SIZE (0x1000)
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#define MPFS_MPUCFG_END (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SIZE)
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#endif /* __NUTTX_ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_MPUCFG_H */
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@ -31,38 +31,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define MPFS_MPUCFG_SEG0_REG0_OFFSET 0xd00
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#define MPFS_MPUCFG_SEG0_REG1_OFFSET 0xd08
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#define MPFS_MPUCFG_SEG0_REG2_OFFSET 0xd10
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#define MPFS_MPUCFG_SEG0_REG3_OFFSET 0xd18
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#define MPFS_MPUCFG_SEG0_REG4_OFFSET 0xd20
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#define MPFS_MPUCFG_SEG0_REG5_OFFSET 0xd28
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#define MPFS_MPUCFG_SEG0_REG6_OFFSET 0xd30
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#define MPFS_MPUCFG_SEG1_REG0_OFFSET 0xe00
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#define MPFS_MPUCFG_SEG1_REG1_OFFSET 0xe08
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#define MPFS_MPUCFG_SEG1_REG2_OFFSET 0xe10
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#define MPFS_MPUCFG_SEG1_REG3_OFFSET 0xe18
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#define MPFS_MPUCFG_SEG1_REG4_OFFSET 0xe20
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#define MPFS_MPUCFG_SEG1_REG5_OFFSET 0xe28
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#define MPFS_MPUCFG_SEG1_REG6_OFFSET 0xe30
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#define MPFS_MPUCFG_SEG0_REG0 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG0_OFFSET)
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#define MPFS_MPUCFG_SEG0_REG1 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG1_OFFSET)
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#define MPFS_MPUCFG_SEG0_REG2 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG2_OFFSET)
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#define MPFS_MPUCFG_SEG0_REG3 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG3_OFFSET)
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#define MPFS_MPUCFG_SEG0_REG4 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG4_OFFSET)
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#define MPFS_MPUCFG_SEG0_REG5 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG5_OFFSET)
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#define MPFS_MPUCFG_SEG0_REG6 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG6_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG0 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG0_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG1 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG1_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG2 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG2_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG3 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG3_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG4 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG4_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG5 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG5_OFFSET)
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#define MPFS_MPUCFG_SEG1_REG6 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG6_OFFSET)
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#define MPFS_IOSCBCFG_TIMER_OFFSET 0x08
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#define MPFS_SYSREGSCB_MSS_RESET_CR_OFFSET 0x100
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@ -48,6 +48,7 @@
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#include "hardware/mpfs_sysreg.h"
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#include "hardware/mpfs_ddr.h"
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#include "hardware/mpfs_sgmii.h"
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#include "hardware/mpfs_mpucfg.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -48,6 +48,7 @@
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#include "mpfs_emmcsd.h"
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#include "riscv_internal.h"
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#include "hardware/mpfs_emmcsd.h"
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#include "hardware/mpfs_mpucfg.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -83,11 +84,6 @@
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#define MPFS_SYSREG_SUBBLK_CLOCK_CR (MPFS_SYSREG_BASE + \
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MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET)
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#define MPFS_PMPCFG_MMC_0 (MPFS_MPUCFG_BASE + 0x700)
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#define MPFS_PMPCFG_MMC_1 (MPFS_MPUCFG_BASE + 0x708)
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#define MPFS_PMPCFG_MMC_2 (MPFS_MPUCFG_BASE + 0x710)
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#define MPFS_PMPCFG_MMC_3 (MPFS_MPUCFG_BASE + 0x718)
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#define MPFS_MMC_CLOCK_400KHZ 400u
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#define MPFS_MMC_CLOCK_12_5MHZ 12500u
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#define MPFS_MMC_CLOCK_25MHZ 25000u
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@ -233,6 +229,7 @@
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MPFS_EMMCSD_SRS14_TC_IE)
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/* SD-Card IOMUX */
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#define LIBERO_SETTING_IOMUX1_CR_SD 0x00000000UL
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#ifdef CONFIG_MPFS_EMMCSD_MUX_GPIO
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#define LIBERO_SETTING_IOMUX2_CR_SD 0X00BB0000UL
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@ -58,6 +58,9 @@
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#include "mpfs_dsn.h"
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#include "mpfs_i2c.h"
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#include "hardware/mpfs_ethernet.h"
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#include "hardware/mpfs_mpucfg.h"
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#if defined(CONFIG_MPFS_ETH0_PHY_KSZ9477) ||\
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defined(CONFIG_MPFS_ETH1_PHY_KSZ9477)
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# if !defined(CONFIG_MPFS_MAC_SGMII)
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@ -78,15 +81,6 @@
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#if defined(CONFIG_NET) && defined(CONFIG_MPFS_ETHMAC)
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#define MPFS_PMPCFG_ETH0_0 (MPFS_MPUCFG_BASE + 0x400)
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#define MPFS_PMPCFG_ETH0_1 (MPFS_MPUCFG_BASE + 0x408)
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#define MPFS_PMPCFG_ETH0_2 (MPFS_MPUCFG_BASE + 0x410)
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#define MPFS_PMPCFG_ETH0_3 (MPFS_MPUCFG_BASE + 0x418)
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#define MPFS_PMPCFG_ETH1_0 (MPFS_MPUCFG_BASE + 0x500)
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#define MPFS_PMPCFG_ETH1_1 (MPFS_MPUCFG_BASE + 0x508)
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#define MPFS_PMPCFG_ETH1_2 (MPFS_MPUCFG_BASE + 0x510)
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#define MPFS_PMPCFG_ETH1_3 (MPFS_MPUCFG_BASE + 0x518)
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#if defined(CONFIG_MPFS_ETHMAC_0) && defined(CONFIG_MPFS_ETHMAC_1)
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# warning "Using 2 MACs is not yet supported."
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# define MPFS_NETHERNET (2)
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@ -27,8 +27,6 @@
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#include <nuttx/config.h>
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#include "hardware/mpfs_ethernet.h"
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#ifndef __ASSEMBLY__
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/****************************************************************************
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@ -50,6 +50,7 @@
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#include <arch/board/board.h>
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#include "hardware/mpfs_usb.h"
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#include "hardware/mpfs_mpucfg.h"
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#include "mpfs_gpio.h"
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#include "riscv_internal.h"
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#include "chip.h"
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@ -108,13 +109,6 @@
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#define MPFS_TRACEINTID_EP0_STALLSENT 0x0014
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#define MPFS_TRACEINTID_DATA_END 0x0015
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/* USB PMP configuration registers */
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#define MPFS_PMPCFG_USB_0 (MPFS_MPUCFG_BASE + 0x600)
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#define MPFS_PMPCFG_USB_1 (MPFS_MPUCFG_BASE + 0x608)
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#define MPFS_PMPCFG_USB_2 (MPFS_MPUCFG_BASE + 0x610)
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#define MPFS_PMPCFG_USB_3 (MPFS_MPUCFG_BASE + 0x618)
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/* Reset and clock control registers */
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#define MPFS_SYSREG_SOFT_RESET_CR (MPFS_SYSREG_BASE + \
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