Initial STM32H5 SPI Commit
Used STM32H7 spi driver as a base. The register set is nearly identical. All registers are named the same with the same offset. There are some bits within the registers that are different but are not referenced in stm32_spi.c. Therfore this driver may just work as is. I did modify the clock source selection for each SPI peripheral, but not much else. Differences in the registers were applied in hardware/stm32h5xxx_spi.h. Added functionality to SPI to configure the SPI RCC clock. Added SPI info to Kconfig, updated stm32_spi.c to select and set the RCC clock, and other minor updates. Updated Pin Map for SPI, added CFG1_BPASS support Fixed redefinition of GPIO_SPI6_SCK_2 Added SPI_MAX_KER_CK definition. This definition was needed because the H50 chips allow a kernel clock of 250 MHz. However the datasheets for all other chips (H52, H53, H56, H57) have a max of 125 MHz. Changed SPI Clock Source Configuration Moved setting of SPIx clock sources to stm32h5xx_rcc.c. STM32_SPIx_FREQUENCY and STM32_RCC_CCIPR3_SPIxSEL are now defined in board.h. Added error checking in stm32_spi.c to make sure STM32_SPIx_FREQUENCY and STM32_RCC_CCIPR3_SPIxSEL are actually defined. Style updates Removed SPI Clock selection from Kconfig Update arch/arm/src/stm32h5/stm32_spi.h Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com> Update arch/arm/src/stm32h5/Kconfig Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com> Update arch/arm/src/stm32h5/stm32_spi.h Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
This commit is contained in:
Kyle Wilson
Xiang Xiao
parent
2cc838aa40
commit
9b99493e14
7 changed files with 3418 additions and 6 deletions
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@ -48,6 +48,9 @@ config STM32H5_STM32H56XXX
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select STM32H5_HAVE_USART10
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select STM32H5_HAVE_USART11
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select STM32H5_HAVE_UART12
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select STM32H5_HAVE_SPI4
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select STM32H5_HAVE_SPI5
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select STM32H5_HAVE_SPI6
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config STM32H5_STM32H563XX
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# STM32H552 and STM32H562 devices documented in RM0439
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@ -211,6 +214,14 @@ config STM32H5_HAVE_LPUART1
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bool
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default n
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config STM32H5_HAVE_SPI5
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bool
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default n
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config STM32H5_HAVE_SPI6
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bool
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default n
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config STM32H5_HAVE_USART1
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bool
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default n
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@ -267,8 +278,16 @@ config STM32H5_USART
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default n
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config STM32H5_ADC
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bool
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default n
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bool
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default n
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config STM32H5_SPI
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bool
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default n
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config STM32H5_SPI_DMA
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bool
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default n
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# These are the peripheral selections proper
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@ -405,6 +424,45 @@ config STM32H5_I2C4
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default n
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select STM32H5_I2C
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config STM32H5_SPI1
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bool "SPI1"
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default n
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select SPI
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select STM32H5_SPI
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config STM32H5_SPI2
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bool "SPI2"
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default n
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select SPI
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select STM32H5_SPI
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config STM32H5_SPI3
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bool "SPI3"
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default n
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select SPI
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select STM32H5_SPI
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config STM32H5_SPI4
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bool "SPI4"
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default n
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depends on STM32H5_HAVE_SPI4
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select SPI
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select STM32H5_SPI
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config STM32H5_SPI5
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bool "SPI5"
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default n
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depends on STM32H5_HAVE_SPI5
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select SPI
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select STM32H5_SPI
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config STM32H5_SPI6
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bool "SPI6"
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default n
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depends on STM32H5_HAVE_SPI6
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select SPI
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select STM32H5_SPI
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endmenu
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@ -429,6 +487,166 @@ config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
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---help---
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Enables special, board-specific STM32 clock configuration.
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menu "SPI Configuration"
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depends on STM32H5_SPI
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config STM32H5_SPI_INTERRUPTS
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bool "Interrupt driver SPI"
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default n
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---help---
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Select to enable interrupt driven SPI support. Non-interrupt-driven,
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poll-waiting is recommended if the interrupt rate would be too high in
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the interrupt driven case.
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config STM32H5_SPI_DMATHRESHOLD
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int "SPI DMA threshold"
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default 4
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depends on STM32H5_SPI_DMA
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---help---
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When SPI DMA is enabled, small DMA transfers will still be performed
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by polling logic. But we need a threshold value to determine what
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is small.
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config STM32H5_SPI1_DMA
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bool "SPI1 DMA"
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default n
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depends on STM32H5_SPI1 && !STM32H5_SPI_INTERRUPT
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select STM32H5_SPI_DMA
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---help---
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Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT
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config STM32H5_SPI1_DMA_BUFFER
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int "SPI1 DMA buffer size"
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default 0
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depends on STM32H5_SPI1_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI1.
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config STM32H5_SPI1_COMMTYPE
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int "SPI1 Operation mode"
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default 0
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range 0 3
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depends on STM32H5_SPI1
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---help---
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Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
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config STM32H5_SPI2_DMA
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bool "SPI2 DMA"
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default n
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depends on STM32H5_SPI2 && !STM32H5_SPI_INTERRUPT
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select STM32H5_SPI_DMA
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---help---
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Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT
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config STM32H5_SPI2_DMA_BUFFER
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int "SPI2 DMA buffer size"
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default 0
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depends on STM32H5_SPI2_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI2.
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config STM32H5_SPI2_COMMTYPE
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int "SPI2 Operation mode"
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default 0
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range 0 3
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depends on STM32H5_SPI2
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---help---
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Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
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config STM32H5_SPI3_DMA
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bool "SPI3 DMA"
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default n
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depends on STM32H5_SPI3 && !STM32H5_SPI_INTERRUPT
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select STM32H5_SPI_DMA
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---help---
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Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT
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config STM32H5_SPI3_DMA_BUFFER
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int "SPI3 DMA buffer size"
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default 0
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depends on STM32H5_SPI3_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI3.
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config STM32H5_SPI3_COMMTYPE
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int "SPI3 Operation mode"
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default 0
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range 0 3
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depends on STM32H5_SPI3
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---help---
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Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
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config STM32H5_SPI4_DMA
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bool "SPI4 DMA"
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default n
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depends on STM32H5_SPI4 && !STM32H5_SPI_INTERRUPT
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select STM32H5_SPI_DMA
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---help---
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Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT
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config STM32H5_SPI4_DMA_BUFFER
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int "SPI4 DMA buffer size"
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default 0
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depends on STM32H5_SPI4_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI4.
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config STM32H5_SPI4_COMMTYPE
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int "SPI4 Operation mode"
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default 0
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range 0 3
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depends on STM32H5_SPI4
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---help---
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Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
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config STM32H5_SPI5_DMA
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bool "SPI5 DMA"
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default n
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depends on STM32H5_SPI5 && !STM32H5_SPI_INTERRUPT
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select STM32H5_SPI_DMA
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---help---
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Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT
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config STM32H5_SPI5_DMA_BUFFER
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int "SPI5 DMA buffer size"
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default 0
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depends on STM32H5_SPI5_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI5.
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config STM32H5_SPI5_COMMTYPE
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int "SPI5 Operation mode"
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default 0
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range 0 3
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depends on STM32H5_SPI5
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---help---
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Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
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config STM32H5_SPI6_DMA
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bool "SPI6 DMA"
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default n
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depends on STM32H5_SPI6 && !STM32H5_SPI_INTERRUPT
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select STM32H5_SPI_DMA
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---help---
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Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT
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config STM32H5_SPI6_DMA_BUFFER
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int "SPI6 DMA buffer size"
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default 0
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depends on STM32H5_SPI6_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI6.
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config STM32H5_SPI6_COMMTYPE
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int "SPI6 Operation mode"
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default 0
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range 0 3
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depends on STM32H5_SPI6
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---help---
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Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
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endmenu # "SPI Configuration"
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config STM32H5_SERIALDRIVER
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bool
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@ -54,6 +54,10 @@ ifeq ($(CONFIG_ADC),y)
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CHIP_CSRCS += stm32_adc.c
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endif
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ifeq ($(CONFIG_STM32H5_SPI),y)
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CHIP_CSRCS += stm32_spi.c
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endif
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# Required chip type specific files
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ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
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@ -146,6 +146,103 @@
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#define GPIO_JTMS_SWDAT_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
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#define GPIO_JTRST_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
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/* SPI */
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#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN6)
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#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN9)
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#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5)
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#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN7)
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#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15)
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#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN10)
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#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5)
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#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3)
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#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN11)
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#define GPIO_SPI1_RDY_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN8)
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#define GPIO_SPI1_RDY_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN2)
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#define GPIO_SPI1_RDY_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTE|GPIO_PIN11)
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#define GPIO_SPI1_RDY_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN6)
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#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN14)
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#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN2)
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#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15)
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#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN1)
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#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN1)
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#define GPIO_SPI2_MOSI_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN3)
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#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
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#define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0)
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#define GPIO_SPI2_NSS_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN12)
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#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
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#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
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#define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1)
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#define GPIO_SPI2_RDY_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_SPI2_RDY_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN0)
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#define GPIO_SPI2_RDY_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN5)
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#define GPIO_SPI2_RDY_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTI|GPIO_PIN4)
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#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11)
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#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6)
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#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
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#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN2)
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#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5)
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#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
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#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3)
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#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10)
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#define GPIO_SPI3_RDY_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_SPI3_RDY_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN0)
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#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN13)
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#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN5)
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#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN14)
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#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN6)
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#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN11)
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#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN4)
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#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN12)
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#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTE|GPIO_PIN2)
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#define GPIO_SPI4_RDY_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_SPI4_RDY_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_SPI4_RDY_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN15)
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#define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN8)
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#define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN7)
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#define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN11)
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#define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN9)
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#define GPIO_SPI5_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN8)
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#define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN6)
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#define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN5)
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#define GPIO_SPI5_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN9)
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#define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN7)
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#define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN6)
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#define GPIO_SPI5_RDY_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN4)
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#define GPIO_SPI5_RDY_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTH|GPIO_PIN4)
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#define GPIO_SPI6_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN12)
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#define GPIO_SPI6_MISO_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN6)
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#define GPIO_SPI6_MISO_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_SPI6_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN14)
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#define GPIO_SPI6_MOSI_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_SPI6_MOSI_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI6_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_SPI6_NSS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI6_NSS_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI6_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_SPI6_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SPI6_SCK_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_SPI6_SCK_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SPI6_RDY_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_SPI6_RDY_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTH|GPIO_PIN5)
|
||||
|
||||
/* Trace */
|
||||
|
||||
#define GPIO_TRACECK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
|
||||
|
|
|
|||
|
|
@ -1002,7 +1002,7 @@
|
|||
# define RCC_CCIPR3_SPI1SEL_PLL2PCK (1 << RCC_CCIPR3_SPI1SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI1SEL_PLL3PCK (2 << RCC_CCIPR3_SPI1SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI1SEL_AUDIOCK (3 << RCC_CCIPR3_SPI1SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI1SEL_PERCKv (4 << RCC_CCIPR3_SPI1SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI1SEL_PERCK (4 << RCC_CCIPR3_SPI1SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR3_SPI2SEL_SHIFT (3)
|
||||
#define RCC_CCIPR3_SPI2SEL_MASK (7 << RCC_CCIPR3_SPI2SEL_SHIFT)
|
||||
|
|
@ -1010,7 +1010,7 @@
|
|||
# define RCC_CCIPR3_SPI2SEL_PLL2PCK (1 << RCC_CCIPR3_SPI2SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI2SEL_PLL3PCK (2 << RCC_CCIPR3_SPI2SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI2SEL_AUDIOCK (3 << RCC_CCIPR3_SPI2SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI2SEL_PERCKv (4 << RCC_CCIPR3_SPI2SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI2SEL_PERCK (4 << RCC_CCIPR3_SPI2SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR3_SPI3SEL_SHIFT (6)
|
||||
#define RCC_CCIPR3_SPI3SEL_MASK (7 << RCC_CCIPR3_SPI3SEL_SHIFT)
|
||||
|
|
@ -1018,11 +1018,11 @@
|
|||
# define RCC_CCIPR3_SPI3SEL_PLL2PCK (1 << RCC_CCIPR3_SPI3SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI3SEL_PLL3PCK (2 << RCC_CCIPR3_SPI3SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI3SEL_AUDIOCK (3 << RCC_CCIPR3_SPI3SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI3SEL_PERCKv (4 << RCC_CCIPR3_SPI3SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI3SEL_PERCK (4 << RCC_CCIPR3_SPI3SEL_SHIFT)
|
||||
|
||||
#define RCC_CCIPR3_SPI4SEL_SHIFT (9)
|
||||
#define RCC_CCIPR3_SPI4SEL_MASK (7 << RCC_CCIPR3_SPI4SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI4SEL_RCCPCLK1 (0 << RCC_CCIPR3_SPI4SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI4SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI4SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI4SEL_PLL2QCK (1 << RCC_CCIPR3_SPI4SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI4SEL_PLL3QCK (2 << RCC_CCIPR3_SPI4SEL_SHIFT)
|
||||
# define RCC_CCIPR3_SPI4SEL_HSIKERCK (3 << RCC_CCIPR3_SPI4SEL_SHIFT)
|
||||
|
|
|
|||
2824
arch/arm/src/stm32h5/stm32_spi.c
Normal file
2824
arch/arm/src/stm32h5/stm32_spi.c
Normal file
File diff suppressed because it is too large
Load diff
215
arch/arm/src/stm32h5/stm32_spi.h
Normal file
215
arch/arm/src/stm32h5/stm32_spi.h
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_spi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_SPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32h5xxx_spi.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
struct spi_dev_s; /* Forward reference */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI bus
|
||||
*
|
||||
* Input Parameters:
|
||||
* bus number (for hardware that has multiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct spi_dev_s *stm32_spibus_initialize(int bus);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi_slave_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI bus for slave operation
|
||||
*
|
||||
* Input Parameters:
|
||||
* bus number
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi1/2/...select and stm32_spi1/2/...status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status,
|
||||
* and stm32_spi1/2/...cmddata must be provided by board-specific logic.
|
||||
* These are implementations of the select, status, and cmddata methods of
|
||||
* the SPI interface defined by struct spi_ops_s (see
|
||||
* include/nuttx/spi/spi.h).
|
||||
* All other methods (including stm32_spibus_initialize()) are provided by
|
||||
* common STM32 logic. To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status()
|
||||
* functions in your board-specific logic. These functions will perform
|
||||
* chip selection and status operations using GPIOs in the way your
|
||||
* board is configured.
|
||||
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
|
||||
* then provide stm32_spi1/2/...cmddata() functions in your board-
|
||||
* specific logic. These functions will perform cmd/data selection
|
||||
* operations using GPIOs in the way your board is configured.
|
||||
* 4. Add a call to stm32_spibus_initialize() in your low level
|
||||
* application initialization logic
|
||||
* 5. The handle returned by stm32_spibus_initialize() may then be used to
|
||||
* bind the SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI1
|
||||
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI2
|
||||
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI3
|
||||
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI4
|
||||
void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI5
|
||||
void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI6
|
||||
void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi1/2/...register
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based
|
||||
* MMC/SD driver when an SD card is inserted or removed, then
|
||||
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
|
||||
* be implemented. These functions implement the registercallback method
|
||||
* of the SPI interface (see include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The function to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_STM32H5_SPI1
|
||||
int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI2
|
||||
int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI3
|
||||
int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI4
|
||||
int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI5
|
||||
int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SPI6
|
||||
int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
void *arg);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_SPI_H */
|
||||
|
|
@ -1204,6 +1204,60 @@ void stm32_stdclockconfig(void)
|
|||
regval |= STM32_RCC_CCIPR5_ADCDACSEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR5);
|
||||
#endif
|
||||
|
||||
/* Configure SPI1 source clock */
|
||||
|
||||
#if defined(STM32_RCC_CCIPR3_SPI1SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR3);
|
||||
regval &= ~RCC_CCIPR3_SPI1SEL_MASK;
|
||||
regval |= STM32_RCC_CCIPR3_SPI1SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
|
||||
/* Configure SPI2 source clock */
|
||||
|
||||
#if defined(STM32_RCC_CCIPR3_SPI2SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR3);
|
||||
regval &= ~RCC_CCIPR3_SPI2SEL_MASK;
|
||||
regval |= STM32_RCC_CCIPR3_SPI2SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
|
||||
/* Configure SPI3 source clock */
|
||||
|
||||
#if defined(STM32_RCC_CCIPR3_SPI3SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR3);
|
||||
regval &= ~RCC_CCIPR3_SPI3SEL_MASK;
|
||||
regval |= STM32_RCC_CCIPR3_SPI3SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
|
||||
/* Configure SPI4 source clock */
|
||||
|
||||
#if defined(STM32_RCC_CCIPR3_SPI4SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR3);
|
||||
regval &= ~RCC_CCIPR3_SPI4SEL_MASK;
|
||||
regval |= STM32_RCC_CCIPR3_SPI4SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
|
||||
/* Configure SPI5 source clock */
|
||||
|
||||
#if defined(STM32_RCC_CCIPR3_SPI5SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR3);
|
||||
regval &= ~RCC_CCIPR3_SPI5SEL_MASK;
|
||||
regval |= STM32_RCC_CCIPR3_SPI5SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
|
||||
/* Configure SPI6 source clock */
|
||||
|
||||
#if defined(STM32_RCC_CCIPR3_SPI6SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR3);
|
||||
regval &= ~RCC_CCIPR3_SPI6SEL_MASK;
|
||||
regval |= STM32_RCC_CCIPR3_SPI6SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue