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sched/wdog: Don't dynamically allocate wdog_s

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to save the preserved space(1KB) and also avoid the heap overhead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I694073f68e1bd63960cedeea1ddec441437be025
This commit is contained in:
Xiang Xiao 2020-08-04 18:31:31 +08:00 committed by patacongo
parent 4df42ba9fb
commit a0ce81d659
666 changed files with 915 additions and 3286 deletions
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111
Documentation/NuttxPortingGuide.html
View file

@ -2824,108 +2824,21 @@ int up_timer_start(FAR const struct timespec *ts);
or <code>kill()</code> to communicate with NuttX tasks.
</p>
<ul>
<li><a href="#wdcreate">4.4.5.1 wd_create/wd_static</a></li>
<li><a href="#wddelete">4.4.5.2 wd_delete</a></li>
<li><a href="#wdstart">4.4.5.3 wd_start</a></li>
<li><a href="#wdcancel">4.4.5.4 wd_cancel</a></li>
<li><a href="#wdgettime">4.4.5.5 wd_gettime</a></li>
<li><a href="#wdcallback">4.4.5.6 Watchdog Timer Callback</a></li>
<li><a href="#wdstart">4.4.5.1 wd_start</a></li>
<li><a href="#wdcancel">4.4.5.2 wd_cancel</a></li>
<li><a href="#wdgettime">4.4.5.3 wd_gettime</a></li>
<li><a href="#wdcallback">4.4.5.4 Watchdog Timer Callback</a></li>
</ul>
<h4><a name="wdcreate">4.4.5.1 wd_create/wd_static</a></h4>
<h4><a name="wdstart">4.4.5.1 wd_start</a></h4>
<p>
<b>Function Prototype:</b>
<pre>
#include &lt;nuttx/wdog.h&gt;
WDOG_ID wd_create(void);
void wd_static(FAR struct wdog_s *wdog);
</pre>
<p>
<b>Description:</b> The <code>wd_create()</code> function will create a timer by allocating the appropriate resources for the watchdog. The <code>wd_create()</code> function returns a pointer to a fully initialized, dynamically allocated <code>struct wdog_s</code> instance (which is <code>typedef</code>'ed as <code>WDOG_ID</code>);
</p>
<p>
<code>wd_static()</code> performs the equivalent initialization of a statically allocated <code>struct wdog_s</code> instance. No allocation is performed in this case. The initializer definition, <code>WDOG_INITIALIZER</code> is also available for initialization of static instances of <code>struct wdog_s</code>. NOTE: <code>wd_static()</code> is also implemented as a macro definition.
</p>
<p>
<b>Input Parameters:</b> None.
<p>
<b>Returned Value:</b>
<ul>
<li>Pointer to watchdog that may be used as a handle in subsequent NuttX calls (i.e., the watchdog ID), or NULL if insufficient resources are available to create the watchdogs.
</ul>
<p>
<b>Assumptions/Limitations:</b>
<p>
<b> POSIX Compatibility:</b> This is a NON-POSIX interface.
VxWorks provides the following comparable interface:
<pre>
WDOG_ID wdCreate (void);
</pre>
<p>
Differences from the VxWorks interface include:
<ul>
<li>The number of available watchdogs is fixed (configured at
initialization time).
</ul>
<h4><a name="wddelete">4.4.5.2 wd_delete</a></h4>
<p>
<b>Function Prototype:</b>
<pre>
#include &lt;nuttx/wdog.h&gt;
int wd_delete(WDOG_ID wdog);
</pre>
<p>
<b>Description:</b> The wd_delete function will deallocate a watchdog timer previously allocated via <code>wd_create()</code>. The watchdog timer will be removed from the timer queue if has been started.
<p>
<p>
This function need not be called for statically allocated timers (but it is not harmful to do so).
</p>
<b>Input Parameters:</b>
<ul>
<li><code>wdog</code>. The watchdog ID to delete. This is actually a
pointer to a watchdog structure.
</ul>
<p>
<b>Returned Value:</b>
<ul>
<li>Zero (<code>OK</code>) is returned on success; a negated <code>errno</code> value is return to indicate the nature of any failure.
</ul>
<p>
<b>Assumptions/Limitations:</b> It is the responsibility of the
caller to assure that the watchdog is inactive before deleting
it.
<p>
<b>POSIX Compatibility:</b> This is a NON-POSIX interface.
VxWorks provides the following comparable interface:
<pre>
STATUS wdDelete (WDOG_ID wdog);
</pre>
<p>
Differences from the VxWorks interface include:
<ul>
<li>Does not make any checks to see if the watchdog is being used
before deallocating it (i.e., never returns ERROR).
</ul>
<h4><a name="wdstart">4.4.5.3 wd_start</a></h4>
<p>
<b>Function Prototype:</b>
<pre>
#include &lt;nuttx/wdog.h&gt;
int wd_start(WDOG_ID wdog, int delay, wdentry_t wdentry,
int argc, ....);
int wd_start(FAR struct wdog_s *wdog, int delay,
wdentry_t wdentry, int argc, ....);
</pre>
<p>
@ -2980,12 +2893,12 @@ to wdentry; VxWorks supports only a single parameter. The maximum
number of parameters is determined by
</ul>
<h4><a name="wdcancel">4.4.5.4 wd_cancel</a></h4>
<h4><a name="wdcancel">4.4.5.2 wd_cancel</a></h4>
<p>
<b>Function Prototype:</b>
<pre>
#include &lt;nuttx/wdog.h&gt;
int wd_cancel(WDOG_ID wdog);
int wd_cancel(FAR struct wdog_s *wdog);
</pre>
<p>
@ -3013,13 +2926,13 @@ VxWorks provides the following comparable interface:
STATUS wdCancel (WDOG_ID wdog);
</pre>
<h3><a name="wdgettime">4.4.5.5 wd_gettime</a></h3>
<h3><a name="wdgettime">4.4.5.3 wd_gettime</a></h3>
<p>
<b>Function Prototype:</b>
</p>
<pre>
#include &lt;nuttx/wdog.h&gt;
int wd_gettime(WDOG_ID wdog);
int wd_gettime(FAR struct wdog_s *wdog);
</pre>
<p>
<b>Description:</b>
@ -3037,7 +2950,7 @@ VxWorks provides the following comparable interface:
means either that wdog is not valid or that the wdog has already expired.
</p>
<h4><a name="wdcallback">4.4.5.6 Watchdog Timer Callback</a></h4>
<h4><a name="wdcallback">4.4.5.4 Watchdog Timer Callback</a></h4>
<p>
When a watchdog expires, the callback function with this type is called:
</p>

1
Documentation/NuttxUserGuide.html
View file

@ -10139,7 +10139,6 @@ OS resources. These hidden structures include:
<li>struct tcb_s
<li>mqd_t
<li>sem_t
<li>WDOG_ID
<li>pthread_key_t
</ul>
<p>

25
arch/arm/src/c5471/c5471_ethernet.c
View file

@ -318,8 +318,8 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
struct c5471_driver_s
{
bool c_bifup; /* true:ifup false:ifdown */
WDOG_ID c_txpoll; /* TX poll timer */
WDOG_ID c_txtimeout; /* TX timeout timer */
struct wdog_s c_txpoll; /* TX poll timer */
struct wdog_s c_txtimeout; /* TX timeout timer */
struct work_s c_irqwork; /* For deferring interrupt work to the work queue */
struct work_s c_pollwork; /* For deferring poll work to the work queue */
@ -1011,7 +1011,7 @@ static int c5471_transmit(struct c5471_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->c_txtimeout, C5471_TXTIMEOUT,
wd_start(&priv->c_txtimeout, C5471_TXTIMEOUT,
c5471_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1575,7 +1575,7 @@ static void c5471_txdone(struct c5471_driver_s *priv)
{
/* If no further xmits are pending, then cancel the TX timeout */
wd_cancel(priv->c_txtimeout);
wd_cancel(&priv->c_txtimeout);
/* Then poll the network for new XMIT data */
@ -1705,7 +1705,7 @@ static int c5471_interrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->c_txtimeout);
wd_cancel(&priv->c_txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1828,7 +1828,7 @@ static void c5471_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
wd_start(&priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
(wdparm_t)priv);
net_unlock();
}
@ -1915,7 +1915,7 @@ static int c5471_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
wd_start(&priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -1968,8 +1968,8 @@ static int c5471_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->c_txpoll);
wd_cancel(priv->c_txtimeout);
wd_cancel(&priv->c_txpoll);
wd_cancel(&priv->c_txtimeout);
/* Reset the device */
@ -2498,12 +2498,7 @@ void arm_netinitialize(void)
g_c5471[0].c_dev.d_addmac = c5471_addmac; /* Add multicast MAC address */
g_c5471[0].c_dev.d_rmmac = c5471_rmmac; /* Remove multicast MAC address */
#endif
g_c5471[0].c_dev.d_private = (void *)g_c5471; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
g_c5471[0].c_txpoll = wd_create(); /* Create periodic poll timer */
g_c5471[0].c_txtimeout = wd_create(); /* Create TX timeout timer */
g_c5471[0].c_dev.d_private = g_c5471; /* Used to recover private state from dev */
/* Register the device with the OS so that socket IOCTLs can be performed */

13
arch/arm/src/cxd56xx/cxd56_i2c.c
View file

@ -98,7 +98,7 @@ struct cxd56_i2cdev_s
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for transfer completion */
WDOG_ID timeout; /* watchdog to timeout when bus hung */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
ssize_t reg_buff_offset;
ssize_t rw_size;
@ -493,7 +493,7 @@ static int cxd56_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
* Therefore, call nxsem_post() only when wd_cancel() succeeds.
*/
ret = wd_cancel(priv->timeout);
ret = wd_cancel(&priv->timeout);
if (ret == OK)
{
i2c_givesem(&priv->wait);
@ -550,7 +550,7 @@ static int cxd56_i2c_receive(struct cxd56_i2cdev_s *priv, int last)
}
flags = enter_critical_section();
wd_start(priv->timeout, I2C_TIMEOUT,
wd_start(&priv->timeout, I2C_TIMEOUT,
cxd56_i2c_timeout, 1, (wdparm_t)priv);
/* Set stop flag for indicate the last data */
@ -596,7 +596,7 @@ static int cxd56_i2c_send(struct cxd56_i2cdev_s *priv, int last)
while (!(i2c_reg_read(priv, CXD56_IC_STATUS) & STATUS_TFNF));
flags = enter_critical_section();
wd_start(priv->timeout, I2C_TIMEOUT,
wd_start(&priv->timeout, I2C_TIMEOUT,
cxd56_i2c_timeout, 1, (wdparm_t)priv);
i2c_reg_write(priv, CXD56_IC_DATA_CMD,
(uint32_t)msg->buffer[i] | (last ? CMD_STOP : 0));
@ -1056,8 +1056,6 @@ struct i2c_master_s *cxd56_i2cbus_initialize(int port)
nxsem_init(&priv->wait, 0, 0);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
priv->timeout = wd_create();
/* Attach Interrupt Handler */
irq_attach(priv->irqid, cxd56_i2c_interrupt, priv);
@ -1119,8 +1117,7 @@ int cxd56_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
up_disable_irq(priv->irqid);
irq_detach(priv->irqid);
wd_delete(priv->timeout);
priv->timeout = NULL;
wd_cancel(&priv->timeout);
nxsem_destroy(&priv->mutex);
nxsem_destroy(&priv->wait);

10
arch/arm/src/cxd56xx/cxd56_icc.c
View file

@ -122,7 +122,7 @@ struct iccdev_s
FAR void *userdata;
sem_t rxwait;
WDOG_ID rxtimeout;
struct wdog_s rxtimeout;
int flags;
@ -338,11 +338,11 @@ static int icc_recv(FAR struct iccdev_s *priv, FAR iccmsg_t *msg, int32_t ms)
{
int32_t timo;
timo = ms * 1000 / CONFIG_USEC_PER_TICK;
wd_start(priv->rxtimeout, timo, icc_rxtimeout, 1, (wdparm_t)priv);
wd_start(&priv->rxtimeout, timo, icc_rxtimeout, 1, (wdparm_t)priv);
icc_semtake(&priv->rxwait);
wd_cancel(priv->rxtimeout);
wd_cancel(&priv->rxtimeout);
}
flags = enter_critical_section();
@ -379,8 +379,6 @@ static FAR struct iccdev_s *icc_devnew(void)
memset(priv, 0, sizeof(struct iccdev_s));
priv->rxtimeout = wd_create();
nxsem_init(&priv->rxwait, 0, 0);
nxsem_set_protocol(&priv->rxwait, SEM_PRIO_NONE);
@ -401,7 +399,7 @@ static FAR struct iccdev_s *icc_devnew(void)
static void icc_devfree(FAR struct iccdev_s *priv)
{
wd_delete(priv->rxtimeout);
wd_cancel(&priv->rxtimeout);
kmm_free(priv);
}

16
arch/arm/src/cxd56xx/cxd56_rtc.c
View file

@ -254,13 +254,8 @@ static void cxd56_rtc_initialize(int argc, ...)
{
struct timespec ts;
#ifdef CONFIG_CXD56_RTC_LATEINIT
static WDOG_ID s_wdog = NULL;
static int s_retry = 0;
if (s_wdog == NULL)
{
s_wdog = wd_create();
}
static struct wdog_s s_wdog;
static int s_retry = 0;
/* Check whether RTC clock source selects the external RTC and the
* synchronization from the external RTC is completed.
@ -278,7 +273,7 @@ static void cxd56_rtc_initialize(int argc, ...)
{
rtcinfo("retry count: %d\n", s_retry);
if (OK == wd_start(s_wdog, MSEC2TICK(RTC_CLOCK_CHECK_INTERVAL),
if (OK == wd_start(&s_wdog, MSEC2TICK(RTC_CLOCK_CHECK_INTERVAL),
(wdentry_t)cxd56_rtc_initialize, 0))
{
/* Again, this function is called recursively */
@ -292,10 +287,7 @@ static void cxd56_rtc_initialize(int argc, ...)
/* RTC clock is stable, or give up using the external RTC */
if (s_wdog != NULL)
{
wd_delete(s_wdog);
}
wd_cancel(&s_wdog);
#endif
#ifdef CONFIG_RTC_ALARM

17
arch/arm/src/cxd56xx/cxd56_sdhci.c
View file

@ -252,7 +252,7 @@ struct cxd56_sdiodev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1016,7 +1016,7 @@ static void cxd56_endwait(struct cxd56_sdiodev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1364,11 +1364,6 @@ static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
/* The next phase of the hardware reset would be to set the SYSCTRL INITA
* bit to send 80 clock ticks for card to power up and then reset the card
* with CMD0. This is done elsewhere.
@ -1383,7 +1378,7 @@ static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev)
priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2085,7 +2080,7 @@ static int cxd56_sdio_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2594,7 +2589,7 @@ static sdio_eventset_t cxd56_sdio_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
cxd56_eventtimeout, 1, (wdparm_t)priv);
if (ret != OK)
{
@ -2623,7 +2618,7 @@ static sdio_eventset_t cxd56_sdio_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
return SDIOWAIT_ERROR;
}

17
arch/arm/src/efm32/efm32_spi.c
View file

@ -126,7 +126,7 @@ struct efm32_spidev_s
const struct efm32_spiconfig_s *config; /* Constant SPI hardware configuration */
#ifdef CONFIG_EFM32_SPI_DMA
WDOG_ID wdog; /* Timer to catch hung DMA */
struct wdog_s wdog; /* Timer to catch hung DMA */
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the TX DMA */
DMA_HANDLE rxdmach; /* RX DMA channel handle */
@ -452,7 +452,7 @@ static void spi_dmarxwait(struct efm32_spidev_s *priv)
DEBUGASSERT(priv->rxresult != EINPROGRESS);
if (priv->txresult != EINPROGRESS)
{
wd_cancel(priv->wdog);
wd_cancel(&priv->wdog);
}
leave_critical_section(flags);
@ -482,7 +482,7 @@ static void spi_dmatxwait(struct efm32_spidev_s *priv)
DEBUGASSERT(priv->txresult != EINPROGRESS);
if (priv->rxresult != EINPROGRESS)
{
wd_cancel(priv->wdog);
wd_cancel(&priv->wdog);
}
leave_critical_section(flags);
@ -1465,7 +1465,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* when both RX and TX transfers complete.
*/
ret = wd_start(priv->wdog, (int)ticks,
ret = wd_start(&priv->wdog, (int)ticks,
spi_dma_timeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -1620,15 +1620,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
goto errout_with_rxdmach;
}
/* Allocate a timer to catch hung DMA transfers */
priv->wdog = wd_create();
if (!priv->wdog)
{
spierr("ERROR: Failed to create a timer for SPI port: %d\n", port);
goto errout_with_txdmach;
}
/* Initialized semaphores used to wait for DMA completion */
nxsem_init(&priv->rxdmasem, 0, 0);

25
arch/arm/src/imxrt/imxrt_enet.c
View file

@ -265,8 +265,8 @@ struct imxrt_driver_s
uint8_t txhead; /* The next TX descriptor to use */
uint8_t rxtail; /* The next RX descriptor to use */
uint8_t phyaddr; /* Selected PHY address */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
@ -565,7 +565,7 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, IMXRT_TXTIMEOUT,
wd_start(&priv->txtimeout, IMXRT_TXTIMEOUT,
imxrt_txtimeout_expiry, 1, (wdparm_t)priv);
/* Start the TX transfer (if it was not already waiting for buffers) */
@ -913,7 +913,7 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv)
* canceled.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* Verify that the oldest descriptor descriptor completed */
@ -955,7 +955,7 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv)
{
/* No.. Cancel the TX timeout and disable further Tx interrupts. */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
regval = getreg32(IMXRT_ENET_EIMR);
regval &= ~TX_INTERRUPTS;
@ -1239,7 +1239,7 @@ static void imxrt_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again in any case */
wd_start(priv->txpoll, IMXRT_WDDELAY,
wd_start(&priv->txpoll, IMXRT_WDDELAY,
imxrt_polltimer_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1371,7 +1371,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Set and activate a timer process */
wd_start(priv->txpoll, IMXRT_WDDELAY,
wd_start(&priv->txpoll, IMXRT_WDDELAY,
imxrt_polltimer_expiry, 1, (wdparm_t)priv);
/* Clear all pending ENET interrupt */
@ -1456,8 +1456,8 @@ static int imxrt_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the imxrt_ifup() always
@ -2535,12 +2535,7 @@ int imxrt_netinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = imxrt_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_enet; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = g_enet; /* Used to recover private state from dev */
#ifdef CONFIG_NET_ETHERNET
/* Determine a semi-unique MAC address from MCU UID

17
arch/arm/src/imxrt/imxrt_usdhc.c
View file

@ -171,7 +171,7 @@ struct imxrt_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1062,7 +1062,7 @@ static void imxrt_endwait(struct imxrt_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1398,7 +1398,7 @@ static void imxrt_reset(FAR struct sdio_dev_s *dev)
priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2279,7 +2279,7 @@ static int imxrt_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2708,7 +2708,7 @@ static sdio_eventset_t imxrt_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
imxrt_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
@ -2738,7 +2738,7 @@ static sdio_eventset_t imxrt_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
return SDIOWAIT_ERROR;
}
@ -3119,11 +3119,6 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
switch (priv->addr)
{
case IMXRT_USDHC1_BASE:

25
arch/arm/src/kinetis/kinetis_enet.c
View file

@ -237,8 +237,8 @@ struct kinetis_driver_s
uint8_t txhead; /* The next TX descriptor to use */
uint8_t rxtail; /* The next RX descriptor to use */
uint8_t phyaddr; /* Selected PHY address */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
uint32_t ints; /* Enabled interrupts */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -520,7 +520,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, KINETIS_TXTIMEOUT,
wd_start(&priv->txtimeout, KINETIS_TXTIMEOUT,
kinetis_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -821,7 +821,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
{
/* No.. Cancel the TX timeout and disable further Tx interrupts. */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
priv->ints &= ~TX_INTERRUPTS;
modifyreg32(KINETIS_ENET_EIMR, TX_INTERRUPTS, priv->ints);
}
@ -975,7 +975,7 @@ static int kinetis_interrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1100,7 +1100,7 @@ static void kinetis_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again in any case */
wd_start(priv->txpoll, KINETIS_WDDELAY,
wd_start(&priv->txpoll, KINETIS_WDDELAY,
kinetis_polltimer_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1243,7 +1243,7 @@ static int kinetis_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, KINETIS_WDDELAY,
wd_start(&priv->txpoll, KINETIS_WDDELAY,
kinetis_polltimer_expiry, 1, (wdparm_t)priv);
putreg32(0, KINETIS_ENET_EIMR);
@ -1309,8 +1309,8 @@ static int kinetis_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the kinetis_ifup() always
@ -2231,12 +2231,7 @@ int kinetis_netinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = kinetis_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_enet; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = g_enet; /* Used to recover private state from dev */
#ifdef CONFIG_NET_ETHERNET
/* Determine a semi-unique MAC address from MCU UID

16
arch/arm/src/kinetis/kinetis_flexcan.c
View file

@ -294,7 +294,7 @@ struct kinetis_driver_s
uint32_t base; /* FLEXCAN base address */
bool bifup; /* true:ifup false:ifdown */
#ifdef TX_TIMEOUT_WQ
WDOG_ID txtimeout[TXMBCOUNT]; /* TX timeout timer */
struct wdog_s txtimeout[TXMBCOUNT]; /* TX timeout timer */
#endif
struct work_s irqwork; /* For deferring interrupt work to the wq */
struct work_s pollwork; /* For deferring poll work to the work wq */
@ -751,7 +751,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
if (timeout > 0)
{
wd_start(priv->txtimeout[mbi], timeout + 1,
wd_start(&priv->txtimeout[mbi], timeout + 1,
kinetis_txtimeout_expiry, 1, (wdparm_t)priv);
}
#endif
@ -1003,7 +1003,7 @@ static void kinetis_txdone(FAR void *arg)
* corresponding watchdog can be canceled.
*/
wd_cancel(priv->txtimeout[mbi]);
wd_cancel(&priv->txtimeout[mbi]);
#endif
}
@ -1867,15 +1867,7 @@ int kinetis_caninitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = kinetis_ioctl; /* Support CAN ioctl() calls */
#endif
priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */
#ifdef TX_TIMEOUT_WQ
for (i = 0; i < TXMBCOUNT; i++)
{
priv->txtimeout[i] = wd_create(); /* Create TX timeout timer */
}
#endif
priv->dev.d_private = priv; /* Used to recover private state from dev */
priv->rx = (struct mb_s *)(priv->base + KINETIS_CAN_MB_OFFSET);
priv->tx = (struct mb_s *)(priv->base + KINETIS_CAN_MB_OFFSET +
(sizeof(struct mb_s) * RXMBCOUNT));

20
arch/arm/src/kinetis/kinetis_i2c.c
View file

@ -130,7 +130,7 @@ struct kinetis_i2cdev_s
bool restart; /* Should next transfer restart or not */
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
WDOG_ID timeout; /* watchdog to timeout when bus hung */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
struct i2c_msg_s *msgs; /* Remaining transfers - first one is in
* progress */
};
@ -1222,11 +1222,11 @@ static int kinetis_i2c_transfer(struct i2c_master_s *dev,
/* Wait for transfer complete */
wd_start(priv->timeout, I2C_TIMEOUT,
wd_start(&priv->timeout, I2C_TIMEOUT,
kinetis_i2c_timeout, 1, (wdparm_t)priv);
kinetis_i2c_wait(priv);
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
msg_n++;
}
@ -1437,14 +1437,6 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
flags = enter_critical_section();
if ((volatile int)priv->refs++ == 0)
{
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
if (priv->timeout == NULL)
{
priv->refs--;
goto errout;
}
kinetis_i2c_sem_init(priv);
kinetis_i2c_init(priv);
}
@ -1452,10 +1444,6 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
leave_critical_section(flags);
return &priv->dev;
errout:
leave_critical_section(flags);
return NULL;
}
/****************************************************************************
@ -1494,7 +1482,7 @@ int kinetis_i2cbus_uninitialize(struct i2c_master_s *dev)
kinetis_i2c_deinit(priv);
kinetis_i2c_sem_destroy(priv);
wd_delete(priv->timeout);
wd_cancel(&priv->timeout);
return OK;
}

17
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -166,7 +166,7 @@ struct kinetis_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -979,7 +979,7 @@ static void kinetis_endwait(struct kinetis_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1295,7 +1295,7 @@ static void kinetis_reset(FAR struct sdio_dev_s *dev)
priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2071,7 +2071,7 @@ static int kinetis_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2506,7 +2506,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
kinetis_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2535,7 +2535,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
return SDIOWAIT_ERROR;
}
@ -2878,11 +2878,6 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
/* In addition to the system clock, the SDHC module needs a clock for the
* base for the external card clock. There are four possible sources for
* this clock, selected by the SIM's SOPT2 register:

12
arch/arm/src/kinetis/kinetis_usbdev.c
View file

@ -496,7 +496,7 @@ struct khci_usbdev_s
uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */
uint16_t epavail; /* Bitset of available endpoints */
uint16_t epstalled; /* Bitset of stalled endpoints */
WDOG_ID wdog; /* Supports the restart delay */
struct wdog_s wdog; /* Supports the restart delay */
uint8_t out0data[2][CONFIG_USBDEV_EP0_MAXSIZE];
uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE];
@ -1118,7 +1118,7 @@ static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno)
/* And start (or re-start) the watchdog timer */
wd_start(priv->wdog, RESTART_DELAY,
wd_start(&priv->wdog, RESTART_DELAY,
khci_rqrestart, 1, (wdparm_t)priv);
}
@ -4356,12 +4356,6 @@ static void khci_swinitialize(struct khci_usbdev_s *priv)
priv->epavail = KHCI_ENDP_ALLSET & ~KHCI_ENDP_BIT(EP0);
priv->rwakeup = 1;
/* Initialize the watchdog timer that is used to perform a delayed
* queue restart after recovering from a stall.
*/
priv->wdog = wd_create();
/* Initialize the endpoint list */
for (epno = 0; epno < KHCI_NENDPOINTS; epno++)
@ -4533,7 +4527,7 @@ void arm_usbuninitialize(void)
kinetis_usbpullup(&priv->usbdev, false);
wd_delete(priv->wdog);
wd_cancel(&priv->wdog);
/* Put the hardware in an inactive state */

27
arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
View file

@ -309,8 +309,8 @@ struct lpc17_40_driver_s
uint8_t lp_phyaddr; /* PHY device address */
#endif
uint32_t lp_inten; /* Shadow copy of INTEN register */
WDOG_ID lp_txpoll; /* TX poll timer */
WDOG_ID lp_txtimeout; /* TX timeout timer */
struct wdog_s lp_txpoll; /* TX poll timer */
struct wdog_s lp_txtimeout; /* TX timeout timer */
struct work_s lp_txwork; /* TX work continuation */
struct work_s lp_rxwork; /* RX work continuation */
@ -701,7 +701,7 @@ static int lpc17_40_transmit(struct lpc17_40_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->lp_txtimeout, LPC17_40_TXTIMEOUT,
wd_start(&priv->lp_txtimeout, LPC17_40_TXTIMEOUT,
lpc17_40_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1331,7 +1331,7 @@ static int lpc17_40_interrupt(int irq, void *context, FAR void *arg)
* Cancel the pending Tx timeout
*/
wd_cancel(priv->lp_txtimeout);
wd_cancel(&priv->lp_txtimeout);
/* Disable further Tx interrupts. Tx interrupts may be
* re-enabled again depending upon the actions of
@ -1509,7 +1509,7 @@ static void lpc17_40_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->lp_txpoll, LPC17_40_WDDELAY,
wd_start(&priv->lp_txpoll, LPC17_40_WDDELAY,
lpc17_40_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1764,7 +1764,7 @@ static int lpc17_40_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->lp_txpoll, LPC17_40_WDDELAY,
wd_start(&priv->lp_txpoll, LPC17_40_WDDELAY,
lpc17_40_poll_expiry, 1, (wdparm_t)priv);
/* Finally, make the interface up and enable the Ethernet interrupt at
@ -1809,8 +1809,8 @@ static int lpc17_40_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->lp_txpoll);
wd_cancel(priv->lp_txtimeout);
wd_cancel(&priv->lp_txpoll);
wd_cancel(&priv->lp_txtimeout);
/* Reset the device and mark it as down. */
@ -3307,19 +3307,14 @@ static inline int lpc17_40_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->lp_dev.d_ioctl = lpc17_40_eth_ioctl; /* Handle network IOCTL commands */
#endif
priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */
priv->lp_dev.d_private = priv; /* Used to recover private state from dev */
#if CONFIG_LPC17_40_NINTERFACES > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"
priv->lp_base = ??; /* Ethernet controller base address */
priv->lp_irq = ??; /* Ethernet controller IRQ number */
priv->lp_base = ??; /* Ethernet controller base address */
priv->lp_irq = ??; /* Ethernet controller IRQ number */
#endif
/* Create a watchdog for timing polling for and timing of transmissions */
priv->lp_txpoll = wd_create(); /* Create periodic poll timer */
priv->lp_txtimeout = wd_create(); /* Create TX timeout timer */
/* Reset the Ethernet controller and leave in the ifdown statue. The
* Ethernet controller will be properly re-initialized each time
* lpc17_40_ifup() is called.

16
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View file

@ -112,7 +112,7 @@ struct lpc17_40_i2cdev_s
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* Watchdog to timeout when bus hung */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
@ -238,7 +238,7 @@ static int lpc17_40_i2c_start(struct lpc17_40_i2cdev_s *priv)
priv->state = 0x00;
wd_start(priv->timeout, timeout,
wd_start(&priv->timeout, timeout,
lpc17_40_i2c_timeout, 1, (wdparm_t)priv);
nxsem_wait(&priv->wait);
@ -261,7 +261,7 @@ static void lpc17_40_i2c_stop(struct lpc17_40_i2cdev_s *priv)
priv->base + LPC17_40_I2C_CONSET_OFFSET);
}
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
nxsem_post(&priv->wait);
}
@ -630,11 +630,6 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc17_40_i2c_interrupt, priv);
@ -670,10 +665,9 @@ int lpc17_40_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
nxsem_destroy(&priv->mutex);
nxsem_destroy(&priv->wait);
/* Free the watchdog timer */
/* Cancel the watchdog timer */
wd_delete(priv->timeout);
priv->timeout = NULL;
wd_cancel(&priv->timeout);
/* Disable interrupts */

17
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
View file

@ -250,7 +250,7 @@ struct lpc17_40_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1131,7 +1131,7 @@ static void lpc17_40_endwait(struct lpc17_40_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1495,7 +1495,7 @@ static void lpc17_40_reset(FAR struct sdio_dev_s *dev)
priv->xfrflags = 0; /* Used to synchronize SD card and DMA completion events */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -1914,7 +1914,7 @@ static int lpc17_40_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2344,7 +2344,7 @@ static sdio_eventset_t lpc17_40_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
lpc17_40_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2373,7 +2373,7 @@ static sdio_eventset_t lpc17_40_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
leave_critical_section(flags);
return SDIOWAIT_ERROR;
}
@ -2793,11 +2793,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
#ifdef CONFIG_LPC17_40_SDCARD_DMA
/* Configure the SDCARD DMA request */

16
arch/arm/src/lpc2378/lpc23xx_i2c.c
View file

@ -118,7 +118,7 @@ struct lpc2378_i2cdev_s
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* Watchdog to timeout when bus hung */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
@ -220,11 +220,11 @@ static int lpc2378_i2c_start(struct lpc2378_i2cdev_s *priv)
priv->base + I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + I2C_CONSET_OFFSET);
wd_start(priv->timeout, I2C_TIMEOUT,
wd_start(&priv->timeout, I2C_TIMEOUT,
lpc2378_i2c_timeout, 1, (wdparm_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
return priv->nmsg;
}
@ -590,11 +590,6 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc2378_i2c_interrupt, priv);
@ -630,10 +625,9 @@ int lpc2378_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
nxsem_destroy(&priv->mutex);
nxsem_destroy(&priv->wait);
/* Free the watchdog timer */
/* Cancel the watchdog timer */
wd_delete(priv->timeout);
priv->timeout = NULL;
wd_cancel(&priv->timeout);
/* Disable interrupts */

11
arch/arm/src/lpc31xx/lpc31_i2c.c
View file

@ -91,7 +91,7 @@ struct lpc31_i2cdev_s
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* Watchdog to timeout when bus hung */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
@ -515,7 +515,7 @@ static int i2c_transfer(FAR struct i2c_master_s *dev,
/* Start a watchdog to timeout the transfer if the bus is locked up... */
wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (wdparm_t)priv);
wd_start(&priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (wdparm_t)priv);
/* Wait for the transfer to complete */
@ -524,7 +524,7 @@ static int i2c_transfer(FAR struct i2c_master_s *dev,
nxsem_wait(&priv->wait);
}
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
ret = count - priv->nmsg;
leave_critical_section(flags);
@ -597,11 +597,6 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port)
i2c_hwreset(priv);
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, i2c_interrupt, priv);

25
arch/arm/src/lpc43xx/lpc43_ethernet.c
View file

@ -526,8 +526,8 @@ struct lpc43_ethmac_s
uint8_t ifup : 1; /* true:ifup false:ifdown */
uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
uint8_t fduplex : 1; /* Full (vs. half) duplex */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring work to the work queue */
struct work_s pollwork; /* For deferring work to the work queue */
@ -1117,7 +1117,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, LPC43_TXTIMEOUT,
wd_start(&priv->txtimeout, LPC43_TXTIMEOUT,
lpc43_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1897,7 +1897,7 @@ static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv)
{
/* Cancel the TX timeout */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* And disable further TX interrupts. */
@ -2055,7 +2055,7 @@ static int lpc43_interrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2209,7 +2209,7 @@ static void lpc43_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, LPC43_WDDELAY,
wd_start(&priv->txpoll, LPC43_WDDELAY,
lpc43_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2286,7 +2286,7 @@ static int lpc43_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, LPC43_WDDELAY,
wd_start(&priv->txpoll, LPC43_WDDELAY,
lpc43_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -2329,8 +2329,8 @@ static int lpc43_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the lpc43_ifup() always
@ -3883,12 +3883,7 @@ static inline int lpc43_ethinitialize(void)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = lpc43_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_lpc43ethmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmission */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = &g_lpc43ethmac; /* Used to recover private state from dev */
/* Configure GPIO pins to support Ethernet */

11
arch/arm/src/lpc43xx/lpc43_i2c.c
View file

@ -107,7 +107,7 @@ struct lpc43_i2cdev_s
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* watchdog to timeout when bus hung */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
@ -202,11 +202,11 @@ static int lpc43_i2c_start(struct lpc43_i2cdev_s *priv)
priv->base + LPC43_I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + LPC43_I2C_CONSET_OFFSET);
wd_start(priv->timeout, I2C_TIMEOUT,
wd_start(&priv->timeout, I2C_TIMEOUT,
lpc43_i2c_timeout, 1, (wdparm_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
return priv->nmsg;
}
@ -538,11 +538,6 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc43_i2c_interrupt, priv);

17
arch/arm/src/lpc43xx/lpc43_sdmmc.c
View file

@ -230,7 +230,7 @@ struct lpc43_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -885,7 +885,7 @@ static void lpc43_endwait(struct lpc43_dev_s *priv,
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1297,7 +1297,7 @@ static void lpc43_reset(FAR struct sdio_dev_s *dev)
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -1878,7 +1878,7 @@ static int lpc43_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Mark no transfer in progress */
@ -2313,7 +2313,7 @@ static sdio_eventset_t lpc43_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
lpc43_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2341,7 +2341,7 @@ static sdio_eventset_t lpc43_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
leave_critical_section(flags);
return SDIOWAIT_ERROR;
}
@ -2883,11 +2883,6 @@ FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog != NULL);
/* Configure GPIOs for 4-bit, wide-bus operation */
lpc43_pin_config(GPIO_SD_D0);

25
arch/arm/src/lpc54xx/lpc54_ethernet.c
View file

@ -296,8 +296,8 @@ struct lpc54_ethdriver_s
uint8_t eth_fullduplex : 1; /* 1:Full duplex 0:Half duplex mode */
uint8_t eth_100mbps : 1; /* 1:100mbps 0:10mbps */
uint8_t eth_rxdiscard : 1; /* 1:Discarding Rx data */
WDOG_ID eth_txpoll; /* TX poll timer */
WDOG_ID eth_txtimeout; /* TX timeout timer */
struct wdog_s eth_txpoll; /* TX poll timer */
struct wdog_s eth_txtimeout; /* TX timeout timer */
struct work_s eth_irqwork; /* For deferring interrupt work to the work queue */
struct work_s eth_pollwork; /* For deferring poll work to the work queue */
struct work_s eth_timeoutwork; /* For deferring timeout work to the work queue */
@ -686,7 +686,7 @@ static int lpc54_eth_transmit(struct lpc54_ethdriver_s *priv,
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->eth_txtimeout, LPC54_TXTIMEOUT,
wd_start(&priv->eth_txtimeout, LPC54_TXTIMEOUT,
lpc54_eth_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1322,7 +1322,7 @@ static void lpc54_eth_txdone(struct lpc54_ethdriver_s *priv,
if (txring->tr_inuse == 0)
#endif
{
wd_cancel(priv->eth_txtimeout);
wd_cancel(&priv->eth_txtimeout);
work_cancel(ETHWORK, &priv->eth_timeoutwork);
}
@ -1858,7 +1858,7 @@ static void lpc54_eth_poll_work(void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->eth_txpoll, LPC54_WDDELAY,
wd_start(&priv->eth_txpoll, LPC54_WDDELAY,
lpc54_eth_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2169,7 +2169,7 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->eth_txpoll, LPC54_WDDELAY,
wd_start(&priv->eth_txpoll, LPC54_WDDELAY,
lpc54_eth_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -2211,8 +2211,8 @@ static int lpc54_eth_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->eth_txpoll);
wd_cancel(priv->eth_txtimeout);
wd_cancel(&priv->eth_txpoll);
wd_cancel(&priv->eth_txtimeout);
/* Put the EMAC in its post-reset, non-operational state. This should be
* a known configuration that will guarantee the lpc54_eth_ifup() always
@ -3085,14 +3085,7 @@ int arm_netinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->eth_dev.d_ioctl = lpc54_eth_ioctl; /* Handle network IOCTL commands */
#endif
priv->eth_dev.d_private = (void *)&g_ethdriver; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->eth_txpoll = wd_create(); /* Create periodic poll timer */
priv->eth_txtimeout = wd_create(); /* Create TX timeout timer */
DEBUGASSERT(priv->eth_txpoll != NULL && priv->eth_txtimeout != NULL);
priv->eth_dev.d_private = &g_ethdriver; /* Used to recover private state from dev */
/* Configure GPIO pins to support Ethernet */

11
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View file

@ -128,7 +128,7 @@ struct lpc54_i2cdev_s
struct i2c_master_s dev; /* Generic I2C device */
uintptr_t base; /* Base address of Flexcomm registers */
WDOG_ID timeout; /* Watchdog to timeout when bus hung */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
uint32_t fclock; /* Flexcomm function clock frequency */
@ -476,7 +476,7 @@ static bool lpc54_i2c_nextmsg(struct lpc54_i2cdev_s *priv)
* Cancel any timeout
*/
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
/* Disable further I2C interrupts and return to the IDLE state */
@ -767,7 +767,7 @@ static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev,
/* Set up the transfer timeout */
wd_start(priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT,
wd_start(&priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT,
lpc54_i2c_timeout, 1, (wdparm_t)priv);
/* Initiate the transfer */
@ -1218,11 +1218,6 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
#ifndef CONFIG_I2C_POLLED
/* Attach Interrupt Handler */

17
arch/arm/src/lpc54xx/lpc54_sdmmc.c
View file

@ -234,7 +234,7 @@ struct lpc54_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -885,7 +885,7 @@ static void lpc54_endwait(struct lpc54_dev_s *priv,
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1297,7 +1297,7 @@ static void lpc54_reset(FAR struct sdio_dev_s *dev)
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -1878,7 +1878,7 @@ static int lpc54_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Mark no transfer in progress */
@ -2313,7 +2313,7 @@ static sdio_eventset_t lpc54_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
lpc54_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2341,7 +2341,7 @@ static sdio_eventset_t lpc54_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
leave_critical_section(flags);
return SDIOWAIT_ERROR;
}
@ -2890,11 +2890,6 @@ FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog != NULL);
/* Configure GPIOs for 4-bit, wide-bus operation */
lpc54_gpio_config(GPIO_SD_D0);

25
arch/arm/src/s32k1xx/s32k1xx_enet.c
View file

@ -271,8 +271,8 @@ struct s32k1xx_driver_s
uint8_t txhead; /* The next TX descriptor to use */
uint8_t rxtail; /* The next RX descriptor to use */
uint8_t phyaddr; /* Selected PHY address */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
@ -572,7 +572,7 @@ static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, S32K1XX_TXTIMEOUT,
wd_start(&priv->txtimeout, S32K1XX_TXTIMEOUT,
s32k1xx_txtimeout_expiry, 1, (wdparm_t)priv);
/* Start the TX transfer (if it was not already waiting for buffers) */
@ -921,7 +921,7 @@ static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv)
* canceled.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* Verify that the oldest descriptor descriptor completed */
@ -963,7 +963,7 @@ static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv)
{
/* No.. Cancel the TX timeout and disable further Tx interrupts. */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
regval = getreg32(S32K1XX_ENET_EIMR);
regval &= ~TX_INTERRUPTS;
@ -1250,7 +1250,7 @@ static void s32k1xx_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again in any case */
wd_start(priv->txpoll, S32K1XX_WDDELAY,
wd_start(&priv->txpoll, S32K1XX_WDDELAY,
s32k1xx_polltimer_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1382,7 +1382,7 @@ static int s32k1xx_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Set and activate a timer process */
wd_start(priv->txpoll, S32K1XX_WDDELAY,
wd_start(&priv->txpoll, S32K1XX_WDDELAY,
s32k1xx_polltimer_expiry, 1, (wdparm_t)priv);
/* Clear all pending ENET interrupt */
@ -1470,8 +1470,8 @@ static int s32k1xx_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the s32k1xx_ifup() always
@ -2605,12 +2605,7 @@ int s32k1xx_netinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = s32k1xx_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_enet; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = g_enet; /* Used to recover private state from dev */
#ifdef CONFIG_NET_ETHERNET
/* Determine a semi-unique MAC address from MCU UID

16
arch/arm/src/s32k1xx/s32k1xx_flexcan.c
View file

@ -295,7 +295,7 @@ struct s32k1xx_driver_s
uint32_t base; /* FLEXCAN base address */
bool bifup; /* true:ifup false:ifdown */
#ifdef TX_TIMEOUT_WQ
WDOG_ID txtimeout[TXMBCOUNT]; /* TX timeout timer */
struct wdog_s txtimeout[TXMBCOUNT]; /* TX timeout timer */
#endif
struct work_s irqwork; /* For deferring interrupt work to the wq */
struct work_s pollwork; /* For deferring poll work to the work wq */
@ -752,7 +752,7 @@ static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv)
if (timeout >= 0)
{
wd_start(priv->txtimeout[mbi], timeout + 1,
wd_start(&priv->txtimeout[mbi], timeout + 1,
s32k1xx_txtimeout_expiry, 1, (wdparm_t)priv);
}
#endif
@ -1004,7 +1004,7 @@ static void s32k1xx_txdone(FAR void *arg)
* corresponding watchdog can be canceled.
*/
wd_cancel(priv->txtimeout[mbi]);
wd_cancel(&priv->txtimeout[mbi]);
#endif
}
@ -1861,15 +1861,7 @@ int s32k1xx_caninitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = s32k1xx_ioctl; /* Support CAN ioctl() calls */
#endif
priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */
#ifdef TX_TIMEOUT_WQ
for (i = 0; i < TXMBCOUNT; i++)
{
priv->txtimeout[i] = wd_create(); /* Create TX timeout timer */
}
#endif
priv->dev.d_private = priv; /* Used to recover private state from dev */
priv->rx = (struct mb_s *)(priv->base + S32K1XX_CAN_MB_OFFSET);
priv->tx = (struct mb_s *)(priv->base + S32K1XX_CAN_MB_OFFSET +
(sizeof(struct mb_s) * RXMBCOUNT));

40
arch/arm/src/sam34/sam_emac.c
View file

@ -271,8 +271,8 @@
struct sam_emac_s
{
uint8_t ifup : 1; /* true:ifup false:ifdown */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -814,7 +814,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, SAM_TXTIMEOUT,
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, 1, (wdparm_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
@ -1675,7 +1675,7 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1792,7 +1792,7 @@ static void sam_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1891,7 +1891,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
/* Enable the EMAC interrupt */
@ -1930,8 +1930,8 @@ static int sam_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the sam_ifup() always
@ -3682,23 +3682,7 @@ void arm_netinitialize(void)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_emac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nerr("ERROR: Failed to create periodic poll timer\n");
return;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed to create periodic poll timer\n");
goto errout_with_txpoll;
}
priv->dev.d_private = &g_emac; /* Used to recover private state from dev */
/* Configure PIO pins to support EMAC MII */
@ -3710,7 +3694,7 @@ void arm_netinitialize(void)
if (ret < 0)
{
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
return;
}
/* Attach the IRQ to the driver. It will not be enabled at the AIC until
@ -3751,10 +3735,6 @@ void arm_netinitialize(void)
errout_with_buffers:
sam_buffer_free(priv);
errout_with_txtimeout:
wd_delete(priv->txtimeout);
errout_with_txpoll:
wd_delete(priv->txpoll);
}
#endif /* CONFIG_NET && CONFIG_SAM34_EMAC */

17
arch/arm/src/sam34/sam_hsmci.c
View file

@ -312,7 +312,7 @@ struct sam_dev_s
uint32_t cmdrmask; /* Interrupt enables for this
* particular cmd/response */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
#ifdef CONFIG_SAM34_DMAC0
bool dmabusy; /* TRUE: DMA is in progress */
#endif
@ -1128,7 +1128,7 @@ static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent)
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts and save wakeup event */
@ -1463,7 +1463,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
priv->dmabusy = false; /* No DMA in progress */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -1890,7 +1890,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Make sure that the DMA is stopped (it will be stopped automatically
* on normal transfers, but not necessarily when the transfer terminates
@ -2328,7 +2328,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
sam_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2356,7 +2356,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
* disable all event, and return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
sam_disablexfrints(priv);
sam_disablewaitints(priv, SDIOWAIT_ERROR);
return SDIOWAIT_ERROR;
@ -2721,11 +2721,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
#ifdef CONFIG_SAM34_DMAC0
/* Allocate a DMA channel. A FIFO size of 8 is sufficient. */

13
arch/arm/src/sam34/sam_spi.c
View file

@ -179,7 +179,7 @@ struct sam_spics_s
#ifdef CONFIG_SAM34_SPI_DMA
bool candma; /* DMA is supported */
sem_t dmawait; /* Used to wait for DMA completion */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
int result; /* DMA result */
DMA_HANDLE rxdma; /* SPI RX DMA handle */
DMA_HANDLE txdma; /* SPI TX DMA handle */
@ -781,7 +781,7 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1589,7 +1589,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&spics->dmadog, DMA_TIMEOUT_TICKS,
spi_dmatimeout, 1, (wdparm_t)spics);
if (ret < 0)
{
@ -1602,7 +1602,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Check if we were awakened by an error of some kind. */
@ -1890,11 +1890,6 @@ struct spi_dev_s *sam_spibus_initialize(int port)
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
spics->dmadog = wd_create();
DEBUGASSERT(spics->dmadog);
#endif
spi_dumpregs(spi, "After initialization");

18
arch/arm/src/sam34/sam_twi.c
View file

@ -121,7 +121,7 @@ struct twi_dev_s
sem_t exclsem; /* Only one thread can access at a time */
sem_t waitsem; /* Wait for TWI transfer completion */
WDOG_ID timeout; /* Watchdog to recover from bus hangs */
struct wdog_s timeout; /* Watchdog to recover from bus hangs */
volatile int result; /* The result of the transfer */
volatile int xfrd; /* Number of bytes transfers */
@ -376,7 +376,7 @@ static int twi_wait(struct twi_dev_s *priv)
/* Start a timeout to avoid hangs */
wd_start(priv->timeout, TWI_TIMEOUT, twi_timeout, 1, (wdparm_t)priv);
wd_start(&priv->timeout, TWI_TIMEOUT, twi_timeout, 1, (wdparm_t)priv);
/* Wait for either the TWI transfer or the timeout to complete */
@ -388,7 +388,7 @@ static int twi_wait(struct twi_dev_s *priv)
if (ret < 0)
{
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
return ret;
}
}
@ -413,7 +413,7 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
{
/* Cancel any pending timeout */
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
/* Disable any further TWI interrupts */
@ -983,11 +983,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
/* Configure and enable the TWI hardware */
priv->pid = pid;
@ -1027,10 +1022,9 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
nxsem_destroy(&priv->exclsem);
nxsem_destroy(&priv->waitsem);
/* Free the watchdog timer */
/* Cancel the watchdog timer */
wd_delete(priv->timeout);
priv->timeout = NULL;
wd_cancel(&priv->timeout);
/* Detach Interrupt Handler */

43
arch/arm/src/sama5/sam_emaca.c
View file

@ -275,8 +275,8 @@
struct sam_emac_s
{
uint8_t ifup : 1; /* true:ifup false:ifdown */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -822,7 +822,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, SAM_TXTIMEOUT,
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, 1, (wdparm_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
@ -1711,7 +1711,7 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1826,7 +1826,7 @@ static void sam_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1925,7 +1925,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
/* Enable the EMAC interrupt */
@ -1964,8 +1964,8 @@ static int sam_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the sam_ifup() always
@ -3719,25 +3719,7 @@ int sam_emac_initialize(void)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_emac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
priv->dev.d_private = &g_emac; /* Used to recover private state from dev */
/* Configure PIO pins to support EMAC */
@ -3749,7 +3731,7 @@ int sam_emac_initialize(void)
if (ret < 0)
{
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
return ret;
}
/* Attach the IRQ to the driver. It will not be enabled at the AIC until
@ -3790,11 +3772,6 @@ int sam_emac_initialize(void)
errout_with_buffers:
sam_buffer_free(priv);
errout_with_txtimeout:
wd_delete(priv->txtimeout);
errout_with_txpoll:
wd_delete(priv->txpoll);
errout:
return ret;
}

41
arch/arm/src/sama5/sam_emacb.c
View file

@ -413,8 +413,8 @@ struct sam_emacattr_s
struct sam_emac_s
{
uint8_t ifup : 1; /* true:ifup false:ifdown */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -1163,7 +1163,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, SAM_TXTIMEOUT,
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, 1, (wdparm_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
@ -2076,7 +2076,7 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2191,7 +2191,7 @@ static void sam_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2298,7 +2298,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
/* Enable the EMAC interrupt */
@ -2337,8 +2337,8 @@ static int sam_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the sam_ifup() always
@ -4416,24 +4416,6 @@ int sam_emac_initialize(int intf)
priv->dev.d_private = priv; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
/* Configure PIO pins to support EMAC */
sam_ethgpioconfig(priv);
@ -4444,7 +4426,7 @@ int sam_emac_initialize(int intf)
if (ret < 0)
{
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
return ret;
}
/* Attach the IRQ to the driver. It will not be enabled at the AIC until
@ -4485,11 +4467,6 @@ int sam_emac_initialize(int intf)
errout_with_buffers:
sam_buffer_free(priv);
errout_with_txtimeout:
wd_delete(priv->txtimeout);
errout_with_txpoll:
wd_delete(priv->txpoll);
errout:
return ret;
}

43
arch/arm/src/sama5/sam_gmac.c
View file

@ -201,8 +201,8 @@
struct sam_gmac_s
{
uint8_t ifup : 1; /* true:ifup false:ifdown */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -764,7 +764,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, SAM_TXTIMEOUT,
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, 1, (wdparm_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
@ -1695,7 +1695,7 @@ static int sam_gmac_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1810,7 +1810,7 @@ static void sam_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1912,7 +1912,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
/* Enable the GMAC interrupt */
@ -1951,8 +1951,8 @@ static int sam_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the GMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the sam_ifup() always
@ -3825,25 +3825,7 @@ int sam_gmac_initialize(void)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_gmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
priv->dev.d_private = &g_gmac; /* Used to recover private state from dev */
/* Configure PIO pins to support GMAC */
@ -3855,7 +3837,7 @@ int sam_gmac_initialize(void)
if (ret < 0)
{
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
return ret;
}
/* Attach the IRQ to the driver. It will not be enabled at the AIC until
@ -3896,11 +3878,6 @@ int sam_gmac_initialize(void)
errout_with_buffers:
sam_buffer_free(priv);
errout_with_txtimeout:
wd_delete(priv->txtimeout);
errout_with_txpoll:
wd_delete(priv->txpoll);
errout:
return ret;
}

29
arch/arm/src/sama5/sam_hsmci.c
View file

@ -398,7 +398,7 @@ struct sam_dev_s
uint32_t cmdrmask; /* Interrupt enables for this
* particular cmd/response */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
uint8_t hsmci; /* HSMCI (0, 1, or 2) */
volatile bool dmabusy; /* TRUE: DMA transfer is in progress */
volatile bool xfrbusy; /* TRUE: Transfer is in progress */
@ -1366,7 +1366,7 @@ static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent)
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts and save wakeup event */
@ -1724,19 +1724,19 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
/* Reset data */
priv->waitevents = 0; /* Set of events to be waited for */
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
priv->dmabusy = false; /* No DMA in progress */
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
priv->waitevents = 0; /* Set of events to be waited for */
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
priv->dmabusy = false; /* No DMA in progress */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
priv->xfrmask = 0; /* Interrupt enables for data transfer */
priv->xfrmask = 0; /* Interrupt enables for data transfer */
/* DMA data transfer support */
priv->widebus = false; /* Required for DMA support */
priv->widebus = false; /* Required for DMA support */
leave_critical_section(flags);
}
@ -2314,7 +2314,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Make sure that the DMA is stopped (it will be stopped automatically
* on normal transfers, but not necessarily when the transfer terminates
@ -2755,7 +2755,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
}
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
sam_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2783,7 +2783,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
* disable all event, and return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
sam_disablexfrints(priv);
sam_disablewaitints(priv, SDIOWAIT_ERROR);
return SDIOWAIT_ERROR;
@ -3346,11 +3346,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
/* Initialize the callbacks */
memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s));

15
arch/arm/src/sama5/sam_sdmmc.c
View file

@ -163,7 +163,7 @@ struct sam_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1216,7 +1216,7 @@ static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent)
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1573,7 +1573,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2479,7 +2479,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2912,7 +2912,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
sam_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
@ -3618,11 +3618,6 @@ FAR struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
switch (priv->addr)
{
case SAM_SDMMC0_VBASE:

13
arch/arm/src/sama5/sam_spi.c
View file

@ -170,7 +170,7 @@ struct sam_spics_s
#ifdef CONFIG_SAMA5_SPI_DMA
bool candma; /* DMA is supported */
sem_t dmawait; /* Used to wait for DMA completion */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
int result; /* DMA result */
DMA_HANDLE rxdma; /* SPI RX DMA handle */
DMA_HANDLE txdma; /* SPI TX DMA handle */
@ -769,7 +769,7 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1517,7 +1517,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&spics->dmadog, DMA_TIMEOUT_TICKS,
spi_dmatimeout, 1, (wdparm_t)spics);
if (ret < 0)
{
@ -1530,7 +1530,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Check if we were awakened by an error of some kind. */
@ -1819,11 +1819,6 @@ struct spi_dev_s *sam_spibus_initialize(int port)
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
spics->dmadog = wd_create();
DEBUGASSERT(spics->dmadog);
#endif
spi_dumpregs(spi, "After initialization");

40
arch/arm/src/sama5/sam_ssc.c
View file

@ -425,7 +425,7 @@ struct sam_buffer_s
struct sam_transport_s
{
DMA_HANDLE dma; /* SSC DMA handle */
WDOG_ID dog; /* Watchdog that handles DMA timeouts */
struct wdog_s dog; /* Watchdog that handles DMA timeouts */
sq_queue_t pend; /* A queue of pending transfers */
sq_queue_t act; /* A queue of active transfers */
sq_queue_t done; /* A queue of completed transfers */
@ -1344,7 +1344,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
ret = wd_start(priv->rx.dog, timeout,
ret = wd_start(&priv->rx.dog, timeout,
ssc_rxdma_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1575,7 +1575,7 @@ static void ssc_rxdma_callback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(priv->rx.dog);
wd_cancel(&priv->rx.dog);
/* Sample DMA registers at the time of the DMA completion */
@ -1761,7 +1761,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
ret = wd_start(priv->tx.dog, timeout,
ret = wd_start(&priv->tx.dog, timeout,
ssc_txdma_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1979,7 +1979,7 @@ static void ssc_txdma_callback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(priv->tx.dog);
wd_cancel(&priv->tx.dog);
/* Sample DMA registers at the time of the DMA completion */
@ -3007,15 +3007,6 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
i2serr("ERROR: Failed to allocate the RX DMA channel\n");
goto errout;
}
/* Create a watchdog time to catch RX DMA timeouts */
priv->rx.dog = wd_create();
if (!priv->rx.dog)
{
i2serr("ERROR: Failed to create the RX DMA watchdog\n");
goto errout;
}
}
#endif
@ -3030,15 +3021,6 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
i2serr("ERROR: Failed to allocate the TX DMA channel\n");
goto errout;
}
/* Create a watchdog time to catch TX DMA timeouts */
priv->tx.dog = wd_create();
if (!priv->tx.dog)
{
i2serr("ERROR: Failed to create the TX DMA watchdog\n");
goto errout;
}
}
#endif
@ -3070,11 +3052,7 @@ errout:
static void ssc_dma_free(struct sam_ssc_s *priv)
{
#ifdef SSC_HAVE_TX
if (priv->tx.dog)
{
wd_delete(priv->tx.dog);
}
wd_cancel(&priv->tx.dog);
if (priv->tx.dma)
{
sam_dmafree(priv->tx.dma);
@ -3082,11 +3060,7 @@ static void ssc_dma_free(struct sam_ssc_s *priv)
#endif
#ifdef SSC_HAVE_RX
if (priv->rx.dog)
{
wd_delete(priv->rx.dog);
}
wd_cancel(&priv->rx.dog);
if (priv->rx.dma)
{
sam_dmafree(priv->rx.dma);

11
arch/arm/src/sama5/sam_tsd.c
View file

@ -179,7 +179,7 @@ struct sam_tsd_s
struct sam_adc_s *adc; /* ADC device handle */
struct work_s work; /* Supports the interrupt handling "bottom half" */
struct sam_sample_s sample; /* Last sampled touch point data */
WDOG_ID wdog; /* Poll the position while the pen is down */
struct wdog_s wdog; /* Poll the position while the pen is down */
/* The following is a list if poll structures of threads waiting for
* driver events. The 'struct pollfd' reference for each open is also
@ -586,7 +586,7 @@ static void sam_tsd_bottomhalf(void *arg)
* this case; we rely on the timer expiry to get us going again.
*/
wd_start(priv->wdog, TSD_WDOG_DELAY,
wd_start(&priv->wdog, TSD_WDOG_DELAY,
sam_tsd_expiry, 1, (wdparm_t)priv);
ier = 0;
goto ignored;
@ -665,7 +665,7 @@ static void sam_tsd_bottomhalf(void *arg)
/* Continue to sample the position while the pen is down */
wd_start(priv->wdog, TSD_WDOG_DELAY,
wd_start(&priv->wdog, TSD_WDOG_DELAY,
sam_tsd_expiry, 1, (wdparm_t)priv);
/* Check the thresholds. Bail if (1) this is not the first
@ -774,7 +774,7 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv)
* while the pen remains down.
*/
wd_cancel(priv->wdog);
wd_cancel(&priv->wdog);
/* Disable further touchscreen interrupts. Touchscreen interrupts will be
* re-enabled after the worker thread executes.
@ -1590,7 +1590,7 @@ static void sam_tsd_uninitialize(struct sam_tsd_s *priv)
* while the pen remains down.
*/
wd_cancel(priv->wdog);
wd_cancel(&priv->wdog);
/* Disable further touchscreen interrupts. Touchscreen interrupts will be
* re-enabled after the worker thread executes.
@ -1655,7 +1655,6 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
memset(priv, 0, sizeof(struct sam_tsd_s));
priv->adc = adc; /* Save the ADC device handle */
priv->wdog = wd_create(); /* Create a watchdog timer */
priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */
priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */

30
arch/arm/src/sama5/sam_twi.c
View file

@ -161,7 +161,7 @@ struct twi_dev_s
sem_t exclsem; /* Only one thread can access at a time */
sem_t waitsem; /* Wait for TWI transfer completion */
WDOG_ID timeout; /* Watchdog to recover from bus hangs */
struct wdog_s timeout; /* Watchdog to recover from bus hangs */
volatile int result; /* The result of the transfer */
volatile int xfrd; /* Number of bytes transfers */
@ -480,7 +480,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
* a TWI transfer stalls.
*/
wd_start(priv->timeout, timeout, twi_timeout, 1, (wdparm_t)priv);
wd_start(&priv->timeout, timeout, twi_timeout, 1, (wdparm_t)priv);
/* Wait for either the TWI transfer or the timeout to complete */
@ -493,7 +493,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
if (ret < 0)
{
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
return ret;
}
}
@ -518,7 +518,7 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
{
/* Cancel any pending timeout */
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
/* Disable any further TWI interrupts */
@ -1257,22 +1257,13 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
flags = enter_critical_section();
/* Allocate a watchdog timer */
priv->timeout = wd_create();
if (priv->timeout == NULL)
{
ierr("ERROR: Failed to allocate a timer\n");
goto errout_with_irq;
}
/* Attach Interrupt Handler */
ret = irq_attach(priv->attr->irq, twi_interrupt, priv);
if (ret < 0)
{
ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq);
goto errout_with_wdog;
goto errout_with_lock;
}
/* Initialize the TWI driver structure */
@ -1296,11 +1287,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
leave_critical_section(flags);
return &priv->dev;
errout_with_wdog:
wd_delete(priv->timeout);
priv->timeout = NULL;
errout_with_irq:
errout_with_lock:
leave_critical_section(flags);
return NULL;
}
@ -1328,10 +1315,9 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
nxsem_destroy(&priv->exclsem);
nxsem_destroy(&priv->waitsem);
/* Free the watchdog timer */
/* Cancel the watchdog timer */
wd_delete(priv->timeout);
priv->timeout = NULL;
wd_cancel(&priv->timeout);
/* Detach Interrupt Handler */

43
arch/arm/src/samd5e5/sam_gmac.c
View file

@ -199,8 +199,8 @@
struct sam_gmac_s
{
uint8_t ifup : 1; /* true:ifup false:ifdown */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -753,7 +753,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, SAM_TXTIMEOUT,
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, 1, (wdparm_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
@ -1663,7 +1663,7 @@ static int sam_gmac_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1778,7 +1778,7 @@ static void sam_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -1880,7 +1880,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
/* Enable the GMAC interrupt */
@ -1919,8 +1919,8 @@ static int sam_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the GMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the sam_ifup() always
@ -3764,25 +3764,7 @@ int sam_gmac_initialize(void)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_gmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
priv->dev.d_private = &g_gmac; /* Used to recover private state from dev */
/* Configure PIO pins to support GMAC */
@ -3794,7 +3776,7 @@ int sam_gmac_initialize(void)
if (ret < 0)
{
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
return ret;
}
/* Attach the IRQ to the driver. It will not be enabled at the AIC until
@ -3836,11 +3818,6 @@ int sam_gmac_initialize(void)
errout_with_buffers:
sam_buffer_free(priv);
errout_with_txtimeout:
wd_delete(priv->txtimeout);
errout_with_txpoll:
wd_delete(priv->txpoll);
errout:
return ret;
}

41
arch/arm/src/samv7/sam_emac.c
View file

@ -529,8 +529,8 @@ struct sam_queue_s
struct sam_emac_s
{
uint8_t ifup : 1; /* true:ifup false:ifdown */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring work to the work queue */
struct work_s pollwork; /* For deferring work to the work queue */
@ -1468,7 +1468,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, SAM_TXTIMEOUT,
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, 1, (wdparm_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
@ -2536,7 +2536,7 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2653,7 +2653,7 @@ static void sam_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2771,7 +2771,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
wd_start(&priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (wdparm_t)priv);
/* Enable the EMAC interrupt */
@ -2810,8 +2810,8 @@ static int sam_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the sam_ifup() always
@ -5049,24 +5049,6 @@ int sam_emac_initialize(int intf)
priv->dev.d_private = priv; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
/* Configure PIO pins to support EMAC */
sam_ethgpioconfig(priv);
@ -5077,7 +5059,7 @@ int sam_emac_initialize(int intf)
if (ret < 0)
{
nerr("ERROR: sam_buffer_allocate failed: %d\n", ret);
goto errout_with_txtimeout;
return ret;
}
/* Attach the IRQ to the driver. It will not be enabled at the AIC until
@ -5118,11 +5100,6 @@ int sam_emac_initialize(int intf)
errout_with_buffers:
sam_buffer_free(priv);
errout_with_txtimeout:
wd_delete(priv->txtimeout);
errout_with_txpoll:
wd_delete(priv->txpoll);
errout:
return ret;
}

29
arch/arm/src/samv7/sam_hsmci.c
View file

@ -333,7 +333,7 @@ struct sam_dev_s
uint32_t cmdrmask; /* Interrupt enables for this
* particular cmd/response */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
uint8_t hsmci; /* HSMCI (0, 1, or 2) */
volatile bool dmabusy; /* TRUE: DMA transfer is in progress */
volatile bool xfrbusy; /* TRUE: Transfer is in progress */
@ -1302,7 +1302,7 @@ static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent)
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts and save wakeup event */
@ -1709,19 +1709,19 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
/* Reset data */
priv->waitevents = 0; /* Set of events to be waited for */
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
priv->dmabusy = false; /* No DMA in progress */
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
priv->waitevents = 0; /* Set of events to be waited for */
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
priv->dmabusy = false; /* No DMA in progress */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
priv->xfrmask = 0; /* Interrupt enables for data transfer */
priv->xfrmask = 0; /* Interrupt enables for data transfer */
/* DMA data transfer support */
priv->widebus = false; /* Required for DMA support */
priv->widebus = false; /* Required for DMA support */
leave_critical_section(flags);
}
@ -2357,7 +2357,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Make sure that the DMA is stopped (it will be stopped automatically
* on normal transfers, but not necessarily when the transfer terminates
@ -2803,7 +2803,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
}
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
sam_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2831,7 +2831,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
* disable all event, and return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
sam_disablexfrints(priv);
sam_disablewaitints(priv, SDIOWAIT_ERROR);
return SDIOWAIT_ERROR;
@ -3380,11 +3380,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
/* Initialize the callbacks */
memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s));

25
arch/arm/src/samv7/sam_qspi.c
View file

@ -192,7 +192,7 @@ struct sam_qspidev_s
uint8_t rxintf; /* RX hardware interface number */
uint8_t txintf; /* TX hardware interface number */
sem_t dmawait; /* Used to wait for DMA completion */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
int result; /* DMA result */
DMA_HANDLE dmach; /* QSPI DMA handle */
#endif
@ -635,7 +635,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -890,7 +890,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&priv->dmadog, DMA_TIMEOUT_TICKS,
qspi_dma_timeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -903,7 +903,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Check if we were awakened by an error of some kind. */
@ -1798,15 +1798,6 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
priv->dmadog = wd_create();
if (priv->dmadog == NULL)
{
spierr("ERROR: Failed to create wdog\n");
goto errout_with_dmahandles;
}
#endif
#ifdef QSPI_USE_INTERRUPTS
@ -1816,7 +1807,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
if (ret < 0)
{
spierr("ERROR: Failed to attach irq %d\n", priv->irq);
goto errout_with_dmadog;
goto errout_with_dmawait;
}
#endif
@ -1845,14 +1836,10 @@ errout_with_irq:
#ifdef QSPI_USE_INTERRUPTS
irq_detach(priv->irq);
errout_with_dmadog:
errout_with_dmawait:
#endif
#ifdef CONFIG_SAMV7_QSPI_DMA
wd_delete(priv->dmadog);
errout_with_dmahandles:
nxsem_destroy(&priv->dmawait);
if (priv->dmach)
{
sam_dmafree(priv->dmach);

13
arch/arm/src/samv7/sam_spi.c
View file

@ -168,7 +168,7 @@ struct sam_spics_s
#ifdef CONFIG_SAMV7_SPI_DMA
bool candma; /* DMA is supported */
sem_t dmawait; /* Used to wait for DMA completion */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
int result; /* DMA result */
DMA_HANDLE rxdma; /* SPI RX DMA handle */
DMA_HANDLE txdma; /* SPI TX DMA handle */
@ -810,7 +810,7 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1864,7 +1864,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&spics->dmadog, DMA_TIMEOUT_TICKS,
spi_dmatimeout, 1, (wdparm_t)spics);
if (ret < 0)
{
@ -1877,7 +1877,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Check if we were awakened by an error of some kind. */
@ -2175,11 +2175,6 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
spics->dmadog = wd_create();
DEBUGASSERT(spics->dmadog);
#endif
spi_dumpregs(spi, "After initialization");

40
arch/arm/src/samv7/sam_ssc.c
View file

@ -400,7 +400,7 @@ struct sam_buffer_s
struct sam_transport_s
{
DMA_HANDLE dma; /* SSC DMA handle */
WDOG_ID dog; /* Watchdog that handles DMA timeouts */
struct wdog_s dog; /* Watchdog that handles DMA timeouts */
sq_queue_t pend; /* A queue of pending transfers */
sq_queue_t act; /* A queue of active transfers */
sq_queue_t done; /* A queue of completed transfers */
@ -1321,7 +1321,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
ret = wd_start(priv->rx.dog, timeout,
ret = wd_start(&priv->rx.dog, timeout,
ssc_rxdma_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1552,7 +1552,7 @@ static void ssc_rxdma_callback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(priv->rx.dog);
wd_cancel(&priv->rx.dog);
/* Sample DMA registers at the time of the DMA completion */
@ -1742,7 +1742,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
ret = wd_start(priv->tx.dog, timeout,
ret = wd_start(&priv->tx.dog, timeout,
ssc_txdma_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1960,7 +1960,7 @@ static void ssc_txdma_callback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(priv->tx.dog);
wd_cancel(&priv->tx.dog);
/* Sample DMA registers at the time of the DMA completion */
@ -2990,15 +2990,6 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
i2serr("ERROR: Failed to allocate the RX DMA channel\n");
goto errout;
}
/* Create a watchdog time to catch RX DMA timeouts */
priv->rx.dog = wd_create();
if (!priv->rx.dog)
{
i2serr("ERROR: Failed to create the RX DMA watchdog\n");
goto errout;
}
}
#endif
@ -3013,15 +3004,6 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
i2serr("ERROR: Failed to allocate the TX DMA channel\n");
goto errout;
}
/* Create a watchdog time to catch TX DMA timeouts */
priv->tx.dog = wd_create();
if (!priv->tx.dog)
{
i2serr("ERROR: Failed to create the TX DMA watchdog\n");
goto errout;
}
}
#endif
@ -3053,11 +3035,7 @@ errout:
static void ssc_dma_free(struct sam_ssc_s *priv)
{
#ifdef SSC_HAVE_TX
if (priv->tx.dog)
{
wd_delete(priv->tx.dog);
}
wd_cancel(&priv->tx.dog);
if (priv->tx.dma)
{
sam_dmafree(priv->tx.dma);
@ -3065,11 +3043,7 @@ static void ssc_dma_free(struct sam_ssc_s *priv)
#endif
#ifdef SSC_HAVE_RX
if (priv->rx.dog)
{
wd_delete(priv->rx.dog);
}
wd_cancel(&priv->rx.dog);
if (priv->rx.dma)
{
sam_dmafree(priv->rx.dma);

30
arch/arm/src/samv7/sam_twihs.c
View file

@ -160,7 +160,7 @@ struct twi_dev_s
sem_t exclsem; /* Only one thread can access at a time */
sem_t waitsem; /* Wait for TWIHS transfer completion */
WDOG_ID timeout; /* Watchdog to recover from bus hangs */
struct wdog_s timeout; /* Watchdog to recover from bus hangs */
volatile int result; /* The result of the transfer */
volatile int xfrd; /* Number of bytes transfers */
@ -484,7 +484,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
* a TWIHS transfer stalls.
*/
wd_start(priv->timeout, (timeout * size),
wd_start(&priv->timeout, (timeout * size),
twi_timeout, 1, (wdparm_t)priv);
/* Wait for either the TWIHS transfer or the timeout to complete */
@ -498,7 +498,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
if (ret < 0)
{
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
return ret;
}
}
@ -543,7 +543,7 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
{
/* Cancel any pending timeout */
wd_cancel(priv->timeout);
wd_cancel(&priv->timeout);
/* Disable any further TWIHS interrupts */
@ -1425,22 +1425,13 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
priv->attr = attr;
/* Allocate a watchdog timer */
priv->timeout = wd_create();
if (priv->timeout == NULL)
{
ierr("ERROR: Failed to allocate a timer\n");
goto errout_with_irq;
}
/* Attach Interrupt Handler */
ret = irq_attach(priv->attr->irq, twi_interrupt, priv);
if (ret < 0)
{
ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq);
goto errout_with_wdog;
goto errout_with_lock;
}
/* Initialize the TWIHS driver structure */
@ -1466,11 +1457,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
leave_critical_section(flags);
return &priv->dev;
errout_with_wdog:
wd_delete(priv->timeout);
priv->timeout = NULL;
errout_with_irq:
errout_with_lock:
priv->refs--;
leave_critical_section(flags);
return NULL;
@ -1513,10 +1500,9 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
nxsem_destroy(&priv->exclsem);
nxsem_destroy(&priv->waitsem);
/* Free the watchdog timer */
/* Cancel the watchdog timer */
wd_delete(priv->timeout);
priv->timeout = NULL;
wd_cancel(&priv->timeout);
/* Detach Interrupt Handler */

25
arch/arm/src/stm32/stm32_eth.c
View file

@ -632,8 +632,8 @@ struct stm32_ethmac_s
uint8_t ifup : 1; /* true:ifup false:ifdown */
uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
uint8_t fduplex : 1; /* Full (vs. half) duplex */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -1228,7 +1228,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, STM32_TXTIMEOUT,
wd_start(&priv->txtimeout, STM32_TXTIMEOUT,
stm32_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -2003,7 +2003,7 @@ static void stm32_txdone(FAR struct stm32_ethmac_s *priv)
{
/* Cancel the TX timeout */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* And disable further TX interrupts. */
@ -2165,7 +2165,7 @@ static int stm32_interrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2317,7 +2317,7 @@ static void stm32_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2395,7 +2395,7 @@ static int stm32_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -2440,8 +2440,8 @@ static int stm32_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the stm32_ifup() always
@ -4108,12 +4108,7 @@ int stm32_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = g_stm32ethmac; /* Used to recover private state from dev */
/* Configure GPIO pins to support Ethernet */

40
arch/arm/src/stm32/stm32_i2s.c
View file

@ -275,7 +275,7 @@ struct stm32_buffer_s
struct stm32_transport_s
{
DMA_HANDLE dma; /* I2S DMA handle */
WDOG_ID dog; /* Watchdog that handles DMA timeouts */
struct wdog_s dog; /* Watchdog that handles DMA timeouts */
sq_queue_t pend; /* A queue of pending transfers */
sq_queue_t act; /* A queue of active transfers */
sq_queue_t done; /* A queue of completed transfers */
@ -1095,7 +1095,7 @@ static int i2s_rxdma_setup(struct stm32_i2s_s *priv)
if (!notimeout)
{
ret = wd_start(priv->rx.dog, timeout,
ret = wd_start(&priv->rx.dog, timeout,
i2s_rxdma_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1320,7 +1320,7 @@ static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->rx.dog);
wd_cancel(&priv->rx.dog);
/* Sample DMA registers at the time of the DMA completion */
@ -1495,7 +1495,7 @@ static int i2s_txdma_setup(struct stm32_i2s_s *priv)
if (!notimeout)
{
ret = wd_start(priv->tx.dog, timeout,
ret = wd_start(&priv->tx.dog, timeout,
i2s_txdma_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1707,7 +1707,7 @@ static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->tx.dog);
wd_cancel(&priv->tx.dog);
/* Sample DMA registers at the time of the DMA completion */
@ -2380,15 +2380,6 @@ static int i2s_dma_allocate(struct stm32_i2s_s *priv)
i2serr("ERROR: Failed to allocate the RX DMA channel\n");
goto errout;
}
/* Create a watchdog time to catch RX DMA timeouts */
priv->rx.dog = wd_create();
if (!priv->rx.dog)
{
i2serr("ERROR: Failed to create the RX DMA watchdog\n");
goto errout;
}
}
#endif
@ -2403,15 +2394,6 @@ static int i2s_dma_allocate(struct stm32_i2s_s *priv)
i2serr("ERROR: Failed to allocate the TX DMA channel\n");
goto errout;
}
/* Create a watchdog time to catch TX DMA timeouts */
priv->tx.dog = wd_create();
if (!priv->tx.dog)
{
i2serr("ERROR: Failed to create the TX DMA watchdog\n");
goto errout;
}
}
#endif
@ -2443,11 +2425,7 @@ errout:
static void i2s_dma_free(struct stm32_i2s_s *priv)
{
#ifdef I2S_HAVE_TX
if (priv->tx.dog)
{
wd_delete(priv->tx.dog);
}
wd_cancel(&priv->tx.dog);
if (priv->tx.dma)
{
stm32_dmafree(priv->tx.dma);
@ -2455,11 +2433,7 @@ static void i2s_dma_free(struct stm32_i2s_s *priv)
#endif
#ifdef I2S_HAVE_RX
if (priv->rx.dog)
{
wd_delete(priv->rx.dog);
}
wd_cancel(&priv->rx.dog);
if (priv->rx.dma)
{
stm32_dmafree(priv->rx.dma);

17
arch/arm/src/stm32/stm32_sdio.c
View file

@ -307,7 +307,7 @@ struct stm32_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1244,7 +1244,7 @@ static void stm32_endwait(struct stm32_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1635,7 +1635,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2100,7 +2100,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2545,7 +2545,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
stm32_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2588,7 +2588,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
wkupevent = SDIOWAIT_ERROR;
goto errout_with_waitints;
}
@ -3042,11 +3042,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
/* Allocate a DMA channel */
#ifdef CONFIG_STM32_SDIO_DMA

25
arch/arm/src/stm32f7/stm32_ethernet.c
View file

@ -632,8 +632,8 @@ struct stm32_ethmac_s
uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
uint8_t fduplex : 1; /* Full (vs. half) duplex */
uint8_t intf; /* Ethernet interface number */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -1268,7 +1268,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, STM32_TXTIMEOUT,
wd_start(&priv->txtimeout, STM32_TXTIMEOUT,
stm32_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -2097,7 +2097,7 @@ static void stm32_txdone(struct stm32_ethmac_s *priv)
{
/* Cancel the TX timeout */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* And disable further TX interrupts. */
@ -2258,7 +2258,7 @@ static int stm32_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
DEBUGASSERT(work_available(&priv->irqwork));
@ -2412,7 +2412,7 @@ static void stm32_poll_work(void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2447,7 +2447,7 @@ static void stm32_poll_expiry(int argc, wdparm_t arg, ...)
}
else
{
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
}
}
@ -2496,7 +2496,7 @@ static int stm32_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -2538,8 +2538,8 @@ static int stm32_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the stm32_ifup() always
@ -4183,11 +4183,6 @@ int stm32_ethinitialize(int intf)
priv->dev.d_private = g_stm32ethmac; /* Used to recover private state from dev */
priv->intf = intf; /* Remember the interface number */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
stm32_get_uniqueid(uid);
crc = crc64(uid, 12);

25
arch/arm/src/stm32f7/stm32_qspi.c
View file

@ -200,7 +200,7 @@ struct stm32f7_qspidev_s
sem_t dmawait; /* Used to wait for DMA completion */
int result; /* DMA result */
DMA_HANDLE dmach; /* QSPI DMA handle */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
#endif
/* Debug stuff */
@ -1392,7 +1392,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1524,7 +1524,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&priv->dmadog, DMA_TIMEOUT_TICKS,
qspi_dma_timeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -1543,7 +1543,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv,
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Check if we were awakened by an error of some kind */
@ -2601,15 +2601,6 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
priv->dmadog = wd_create();
if (priv->dmadog == NULL)
{
spierr("ERROR: Failed to create wdog\n");
goto errout_with_dmahandles;
}
#endif
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
@ -2619,7 +2610,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
if (ret < 0)
{
spierr("ERROR: Failed to attach irq %d\n", priv->irq);
goto errout_with_dmadog;
goto errout_with_dmawait;
}
/* Initialize the semaphore that blocks until the operation completes.
@ -2657,14 +2648,10 @@ errout_with_irq:
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
irq_detach(priv->irq);
errout_with_dmadog:
errout_with_dmawait:
#endif
#ifdef CONFIG_STM32F7_QSPI_DMA
wd_delete(priv->dmadog);
errout_with_dmahandles:
nxsem_destroy(&priv->dmawait);
if (priv->dmach)
{
stm32_dmafree(priv->dmach);

11
arch/arm/src/stm32f7/stm32_sai.c
View file

@ -217,7 +217,7 @@ struct stm32f7_sai_s
uint32_t samplerate; /* Data sample rate */
uint8_t rxenab:1; /* True: RX transfers enabled */
uint8_t txenab:1; /* True: TX transfers enabled */
WDOG_ID dog; /* Watchdog that handles timeouts */
struct wdog_s dog; /* Watchdog that handles timeouts */
sq_queue_t pend; /* A queue of pending transfers */
sq_queue_t act; /* A queue of active transfers */
sq_queue_t done; /* A queue of completed transfers */
@ -988,7 +988,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv)
if (bfcontainer->timeout > 0)
{
ret = wd_start(priv->dog, bfcontainer->timeout,
ret = wd_start(&priv->dog, bfcontainer->timeout,
sai_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -1170,7 +1170,7 @@ static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dog);
wd_cancel(&priv->dog);
/* Then schedule completion of the transfer to occur on the worker thread */
@ -1624,11 +1624,6 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv)
nxsem_init(&priv->exclsem, 0, 1);
/* Create a watchdog timer to catch transfer timeouts */
priv->dog = wd_create();
DEBUGASSERT(priv->dog);
/* Initialize buffering */
sai_buf_initialize(priv);

17
arch/arm/src/stm32f7/stm32_sdmmc.c
View file

@ -397,7 +397,7 @@ struct stm32_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1495,7 +1495,7 @@ static void stm32_endwait(struct stm32_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1918,7 +1918,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
* completion events */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2375,7 +2375,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2827,7 +2827,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
stm32_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2870,7 +2870,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
wkupevent = SDIOWAIT_ERROR;
goto errout_with_waitints;
}
@ -3475,11 +3475,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
#ifdef CONFIG_STM32F7_SDMMC_DMA
/* Allocate a DMA channel */

28
arch/arm/src/stm32h7/stm32_ethernet.c
View file

@ -610,8 +610,8 @@ struct stm32_ethmac_s
uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
uint8_t fduplex : 1; /* Full (vs. half) duplex */
uint8_t intf; /* Ethernet interface number */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -1277,7 +1277,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, STM32_TXTIMEOUT,
wd_start(&priv->txtimeout, STM32_TXTIMEOUT,
stm32_txtimeout_expiry, 1, (wdparm_t)priv);
/* Update the tx descriptor tail pointer register to start the DMA */
@ -2184,7 +2184,7 @@ static void stm32_txdone(struct stm32_ethmac_s *priv)
{
/* Cancel the TX timeout */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* And disable further TX interrupts. */
@ -2345,7 +2345,7 @@ static int stm32_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
DEBUGASSERT(work_available(&priv->irqwork));
@ -2502,7 +2502,7 @@ static void stm32_poll_work(void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2537,7 +2537,7 @@ static void stm32_poll_expiry(int argc, wdparm_t arg, ...)
}
else
{
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
}
}
@ -2586,7 +2586,7 @@ static int stm32_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, STM32_WDDELAY,
wd_start(&priv->txpoll, STM32_WDDELAY,
stm32_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -2628,8 +2628,8 @@ static int stm32_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the stm32_ifup() always
@ -4385,15 +4385,9 @@ static inline int stm32_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_PHY_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private =
(void *)g_stm32ethmac; /* Used to recover private state */
priv->dev.d_private = g_stm32ethmac; /* Used to recover private state */
priv->intf = intf; /* Remember the interface number */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
stm32_get_uniqueid(uid);
crc = crc64(uid, 12);

25
arch/arm/src/stm32h7/stm32_qspi.c
View file

@ -224,7 +224,7 @@ struct stm32h7_qspidev_s
sem_t dmawait; /* Used to wait for DMA completion */
int result; /* DMA result */
DMA_HANDLE dmach; /* QSPI DMA handle */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
#endif
/* Debug stuff */
@ -1436,7 +1436,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1568,7 +1568,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&priv->dmadog, DMA_TIMEOUT_TICKS,
qspi_dma_timeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -1587,7 +1587,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv,
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Check if we were awakened by an error of some kind */
@ -2668,15 +2668,6 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
priv->dmadog = wd_create();
if (priv->dmadog == NULL)
{
spierr("ERROR: Failed to create wdog\n");
goto errout_with_dmahandles;
}
#endif
#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS
@ -2686,7 +2677,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
if (ret < 0)
{
spierr("ERROR: Failed to attach irq %d\n", priv->irq);
goto errout_with_dmadog;
goto errout_with_dmawait;
}
/* Initialize the semaphore that blocks until the operation completes.
@ -2724,14 +2715,10 @@ errout_with_irq:
#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS
irq_detach(priv->irq);
errout_with_dmadog:
errout_with_dmawait:
#endif
#ifdef CONFIG_STM32H7_QSPI_DMA
wd_delete(priv->dmadog);
errout_with_dmahandles:
nxsem_destroy(&priv->dmawait);
if (priv->dmach)
{
stm32_dmafree(priv->dmach);

17
arch/arm/src/stm32h7/stm32_sdmmc.c
View file

@ -336,7 +336,7 @@ struct stm32_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1476,7 +1476,7 @@ static void stm32_endwait(struct stm32_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1952,7 +1952,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
priv->waitmask = 0; /* Interrupt enables for event waiting */
priv->wkupevent = 0; /* The event that caused the wakeup */
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2453,7 +2453,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Mark no transfer in progress */
@ -2891,7 +2891,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
stm32_eventtimeout, 1, (wdparm_t)priv);
if (ret < OK)
{
@ -2934,7 +2934,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
wkupevent = SDIOWAIT_ERROR;
goto errout_with_waitints;
}
@ -3535,11 +3535,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
/* Reset the card and assure that it is in the initial, unconfigured
* state.
*/

25
arch/arm/src/stm32l4/stm32l4_qspi.c
View file

@ -197,7 +197,7 @@ struct stm32l4_qspidev_s
sem_t dmawait; /* Used to wait for DMA completion */
int result; /* DMA result */
DMA_HANDLE dmach; /* QSPI DMA handle */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
#endif
/* Debug stuff */
@ -1347,7 +1347,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1477,7 +1477,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&priv->dmadog, DMA_TIMEOUT_TICKS,
qspi_dma_timeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -1490,7 +1490,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Check if we were awakened by an error of some kind */
@ -2541,15 +2541,6 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
priv->dmadog = wd_create();
if (priv->dmadog == NULL)
{
spierr("ERROR: Failed to create wdog\n");
goto errout_with_dmahandles;
}
#endif
#ifdef STM32L4_QSPI_INTERRUPTS
@ -2559,7 +2550,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
if (ret < 0)
{
spierr("ERROR: Failed to attach irq %d\n", priv->irq);
goto errout_with_dmadog;
goto errout_with_dmawait;
}
/* Initialize the semaphore that blocks until the operation completes.
@ -2597,14 +2588,10 @@ errout_with_irq:
#ifdef STM32L4_QSPI_INTERRUPTS
irq_detach(priv->irq);
errout_with_dmadog:
errout_with_dmawait:
#endif
#ifdef CONFIG_STM32L4_QSPI_DMA
wd_delete(priv->dmadog);
errout_with_dmahandles:
nxsem_destroy(&priv->dmawait);
if (priv->dmach)
{
stm32l4_dmafree(priv->dmach);

11
arch/arm/src/stm32l4/stm32l4_sai.c
View file

@ -156,7 +156,7 @@ struct stm32l4_sai_s
uint32_t samplerate; /* Data sample rate */
uint8_t rxenab:1; /* True: RX transfers enabled */
uint8_t txenab:1; /* True: TX transfers enabled */
WDOG_ID dog; /* Watchdog that handles timeouts */
struct wdog_s dog; /* Watchdog that handles timeouts */
sq_queue_t pend; /* A queue of pending transfers */
sq_queue_t act; /* A queue of active transfers */
sq_queue_t done; /* A queue of completed transfers */
@ -657,7 +657,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv)
if (bfcontainer->timeout > 0)
{
ret = wd_start(priv->dog, bfcontainer->timeout,
ret = wd_start(&priv->dog, bfcontainer->timeout,
sai_timeout, 1, (wdparm_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@ -839,7 +839,7 @@ static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dog);
wd_cancel(&priv->dog);
/* Then schedule completion of the transfer to occur on the worker thread */
@ -1296,11 +1296,6 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv)
nxsem_init(&priv->exclsem, 0, 1);
/* Create a watchdog timer to catch transfer timeouts */
priv->dog = wd_create();
DEBUGASSERT(priv->dog);
/* Initialize buffering */
sai_buf_initialize(priv);

17
arch/arm/src/stm32l4/stm32l4_sdmmc.c
View file

@ -347,7 +347,7 @@ struct stm32_dev_s
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitmask; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */
@ -1375,7 +1375,7 @@ static void stm32_endwait(struct stm32_dev_s *priv,
{
/* Cancel the watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* Disable event-related interrupts */
@ -1743,7 +1743,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
* completion events */
#endif
wd_cancel(priv->waitwdog); /* Cancel any timeouts */
wd_cancel(&priv->waitwdog); /* Cancel any timeouts */
/* Interrupt mode data transfer support */
@ -2168,7 +2168,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -2631,7 +2631,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
ret = wd_start(&priv->waitwdog, delay,
stm32_eventtimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -2674,7 +2674,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
* return an SDIO error.
*/
wd_cancel(priv->waitwdog);
wd_cancel(&priv->waitwdog);
wkupevent = SDIOWAIT_ERROR;
goto errout_with_waitints;
}
@ -3178,11 +3178,6 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
priv->waitwdog = wd_create();
DEBUGASSERT(priv->waitwdog);
#ifdef CONFIG_STM32L4_SDMMC_DMA
/* Allocate a DMA channel */

28
arch/arm/src/tiva/lm/lm3s_ethernet.c
View file

@ -205,8 +205,8 @@ struct tiva_driver_s
#endif
bool ld_bifup; /* true:ifup false:ifdown */
WDOG_ID ld_txpoll; /* TX poll timer */
WDOG_ID ld_txtimeout; /* TX timeout timer */
struct wdog_s ld_txpoll; /* TX poll timer */
struct wdog_s ld_txtimeout; /* TX timeout timer */
struct work_s ld_irqwork; /* For deferring interrupt work to the work queue */
struct work_s ld_pollwork; /* For deferring poll work to the work queue */
@ -597,7 +597,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->ld_txtimeout, TIVA_TXTIMEOUT,
wd_start(&priv->ld_txtimeout, TIVA_TXTIMEOUT,
tiva_txtimeout_expiry, 1, (wdparm_t)priv);
ret = OK;
}
@ -952,7 +952,7 @@ static void tiva_txdone(struct tiva_driver_s *priv)
{
/* Cancel the TX timeout */
wd_cancel(priv->ld_txtimeout);
wd_cancel(&priv->ld_txtimeout);
/* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an
* Ethernet transmission once the packet has been placed in the TX FIFO.
@ -1116,7 +1116,7 @@ static int tiva_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->ld_txtimeout);
wd_cancel(&priv->ld_txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -1243,7 +1243,7 @@ static void tiva_poll_work(void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->ld_txpoll, TIVA_WDDELAY,
wd_start(&priv->ld_txpoll, TIVA_WDDELAY,
tiva_poll_expiry, 1, (wdparm_t)priv);
}
@ -1430,7 +1430,7 @@ static int tiva_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->ld_txpoll, TIVA_WDDELAY,
wd_start(&priv->ld_txpoll, TIVA_WDDELAY,
tiva_poll_expiry, 1, (wdparm_t)priv);
priv->ld_bifup = true;
@ -1468,8 +1468,8 @@ static int tiva_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
flags = enter_critical_section();
wd_cancel(priv->ld_txpoll);
wd_cancel(priv->ld_txtimeout);
wd_cancel(&priv->ld_txpoll);
wd_cancel(&priv->ld_txtimeout);
/* Disable the Ethernet interrupt */
@ -1715,17 +1715,13 @@ static inline int tiva_ethinitialize(int intf)
priv->ld_dev.d_addmac = tiva_addmac; /* Add multicast MAC address */
priv->ld_dev.d_rmmac = tiva_rmmac; /* Remove multicast MAC address */
#endif
priv->ld_dev.d_private = (void *)priv; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->ld_dev.d_private = priv; /* Used to recover private state from dev */
#if TIVA_NETHCONTROLLERS > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"
priv->ld_base = ??; /* Ethernet controller base address */
priv->ld_irq = ??; /* Ethernet controller IRQ number */
priv->ld_base = ??; /* Ethernet controller base address */
priv->ld_irq = ??; /* Ethernet controller IRQ number */
#endif
priv->ld_txpoll = wd_create(); /* Create periodic poll timer */
priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */
#ifdef CONFIG_TIVA_BOARDMAC
/* If the board can provide us with a MAC address, get the address

25
arch/arm/src/tiva/tm4c/tm4c_ethernet.c
View file

@ -628,8 +628,8 @@ struct tiva_ethmac_s
uint8_t ifup : 1; /* true:ifup false:ifdown */
uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
uint8_t fduplex : 1; /* Full (vs. half) duplex */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@ -1218,7 +1218,7 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, TIVA_TXTIMEOUT,
wd_start(&priv->txtimeout, TIVA_TXTIMEOUT,
tiva_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1983,7 +1983,7 @@ static void tiva_txdone(FAR struct tiva_ethmac_s *priv)
{
/* Cancel the TX timeout */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
/* And disable further TX interrupts. */
@ -2145,7 +2145,7 @@ static int tiva_interrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2313,7 +2313,7 @@ static void tiva_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, TIVA_WDDELAY,
wd_start(&priv->txpoll, TIVA_WDDELAY,
tiva_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2390,7 +2390,7 @@ static int tiva_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, TIVA_WDDELAY,
wd_start(&priv->txpoll, TIVA_WDDELAY,
tiva_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -2433,8 +2433,8 @@ static int tiva_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the tiva_ifup() always
@ -4092,12 +4092,7 @@ int tiva_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = tiva_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_tiva_ethmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = g_tiva_ethmac; /* Used to recover private state from dev */
#ifdef CONFIG_TIVA_BOARDMAC
/* If the board can provide us with a MAC address, get the address

13
arch/arm/src/xmc4/xmc4_spi.c
View file

@ -185,7 +185,7 @@ struct xmc4_spics_s
#ifdef CONFIG_XMC4_SPI_DMA
bool candma; /* DMA is supported */
sem_t dmawait; /* Used to wait for DMA completion */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
int result; /* DMA result */
DMA_HANDLE rxdma; /* SPI RX DMA handle */
DMA_HANDLE txdma; /* SPI TX DMA handle */
@ -959,7 +959,7 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1661,7 +1661,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&spics->dmadog, DMA_TIMEOUT_TICKS,
spi_dmatimeout, 1, (wdparm_t)spics);
if (ret != OK)
{
@ -1674,7 +1674,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Cancel the watchdog timeout */
wd_cancel(spics->dmadog);
wd_cancel(&spics->dmadog);
/* Check if we were awakened by an error of some kind. */
@ -2092,11 +2092,6 @@ struct spi_dev_s *xmc4_spibus_initialize(int channel)
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
spics->dmadog = wd_create();
DEBUGASSERT(spics->dmadog);
#endif
spi_dumpregs(spi, "After initialization");

22
arch/hc/src/m9s12/m9s12_ethernet.c
View file

@ -96,8 +96,8 @@
struct emac_driver_s
{
bool d_bifup; /* true:ifup false:ifdown */
WDOG_ID d_txpoll; /* TX poll timer */
WDOG_ID d_txtimeout; /* TX timeout timer */
struct wdog_s d_txpoll; /* TX poll timer */
struct wdog_s d_txtimeout; /* TX timeout timer */
/* This holds the information visible to the NuttX network */
@ -185,7 +185,7 @@ static int emac_transmit(FAR struct emac_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->d_txtimeout, HCS12_TXTIMEOUT,
wd_start(&priv->d_txtimeout, HCS12_TXTIMEOUT,
emac_txtimeout, 1, (wdparm_t)priv);
return OK;
}
@ -427,7 +427,7 @@ static void emac_txdone(FAR struct emac_driver_s *priv)
* disable further Tx interrupts.
*/
wd_cancel(priv->d_txtimeout);
wd_cancel(&priv->d_txtimeout);
/* Then poll the network for new XMIT data */
@ -540,7 +540,7 @@ static void emac_polltimer(int argc, wdparm_t arg, ...)
/* Setup the watchdog poll timer again */
wd_start(priv->d_txpoll, HCS12_WDDELAY, emac_polltimer, 1, (wdparm_t)arg);
wd_start(&priv->d_txpoll, HCS12_WDDELAY, emac_polltimer, 1, (wdparm_t)arg);
}
/****************************************************************************
@ -573,7 +573,8 @@ static int emac_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->d_txpoll, HCS12_WDDELAY, emac_polltimer, 1, (wdparm_t)priv);
wd_start(&priv->d_txpoll, HCS12_WDDELAY,
emac_polltimer, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -611,8 +612,8 @@ static int emac_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->d_txpoll);
wd_cancel(priv->d_txtimeout);
wd_cancel(&priv->d_txpoll);
wd_cancel(&priv->d_txtimeout);
/* Put the EMAC is its reset, non-operational state. This should be
* a known configuration that will guarantee the emac_ifup() always
@ -786,11 +787,6 @@ int emac_initialize(int intf)
#endif
priv->d_dev.d_private = priv; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->d_txpoll = wd_create(); /* Create periodic poll timer */
priv->d_txtimeout = wd_create(); /* Create TX timeout timer */
/* Put the interface in the down state. This usually amounts to resetting
* the device and/or calling emac_ifdown().
*/

31
arch/mips/src/pic32mx/pic32mx_ethernet.c
View file

@ -330,8 +330,8 @@ struct pic32mx_driver_s
#endif
uint8_t pd_txnext; /* Index to the next Tx descriptor */
uint32_t pd_inten; /* Shadow copy of INTEN register */
WDOG_ID pd_txpoll; /* TX poll timer */
WDOG_ID pd_txtimeout; /* TX timeout timer */
struct wdog_s pd_txpoll; /* TX poll timer */
struct wdog_s pd_txtimeout; /* TX timeout timer */
struct work_s pd_irqwork; /* For deferring interrupt work to the work queue */
struct work_s pd_pollwork; /* For deferring poll work to the work queue */
@ -1112,7 +1112,7 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->pd_txtimeout, PIC32MX_TXTIMEOUT,
wd_start(&priv->pd_txtimeout, PIC32MX_TXTIMEOUT,
pic32mx_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
@ -1628,7 +1628,7 @@ static void pic32mx_txdone(struct pic32mx_driver_s *priv)
/* Cancel the pending Tx timeout */
wd_cancel(priv->pd_txtimeout);
wd_cancel(&priv->pd_txtimeout);
/* Disable further Tx interrupts. Tx interrupts may be re-enabled again
* depending upon the result of the poll.
@ -1939,7 +1939,7 @@ static int pic32mx_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->pd_txtimeout);
wd_cancel(&priv->pd_txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2069,7 +2069,7 @@ static void pic32mx_poll_work(void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->pd_txpoll, PIC32MX_WDDELAY,
wd_start(&priv->pd_txpoll, PIC32MX_WDDELAY,
pic32mx_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2401,7 +2401,7 @@ static int pic32mx_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->pd_txpoll, PIC32MX_WDDELAY,
wd_start(&priv->pd_txpoll, PIC32MX_WDDELAY,
pic32mx_poll_expiry, 1, (wdparm_t)priv);
/* Finally, enable the Ethernet interrupt at the interrupt controller */
@ -2448,8 +2448,8 @@ static int pic32mx_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->pd_txpoll);
wd_cancel(priv->pd_txtimeout);
wd_cancel(&priv->pd_txpoll);
wd_cancel(&priv->pd_txtimeout);
/* Reset the device and mark it as down. */
@ -3414,20 +3414,15 @@ static inline int pic32mx_ethinitialize(int intf)
priv->pd_dev.d_addmac = pic32mx_addmac; /* Add multicast MAC address */
priv->pd_dev.d_rmmac = pic32mx_rmmac; /* Remove multicast MAC address */
#endif
priv->pd_dev.d_private = (void *)priv; /* Used to recover private state from dev */
priv->pd_dev.d_private = priv; /* Used to recover private state from dev */
#if CONFIG_PIC32MX_NINTERFACES > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"
priv->pd_base = ??; /* Ethernet controller base address */
priv->pd_irq = ??; /* Ethernet controller IRQ vector number */
priv->pd_irqsrc = ??; /* Ethernet controller IRQ source number */
priv->pd_base = ??; /* Ethernet controller base address */
priv->pd_irq = ??; /* Ethernet controller IRQ vector number */
priv->pd_irqsrc = ??; /* Ethernet controller IRQ source number */
#endif
/* Create a watchdog for timing polling for and timing of transmissions */
priv->pd_txpoll = wd_create(); /* Create periodic poll timer */
priv->pd_txtimeout = wd_create(); /* Create TX timeout timer */
/* Reset the Ethernet controller and leave in the ifdown state. The
* Ethernet controller will be properly re-initialized each time
* pic32mx_ifup() is called.

5
arch/mips/src/pic32mx/pic32mx_usbdev.c
View file

@ -422,7 +422,7 @@ struct pic32mx_usbdev_s
uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */
uint16_t epavail; /* Bitset of available endpoints */
uint16_t epstalled; /* Bitset of stalled endpoints */
WDOG_ID wdog; /* Supports the restart delay */
struct wdog_s wdog; /* Supports the restart delay */
/* The endpoint list */
@ -1042,7 +1042,7 @@ static void pic32mx_delayedrestart(struct pic32mx_usbdev_s *priv,
/* And start (or re-start) the watchdog timer */
wd_start(priv->wdog, RESTART_DELAY,
wd_start(&priv->wdog, RESTART_DELAY,
pic32mx_rqrestart, 1, (wdparm_t)priv);
}
@ -4366,7 +4366,6 @@ void up_usbinitialize(void)
*/
priv->epstalled = 0;
priv->wdog = wd_create();
/* Attach USB controller interrupt handler. The hardware will not be
* initialized and interrupts will not be enabled until the class device

31
arch/mips/src/pic32mz/pic32mz_ethernet.c
View file

@ -386,8 +386,8 @@ struct pic32mz_driver_s
#endif
uint8_t pd_txnext; /* Index to the next Tx descriptor */
uint32_t pd_inten; /* Shadow copy of INTEN register */
WDOG_ID pd_txpoll; /* TX poll timer */
WDOG_ID pd_txtimeout; /* TX timeout timer */
struct wdog_s pd_txpoll; /* TX poll timer */
struct wdog_s pd_txtimeout; /* TX timeout timer */
struct work_s pd_irqwork; /* For deferring interrupt work to the work queue */
struct work_s pd_pollwork; /* For deferring poll work to the work queue */
@ -1217,7 +1217,7 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT,
wd_start(&priv->pd_txtimeout, PIC32MZ_TXTIMEOUT,
pic32mz_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
@ -1746,7 +1746,7 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv)
/* Cancel the pending Tx timeout */
wd_cancel(priv->pd_txtimeout);
wd_cancel(&priv->pd_txtimeout);
/* Disable further Tx interrupts. Tx interrupts may be re-enabled again
* depending upon the result of the poll.
@ -2073,7 +2073,7 @@ static int pic32mz_interrupt(int irq, void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->pd_txtimeout);
wd_cancel(&priv->pd_txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -2202,7 +2202,7 @@ static void pic32mz_poll_work(void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY,
wd_start(&priv->pd_txpoll, PIC32MZ_WDDELAY,
pic32mz_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2545,7 +2545,7 @@ static int pic32mz_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY,
wd_start(&priv->pd_txpoll, PIC32MZ_WDDELAY,
pic32mz_poll_expiry, 1, (wdparm_t)priv);
/* Finally, enable the Ethernet interrupt at the interrupt controller */
@ -2593,8 +2593,8 @@ static int pic32mz_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->pd_txpoll);
wd_cancel(priv->pd_txtimeout);
wd_cancel(&priv->pd_txpoll);
wd_cancel(&priv->pd_txtimeout);
/* Reset the device and mark it as down. */
@ -3577,20 +3577,15 @@ static inline int pic32mz_ethinitialize(int intf)
priv->pd_dev.d_addmac = pic32mz_addmac; /* Add multicast MAC address */
priv->pd_dev.d_rmmac = pic32mz_rmmac; /* Remove multicast MAC address */
#endif
priv->pd_dev.d_private = (void *)priv; /* Used to recover private state from dev */
priv->pd_dev.d_private = priv; /* Used to recover private state from dev */
#if CONFIG_PIC32MZ_NINTERFACES > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"
priv->pd_base = ; /* Ethernet controller base address */
priv->pd_irq = ; /* Ethernet controller IRQ vector number */
priv->pd_irqsrc = ; /* Ethernet controller IRQ source number */
priv->pd_base = ; /* Ethernet controller base address */
priv->pd_irq = ; /* Ethernet controller IRQ vector number */
priv->pd_irqsrc = ; /* Ethernet controller IRQ source number */
#endif
/* Create a watchdog for timing polling for and timing of transmissions */
priv->pd_txpoll = wd_create(); /* Create periodic poll timer */
priv->pd_txtimeout = wd_create(); /* Create TX timeout timer */
/* Configure Ethernet peripheral pin selections */
/* Controlled by DEVCFG FMIIEN and FETHIO settings */

15
arch/mips/src/pic32mz/pic32mz_spi.c
View file

@ -154,7 +154,7 @@ struct pic32mz_dev_s
DMA_HANDLE txdma; /* SPI TX DMA handle */
int result; /* DMA result */
sem_t dmawait; /* Used to wait for DMA completion */
WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */
struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */
#endif
#ifdef CONFIG_PIC32MZ_SPI_REGDEBUG
@ -889,7 +889,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -944,7 +944,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1774,7 +1774,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
{
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
ret = wd_start(&priv->dmadog, DMA_TIMEOUT_TICKS,
spi_dmatimeout, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -1787,7 +1787,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* Cancel the watchdog timeout */
wd_cancel(priv->dmadog);
wd_cancel(&priv->dmadog);
/* Check if we were awakened by an error of some kind. EINTR is not a
* failure. It simply means that the wait was awakened by a signal.
@ -2039,11 +2039,6 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port)
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog timer to catch DMA timeouts */
priv->dmadog = wd_create();
DEBUGASSERT(priv->dmadog);
#endif
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS

25
arch/misoc/src/common/misoc_net.c
View file

@ -117,8 +117,8 @@
struct misoc_net_driver_s
{
bool misoc_net_bifup; /* true:ifup false:ifdown */
WDOG_ID misoc_net_txpoll; /* TX poll timer */
WDOG_ID misoc_net_txtimeout; /* TX timeout timer */
struct wdog_s misoc_net_txpoll; /* TX poll timer */
struct wdog_s misoc_net_txtimeout; /* TX timeout timer */
struct work_s misoc_net_irqwork; /* For deferring interrupt work to the work queue */
struct work_s misoc_net_pollwork; /* For deferring poll work to the work queue */
uint8_t *rx0_buf; /* 2 RX and 2 TX buffer */
@ -273,7 +273,7 @@ static int misoc_net_transmit(FAR struct misoc_net_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->misoc_net_txtimeout, MISOC_NET_TXTIMEOUT,
wd_start(&priv->misoc_net_txtimeout, MISOC_NET_TXTIMEOUT,
misoc_net_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -557,7 +557,7 @@ static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv)
* disable further Tx interrupts.
*/
wd_cancel(priv->misoc_net_txtimeout);
wd_cancel(&priv->misoc_net_txtimeout);
/* And disable further TX interrupts. */
@ -661,7 +661,7 @@ static int misoc_net_interrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->misoc_net_txtimeout);
wd_cancel(&priv->misoc_net_txtimeout);
}
/* Schedule to perform the interrupt processing on the worker thread. */
@ -781,7 +781,7 @@ static void misoc_net_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY,
wd_start(&priv->misoc_net_txpoll, MISOC_NET_WDDELAY,
misoc_net_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
@ -866,7 +866,7 @@ static int misoc_net_ifup(FAR struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY,
wd_start(&priv->misoc_net_txpoll, MISOC_NET_WDDELAY,
misoc_net_poll_expiry, 1, (wdparm_t)priv);
priv->misoc_net_bifup = true;
@ -911,8 +911,8 @@ static int misoc_net_ifdown(FAR struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->misoc_net_txpoll);
wd_cancel(priv->misoc_net_txtimeout);
wd_cancel(&priv->misoc_net_txpoll);
wd_cancel(&priv->misoc_net_txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the misoc_net_ifup() always
@ -1205,12 +1205,7 @@ int misoc_net_initialize(int intf)
priv->misoc_net_dev.d_addmac = misoc_net_addmac; /* Add multicast MAC address */
priv->misoc_net_dev.d_rmmac = misoc_net_rmmac; /* Remove multicast MAC address */
#endif
priv->misoc_net_dev.d_private = (FAR void *)g_misoc_net; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->misoc_net_txpoll = wd_create(); /* Create periodic poll timer */
priv->misoc_net_txtimeout = wd_create(); /* Create TX timeout timer */
priv->misoc_net_dev.d_private = g_misoc_net; /* Used to recover private state from dev */
/* Put the interface in the down state. This usually amounts to resetting
* the device and/or calling misoc_net_ifdown().

2
arch/renesas/src/rx65n/rx65n_eth.c
View file

@ -4194,7 +4194,7 @@ int rx65n_ethinitialize(int intf)
/* Used to recover private state from dev */
priv->dev.d_private = (void *)g_rx65nethmac;
priv->dev.d_private = g_rx65nethmac;
/* Multi cast flag */

11
arch/sim/src/sim/up_ioexpander.c
View file

@ -108,7 +108,7 @@ struct sim_dev_s
ioe_pinset_t level[2]; /* Bit encoded: 01=high/rising,
* 10 low/falling, 11 both */
WDOG_ID wdog; /* Timer used to poll for interrupt
struct wdog_s wdog; /* Timer used to poll for interrupt
* simulation */
struct work_s work; /* Supports the interrupt handling
* "bottom half" */
@ -774,7 +774,7 @@ static void sim_interrupt_work(void *arg)
/* Re-start the poll timer */
ret = wd_start(priv->wdog, SIM_POLLDELAY,
ret = wd_start(&priv->wdog, SIM_POLLDELAY,
sim_interrupt, 1, (wdparm_t)priv);
if (ret < 0)
{
@ -858,12 +858,7 @@ FAR struct ioexpander_dev_s *sim_ioexpander_initialize(void)
priv->level[0] = PINSET_ALL; /* All rising edge */
priv->level[1] = PINSET_ALL; /* All falling edge */
/* Set up a timer to poll for simulated interrupts */
priv->wdog = wd_create();
DEBUGASSERT(priv->wdog != NULL);
ret = wd_start(priv->wdog, SIM_POLLDELAY,
ret = wd_start(&priv->wdog, SIM_POLLDELAY,
sim_interrupt, 1, (wdparm_t)priv);
if (ret < 0)
{

51
arch/xtensa/src/esp32/esp32_emac.c
View file

@ -200,8 +200,8 @@ struct esp32_emac_s
uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
uint8_t fduplex : 1; /* Full (vs. half) duplex */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s txwork; /* For deferring TX work to the work queue */
struct work_s rxwork; /* For deferring RX work to the work queue */
@ -825,8 +825,8 @@ static int emac_transmit(struct esp32_emac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
ret = wd_start(priv->txtimeout, EMAC_TX_TO, emac_txtimeout_expiry,
1, (uint32_t)priv);
ret = wd_start(&priv->txtimeout, EMAC_TX_TO,
emac_txtimeout_expiry, 1, (wdparm_t)priv);
if (ret)
{
nerr("ERROR: Failed to start TX timeout timer");
@ -1503,7 +1503,7 @@ static void emac_tx_interrupt_work(FAR void *arg)
net_lock();
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
emac_dopoll(priv);
@ -1798,8 +1798,8 @@ static void emac_poll_work(FAR void *arg)
}
}
ret = wd_start(priv->txpoll, EMAC_WDDELAY , emac_poll_expiry,
1, (uint32_t)priv);
ret = wd_start(&priv->txpoll, EMAC_WDDELAY,
emac_poll_expiry, 1, (wdparm_t)priv);
if (ret)
{
nerr("ERROR: Failed to start TX poll timer");
@ -1901,7 +1901,8 @@ static int emac_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, EMAC_WDDELAY , emac_poll_expiry, 1, (uint32_t)priv);
wd_start(&priv->txpoll, EMAC_WDDELAY,
emac_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -1948,8 +1949,8 @@ static int emac_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Reset ethernet MAC and disable clock */
@ -2209,26 +2210,6 @@ int esp32_emac_init(void)
goto errout_with_attachirq;
}
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
if (!priv->txpoll)
{
nerr("ERROR: Failed create TX poll watch dog\n");
ret = -ENOMEM;
goto errout_with_attachirq;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nerr("ERROR: Failed create TX timeout watch dog\n");
ret = -ENOMEM;
goto errout_with_createtxtimeout;
}
/* Initialize the driver structure */
priv->dev.d_ifup = emac_ifup; /* I/F up (new IP address) callback */
@ -2255,19 +2236,11 @@ int esp32_emac_init(void)
{
nerr("ERROR: Failed to register net device\n");
goto errout_with_registernetdev;
goto errout_with_attachirq;
}
return 0;
errout_with_registernetdev:
wd_delete(priv->txtimeout);
priv->txtimeout = NULL;
errout_with_createtxtimeout:
wd_delete(priv->txpoll);
priv->txpoll = NULL;
errout_with_attachirq:
esp32_detach_peripheral(0, ESP32_PERIPH_EMAC, priv->cpuint);
esp32_free_cpuint(priv->cpuint);

27
arch/z80/src/ez80/ez80_emac.c
View file

@ -338,8 +338,8 @@ struct ez80emac_driver_s
bool bfullduplex; /* true:full duplex */
bool b100mbs; /* true:100Mbp */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
struct wdog_s txpoll; /* TX poll timer */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s txwork; /* For deferring Tx-related work to the work queue */
struct work_s rxwork; /* For deferring Rx-related work to the work queue */
@ -1134,7 +1134,7 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->txtimeout, EMAC_TXTIMEOUT,
wd_start(&priv->txtimeout, EMAC_TXTIMEOUT,
ez80emac_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1617,7 +1617,7 @@ static void ez80emac_txinterrupt_work(FAR void *arg)
/* Cancel any pending the TX timeout */
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
net_unlock();
@ -1666,7 +1666,7 @@ static int ez80emac_txinterrupt(int irq, FAR void *context, FAR void *arg)
* expiration and the deferred interrupt processing.
*/
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txtimeout);
}
/* Schedule to perform the Tx interrupt processing on the worker thread. */
@ -1995,7 +1995,7 @@ static void ez80emac_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
wd_start(priv->txpoll, EMAC_WDDELAY,
wd_start(&priv->txpoll, EMAC_WDDELAY,
ez80emac_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -2038,7 +2038,7 @@ static void ez80emac_poll_expiry(int argc, wdparm_t arg, ...)
* cycle.
*/
wd_start(priv->txpoll, EMAC_WDDELAY,
wd_start(&priv->txpoll, EMAC_WDDELAY,
ez80emac_poll_expiry, 1, (wdparm_t)arg);
}
}
@ -2130,7 +2130,7 @@ static int ez80emac_ifup(FAR struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->txpoll, EMAC_WDDELAY,
wd_start(&priv->txpoll, EMAC_WDDELAY,
ez80emac_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupts */
@ -2177,8 +2177,8 @@ static int ez80emac_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(priv->txpoll);
wd_cancel(priv->txtimeout);
wd_cancel(&priv->txpoll);
wd_cancel(&priv->txtimeout);
/* Disable Rx */
@ -2620,12 +2620,7 @@ int up_netinitialize(void)
priv->dev.d_addmac = ez80emac_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = ez80emac_rmmac; /* Remove multicast MAC address */
#endif
priv->dev.d_private = (FAR void *)&g_emac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
priv->dev.d_private = &g_emac; /* Used to recover private state from dev */
/* Read the MAC address from the hardware into
* priv->dev.d_mac.ether.ether_addr_octet

2
boards/arm/a1x/pcduino-a10/configs/nsh/defconfig
View file

@ -37,7 +37,6 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=905969664
CONFIG_RAM_START=0x4a000000
CONFIG_RAM_VSTART=0x4a000000
@ -52,4 +51,3 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=2

2
boards/arm/am335x/beaglebone-black/configs/lcd/defconfig
View file

@ -39,7 +39,6 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=369098752
CONFIG_RAM_START=0x8a000000
CONFIG_RAM_VSTART=0x8a000000
@ -54,4 +53,3 @@ CONFIG_SYSTEM_NSH=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_VIDEO=y
CONFIG_WDOG_INTRESERVE=2

2
boards/arm/am335x/beaglebone-black/configs/nsh/defconfig
View file

@ -37,7 +37,6 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=369098752
CONFIG_RAM_START=0x8a000000
CONFIG_RAM_VSTART=0x8a000000
@ -51,4 +50,3 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=2

2
boards/arm/c5471/c5471evm/configs/httpd/defconfig
View file

@ -31,7 +31,6 @@ CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PREALLOC_WDOGS=8
CONFIG_PTHREAD_STACK_DEFAULT=4096
CONFIG_RAM_SIZE=285212672
CONFIG_RAM_START=0
@ -45,4 +44,3 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="webserver_main"
CONFIG_WATCHDOG=y
CONFIG_WDOG_INTRESERVE=1

2
boards/arm/c5471/c5471evm/configs/nettest/defconfig
View file

@ -30,7 +30,6 @@ CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PREALLOC_WDOGS=8
CONFIG_PTHREAD_STACK_DEFAULT=4096
CONFIG_RAM_SIZE=285212672
CONFIG_RAM_START=0
@ -44,4 +43,3 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="nettest_main"
CONFIG_WATCHDOG=y
CONFIG_WDOG_INTRESERVE=1

2
boards/arm/c5471/c5471evm/configs/nsh/defconfig
View file

@ -41,7 +41,6 @@ CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_WDOGS=8
CONFIG_PTHREAD_STACK_DEFAULT=4096
CONFIG_RAM_SIZE=285212672
CONFIG_RAM_START=0
@ -56,4 +55,3 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WATCHDOG=y
CONFIG_WDOG_INTRESERVE=1

1
boards/arm/cxd56xx/spresense/configs/audio/defconfig
View file

@ -59,7 +59,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/audio_sdk/defconfig
View file

@ -57,7 +57,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/camera/defconfig
View file

@ -58,7 +58,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/elf/defconfig
View file

@ -37,7 +37,6 @@ CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PATH_INITIAL="/mnt/romfs"
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_RR_INTERVAL=200

1
boards/arm/cxd56xx/spresense/configs/example_camera/defconfig
View file

@ -58,7 +58,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/example_lcd/defconfig
View file

@ -77,7 +77,6 @@ CONFIG_NX=y
CONFIG_NXFONT_SERIF22X29=y
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/lcd/defconfig
View file

@ -65,7 +65,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/lte/defconfig
View file

@ -57,7 +57,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/module/defconfig
View file

@ -39,7 +39,6 @@ CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PATH_INITIAL="/mnt/romfs"
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_RR_INTERVAL=200

1
boards/arm/cxd56xx/spresense/configs/mpy/defconfig
View file

@ -67,7 +67,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/nsh/defconfig
View file

@ -37,7 +37,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/posix_spawn/defconfig
View file

@ -42,7 +42,6 @@ CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PATH_INITIAL="/mnt/romfs"
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_RR_INTERVAL=200

1
boards/arm/cxd56xx/spresense/configs/rndis/defconfig
View file

@ -105,7 +105,6 @@ CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y
CONFIG_NXPLAYER_MAINTHREAD_STACKSIZE=3072
CONFIG_PATH_INITIAL="/mnt/sd0/bin"
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/smp/defconfig
View file

@ -38,7 +38,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/usbmsc/defconfig
View file

@ -62,7 +62,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/usbnsh/defconfig
View file

@ -55,7 +55,6 @@ CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

1
boards/arm/cxd56xx/spresense/configs/wifi/defconfig
View file

@ -108,7 +108,6 @@ CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y
CONFIG_NXPLAYER_MAINTHREAD_STACKSIZE=3072
CONFIG_PATH_INITIAL="/mnt/sd0/bin"
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=1572864
CONFIG_RAM_START=0x0d000000
CONFIG_READLINE_CMD_HISTORY=y

2
boards/arm/dm320/ntosd-dm320/configs/nettest/defconfig
View file

@ -31,7 +31,6 @@ CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PREALLOC_WDOGS=8
CONFIG_PTHREAD_STACK_DEFAULT=4096
CONFIG_RAM_SIZE=33554432
CONFIG_RAM_START=0x01100000
@ -47,4 +46,3 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="nettest_main"
CONFIG_WDOG_INTRESERVE=0

2
boards/arm/dm320/ntosd-dm320/configs/poll/defconfig
View file

@ -33,7 +33,6 @@ CONFIG_NET_TCPBACKLOG=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PIPES=y
CONFIG_PREALLOC_WDOGS=8
CONFIG_PTHREAD_STACK_DEFAULT=4096
CONFIG_RAM_SIZE=33554432
CONFIG_RAM_START=0x01100000
@ -49,4 +48,3 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="poll_main"
CONFIG_WDOG_INTRESERVE=0

2
boards/arm/dm320/ntosd-dm320/configs/udp/defconfig
View file

@ -33,7 +33,6 @@ CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_PREALLOC_WDOGS=8
CONFIG_PTHREAD_STACK_DEFAULT=4096
CONFIG_RAM_SIZE=33554432
CONFIG_RAM_START=0x01100000
@ -49,4 +48,3 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="udpclient_main"
CONFIG_WDOG_INTRESERVE=0

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