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arch/arm: add support for imx95 m7 core

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- Add support for i.MX95 M7 core
- Interprocessor communication by RPMSG and SCMI
- Drivers available for UART, SPI, I2C, CAN, IO and timers
This commit is contained in:
Andre Heinemans 2024-12-16 14:48:41 +01:00 committed by Xiang Xiao
parent 5db6767f6f
commit a84257c885
70 changed files with 34946 additions and 0 deletions
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18
arch/arm/Kconfig
View file

@ -183,6 +183,20 @@ config ARCH_CHIP_IMX6
---help---
Freescale iMX.6 architectures (Cortex-A9)
config ARCH_CHIP_IMX9_CORTEX_M
bool "NXP iMX.9 Cortex-M7"
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_CS_CONTROL
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
iMX.9 architectures (Cortex-M7)
config ARCH_CHIP_IMXRT
bool "NXP/Freescale iMX.RT"
select ARCH_CORTEXM7
@ -1124,6 +1138,7 @@ config ARCH_CHIP
default "gd32f4" if ARCH_CHIP_GD32F4
default "imx1" if ARCH_CHIP_IMX1
default "imx6" if ARCH_CHIP_IMX6
default "imx9" if ARCH_CHIP_IMX9_CORTEX_M
default "imxrt" if ARCH_CHIP_IMXRT
default "kinetis" if ARCH_CHIP_KINETIS
default "kl" if ARCH_CHIP_KL
@ -1536,6 +1551,9 @@ endif
if ARCH_CHIP_IMX6
source "arch/arm/src/imx6/Kconfig"
endif
if ARCH_CHIP_IMX9_CORTEX_M
source "arch/arm/src/imx9/Kconfig"
endif
if ARCH_CHIP_IMXRT
source "arch/arm/src/imxrt/Kconfig"
endif

52
arch/arm/include/imx9/chip.h Normal file
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@ -0,0 +1,52 @@
/****************************************************************************
* arch/arm/include/imx9/chip.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_IMX9_CHIP_H
#define __ARCH_ARM_INCLUDE_IMX9_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* NVIC priority levels *****************************************************/
/* Each priority field holds an 8-bit priority value, 0-15. The lower the
* value, the greater the priority of the corresponding interrupt. The i.MX
* RT processor implements only bits[7:4] of each field, bits[3:0] read as
* zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
#define IMX9_GPIO_NPORTS 4
#endif /* __ARCH_ARM_INCLUDE_IMX9_CHIP_H */

420
arch/arm/include/imx9/imx95_irq.h Normal file
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@ -0,0 +1,420 @@
/****************************************************************************
* arch/arm/include/imx9/imx95_irq.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H
#define __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H
#define IMX9_IRQ_RESERVED16 (IMX9_IRQ_EXTINT + 0) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED17 (IMX9_IRQ_EXTINT + 1) /* DAP interrupt */
#define IMX9_IRQ_RESERVED18 (IMX9_IRQ_EXTINT + 2) /* CTI trigger outputs from CM7 platform */
#define IMX9_IRQ_RESERVED19 (IMX9_IRQ_EXTINT + 3) /* CTI trigger outputs from CM33 platform */
#define IMX9_IRQ_RESERVED20 (IMX9_IRQ_EXTINT + 4) /* CTI trigger outputs from CA55 platform */
#define IMX9_IRQ_RESERVED21 (IMX9_IRQ_EXTINT + 5) /* Performance Unit Interrupts from CA55 platform */
#define IMX9_IRQ_RESERVED22 (IMX9_IRQ_EXTINT + 6) /* ECC error from CA55 platform cache */
#define IMX9_IRQ_RESERVED23 (IMX9_IRQ_EXTINT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */
#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXTINT + 8) /* CAN1 interrupt */
#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXTINT + 9) /* CAN1 error interrupt */
#define IMX9_IRQ_GPIO1_0 (IMX9_IRQ_EXTINT + 10) /* General Purpose Input/Output 1 interrupt 0 */
#define IMX9_IRQ_GPIO1_1 (IMX9_IRQ_EXTINT + 11) /* General Purpose Input/Output 1 interrupt 1 */
#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXTINT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */
#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXTINT + 13) /* Low Power Inter-Integrated Circuit module 1 */
#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXTINT + 14) /* Low Power Inter-Integrated Circuit module 2 */
#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXTINT + 15) /* Low Power Periodic Interrupt Timer 1 */
#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXTINT + 16) /* Low Power Serial Peripheral Interface 1 */
#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXTINT + 17) /* Low Power Serial Peripheral Interface 2 */
#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXTINT + 18) /* Low Power Timer 1 */
#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXTINT + 19) /* Low Power UART 1 */
#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXTINT + 20) /* Low Power UART 2 */
#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXTINT + 21) /* AONMIX Sentinel MU0 SideA interrupt */
#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXTINT + 22) /* AONMIX Sentinel MU1 SideA interrupt */
#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXTINT + 23) /* AONMIX Sentinel MU2 SideA interrupt */
#define IMX9_IRQ_RESERVED40 (IMX9_IRQ_EXTINT + 24) /* AONMIX Sentinel MU3 SideA interrupt */
#define IMX9_IRQ_RESERVED41 (IMX9_IRQ_EXTINT + 25) /* AONMIX Sentinel MU4 SideA interrupt */
#define IMX9_IRQ_RESERVED42 (IMX9_IRQ_EXTINT + 26) /* AONMIX Sentinel MU5 SideA interrupt */
#define IMX9_IRQ_V2X_FH_APCH0 (IMX9_IRQ_EXTINT + 27) /* V2X-FH MU APCH0 (APP0) interrupt */
#define IMX9_IRQ_V2X_FH_APHSM1 (IMX9_IRQ_EXTINT + 28) /* V2X-FH MU APHSM1 (HSM1) interrupt */
#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXTINT + 29) /* Timer PWM module 1 */
#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXTINT + 30) /* Timer PWM module 2 */
#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXTINT + 31) /* Watchdog 1 Interrupt */
#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXTINT + 32) /* Watchdog 2 Interrupt */
#define IMX9_IRQ_TRDC_MGR_A (IMX9_IRQ_EXTINT + 33) /* AONMIX TRDC transfer error interrupt */
#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXTINT + 34) /* Serial Audio Interface 1 */
#define IMX9_IRQ_RESERVED51 (IMX9_IRQ_EXTINT + 35) /* AONMIX M33 PS Error */
#define IMX9_IRQ_RESERVED52 (IMX9_IRQ_EXTINT + 36) /* AONMIX M33 TCM Error interrupt */
#define IMX9_IRQ_RESERVED53 (IMX9_IRQ_EXTINT + 37) /* M7MIX ECC Multi-bit error */
#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXTINT + 38) /* CAN2 interrupt */
#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXTINT + 39) /* CAN2 error interrupt */
#define IMX9_IRQ_CAN3 (IMX9_IRQ_EXTINT + 40) /* CAN3 interrupt */
#define IMX9_IRQ_CAN3_ERROR (IMX9_IRQ_EXTINT + 41) /* CAN3 error interrupt */
#define IMX9_IRQ_CAN4 (IMX9_IRQ_EXTINT + 42) /* CAN4 interrupt */
#define IMX9_IRQ_CAN4_ERROR (IMX9_IRQ_EXTINT + 43) /* CAN4 error interrupt */
#define IMX9_IRQ_CAN5 (IMX9_IRQ_EXTINT + 44) /* CAN5 interrupt */
#define IMX9_IRQ_CAN5_ERROR (IMX9_IRQ_EXTINT + 45) /* CAN5 error interrupt */
#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXTINT + 46) /* Flexible IO 1 interrupt */
#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXTINT + 47) /* Flexible IO 2 interrupt */
#define IMX9_IRQ_FlexSPI1 (IMX9_IRQ_EXTINT + 48) /* FlexSPI controller interface interrupt 1 */
#define IMX9_IRQ_GPIO2_0 (IMX9_IRQ_EXTINT + 49) /* General Purpose Input/Output 2 interrupt 0 */
#define IMX9_IRQ_GPIO2_1 (IMX9_IRQ_EXTINT + 50) /* General Purpose Input/Output 2 interrupt 1 */
#define IMX9_IRQ_GPIO3_0 (IMX9_IRQ_EXTINT + 51) /* General Purpose Input/Output 3 interrupt 0 */
#define IMX9_IRQ_GPIO3_1 (IMX9_IRQ_EXTINT + 52) /* General Purpose Input/Output 3 interrupt 1 */
#define IMX9_IRQ_GPIO4_0 (IMX9_IRQ_EXTINT + 53) /* General Purpose Input/Output 4 interrupt 0 */
#define IMX9_IRQ_GPIO4_1 (IMX9_IRQ_EXTINT + 54) /* General Purpose Input/Output 4 interrupt 1 */
#define IMX9_IRQ_GPIO5_0 (IMX9_IRQ_EXTINT + 55) /* General Purpose Input/Output 5 interrupt 0 */
#define IMX9_IRQ_GPIO5_1 (IMX9_IRQ_EXTINT + 56) /* General Purpose Input/Output 5 interrupt 1 */
#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXTINT + 57) /* Improved Inter-Integrated Circuit 2 interrupt */
#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXTINT + 58) /* Low Power Inter-Integrated Circuit module 3 */
#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXTINT + 59) /* Low Power Inter-Integrated Circuit module 4 */
#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXTINT + 60) /* Low Power Periodic Interrupt Timer 2 */
#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXTINT + 61) /* Low Power Serial Peripheral Interface 3 */
#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXTINT + 62) /* Low Power Serial Peripheral Interface 4 */
#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXTINT + 63) /* Low Power Timer 2 */
#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXTINT + 64) /* Low Power UART 3 */
#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXTINT + 65) /* Low Power UART 4 */
#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXTINT + 66) /* Low Power UART 5 */
#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXTINT + 67) /* Low Power UART 6 */
#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXTINT + 68) /* Low Power UART 7 */
#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXTINT + 69) /* Low Power UART 8 */
#define IMX9_IRQ_RESERVED86 (IMX9_IRQ_EXTINT + 70) /* MTR Master error interrupt */
#define IMX9_IRQ_RESERVED87 (IMX9_IRQ_EXTINT + 71) /* BBNSM Non-Secure interrupt */
#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXTINT + 72) /* System Counter compare interrupt */
#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXTINT + 73) /* Timer PWM module 3 */
#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXTINT + 74) /* Timer PWM module 4 */
#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXTINT + 75) /* Timer PWM module 5 */
#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXTINT + 76) /* Timer PWM module 6 */
#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXTINT + 77) /* Watchdog 3 Interrupt */
#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXTINT + 78) /* Watchdog 4 Interrupt */
#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXTINT + 79) /* Watchdog 5 Interrupt */
#define IMX9_IRQ_TMPSNS1_THR1 (IMX9_IRQ_EXTINT + 80) /* ANAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS1_THR2 (IMX9_IRQ_EXTINT + 81) /* ANAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS1_DRDY (IMX9_IRQ_EXTINT + 82) /* ANAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXTINT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXTINT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXTINT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 90) /* NOCMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED107 (IMX9_IRQ_EXTINT + 91) /* DRAM controller Performance Monitor Interrupt */
#define IMX9_IRQ_RESERVED108 (IMX9_IRQ_EXTINT + 92) /* DRAM controller Critical Interrupt */
#define IMX9_IRQ_RESERVED109 (IMX9_IRQ_EXTINT + 93) /* DRAM Phy Critical Interrupt */
#define IMX9_IRQ_RESERVED110 (IMX9_IRQ_EXTINT + 94) /* Reserved */
#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXTINT + 95) /* eDMA1 error interrupt */
#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXTINT + 96) /* eDMA1 channel 0 interrupt */
#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXTINT + 97) /* eDMA1 channel 1 interrupt */
#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXTINT + 98) /* eDMA1 channel 2 interrupt */
#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXTINT + 99) /* eDMA1 channel 3 interrupt */
#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXTINT + 100) /* eDMA1 channel 4 interrupt */
#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXTINT + 101) /* eDMA1 channel 5 interrupt */
#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXTINT + 102) /* eDMA1 channel 6 interrupt */
#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXTINT + 103) /* eDMA1 channel 7 interrupt */
#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXTINT + 104) /* eDMA1 channel 8 interrupt */
#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXTINT + 105) /* eDMA1 channel 9 interrupt */
#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXTINT + 106) /* eDMA1 channel 10 interrupt */
#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXTINT + 107) /* eDMA1 channel 11 interrupt */
#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXTINT + 108) /* eDMA1 channel 12 interrupt */
#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXTINT + 109) /* eDMA1 channel 13 interrupt */
#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXTINT + 110) /* eDMA1 channel 14 interrupt */
#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXTINT + 111) /* eDMA1 channel 15 interrupt */
#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXTINT + 112) /* eDMA1 channel 16 interrupt */
#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXTINT + 113) /* eDMA1 channel 17 interrupt */
#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXTINT + 114) /* eDMA1 channel 18 interrupt */
#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXTINT + 115) /* eDMA1 channel 19 interrupt */
#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXTINT + 116) /* eDMA1 channel 20 interrupt */
#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXTINT + 117) /* eDMA1 channel 21 interrupt */
#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXTINT + 118) /* eDMA1 channel 22 interrupt */
#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXTINT + 119) /* eDMA1 channel 23 interrupt */
#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXTINT + 120) /* eDMA1 channel 24 interrupt */
#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXTINT + 121) /* eDMA1 channel 25 interrupt */
#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXTINT + 122) /* eDMA1 channel 26 interrupt */
#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXTINT + 123) /* eDMA1 channel 27 interrupt */
#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXTINT + 124) /* eDMA1 channel 28 interrupt */
#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXTINT + 125) /* eDMA1 channel 29 interrupt */
#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXTINT + 126) /* eDMA1 channel 30 interrupt */
#define IMX9_IRQ_DMA5_2_ERROR (IMX9_IRQ_EXTINT + 127) /* eDMA2 error interrupt */
#define IMX9_IRQ_DMA5_2_0_1 (IMX9_IRQ_EXTINT + 128) /* eDMA2 channel 0/1 interrupt */
#define IMX9_IRQ_DMA5_2_2_3 (IMX9_IRQ_EXTINT + 129) /* eDMA2 channel 2/3 interrupt */
#define IMX9_IRQ_DMA5_2_4_5 (IMX9_IRQ_EXTINT + 130) /* eDMA2 channel 4/5 interrupt */
#define IMX9_IRQ_DMA5_2_6_7 (IMX9_IRQ_EXTINT + 131) /* eDMA2 channel 6/7 interrupt */
#define IMX9_IRQ_DMA5_2_8_9 (IMX9_IRQ_EXTINT + 132) /* eDMA2 channel 8/9 interrupt */
#define IMX9_IRQ_DMA5_2_10_11 (IMX9_IRQ_EXTINT + 133) /* eDMA2 channel 10/11 interrupt */
#define IMX9_IRQ_DMA5_2_12_13 (IMX9_IRQ_EXTINT + 134) /* eDMA2 channel 12/13 interrupt */
#define IMX9_IRQ_DMA5_2_14_15 (IMX9_IRQ_EXTINT + 135) /* eDMA2 channel 14/15 interrupt */
#define IMX9_IRQ_DMA5_2_16_17 (IMX9_IRQ_EXTINT + 136) /* eDMA2 channel 16/17 interrupt */
#define IMX9_IRQ_DMA5_2_18_19 (IMX9_IRQ_EXTINT + 137) /* eDMA2 channel 18/19 interrupt */
#define IMX9_IRQ_DMA5_2_20_21 (IMX9_IRQ_EXTINT + 138) /* eDMA2 channel 20/21 interrupt */
#define IMX9_IRQ_DMA5_2_22_23 (IMX9_IRQ_EXTINT + 139) /* eDMA2 channel 22/23 interrupt */
#define IMX9_IRQ_DMA5_2_24_25 (IMX9_IRQ_EXTINT + 140) /* eDMA2 channel 24/25 interrupt */
#define IMX9_IRQ_DMA5_2_26_27 (IMX9_IRQ_EXTINT + 141) /* eDMA2 channel 26/27 interrupt */
#define IMX9_IRQ_DMA5_2_28_29 (IMX9_IRQ_EXTINT + 142) /* eDMA2 channel 28/29 interrupt */
#define IMX9_IRQ_DMA5_2_30_31 (IMX9_IRQ_EXTINT + 143) /* eDMA2 channel 30/31 interrupt */
#define IMX9_IRQ_DMA5_2_32_33 (IMX9_IRQ_EXTINT + 144) /* eDMA2 channel 32/33 interrupt */
#define IMX9_IRQ_DMA5_2_34_35 (IMX9_IRQ_EXTINT + 145) /* eDMA2 channel 34/35 interrupt */
#define IMX9_IRQ_DMA5_2_36_37 (IMX9_IRQ_EXTINT + 146) /* eDMA2 channel 36/37 interrupt */
#define IMX9_IRQ_DMA5_2_38_39 (IMX9_IRQ_EXTINT + 147) /* eDMA2 channel 38/39 interrupt */
#define IMX9_IRQ_DMA5_2_40_41 (IMX9_IRQ_EXTINT + 148) /* eDMA2 channel 40/41 interrupt */
#define IMX9_IRQ_DMA5_2_42_43 (IMX9_IRQ_EXTINT + 149) /* eDMA2 channel 42/43 interrupt */
#define IMX9_IRQ_DMA5_2_44_45 (IMX9_IRQ_EXTINT + 150) /* eDMA2 channel 44/45 interrupt */
#define IMX9_IRQ_DMA5_2_46_47 (IMX9_IRQ_EXTINT + 151) /* eDMA2 channel 46/47 interrupt */
#define IMX9_IRQ_DMA5_2_48_49 (IMX9_IRQ_EXTINT + 152) /* eDMA2 channel 48/49 interrupt */
#define IMX9_IRQ_DMA5_2_50_51 (IMX9_IRQ_EXTINT + 153) /* eDMA2 channel 50/51 interrupt */
#define IMX9_IRQ_DMA5_2_52_53 (IMX9_IRQ_EXTINT + 154) /* eDMA2 channel 52/53 interrupt */
#define IMX9_IRQ_DMA5_2_54_55 (IMX9_IRQ_EXTINT + 155) /* eDMA2 channel 54/55 interrupt */
#define IMX9_IRQ_DMA5_2_56_57 (IMX9_IRQ_EXTINT + 156) /* eDMA2 channel 56/57 interrupt */
#define IMX9_IRQ_DMA5_2_58_59 (IMX9_IRQ_EXTINT + 157) /* eDMA2 channel 58/59 interrupt */
#define IMX9_IRQ_DMA5_2_60_61 (IMX9_IRQ_EXTINT + 158) /* eDMA2 channel 60/61 interrupt */
#define IMX9_IRQ_DMA5_2_62_63 (IMX9_IRQ_EXTINT + 159) /* eDMA2 channel 62/63 interrupt */
#define IMX9_IRQ_RESERVED176 (IMX9_IRQ_EXTINT + 160) /* Sentinel Group 1 reset source if no s500 reference clock is detected. Output synchronized to 32khz clk. */
#define IMX9_IRQ_RESERVED177 (IMX9_IRQ_EXTINT + 161) /* Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */
#define IMX9_IRQ_RESERVED178 (IMX9_IRQ_EXTINT + 162) /* Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */
#define IMX9_IRQ_RESERVED179 (IMX9_IRQ_EXTINT + 163) /* JTAGSW DAP MDM-AP SRC reset source */
#define IMX9_IRQ_RESERVED180 (IMX9_IRQ_EXTINT + 164) /* JTAGC SRC reset source */
#define IMX9_IRQ_RESERVED181 (IMX9_IRQ_EXTINT + 165) /* CM33 SYSREQRST SRC reset source */
#define IMX9_IRQ_RESERVED182 (IMX9_IRQ_EXTINT + 166) /* CM33 LOCKUP SRC reset source */
#define IMX9_IRQ_RESERVED183 (IMX9_IRQ_EXTINT + 167) /* CM7 SYSREQRST SRC reset source */
#define IMX9_IRQ_RESERVED184 (IMX9_IRQ_EXTINT + 168) /* CM7 LOCKUP SRC reset source */
#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXTINT + 169) /* Serial Audio Interface 2 */
#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXTINT + 170) /* Serial Audio Interface 3 */
#define IMX9_IRQ_SAI4 (IMX9_IRQ_EXTINT + 171) /* Serial Audio Interface 4 */
#define IMX9_IRQ_SAI5 (IMX9_IRQ_EXTINT + 172) /* Serial Audio Interface 5 */
#define IMX9_IRQ_RESERVED189 (IMX9_IRQ_EXTINT + 173) /* USB-1 Wake-up Interrupt */
#define IMX9_IRQ_RESERVED190 (IMX9_IRQ_EXTINT + 174) /* USB-2 Wake-up Interrupt */
#define IMX9_IRQ_USB1 (IMX9_IRQ_EXTINT + 175) /* USB-1 Interrupt */
#define IMX9_IRQ_USB2 (IMX9_IRQ_EXTINT + 176) /* USB-2 Interrupt */
#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXTINT + 177) /* Low Power Serial Peripheral Interface 5 */
#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXTINT + 178) /* Low Power Serial Peripheral Interface 6 */
#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXTINT + 179) /* Low Power Serial Peripheral Interface 7 */
#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXTINT + 180) /* Low Power Serial Peripheral Interface 8 */
#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXTINT + 181) /* Low Power Inter-Integrated Circuit module 5 */
#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXTINT + 182) /* Low Power Inter-Integrated Circuit module 6 */
#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXTINT + 183) /* Low Power Inter-Integrated Circuit module 7 */
#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXTINT + 184) /* Low Power Inter-Integrated Circuit module 8 */
#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXTINT + 185) /* PDM interrupt */
#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXTINT + 186) /* PDM interrupt */
#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXTINT + 187) /* PDM interrupt */
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 188) /* PDM interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 189) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 190) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 192) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXTINT + 193) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 194) /* CM33 MCM interrupt */
#define IMX9_IRQ_RESERVED211 (IMX9_IRQ_EXTINT + 195) /* ANAMIX SFA interrupt */
#define IMX9_IRQ_RESERVED212 (IMX9_IRQ_EXTINT + 196) /* GIC700 Fault */
#define IMX9_IRQ_RESERVED213 (IMX9_IRQ_EXTINT + 197) /* GIC700 Error */
#define IMX9_IRQ_RESERVED214 (IMX9_IRQ_EXTINT + 198) /* GIC700 PMU Counter Overflow */
#define IMX9_IRQ_ADC_ER (IMX9_IRQ_EXTINT + 199) /* ADC interrupt */
#define IMX9_IRQ_ADC_WD (IMX9_IRQ_EXTINT + 200) /* ADC interrupt */
#define IMX9_IRQ_ADC_EOC (IMX9_IRQ_EXTINT + 201) /* ADC interrupt */
#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXTINT + 202) /* s500 glue logic IRQ */
#define IMX9_IRQ_RESERVED219 (IMX9_IRQ_EXTINT + 203) /* I3C1 wakeup irq after double sync */
#define IMX9_IRQ_RESERVED220 (IMX9_IRQ_EXTINT + 204) /* I3C2 wakeup irq after double sync */
#define IMX9_IRQ_MU5_A (IMX9_IRQ_EXTINT + 205) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU6_A (IMX9_IRQ_EXTINT + 206) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU7_B (IMX9_IRQ_EXTINT + 207) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU8_B (IMX9_IRQ_EXTINT + 208) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_RESERVED225 (IMX9_IRQ_EXTINT + 209) /* WAKEUPMIX XSPI Responder */
#define IMX9_IRQ_RESERVED226 (IMX9_IRQ_EXTINT + 210) /* AONMIX FCCU Interrupt Reaction 0 */
#define IMX9_IRQ_RESERVED227 (IMX9_IRQ_EXTINT + 211) /* AONMIX FCCU Interrupt Reaction 1 */
#define IMX9_IRQ_RESERVED228 (IMX9_IRQ_EXTINT + 212) /* AONMIX FCCU Interrupt Reaction 2 */
#define IMX9_IRQ_RESERVED229 (IMX9_IRQ_EXTINT + 213) /* AONMIX STCU Selftest end Interrupt */
#define IMX9_IRQ_DISP_IRQSTEER0 (IMX9_IRQ_EXTINT + 214) /* DISPLAYMIX IRQSTEER 0 */
#define IMX9_IRQ_DISP_IRQSTEER1 (IMX9_IRQ_EXTINT + 215) /* DISPLAYMIX IRQSTEER 1 */
#define IMX9_IRQ_DISP_IRQSTEER2 (IMX9_IRQ_EXTINT + 216) /* DISPLAYMIX IRQSTEER 2 */
#define IMX9_IRQ_DISP_IRQSTEER3 (IMX9_IRQ_EXTINT + 217) /* DISPLAYMIX IRQSTEER 3 */
#define IMX9_IRQ_DISP_IRQSTEER4 (IMX9_IRQ_EXTINT + 218) /* DISPLAYMIX IRQSTEER 4 */
#define IMX9_IRQ_DISP_IRQSTEER7 (IMX9_IRQ_EXTINT + 219) /* DISPLAYMIX IRQSTEER 7 */
#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXTINT + 220) /* CAMERAMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_ISI (IMX9_IRQ_EXTINT + 221) /* CAMERAMIX ISI interrupt Channel 0 */
#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXTINT + 222) /* ISP Processing Interrupt - Context 0 */
#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXTINT + 223) /* M7MIX MCM interrupt */
#define IMX9_IRQ_IRQSTEER_0 (IMX9_IRQ_EXTINT + 224) /* IRQSTEER0 interrupt */
#define IMX9_IRQ_IRQSTEER_1 (IMX9_IRQ_EXTINT + 225) /* IRQSTEER1 interrupt */
#define IMX9_IRQ_IRQSTEER_2 (IMX9_IRQ_EXTINT + 226) /* IRQSTEER2 interrupt */
#define IMX9_IRQ_IRQSTEER_3 (IMX9_IRQ_EXTINT + 227) /* IRQSTEER3 interrupt */
#define IMX9_IRQ_IRQSTEER_4 (IMX9_IRQ_EXTINT + 228) /* IRQSTEER4 interrupt */
#define IMX9_IRQ_IRQSTEER_5 (IMX9_IRQ_EXTINT + 229) /* IRQSTEER5 interrupt */
#define IMX9_IRQ_IRQSTEER_6 (IMX9_IRQ_EXTINT + 230) /* IRQSTEER6 interrupt */
#define IMX9_IRQ_IRQSTEER_7 (IMX9_IRQ_EXTINT + 231) /* IRQSTEER7 interrupt */
#define IMX9_IRQ_IRQSTEER_8 (IMX9_IRQ_EXTINT + 232) /* IRQSTEER8 interrupt */
#define IMX9_IRQ_IRQSTEER_9 (IMX9_IRQ_EXTINT + 233) /* IRQSTEER9 interrupt */
#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXTINT + 234) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXTINT + 235) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXTINT + 236) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXTINT + 237) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU3_A (IMX9_IRQ_EXTINT + 238) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU3_B (IMX9_IRQ_EXTINT + 239) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU4_A (IMX9_IRQ_EXTINT + 240) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU4_B (IMX9_IRQ_EXTINT + 241) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU5_B (IMX9_IRQ_EXTINT + 242) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU6_B (IMX9_IRQ_EXTINT + 243) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU7_A (IMX9_IRQ_EXTINT + 244) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU8_A (IMX9_IRQ_EXTINT + 245) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MSGINTR1 (IMX9_IRQ_EXTINT + 246) /* MSGINTR Instance 1, Interrupt */
#define IMX9_IRQ_MSGINTR2 (IMX9_IRQ_EXTINT + 247) /* MSGINTR Instance 2, Interrupts */
#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXTINT + 248) /* V2X-FH MU APCH1 (APP1) interrupt */
#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXTINT + 249) /* V2X-FH MU APHSM2 (HSM2) interrupt */
#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXTINT + 250) /* CAMERAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXTINT + 251) /* DISPLAYMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXTINT + 252) /* NETCMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXTINT + 253) /* GPUMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXTINT + 254) /* HSIOMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXTINT + 255) /* VPUMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXTINT + 256) /* AONMIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXTINT + 257) /* M7MIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXTINT + 258) /* WAKEUPMIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXTINT + 259) /* NPUMIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXTINT + 260) /* WAKEUPMIX ACP EDMA error interrupt */
#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXTINT + 261) /* OCRAM_C ECC multiple bit or address error */
#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXTINT + 262) /* CAMERAMIX Cortex-M0+ Cache write-buffer error */
#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXTINT + 263) /* CAMERAMIX Cortex-M0+ Cache data parity error */
#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXTINT + 264) /* V2X-FH MU APSHE (SHE) interrupt */
#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXTINT + 265) /* V2X-FH MU SCU/APDEBUG (DEBUG) interrupt */
#define IMX9_IRQ_DMA5_3_0_1 (IMX9_IRQ_EXTINT + 266) /* eDMA3 channel 0/1 interrupt */
#define IMX9_IRQ_DMA5_3_2_3 (IMX9_IRQ_EXTINT + 267) /* eDMA3 channel 2/3 interrupt */
#define IMX9_IRQ_DMA5_3_4_5 (IMX9_IRQ_EXTINT + 268) /* eDMA3 channel 4/5 interrupt */
#define IMX9_IRQ_DMA5_3_6_7 (IMX9_IRQ_EXTINT + 269) /* eDMA3 channel 6/7 interrupt */
#define IMX9_IRQ_DMA5_3_8_9 (IMX9_IRQ_EXTINT + 270) /* eDMA3 channel 8/9 interrupt */
#define IMX9_IRQ_DMA5_3_10_11 (IMX9_IRQ_EXTINT + 271) /* eDMA3 channel 10/11 interrupt */
#define IMX9_IRQ_DMA5_3_12_13 (IMX9_IRQ_EXTINT + 272) /* eDMA3 channel 12/13 interrupt */
#define IMX9_IRQ_DMA5_3_14_15 (IMX9_IRQ_EXTINT + 273) /* eDMA3 channel 14/15 interrupt */
#define IMX9_IRQ_DMA5_3_16_17 (IMX9_IRQ_EXTINT + 274) /* eDMA3 channel 16/17 interrupt */
#define IMX9_IRQ_DMA5_3_18_19 (IMX9_IRQ_EXTINT + 275) /* eDMA3 channel 18/19 interrupt */
#define IMX9_IRQ_DMA5_3_20_21 (IMX9_IRQ_EXTINT + 276) /* eDMA3 channel 20/21 interrupt */
#define IMX9_IRQ_DMA5_3_22_23 (IMX9_IRQ_EXTINT + 277) /* eDMA3 channel 22/23 interrupt */
#define IMX9_IRQ_DMA5_3_24_25 (IMX9_IRQ_EXTINT + 278) /* eDMA3 channel 24/25 interrupt */
#define IMX9_IRQ_DMA5_3_26_27 (IMX9_IRQ_EXTINT + 279) /* eDMA3 channel 26/27 interrupt */
#define IMX9_IRQ_DMA5_3_28_29 (IMX9_IRQ_EXTINT + 280) /* eDMA3 channel 29/29 interrupt */
#define IMX9_IRQ_DMA5_3_30_31 (IMX9_IRQ_EXTINT + 281) /* eDMA3 channel 30/31 interrupt */
#define IMX9_IRQ_DMA5_3_32_33 (IMX9_IRQ_EXTINT + 282) /* eDMA3 channel 32/33 interrupt */
#define IMX9_IRQ_DMA5_3_34_35 (IMX9_IRQ_EXTINT + 283) /* eDMA3 channel 34/35 interrupt */
#define IMX9_IRQ_DMA5_3_36_37 (IMX9_IRQ_EXTINT + 284) /* eDMA3 channel 36/37 interrupt */
#define IMX9_IRQ_DMA5_3_38_39 (IMX9_IRQ_EXTINT + 285) /* eDMA3 channel 38/39 interrupt */
#define IMX9_IRQ_DMA5_3_40_41 (IMX9_IRQ_EXTINT + 286) /* eDMA3 channel 40/41 interrupt */
#define IMX9_IRQ_DMA5_3_42_43 (IMX9_IRQ_EXTINT + 287) /* eDMA3 channel 42/43 interrupt */
#define IMX9_IRQ_DMA5_3_44_45 (IMX9_IRQ_EXTINT + 288) /* eDMA3 channel 44/45 interrupt */
#define IMX9_IRQ_DMA5_3_46_47 (IMX9_IRQ_EXTINT + 289) /* eDMA3 channel 46/47 interrupt */
#define IMX9_IRQ_DMA5_3_48_49 (IMX9_IRQ_EXTINT + 290) /* eDMA3 channel 48/49 interrupt */
#define IMX9_IRQ_DMA5_3_50_51 (IMX9_IRQ_EXTINT + 291) /* eDMA3 channel 50/51 interrupt */
#define IMX9_IRQ_DMA5_3_52_53 (IMX9_IRQ_EXTINT + 292) /* eDMA3 channel 52/53 interrupt */
#define IMX9_IRQ_DMA5_3_54_55 (IMX9_IRQ_EXTINT + 293) /* eDMA3 channel 54/55 interrupt */
#define IMX9_IRQ_DMA5_3_56_57 (IMX9_IRQ_EXTINT + 294) /* eDMA3 channel 56/57 interrupt */
#define IMX9_IRQ_DMA5_3_58_59 (IMX9_IRQ_EXTINT + 295) /* eDMA3 channel 58/59 interrupt */
#define IMX9_IRQ_DMA5_3_60_61 (IMX9_IRQ_EXTINT + 296) /* eDMA3 channel 60/61 interrupt */
#define IMX9_IRQ_DMA5_3_62_63 (IMX9_IRQ_EXTINT + 297) /* eDMA3 channel 62/63 interrupt */
#define IMX9_IRQ_RESERVED314 (IMX9_IRQ_EXTINT + 298) /* GPUMIX GPU Interrupt */
#define IMX9_IRQ_RESERVED315 (IMX9_IRQ_EXTINT + 299) /* GPUMIX Job Interrupt */
#define IMX9_IRQ_RESERVED316 (IMX9_IRQ_EXTINT + 300) /* GPUMIX MMU Interrupt */
#define IMX9_IRQ_RESERVED317 (IMX9_IRQ_EXTINT + 301) /* Reserved INTERRUPT */
#define IMX9_IRQ_RESERVED318 (IMX9_IRQ_EXTINT + 302) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED319 (IMX9_IRQ_EXTINT + 303) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED320 (IMX9_IRQ_EXTINT + 304) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED321 (IMX9_IRQ_EXTINT + 305) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED322 (IMX9_IRQ_EXTINT + 306) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED323 (IMX9_IRQ_EXTINT + 307) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED324 (IMX9_IRQ_EXTINT + 308) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED325 (IMX9_IRQ_EXTINT + 309) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED326 (IMX9_IRQ_EXTINT + 310) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED327 (IMX9_IRQ_EXTINT + 311) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED328 (IMX9_IRQ_EXTINT + 312) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED329 (IMX9_IRQ_EXTINT + 313) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED330 (IMX9_IRQ_EXTINT + 314) /* NETC iEPRC PCI INT */
#define IMX9_IRQ_RESERVED331 (IMX9_IRQ_EXTINT + 315) /* NETC iEPRC PCI INT */
#define IMX9_IRQ_RESERVED332 (IMX9_IRQ_EXTINT + 316) /* PCIe Controller 1 INTA */
#define IMX9_IRQ_RESERVED333 (IMX9_IRQ_EXTINT + 317) /* PCIe Controller 1 INTB */
#define IMX9_IRQ_RESERVED334 (IMX9_IRQ_EXTINT + 318) /* PCIe Controller 1 INTC */
#define IMX9_IRQ_RESERVED335 (IMX9_IRQ_EXTINT + 319) /* PCIe Controller 1 INTD */
#define IMX9_IRQ_RESERVED336 (IMX9_IRQ_EXTINT + 320) /* PCIe interrupts */
#define IMX9_IRQ_RESERVED337 (IMX9_IRQ_EXTINT + 321) /* PCIe Controller EDMA channel interrupt */
#define IMX9_IRQ_RESERVED338 (IMX9_IRQ_EXTINT + 322) /* PCIe Controller 1 INTA */
#define IMX9_IRQ_RESERVED339 (IMX9_IRQ_EXTINT + 323) /* PCIe Controller 1 INTB */
#define IMX9_IRQ_RESERVED340 (IMX9_IRQ_EXTINT + 324) /* PCIe Controller 1 INTC */
#define IMX9_IRQ_RESERVED341 (IMX9_IRQ_EXTINT + 325) /* PCIe Controller 1 INTD */
#define IMX9_IRQ_RESERVED342 (IMX9_IRQ_EXTINT + 326) /* PCIe miscellaneous interrupts */
#define IMX9_IRQ_RESERVED343 (IMX9_IRQ_EXTINT + 327) /* PCIe Controller EDMA channel interrupt */
#define IMX9_IRQ_RESERVED344 (IMX9_IRQ_EXTINT + 328) /* Wakeup interrupt from CLKREQ#, WAKEUP#, BEACON_DET */
#define IMX9_IRQ_RESERVED345 (IMX9_IRQ_EXTINT + 329) /* NPUMIX Functional interrupt */
#define IMX9_IRQ_RESERVED346 (IMX9_IRQ_EXTINT + 330) /* DISPLAYMIX Real-time traffic TBU: Fault Handling RAS Interrupt for a contained error */
#define IMX9_IRQ_RESERVED347 (IMX9_IRQ_EXTINT + 331) /* DISPLAYMIX Real-time traffic TBU: Error Handling RAS Interrupt for an uncontained error */
#define IMX9_IRQ_RESERVED348 (IMX9_IRQ_EXTINT + 332) /* DISPLAYMIX Real-time traffic TBU: Critical Error Interrupt for an uncontainable error */
#define IMX9_IRQ_RESERVED349 (IMX9_IRQ_EXTINT + 333) /* DISPLAYMIX Real-time traffic TBU: PMU Interrupt */
#define IMX9_IRQ_RESERVED350 (IMX9_IRQ_EXTINT + 334) /* TCU Event queue, secure interrupt */
#define IMX9_IRQ_RESERVED351 (IMX9_IRQ_EXTINT + 335) /* TCU Event queue, non-secure interrupt */
#define IMX9_IRQ_RESERVED352 (IMX9_IRQ_EXTINT + 336) /* TCU SYNC complete, non-secure interrupt */
#define IMX9_IRQ_RESERVED353 (IMX9_IRQ_EXTINT + 337) /* TCU SYNC complete, secure interrupt */
#define IMX9_IRQ_RESERVED354 (IMX9_IRQ_EXTINT + 338) /* TCU global non-secure interrupt */
#define IMX9_IRQ_RESERVED355 (IMX9_IRQ_EXTINT + 339) /* TCU global secure interrupt */
#define IMX9_IRQ_RESERVED356 (IMX9_IRQ_EXTINT + 340) /* TCU fault handling RAS interrupt for a contained error */
#define IMX9_IRQ_RESERVED357 (IMX9_IRQ_EXTINT + 341) /* TCU error recovery RAS interrupt for an uncontained error */
#define IMX9_IRQ_RESERVED358 (IMX9_IRQ_EXTINT + 342) /* TCU critical error interrupt, for an uncontainable uncorrected error */
#define IMX9_IRQ_RESERVED359 (IMX9_IRQ_EXTINT + 343) /* TCU PMU interrupt */
#define IMX9_IRQ_RESERVED360 (IMX9_IRQ_EXTINT + 344) /* TCU Page Request Interface */
#define IMX9_IRQ_RESERVED361 (IMX9_IRQ_EXTINT + 345) /* SRC GPC Low Power Handshake Gasket interrupt request for system management */
#define IMX9_IRQ_RESERVED362 (IMX9_IRQ_EXTINT + 346) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED363 (IMX9_IRQ_EXTINT + 347) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED364 (IMX9_IRQ_EXTINT + 348) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED365 (IMX9_IRQ_EXTINT + 349) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED366 (IMX9_IRQ_EXTINT + 350) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED367 (IMX9_IRQ_EXTINT + 351) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED368 (IMX9_IRQ_EXTINT + 352) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED369 (IMX9_IRQ_EXTINT + 353) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED370 (IMX9_IRQ_EXTINT + 354) /* CAMERAMIX ISI interrupt Channel 1 */
#define IMX9_IRQ_RESERVED371 (IMX9_IRQ_EXTINT + 355) /* CAMERAMIX ISI interrupt Channel 2 */
#define IMX9_IRQ_RESERVED372 (IMX9_IRQ_EXTINT + 356) /* CAMERAMIX ISI interrupt Channel 3 */
#define IMX9_IRQ_RESERVED373 (IMX9_IRQ_EXTINT + 357) /* CAMERAMIX ISI interrupt Channel 4 */
#define IMX9_IRQ_RESERVED374 (IMX9_IRQ_EXTINT + 358) /* CAMERAMIX ISI interrupt Channel 5 */
#define IMX9_IRQ_RESERVED375 (IMX9_IRQ_EXTINT + 359) /* CAMERAMIX ISI interrupt Channel 6 */
#define IMX9_IRQ_RESERVED376 (IMX9_IRQ_EXTINT + 360) /* CAMERAMIX ISI interrupt Channel 7 */
#define IMX9_IRQ_DMA5_4_ERROR (IMX9_IRQ_EXTINT + 361) /* CAMERAMIX EDMA error interrupt */
#define IMX9_IRQ_DMA5_4_0_1 (IMX9_IRQ_EXTINT + 362) /* CAMERAMIX EDMA channel 0 interrupt */
#define IMX9_IRQ_DMA5_4_2_3 (IMX9_IRQ_EXTINT + 363) /* CAMERAMIX EDMA channel 2 interrupt */
#define IMX9_IRQ_DMA5_4_4_5 (IMX9_IRQ_EXTINT + 364) /* CAMERAMIX EDMA channel 4 interrupt */
#define IMX9_IRQ_DMA5_4_6_7 (IMX9_IRQ_EXTINT + 365) /* CAMERAMIX EDMA channel 6 interrupt */
#define IMX9_IRQ_DMA5_4_8_9 (IMX9_IRQ_EXTINT + 366) /* CAMERAMIX EDMA channel 8 interrupt */
#define IMX9_IRQ_DMA5_4_10_11 (IMX9_IRQ_EXTINT + 367) /* CAMERAMIX EDMA channel 10 interrupt */
#define IMX9_IRQ_DMA5_4_12_13 (IMX9_IRQ_EXTINT + 368) /* CAMERAMIX EDMA channel 12 interrupt */
#define IMX9_IRQ_DMA5_4_14_15 (IMX9_IRQ_EXTINT + 369) /* CAMERAMIX EDMA channel 14 interrupt */
#define IMX9_IRQ_DMA5_4_16_17 (IMX9_IRQ_EXTINT + 370) /* CAMERAMIX EDMA channel 16 interrupt */
#define IMX9_IRQ_DMA5_4_18_19 (IMX9_IRQ_EXTINT + 371) /* CAMERAMIX EDMA channel 18 interrupt */
#define IMX9_IRQ_DMA5_4_20_21 (IMX9_IRQ_EXTINT + 372) /* CAMERAMIX EDMA channel 20 interrupt */
#define IMX9_IRQ_DMA5_4_22_23 (IMX9_IRQ_EXTINT + 373) /* CAMERAMIX EDMA channel 22 interrupt */
#define IMX9_IRQ_DMA5_4_24_25 (IMX9_IRQ_EXTINT + 374) /* CAMERAMIX EDMA channel 24 interrupt */
#define IMX9_IRQ_DMA5_4_26_27 (IMX9_IRQ_EXTINT + 375) /* CAMERAMIX EDMA channel 26 interrupt */
#define IMX9_IRQ_DMA5_4_28_29 (IMX9_IRQ_EXTINT + 376) /* CAMERAMIX EDMA channel 28 interrupt */
#define IMX9_IRQ_DMA5_4_30_31 (IMX9_IRQ_EXTINT + 377) /* CAMERAMIX EDMA channel 30 interrupt */
#define IMX9_IRQ_RESERVED394 (IMX9_IRQ_EXTINT + 378) /* CAMERAMIX CSI Formatting Unit 1: Buffer overflow */
#define IMX9_IRQ_RESERVED395 (IMX9_IRQ_EXTINT + 379) /* CAMERAMIX CSI Formatting Unit 1: Interlaced Error */
#define IMX9_IRQ_RESERVED396 (IMX9_IRQ_EXTINT + 380) /* CAMERAMIX CSI Formatting Unit 1: Pixel Data Type Error */
#define IMX9_IRQ_RESERVED397 (IMX9_IRQ_EXTINT + 381) /* CAMERAMIX CSI Formatting Unit 2: Buffer overflow */
#define IMX9_IRQ_RESERVED398 (IMX9_IRQ_EXTINT + 382) /* CAMERAMIX CSI Formatting Unit 2: Interlaced Error */
#define IMX9_IRQ_RESERVED399 (IMX9_IRQ_EXTINT + 383) /* CAMERAMIX CSI Formatting Unit 2: Pixel Data Type Error */
#define IMX9_IRQ_RESERVED400 (IMX9_IRQ_EXTINT + 384) /* CAMERAMIX CSI1 */
#define IMX9_IRQ_RESERVED401 (IMX9_IRQ_EXTINT + 385) /* CAMERAMIX CSI2 */
#define IMX9_IRQ_NEXTINT (218)
/* Total amount of entries in system vector table */
#define NR_IRQS (IMX9_IRQ_EXTINT + IMX9_IRQ_NEXTINT)
#endif /* __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H */

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/****************************************************************************
* arch/arm/include/imx9/irq.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_IMX9_IRQ_H
#define __ARCH_ARM_INCLUDE_IMX9_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include <arch/imx9/imx95_irq.h>
#else
# error "Unrecognized i.MX9 architecture"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words
* of memory in the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define IMX9_IRQ_RESERVED (0) /* Reserved vector .. only used with
* CONFIG_DEBUG_FEATURES */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset(not handled by IRQ) */
#define IMX9_IRQ_NMI (2) /* Vector 2: Non-Maskable Int (NMI) */
#define IMX9_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define IMX9_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define IMX9_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define IMX9_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define IMX9_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define IMX9_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define IMX9_IRQ_PENDSV (14) /* Vector 14: Pendable SSR */
#define IMX9_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define IMX9_IRQ_EXTINT (16) /* Vector number of the first ext int */
#define ARMV7M_PERIPHERAL_INTERRUPTS IMX9_IRQ_NEXTINT
#endif /* __ARCH_ARM_INCLUDE_IMX9_IRQ_H */

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arch/arm/src/imx9/CMakeLists.txt Normal file
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# ##############################################################################
# arch/arm/src/imx9/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS
imx9_allocateheap.c
imx9_start.c
imx9_clockconfig.c
imx9_gpio.c
imx9_iomuxc.c
imx9_irq.c
imx9_timerisr.c
imx9_idle.c)
if(CONFIG_IMX9_SCMI)
list(APPEND SRCS imx9_scmi.c)
# NXP SDK SCMI interface for pinctrl and clocking
endif()
if(CONFIG_RPTUN)
list(APPEND SRCS imx9_rsctable.c imx9_rptun.c)
endif()
if(CONFIG_IMX9_MU)
list(APPEND SRCS imx9_mu.c)
endif()
if(CONFIG_ARM_MPU)
list(APPEND SRCS imx9_mpuinit.c)
endif()
if(CONFIG_IMX9_FLEXCAN)
list(APPEND SRCS imx9_flexcan.c)
endif()
if(CONFIG_IMX9_LPUART)
list(APPEND SRCS imx9_lpuart.c imx9_lowputc.c)
endif()
if(CONFIG_IMX9_GPIO_IRQ)
list(APPEND SRCS imx9_gpioirq.c)
endif()
if(CONFIG_IMX9_FLEXIO_PWM)
list(APPEND SRCS imx9_flexio_pwm.c)
endif()
if(CONFIG_IMX9_TPM_PWM)
list(APPEND SRCS imx9_tpm_pwm.c)
endif()
if(CONFIG_IMX9_USBDEV)
list(APPEND SRCS imx9_usbdev.c)
endif()
if(CONFIG_IMX9_LPI2C)
list(APPEND SRCS imx9_lpi2c.c)
endif()
if(CONFIG_IMX9_LPSPI)
list(APPEND SRCS imx9_lpspi.c)
endif()
if(CONFIG_IMX9_EDMA)
list(APPEND SRCS imx9_edma.c)
endif()
target_sources(arch PRIVATE ${SRCS})

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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_IMX9_CORTEX_M
menu "i.MX9 Chip Selection"
choice
prompt "i.MX9 Core Configuration"
default ARCH_CHIP_IMX95_M7
config ARCH_CHIP_IMX95_M7
bool "i.MX95 Cortex-M7 Processor"
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM
select ARMV7M_HAVE_DTCM
select IMX9_HAVE_MU
endchoice # i.MX9 Chip Selection
endmenu # "i.MX9 Chip Selection"
config IMX9_HAVE_MU
bool
default n
config IMX9_SCMI
bool "SCMI Interface"
default y
depends on IMX9_MU5
if IMX9_SCMI
config IMX9_CLK_OVER_SCMI
bool "Configure CLK over SCMI"
default y
config IMX9_IOMUX_OVER_SCMI
bool "Configure IOMUX over SCMI"
default n
endif
menu "i.MX9 Peripheral Selection"
config IMX9_EDMA
bool "eDMA"
default n
select ARCH_DMA
menu "FLEXCAN Peripherals"
config IMX9_FLEXCAN
bool
default n
select NET_CAN_HAVE_TX_DEADLINE
select NET_CAN_HAVE_CANFD
config IMX9_FLEXCAN1
bool "FLEXCAN1"
default n
select IMX9_FLEXCAN
config IMX9_FLEXCAN2
bool "FLEXCAN2"
default n
select IMX9_FLEXCAN
config IMX9_FLEXCAN3
bool "FLEXCAN3"
default n
select IMX9_FLEXCAN
config IMX9_FLEXCAN4
bool "FLEXCAN4"
default n
select IMX9_FLEXCAN
config IMX9_FLEXCAN5
bool "FLEXCAN5"
default n
select IMX9_FLEXCAN
if IMX9_FLEXCAN
config IMX9_FLEXCAN_TXMB
int "Number of TX message buffers"
default 5
---help---
This defines number of TX messages buffers. Please note that
maximum number of all message buffers is 20
config IMX9_FLEXCAN_RXMB
int "Number of RX message buffers"
default 15
---help---
This defines number of RX messages buffers. Please note that
maximum number of all message buffers is 20
endif
endmenu # FLEXCAN Peripherals
menu "FLEXCAN1 Configuration"
depends on IMX9_FLEXCAN1
config FLEXCAN1_BITRATE
int "CAN bitrate"
depends on !(NET_CAN_CANFD)
default 1000000
config FLEXCAN1_SAMPLEP
int "CAN sample point"
depends on !(NET_CAN_CANFD)
default 80
config FLEXCAN1_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 1000000
config FLEXCAN1_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN1_DATA_BITRATE
int "CAN FD Data phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN1_DATA_SAMPLEP
int "CAN FD Data phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # IMX9_FLEXCAN1
menu "FLEXCAN2 Configuration"
depends on IMX9_FLEXCAN2
config FLEXCAN2_BITRATE
int "CAN bitrate"
depends on !(NET_CAN_CANFD && IMX9_FLEXCAN2_FD)
default 1000000
config FLEXCAN2_SAMPLEP
int "CAN sample point"
depends on !(NET_CAN_CANFD && IMX9_FLEXCAN2_FD)
default 80
config FLEXCAN2_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
default 1000000
config FLEXCAN2_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
default 80
config FLEXCAN2_DATA_BITRATE
int "CAN FD Data phase bitrate"
depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
default 4000000
config FLEXCAN2_DATA_SAMPLEP
int "CAN FD Data phase sample point"
depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
default 90
endmenu # IMX9_FLEXCAN2
menu "FLEXCAN3 Configuration"
depends on IMX9_FLEXCAN3
config FLEXCAN3_BITRATE
int "CAN bitrate"
depends on !NET_CAN_CANFD
default 1000000
config FLEXCAN3_SAMPLEP
int "CAN sample point"
depends on !NET_CAN_CANFD
default 80
config FLEXCAN3_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 1000000
config FLEXCAN3_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN3_DATA_BITRATE
int "CAN FD Data phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN3_DATA_SAMPLEP
int "CAN FD Data phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # IMX9_FLEXCAN3
menu "FLEXCAN4 Configuration"
depends on IMX9_FLEXCAN4
config FLEXCAN4_BITRATE
int "CAN bitrate"
depends on !(NET_CAN_CANFD)
default 4000000
config FLEXCAN4_SAMPLEP
int "CAN sample point"
depends on !(NET_CAN_CANFD)
default 80
config FLEXCAN4_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN4_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN4_DATA_BITRATE
int "CAN FD Data phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN4_DATA_SAMPLEP
int "CAN FD Data phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # IMX9_FLEXCAN4
menu "FLEXCAN5 Configuration"
depends on IMX9_FLEXCAN5
config FLEXCAN5_BITRATE
int "CAN bitrate"
depends on !(NET_CAN_CANFD)
default 5000000
config FLEXCAN5_SAMPLEP
int "CAN sample point"
depends on !(NET_CAN_CANFD)
default 80
config FLEXCAN5_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 5000000
config FLEXCAN5_ARBI_SAMPLEP
int "CAN FD Arbitration phase sample point"
depends on NET_CAN_CANFD
default 80
config FLEXCAN5_DATA_BITRATE
int "CAN FD Data phase bitrate"
depends on NET_CAN_CANFD
default 4000000
config FLEXCAN5_DATA_SAMPLEP
int "CAN FD Data phase sample point"
depends on NET_CAN_CANFD
default 90
endmenu # IMX9_FLEXCAN5
menu "LPUART"
config IMX9_LPUART
bool
default n
select ARCH_HAVE_SERIAL_TERMIOS
config IMX9_LPUART1
bool "LPUART1"
default n
select IMX9_LPUART
select LPUART1_SERIALDRIVER
config IMX9_LPUART2
bool "LPUART2"
default n
select IMX9_LPUART
select LPUART2_SERIALDRIVER
config IMX9_LPUART3
bool "LPUART3"
default n
select IMX9_LPUART
select LPUART3_SERIALDRIVER
config IMX9_LPUART4
bool "LPUART4"
default n
select IMX9_LPUART
select LPUART4_SERIALDRIVER
config IMX9_LPUART5
bool "LPUART5"
default n
select IMX9_LPUART
select LPUART5_SERIALDRIVER
config IMX9_LPUART6
bool "LPUART6"
default n
select IMX9_LPUART
select LPUART6_SERIALDRIVER
config IMX9_LPUART7
bool "LPUART7"
default n
select IMX9_LPUART
select LPUART7_SERIALDRIVER
config IMX9_LPUART8
bool "LPUART8"
default n
select IMX9_LPUART
select LPUART8_SERIALDRIVER
menu "LPUART Configuration"
depends on IMX9_LPUART
config IMX9_LPUART_INVERT
bool "Signal Invert Support"
default n
config IMX9_LPUART_SINGLEWIRE
bool "Signal Wire Support"
default n
config IMX9_SERIAL_RXDMA_BUFFER_SIZE
int "RX DMA buffer size"
default 64
depends on LPUART1_RXDMA || LPUART2_RXDMA || LPUART3_RXDMA || LPUART4_RXDMA || \
LPUART5_RXDMA || LPUART6_RXDMA || LPUART7_RXDMA || LPUART8_RXDMA
---help---
The DMA buffer size when using RX DMA to emulate a FIFO.
When streaming data, the generic serial layer will be called
every time the FIFO receives half this number of bytes.
Value given here will be rounded up to next multiple of 64 bytes.
endmenu # LPUART Configuration
endmenu # LPUART
config IMX9_GPIO_IRQ
bool "GPIO Interrupt Support"
default n
config IMX9_LPI2C
bool "LPI2C support"
default n
config IMX9_LPSPI
bool "LPSPI support"
default n
menu "LPI2C Peripherals"
menuconfig IMX9_LPI2C1
bool "LPI2C1"
default n
select IMX9_LPI2C
if IMX9_LPI2C1
config IMX9_LPI2C1_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C1_DMA
bool "Enable DMA for I2C1"
default n
depends on IMX9_LPI2C_DMA
config IMX9_LPI2C1_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C1_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C1
menuconfig IMX9_LPI2C2
bool "LPI2C2"
default n
select IMX9_LPI2C
if IMX9_LPI2C2
config IMX9_LPI2C2_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C2_DMA
bool "Enable DMA for I2C2"
default n
depends on IMX9_LPI2C_DMA
config IMX9_LPI2C2_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C2_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C2
menuconfig IMX9_LPI2C3
bool "LPI2C3"
default n
select IMX9_LPI2C
if IMX9_LPI2C3
config IMX9_LPI2C3_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C3_DMA
bool "Enable DMA for I2C3"
default n
depends on IMX9_LPI2C_DMA
config IMX9_LPI2C3_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C3_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C3
menuconfig IMX9_LPI2C4
bool "LPI2C4"
default n
select IMX9_LPI2C
if IMX9_LPI2C4
config IMX9_LPI2C4_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C4_DMA
bool "Enable DMA for I2C4"
default n
depends on IMX9_LPI2C_DMA
config IMX9_LPI2C4_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C4_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C4
menuconfig IMX9_LPI2C5
bool "LPI2C5"
default n
select IMX9_LPI2C
if IMX9_LPI2C5
config IMX9_LPI2C5_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C5_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C5_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C5
menuconfig IMX9_LPI2C6
bool "LPI2C6"
default n
select IMX9_LPI2C
if IMX9_LPI2C6
config IMX9_LPI2C6_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C6_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C6_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C6
menuconfig IMX9_LPI2C7
bool "LPI2C7"
default n
select IMX9_LPI2C
if IMX9_LPI2C7
config IMX9_LPI2C7_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C7_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C7_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C7
menuconfig IMX9_LPI2C8
bool "LPI2C8"
default n
select IMX9_LPI2C
if IMX9_LPI2C8
config IMX9_LPI2C8_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config IMX9_LPI2C8_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
config IMX9_LPI2C8_FILTSDA
int "I2C master digital glitch filters for SDA input in clock cycles"
default 0
endif # IMX9_LPI2C8
endmenu # LPI2C Peripherals
menu "LPSPI Peripherals"
menuconfig IMX9_LPSPI1
bool "LPSPI1"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI2
bool "LPSPI2"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI3
bool "LPSPI3"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI4
bool "LPSPI4"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI5
bool "LPSPI5"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI6
bool "LPSPI6"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI7
bool "LPSPI7"
default n
select IMX9_LPSPI
menuconfig IMX9_LPSPI8
bool "LPSPI8"
default n
select IMX9_LPSPI
endmenu # LPSPI Peripherals
menu "eDMA Configuration"
depends on IMX9_EDMA
config IMX9_EDMA_NTCD
int "Number of transfer descriptors"
default 0
---help---
Number of pre-allocated transfer descriptors. Needed for scatter-
gather DMA. Make to be set to zero to disable in-memory TCDs in
which case only the TCD channel registers will be used and scatter-
will not be supported.
config IMX9_EDMA_ELINK
bool "Channeling Linking"
default n
---help---
This option enables optional minor or major loop channel linking:
Minor loop channel linking: As the channel completes the minor
loop, this flag enables linking to another channel. The link target
channel initiates a channel service request via an internal
mechanism that sets the TCDn_CSR[START] bit of the specified
channel.
If minor loop channel linking is disabled, this link mechanism is
suppressed in favor of the major loop channel linking.
Major loop channel linking: As the channel completes the minor
loop, this option enables the linking to another channel. The link
target channel initiates a channel service request via an internal
mechanism that sets the TCDn_CSR[START] bit of the linked channel.
config IMX9_EDMA_ERCA
bool "Round Robin Channel Arbitration"
default n
---help---
Normally, a fixed priority arbitration is used for channel
selection. If this option is selected, round robin arbitration is
used for channel selection.
config IMX9_EDMA_HOE
bool "Halt On Error"
default y
---help---
Any error causes the HALT bit to set. Subsequently, all service
requests are ignored until the HALT bit is cleared.
config IMX9_EDMA_CLM
bool "Continuous Link Mode"
default n
---help---
By default, A minor loop channel link made to itself goes through
channel arbitration before being activated again. If this option is
selected, a minor loop channel link made to itself does not go
through channel arbitration before being activated again. Upon minor
loop completion, the channel activates again if that channel has a
minor loop channel link enabled and the link channel is itself. This
effectively applies the minor loop offsets and restarts the next
minor loop.
config IMX9_EDMA_EMLIM
bool "Minor Loop Mapping"
default n
---help---
Normally TCD word 2 is a 32-bit NBYTES field. When this option is
enabled, TCD word 2 is redefined to include individual enable fields,
an offset field, and the NBYTES field. The individual enable fields
allow the minor loop offset to be applied to the source address, the
destination address, or both. The NBYTES field is reduced when either
offset is enabled.
config IMX9_EDMA_EDBG
bool "Enable Debug"
default n
---help---
When in debug mode, the DMA stalls the start of a new channel. Executing
channels are allowed to complete. Channel execution resumes when the
system exits debug mode or the EDBG bit is cleared
endmenu # eDMA Global Configuration
menu "i.MX 95 Memory Configuration"
config IMX9_OCRAM_HEAP
bool "Add OCRAM to heap"
depends on !IMX9_OCRAM_PRIMARY
---help---
Select to add the entire OCRAM to the heap
config IMX9_INIT_ISRAM
bool "Calls out to the board code to set instruction RAM"
---help---
Some configuration will need to map instruction ram (ITCM)
this must be done prior to data/bss etc init.
endmenu # i.MX 95 Heap Configuration
menu "LPI2C Configuration"
depends on IMX9_LPI2C
config IMX9_LPI2C_DMA
bool "I2C DMA Support"
default n
depends on IMX9_LPI2C && IMX9_EDMA && !I2C_POLLED
---help---
This option enables the DMA for I2C transfers.
Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value
for the I2C dma streams, else the default priority level is set to
medium.
config IMX9_LPI2C_DMA_MAXMSG
int "Maximum number messages that will be DMAed"
default 8
depends on IMX9_LPI2C_DMA
---help---
This option set the mumber of mesg that can be in a transfer.
It is used to allocate space for the 16 bit LPI2C commands
that will be DMA-ed to the LPI2C device.
config IMX9_LPI2C_DYNTIMEO
bool "Use dynamic timeouts"
default n
depends on IMX9_LPI2C
config IMX9_LPI2C_DYNTIMEO_USECPERBYTE
int "Timeout Microseconds per Byte"
default 500
depends on IMX9_LPI2C_DYNTIMEO
config IMX9_LPI2C_DYNTIMEO_STARTSTOP
int "Timeout for Start/Stop (Milliseconds)"
default 1000
depends on IMX9_LPI2C_DYNTIMEO
config IMX9_LPI2C_TIMEOSEC
int "Timeout seconds"
default 0
depends on IMX9_LPI2C
config IMX9_LPI2C_TIMEOMS
int "Timeout Milliseconds"
default 500
depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO
config IMX9_LPI2C_TIMEOTICKS
int "Timeout for Done and Stop (ticks)"
default 500
depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO
endmenu # LPI2C Configuration
menu "LPSPI Configuration"
depends on IMX9_LPSPI
config IMX9_LPSPI_DMA
bool "LPSPI DMA"
depends on IMX9_EDMA
default n
---help---
Use DMA to improve LPSPI transfer performance.
config IMX9_LPSPI_DMATHRESHOLD
int "LPSPI DMA threshold"
default 4
depends on IMX9_LPSPI_DMA
---help---
When SPI DMA is enabled, small DMA transfers will still be performed
by polling logic. But we need a threshold value to determine what
is small.
config IMX9_LPSPI_HWPCS
bool "Use native hardware peripheral chip selects instead of GPIO pins"
default n
config IMX9_LPSPI1_DMA
bool "LPSPI1 DMA"
default n
depends on IMX9_LPSPI1 && IMX9_LPSPI_DMA
---help---
Use DMA to improve LPSPI1 transfer performance.
config IMX9_LPSPI2_DMA
bool "LPSPI2 DMA"
default n
depends on IMX9_LPSPI2 && IMX9_LPSPI_DMA
---help---
Use DMA to improve LPSPI2 transfer performance.
config IMX9_LPSPI3_DMA
bool "LPSPI3 DMA"
default n
depends on IMX9_LPSPI3 && IMX9_LPSPI_DMA
---help---
Use DMA to improve LPSPI3 transfer performance.
config IMX9_LPSPI4_DMA
bool "LPSPI4 DMA"
default n
depends on IMX9_LPSPI4 && IMX9_LPSPI_DMA
---help---
Use DMA to improve SPI4 transfer performance.
config IMX9_LPSPI5_DMA
bool "LPSPI5 DMA"
default n
depends on IMX9_LPSPI5 && IMX9_LPSPI_DMA
---help---
Use DMA to improve SPI5 transfer performance.
config IMX9_LPSPI6_DMA
bool "LPSPI6 DMA"
default n
depends on IMX9_LPSPI6 && IMX9_LPSPI_DMA
---help---
Use DMA to improve SPI6 transfer performance.
config IMX9_LPSPI7_DMA
bool "LPSPI7 DMA"
default n
depends on IMX9_LPSPI7 && IMX9_LPSPI_DMA
---help---
Use DMA to improve SPI7 transfer performance.
config IMX9_LPSPI8_DMA
bool "LPSPI8 DMA"
default n
depends on IMX9_LPSPI8 && IMX9_LPSPI_DMA
---help---
Use DMA to improve SPI8 transfer performance.
endmenu # LPSPI Configuration
menuconfig IMX9_MU
bool "Mailbox support"
default y
depends on IMX9_HAVE_MU
if IMX9_MU
config IMX9_MU5
bool "MU5 M7 <-> M33"
default y
---help---
Enable mailbox 5 that operates between M7 and M33 cores
config IMX9_MU7
bool "MU7 M7 <-> A55"
default n
---help---
Enable mailbox 7 that operates between M7 and A55 cores
config IMX9_MU8
bool "MU8 M7 <-> A55"
default n
---help---
Enable mailbox 5 that operates between M7 and A55 cores
endif # IMX9_MU Configuration
endmenu # iMX Peripheral Selection
endif # ARCH_CHIP_IMX9

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############################################################################
# arch/arm/src/imx9/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: 2024 NXP
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include armv7-m/Make.defs
# i.MX9-specific C source files
CHIP_CSRCS = imx9_allocateheap.c imx9_start.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c imx9_irq.c imx9_timerisr.c imx9_idle.c
ifeq ($(CONFIG_IMX9_SCMI),y)
CHIP_CSRCS += imx9_scmi.c
# NXP SDK SCMI interface for pinctrl and clocking
endif
ifeq ($(CONFIG_RPTUN),y)
CHIP_CSRCS += imx9_rsctable.c imx9_rptun.c
endif
ifeq ($(CONFIG_IMX9_MU),y)
CHIP_CSRCS += imx9_mu.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CHIP_CSRCS += imx9_mpuinit.c
endif
ifeq ($(CONFIG_IMX9_FLEXCAN),y)
CHIP_CSRCS += imx9_flexcan.c
endif
ifeq ($(CONFIG_IMX9_LPUART),y)
CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c
endif
ifeq ($(CONFIG_IMX9_GPIO_IRQ),y)
CHIP_CSRCS += imx9_gpioirq.c
endif
ifeq ($(CONFIG_IMX9_FLEXIO_PWM),y)
CHIP_CSRCS += imx9_flexio_pwm.c
endif
ifeq ($(CONFIG_IMX9_TPM_PWM),y)
CHIP_CSRCS += imx9_tpm_pwm.c
endif
ifeq ($(CONFIG_IMX9_USBDEV),y)
CHIP_CSRCS += imx9_usbdev.c
endif
ifeq ($(CONFIG_IMX9_LPI2C),y)
CHIP_CSRCS += imx9_lpi2c.c
endif
ifeq ($(CONFIG_IMX9_LPSPI), y)
CHIP_CSRCS += imx9_lpspi.c
endif
ifeq ($(CONFIG_IMX9_EDMA), y)
CHIP_CSRCS += imx9_edma.c
endif

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/****************************************************************************
* arch/arm/src/imx9/chip.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_CHIP_H
#define __ARCH_ARM_SRC_IMX9_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <nuttx/arch.h>
# include <arch/irq.h>
# include <arch/imx9/chip.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Cache line sizes (in bytes) for the i.MX 9 M7 Core */
#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */
#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */
/****************************************************************************
* Macro Definitions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX9_CHIP_H */

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arch/arm/src/imx9/hardware/imx95/imx95_clock.h Normal file
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_clock.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_CLOCK_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_CLOCK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
typedef enum
{
EXT_CLK = 0,
OSC_32K_CLK = 1,
OSC_24M_CLK = 2,
FRO_CLK = 3,
SYS_PLL1_CTL = 4,
SYS_PLL1_DFS0_CTL = 5,
SYS_PLL1_DFS0_CLK = 6,
SYS_PLL1_DFS0_DIV2_CLK = 7,
SYS_PLL1_DFS1_CTL = 8,
SYS_PLL1_DFS1_CLK = 9,
SYS_PLL1_DFS1_DIV2_CLK = 10,
SYS_PLL1_DFS2_CTL = 11,
SYS_PLL1_DFS2_CLK = 12,
SYS_PLL1_DFS2_DIV2_CLK = 13,
AUDIO_PLL1_CTL = 14,
AUDIO_PLL1_CLK = 15,
AUDIO_PLL2_CTL = 16,
AUDIO_PLL2_CLK = 17,
VIDEO_PLL1_CTL = 18,
VIDEO_PLL1_CLK = 19,
VIDEO_PLL2_CTL = 20,
VIDEO_PLL2_CLK = 21,
VIDEO_PLL3_CTL = 22,
VIDEO_PLL3_CLK = 23,
ARM_PLL_CTL = 24,
ARM_PLL_DFS0_CTL = 25,
ARM_PLL_DFS0_CLK = 26,
ARM_PLL_DFS1_CTL = 27,
ARM_PLL_DFS1_CLK = 28,
ARM_PLL_DFS2_CTL = 29,
ARM_PLL_DFS2_CLK = 30,
ARM_PLL_DFS3_CTL = 31,
ARM_PLL_DFS3_CLK = 32,
DRAM_PLL_CTL = 33,
DRAM_PLL_CLK = 34,
HSIO_PLL_CTL = 35,
HSIO_PLL_CLK = 36,
LDB_PLL_CTL = 37,
LDB_PLL_CLK = 38,
} clock_id_e;
#define CCM_CR_COUNT 122
typedef uint32_t clock_config_t;
#define CLOCK_DIV_SHIFT (16)
#define CLOCK_DIV_MASK (0xff << CLOCK_DIV_SHIFT)
#define CLOCK_DIV(n) (((n) << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK)
#define GET_CLOCK_DIV(n) (((n) & CLOCK_DIV_MASK) >> CLOCK_DIV_SHIFT)
#define CLOCK_ROOT_SHIFT (8)
#define CLOCK_ROOT_MASK (0x7f << CLOCK_ROOT_SHIFT)
#define CLOCK_ROOT(n) (((n) << CLOCK_ROOT_SHIFT) & CLOCK_ROOT_MASK)
#define GET_CLOCK_ROOT(n) (((n) & CLOCK_ROOT_MASK) >> CLOCK_ROOT_SHIFT)
#define CLOCK_ID_SHIFT (3)
#define CLOCK_ID_MASK (0x1f << CLOCK_ID_SHIFT)
#define CLOCK_ID(n) (((n) << CLOCK_ID_SHIFT) & CLOCK_ID_MASK)
#define GET_CLOCK_ID(n) (((n) & CLOCK_ID_MASK) >> CLOCK_ID_SHIFT)
#define ROOT_MUX_SHIFT (0)
#define ROOT_MUX_MASK (0x07 << ROOT_MUX_SHIFT)
#define ROOT_MUX(n) (((n) << ROOT_MUX_SHIFT) & ROOT_MUX_MASK)
/* ADC_CLK_ROOT */
#define ADC_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(0U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ADC_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(0U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define ADC_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(0U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define ADC_CLK_ROOT_FRO_CLK CLOCK_ROOT(0U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* TMU_CLK_ROOT */
#define TMU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(1U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TMU_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(1U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define TMU_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(1U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define TMU_CLK_ROOT_FRO_CLK CLOCK_ROOT(1U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* BUS_AON_CLK_ROOT */
#define BUS_AON_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(2U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define BUS_AON_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(2U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define BUS_AON_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(2U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define BUS_AON_CLK_ROOT_FRO_CLK CLOCK_ROOT(2U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAN1_CLK_ROOT */
#define CAN1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(3U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAN1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(3U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define CAN1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(3U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define CAN1_CLK_ROOT_FRO_CLK CLOCK_ROOT(3U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* I3C1_CLK_ROOT */
#define I3C1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(4U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define I3C1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(4U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define I3C1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(4U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define I3C1_CLK_ROOT_FRO_CLK CLOCK_ROOT(4U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* I3C1_SLOW_CLK_ROOT */
#define I3C1_SLOW_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(5U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define I3C1_SLOW_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(5U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define I3C1_SLOW_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(5U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define I3C1_SLOW_CLK_ROOT_FRO_CLK CLOCK_ROOT(5U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C1_CLK_ROOT */
#define LPI2C1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(6U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(6U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(6U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C1_CLK_ROOT_FRO_CLK CLOCK_ROOT(6U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C2_CLK_ROOT */
#define LPI2C2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(7U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(7U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(7U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C2_CLK_ROOT_FRO_CLK CLOCK_ROOT(7U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI1_CLK_ROOT */
#define LPSPI1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(8U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(8U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(8U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI1_CLK_ROOT_FRO_CLK CLOCK_ROOT(8U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI2_CLK_ROOT */
#define LPSPI2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(9U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(9U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(9U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI2_CLK_ROOT_FRO_CLK CLOCK_ROOT(9U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPTMR1_CLK_ROOT */
#define LPTMR1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(10U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPTMR1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(10U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPTMR1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(10U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPTMR1_CLK_ROOT_FRO_CLK CLOCK_ROOT(10U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART1_CLK_ROOT */
#define LPUART1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(11U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(11U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(11U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART1_CLK_ROOT_FRO_CLK CLOCK_ROOT(11U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART2_CLK_ROOT */
#define LPUART2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(12U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(12U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(12U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART2_CLK_ROOT_FRO_CLK CLOCK_ROOT(12U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* M33_CLK_ROOT */
#define M33_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(13U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define M33_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(13U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define M33_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(13U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define M33_CLK_ROOT_FRO_CLK CLOCK_ROOT(13U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* M33_SYSTICK_CLK_ROOT */
#define M33_SYSTICK_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(14U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define M33_SYSTICK_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(14U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define M33_SYSTICK_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(14U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define M33_SYSTICK_CLK_ROOT_FRO_CLK CLOCK_ROOT(14U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* MQS1_CLK_ROOT */
#define MQS1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(15U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define MQS1_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(15U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define MQS1_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(15U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define MQS1_CLK_ROOT_EXT_CLK CLOCK_ROOT(15U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* PDM_CLK_ROOT */
#define PDM_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(16U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define PDM_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(16U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define PDM_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(16U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define PDM_CLK_ROOT_EXT_CLK CLOCK_ROOT(16U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SAI1_CLK_ROOT */
#define SAI1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(17U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SAI1_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(17U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define SAI1_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(17U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define SAI1_CLK_ROOT_EXT_CLK CLOCK_ROOT(17U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SENTINEL_CLK_ROOT */
#define SENTINEL_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(18U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SENTINEL_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(18U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define SENTINEL_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(18U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define SENTINEL_CLK_ROOT_FRO_CLK CLOCK_ROOT(18U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* TPM2_CLK_ROOT */
#define TPM2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(19U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TPM2_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(19U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define TPM2_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(19U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define TPM2_CLK_ROOT_EXT_CLK CLOCK_ROOT(19U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* TSTMR1_CLK_ROOT */
#define TSTMR1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(20U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TSTMR1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(20U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define TSTMR1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(20U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define TSTMR1_CLK_ROOT_FRO_CLK CLOCK_ROOT(20U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAM_APB_CLK_ROOT */
#define CAM_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(21U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAM_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(21U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define CAM_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(21U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define CAM_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(21U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAM_AXI_CLK_ROOT */
#define CAM_AXI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(22U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAM_AXI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(22U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CAM_AXI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(22U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define CAM_AXI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(22U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* CAM_CM0_CLK_ROOT */
#define CAM_CM0_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(23U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAM_CM0_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(23U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CAM_CM0_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(23U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define CAM_CM0_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(23U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* CAM_ISI_CLK_ROOT */
#define CAM_ISI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(24U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAM_ISI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(24U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CAM_ISI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(24U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define CAM_ISI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(24U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* MIPI_PHY_CFG_CLK_ROOT */
#define MIPI_PHY_CFG_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(25U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define MIPI_PHY_CFG_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(25U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define MIPI_PHY_CFG_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(25U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* MIPI_PHY_PLL_BYPASS_CLK_ROOT */
#define MIPI_PHY_PLL_BYPASS_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(26U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define MIPI_PHY_PLL_BYPASS_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(26U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define MIPI_PHY_PLL_BYPASS_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(26U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* MIPI_PHY_PLL_REF_CLK_ROOT */
#define MIPI_PHY_PLL_REF_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(27U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define MIPI_PHY_PLL_REF_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(27U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define MIPI_PHY_PLL_REF_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(27U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* MIPI_TEST_BYTE_CLK_ROOT */
#define MIPI_TEST_BYTE_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(28U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define MIPI_TEST_BYTE_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(28U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define MIPI_TEST_BYTE_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(28U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* ARM_A55_CLK_ROOT */
#define ARM_A55_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(29U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ARM_A55_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(29U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ARM_A55_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(29U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define ARM_A55_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(29U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* ARM_A55_MTR_BUS_CLK_ROOT */
#define ARM_A55_MTR_BUS_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(30U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ARM_A55_MTR_BUS_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(30U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define ARM_A55_MTR_BUS_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(30U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define ARM_A55_MTR_BUS_CLK_ROOT_FRO_CLK CLOCK_ROOT(30U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* ARM_A55_PERIPH_CLK_ROOT */
#define ARM_A55_PERIPH_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(31U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ARM_A55_PERIPH_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(31U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ARM_A55_PERIPH_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(31U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define ARM_A55_PERIPH_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(31U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* DRAM_ALT_CLK_ROOT */
#define DRAM_ALT_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(32U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DRAM_ALT_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(32U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define DRAM_ALT_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(32U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define DRAM_ALT_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(32U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* DRAM_APB_CLK_ROOT */
#define DRAM_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(33U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DRAM_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(33U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define DRAM_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(33U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define DRAM_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(33U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* DISP_APB_CLK_ROOT */
#define DISP_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(34U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DISP_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(34U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define DISP_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(34U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define DISP_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(34U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* DISP_AXI_CLK_ROOT */
#define DISP_AXI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(35U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DISP_AXI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(35U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define DISP_AXI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(35U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define DISP_AXI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(35U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* DISP_DP_CLK_ROOT */
#define DISP_DP_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(36U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DISP_DP_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(36U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define DISP_DP_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(36U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define DISP_DP_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(36U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* DISP_OCRAM_CLK_ROOT */
#define DISP_OCRAM_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(37U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DISP_OCRAM_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(37U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define DISP_OCRAM_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(37U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define DISP_OCRAM_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(37U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* DISP_USB31_CLK_ROOT */
#define DISP_USB31_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(38U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DISP_USB31_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(38U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define DISP_USB31_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(38U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define DISP_USB31_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(38U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* DISP1_PIX_CLK_ROOT */
#define DISP1_PIX_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(39U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define DISP1_PIX_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(39U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define DISP1_PIX_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(39U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* GPU_APB_CLK_ROOT */
#define GPU_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(42U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define GPU_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(42U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define GPU_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(42U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define GPU_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(42U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* GPU_CLK_ROOT */
#define GPU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(43U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define GPU_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(43U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define GPU_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(43U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define GPU_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(43U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* HSIO_ACSCAN_480M_CLK_ROOT */
#define HSIO_ACSCAN_480M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(44U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_ACSCAN_480M_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(44U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define HSIO_ACSCAN_480M_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(44U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK)
#define HSIO_ACSCAN_480M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(44U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* HSIO_ACSCAN_80M_CLK_ROOT */
#define HSIO_ACSCAN_80M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(45U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_ACSCAN_80M_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(45U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define HSIO_ACSCAN_80M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(45U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define HSIO_ACSCAN_80M_CLK_ROOT_FRO_CLK CLOCK_ROOT(45U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* HSIO_CLK_ROOT */
#define HSIO_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(46U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(46U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define HSIO_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(46U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define HSIO_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(46U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* HSIO_PCIE_AUX_CLK_ROOT */
#define HSIO_PCIE_AUX_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(47U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_PCIE_AUX_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(47U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define HSIO_PCIE_AUX_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(47U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define HSIO_PCIE_AUX_CLK_ROOT_FRO_CLK CLOCK_ROOT(47U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* HSIO_PCIE_TEST_160M_CLK_ROOT */
#define HSIO_PCIE_TEST_160M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(48U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_PCIE_TEST_160M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(48U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define HSIO_PCIE_TEST_160M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(48U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define HSIO_PCIE_TEST_160M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(48U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* HSIO_PCIE_TEST_400M_CLK_ROOT */
#define HSIO_PCIE_TEST_400M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(49U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_PCIE_TEST_400M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(49U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define HSIO_PCIE_TEST_400M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(49U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define HSIO_PCIE_TEST_400M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(49U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* HSIO_PCIE_TEST_500M_CLK_ROOT */
#define HSIO_PCIE_TEST_500M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(50U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_PCIE_TEST_500M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(50U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define HSIO_PCIE_TEST_500M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(50U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define HSIO_PCIE_TEST_500M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(50U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* HSIO_USB_TEST_50M_CLK_ROOT */
#define HSIO_USB_TEST_50M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(51U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_USB_TEST_50M_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(51U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define HSIO_USB_TEST_50M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(51U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define HSIO_USB_TEST_50M_CLK_ROOT_FRO_CLK CLOCK_ROOT(51U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* HSIO_USB_TEST_60M_CLK_ROOT */
#define HSIO_USB_TEST_60M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(52U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define HSIO_USB_TEST_60M_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(52U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define HSIO_USB_TEST_60M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(52U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define HSIO_USB_TEST_60M_CLK_ROOT_FRO_CLK CLOCK_ROOT(52U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* BUS_M7_CLK_ROOT */
#define BUS_M7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(53U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define BUS_M7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(53U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define BUS_M7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(53U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define BUS_M7_CLK_ROOT_FRO_CLK CLOCK_ROOT(53U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* M7_CLK_ROOT */
#define M7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(54U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define M7_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(54U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define M7_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(54U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define M7_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(54U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* M7_SYSTICK_CLK_ROOT */
#define M7_SYSTICK_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(55U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define M7_SYSTICK_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(55U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define M7_SYSTICK_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(55U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define M7_SYSTICK_CLK_ROOT_FRO_CLK CLOCK_ROOT(55U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* BUS_NETCMIX_CLK_ROOT */
#define BUS_NETCMIX_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(56U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define BUS_NETCMIX_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(56U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define BUS_NETCMIX_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(56U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define BUS_NETCMIX_CLK_ROOT_FRO_CLK CLOCK_ROOT(56U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* ENET_CLK_ROOT */
#define ENET_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(57U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ENET_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(57U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ENET_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(57U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define ENET_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(57U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* ENET_PHY_TEST_200M_CLK_ROOT */
#define ENET_PHY_TEST_200M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(58U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ENET_PHY_TEST_200M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(58U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ENET_PHY_TEST_200M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(58U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define ENET_PHY_TEST_200M_CLK_ROOT_FRO_CLK CLOCK_ROOT(58U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* ENET_PHY_TEST_500M_CLK_ROOT */
#define ENET_PHY_TEST_500M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(59U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ENET_PHY_TEST_500M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(59U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ENET_PHY_TEST_500M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(59U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define ENET_PHY_TEST_500M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(59U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* ENET_PHY_TEST_667M_CLK_ROOT */
#define ENET_PHY_TEST_667M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(60U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ENET_PHY_TEST_667M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(60U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ENET_PHY_TEST_667M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(60U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define ENET_PHY_TEST_667M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(60U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* ENET_REF_CLK_ROOT */
#define ENET_REF_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(61U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ENET_REF_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(61U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define ENET_REF_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(61U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define ENET_REF_CLK_ROOT_FRO_CLK CLOCK_ROOT(61U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* ENET_TIMER1_CLK_ROOT */
#define ENET_TIMER1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(62U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define ENET_TIMER1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(62U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define ENET_TIMER1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(62U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define ENET_TIMER1_CLK_ROOT_FRO_CLK CLOCK_ROOT(62U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* MQS2_CLK_ROOT */
#define MQS2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(63U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define MQS2_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(63U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define MQS2_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(63U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define MQS2_CLK_ROOT_EXT_CLK CLOCK_ROOT(63U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SAI2_CLK_ROOT */
#define SAI2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(64U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SAI2_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(64U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define SAI2_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(64U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define SAI2_CLK_ROOT_EXT_CLK CLOCK_ROOT(64U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* NOC_APB_CLK_ROOT */
#define NOC_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(65U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define NOC_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(65U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define NOC_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(65U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define NOC_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(65U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* NOC_CLK_ROOT */
#define NOC_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(66U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define NOC_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(66U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define NOC_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(66U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define NOC_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(66U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* NPU_APB_CLK_ROOT */
#define NPU_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(67U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define NPU_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(67U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define NPU_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(67U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define NPU_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(67U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* NPU_CLK_ROOT */
#define NPU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(68U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define NPU_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(68U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define NPU_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(68U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define NPU_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(68U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* CCM_CKO1_CLK_ROOT */
#define CCM_CKO1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(69U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CCM_CKO1_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(69U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CCM_CKO1_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(69U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK)
#define CCM_CKO1_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(69U) | ROOT_MUX(3U) | CLOCK_ID(AUDIO_PLL1_CLK)
/* CCM_CKO2_CLK_ROOT */
#define CCM_CKO2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(70U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CCM_CKO2_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(70U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CCM_CKO2_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(70U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK)
#define CCM_CKO2_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(70U) | ROOT_MUX(3U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* CCM_CKO3_CLK_ROOT */
#define CCM_CKO3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(71U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CCM_CKO3_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(71U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CCM_CKO3_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(71U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK)
#define CCM_CKO3_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(71U) | ROOT_MUX(3U) | CLOCK_ID(AUDIO_PLL2_CLK)
/* CCM_CKO4_CLK_ROOT */
#define CCM_CKO4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(72U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CCM_CKO4_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(72U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define CCM_CKO4_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(72U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK)
#define CCM_CKO4_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(72U) | ROOT_MUX(3U) | CLOCK_ID(VIDEO_PLL1_CLK)
/* VPU_APB_CLK_ROOT */
#define VPU_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(73U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define VPU_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(73U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define VPU_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(73U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define VPU_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(73U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* VPU_CLK_ROOT */
#define VPU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(74U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define VPU_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(74U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define VPU_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(74U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define VPU_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(74U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* VPU_DSP_CLK_ROOT */
#define VPU_DSP_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(75U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define VPU_DSP_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(75U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define VPU_DSP_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(75U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define VPU_DSP_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(75U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* VPU_JPEG_CLK_ROOT */
#define VPU_JPEG_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(76U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define VPU_JPEG_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(76U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define VPU_JPEG_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(76U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define VPU_JPEG_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(76U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* AUDIO_XCVR_CLK_ROOT */
#define AUDIO_XCVR_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(77U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define AUDIO_XCVR_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(77U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define AUDIO_XCVR_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(77U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define AUDIO_XCVR_CLK_ROOT_FRO_CLK CLOCK_ROOT(77U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* BUS_WAKEUP_CLK_ROOT */
#define BUS_WAKEUP_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(78U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define BUS_WAKEUP_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(78U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define BUS_WAKEUP_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(78U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define BUS_WAKEUP_CLK_ROOT_FRO_CLK CLOCK_ROOT(78U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAN2_CLK_ROOT */
#define CAN2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(79U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAN2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(79U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define CAN2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(79U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define CAN2_CLK_ROOT_FRO_CLK CLOCK_ROOT(79U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAN3_CLK_ROOT */
#define CAN3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(80U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAN3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(80U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define CAN3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(80U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define CAN3_CLK_ROOT_FRO_CLK CLOCK_ROOT(80U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAN4_CLK_ROOT */
#define CAN4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(81U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAN4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(81U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define CAN4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(81U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define CAN4_CLK_ROOT_FRO_CLK CLOCK_ROOT(81U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* CAN5_CLK_ROOT */
#define CAN5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(82U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define CAN5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(82U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define CAN5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(82U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define CAN5_CLK_ROOT_FRO_CLK CLOCK_ROOT(82U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* FLEXIO1_CLK_ROOT */
#define FLEXIO1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(83U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define FLEXIO1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(83U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define FLEXIO1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(83U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define FLEXIO1_CLK_ROOT_FRO_CLK CLOCK_ROOT(83U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* FLEXIO2_CLK_ROOT */
#define FLEXIO2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(84U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define FLEXIO2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(84U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define FLEXIO2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(84U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define FLEXIO2_CLK_ROOT_FRO_CLK CLOCK_ROOT(84U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* FLEXSPI1_CLK_ROOT */
#define FLEXSPI1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(85U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define FLEXSPI1_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(85U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define FLEXSPI1_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(85U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define FLEXSPI1_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(85U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* I3C2_CLK_ROOT */
#define I3C2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(86U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define I3C2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(86U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define I3C2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(86U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define I3C2_CLK_ROOT_FRO_CLK CLOCK_ROOT(86U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* I3C2_SLOW_CLK_ROOT */
#define I3C2_SLOW_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(87U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define I3C2_SLOW_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(87U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define I3C2_SLOW_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(87U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define I3C2_SLOW_CLK_ROOT_FRO_CLK CLOCK_ROOT(87U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C3_CLK_ROOT */
#define LPI2C3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(88U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(88U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(88U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C3_CLK_ROOT_FRO_CLK CLOCK_ROOT(88U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C4_CLK_ROOT */
#define LPI2C4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(89U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(89U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(89U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C4_CLK_ROOT_FRO_CLK CLOCK_ROOT(89U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C5_CLK_ROOT */
#define LPI2C5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(90U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(90U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(90U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C5_CLK_ROOT_FRO_CLK CLOCK_ROOT(90U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C6_CLK_ROOT */
#define LPI2C6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(91U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C6_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(91U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C6_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(91U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C6_CLK_ROOT_FRO_CLK CLOCK_ROOT(91U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C7_CLK_ROOT */
#define LPI2C7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(92U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(92U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(92U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C7_CLK_ROOT_FRO_CLK CLOCK_ROOT(92U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPI2C8_CLK_ROOT */
#define LPI2C8_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(93U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPI2C8_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(93U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPI2C8_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(93U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPI2C8_CLK_ROOT_FRO_CLK CLOCK_ROOT(93U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI3_CLK_ROOT */
#define LPSPI3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(94U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(94U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(94U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI3_CLK_ROOT_FRO_CLK CLOCK_ROOT(94U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI4_CLK_ROOT */
#define LPSPI4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(95U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(95U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(95U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI4_CLK_ROOT_FRO_CLK CLOCK_ROOT(95U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI5_CLK_ROOT */
#define LPSPI5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(96U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(96U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(96U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI5_CLK_ROOT_FRO_CLK CLOCK_ROOT(96U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI6_CLK_ROOT */
#define LPSPI6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(97U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI6_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(97U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI6_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(97U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI6_CLK_ROOT_FRO_CLK CLOCK_ROOT(97U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI7_CLK_ROOT */
#define LPSPI7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(98U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(98U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(98U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI7_CLK_ROOT_FRO_CLK CLOCK_ROOT(98U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPSPI8_CLK_ROOT */
#define LPSPI8_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(99U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPSPI8_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(99U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPSPI8_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(99U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPSPI8_CLK_ROOT_FRO_CLK CLOCK_ROOT(99U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPTMR2_CLK_ROOT */
#define LPTMR2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(100U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPTMR2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(100U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPTMR2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(100U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPTMR2_CLK_ROOT_FRO_CLK CLOCK_ROOT(100U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART3_CLK_ROOT */
#define LPUART3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(101U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(101U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(101U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART3_CLK_ROOT_FRO_CLK CLOCK_ROOT(101U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART4_CLK_ROOT */
#define LPUART4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(102U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(102U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(102U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART4_CLK_ROOT_FRO_CLK CLOCK_ROOT(102U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART5_CLK_ROOT */
#define LPUART5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(103U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(103U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(103U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART5_CLK_ROOT_FRO_CLK CLOCK_ROOT(103U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART6_CLK_ROOT */
#define LPUART6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(104U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART6_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(104U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART6_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(104U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART6_CLK_ROOT_FRO_CLK CLOCK_ROOT(104U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART7_CLK_ROOT */
#define LPUART7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(105U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(105U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(105U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART7_CLK_ROOT_FRO_CLK CLOCK_ROOT(105U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* LPUART8_CLK_ROOT */
#define LPUART8_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(106U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define LPUART8_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(106U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define LPUART8_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(106U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define LPUART8_CLK_ROOT_FRO_CLK CLOCK_ROOT(106U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* SAI3_CLK_ROOT */
#define SAI3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(107U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SAI3_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(107U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define SAI3_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(107U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define SAI3_CLK_ROOT_EXT_CLK CLOCK_ROOT(107U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SAI4_CLK_ROOT */
#define SAI4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(108U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SAI4_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(108U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define SAI4_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(108U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define SAI4_CLK_ROOT_EXT_CLK CLOCK_ROOT(108U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SAI5_CLK_ROOT */
#define SAI5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(109U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SAI5_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(109U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define SAI5_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(109U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define SAI5_CLK_ROOT_EXT_CLK CLOCK_ROOT(109U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SPDIF_CLK_ROOT */
#define SPDIF_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(110U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SPDIF_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(110U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define SPDIF_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(110U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK)
#define SPDIF_CLK_ROOT_EXT_CLK CLOCK_ROOT(110U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* SWO_TRACE_CLK_ROOT */
#define SWO_TRACE_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(111U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define SWO_TRACE_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(111U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define SWO_TRACE_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(111U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define SWO_TRACE_CLK_ROOT_FRO_CLK CLOCK_ROOT(111U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* TPM4_CLK_ROOT */
#define TPM4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(112U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TPM4_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(112U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define TPM4_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(112U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define TPM4_CLK_ROOT_EXT_CLK CLOCK_ROOT(112U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* TPM5_CLK_ROOT */
#define TPM5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(113U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TPM5_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(113U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define TPM5_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(113U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define TPM5_CLK_ROOT_EXT_CLK CLOCK_ROOT(113U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* TPM6_CLK_ROOT */
#define TPM6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(114U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TPM6_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(114U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define TPM6_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(114U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK)
#define TPM6_CLK_ROOT_EXT_CLK CLOCK_ROOT(114U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK)
/* TSTMR2_CLK_ROOT */
#define TSTMR2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(115U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define TSTMR2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(115U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define TSTMR2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(115U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define TSTMR2_CLK_ROOT_FRO_CLK CLOCK_ROOT(115U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* USB_PHY_BURUNIN_CLK_ROOT */
#define USB_PHY_BURUNIN_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(116U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define USB_PHY_BURUNIN_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(116U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK)
#define USB_PHY_BURUNIN_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(116U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK)
#define USB_PHY_BURUNIN_CLK_ROOT_FRO_CLK CLOCK_ROOT(116U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK)
/* USDHC1_CLK_ROOT */
#define USDHC1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(117U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define USDHC1_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(117U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define USDHC1_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(117U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define USDHC1_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(117U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* USDHC2_CLK_ROOT */
#define USDHC2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(118U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define USDHC2_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(118U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define USDHC2_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(118U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define USDHC2_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(118U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* USDHC3_CLK_ROOT */
#define USDHC3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(119U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define USDHC3_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(119U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define USDHC3_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(119U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define USDHC3_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(119U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* V2X_PK_CLK_ROOT */
#define V2X_PK_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(120U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define V2X_PK_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(120U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define V2X_PK_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(120U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define V2X_PK_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(120U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* WAKEUP_AXI_CLK_ROOT */
#define WAKEUP_AXI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(121U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define WAKEUP_AXI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(121U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define WAKEUP_AXI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(121U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define WAKEUP_AXI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(121U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
/* XSPI_SLV_ROOT_CLK_ROOT */
#define XSPI_SLV_ROOT_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(122U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK)
#define XSPI_SLV_ROOT_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(122U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK)
#define XSPI_SLV_ROOT_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(122U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK)
#define XSPI_SLV_ROOT_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(122U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "imx95_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Identify channel MUX from 9th bit */
#define EDMA3_MUX_ID 0x0000
#define EDMA4_MUX_ID 0x0100
#define EDMA_MUX_ID_MASK 0xff00
#define EDMA_MUX_MASK 0x00ff
/* eDMA3 MUXs */
#define DMA_REQUEST_DISABLED (0 | EDMA3_MUX_ID) /**< DSisabled*/
#define DMA_REQUEST_MUXCAN1 (1 | EDMA3_MUX_ID) /**< CAN1 */
#define DMA_REQUEST_MUXLPTMR1REQUEST (2 | EDMA3_MUX_ID) /**< LPTMR1 Request */
#define DMA_REQUEST_MUXELEREQUEST (3 | EDMA3_MUX_ID) /**< ELE Request */
#define DMA_REQUEST_MUXTPM1OVERFLOWREQUEST (4 | EDMA3_MUX_ID) /**< TPM1 Overflow Request */
#define DMA_REQUEST_MUXTPM2OVERFLOWREQUEST (5 | EDMA3_MUX_ID) /**< TPM2 Overflow Request */
#define DMA_REQUEST_MUXPDMREQUEST (6 | EDMA3_MUX_ID) /**< PDM */
#define DMA_REQUEST_MUXADC1REQUEST (7 | EDMA3_MUX_ID) /**< ADC1 */
#define DMA_REQUEST_MUXGPIO1REQUEST0 (8 | EDMA3_MUX_ID) /**< GPIO1 channel 0 */
#define DMA_REQUEST_MUXGPIO1REQUEST1 (9 | EDMA3_MUX_ID) /**< GPIO1 channel 1 */
#define DMA_REQUEST_MUXI3C1TOBUSREQUEST (10 | EDMA3_MUX_ID) /**< I3C1 To-bus Request */
#define DMA_REQUEST_MUXI3C1FROMBUSREQUEST (11 | EDMA3_MUX_ID) /**< I3C1 From-bus Request */
#define DMA_REQUEST_MUXLPI2C1TX (12 | EDMA3_MUX_ID) /**< LPI2C1 */
#define DMA_REQUEST_MUXLPI2C1RX (13 | EDMA3_MUX_ID) /**< LPI2C1 */
#define DMA_REQUEST_MUXLPI2C2TX (14 | EDMA3_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPI2C2RX (15 | EDMA3_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPSPI1TX (16 | EDMA3_MUX_ID) /**< LPSPI1 Transmit */
#define DMA_REQUEST_MUXLPSPI1RX (17 | EDMA3_MUX_ID) /**< LPSPI1 Receive */
#define DMA_REQUEST_MUXLPSPI2TX (18 | EDMA3_MUX_ID) /**< LPSPI2 Transmit */
#define DMA_REQUEST_MUXLPSPI2RX (19 | EDMA3_MUX_ID) /**< LPSPI2 Receive */
#define DMA_REQUEST_MUXLPUART1TX (20 | EDMA3_MUX_ID) /**< LPUART1 Transmit */
#define DMA_REQUEST_MUXLPUART1RX (21 | EDMA3_MUX_ID) /**< LPUART1 Receive */
#define DMA_REQUEST_MUXLPUART2TX (22 | EDMA3_MUX_ID) /**< LPUART2 Transmit */
#define DMA_REQUEST_MUXLPUART2RX (23 | EDMA3_MUX_ID) /**< LPUART2 Receive */
#define DMA_REQUEST_MUXSAI1TX (24 | EDMA3_MUX_ID) /**< SAI1 Transmit */
#define DMA_REQUEST_MUXSAI1RX (25 | EDMA3_MUX_ID) /**< SAI1 Receive */
#define DMA_REQUEST_MUXTPM1REQUEST0REQUEST2 (26 | EDMA3_MUX_ID) /**< TPM1 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM1REQUEST1REQUEST3 (27 | EDMA3_MUX_ID) /**< TPM1 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM2REQUEST0REQUEST2 (28 | EDMA3_MUX_ID) /**< TPM2 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM2REQUEST1REQUEST3 (29 | EDMA3_MUX_ID) /**< TPM2 request 1 and request 3 */
#define DMA3_REQUEST_MUX_COUNT (30)
/* eDMA4 MUXs */
#define DMA_REQUEST_MUXCAN2 (1U | EDMA4_MUX_ID) /**< CAN2 */
#define DMA_REQUEST_MUXGPIO2REQUEST0 (2U | EDMA4_MUX_ID) /**< GPIO2 channel 0 */
#define DMA_REQUEST_MUXGPIO2REQUEST1 (3U | EDMA4_MUX_ID) /**< GPIO2 channel 1 */
#define DMA_REQUEST_MUXGPIO3REQUEST0 (4U | EDMA4_MUX_ID) /**< GPIO3 channel 0 */
#define DMA_REQUEST_MUXGPIO3REQUEST1 (5U | EDMA4_MUX_ID) /**< GPIO3 channel 1 */
#define DMA_REQUEST_MUXI3C2TOBUSREQUEST (6U | EDMA4_MUX_ID) /**< I3C2 To-bus Request */
#define DMA_REQUEST_MUXI3C2FROMBUSREQUEST (7U | EDMA4_MUX_ID) /**< I3C2 From-bus Request */
#define DMA_REQUEST_MUXLPI2C3TX (8U | EDMA4_MUX_ID) /**< LPI2C3 */
#define DMA_REQUEST_MUXLPI2C3RX (9U | EDMA4_MUX_ID) /**< LPI2C3 */
#define DMA_REQUEST_MUXLPI2C4TX (10U | EDMA4_MUX_ID) /**< LPI2C4 */
#define DMA_REQUEST_MUXLPI2C4RX (11U | EDMA4_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPSPI3TX (12U | EDMA4_MUX_ID) /**< LPSPI3 Transmit */
#define DMA_REQUEST_MUXLPSPI3RX (13U | EDMA4_MUX_ID) /**< LPSPI3 Receive */
#define DMA_REQUEST_MUXLPSPI4TX (14U | EDMA4_MUX_ID) /**< LPSPI4 Transmit */
#define DMA_REQUEST_MUXLPSPI4RX (15U | EDMA4_MUX_ID) /**< LPSPI4 Receive */
#define DMA_REQUEST_MUXLPTMR2REQUEST (16U | EDMA4_MUX_ID) /**< LPTMR2 Request */
#define DMA_REQUEST_MUXLPUART3TX (17U | EDMA4_MUX_ID) /**< LPUART3 Transmit */
#define DMA_REQUEST_MUXLPUART3RX (18U | EDMA4_MUX_ID) /**< LPUART3 Receive */
#define DMA_REQUEST_MUXLPUART4TX (19U | EDMA4_MUX_ID) /**< LPUART4 Transmit */
#define DMA_REQUEST_MUXLPUART4RX (20U | EDMA4_MUX_ID) /**< LPUART4 Receive */
#define DMA_REQUEST_MUXLPUART5TX (21U | EDMA4_MUX_ID) /**< LPUART5 Transmit */
#define DMA_REQUEST_MUXLPUART5RX (22U | EDMA4_MUX_ID) /**< LPUART5 Receive */
#define DMA_REQUEST_MUXLPUART6TX (23U | EDMA4_MUX_ID) /**< LPUART6 Transmit */
#define DMA_REQUEST_MUXLPUART6RX (24U | EDMA4_MUX_ID) /**< LPUART6 Receive */
#define DMA_REQUEST_MUXTPM3REQUEST0REQUEST2 (25U | EDMA4_MUX_ID) /**< TPM3 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM3REQUEST1REQUEST3 (26U | EDMA4_MUX_ID) /**< TPM3 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM3OVERFLOWREQUEST (27U | EDMA4_MUX_ID) /**< TPM3 Overflow request */
#define DMA_REQUEST_MUXTPM4REQUEST0REQUEST2 (28U | EDMA4_MUX_ID) /**< TPM4 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM4REQUEST1REQUEST3 (29U | EDMA4_MUX_ID) /**< TPM4 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM4OVERFLOWREQUEST (30U | EDMA4_MUX_ID) /**< TPM4 Overflow request */
#define DMA_REQUEST_MUXTPM5REQUEST0REQUEST2 (31U | EDMA4_MUX_ID) /**< TPM5 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM5REQUEST1REQUEST3 (32U | EDMA4_MUX_ID) /**< TPM5 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM5OVERFLOWREQUEST (33U | EDMA4_MUX_ID) /**< TPM5 Overflow request */
#define DMA_REQUEST_MUXTPM6REQUEST0REQUEST2 (34U | EDMA4_MUX_ID) /**< TPM6 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM6REQUEST1REQUEST3 (35U | EDMA4_MUX_ID) /**< TPM6 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM6OVERFLOWREQUEST (36U | EDMA4_MUX_ID) /**< TPM6 Overflow request */
#define DMA_REQUEST_MUXFLEXIO1REQUEST0 (37U | EDMA4_MUX_ID) /**< FlexIO1 Request0 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST1 (38U | EDMA4_MUX_ID) /**< FlexIO1 Request1 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST2 (39U | EDMA4_MUX_ID) /**< FlexIO1 Request2 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST3 (40U | EDMA4_MUX_ID) /**< FlexIO1 Request3 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST4 (41U | EDMA4_MUX_ID) /**< FlexIO1 Request4 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST5 (42U | EDMA4_MUX_ID) /**< FlexIO1 Request5 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST6 (43U | EDMA4_MUX_ID) /**< FlexIO1 Request6 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST7 (44U | EDMA4_MUX_ID) /**< FlexIO1 Request7 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST0 (45U | EDMA4_MUX_ID) /**< FlexIO2 Request0 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST1 (46U | EDMA4_MUX_ID) /**< FlexIO2 Request1 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST2 (47U | EDMA4_MUX_ID) /**< FlexIO2 Request2 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST3 (48U | EDMA4_MUX_ID) /**< FlexIO2 Request3 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST4 (49U | EDMA4_MUX_ID) /**< FlexIO2 Request4 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST5 (50U | EDMA4_MUX_ID) /**< FlexIO2 Request5 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST6 (51U | EDMA4_MUX_ID) /**< FlexIO2 Request6 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST7 (52U | EDMA4_MUX_ID) /**< FlexIO2 Request7 */
#define DMA_REQUEST_MUXFLEXSPI1TX (53U | EDMA4_MUX_ID) /**< FlexSPI1 Transmit */
#define DMA_REQUEST_MUXFLEXSPI1RX (54U | EDMA4_MUX_ID) /**< FlexSPI1 Receive */
#define DMA_REQUEST_MUXGPIO5REQUEST0 (53U | EDMA4_MUX_ID) /**< GPIO5 Request0 */
#define DMA_REQUEST_MUXGPIO5REQUEST1 (54U | EDMA4_MUX_ID) /**< GPIO5 Request1 */
#define DMA_REQUEST_MUXCAN3 (57U | EDMA4_MUX_ID) /**< CAN3 */
#define DMA_REQUEST_MUXSAI2TX (58U | EDMA4_MUX_ID) /**< SAI2 Transmit */
#define DMA_REQUEST_MUXSAI2RX (59U | EDMA4_MUX_ID) /**< SAI2 Receive */
#define DMA_REQUEST_MUXSAI3TX (60U | EDMA4_MUX_ID) /**< SAI3 Transmit */
#define DMA_REQUEST_MUXSAI3RX (61U | EDMA4_MUX_ID) /**< SAI3 Receive */
#define DMA_REQUEST_MUXGPIO4REQUEST0 (62U | EDMA4_MUX_ID) /**< GPIO4 Request0 */
#define DMA_REQUEST_MUXGPIO4REQUEST1 (63U | EDMA4_MUX_ID) /**< GPIO4 Request1 */
#define DMA_REQUEST_MUXEARCREQUEST0 (65U | EDMA4_MUX_ID) /**< eARC enhanced Audio Return Channel */
#define DMA_REQUEST_MUXEARCREQUEST1 (66U | EDMA4_MUX_ID) /**< eARC enhanced Audio Return Channel */
#define DMA_REQUEST_MUXSAI4TX (67U | EDMA4_MUX_ID) /**< SAI4 Transmit */
#define DMA_REQUEST_MUXSAI4RX (68U | EDMA4_MUX_ID) /**< SAI4 Receive */
#define DMA_REQUEST_MUXSAI5TX (69U | EDMA4_MUX_ID) /**< SAI5 Transmit */
#define DMA_REQUEST_MUXSAI5RX (70U | EDMA4_MUX_ID) /**< SAI5 Receive */
#define DMA_REQUEST_MUXLPI2C5TX (71U | EDMA4_MUX_ID) /**< LPI2C5 */
#define DMA_REQUEST_MUXLPI2C5RX (72U | EDMA4_MUX_ID) /**< LPI2C5 */
#define DMA_REQUEST_MUXLPI2C6TX (73U | EDMA4_MUX_ID) /**< LPI2C6 */
#define DMA_REQUEST_MUXLPI2C6RX (74U | EDMA4_MUX_ID) /**< LPI2C6 */
#define DMA_REQUEST_MUXLPI2C7TX (75U | EDMA4_MUX_ID) /**< LPI2C7 */
#define DMA_REQUEST_MUXLPI2C7RX (76U | EDMA4_MUX_ID) /**< LPI2C7 */
#define DMA_REQUEST_MUXLPI2C8TX (77U | EDMA4_MUX_ID) /**< LPI2C8 */
#define DMA_REQUEST_MUXLPI2C8RX (78U | EDMA4_MUX_ID) /**< LPI2C8 */
#define DMA_REQUEST_MUXLPSPI5TX (79U | EDMA4_MUX_ID) /**< LPSPI5 Transmit */
#define DMA_REQUEST_MUXLPSPI5RX (80U | EDMA4_MUX_ID) /**< LPSPI5 Receive */
#define DMA_REQUEST_MUXLPSPI6TX (81U | EDMA4_MUX_ID) /**< LPSPI6 Transmit */
#define DMA_REQUEST_MUXLPSPI6RX (82U | EDMA4_MUX_ID) /**< LPSPI6 Receive */
#define DMA_REQUEST_MUXLPSPI7TX (83U | EDMA4_MUX_ID) /**< LPSPI7 Transmit */
#define DMA_REQUEST_MUXLPSPI7RX (84U | EDMA4_MUX_ID) /**< LPSPI7 Receive */
#define DMA_REQUEST_MUXLPSPI8TX (85U | EDMA4_MUX_ID) /**< LPSPI8 Transmit */
#define DMA_REQUEST_MUXLPSPI8RX (86U | EDMA4_MUX_ID) /**< LPSPI8 Receive */
#define DMA_REQUEST_MUXLPUART7TX (87U | EDMA4_MUX_ID) /**< LPUART7 Transmit */
#define DMA_REQUEST_MUXLPUART7RX (88U | EDMA4_MUX_ID) /**< LPUART7 Receive */
#define DMA_REQUEST_MUXLPUART8TX (89U | EDMA4_MUX_ID) /**< LPUART8 Transmit */
#define DMA_REQUEST_MUXLPUART8RX (90U | EDMA4_MUX_ID) /**< LPUART8 Receive */
#define DMA_REQUEST_MUXCAN4 (91U | EDMA4_MUX_ID) /**< CAN4 */
#define DMA_REQUEST_MUXCAN5 (92U | EDMA4_MUX_ID) /**< CAN5 */
#define DMA4_REQUEST_MUX_COUNT (95)
/* Combined MUX count (eDMA3 and eDMA4) */
#define DMA_REQUEST_MUX_COUNT (DMA3_REQUEST_MUX_COUNT + DMA4_REQUEST_MUX_COUNT)
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_dmamux_get_dmabase
*
* Description:
* Get DMA engine base address from MUX identifier.
*
* Input Parameters:
* dmamux - The DMA MUX identifier.
*
* Returned Value:
* Base address of the associated DMA engine.
*
****************************************************************************/
static inline uintptr_t imx9_dmamux_get_dmabase(uint16_t dmamux)
{
if ((dmamux & EDMA_MUX_ID_MASK) == EDMA3_MUX_ID)
{
return IMX9_DMA3_BASE;
}
else
{
return IMX9_EDMA5_2_BASE;
}
}
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_edma.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include "imx95_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* eDMA3 / eDMA4 Register Offsets */
#define IMX9_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
#define IMX9_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
#define IMX9_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
/* eDMA3 only */
#define IMX9_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
#define IMX9_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
/* eDMA4 only */
#define IMX9_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */
#define IMX9_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */
#define IMX9_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */
#define IMX9_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */
/* eDNA5 only */
#define IMX9_EDMA_MP_CH_MUX_OFFSET(n) (0x000200 + ((n) << 2)) /* Channel Multiplexor Configuration (CH_MUX) */
/* eDMA3 / eDMA4 Register Addresses */
#define IMX9_EDMA_CSR(n) ((n) + IMX9_EDMA_CSR_OFFSET)
#define IMX9_EDMA_ES(n) ((n) + IMX9_EDMA_ES_OFFSET)
#define IMX9_EDMA_CH_GRPRI(n,c) ((n) + IMX9_EDMA_CH_GRPRI_OFFSET(n))
/* eDMA3 only */
#define IMX9_EDMA_INT (IMX9_DMA3_BASE + IMX9_EDMA_INT_OFFSET)
#define IMX9_EDMA_HRS (IMX9_DMA3_BASE + IMX9_EDMA_HRS_OFFSET)
/* eDMA5 only */
#define IMX9_EDMA_INT_LOW (IMX9_EDMA5_2_BASE + IMX9_EDMA_INT_LOW_OFFSET)
#define IMX9_EDMA_INT_HIGH (IMX9_EDMA5_2_BASE + IMX9_EDMA_INT_HIGH_OFFSET)
#define IMX9_EDMA_HRS_LOW (IMX9_EDMA5_2_BASE + IMX9_EDMA_HRS_LOW_OFFSET)
#define IMX9_EDMA_HRS_HIGH (IMX9_EDMA5_2_BASE + IMX9_EDMA_HRS_HIGH_OFFSET)
/* eDMA Transfer Control Descriptor (TCD) Register Offsets */
#define IMX9_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
#define IMX9_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
#define IMX9_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
#define IMX9_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
#define IMX9_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
#define IMX9_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */
#define IMX9_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */
#define IMX9_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
#define IMX9_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
#define IMX9_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
#define IMX9_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
#define IMX9_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
#define IMX9_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
#define IMX9_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
#define IMX9_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
#define IMX9_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
#define IMX9_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
#define IMX9_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */
#define IMX9_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */
#define IMX9_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */
#define IMX9_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */
#define IMX9_EDMA_TCD_BASE(n) ((n) + IMX9_EDMA_TCD_BASE_OFFSET)
#define IMX9_EDMA_TCD_INST_OFFSET(n) ((n) == IMX9_DMA3_BASE ? IMX9_EDMA3_TCD_INST_OFFSET : IMX9_EDMA4_TCD_INST_OFFSET)
#define IMX9_EDMA_TCD(n,t) (IMX9_EDMA_TCD_BASE(n) + (t) * IMX9_EDMA_TCD_INST_OFFSET(n))
/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
#define IMX9_EDMA_CH_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_CSR_OFFSET)
#define IMX9_EDMA_CH_ES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_ES_OFFSET)
#define IMX9_EDMA_CH_INT(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_INT_OFFSET)
#define IMX9_EDMA_CH_SBR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_SBR_OFFSET)
#define IMX9_EDMA_CH_PRI(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_PRI_OFFSET)
#define IMX9_EDMA_CH_MUX(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_MUX_OFFSET)
#define IMX9_EDMA_TCD_SADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SADDR_OFFSET)
#define IMX9_EDMA_TCD_SOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SOFF_OFFSET)
#define IMX9_EDMA_TCD_ATTR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_ATTR_OFFSET)
#define IMX9_EDMA_TCD_NBYTES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_NBYTES_OFFSET)
#define IMX9_EDMA_TCD_SLAST_SDA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SLAST_SDA_OFFSET)
#define IMX9_EDMA_TCD_DADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DADDR_OFFSET)
#define IMX9_EDMA_TCD_DOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DOFF_OFFSET)
#define IMX9_EDMA_TCD_CITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CITER_OFFSET)
#define IMX9_EDMA_TCD_DLAST_SGA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DLAST_SGA_OFFSET)
#define IMX9_EDMA_TCD_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CSR_OFFSET)
#define IMX9_EDMA_TCD_BITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_BITER_OFFSET)
/* eDMA Register Bitfield Definitions ***************************************/
/* Management Page Control Register (CSR) */
/* Bit 0: Reserved */
#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
/* Bit 3: Reserved */
#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
/* Bits 10-23: Reserved */
#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
/* Bits 29-30: Reserved */
#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
/* Management Page Error Status Register (ES) */
#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
/* Bits 9-23: Reserved */
#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
/* Bits 29-30: Reserved */
#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
/* Management Page Interrupt Request Status Register (INT) */
#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
/* Management Page Hardware Request Status Register (HRS) */
#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
/* Channel n Arbitration Group Register (CHn_GRPRI) */
#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
/* Bits 5-31: Reserved */
/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
/* Channel n Control and Status Register (CHn_CSR) */
#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
/* Bit 4-29: Reserved */
#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
/* Channel n Error Status Register (CHn_ES) */
#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
/* Bit 8-30: Reserved */
#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
/* Channel n Interrupt Status Register (CHn_INT) */
#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
/* Bits 1-31: Reserved */
/* Channel n System Bus Register (CHn_SBR) */
#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
/* Bits 4-13: Reserved */
#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */
#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
/* Bits 20-31: Reserved */
/* Channel n Priority Register (CHn_PRI) */
#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
/* Bits 3-29: Reserved */
#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
/* Channel Multiplexor Configuration (CHn_MUX) */
#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-6: Service Request Source */
#define EDMA_CH_SRC_MASK (0x7f << EDMA_CH_SRC_SHIFT)
/* TCDn Source Address Register (TCDn_SADDR) */
#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
/* TCDn Transfer Attributes (TCDn_ATTR) */
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
/* TCDn Transfer Size (TCDn_NBYTES) */
#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
/* TCDn Last Source Address Adjustment / Store DADDR Address Register
* (TCDn_SLAST_SDA)
*/
#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
/* TCDn Destination Address Register (TCDn_DADDR) */
#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
/* TCDn Current Major Loop Count Register (TCDn_CITER) */
#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
* (TCDn_DLAST_SGA)
*/
#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
/* TCDn Control and Status Register (TCDn_CSR) */
#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
/* Bit 13: Reserved */
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */
# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */
# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */
/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */
#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */
#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* Amount of channels */
#define DMA3_CHANNEL_COUNT (31)
#define DMA4_CHANNEL_COUNT (64)
#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT)
/* Amount of interrupt sources */
#ifdef CONFIG_ARCH_CHIP_IMX95_M7
#define DMA3_IRQ_COUNT (31) /* Error interrupt not counted */
#else
#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */
#endif
#define DMA4_IRQ_COUNT (32) /* Error interrupt not counted */
/****************************************************************************
* Public Types
****************************************************************************/
/* In-memory representation of the 32-byte Transfer Control Descriptor
* (TCD)
*/
struct imx9_edmatcd_s
{
uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* Offset: 0x001c TCD Control and Status */
uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_edma_tcdhasmux
*
* Description:
* Check if DMA TCD has TCD.MUX register.
*
* Input Parameters:
* dmabase - The eDMA base.
*
* Returned Value:
* true if TCD.MUX exists; false if not.
*
****************************************************************************/
static inline bool imx9_edma_tcdhasmux(uintptr_t dmabase)
{
/* Only eDMA5 has TCD.MUX register */
return dmabase == IMX9_EDMA5_2_BASE ? true : false;
}
/****************************************************************************
* Name: imx9_edma_choffset
*
* Description:
* Channel offset in global channel list for dma base.
*
* Input Parameters:
* base - The eDMA base.
*
* Returned Value:
* Channel offset.
*
****************************************************************************/
static inline uint32_t imx9_edma_choffset(uintptr_t base)
{
return base == IMX9_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT;
}
/****************************************************************************
* Name: imx9_edma_chmax
*
* Description:
* Max channel in global channel list for dma base.
*
* Input Parameters:
* base - The eDMA base.
*
* Returned Value:
* Channel max.
*
****************************************************************************/
static inline uint32_t imx9_edma_chmax(uintptr_t base)
{
return base == IMX9_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMX9_EDMA_NCHANNELS;
}
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "imx95_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */
#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */
#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */
#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */
#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */
#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */
#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */
#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */
#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */
#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */
#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */
#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */
#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */
#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */
#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */
#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */
#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */
#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */
#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */
#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_iomuxc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IOMUXC_MUX_CTL_DAP_TDI_OFFSET (0x0000)
#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET (0x0004)
#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET (0x0008)
#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET (0x000c)
#define IOMUXC_MUX_CTL_GPIO_IO00_OFFSET (0x0010)
#define IOMUXC_MUX_CTL_GPIO_IO01_OFFSET (0x0014)
#define IOMUXC_MUX_CTL_GPIO_IO02_OFFSET (0x0018)
#define IOMUXC_MUX_CTL_GPIO_IO03_OFFSET (0x001c)
#define IOMUXC_MUX_CTL_GPIO_IO04_OFFSET (0x0020)
#define IOMUXC_MUX_CTL_GPIO_IO05_OFFSET (0x0024)
#define IOMUXC_MUX_CTL_GPIO_IO06_OFFSET (0x0028)
#define IOMUXC_MUX_CTL_GPIO_IO07_OFFSET (0x002c)
#define IOMUXC_MUX_CTL_GPIO_IO08_OFFSET (0x0030)
#define IOMUXC_MUX_CTL_GPIO_IO09_OFFSET (0x0034)
#define IOMUXC_MUX_CTL_GPIO_IO10_OFFSET (0x0038)
#define IOMUXC_MUX_CTL_GPIO_IO11_OFFSET (0x003c)
#define IOMUXC_MUX_CTL_GPIO_IO12_OFFSET (0x0040)
#define IOMUXC_MUX_CTL_GPIO_IO13_OFFSET (0x0044)
#define IOMUXC_MUX_CTL_GPIO_IO14_OFFSET (0x0048)
#define IOMUXC_MUX_CTL_GPIO_IO15_OFFSET (0x004c)
#define IOMUXC_MUX_CTL_GPIO_IO16_OFFSET (0x0050)
#define IOMUXC_MUX_CTL_GPIO_IO17_OFFSET (0x0054)
#define IOMUXC_MUX_CTL_GPIO_IO18_OFFSET (0x0058)
#define IOMUXC_MUX_CTL_GPIO_IO19_OFFSET (0x005c)
#define IOMUXC_MUX_CTL_GPIO_IO20_OFFSET (0x0060)
#define IOMUXC_MUX_CTL_GPIO_IO21_OFFSET (0x0064)
#define IOMUXC_MUX_CTL_GPIO_IO22_OFFSET (0x0068)
#define IOMUXC_MUX_CTL_GPIO_IO23_OFFSET (0x006c)
#define IOMUXC_MUX_CTL_GPIO_IO24_OFFSET (0x0070)
#define IOMUXC_MUX_CTL_GPIO_IO25_OFFSET (0x0074)
#define IOMUXC_MUX_CTL_GPIO_IO26_OFFSET (0x0078)
#define IOMUXC_MUX_CTL_GPIO_IO27_OFFSET (0x007c)
#define IOMUXC_MUX_CTL_GPIO_IO28_OFFSET (0x0080)
#define IOMUXC_MUX_CTL_GPIO_IO29_OFFSET (0x0084)
#define IOMUXC_MUX_CTL_GPIO_IO30_OFFSET (0x0088)
#define IOMUXC_MUX_CTL_GPIO_IO31_OFFSET (0x008c)
#define IOMUXC_MUX_CTL_GPIO_IO32_OFFSET (0x0090)
#define IOMUXC_MUX_CTL_GPIO_IO33_OFFSET (0x0094)
#define IOMUXC_MUX_CTL_GPIO_IO34_OFFSET (0x0098)
#define IOMUXC_MUX_CTL_GPIO_IO35_OFFSET (0x009c)
#define IOMUXC_MUX_CTL_GPIO_IO36_OFFSET (0x00a0)
#define IOMUXC_MUX_CTL_GPIO_IO37_OFFSET (0x00a4)
#define IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET (0x00a8)
#define IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET (0x00ac)
#define IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET (0x00b0)
#define IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET (0x00b4)
#define IOMUXC_MUX_CTL_ENET1_MDC_OFFSET (0x00b8)
#define IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET (0x00bc)
#define IOMUXC_MUX_CTL_ENET1_TD3_OFFSET (0x00c0)
#define IOMUXC_MUX_CTL_ENET1_TD2_OFFSET (0x00c4)
#define IOMUXC_MUX_CTL_ENET1_TD1_OFFSET (0x00c8)
#define IOMUXC_MUX_CTL_ENET1_TD0_OFFSET (0x00cc)
#define IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET (0x00d0)
#define IOMUXC_MUX_CTL_ENET1_TXC_OFFSET (0x00d4)
#define IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET (0x00d8)
#define IOMUXC_MUX_CTL_ENET1_RXC_OFFSET (0x00dc)
#define IOMUXC_MUX_CTL_ENET1_RD0_OFFSET (0x00e0)
#define IOMUXC_MUX_CTL_ENET1_RD1_OFFSET (0x00e4)
#define IOMUXC_MUX_CTL_ENET1_RD2_OFFSET (0x00e8)
#define IOMUXC_MUX_CTL_ENET1_RD3_OFFSET (0x00ec)
#define IOMUXC_MUX_CTL_ENET2_MDC_OFFSET (0x00f0)
#define IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET (0x00f4)
#define IOMUXC_MUX_CTL_ENET2_TD3_OFFSET (0x00f8)
#define IOMUXC_MUX_CTL_ENET2_TD2_OFFSET (0x00fc)
#define IOMUXC_MUX_CTL_ENET2_TD1_OFFSET (0x0100)
#define IOMUXC_MUX_CTL_ENET2_TD0_OFFSET (0x0104)
#define IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET (0x0108)
#define IOMUXC_MUX_CTL_ENET2_TXC_OFFSET (0x010c)
#define IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET (0x0110)
#define IOMUXC_MUX_CTL_ENET2_RXC_OFFSET (0x0114)
#define IOMUXC_MUX_CTL_ENET2_RD0_OFFSET (0x0118)
#define IOMUXC_MUX_CTL_ENET2_RD1_OFFSET (0x011c)
#define IOMUXC_MUX_CTL_ENET2_RD2_OFFSET (0x0120)
#define IOMUXC_MUX_CTL_ENET2_RD3_OFFSET (0x0124)
#define IOMUXC_MUX_CTL_SD1_CLK_OFFSET (0x0128)
#define IOMUXC_MUX_CTL_SD1_CMD_OFFSET (0x012c)
#define IOMUXC_MUX_CTL_SD1_DATA0_OFFSET (0x0130)
#define IOMUXC_MUX_CTL_SD1_DATA1_OFFSET (0x0134)
#define IOMUXC_MUX_CTL_SD1_DATA2_OFFSET (0x0138)
#define IOMUXC_MUX_CTL_SD1_DATA3_OFFSET (0x013c)
#define IOMUXC_MUX_CTL_SD1_DATA4_OFFSET (0x0140)
#define IOMUXC_MUX_CTL_SD1_DATA5_OFFSET (0x0144)
#define IOMUXC_MUX_CTL_SD1_DATA6_OFFSET (0x0148)
#define IOMUXC_MUX_CTL_SD1_DATA7_OFFSET (0x014c)
#define IOMUXC_MUX_CTL_SD1_STROBE_OFFSET (0x0150)
#define IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET (0x0154)
#define IOMUXC_MUX_CTL_SD3_CLK_OFFSET (0x0158)
#define IOMUXC_MUX_CTL_SD3_CMD_OFFSET (0x015c)
#define IOMUXC_MUX_CTL_SD3_DATA0_OFFSET (0x0160)
#define IOMUXC_MUX_CTL_SD3_DATA1_OFFSET (0x0164)
#define IOMUXC_MUX_CTL_SD3_DATA2_OFFSET (0x0168)
#define IOMUXC_MUX_CTL_SD3_DATA3_OFFSET (0x016c)
#define IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET (0x0170)
#define IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET (0x0174)
#define IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET (0x0178)
#define IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET (0x017c)
#define IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET (0x0180)
#define IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET (0x0184)
#define IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET (0x0188)
#define IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET (0x018c)
#define IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET (0x0190)
#define IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET (0x0194)
#define IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET (0x0198)
#define IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET (0x019c)
#define IOMUXC_MUX_CTL_SD2_CD_B_OFFSET (0x01a0)
#define IOMUXC_MUX_CTL_SD2_CLK_OFFSET (0x01a4)
#define IOMUXC_MUX_CTL_SD2_CMD_OFFSET (0x01a8)
#define IOMUXC_MUX_CTL_SD2_DATA0_OFFSET (0x01ac)
#define IOMUXC_MUX_CTL_SD2_DATA1_OFFSET (0x01b0)
#define IOMUXC_MUX_CTL_SD2_DATA2_OFFSET (0x01b4)
#define IOMUXC_MUX_CTL_SD2_DATA3_OFFSET (0x01b8)
#define IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET (0x01bc)
#define IOMUXC_MUX_CTL_I2C1_SCL_OFFSET (0x01c0)
#define IOMUXC_MUX_CTL_I2C1_SDA_OFFSET (0x01c4)
#define IOMUXC_MUX_CTL_I2C2_SCL_OFFSET (0x01c8)
#define IOMUXC_MUX_CTL_I2C2_SDA_OFFSET (0x01cc)
#define IOMUXC_MUX_CTL_UART1_RXD_OFFSET (0x01d0)
#define IOMUXC_MUX_CTL_UART1_TXD_OFFSET (0x01d4)
#define IOMUXC_MUX_CTL_UART2_RXD_OFFSET (0x01d8)
#define IOMUXC_MUX_CTL_UART2_TXD_OFFSET (0x01dc)
#define IOMUXC_MUX_CTL_PDM_CLK_OFFSET (0x01e0)
#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET (0x01e4)
#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET (0x01e8)
#define IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET (0x01ec)
#define IOMUXC_MUX_CTL_SAI1_TXC_OFFSET (0x01f0)
#define IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET (0x01f4)
#define IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET (0x01f8)
#define IOMUXC_MUX_CTL_WDOG_ANY_OFFSET (0x01fc)
#define IOMUXC_PAD_CTL_DAP_TDI_OFFSET (0x0204)
#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET (0x0208)
#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET (0x020c)
#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET (0x0210)
#define IOMUXC_PAD_CTL_GPIO_IO00_OFFSET (0x0214)
#define IOMUXC_PAD_CTL_GPIO_IO01_OFFSET (0x0218)
#define IOMUXC_PAD_CTL_GPIO_IO02_OFFSET (0x021c)
#define IOMUXC_PAD_CTL_GPIO_IO03_OFFSET (0x0220)
#define IOMUXC_PAD_CTL_GPIO_IO04_OFFSET (0x0224)
#define IOMUXC_PAD_CTL_GPIO_IO05_OFFSET (0x0228)
#define IOMUXC_PAD_CTL_GPIO_IO06_OFFSET (0x022c)
#define IOMUXC_PAD_CTL_GPIO_IO07_OFFSET (0x0230)
#define IOMUXC_PAD_CTL_GPIO_IO08_OFFSET (0x0234)
#define IOMUXC_PAD_CTL_GPIO_IO09_OFFSET (0x0238)
#define IOMUXC_PAD_CTL_GPIO_IO10_OFFSET (0x023c)
#define IOMUXC_PAD_CTL_GPIO_IO11_OFFSET (0x0240)
#define IOMUXC_PAD_CTL_GPIO_IO12_OFFSET (0x0244)
#define IOMUXC_PAD_CTL_GPIO_IO13_OFFSET (0x0248)
#define IOMUXC_PAD_CTL_GPIO_IO14_OFFSET (0x024c)
#define IOMUXC_PAD_CTL_GPIO_IO15_OFFSET (0x0250)
#define IOMUXC_PAD_CTL_GPIO_IO16_OFFSET (0x0254)
#define IOMUXC_PAD_CTL_GPIO_IO17_OFFSET (0x0258)
#define IOMUXC_PAD_CTL_GPIO_IO18_OFFSET (0x025c)
#define IOMUXC_PAD_CTL_GPIO_IO19_OFFSET (0x0260)
#define IOMUXC_PAD_CTL_GPIO_IO20_OFFSET (0x0264)
#define IOMUXC_PAD_CTL_GPIO_IO21_OFFSET (0x0268)
#define IOMUXC_PAD_CTL_GPIO_IO22_OFFSET (0x026c)
#define IOMUXC_PAD_CTL_GPIO_IO23_OFFSET (0x0270)
#define IOMUXC_PAD_CTL_GPIO_IO24_OFFSET (0x0274)
#define IOMUXC_PAD_CTL_GPIO_IO25_OFFSET (0x0278)
#define IOMUXC_PAD_CTL_GPIO_IO26_OFFSET (0x027c)
#define IOMUXC_PAD_CTL_GPIO_IO27_OFFSET (0x0280)
#define IOMUXC_PAD_CTL_GPIO_IO28_OFFSET (0x0284)
#define IOMUXC_PAD_CTL_GPIO_IO29_OFFSET (0x0288)
#define IOMUXC_PAD_CTL_GPIO_IO30_OFFSET (0x028c)
#define IOMUXC_PAD_CTL_GPIO_IO31_OFFSET (0x0290)
#define IOMUXC_PAD_CTL_GPIO_IO32_OFFSET (0x0294)
#define IOMUXC_PAD_CTL_GPIO_IO33_OFFSET (0x0298)
#define IOMUXC_PAD_CTL_GPIO_IO34_OFFSET (0x029c)
#define IOMUXC_PAD_CTL_GPIO_IO35_OFFSET (0x02a0)
#define IOMUXC_PAD_CTL_GPIO_IO36_OFFSET (0x02a4)
#define IOMUXC_PAD_CTL_GPIO_IO37_OFFSET (0x02a8)
#define IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET (0x02ac)
#define IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET (0x02b0)
#define IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET (0x02b4)
#define IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET (0x02b8)
#define IOMUXC_PAD_CTL_ENET1_MDC_OFFSET (0x02bc)
#define IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET (0x02c0)
#define IOMUXC_PAD_CTL_ENET1_TD3_OFFSET (0x02c4)
#define IOMUXC_PAD_CTL_ENET1_TD2_OFFSET (0x02c8)
#define IOMUXC_PAD_CTL_ENET1_TD1_OFFSET (0x02cc)
#define IOMUXC_PAD_CTL_ENET1_TD0_OFFSET (0x02d0)
#define IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET (0x02d4)
#define IOMUXC_PAD_CTL_ENET1_TXC_OFFSET (0x02d8)
#define IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET (0x02dc)
#define IOMUXC_PAD_CTL_ENET1_RXC_OFFSET (0x02e0)
#define IOMUXC_PAD_CTL_ENET1_RD0_OFFSET (0x02e4)
#define IOMUXC_PAD_CTL_ENET1_RD1_OFFSET (0x02e8)
#define IOMUXC_PAD_CTL_ENET1_RD2_OFFSET (0x02ec)
#define IOMUXC_PAD_CTL_ENET1_RD3_OFFSET (0x02f0)
#define IOMUXC_PAD_CTL_ENET2_MDC_OFFSET (0x02f4)
#define IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET (0x02f8)
#define IOMUXC_PAD_CTL_ENET2_TD3_OFFSET (0x02fc)
#define IOMUXC_PAD_CTL_ENET2_TD2_OFFSET (0x0300)
#define IOMUXC_PAD_CTL_ENET2_TD1_OFFSET (0x0304)
#define IOMUXC_PAD_CTL_ENET2_TD0_OFFSET (0x0308)
#define IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET (0x030c)
#define IOMUXC_PAD_CTL_ENET2_TXC_OFFSET (0x0310)
#define IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET (0x0314)
#define IOMUXC_PAD_CTL_ENET2_RXC_OFFSET (0x0318)
#define IOMUXC_PAD_CTL_ENET2_RD0_OFFSET (0x031c)
#define IOMUXC_PAD_CTL_ENET2_RD1_OFFSET (0x0320)
#define IOMUXC_PAD_CTL_ENET2_RD2_OFFSET (0x0324)
#define IOMUXC_PAD_CTL_ENET2_RD3_OFFSET (0x0328)
#define IOMUXC_PAD_CTL_SD1_CLK_OFFSET (0x032c)
#define IOMUXC_PAD_CTL_SD1_CMD_OFFSET (0x0330)
#define IOMUXC_PAD_CTL_SD1_DATA0_OFFSET (0x0334)
#define IOMUXC_PAD_CTL_SD1_DATA1_OFFSET (0x0338)
#define IOMUXC_PAD_CTL_SD1_DATA2_OFFSET (0x033c)
#define IOMUXC_PAD_CTL_SD1_DATA3_OFFSET (0x0340)
#define IOMUXC_PAD_CTL_SD1_DATA4_OFFSET (0x0344)
#define IOMUXC_PAD_CTL_SD1_DATA5_OFFSET (0x0348)
#define IOMUXC_PAD_CTL_SD1_DATA6_OFFSET (0x034c)
#define IOMUXC_PAD_CTL_SD1_DATA7_OFFSET (0x0350)
#define IOMUXC_PAD_CTL_SD1_STROBE_OFFSET (0x0354)
#define IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET (0x0358)
#define IOMUXC_PAD_CTL_SD3_CLK_OFFSET (0x035c)
#define IOMUXC_PAD_CTL_SD3_CMD_OFFSET (0x0360)
#define IOMUXC_PAD_CTL_SD3_DATA0_OFFSET (0x0364)
#define IOMUXC_PAD_CTL_SD3_DATA1_OFFSET (0x0368)
#define IOMUXC_PAD_CTL_SD3_DATA2_OFFSET (0x036c)
#define IOMUXC_PAD_CTL_SD3_DATA3_OFFSET (0x0370)
#define IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET (0x0374)
#define IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET (0x0378)
#define IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET (0x037c)
#define IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET (0x0380)
#define IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET (0x0384)
#define IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET (0x0388)
#define IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET (0x038c)
#define IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET (0x0390)
#define IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET (0x0394)
#define IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET (0x0398)
#define IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET (0x039c)
#define IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET (0x03a0)
#define IOMUXC_PAD_CTL_SD2_CD_B_OFFSET (0x03a4)
#define IOMUXC_PAD_CTL_SD2_CLK_OFFSET (0x03a8)
#define IOMUXC_PAD_CTL_SD2_CMD_OFFSET (0x03ac)
#define IOMUXC_PAD_CTL_SD2_DATA0_OFFSET (0x03b0)
#define IOMUXC_PAD_CTL_SD2_DATA1_OFFSET (0x03b4)
#define IOMUXC_PAD_CTL_SD2_DATA2_OFFSET (0x03b8)
#define IOMUXC_PAD_CTL_SD2_DATA3_OFFSET (0x03bc)
#define IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET (0x03c0)
#define IOMUXC_PAD_CTL_I2C1_SCL_OFFSET (0x03c4)
#define IOMUXC_PAD_CTL_I2C1_SDA_OFFSET (0x03c8)
#define IOMUXC_PAD_CTL_I2C2_SCL_OFFSET (0x03cc)
#define IOMUXC_PAD_CTL_I2C2_SDA_OFFSET (0x03d0)
#define IOMUXC_PAD_CTL_UART1_RXD_OFFSET (0x03d4)
#define IOMUXC_PAD_CTL_UART1_TXD_OFFSET (0x03d8)
#define IOMUXC_PAD_CTL_UART2_RXD_OFFSET (0x03dc)
#define IOMUXC_PAD_CTL_UART2_TXD_OFFSET (0x03e0)
#define IOMUXC_PAD_CTL_PDM_CLK_OFFSET (0x03e4)
#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET (0x03e8)
#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET (0x03ec)
#define IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET (0x03f0)
#define IOMUXC_PAD_CTL_SAI1_TXC_OFFSET (0x03f4)
#define IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET (0x03f8)
#define IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET (0x03fc)
#define IOMUXC_PAD_CTL_WDOG_ANY_OFFSET (0x0400)
#define IOMUXC_PAD_CTL_FCCU_ERR0_OFFSET (0x0404)
#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0408)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET (0x040c)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET (0x0410)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET (0x0414)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET (0x0418)
#define IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET (0x041c)
#define IOMUXC_EXT1_CLK_SELECT_INPUT_OFFSET (0x0420)
#define IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET (0x0424)
#define IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET (0x0428)
#define IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET (0x042c)
#define IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET (0x0430)
#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET (0x0434)
#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET (0x0438)
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET (0x043c)
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET (0x0440)
#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0444)
#define IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0448)
#define IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x044c)
#define IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0450)
#define IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET (0x0454)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET (0x0458)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET (0x045c)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET (0x0460)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET (0x0464)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET (0x0468)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET (0x046c)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET (0x0470)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET (0x0474)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET (0x0478)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET (0x047c)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET (0x0480)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET (0x0484)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET (0x0488)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET (0x048c)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET (0x0490)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET (0x0494)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET (0x0498)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET (0x049c)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET (0x04a0)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET (0x04a4)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET (0x04a8)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET (0x04ac)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET (0x04b0)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET (0x04b4)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET (0x04b8)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET (0x04bc)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET (0x04c0)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET (0x04c4)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET (0x04c8)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET (0x04cc)
#define IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET (0x04d0)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET (0x04d4)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET (0x04d8)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET (0x04dc)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET (0x04e0)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET (0x04e4)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET (0x04e8)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET (0x04ec)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET (0x04f0)
#define IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET (0x04f4)
#define IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET (0x04f8)
#define IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET (0x04fc)
#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0500)
#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0504)
#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0508)
#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x050c)
#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0510)
#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0514)
#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0518)
#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x051c)
#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0520)
#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0524)
#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0528)
#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x052c)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET (0x0530)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET (0x0534)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET (0x0538)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET (0x053c)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET (0x0540)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET (0x0544)
#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET (0x0548)
#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET (0x054c)
#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET (0x0550)
#define IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x0554)
#define IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0558)
#define IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x055c)
#define IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x0560)
#define IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0564)
#define IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0568)
#define IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x056c)
#define IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0570)
#define IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0574)
#define IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x0578)
#define IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x057c)
#define IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0580)
#define IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0584)
#define IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0588)
#define IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x058c)
#define IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x0590)
#define IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x0594)
#define IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET (0x0598)
#define IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x059c)
#define IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET (0x05a0)
#define IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET (0x05a4)
#define IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x05a8)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET (0x05ac)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET (0x05b0)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET (0x05b4)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET (0x05b8)
#define IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x05bc)
#define IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET (0x05c0)
#define IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET (0x05c4)
#define IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET (0x05c8)
#define IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET (0x05cc)
#define IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET (0x05d0)
#define IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET (0x05d4)
#define IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET (0x05d8)
#define IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET (0x05dc)
#define IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET (0x05e0)
#define IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET (0x05e4)
#define IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET (0x05e8)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET (0x05ec)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET (0x05f0)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET (0x05f4)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET (0x05f8)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET (0x05fc)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET (0x0600)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET (0x0604)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET (0x0608)
#define IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET (0x060c)
#define IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET (0x0610)
#define IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET (0x0614)
#define IOMUXC_MUX_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDI_OFFSET)
#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO28_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO29_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO30 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO30_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO31 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO31_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO32 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO32_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO33 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO33_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO34 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO34_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO35 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO35_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO36 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO36_OFFSET)
#define IOMUXC_MUX_CTL_GPIO_IO37 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO37_OFFSET)
#define IOMUXC_MUX_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET)
#define IOMUXC_MUX_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET)
#define IOMUXC_MUX_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_MUX_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TXC_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RXC_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_MUX_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD3_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD3_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_MUX_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_MUX_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CLK_OFFSET)
#define IOMUXC_MUX_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CMD_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA0_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA1_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA2_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA3_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_MUX_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_MUX_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_MUX_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_MUX_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CLK_OFFSET)
#define IOMUXC_MUX_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CMD_OFFSET)
#define IOMUXC_MUX_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_MUX_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_MUX_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_MUX_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_DQS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_SCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_SS0_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_MUX_CTL_XSPI1_SS1_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_MUX_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_MUX_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CLK_OFFSET)
#define IOMUXC_MUX_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CMD_OFFSET)
#define IOMUXC_MUX_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_MUX_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_MUX_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_MUX_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_MUX_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_MUX_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_MUX_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_MUX_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_MUX_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_MUX_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_RXD_OFFSET)
#define IOMUXC_MUX_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_TXD_OFFSET)
#define IOMUXC_MUX_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_RXD_OFFSET)
#define IOMUXC_MUX_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_TXD_OFFSET)
#define IOMUXC_MUX_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_CLK_OFFSET)
#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_MUX_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_MUX_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_MUX_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_MUX_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_MUX_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_WDOG_ANY_OFFSET)
#define IOMUXC_PAD_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO28_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO29_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO30 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO30_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO31 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO31_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO32 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO32_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO33 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO33_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO34 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO34_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO35 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO35_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO36 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO36_OFFSET)
#define IOMUXC_PAD_CTL_GPIO_IO37 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO37_OFFSET)
#define IOMUXC_PAD_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET)
#define IOMUXC_PAD_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET)
#define IOMUXC_PAD_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_PAD_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TXC_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RXC_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_PAD_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD3_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD3_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CLK_OFFSET)
#define IOMUXC_PAD_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CMD_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA0_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA1_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA2_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA3_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_PAD_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_PAD_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_DQS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_SCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_SS0_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_CTL_XSPI1_SS1_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_PAD_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_PAD_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CLK_OFFSET)
#define IOMUXC_PAD_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_PAD_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_PAD_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_PAD_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_PAD_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_PAD_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_RXD_OFFSET)
#define IOMUXC_PAD_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_TXD_OFFSET)
#define IOMUXC_PAD_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_TXD_OFFSET)
#define IOMUXC_PAD_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_CLK_OFFSET)
#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_WDOG_ANY_OFFSET)
#define IOMUXC_PAD_CTL_FCCU_ERR0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_FCCU_ERR0_OFFSET)
#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET)
#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET)
#define IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET)
#define IOMUXC_EXT1_CLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_EXT1_CLK_SELECT_INPUT_OFFSET)
#define IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET)
#define IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET)
#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET)
#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET)
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET)
#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET)
#define IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET)
#define IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET)
#define IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET)
#define IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET)
#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET)
#define IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET)
#define IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET)
#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET)
#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET)
#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET)
#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET)
#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET)
#define IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET)
#define IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET)
#define IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET)
#define IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET)
#define IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET)
#define IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET)
#define IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET)
#define IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET)
#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET)
#define IOMUXC_JTAG_MUX_TCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET)
#define IOMUXC_JTAG_MUX_TDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET)
#define IOMUXC_JTAG_MUX_TMS_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET)

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arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h Normal file
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMX9_ITCM_BASE (0x00000000) /* 512 KB ITCM (FlexRAM) */
#define IMX9_FLEXSPI1_ALIAS_BASE (0x02000000) /* 32 MB FlexSPI1 (alias) */
#define IMX9_DTCM_BASE (0x20000000) /* 512 KB DTCM (FlexRAM) */
#define IMX9_OCRAM_BASE (0x20480000) /* 352 KB, OCRAM */
#define IMX9_FLEXSPI1_BASE (0x28000000) /* 128 MB FlexSPI1 */
#define IMX9_AIPS1_BASE (0x42000000) /* AIPS 8192KB */
#define IMX9_AIPS2_BASE (0x42800000) /* AIPS 8192KB */
#define IMX9_AIPS3_BASE (0x44000000) /* AIPS 8192KB */
#define IMX9_AIPS4_BASE (0x49000000) /* AIPS 8192KB */
#define IMX9_GPIO_MEM_BASE (0x43810000) /* GPIO 2-3-4-5 320KB region */
#define IMX9_GPIO1_BASE (0x47400000) /* GPIO 1 64KB region */
#define IMX9_DRAM_BASE (0x80000000) /* DRAM */
#define IMX9_DRAM_XIP_BASE (0x90000800) /* DRAM XIP */
#define IMX9_RPMSG_BASE (0x88000000) /* DRAM for VRING and RSC */
#define IMX9_ADC_BASE (0x44530000)
#define IMX9_ANALOG__AGDET_BASE (0x44487000)
#define IMX9_ANALOG__AUDIO_FRACT_PLL1_BASE (0x44481100)
#define IMX9_ANALOG__AUDIO_FRACT_PLL2_BASE (0x44481200)
#define IMX9_ANALOG__CMU0_BASE (0x44670000)
#define IMX9_ANALOG__FRO_BASE (0x44485000)
#define IMX9_ANALOG__OSC24M_BASE (0x44480000)
#define IMX9_ANALOG__PMRO_BASE (0x44484000)
#define IMX9_ANALOG__SFA_BASE (0x44483000)
#define IMX9_ANALOG__SYS_FRACT_PLL1_BASE (0x44481000)
#define IMX9_ANALOG__TCU_BASE (0x444C0000)
#define IMX9_ANALOG__TRGMUX_BASE (0x44531000)
#define IMX9_ANALOG__VDET_BASE (0x44486000)
#define IMX9_ANALOG__VIDEO_FRACT_PLL1_BASE (0x44481300)
#define IMX9_AON__AXBS_BASE (0x44510000)
#define IMX9_AON__BLK_CTRL_NS_AONMIX1_BASE (0x44210000)
#define IMX9_AON__BLK_CTRL_S_AONMIX2_BASE (0x444F0000)
#define IMX9_AON__CMUA1_BASE (0x44540000)
#define IMX9_AON__CMUA2_BASE (0x44650000)
#define IMX9_AON__CRCA_BASE (0x44660000)
#define IMX9_AON__CSTCU_BASE (0x44590000)
#define IMX9_AON__EDMA3_TCD1_BASE (0x44010000)
#define IMX9_AON__EIMA_BASE (0x44550000)
#define IMX9_AON__FCCU_BASE (0x44570000)
#define IMX9_AON__INTM_BASE (0x44580000)
#define IMX9_AON__IOMUXC0__IOMUXC_GPR_BASE (0x443D0000)
#define IMX9_AON__LSTCUA_BASE (0x445A0000)
#define IMX9_AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM_BASE (0x44401000)
#define IMX9_AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM_BASE (0x44420000)
#define IMX9_AON__M33_PCF1_BASE (0x443E0000)
#define IMX9_AON__M33_PSF1_BASE (0x443F0000)
#define IMX9_AON__MCM_BASE (0xE0080000)
#define IMX9_AON__ROMCP1_BASE (0x44430000)
#define IMX9_AON__SYS_CTR1__SYS_CTR_COMPARE_BASE (0x442A0000)
#define IMX9_AON__SYS_CTR1__SYS_CTR_CONTROL_BASE (0x44290000)
#define IMX9_AON__SYS_CTR1__SYS_CTR_READ_BASE (0x442B0000)
#define IMX9_AON__TCU_BASE (0x444B0000)
#define IMX9_BBSM__BBNSM_BASE (0x44440000)
#define IMX9_BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1_BASE (0x44410000)
#define IMX9_BBSM__TCU_BBSMMIX_BASE (0x444E0000)
#define IMX9_BLK_CTRL_CAMERAMIX_BASE (0x4AC10000)
#define IMX9_BLK_CTRL_NETCMIX_BASE (0x4C810000)
#define IMX9_CAMERA__DSI_CAMID_CSR_BASE (0x4ADE0000)
#define IMX9_CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI_BASE (0x4AD40000)
#define IMX9_CAMERA__DSI_MASTER_CSR_BASE (0x4AD10000)
#define IMX9_CAMERA__DSI_OR_CSI_PHY_CSR_BASE (0x4AD20000)
#define IMX9_CAMERA__DSI_PIXEL_FORMATTING_BASE (0x4AC00000)
#define IMX9_CAMERA__DSI_STREAM_CSR_BASE (0x4AD00000)
#define IMX9_CAMERA__EDMA5_TCDC_BASE (0x4AE20000)
#define IMX9_CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR_BASE (0x4AFF0C00)
#define IMX9_CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1000)
#define IMX9_CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR_BASE (0x4AFF0C80)
#define IMX9_CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1080)
#define IMX9_CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR_BASE (0x4AFF0D00)
#define IMX9_CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1100)
#define IMX9_CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR_BASE (0x4AFF0D80)
#define IMX9_CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1180)
#define IMX9_CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR_BASE (0x4AFF0E00)
#define IMX9_CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1200)
#define IMX9_CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR_BASE (0x4AFF0E80)
#define IMX9_CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1280)
#define IMX9_CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR_BASE (0x4AFF0F00)
#define IMX9_CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1300)
#define IMX9_CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR_BASE (0x4AFF0F80)
#define IMX9_CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1380)
#define IMX9_CAMERA__GPV__PROBE_ISI_MAIN_PROBE_BASE (0x4AFF0000)
#define IMX9_CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4AFF1400)
#define IMX9_CAMERA__GPV__PROBE_ISP_MAIN_PROBE_BASE (0x4AFF0400)
#define IMX9_CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4AFF1480)
#define IMX9_CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE_BASE (0x4AFF0800)
#define IMX9_CAMERA__ISI_BASE (0x4AD50000)
#define IMX9_CAMERA__ISP__ALIAS_BASE (0x4AE02000)
#define IMX9_CAMERA__ISP__AUTOFOCUS_BASE (0x4AE01700)
#define IMX9_CAMERA__ISP__BNR_BASE (0x4AE00800)
#define IMX9_CAMERA__ISP__CAS_BASE (0x4AE01500)
#define IMX9_CAMERA__ISP__CCONVMED_BASE (0x4AE014C0)
#define IMX9_CAMERA__ISP__COLOR_TEMP_BASE (0x4AE00400)
#define IMX9_CAMERA__ISP__DEMOSAIC_BASE (0x4AE01180)
#define IMX9_CAMERA__ISP__DF_BASE (0x4AE01440)
#define IMX9_CAMERA__ISP__DRC_BASE (0x4AE01300)
#define IMX9_CAMERA__ISP__EE_BASE (0x4AE01480)
#define IMX9_CAMERA__ISP__GCM_BASE (0x4AE01600)
#define IMX9_CAMERA__ISP__HC_BASE (0x4AE000C0)
#define IMX9_CAMERA__ISP__HDR_DECOMPRESS0_BASE (0x4AE00100)
#define IMX9_CAMERA__ISP__HDR_DECOMPRESS1_BASE (0x4AE00180)
#define IMX9_CAMERA__ISP__HDR_MERGE_BASE (0x4AE00300)
#define IMX9_CAMERA__ISP__IDBG1_BASE (0x4AE00FC0)
#define IMX9_CAMERA__ISP__IDBG2_BASE (0x4AE01FC0)
#define IMX9_CAMERA__ISP__IR_COMPRESS_BASE (0x4AE00780)
#define IMX9_CAMERA__ISP__NR_BASE (0x4AE01400)
#define IMX9_CAMERA__ISP__OB_WB0_BASE (0x4AE00200)
#define IMX9_CAMERA__ISP__OB_WB1_BASE (0x4AE00240)
#define IMX9_CAMERA__ISP__OB_WB2_BASE (0x4AE00280)
#define IMX9_CAMERA__ISP__PACKETIZER_BASE (0x4AE01580)
#define IMX9_CAMERA__ISP__PIPE_CONF_BASE (0x4AE00000)
#define IMX9_CAMERA__ISP__RGBIR_BASE (0x4AE00600)
#define IMX9_CAMERA__ISP__RGB_TO_YUV_BASE (0x4AE011C0)
#define IMX9_CAMERA__ISP__STAT_BASE (0x4AE00700)
#define IMX9_CAMERA__ISP__VIGNETTING_BASE (0x4AE00900)
#define IMX9_CAMERA__MUI_A1__MUA_BASE (0x4AC60000)
#define IMX9_CAMERA__MUI_A2__MUA_BASE (0x4AC70000)
#define IMX9_CAMERA__MUI_A3__MUA_BASE (0x4AC80000)
#define IMX9_CAMERA__MUI_A4__MUA_BASE (0x4AC90000)
#define IMX9_CAMERA__MUI_A5__MUA_BASE (0x4ACA0000)
#define IMX9_CAMERA__MUI_A6__MUA_BASE (0x4ACB0000)
#define IMX9_CAMERA__MUI_A7__MUA_BASE (0x4ACC0000)
#define IMX9_CAMERA__MUI_A8__MUA_BASE (0x4ACD0000)
#define IMX9_CAMERA__MUI_A9__MUA_BASE (0x4ACE0000)
#define IMX9_CAMERA__OCRAM_MECC_BASE (0x4ADD0000)
#define IMX9_CAMERA__TCU_BASE (0x4AC00000)
#define IMX9_CAN1_BASE (0x443A0000)
#define IMX9_CAN2_BASE (0x425B0000)
#define IMX9_CAN3_BASE (0x42600000)
#define IMX9_CAN4_BASE (0x427C0000)
#define IMX9_CAN5_BASE (0x427D0000)
#define IMX9_CCM_CTRL_BASE (0x44450000)
#define IMX9_CCMSRCGPC__GPC__GPC_GLOBAL_BASE (0x44474800)
#define IMX9_CCMSRCGPC__SRC__SRC_CENTRAL_REG_BASE (0x44460000)
#define IMX9_CCMSRCGPC__SRC__XSPR_ANAMIX_BASE (0x44460400)
#define IMX9_CCMSRCGPC__SRC__XSPR_AONMIX_BASE (0x44460800)
#define IMX9_CCMSRCGPC__SRC__XSPR_AONMIX_MEM_BASE (0x44460900)
#define IMX9_CCMSRCGPC__SRC__XSPR_BBSMMIX_BASE (0x44460C00)
#define IMX9_CCMSRCGPC__SRC__XSPR_CAMERAMIX_BASE (0x44461000)
#define IMX9_CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM_BASE (0x44461100)
#define IMX9_CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX_BASE (0x44461400)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_BASE (0x44461800)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM_BASE (0x44461900)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_BASE (0x44461C00)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM_BASE (0x44461D00)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_BASE (0x44462000)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM_BASE (0x44462100)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_BASE (0x44462400)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM_BASE (0x44462500)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_BASE (0x44462800)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM_BASE (0x44462900)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_BASE (0x44462C00)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM_BASE (0x44462D00)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_BASE (0x44463000)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0_BASE (0x44463100)
#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1_BASE (0x44463120)
#define IMX9_CCMSRCGPC__SRC__XSPR_DDRMIX_BASE (0x44463400)
#define IMX9_CCMSRCGPC__SRC__XSPR_DDRMIX_MEM_BASE (0x44463500)
#define IMX9_CCMSRCGPC__SRC__XSPR_DISPLAYMIX_BASE (0x44463800)
#define IMX9_CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM_BASE (0x44463900)
#define IMX9_CCMSRCGPC__SRC__XSPR_GPUMIX_BASE (0x44463C00)
#define IMX9_CCMSRCGPC__SRC__XSPR_GPUMIX_MEM_BASE (0x44463D00)
#define IMX9_CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM_BASE (0x44464100)
#define IMX9_CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP_BASE (0x44464000)
#define IMX9_CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON_BASE (0x44464400)
#define IMX9_CCMSRCGPC__SRC__XSPR_M7MIX_BASE (0x44464800)
#define IMX9_CCMSRCGPC__SRC__XSPR_M7MIX_MEM_BASE (0x44464900)
#define IMX9_CCMSRCGPC__SRC__XSPR_NETCMIX_BASE (0x44464C00)
#define IMX9_CCMSRCGPC__SRC__XSPR_NETCMIX_MEM_BASE (0x44464D00)
#define IMX9_CCMSRCGPC__SRC__XSPR_NOCMIX_BASE (0x44465000)
#define IMX9_CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0_BASE (0x44465100)
#define IMX9_CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1_BASE (0x44465120)
#define IMX9_CCMSRCGPC__SRC__XSPR_NPUMIX_BASE (0x44465400)
#define IMX9_CCMSRCGPC__SRC__XSPR_NPUMIX_MEM_BASE (0x44465500)
#define IMX9_CCMSRCGPC__SRC__XSPR_VPUMIX_BASE (0x44465800)
#define IMX9_CCMSRCGPC__SRC__XSPR_VPUMIX_MEM_BASE (0x44465900)
#define IMX9_CCMSRCGPC__SRC__XSPR_WAKEUPMIX_BASE (0x44465C00)
#define IMX9_CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM_BASE (0x44465D00)
#define IMX9_CCMSRCGPC__TCU_BASE (0x444D0000)
#define IMX9_CORTEXA__FRACT_PLL_ARMPLL_BASE (0x44481600)
#define IMX9_CORTEXA__TCU_BASE (0x4A400000)
#define IMX9_DDRC_BASE (0x4E080000)
#define IMX9_DDRC__BLK_CTRL_DDRMIX_BASE (0x4E010000)
#define IMX9_DDRC__CMU_1_BASE (0x4E060000)
#define IMX9_DDRC__CMU_2_BASE (0x4E070000)
#define IMX9_DDRC__FRACT_PLL_BASE (0x44481700)
#define IMX9_DDRC__LSTCU_BASE (0x4E050000)
#define IMX9_DDRC__TCU_BASE (0x4E000000)
#define IMX9_DISPLAY__BLK_CTRL_DISPLAYMIX_BASE (0x4B010000)
#define IMX9_DISPLAY__FRACT_PLL_BASE (0x44481900)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR_BASE (0x4B7E0800)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0A00)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR_BASE (0x4B7E0880)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0A80)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR_BASE (0x4B7E0900)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0B00)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR_BASE (0x4B7E0980)
#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0B80)
#define IMX9_DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0C00)
#define IMX9_DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0C80)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0D00)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0D80)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0E00)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0E80)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0F00)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0F80)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1000)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1080)
#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1100)
#define IMX9_DISPLAY__GPV__PROBE1_MAIN_PROBE_BASE (0x4B7E0000)
#define IMX9_DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4B7E1180)
#define IMX9_DISPLAY__GPV__PROBE_MAIN_PROBE_BASE (0x4B7E0400)
#define IMX9_DISPLAY__OCRAM_MECC_BASE (0x4B0F0000)
#define IMX9_DISPLAY__PIXEL_INTERLEAVER1_BASE (0x4B0D0000)
#define IMX9_DISPLAY__PIXEL_MAPPER_BASE (0x4B000000)
#define IMX9_DISPLAY_SEERIS_BASE (0x4B400000)
#define IMX9_DISPLAY__SEERIS__BLITBLEND_BASE (0x4B470000)
#define IMX9_DISPLAY__SEERIS__CLUT_clut_1_BASE (0x4B450400)
#define IMX9_DISPLAY__SEERIS__CLUT_clut_BASE (0x4B450000)
#define IMX9_DISPLAY__SEERIS__CMDSEQ_cmdseq_1_BASE (0x4B410100)
#define IMX9_DISPLAY__SEERIS__CMDSEQ_cmdseq_2_BASE (0x4B410180)
#define IMX9_DISPLAY__SEERIS__CMDSEQ_cmdseq_BASE (0x4B410000)
#define IMX9_DISPLAY__SEERIS__CONSTFRAME_1_BASE (0x4B500000)
#define IMX9_DISPLAY__SEERIS__CONSTFRAME_2_BASE (0x4B530000)
#define IMX9_DISPLAY__SEERIS__CONSTFRAME_3_BASE (0x4B540000)
#define IMX9_DISPLAY__SEERIS__CONSTFRAME_BASE (0x4B4F0000)
#define IMX9_DISPLAY__SEERIS__DITHER_1_BASE (0x4B770000)
#define IMX9_DISPLAY__SEERIS__DITHER_BASE (0x4B710000)
#define IMX9_DISPLAY__SEERIS__DOMAINBLEND_1_BASE (0x4B720000)
#define IMX9_DISPLAY__SEERIS__DOMAINBLEND_BASE (0x4B6A0000)
#define IMX9_DISPLAY__SEERIS__EXTDST_1_BASE (0x4B520000)
#define IMX9_DISPLAY__SEERIS__EXTDST_2_BASE (0x4B550000)
#define IMX9_DISPLAY__SEERIS__EXTDST_3_BASE (0x4B560000)
#define IMX9_DISPLAY__SEERIS__EXTDST_BASE (0x4B510000)
#define IMX9_DISPLAY__SEERIS__FETCHDECODE_1_BASE (0x4B490028)
#define IMX9_DISPLAY__SEERIS__FETCHDECODE_2_BASE (0x4B490060)
#define IMX9_DISPLAY__SEERIS__FETCHDECODE_3_BASE (0x4B490088)
#define IMX9_DISPLAY__SEERIS__FETCHDECODE_4_BASE (0x4B490098)
#define IMX9_DISPLAY__SEERIS__FETCHDECODE_5_BASE (0x4B490400)
#define IMX9_DISPLAY__SEERIS__FETCHDECODE_BASE (0x4B490000)
#define IMX9_DISPLAY__SEERIS__FETCHECO_10_BASE (0x4B630000)
#define IMX9_DISPLAY__SEERIS__FETCHECO_11_BASE (0x4B630010)
#define IMX9_DISPLAY__SEERIS__FETCHECO_12_BASE (0x4B630048)
#define IMX9_DISPLAY__SEERIS__FETCHECO_13_BASE (0x4B630060)
#define IMX9_DISPLAY__SEERIS__FETCHECO_14_BASE (0x4B630068)
#define IMX9_DISPLAY__SEERIS__FETCHECO_15_BASE (0x4B650000)
#define IMX9_DISPLAY__SEERIS__FETCHECO_16_BASE (0x4B650010)
#define IMX9_DISPLAY__SEERIS__FETCHECO_17_BASE (0x4B650048)
#define IMX9_DISPLAY__SEERIS__FETCHECO_18_BASE (0x4B650060)
#define IMX9_DISPLAY__SEERIS__FETCHECO_19_BASE (0x4B650068)
#define IMX9_DISPLAY__SEERIS__FETCHECO_1_BASE (0x4B4A0010)
#define IMX9_DISPLAY__SEERIS__FETCHECO_2_BASE (0x4B4A0048)
#define IMX9_DISPLAY__SEERIS__FETCHECO_3_BASE (0x4B4A0060)
#define IMX9_DISPLAY__SEERIS__FETCHECO_4_BASE (0x4B4A0068)
#define IMX9_DISPLAY__SEERIS__FETCHECO_5_BASE (0x4B610000)
#define IMX9_DISPLAY__SEERIS__FETCHECO_6_BASE (0x4B610010)
#define IMX9_DISPLAY__SEERIS__FETCHECO_7_BASE (0x4B610048)
#define IMX9_DISPLAY__SEERIS__FETCHECO_8_BASE (0x4B610060)
#define IMX9_DISPLAY__SEERIS__FETCHECO_9_BASE (0x4B610068)
#define IMX9_DISPLAY__SEERIS__FETCHECO_BASE (0x4B4A0000)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_10_BASE (0x4B5D01F8)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_11_BASE (0x4B5D0200)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_12_BASE (0x4B5D0400)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_13_BASE (0x4B5E0000)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_14_BASE (0x4B5E0018)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_15_BASE (0x4B5E0050)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_16_BASE (0x4B5E0088)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_17_BASE (0x4B5E00C0)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_18_BASE (0x4B5E00F8)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_19_BASE (0x4B5E0130)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_1_BASE (0x4B5D0018)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_20_BASE (0x4B5E0168)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_21_BASE (0x4B5E01A0)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_22_BASE (0x4B5E01D8)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_23_BASE (0x4B5E01F8)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_24_BASE (0x4B5E0200)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_25_BASE (0x4B5E0400)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_2_BASE (0x4B5D0050)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_3_BASE (0x4B5D0088)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_4_BASE (0x4B5D00C0)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_5_BASE (0x4B5D00F8)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_6_BASE (0x4B5D0130)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_7_BASE (0x4B5D0168)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_8_BASE (0x4B5D01A0)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_9_BASE (0x4B5D01D8)
#define IMX9_DISPLAY__SEERIS__FETCHLAYER_BASE (0x4B5D0000)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_10_BASE (0x4B484000)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_1_BASE (0x4B480020)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_2_BASE (0x4B480058)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_3_BASE (0x4B4800A0)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_4_BASE (0x4B4800B0)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_5_BASE (0x4B480100)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_6_BASE (0x4B480200)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_7_BASE (0x4B480400)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_8_BASE (0x4B480600)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_9_BASE (0x4B482000)
#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_BASE (0x4B480000)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_10_BASE (0x4B620000)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_11_BASE (0x4B620028)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_12_BASE (0x4B620060)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_13_BASE (0x4B620078)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_14_BASE (0x4B620088)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_15_BASE (0x4B640000)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_16_BASE (0x4B640028)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_17_BASE (0x4B640060)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_18_BASE (0x4B640078)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_19_BASE (0x4B640088)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_1_BASE (0x4B5F0028)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_2_BASE (0x4B5F0060)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_3_BASE (0x4B5F0078)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_4_BASE (0x4B5F0088)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_5_BASE (0x4B600000)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_6_BASE (0x4B600028)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_7_BASE (0x4B600060)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_8_BASE (0x4B600078)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_9_BASE (0x4B600088)
#define IMX9_DISPLAY__SEERIS__FETCHYUV_BASE (0x4B5F0000)
#define IMX9_DISPLAY__SEERIS__FILTER_BASE (0x4B4D0000)
#define IMX9_DISPLAY__SEERIS__FRAMEGEN_1_BASE (0x4B730000)
#define IMX9_DISPLAY__SEERIS__FRAMEGEN_BASE (0x4B6B0000)
#define IMX9_DISPLAY__SEERIS__HSCALER_1_BASE (0x4B670000)
#define IMX9_DISPLAY__SEERIS__HSCALER_BASE (0x4B4B0000)
#define IMX9_DISPLAY__SEERIS__IDHASH_1_BASE (0x4B6C1000)
#define IMX9_DISPLAY__SEERIS__IDHASH_BASE (0x4B6C0000)
#define IMX9_DISPLAY__SEERIS__LAYERBLEND_1_BASE (0x4B580000)
#define IMX9_DISPLAY__SEERIS__LAYERBLEND_2_BASE (0x4B590000)
#define IMX9_DISPLAY__SEERIS__LAYERBLEND_3_BASE (0x4B5A0000)
#define IMX9_DISPLAY__SEERIS__LAYERBLEND_4_BASE (0x4B5B0000)
#define IMX9_DISPLAY__SEERIS__LAYERBLEND_5_BASE (0x4B5C0000)
#define IMX9_DISPLAY__SEERIS__LAYERBLEND_BASE (0x4B570000)
#define IMX9_DISPLAY__SEERIS__LUT3D_1_BASE (0x4B702000)
#define IMX9_DISPLAY__SEERIS__LUT3D_2_BASE (0x4B750000)
#define IMX9_DISPLAY__SEERIS__LUT3D_3_BASE (0x4B752000)
#define IMX9_DISPLAY__SEERIS__LUT3D_BASE (0x4B700000)
#define IMX9_DISPLAY__SEERIS__MATRIX_1_BASE (0x4B660000)
#define IMX9_DISPLAY__SEERIS__MATRIX_BASE (0x4B460000)
#define IMX9_DISPLAY__SEERIS__MATRIXL_1_BASE (0x4B6F0030)
#define IMX9_DISPLAY__SEERIS__MATRIXL_2_BASE (0x4B760000)
#define IMX9_DISPLAY__SEERIS__MATRIXL_3_BASE (0x4B760030)
#define IMX9_DISPLAY__SEERIS__MATRIXL_BASE (0x4B6F0000)
#define IMX9_DISPLAY__SEERIS__ROP_BASE (0x4B440000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_BLITBLEND9CFG_BASE (0x4B471000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CLUT9CFG_BASE (0x4B451000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CMDSEQMASK_BASE (0x4B403000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME0CFG_BASE (0x4B4F1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME1CFG_BASE (0x4B531000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME4CFG_BASE (0x4B501000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME5CFG_BASE (0x4B541000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_DITHER0CFG_BASE (0x4B711000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_DITHER1CFG_BASE (0x4B771020)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_DOMAINMASK_BASE (0x4B402000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST0CFG_BASE (0x4B511000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST1CFG_BASE (0x4B551000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST4CFG_BASE (0x4B521000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST5CFG_BASE (0x4B561000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHDECODE9CFG_BASE (0x4B491000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO0CFG_BASE (0x4B611000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO1CFG_BASE (0x4B631000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO2CFG_BASE (0x4B651000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO9CFG_BASE (0x4B4A1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHLAYER0CFG_BASE (0x4B5D1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHLAYER1CFG_BASE (0x4B5E1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHROT9CFG_BASE (0x4B486000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV0CFG_BASE (0x4B601000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV1CFG_BASE (0x4B621000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV2CFG_BASE (0x4B641000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV3CFG_BASE (0x4B5F1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FILTER9CFG_BASE (0x4B4D1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_GENERALPURPOSE_BASE (0x4B412000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_HSCALER4CFG_BASE (0x4B671000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_HSCALER9CFG_BASE (0x4B4B1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IDHASH0CFG_BASE (0x4B6C3000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_1_BASE (0x4B411000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_2_BASE (0x4B431000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_3_BASE (0x4B781000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_4_BASE (0x4B791000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_5_BASE (0x4B7A1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_6_BASE (0x4B7B1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_BASE (0x4B401000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND1CFG_BASE (0x4B571000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND2CFG_BASE (0x4B581000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND3CFG_BASE (0x4B591000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND4CFG_BASE (0x4B5A1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND5CFG_BASE (0x4B5B1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND6CFG_BASE (0x4B5C1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_MATRIX4CFG_BASE (0x4B661000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_MATRIX9CFG_BASE (0x4B461000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_ROP9CFG_BASE (0x4B441000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_SIG0CFG_BASE (0x4B6D1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_SIG1CFG_BASE (0x4B741020)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_SIG2CFG_BASE (0x4B6E1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_STORE9CFG_BASE (0x4B4E1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_VSCALER4CFG_BASE (0x4B681000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_VSCALER9CFG_BASE (0x4B4C1000)
#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_XPC_BASE (0x4B420000)
#define IMX9_DISPLAY__SEERIS__SIG_1_BASE (0x4B6D0400)
#define IMX9_DISPLAY__SEERIS__SIG_2_BASE (0x4B6E0000)
#define IMX9_DISPLAY__SEERIS__SIG_3_BASE (0x4B6E0400)
#define IMX9_DISPLAY__SEERIS__SIG_4_BASE (0x4B740000)
#define IMX9_DISPLAY__SEERIS__SIG_5_BASE (0x4B740400)
#define IMX9_DISPLAY__SEERIS__SIG_BASE (0x4B6D0000)
#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_1_BASE (0x4B4E0038)
#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_2_BASE (0x4B4E0048)
#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_3_BASE (0x4B4E0070)
#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_BASE (0x4B4E0000)
#define IMX9_DISPLAY__SEERIS__VSCALER_1_BASE (0x4B680000)
#define IMX9_DISPLAY__SEERIS__VSCALER_BASE (0x4B4C0000)
#define IMX9_DISPLAY__TCU_BASE (0x4B000000)
#define IMX9_DMA3_BASE (0x44000000)
#define IMX9_DPU_IRQSTEER_BASE (0x4B0B0000)
#define IMX9_EDMA5_2_BASE (0x42000000)
#define IMX9_EDMA5_3_BASE (0x42210000)
#define IMX9_EDMA5_4_BASE (0x4AE10000)
#define IMX9_EMDIO0_PCI_HDR_TYPE0_BASE (0x4CB00000)
#define IMX9_EMDIO_BASE_BASE (0x4CCE0000)
#define IMX9_EMDIO_GLOBAL_BASE (0x4CCF0000)
#define IMX9_ENETC0_BASE_BASE (0x4CC10000)
#define IMX9_ENETC0_COMMON_BASE (0x4CC11000)
#define IMX9_ENETC0_ETH_MAC_PORT_BASE (0x4CC15000)
#define IMX9_ENETC0_GLOBAL_BASE (0x4CC20000)
#define IMX9_ENETC0_PCI_HDR_TYPE0_BASE (0x4CA00000)
#define IMX9_ENETC0_PORT_BASE (0x4CC14000)
#define IMX9_ENETC0_PSI_BASE (0x4CC00000)
#define IMX9_ENETC1_BASE_BASE (0x4CC50000)
#define IMX9_ENETC1_COMMON_BASE (0x4CC51000)
#define IMX9_ENETC1_ETH_MAC_PORT_BASE (0x4CC55000)
#define IMX9_ENETC1_GLOBAL_BASE (0x4CC60000)
#define IMX9_ENETC1_PCI_HDR_TYPE0_BASE (0x4CA40000)
#define IMX9_ENETC1_PORT_BASE (0x4CC54000)
#define IMX9_ENETC1_PSI_BASE (0x4CC40000)
#define IMX9_ENETC2_BASE_BASE (0x4CC90000)
#define IMX9_ENETC2_COMMON_BASE (0x4CC91000)
#define IMX9_ENETC2_ETH_MAC_PORT_BASE (0x4CC95000)
#define IMX9_ENETC2_GLOBAL_BASE (0x4CCA0000)
#define IMX9_ENETC2_PCI_HDR_TYPE0_BASE (0x4CA80000)
#define IMX9_ENETC2_PORT_BASE (0x4CC94000)
#define IMX9_ENETC2_PSI_BASE (0x4CC80000)
#define IMX9_ENETC_VSI0_BASE (0x4CD20000)
#define IMX9_ENETC_VSI1_BASE (0x4CD30000)
#define IMX9_ENETC_VSI2_BASE (0x4CD40000)
#define IMX9_ENETC_VSI3_BASE (0x4CD50000)
#define IMX9_ENETC_VSI4_BASE (0x4CD60000)
#define IMX9_ENETC_VSI5_BASE (0x4CD70000)
#define IMX9_ENET_PHY_MAC_ADAPTER_BASE (0x3E0000)
#define IMX9_ENET_PHY_PMA_MMD_BASE (0x20000)
#define IMX9_ENET_PHY_VS_MII_MMD_BASE (0x3E0000)
#define IMX9_ENET_PHY_VS_MMD1_BASE (0x3C0000)
#define IMX9_ENET_PHY_XS_PCS_MMD_BASE (0x60000)
#define IMX9_FLEXIO1_BASE (0x425C0000)
#define IMX9_FLEXIO2_BASE (0x425D0000)
#define IMX9_FLEXSPI_BASE (0x425E0000)
#define IMX9_GPC_CTRL_CA55_0_BASE (0x44471000)
#define IMX9_GPC_CTRL_CA55_1_BASE (0x44471800)
#define IMX9_GPC_CTRL_CA55_2_BASE (0x44472000)
#define IMX9_GPC_CTRL_CA55_3_BASE (0x44472800)
#define IMX9_GPC_CTRL_CA55_4_BASE (0x44473000)
#define IMX9_GPC_CTRL_CA55_5_BASE (0x44473800)
#define IMX9_GPC_CTRL_CA55_CLUSTER_BASE (0x44474000)
#define IMX9_GPC_CTRL_CM33_BASE (0x44470000)
#define IMX9_GPC_CTRL_CM7_BASE (0x44470800)
#define IMX9_GPIO1_BASE (0x47400000)
#define IMX9_GPIO2_BASE (0x43810000)
#define IMX9_GPIO3_BASE (0x43820000)
#define IMX9_GPIO4_BASE (0x43840000)
#define IMX9_GPIO5_BASE (0x43850000)
#define IMX9_GPU__BLK_CTRL_GPUMIX_BASE (0x4D810000)
#define IMX9_GPU__REG__GPU_MALI_DOORBELLS_BASE (0x4D980000)
#define IMX9_GPU__REG__GPU_MALI_GPU_REGISTERS_BASE (0x4D900000)
#define IMX9_GPU__REG__GPU_MALI_IPA_CONTROL_BASE (0x4D940000)
#define IMX9_GPU__REG__GPU_MALI_USER_BASE (0x4D910000)
#define IMX9_GPU__TCU_BASE (0x4D800000)
#define IMX9_HSIO__BLK_CTRL_HSIOMIX_BASE (0x4C010000)
#define IMX9_HSIO__GHZ_LN_PLL_BASE (0x44481800)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_BASE (0x980C0000)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0480)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0400)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0380)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0300)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE_BASE (0x980C0800)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_BASE (0x980C0280)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0200)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0180)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0100)
#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0080)
#define IMX9_HSIO__PCIE1__PCIE_DMA_IATU_BASE (0x4C360000)
#define IMX9_HSIO__PCIE1__PCIE_EP_BASE (0x4C300000)
#define IMX9_HSIO__PCIE1__PCIE_RC_BASE (0x4C300000)
#define IMX9_HSIO__PCIE1__PCIE_SHADOW_EP_BASE (0x4C320000)
#define IMX9_HSIO__PCIE1__SERDES_SS_BASE (0x4C340000)
#define IMX9_HSIO__PCIE2__PCIE_DMA_IATU_BASE (0x4C3E0000)
#define IMX9_HSIO__PCIE2__PCIE_EP_BASE (0x4C380000)
#define IMX9_HSIO__PCIE2__PCIE_RC_BASE (0x4C380000)
#define IMX9_HSIO__PCIE2__PCIE_SHADOW_EP_BASE (0x4C3A0000)
#define IMX9_HSIO__PCIE2__SERDES_SS_BASE (0x4C3C0000)
#define IMX9_HSIO__TCU_BASE (0x4C000000)
#define IMX9_HSIO__USB_3_01__GLUE_BASE (0x4C1F0000)
#define IMX9_HSIO__USB_3_01__USB3_BASE (0x4C100000)
#define IMX9_HSIO__USB_3_0_PHY__TCA_BASE (0x4C1FC000)
#define IMX9_I3C1_BASE (0x44330000)
#define IMX9_I3C2_BASE (0x42520000)
#define IMX9_IOMUXC_BASE (0x443C0000)
#define IMX9_IRQSTEER_BASE (0x44680000)
#define IMX9_LPI2C1_BASE (0x44340000)
#define IMX9_LPI2C2_BASE (0x44350000)
#define IMX9_LPI2C3_BASE (0x42530000)
#define IMX9_LPI2C4_BASE (0x42540000)
#define IMX9_LPI2C5_BASE (0x426B0000)
#define IMX9_LPI2C6_BASE (0x426C0000)
#define IMX9_LPI2C7_BASE (0x426D0000)
#define IMX9_LPI2C8_BASE (0x426E0000)
#define IMX9_LPIT1_BASE (0x442F0000)
#define IMX9_LPIT2_BASE (0x424C0000)
#define IMX9_LPSPI1_BASE (0x44360000)
#define IMX9_LPSPI2_BASE (0x44370000)
#define IMX9_LPSPI3_BASE (0x42550000)
#define IMX9_LPSPI4_BASE (0x42560000)
#define IMX9_LPSPI5_BASE (0x426F0000)
#define IMX9_LPSPI6_BASE (0x42700000)
#define IMX9_LPSPI7_BASE (0x42710000)
#define IMX9_LPSPI8_BASE (0x42720000)
#define IMX9_LPTMR1_BASE (0x44300000)
#define IMX9_LPTMR2_BASE (0x424D0000)
#define IMX9_LPUART1_BASE (0x44380000)
#define IMX9_LPUART2_BASE (0x44390000)
#define IMX9_LPUART3_BASE (0x42570000)
#define IMX9_LPUART4_BASE (0x42580000)
#define IMX9_LPUART5_BASE (0x42590000)
#define IMX9_LPUART6_BASE (0x425A0000)
#define IMX9_LPUART7_BASE (0x42690000)
#define IMX9_LPUART8_BASE (0x426A0000)
#define IMX9_LVDS_BASE (0x4B0C0000)
#define IMX9_M33_CACHE_CTRLPC_BASE (0x44400000)
#define IMX9_M33_CACHE_CTRLPS_BASE (0x44400800)
#define IMX9_M7__A7_APB_MCM1_BASE (0x4A0A0000)
#define IMX9_M7__CMU_M0_BASE (0x4A080000)
#define IMX9_M7__CMU_M1_BASE (0x4A090000)
#define IMX9_M7__EIM_BASE (0x4A060000)
#define IMX9_M7__ERM_BASE (0x4A070000)
#define IMX9_M7__LSTCU_M7MIX_BASE (0x4A050000)
#define IMX9_M7__TCU_BASE (0x4A000000)
#define IMX9_MIPI_CSI2_BASE (0x4AD30000)
#define IMX9_MIPI_DSI_BASE (0x4ACF0000)
#define IMX9_MSGINTR1_BASE (0x44690000)
#define IMX9_MSGINTR2_BASE (0x446A0000)
#define IMX9_MU5_MUA_BASE (0x44610000)
#define IMX9_MU7_MUB_BASE (0x42440000)
#define IMX9_MU8_MUB_BASE (0x42740000)
#define IMX9_NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0_BASE (0x4CA08000)
#define IMX9_NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0_BASE (0x4CB08000)
#define IMX9_NETC__IEPRC_1__IEPRC_IERB_BASE (0x4C8A0000)
#define IMX9_NETC__IEPRC_1__IEPRC_PRB_BASE (0x4C8B0000)
#define IMX9_NETC_IERB_BASE (0x4CDE0000)
#define IMX9_NETC_PRIV_BASE (0x4CDF0000)
#define IMX9_NETC__TCU_BASE (0x4C800000)
#define IMX9_NETC_VF1_PCI_HDR_TYPE0_BASE (0x4CA10000)
#define IMX9_NETC_VF2_PCI_HDR_TYPE0_BASE (0x4CA20000)
#define IMX9_NETC_VF3_PCI_HDR_TYPE0_BASE (0x4CA50000)
#define IMX9_NETC_VF4_PCI_HDR_TYPE0_BASE (0x4CA60000)
#define IMX9_NETC_VF5_PCI_HDR_TYPE0_BASE (0x4CA90000)
#define IMX9_NETC_VF6_PCI_HDR_TYPE0_BASE (0x4CAA0000)
#define IMX9_NOC__BLK_CTRL_NOCMIX_BASE (0x49000000)
#define IMX9_NOC__CMU_N0_BASE (0x49070000)
#define IMX9_NOC__CMU_N1_BASE (0x49080000)
#define IMX9_NOC__EIMN_BASE (0x49270000)
#define IMX9_NOC__GIC__GICA_BASE (0x48010000)
#define IMX9_NOC__GIC__GICDA_BASE (0x48120000)
#define IMX9_NOC__GIC__GICD_BASE (0x48000000)
#define IMX9_NOC__GIC__GICP_BASE (0x48030000)
#define IMX9_NOC__GIC__GICRLPI0_BASE (0x48060000)
#define IMX9_NOC__GIC__GICRLPI1_BASE (0x48080000)
#define IMX9_NOC__GIC__GICRLPI2_BASE (0x480A0000)
#define IMX9_NOC__GIC__GICRLPI3_BASE (0x480C0000)
#define IMX9_NOC__GIC__GICRLPI4_BASE (0x480E0000)
#define IMX9_NOC__GIC__GICRLPI5_BASE (0x48100000)
#define IMX9_NOC__GIC__GICRSGI0_BASE (0x48070000)
#define IMX9_NOC__GIC__GICRSGI1_BASE (0x48090000)
#define IMX9_NOC__GIC__GICRSGI2_BASE (0x480B0000)
#define IMX9_NOC__GIC__GICRSGI3_BASE (0x480D0000)
#define IMX9_NOC__GIC__GICRSGI4_BASE (0x480F0000)
#define IMX9_NOC__GIC__GICRSGI5_BASE (0x48110000)
#define IMX9_NOC__GIC__GICT_BASE (0x48020000)
#define IMX9_NOC__GIC__GITS0_BASE (0x48040000)
#define IMX9_NOC__GIC__GITS0TRANSLATER_BASE (0x48050000)
#define IMX9_NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER_BASE (0x49063080)
#define IMX9_NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR_BASE (0x49062400)
#define IMX9_NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063100)
#define IMX9_NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR_BASE (0x49062480)
#define IMX9_NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063180)
#define IMX9_NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR_BASE (0x49062E80)
#define IMX9_NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063780)
#define IMX9_NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR_BASE (0x49062F00)
#define IMX9_NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063800)
#define IMX9_NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR_BASE (0x49062F80)
#define IMX9_NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063880)
#define IMX9_NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR_BASE (0x49063000)
#define IMX9_NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063900)
#define IMX9_NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR_BASE (0x49062500)
#define IMX9_NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR_BASE (0x49062580)
#define IMX9_NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR_BASE (0x49062600)
#define IMX9_NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR_BASE (0x49062680)
#define IMX9_NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR_BASE (0x49062800)
#define IMX9_NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063200)
#define IMX9_NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR_BASE (0x49062880)
#define IMX9_NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063280)
#define IMX9_NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR_BASE (0x49062900)
#define IMX9_NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063300)
#define IMX9_NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR_BASE (0x49062980)
#define IMX9_NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063380)
#define IMX9_NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR_BASE (0x49062A00)
#define IMX9_NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063400)
#define IMX9_NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR_BASE (0x49062A80)
#define IMX9_NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063480)
#define IMX9_NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR_BASE (0x49062B00)
#define IMX9_NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063500)
#define IMX9_NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR_BASE (0x49062B80)
#define IMX9_NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063580)
#define IMX9_NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR_BASE (0x49062C00)
#define IMX9_NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063600)
#define IMX9_NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR_BASE (0x49062C80)
#define IMX9_NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR_BASE (0x49062D00)
#define IMX9_NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR_BASE (0x49062D80)
#define IMX9_NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063680)
#define IMX9_NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR_BASE (0x49062E00)
#define IMX9_NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063700)
#define IMX9_NOC__GPV__PROBE_M_E_0_MAIN_PROBE_BASE (0x49060000)
#define IMX9_NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063980)
#define IMX9_NOC__GPV__PROBE_M_E_10_MAIN_PROBE_BASE (0x49061C00)
#define IMX9_NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063D00)
#define IMX9_NOC__GPV__PROBE_M_E_11_MAIN_PROBE_BASE (0x49062000)
#define IMX9_NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063D80)
#define IMX9_NOC__GPV__PROBE_M_E_3_MAIN_PROBE_BASE (0x49060400)
#define IMX9_NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063A00)
#define IMX9_NOC__GPV__PROBE_M_E_4_MAIN_PROBE_BASE (0x49060800)
#define IMX9_NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063A80)
#define IMX9_NOC__GPV__PROBE_M_E_5_MAIN_PROBE_BASE (0x49060C00)
#define IMX9_NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063B00)
#define IMX9_NOC__GPV__PROBE_M_E_6_MAIN_PROBE_BASE (0x49061000)
#define IMX9_NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063B80)
#define IMX9_NOC__GPV__PROBE_M_E_7_MAIN_PROBE_BASE (0x49061400)
#define IMX9_NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063C00)
#define IMX9_NOC__GPV__PROBE_M_E_9_MAIN_PROBE_BASE (0x49061800)
#define IMX9_NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063C80)
#define IMX9_NOC__LSTCUN_BASE (0x490B0000)
#define IMX9_NOC__MMU_TBU_TCU__TBU0_BASE (0x49110000)
#define IMX9_NOC__MMU_TBU_TCU__TBU10_BASE (0x49230000)
#define IMX9_NOC__MMU_TBU_TCU__TBU11_BASE (0x49250000)
#define IMX9_NOC__MMU_TBU_TCU__TBU1_BASE (0x49130000)
#define IMX9_NOC__MMU_TBU_TCU__TBU2_BASE (0x49150000)
#define IMX9_NOC__MMU_TBU_TCU__TBU3_BASE (0x49170000)
#define IMX9_NOC__MMU_TBU_TCU__TBU4_BASE (0x49190000)
#define IMX9_NOC__MMU_TBU_TCU__TBU5_BASE (0x491B0000)
#define IMX9_NOC__MMU_TBU_TCU__TBU6_BASE (0x491D0000)
#define IMX9_NOC__MMU_TBU_TCU__TBU7_BASE (0x491F0000)
#define IMX9_NOC__MMU_TBU_TCU__TBU9_BASE (0x49210000)
#define IMX9_NOC__MMU_TBU_TCU__TCU_BASE (0x490D0000)
#define IMX9_NOC__SRAMCTL_BASE (0x490A0000)
#define IMX9_NOC__TCU_BASE (0x49040000)
#define IMX9_NPU__EIM_NPUMIX_BASE (0x4A860000)
#define IMX9_NPU__LSTCU_NPUMIX_BASE (0x4A850000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON0__NEUTRON_BASE (0x4ABC0000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON1__NEUTRON_BASE (0x4ABC1000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON2__NEUTRON_BASE (0x4ABC2000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON3__NEUTRON_BASE (0x4ABC3000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON_BASE (0x4ABC4000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC_BASE (0x4AB00000)
#define IMX9_NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV_BASE (0x4AB80000)
#define IMX9_NPU__TCU_BASE (0x4A800000)
#define IMX9_PDM_BASE (0x44520000)
#define IMX9_SAI1_BASE (0x443B0000)
#define IMX9_SAI2_BASE (0x4C880000)
#define IMX9_SAI3_BASE (0x42650000)
#define IMX9_SAI4_BASE (0x42660000)
#define IMX9_SAI5_BASE (0x42670000)
#define IMX9_SEMA42_1_BASE (0x44260000)
#define IMX9_SEMA42_2_BASE (0x42450000)
#define IMX9_TMPSNS1_BASE (0x44482000)
#define IMX9_TMPSNS2_BASE (0x4A440000)
#define IMX9_TMR0_BASE_BASE (0x4CCC0000)
#define IMX9_TMR0_GLOBAL_BASE (0x4CCD0000)
#define IMX9_TMR0_PCI_HDR_TYPE0_BASE (0x4CAC0000)
#define IMX9_TPM1_BASE (0x44310000)
#define IMX9_TPM2_BASE (0x44320000)
#define IMX9_TPM3_BASE (0x424E0000)
#define IMX9_TPM4_BASE (0x424F0000)
#define IMX9_TPM5_BASE (0x42500000)
#define IMX9_TPM6_BASE (0x42510000)
#define IMX9_TRDC1_BASE (0x44270000)
#define IMX9_TSTMR1_BASE (0x442C0000)
#define IMX9_TSTMR2_BASE (0x42480000)
#define IMX9_USBC_BASE (0x4C200000)
#define IMX9_USBNC_BASE (0x4C200200)
#define IMX9_VPU__BLK_CTRL_VPUMIX_BASE (0x4C410000)
#define IMX9_VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE_BASE (0x4C801000)
#define IMX9_VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C801580)
#define IMX9_VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C801480)
#define IMX9_VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR_BASE (0x4C801400)
#define IMX9_VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C801500)
#define IMX9_VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE_BASE (0x4C802000)
#define IMX9_VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C802580)
#define IMX9_VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR_BASE (0x4C802400)
#define IMX9_VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C802480)
#define IMX9_VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C802500)
#define IMX9_VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE_BASE (0x4C800000)
#define IMX9_VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE_BASE (0x4C800400)
#define IMX9_VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C800A00)
#define IMX9_VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR_BASE (0x4C800800)
#define IMX9_VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C800900)
#define IMX9_VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR_BASE (0x4C800880)
#define IMX9_VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C800980)
#define IMX9_VPU__JPEG_DEC_BASE (0x4C500100)
#define IMX9_VPU__JPEG_DEC_WRAP_BASE (0x4C500000)
#define IMX9_VPU__JPEG_ENC_BASE (0x4C550100)
#define IMX9_VPU__JPEG_ENC_WRAP_BASE (0x4C550000)
#define IMX9_VPU__TCU_BASE (0x4C400000)
#define IMX9_VPU__VPU__VPU_CODEC_BASE (0x4C480000)
#define IMX9_WAKEUP__AHBRM1_BASE (0x425E0000)
#define IMX9_WAKEUP__ATUA_BASE (0x42760000)
#define IMX9_WAKEUP__ATUM_BASE (0x42770000)
#define IMX9_WAKEUP__AUDIO_XCVR_BASE (0x42680000)
#define IMX9_WAKEUP__BLK_CTRL_WAKEUPMIX_BASE (0x42420000)
#define IMX9_WAKEUP__CMU1_BASE (0x42750000)
#define IMX9_WAKEUP__CMU2_BASE (0x427A0000)
#define IMX9_WAKEUP__DMA_CRC2_BASE (0x427B0000)
#define IMX9_WAKEUP__EDMA5_TCD2_BASE (0x42010000)
#define IMX9_WAKEUP__EDMA5_TCD3_BASE (0x42220000)
#define IMX9_WAKEUP__EIMW_BASE (0x42780000)
#define IMX9_WAKEUP__FLEXSPI_OTFAD_BASE (0x425E0000)
#define IMX9_WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER_BASE (0x42830000)
#define IMX9_WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER_BASE (0x43900000)
#define IMX9_WAKEUP__ROMCP2_BASE (0x42640000)
#define IMX9_WAKEUP__USDHC1_BASE (0x42850000)
#define IMX9_WAKEUP__USDHC2_BASE (0x42860000)
#define IMX9_WAKEUP__USDHC3_BASE (0x428B0000)
#define IMX9_WAKEUP__XSPI_RESPONDER_BASE (0x428A0000)
#define IMX9_WDOG1_BASE (0x442D0000)
#define IMX9_WDOG2_BASE (0x442E0000)
#define IMX9_WDOG3_BASE (0x42490000)
#define IMX9_WDOG4_BASE (0x424A0000)
#define IMX9_WDOG5_BASE (0x424B0000)

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arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h Normal file
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@ -0,0 +1,748 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IOMUXC_REGISTER_NOT_AVAILABLE 0x0000
#define IOMUXC_PAD_DAP_TDI_JTAG_MUX_TDI IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x0, IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TDI_MQS2_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TDI_NETC_TMR_1588_ALARM1 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TDI_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TDI_FLEXIO2_FLEXIO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TDI_GPIO3_IO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TDI_LPUART5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x6, IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET)
#define IOMUXC_PAD_DAP_TMS_SWDIO_JTAG_MUX_TMS IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x0, IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_PAD_DAP_TMS_SWDIO_CAN4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_PAD_DAP_TMS_SWDIO_FLEXIO2_FLEXIO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_PAD_DAP_TMS_SWDIO_GPIO3_IO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_PAD_DAP_TMS_SWDIO_LPUART5_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET)
#define IOMUXC_PAD_DAP_TCLK_SWCLK_JTAG_MUX_TCK IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x0, IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_PAD_DAP_TCLK_SWCLK_CAN4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x2, IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_PAD_DAP_TCLK_SWCLK_FLEXIO1_FLEXIO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_PAD_DAP_TCLK_SWCLK_GPIO3_IO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_PAD_DAP_TCLK_SWCLK_LPUART5_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x6, IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_JTAG_MUX_TDO IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_MQS2_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_NETC_TMR_1588_ALARM2 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x3, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_FLEXIO1_FLEXIO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_GPIO3_IO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_DAP_TDO_TRACESWO_LPUART5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x6, IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET)
#define IOMUXC_PAD_GPIO_IO00_GPIO2_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_GPIO_IO00_LPI2C3_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_GPIO_IO00_LPSPI6_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_GPIO_IO00_LPUART5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x5, IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_GPIO_IO00_LPI2C5_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_GPIO_IO00_FLEXIO1_FLEXIO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET)
#define IOMUXC_PAD_GPIO_IO01_GPIO2_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_GPIO_IO01_LPI2C3_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_GPIO_IO01_LPSPI6_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_GPIO_IO01_LPUART5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x5, IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_GPIO_IO01_LPI2C5_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_GPIO_IO01_FLEXIO1_FLEXIO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET)
#define IOMUXC_PAD_GPIO_IO02_GPIO2_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_GPIO_IO02_LPI2C4_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_GPIO_IO02_LPSPI6_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_GPIO_IO02_LPUART5_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x5, IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_GPIO_IO02_FLEXIO1_FLEXIO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET)
#define IOMUXC_PAD_GPIO_IO03_GPIO2_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_GPIO_IO03_LPI2C4_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_GPIO_IO03_LPSPI6_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_GPIO_IO03_LPUART5_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_GPIO_IO03_FLEXIO1_FLEXIO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_GPIO2_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_TPM3_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_PDM_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_CAN4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_LPSPI7_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_LPUART6_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x5, IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_LPI2C6_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_GPIO2_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_TPM4_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_PDM_BIT_STREAM00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_CAN4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x3, IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_LPSPI7_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_LPUART6_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x5, IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_LPI2C6_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_GPIO2_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_TPM5_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_PDM_BIT_STREAM01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_LPSPI7_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_LPUART6_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x5, IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_LPI2C7_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET)
#define IOMUXC_PAD_GPIO_IO07_GPIO2_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_GPIO_IO07_LPSPI3_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_GPIO_IO07_LPSPI7_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_GPIO_IO07_LPUART6_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_GPIO_IO07_LPI2C7_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET)
#define IOMUXC_PAD_GPIO_IO08_GPIO2_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_GPIO_IO08_LPSPI3_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_GPIO_IO08_TPM6_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_GPIO_IO08_LPUART7_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x5, IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_GPIO_IO08_LPI2C7_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_GPIO_IO08_FLEXIO1_FLEXIO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET)
#define IOMUXC_PAD_GPIO_IO09_GPIO2_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_GPIO_IO09_LPSPI3_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_GPIO_IO09_TPM3_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_GPIO_IO09_LPUART7_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x5, IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_GPIO_IO09_LPI2C7_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_GPIO_IO09_FLEXIO1_FLEXIO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET)
#define IOMUXC_PAD_GPIO_IO10_GPIO2_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_GPIO_IO10_LPSPI3_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_GPIO_IO10_TPM4_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_GPIO_IO10_LPUART7_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_GPIO_IO10_LPI2C8_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_GPIO_IO10_FLEXIO1_FLEXIO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET)
#define IOMUXC_PAD_GPIO_IO11_GPIO2_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_GPIO_IO11_LPSPI3_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_GPIO_IO11_TPM5_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_GPIO_IO11_LPUART7_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_GPIO_IO11_LPI2C8_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_GPIO_IO11_FLEXIO1_FLEXIO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_GPIO2_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_TPM3_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_PDM_BIT_STREAM02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_FLEXIO1_FLEXIO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_LPSPI8_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_LPUART8_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_LPI2C8_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO12_SAI3_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x7, IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_GPIO2_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_TPM4_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_PDM_BIT_STREAM03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_LPSPI8_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_LPUART8_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_LPI2C8_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO13_FLEXIO1_FLEXIO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET)
#define IOMUXC_PAD_GPIO_IO14_GPIO2_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_GPIO_IO14_LPUART3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_GPIO_IO14_LPSPI8_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_GPIO_IO14_LPUART8_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_GPIO_IO14_LPUART4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x6, IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_GPIO_IO14_FLEXIO1_FLEXIO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET)
#define IOMUXC_PAD_GPIO_IO15_GPIO2_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_GPIO_IO15_LPUART3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_GPIO_IO15_LPSPI8_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_GPIO_IO15_LPUART8_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_GPIO_IO15_LPUART4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x6, IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_GPIO_IO15_FLEXIO1_FLEXIO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_GPIO2_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_SAI3_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_PDM_BIT_STREAM02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_LPUART3_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x4, IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_LPSPI4_PCS2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_LPUART4_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x6, IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO16_FLEXIO1_FLEXIO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET)
#define IOMUXC_PAD_GPIO_IO17_GPIO2_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_GPIO_IO17_SAI3_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_GPIO_IO17_LPUART3_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_GPIO_IO17_LPSPI4_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_GPIO_IO17_LPUART4_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_GPIO_IO17_FLEXIO1_FLEXIO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET)
#define IOMUXC_PAD_GPIO_IO18_GPIO2_IO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_GPIO_IO18_SAI3_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x1, IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_GPIO_IO18_LPSPI5_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_GPIO_IO18_LPSPI4_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_GPIO_IO18_TPM5_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_GPIO_IO18_FLEXIO1_FLEXIO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_GPIO2_IO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_SAI3_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x1, IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_PDM_BIT_STREAM03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_FLEXIO1_FLEXIO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_LPSPI5_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_LPSPI4_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_TPM6_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO19_SAI3_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_GPIO2_IO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_SAI3_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_PDM_BIT_STREAM00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_LPSPI5_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_LPSPI4_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_TPM3_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO20_FLEXIO1_FLEXIO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_GPIO2_IO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_SAI3_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_PDM_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_FLEXIO1_FLEXIO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_LPSPI5_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_LPSPI4_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_TPM4_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO21_SAI3_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x7, IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_GPIO2_IO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_USDHC3_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x1, IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_SPDIF_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x2, IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_CAN5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_TPM5_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_TPM6_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_LPI2C5_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO22_FLEXIO1_FLEXIO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_GPIO2_IO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_USDHC3_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x1, IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_SPDIF_OUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_CAN5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x3, IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_TPM6_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_LPI2C5_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO23_FLEXIO1_FLEXIO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET)
#define IOMUXC_PAD_GPIO_IO24_GPIO2_IO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_GPIO_IO24_USDHC3_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_GPIO_IO24_TPM3_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_GPIO_IO24_JTAG_MUX_TDO IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_GPIO_IO24_LPSPI6_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_GPIO_IO24_FLEXIO1_FLEXIO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_GPIO2_IO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_USDHC3_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_TPM4_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_JTAG_MUX_TCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x5, IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_LPSPI7_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO25_FLEXIO1_FLEXIO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_GPIO2_IO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_USDHC3_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_PDM_BIT_STREAM01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_FLEXIO1_FLEXIO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_TPM5_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_JTAG_MUX_TDI IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x5, IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_LPSPI8_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO26_SAI3_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_GPIO2_IO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_USDHC3_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x2, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_TPM6_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_JTAG_MUX_TMS IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x5, IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_LPSPI5_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO27_FLEXIO1_FLEXIO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET)
#define IOMUXC_PAD_GPIO_IO28_GPIO2_IO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET)
#define IOMUXC_PAD_GPIO_IO28_LPI2C3_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET)
#define IOMUXC_PAD_GPIO_IO28_CAN3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET)
#define IOMUXC_PAD_GPIO_IO28_FLEXIO1_FLEXIO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET)
#define IOMUXC_PAD_GPIO_IO29_GPIO2_IO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET)
#define IOMUXC_PAD_GPIO_IO29_LPI2C3_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET)
#define IOMUXC_PAD_GPIO_IO29_CAN3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x2, IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET)
#define IOMUXC_PAD_GPIO_IO29_FLEXIO1_FLEXIO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET)
#define IOMUXC_PAD_GPIO_IO30_GPIO2_IO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET)
#define IOMUXC_PAD_GPIO_IO30_LPI2C4_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET)
#define IOMUXC_PAD_GPIO_IO30_CAN5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET)
#define IOMUXC_PAD_GPIO_IO30_FLEXIO1_FLEXIO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET)
#define IOMUXC_PAD_GPIO_IO31_GPIO2_IO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET)
#define IOMUXC_PAD_GPIO_IO31_LPI2C4_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET)
#define IOMUXC_PAD_GPIO_IO31_CAN5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x2, IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET)
#define IOMUXC_PAD_GPIO_IO31_FLEXIO1_FLEXIO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET)
#define IOMUXC_PAD_GPIO_IO32_GPIO5_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET)
#define IOMUXC_PAD_GPIO_IO32_PCIE1_CLKREQ_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET)
#define IOMUXC_PAD_GPIO_IO32_LPUART6_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x2, IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET)
#define IOMUXC_PAD_GPIO_IO32_LPSPI4_PCS2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET)
#define IOMUXC_PAD_GPIO_IO33_GPIO5_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO33_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO33_OFFSET)
#define IOMUXC_PAD_GPIO_IO33_LPUART6_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO33_OFFSET, 0x2, IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO33_OFFSET)
#define IOMUXC_PAD_GPIO_IO33_LPSPI4_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO33_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO33_OFFSET)
#define IOMUXC_PAD_GPIO_IO34_GPIO5_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO34_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO34_OFFSET)
#define IOMUXC_PAD_GPIO_IO34_LPUART6_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO34_OFFSET, 0x2, IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO34_OFFSET)
#define IOMUXC_PAD_GPIO_IO34_LPSPI4_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO34_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO34_OFFSET)
#define IOMUXC_PAD_GPIO_IO35_GPIO5_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET)
#define IOMUXC_PAD_GPIO_IO35_PCIE2_CLKREQ_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET)
#define IOMUXC_PAD_GPIO_IO35_LPUART6_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET)
#define IOMUXC_PAD_GPIO_IO35_LPSPI4_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET)
#define IOMUXC_PAD_GPIO_IO36_GPIO5_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO36_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO36_OFFSET)
#define IOMUXC_PAD_GPIO_IO36_LPUART7_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO36_OFFSET, 0x2, IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO36_OFFSET)
#define IOMUXC_PAD_GPIO_IO36_LPSPI4_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO36_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO36_OFFSET)
#define IOMUXC_PAD_GPIO_IO37_GPIO5_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO37_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO37_OFFSET)
#define IOMUXC_PAD_GPIO_IO37_LPUART7_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO37_OFFSET, 0x2, IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO37_OFFSET)
#define IOMUXC_PAD_GPIO_IO37_LPSPI4_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO37_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO37_OFFSET)
#define IOMUXC_PAD_CCM_CLKO1_CLKO_1 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET)
#define IOMUXC_PAD_CCM_CLKO1_NETC_TMR_1588_TRIG1 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET)
#define IOMUXC_PAD_CCM_CLKO1_FLEXIO1_FLEXIO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET)
#define IOMUXC_PAD_CCM_CLKO1_GPIO3_IO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET)
#define IOMUXC_PAD_CCM_CLKO2_CLKO_2 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET)
#define IOMUXC_PAD_CCM_CLKO2_NETC_TMR_1588_PP1 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET)
#define IOMUXC_PAD_CCM_CLKO2_FLEXIO1_FLEXIO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET)
#define IOMUXC_PAD_CCM_CLKO2_GPIO3_IO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET)
#define IOMUXC_PAD_CCM_CLKO3_CLKO_3 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_PAD_CCM_CLKO3_NETC_TMR_1588_TRIG2 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_PAD_CCM_CLKO3_CAN3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_PAD_CCM_CLKO3_FLEXIO2_FLEXIO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_PAD_CCM_CLKO3_GPIO4_IO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET)
#define IOMUXC_PAD_CCM_CLKO4_CLKO_4 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_PAD_CCM_CLKO4_NETC_TMR_1588_PP2 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_PAD_CCM_CLKO4_CAN3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x2, IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_PAD_CCM_CLKO4_FLEXIO2_FLEXIO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_PAD_CCM_CLKO4_GPIO4_IO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET)
#define IOMUXC_PAD_ENET1_MDC_NETC_MDC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_ENET1_MDC_LPUART3_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_ENET1_MDC_I3C2_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x2, IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_ENET1_MDC_USB1_OTG_ID IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_ENET1_MDC_FLEXIO2_FLEXIO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_ENET1_MDC_GPIO4_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET)
#define IOMUXC_PAD_ENET1_MDIO_NETC_MDIO IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_ENET1_MDIO_LPUART3_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_ENET1_MDIO_I3C2_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x2, IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_ENET1_MDIO_USB1_OTG_PWR IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_ENET1_MDIO_FLEXIO2_FLEXIO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_ENET1_MDIO_GPIO4_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET)
#define IOMUXC_PAD_ENET1_TD3_ETH0_RGMII_TD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_PAD_ENET1_TD3_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_PAD_ENET1_TD3_USB2_OTG_ID IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_PAD_ENET1_TD3_FLEXIO2_FLEXIO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_PAD_ENET1_TD3_GPIO4_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET)
#define IOMUXC_PAD_ENET1_TD2_ETH0_RGMII_TD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_ENET1_TD2_ETH0_RMII_REF50_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_ENET1_TD2_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x2, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_ENET1_TD2_USB2_OTG_OC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_ENET1_TD2_FLEXIO2_FLEXIO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_ENET1_TD2_GPIO4_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_ETH0_RGMII_TD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_LPUART3_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_USB1_OTG_OC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_FLEXIO2_FLEXIO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_GPIO4_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD1_ETH0_RMII_TXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET)
#define IOMUXC_PAD_ENET1_TD0_ETH0_RGMII_TD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_PAD_ENET1_TD0_LPUART3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_PAD_ENET1_TD0_ETH0_RMII_TXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_PAD_ENET1_TD0_FLEXIO2_FLEXIO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_PAD_ENET1_TD0_GPIO4_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET)
#define IOMUXC_PAD_ENET1_TX_CTL_ETH0_RGMII_TX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_TX_CTL_LPUART3_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_TX_CTL_ETH0_RMII_TX_EN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_TX_CTL_FLEXIO2_FLEXIO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_TX_CTL_GPIO4_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_TXC_ETH0_RGMII_TX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET)
#define IOMUXC_PAD_ENET1_TXC_ENET_CLK_ROOT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET)
#define IOMUXC_PAD_ENET1_TXC_FLEXIO2_FLEXIO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET)
#define IOMUXC_PAD_ENET1_TXC_GPIO4_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET)
#define IOMUXC_PAD_ENET1_RX_CTL_ETH0_RGMII_RX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_RX_CTL_LPUART3_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_RX_CTL_ETH0_RMII_CRS_DV IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_RX_CTL_USB2_OTG_PWR IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_RX_CTL_FLEXIO2_FLEXIO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_RX_CTL_GPIO4_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET1_RXC_ETH0_RGMII_RX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET)
#define IOMUXC_PAD_ENET1_RXC_ETH0_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x1, IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET)
#define IOMUXC_PAD_ENET1_RXC_FLEXIO2_FLEXIO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET)
#define IOMUXC_PAD_ENET1_RXC_GPIO4_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET)
#define IOMUXC_PAD_ENET1_RD0_ETH0_RGMII_RD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_PAD_ENET1_RD0_LPUART3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_PAD_ENET1_RD0_ETH0_RMII_RXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_PAD_ENET1_RD0_FLEXIO2_FLEXIO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_PAD_ENET1_RD0_GPIO4_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET)
#define IOMUXC_PAD_ENET1_RD1_ETH0_RGMII_RD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_ENET1_RD1_LPUART3_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_ENET1_RD1_ETH0_RMII_RXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_ENET1_RD1_LPTMR2_ALT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x3, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_ENET1_RD1_FLEXIO2_FLEXIO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_ENET1_RD1_GPIO4_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET)
#define IOMUXC_PAD_ENET1_RD2_ETH0_RGMII_RD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_PAD_ENET1_RD2_ETH0_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x2, IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_PAD_ENET1_RD2_LPTMR2_ALT2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x3, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_PAD_ENET1_RD2_FLEXIO2_FLEXIO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_PAD_ENET1_RD2_GPIO4_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET)
#define IOMUXC_PAD_ENET1_RD3_ETH0_RGMII_RD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET)
#define IOMUXC_PAD_ENET1_RD3_LPTMR2_ALT3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x3, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET)
#define IOMUXC_PAD_ENET1_RD3_FLEXIO2_FLEXIO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET)
#define IOMUXC_PAD_ENET1_RD3_GPIO4_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET)
#define IOMUXC_PAD_ENET2_MDC_NETC_MDC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_PAD_ENET2_MDC_LPUART4_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_PAD_ENET2_MDC_SAI2_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_PAD_ENET2_MDC_FLEXIO2_FLEXIO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_PAD_ENET2_MDC_GPIO4_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET)
#define IOMUXC_PAD_ENET2_MDIO_NETC_MDIO IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_PAD_ENET2_MDIO_LPUART4_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_PAD_ENET2_MDIO_SAI2_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_PAD_ENET2_MDIO_FLEXIO2_FLEXIO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_PAD_ENET2_MDIO_GPIO4_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET)
#define IOMUXC_PAD_ENET2_TD3_ETH1_RGMII_TD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET)
#define IOMUXC_PAD_ENET2_TD3_SAI2_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET)
#define IOMUXC_PAD_ENET2_TD3_FLEXIO2_FLEXIO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET)
#define IOMUXC_PAD_ENET2_TD3_GPIO4_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET)
#define IOMUXC_PAD_ENET2_TD2_ETH1_RGMII_TD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_ENET2_TD2_ETH1_RMII_REF50_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_ENET2_TD2_SAI2_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_ENET2_TD2_SAI4_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_ENET2_TD2_FLEXIO2_FLEXIO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_ENET2_TD2_GPIO4_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_ETH1_RGMII_TD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_LPUART4_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_SAI2_RX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_SAI4_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_FLEXIO2_FLEXIO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_GPIO4_IO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD1_ETH1_RMII_TXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_ETH1_RGMII_TD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_LPUART4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x1, IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_SAI2_RX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_SAI4_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_FLEXIO2_FLEXIO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_GPIO4_IO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TD0_ETH1_RMII_TXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET)
#define IOMUXC_PAD_ENET2_TX_CTL_ETH1_RGMII_TX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_TX_CTL_LPUART4_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_TX_CTL_SAI2_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_TX_CTL_ETH1_RMII_TX_EN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_TX_CTL_FLEXIO2_FLEXIO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_TX_CTL_GPIO4_IO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_TXC_ETH1_RGMII_TX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_PAD_ENET2_TXC_ENET_CLK_ROOT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_PAD_ENET2_TXC_SAI2_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_PAD_ENET2_TXC_FLEXIO2_FLEXIO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_PAD_ENET2_TXC_GPIO4_IO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET)
#define IOMUXC_PAD_ENET2_RX_CTL_ETH1_RGMII_RX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_RX_CTL_LPUART4_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_RX_CTL_SAI2_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_RX_CTL_FLEXIO2_FLEXIO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_RX_CTL_GPIO4_IO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_RX_CTL_ETH1_RMII_CRS_DV IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET)
#define IOMUXC_PAD_ENET2_RXC_ETH1_RGMII_RX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_ENET2_RXC_ETH1_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x1, IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_ENET2_RXC_SAI2_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_ENET2_RXC_SAI4_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_ENET2_RXC_FLEXIO2_FLEXIO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_ENET2_RXC_GPIO4_IO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_ETH1_RGMII_RD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_LPUART4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x1, IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_SAI2_TX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_SAI4_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_FLEXIO2_FLEXIO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_GPIO4_IO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD0_ETH1_RMII_RXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_ETH1_RGMII_RD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_SPDIF_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x1, IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_SAI2_TX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_SAI4_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_FLEXIO2_FLEXIO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_GPIO4_IO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD1_ETH1_RMII_RXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_ETH1_RGMII_RD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_LPUART4_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x1, IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_SAI2_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_MQS2_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_FLEXIO2_FLEXIO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_GPIO4_IO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD2_ETH1_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x6, IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET)
#define IOMUXC_PAD_ENET2_RD3_ETH1_RGMII_RD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_ENET2_RD3_SPDIF_OUT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_ENET2_RD3_SPDIF_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x2, IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_ENET2_RD3_MQS2_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_ENET2_RD3_FLEXIO2_FLEXIO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_ENET2_RD3_GPIO4_IO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET)
#define IOMUXC_PAD_SD1_CLK_USDHC1_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CLK_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CLK_OFFSET)
#define IOMUXC_PAD_SD1_CLK_FLEXIO1_FLEXIO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_CLK_OFFSET)
#define IOMUXC_PAD_SD1_CLK_GPIO3_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CLK_OFFSET)
#define IOMUXC_PAD_SD1_CMD_USDHC1_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CMD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CMD_OFFSET)
#define IOMUXC_PAD_SD1_CMD_FLEXIO1_FLEXIO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CMD_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_CMD_OFFSET)
#define IOMUXC_PAD_SD1_CMD_GPIO3_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CMD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CMD_OFFSET)
#define IOMUXC_PAD_SD1_DATA0_USDHC1_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA0_OFFSET)
#define IOMUXC_PAD_SD1_DATA0_FLEXIO1_FLEXIO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA0_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA0_OFFSET)
#define IOMUXC_PAD_SD1_DATA0_GPIO3_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA0_OFFSET)
#define IOMUXC_PAD_SD1_DATA1_USDHC1_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA1_OFFSET)
#define IOMUXC_PAD_SD1_DATA1_FLEXIO1_FLEXIO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA1_OFFSET)
#define IOMUXC_PAD_SD1_DATA1_GPIO3_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA1_OFFSET)
#define IOMUXC_PAD_SD1_DATA2_USDHC1_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA2_OFFSET)
#define IOMUXC_PAD_SD1_DATA2_FLEXIO1_FLEXIO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA2_OFFSET)
#define IOMUXC_PAD_SD1_DATA2_GPIO3_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA2_OFFSET)
#define IOMUXC_PAD_SD1_DATA3_USDHC1_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET)
#define IOMUXC_PAD_SD1_DATA3_FLEXSPI1_A_SS1_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET)
#define IOMUXC_PAD_SD1_DATA3_FLEXIO1_FLEXIO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET)
#define IOMUXC_PAD_SD1_DATA3_GPIO3_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET)
#define IOMUXC_PAD_SD1_DATA4_USDHC1_DATA4 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_PAD_SD1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_PAD_SD1_DATA4_FLEXIO1_FLEXIO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_PAD_SD1_DATA4_GPIO3_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_PAD_SD1_DATA4_XSPI_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET)
#define IOMUXC_PAD_SD1_DATA5_USDHC1_DATA5 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_SD1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_SD1_DATA5_USDHC1_RESET_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_SD1_DATA5_FLEXIO1_FLEXIO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_SD1_DATA5_GPIO3_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_SD1_DATA5_XSPI_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET)
#define IOMUXC_PAD_SD1_DATA6_USDHC1_DATA6 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_SD1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_SD1_DATA6_USDHC1_CD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_SD1_DATA6_FLEXIO1_FLEXIO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_SD1_DATA6_GPIO3_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_SD1_DATA6_XSPI_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET)
#define IOMUXC_PAD_SD1_DATA7_USDHC1_DATA7 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_SD1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_SD1_DATA7_USDHC1_WP IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_SD1_DATA7_FLEXIO1_FLEXIO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_SD1_DATA7_GPIO3_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_SD1_DATA7_XSPI_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET)
#define IOMUXC_PAD_SD1_STROBE_USDHC1_STROBE IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_PAD_SD1_STROBE_FLEXSPI1_A_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_PAD_SD1_STROBE_FLEXIO1_FLEXIO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_PAD_SD1_STROBE_GPIO3_IO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_PAD_SD1_STROBE_XSPI_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x6, IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET)
#define IOMUXC_PAD_SD2_VSELECT_USDHC2_VSELECT IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_PAD_SD2_VSELECT_USDHC2_WP IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_PAD_SD2_VSELECT_LPTMR2_ALT3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x2, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_PAD_SD2_VSELECT_FLEXIO1_FLEXIO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_PAD_SD2_VSELECT_GPIO3_IO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET)
#define IOMUXC_PAD_SD3_CLK_USDHC3_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x0, IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CLK_SAI5_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CLK_SAI5_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CLK_FLEXIO1_FLEXIO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CLK_GPIO3_IO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CLK_XSPI_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x6, IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET)
#define IOMUXC_PAD_SD3_CMD_USDHC3_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x0, IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_CMD_FLEXSPI1_A_SS0_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_CMD_SAI5_TX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_CMD_SAI5_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_CMD_FLEXIO1_FLEXIO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_CMD_GPIO3_IO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_CMD_XSPI_CS IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x6, IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_USDHC3_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_SAI5_TX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_SAI5_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_FLEXIO1_FLEXIO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_GPIO3_IO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA0_XSPI_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_USDHC3_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_SAI5_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_SAI5_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_FLEXIO1_FLEXIO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_GPIO3_IO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA1_XSPI_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_USDHC3_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_SAI5_RX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_SAI5_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_FLEXIO1_FLEXIO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_GPIO3_IO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA2_XSPI_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_USDHC3_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_SAI5_RX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_SAI5_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_FLEXIO1_FLEXIO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_GPIO3_IO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_SD3_DATA3_XSPI_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA0_SAI2_TX_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA0_SAI4_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA0_SAI4_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA0_XSPI_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA0_GPIO5_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA1_SAI2_TX_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA1_SAI4_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA1_SAI4_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA1_XSPI_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA1_GPIO5_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA2_SAI2_TX_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA2_SAI4_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA2_XSPI_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA2_GPIO5_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA3_SAI2_TX_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA3_SAI4_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA3_XSPI_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA3_GPIO5_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA4_SAI5_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA4_SAI5_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA4_XSPI_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA4_GPIO5_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA5_SAI5_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA5_SAI5_RX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA5_SAI2_RX_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA5_XSPI_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA5_GPIO5_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA6_SAI5_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA6_SAI5_RX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA6_SAI2_RX_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA6_XSPI_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA6_GPIO5_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA7_SAI5_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA7_SAI5_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA7_XSPI_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_PAD_XSPI1_DATA7_GPIO5_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET)
#define IOMUXC_PAD_XSPI1_DQS_FLEXSPI1_A_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_XSPI1_DQS_SAI5_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_XSPI1_DQS_SAI5_TX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_XSPI1_DQS_SAI2_RX_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_XSPI1_DQS_XSPI_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x4, IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_XSPI1_DQS_GPIO5_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET)
#define IOMUXC_PAD_XSPI1_SCLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_XSPI1_SCLK_SAI2_RX_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_XSPI1_SCLK_SAI4_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_XSPI1_SCLK_EARC_DC_HPD_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_XSPI1_SCLK_XSPI_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x4, IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_XSPI1_SCLK_GPIO5_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET)
#define IOMUXC_PAD_XSPI1_SS0_B_FLEXSPI1_A_SS0_B IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS0_B_SAI2_RX_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS0_B_SAI4_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS0_B_EARC_CEC_OUT IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS0_B_XSPI_CS IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x4, IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS0_B_GPIO5_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS1_B_FLEXSPI1_A_SS1_B IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS1_B_SAI5_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS1_B_SAI5_TX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS1_B_SAI2_RX_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_PAD_XSPI1_SS1_B_GPIO5_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET)
#define IOMUXC_PAD_SD2_CD_B_USDHC2_CD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_PAD_SD2_CD_B_NETC_TMR_1588_TRIG1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_PAD_SD2_CD_B_I3C2_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x2, IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_PAD_SD2_CD_B_FLEXIO1_FLEXIO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_PAD_SD2_CD_B_GPIO3_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET)
#define IOMUXC_PAD_SD2_CLK_USDHC2_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CLK_OFFSET)
#define IOMUXC_PAD_SD2_CLK_NETC_TMR_1588_PP1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CLK_OFFSET)
#define IOMUXC_PAD_SD2_CLK_I3C2_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x2, IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CLK_OFFSET)
#define IOMUXC_PAD_SD2_CLK_FLEXIO1_FLEXIO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CLK_OFFSET)
#define IOMUXC_PAD_SD2_CLK_GPIO3_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CLK_OFFSET)
#define IOMUXC_PAD_SD2_CMD_USDHC2_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_SD2_CMD_NETC_TMR_1588_TRIG2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_SD2_CMD_I3C2_PUR IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_SD2_CMD_I3C2_PUR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_SD2_CMD_FLEXIO1_FLEXIO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_SD2_CMD_GPIO3_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET)
#define IOMUXC_PAD_SD2_DATA0_USDHC2_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_PAD_SD2_DATA0_NETC_TMR_1588_PP2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_PAD_SD2_DATA0_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_PAD_SD2_DATA0_FLEXIO1_FLEXIO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_PAD_SD2_DATA0_GPIO3_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET)
#define IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_PAD_SD2_DATA1_NETC_TMR_1588_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_PAD_SD2_DATA1_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x2, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x3, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_PAD_SD2_DATA1_FLEXIO1_FLEXIO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_PAD_SD2_DATA1_GPIO3_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET)
#define IOMUXC_PAD_SD2_DATA2_USDHC2_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_PAD_SD2_DATA2_NETC_TMR_1588_PP3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_PAD_SD2_DATA2_MQS2_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_PAD_SD2_DATA2_FLEXIO1_FLEXIO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_PAD_SD2_DATA2_GPIO3_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET)
#define IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_SD2_DATA3_LPTMR2_ALT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x1, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_SD2_DATA3_MQS2_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_SD2_DATA3_NETC_TMR_1588_ALARM1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_SD2_DATA3_FLEXIO1_FLEXIO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_SD2_DATA3_GPIO3_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET)
#define IOMUXC_PAD_SD2_RESET_B_USDHC2_RESET_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_PAD_SD2_RESET_B_LPTMR2_ALT2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x1, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_PAD_SD2_RESET_B_NETC_TMR_1588_GCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_PAD_SD2_RESET_B_FLEXIO1_FLEXIO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_PAD_SD2_RESET_B_GPIO3_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET)
#define IOMUXC_PAD_I2C1_SCL_LPI2C1_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_I2C1_SCL_I3C1_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_I2C1_SCL_LPUART1_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_I2C1_SCL_TPM2_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_I2C1_SCL_UART_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_I2C1_SCL_GPIO1_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET)
#define IOMUXC_PAD_I2C1_SDA_LPI2C1_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_I2C1_SDA_I3C1_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_I2C1_SDA_LPUART1_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_I2C1_SDA_TPM2_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_I2C1_SDA_UART_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_I2C1_SDA_GPIO1_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_LPI2C2_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_LPUART2_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_TPM2_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_SAI1_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_GPIO1_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET)
#define IOMUXC_PAD_I2C2_SDA_LPI2C2_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_PAD_I2C2_SDA_LPUART2_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_PAD_I2C2_SDA_TPM2_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_PAD_I2C2_SDA_SAI1_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_PAD_I2C2_SDA_GPIO1_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET)
#define IOMUXC_PAD_UART1_RXD_LPUART1_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET)
#define IOMUXC_PAD_UART1_RXD_ELE_UART_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET)
#define IOMUXC_PAD_UART1_RXD_LPSPI2_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET)
#define IOMUXC_PAD_UART1_RXD_TPM1_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET)
#define IOMUXC_PAD_UART1_RXD_GPIO1_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET)
#define IOMUXC_PAD_UART1_TXD_LPUART1_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET)
#define IOMUXC_PAD_UART1_TXD_ELE_UART_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET)
#define IOMUXC_PAD_UART1_TXD_LPSPI2_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET)
#define IOMUXC_PAD_UART1_TXD_TPM1_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET)
#define IOMUXC_PAD_UART1_TXD_GPIO1_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET)
#define IOMUXC_PAD_UART2_RXD_LPUART2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_UART2_RXD_LPUART1_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_UART2_RXD_LPSPI2_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_UART2_RXD_TPM1_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_UART2_RXD_SAI1_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x4, IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_UART2_RXD_GPIO1_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET)
#define IOMUXC_PAD_UART2_TXD_LPUART2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET)
#define IOMUXC_PAD_UART2_TXD_LPUART1_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET)
#define IOMUXC_PAD_UART2_TXD_LPSPI2_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET)
#define IOMUXC_PAD_UART2_TXD_TPM1_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET)
#define IOMUXC_PAD_UART2_TXD_GPIO1_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET)
#define IOMUXC_PAD_PDM_CLK_PDM_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET)
#define IOMUXC_PAD_PDM_CLK_MQS1_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET)
#define IOMUXC_PAD_PDM_CLK_LPTMR1_ALT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET)
#define IOMUXC_PAD_PDM_CLK_GPIO1_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET)
#define IOMUXC_PAD_PDM_CLK_CAN1_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_PDM_BIT_STREAM00 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x0, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_MQS1_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_LPSPI1_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_TPM1_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_LPTMR1_ALT2 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_GPIO1_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x6, IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM1_PDM_BIT_STREAM01 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x0, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM1_NMI_GLUE_NMI IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM1_LPSPI2_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM1_TPM2_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM1_LPTMR1_ALT3 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_PDM_BIT_STREAM1_GPIO1_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET)
#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_SAI1_TXFS_LPSPI1_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_SAI1_TXFS_LPUART2_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_SAI1_TXFS_MQS1_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET)
#define IOMUXC_PAD_SAI1_TXC_SAI1_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_SAI1_TXC_LPUART2_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_SAI1_TXC_LPUART1_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_SAI1_TXC_CAN1_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x4, IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_SAI1_TXC_GPIO1_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET)
#define IOMUXC_PAD_SAI1_TXD0_SAI1_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_SAI1_TXD0_LPUART2_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_SAI1_TXD0_LPUART1_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_SAI1_TXD0_CAN1_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_SAI1_TXD0_GPIO1_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET)
#define IOMUXC_PAD_SAI1_RXD0_SAI1_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_SAI1_RXD0_SAI1_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x1, IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_SAI1_RXD0_LPUART2_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_SAI1_RXD0_MQS1_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_SAI1_RXD0_GPIO1_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET)
#define IOMUXC_PAD_WDOG_ANY_WDOG_ANY IOMUX_PADCFG(IOMUXC_MUX_CTL_WDOG_ANY_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_WDOG_ANY_OFFSET)
#define IOMUXC_PAD_WDOG_ANY_FCCU_EOUT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_WDOG_ANY_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_WDOG_ANY_OFFSET)
#define IOMUXC_PAD_WDOG_ANY_GPIO1_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_WDOG_ANY_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_WDOG_ANY_OFFSET)

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_clock.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_memorymap.h"
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_clock.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H_ */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_dmamux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_dmamux.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_edma.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_edma.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_gpc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_OFFSET 0x0004 /* CMC Authentication Control */
#define IMX9_GPC_CTRL_CMC_MISC_OFFSET 0x000c /* Miscellaneous */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_OFFSET 0x0010 /* CPU mode control */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_OFFSET 0x0014 /* CPU mode Status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_OFFSET 0x0018 /* CMC pin Status */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1_OFFSET 0x0100 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2_OFFSET 0x0104 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3_OFFSET 0x0108 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4_OFFSET 0x010c /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5_OFFSET 0x0110 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6_OFFSET 0x0114 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7_OFFSET 0x0118 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8_OFFSET 0x011c /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9_OFFSET 0x0120 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10_OFFSET 0x0124 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11_OFFSET 0x0128 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12_OFFSET 0x012c /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_OFFSET 0x0140 /* CMC non-IRQ wakeup mask */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1_OFFSET 0x0150 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2_OFFSET 0x0154 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3_OFFSET 0x0158 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4_OFFSET 0x015c /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5_OFFSET 0x0160 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6_OFFSET 0x0164 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7_OFFSET 0x0168 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8_OFFSET 0x016c /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9_OFFSET 0x0170 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10_OFFSET 0x0174 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11_OFFSET 0x0178 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12_OFFSET 0x017c /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_OFFSET 0x0190 /* CMC non-IRQ wakeup status */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_OFFSET 0x0200 /* CMC sleep A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_OFFSET 0x0204 /* CMC sleep A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_OFFSET 0x0208 /* CMC sleep SSAR control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_OFFSET 0x020c /* CMC sleep SSAR status */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_OFFSET 0x0230 /* CMC sleep reset control */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_OFFSET 0x0234 /* CMC sleep reset status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_OFFSET 0x0248 /* CMC sleep Sysman control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_OFFSET 0x024c /* CMC Sleep Sysman status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_OFFSET 0x0290 /* CMC wakeup power control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_OFFSET 0x0294 /* CMC wakeup power status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_OFFSET 0x02c8 /* CMC wakeup SSAR control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_OFFSET 0x02cc /* CMC wakeup SSAR status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_OFFSET 0x02d0 /* CMC wakeup A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_OFFSET 0x02d4 /* CMC wakeup A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_OFFSET 0x02d8 /* CMC wakeup Sysman control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_OFFSET 0x02dc /* CMC wakeup Sysman status */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_OFFSET 0x0380 /* CMC system sleep control */
#define IMX9_GPC_CTRL_CMC_DEBUG_OFFSET 0x0390 /* CMC debug */
/* Register macros */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_OFFSET) /* CMC Authentication Control */
#define IMX9_GPC_CTRL_CMC_MISC(n) ((n) + IMX9_GPC_CTRL_CMC_MISC_OFFSET) /* Miscellaneous */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_MODE_CTRL_OFFSET) /* CPU mode control */
#define IMX9_GPC_CTRL_CMC_MODE_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_MODE_STAT_OFFSET) /* CPU mode Status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_PIN_STAT_OFFSET) /* CMC pin Status */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK(n) ((n) + IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_OFFSET) /* CMC non-IRQ wakeup mask */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_OFFSET) /* CMC non-IRQ wakeup status */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_OFFSET) /* CMC sleep A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_OFFSET) /* CMC sleep A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_OFFSET) /* CMC sleep SSAR control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_OFFSET) /* CMC sleep SSAR status */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_OFFSET) /* CMC sleep reset control */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_OFFSET) /* CMC sleep reset status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_OFFSET) /* CMC sleep Sysman control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_OFFSET) /* CMC Sleep Sysman status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_OFFSET) /* CMC wakeup power control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_OFFSET) /* CMC wakeup power status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_OFFSET) /* CMC wakeup SSAR control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_OFFSET) /* CMC wakeup SSAR status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_OFFSET) /* CMC wakeup A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_OFFSET) /* CMC wakeup A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_OFFSET) /* CMC wakeup Sysman control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_OFFSET) /* CMC wakeup Sysman status */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_OFFSET) /* CMC system sleep control */
#define IMX9_GPC_CTRL_CMC_DEBUG(n) ((n) + IMX9_GPC_CTRL_CMC_DEBUG_OFFSET) /* CMC debug */
/* Field definitions */
/* CMC_AUTHEN_CTRL register */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT 7 /* Configuration lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT) /* Configuration lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_SHIFT 8 /* Allow user mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_SHIFT) /* Allow user mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_SHIFT 9 /* Allow non-secure mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_SHIFT) /* Allow non-secure mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT 11 /* Lock NONSECURE and USER */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT) /* Lock NONSECURE and USER */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT 15 /* White list lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT) /* White list lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_WHITE_LIST_SHIFT 16 /* Domain ID white list */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_WHITE_LIST_MASK 0xffff /* Domain ID white list */
/* CMC_MISC register */
#define IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_SHIFT 0 /* Non-masked interrupt status */
#define IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_SHIFT) /* Non-masked interrupt status */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_SHIFT 1 /* Allow cpu_sleep_hold_req assert during CPU low power status */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_SHIFT) /* Allow cpu_sleep_hold_req assert during CPU low power status */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_SHIFT 2 /* Status of cpu_sleep_hold_ack_b */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_SHIFT) /* Status of cpu_sleep_hold_ack_b */
#define IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_SHIFT 4 /* GIC wakeup request status */
#define IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_SHIFT) /* GIC wakeup request status */
#define IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_SHIFT 5 /* IRQ select */
#define IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_SHIFT) /* IRQ select */
#define IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_SHIFT 6 /* Software wakeup. Used for CPU hotplug. */
#define IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_SHIFT) /* Software wakeup. Used for CPU hotplug. */
/* CMC_MODE_CTRL register */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT 0 /* The CPU mode the CPU platform should transit to on next sleep event */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK 0x3 /* The CPU mode the CPU platform should transit to on next sleep event */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_STAY_IN_RUN_MODE 0
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_WAIT 1
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_STOP 2
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_SUSPEND 3
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET(n) (n << IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT)
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_SHIFT 4 /* WFE assertion can be sleep event */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_SHIFT) /* WFE assertion can be sleep event */
/* CMC_MODE_STAT register */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_CURRENT_SHIFT 0 /* Current CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_CURRENT_MASK 0x3 /* Current CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT 2 /* Previous CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_PREVIOUS_MASK 0x3 /* Previous CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT 8 /* Busy on CPU mode transition of sleep, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT) /* Busy on CPU mode transition of sleep, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT 9 /* Busy on CPU mode transition of wakeup, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT) /* Busy on CPU mode transition of wakeup, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT 10 /* Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT) /* Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT 16 /* Status of sleep_request input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT) /* Status of sleep_request input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_SHIFT 17 /* Status of standby_wfe input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_SHIFT) /* Status of standby_wfe input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT 18 /* "ORed" of all unmasked IRQ */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT) /* "ORed" of all unmasked IRQ */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_FSM_STATE_SHIFT 24 /* CPU mode trans FSM state. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_FSM_STATE_MASK 0x1f /* CPU mode trans FSM state. */
/* CMC_PIN_STAT register */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT 0 /* cpu_mode_trans_a55_hdsk_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT) /* cpu_mode_trans_a55_hdsk_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT 1 /* cpu_mode_trans_ssar_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT) /* cpu_mode_trans_ssar_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT 6 /* cpu_mode_trans_reset_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT) /* cpu_mode_trans_reset_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT 7 /* cpu_mode_trans_power_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT) /* cpu_mode_trans_power_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT 9 /* cpu_mode_trans_sysman_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT) /* cpu_mode_trans_sysman_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT 16 /* cpu_mode_trans_a55_hdsk_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT) /* cpu_mode_trans_a55_hdsk_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT 17 /* cpu_mode_trans_ssar_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT) /* cpu_mode_trans_ssar_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT 22 /* cpu_mode_trans_reset_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT) /* cpu_mode_trans_reset_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT 23 /* cpu_mode_trans_power_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT) /* cpu_mode_trans_power_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT 25 /* cpu_mode_trans_sysman_done pin status. */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT) /* cpu_mode_trans_sysman_done pin status. */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_CPU_MODE_STAT_SHIFT 29 /* cpu_power_mode pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_CPU_MODE_STAT_MASK 0x3 /* cpu_power_mode pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT 31 /* Debug wakeup acknowledge pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT) /* Debug wakeup acknowledge pin status */
/* CMC_NON_IRQ_WAKEUP_MASK register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT 0 /* "1" means the event cannot wakeup CPU platform */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT) /* "1" means the event cannot wakeup CPU platform */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT 1 /* "1" means the debug_wakeup_request cannot wakeup CPU platform */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT) /* "1" means the debug_wakeup_request cannot wakeup CPU platform */
/* CMC_NON_IRQ_WAKEUP_STAT register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT 0 /* Event wakeup status */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT) /* Event wakeup status */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT 1 /* Debug wakeup status */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT) /* Debug wakeup status */
/* CMC_SLEEP_A55_HDSK_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_A55_HDSK_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SLEEP_SSAR_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_SSAR_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SLEEP_RESET_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_RESET_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SLEEP_SYSMAN_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_SYSMAN_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_POWER_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_POWER_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_SSAR_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_SSAR_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_A55_HDSK_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_A55_HDSK_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_SYSMAN_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_SYSMAN_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SYS_SLEEP_CTRL register */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT 0 /* Request system sleep when CPU is in WAIT mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT) /* Request system sleep when CPU is in WAIT mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT 1 /* Request system sleep when CPU is in STOP mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT) /* Request system sleep when CPU is in STOP mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT 2 /* Request system sleep when CPU is in SUSPEND mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT) /* Request system sleep when CPU is in SUSPEND mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT 16 /* Indicates the CPU is busy entering system sleep mode. */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT) /* Indicates the CPU is busy entering system sleep mode. */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT 17 /* Indicates the CPU is busy exiting system sleep mode. */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT) /* Indicates the CPU is busy exiting system sleep mode. */
/* CMC_DEBUG register */
#define IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_SHIFT 0 /* Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */
#define IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_FLAG (1 << IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_SHIFT) /* Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */
/* Register array dimensions */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK__REGARRAY_SIZE 12
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT__REGARRAY_SIZE 12
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_gpio.h"
#else
# error Unrecognized i.MX9 architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define GPIO1 0 /* Port 1 index */
#define GPIO2 1 /* Port 2 index */
#define GPIO3 2 /* Port 3 index */
#define GPIO4 3 /* Port 4 index */
#define GPIO5 4 /* Port 5 index */
#define GPIO6 5 /* Port 6 index */
#define GPIO7 6 /* Port 7 index */
#define GPIO8 7 /* Port 8 index */
#define GPIO9 8 /* Port 9 index */
#define GPIO10 9 /* Port 10 index */
#define GPIO11 10 /* Port 11 index */
#define GPIO12 11 /* Port 12 index */
#define GPIO13 12 /* Port 13 index */
#define IMX9_GPIO_NPINS 32 /* Up to 32 pins per port */
/* Register bit definitions *************************************************/
/* Most registers are laid out simply with one bit per pin */
#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */
/* ICRN Register */
#define IMX9_GPIO_ICRN_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */
#define IMX9_GPIO_ICRN_LK (1 << 23) /* Bit 23: Lock Register */
#define IMX9_GPIO_ICRN_IRQS (1 << 20) /* Bit 20: Configures the selected interrupt, or DMA request. */
#define IMX9_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */
#define IMX9_GPIO_ICRN_MASK (0xf << IMX9_GPIO_ICRN_SHIFT)
# define IMX9_GPIO_ICRN_DISABLED (0 << IMX9_GPIO_ICRN_SHIFT) /* Interrupt Status Flag (ISF) is disabled */
# define IMX9_GPIO_ICRN_DMARISING (1 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on rising edge */
# define IMX9_GPIO_ICRN_DMAFALLING (2 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on falling edge */
# define IMX9_GPIO_ICRN_DMABOTH (3 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on either edge */
# define IMX9_GPIO_ICRN_ISFRISING (5 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on rising edge */
# define IMX9_GPIO_ICRN_ISFFALLING (6 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on falling edge */
# define IMX9_GPIO_ICRN_ISFBOTH (7 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on either edge */
# define IMX9_GPIO_ICRN_ZERO (8 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 0 */
# define IMX9_GPIO_ICRN_RISING (9 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on rising-edge */
# define IMX9_GPIO_ICRN_FALLING (10 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on falling-edge */
# define IMX9_GPIO_ICRN_BOTH (11 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on either edge */
# define IMX9_GPIO_ICRN_ONE (12 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 1 */
/* Global Interrupt Control Low Register */
#define IMX9_GPIO_GICLR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */
#define IMX9_GPIO_GICLR_GIWD_MASK (0xffff << IMX9_GPIO_GICLR_GIWD_SHIFT)
# define IMX9_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWD_SHIFT) /* Pin n=0..15 */
#define IMX9_GPIO_GICLR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */
#define IMX9_GPIO_GICLR_GIWE_MASK (0xffff << IMX9_GPIO_GICLR_GIWE_SHIFT)
# define IMX9_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWE_SHIFT) /* Pin n=0..15 */
/* Global Interrupt Control High Register */
#define IMX9_GPIO_GICHR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */
#define IMX9_GPIO_GICHR_GIWD_MASK (0xffff << IMX9_GPIO_GICHR_GIWD_SHIFT)
# define IMX9_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWD_SHIFT) /* Pin n=16..31 */
#define IMX9_GPIO_GICHR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */
#define IMX9_GPIO_GICHR_GIWE_MASK (0xffff << IMX9_GPIO_GICHR_GIWE_SHIFT)
# define IMX9_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWE_SHIFT) /* Pin n=16..31 */
/* Interrupt Status Flag Register */
#define IMX9_GPIO_ISFR(n) (1 << (n)) /* Interrupt Status Flag, n=0-31 */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_iomuxc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_iomuxc.h"
#else
# error Unrecognized i.MX9 architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Pad muxing */
#define IOMUXC_MUX_MODE_SHIFT (0) /* MODE: pin alternate function */
#define IOMUXC_MUX_MODE_MASK (0x03 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT0 (0 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT1 (1 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT2 (2 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT3 (3 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT4 (4 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT5 (5 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT6 (6 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_SION_SHIFT (4) /* SION: Force input path */
#define IPMUXC_MUX_SION_MASK (0x01 << IOMUXC_MUX_SION_SHIFT)
#define IOMUXC_MUX_SION_OFF (0 << IOMUXC_MUX_SION_SHIFT)
#define IOMUXC_MUX_SION_ON (1 << IOMUXC_MUX_SION_SHIFT)
/* Pad control */
#define IOMUXC_PAD_DSE_SHIFT (1) /* DSE: Drive strength */
#define IOMUXC_PAD_DSE_MASK (0x3f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X0 (0x00 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X1 (0x01 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X2 (0x03 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X3 (0x07 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X4 (0x0f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X5 (0x1f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X6 (0x3f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_FSEL_SHIFT (7) /* FSEL: Slew rate control */
#define IOMUXC_PAD_FSEL_MASK (0x02 << IOMUXC_PAD_FSEL_SHIFT)
#define IOMUXC_PAD_FSEL_SLOW (0 << IOMUXC_PAD_FSEL_SHIFT)
#define IOMUXC_PAD_FSEL_SSLOW (1 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly slow */
#define IOMUXC_PAD_FSEL_SFAST (2 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly fast */
#define IOMUXC_PAD_FSEL_FAST (3 << IOMUXC_PAD_FSEL_SHIFT)
#define IOMUXC_PAD_PU_SHIFT (9) /* PU: Pull-up */
#define IOMUXC_PAD_PU_MASK (0x01 << IOMUXC_PAD_PU_SHIFT)
#define IOMUXC_PAD_PU_OFF (0 << IOMUXC_PAD_PU_SHIFT)
#define IOMUXC_PAD_PU_ON (1 << IOMUXC_PAD_PU_SHIFT)
#define IOMUXC_PAD_PD_SHIFT (10) /* PD: Pull-down */
#define IOMUXC_PAD_PD_MASK (0x01 << IOMUXC_PAD_PD_SHIFT)
#define IOMUXC_PAD_PD_OFF (0 << IOMUXC_PAD_PD_SHIFT)
#define IOMUXC_PAD_PD_ON (1 << IOMUXC_PAD_PD_SHIFT)
#define IOMUXC_PAD_OD_SHIFT (11) /* OD: Open-drain */
#define IOMUXC_PAD_OD_MASK (0x01 << IOMUXC_PAD_OD_SHIFT)
#define IOMUXC_PAD_OD_DISABE (0 << IOMUXC_PAD_OD_SHIFT)
#define IOMUXC_PAD_OD_ENABLE (1 << IOMUXC_PAD_OD_SHIFT)
#define IOMUXC_PAD_HYS_SHIFT (12) /* HYS: Enable schmitt-trigger on input */
#define IOMUXC_PAD_HYS_MASK (0x01 << IOMUXC_PAD_HYS_SHIFT)
#define IOMUXC_PAD_HYS_ST_OFF (0 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger off */
#define IOMUXC_PAD_HYS_ST_ON (1 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger on */
#define IOMUXC_PAD_APC_SHIFT (24) /* APC: Access control */
#define IOMUXC_PAD_APC_MASK (0xff << IOMUXC_PAD_APC_SHIFT)
/* Daisy chain control, 2 bits seems to be enough */
#define IOMUXC_DSY_SHIFT (0)
#define IOMUXC_DSY_MASK (0x03 << IOMUXC_DSY_SHIFT)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpi2c.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define IMX9_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */
#define IMX9_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */
#define IMX9_LPI2C_MCR_OFFSET 0x0010 /* Master Control Register offset */
#define IMX9_LPI2C_MSR_OFFSET 0x0014 /* Master Status Register offset */
#define IMX9_LPI2C_MIER_OFFSET 0x0018 /* Master Interrupt Enable Register offset */
#define IMX9_LPI2C_MDER_OFFSET 0x001c /* Master DMA Enable Register offset */
#define IMX9_LPI2C_MCFGR0_OFFSET 0x0020 /* Master Config Register 0 offset */
#define IMX9_LPI2C_MCFGR1_OFFSET 0x0024 /* Master Config Register 1 offset */
#define IMX9_LPI2C_MCFGR2_OFFSET 0x0028 /* Master Config Register 2 offset */
#define IMX9_LPI2C_MCFGR3_OFFSET 0x002c /* Master Config Register 3 offset */
#define IMX9_LPI2C_MDMR_OFFSET 0x0040 /* Master Data Match Register offset */
#define IMX9_LPI2C_MCCR0_OFFSET 0x0048 /* Master Clock Configuration Register 0 offset */
#define IMX9_LPI2C_MCCR1_OFFSET 0x0050 /* Master Clock Configuration Register 1 offset */
#define IMX9_LPI2C_MFCR_OFFSET 0x0058 /* Master FIFO Control Register offset */
#define IMX9_LPI2C_MFSR_OFFSET 0x005C /* Master FIFO Status Register offset */
#define IMX9_LPI2C_MTDR_OFFSET 0x0060 /* Master Transmit Data Register offset */
#define IMX9_LPI2C_MRDR_OFFSET 0x0070 /* Master Receive Data Register offset */
#define IMX9_LPI2C_SCR_OFFSET 0x0110 /* Slave Control Register offset */
#define IMX9_LPI2C_SSR_OFFSET 0x0114 /* Slave Status Register offset */
#define IMX9_LPI2C_SIER_OFFSET 0x0118 /* Slave Interrupt Enable Register offset */
#define IMX9_LPI2C_SDER_OFFSET 0x011c /* Slave DMA Enable Register offset */
#define IMX9_LPI2C_SCFGR1_OFFSET 0x0124 /* Slave Config Register 1 offset */
#define IMX9_LPI2C_SCFGR2_OFFSET 0x0128 /* Slave Config Register 2 offset */
#define IMX9_LPI2C_SAMR_OFFSET 0x0140 /* Slave Address Match Register offset */
#define IMX9_LPI2C_SASR_OFFSET 0x0150 /* Slave Address Status Register offset */
#define IMX9_LPI2C_STAR_OFFSET 0x0154 /* Slave Transmit ACK Register offset */
#define IMX9_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */
#define IMX9_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */
/* Register addresses *******************************************************/
/* LPI2C1 Registers */
#define IMX9_LPI2C1_VERID (IMX9_LPI2C1_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */
#define IMX9_LPI2C1_PARAM (IMX9_LPI2C1_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */
#define IMX9_LPI2C1_MCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */
#define IMX9_LPI2C1_MSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */
#define IMX9_LPI2C1_MIER (IMX9_LPI2C1_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */
#define IMX9_LPI2C1_MDER (IMX9_LPI2C1_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */
#define IMX9_LPI2C1_MCFGR0 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */
#define IMX9_LPI2C1_MCFGR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */
#define IMX9_LPI2C1_MCFGR2 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */
#define IMX9_LPI2C1_MCFGR3 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */
#define IMX9_LPI2C1_MDMR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */
#define IMX9_LPI2C1_MCCR0 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */
#define IMX9_LPI2C1_MCCR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */
#define IMX9_LPI2C1_MFCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */
#define IMX9_LPI2C1_MFSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */
#define IMX9_LPI2C1_MTDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */
#define IMX9_LPI2C1_MRDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */
#define IMX9_LPI2C1_SCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */
#define IMX9_LPI2C1_SSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */
#define IMX9_LPI2C1_SIER (IMX9_LPI2C1_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */
#define IMX9_LPI2C1_SDER (IMX9_LPI2C1_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */
#define IMX9_LPI2C1_SCFGR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */
#define IMX9_LPI2C1_SCFGR2 (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */
#define IMX9_LPI2C1_SAMR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */
#define IMX9_LPI2C1_SASR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */
#define IMX9_LPI2C1_STAR (IMX9_LPI2C1_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */
#define IMX9_LPI2C1_STDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */
#define IMX9_LPI2C1_SRDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */
/* LPI2C2 Registers */
#define IMX9_LPI2C2_VERID (IMX9_LPI2C2_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */
#define IMX9_LPI2C2_PARAM (IMX9_LPI2C2_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */
#define IMX9_LPI2C2_MCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */
#define IMX9_LPI2C2_MSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */
#define IMX9_LPI2C2_MIER (IMX9_LPI2C2_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */
#define IMX9_LPI2C2_MDER (IMX9_LPI2C2_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */
#define IMX9_LPI2C2_MCFGR0 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */
#define IMX9_LPI2C2_MCFGR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */
#define IMX9_LPI2C2_MCFGR2 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */
#define IMX9_LPI2C2_MCFGR3 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */
#define IMX9_LPI2C2_MDMR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */
#define IMX9_LPI2C2_MCCR0 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */
#define IMX9_LPI2C2_MCCR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */
#define IMX9_LPI2C2_MFCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */
#define IMX9_LPI2C2_MFSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */
#define IMX9_LPI2C2_MTDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */
#define IMX9_LPI2C2_MRDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */
#define IMX9_LPI2C2_SCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */
#define IMX9_LPI2C2_SSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */
#define IMX9_LPI2C2_SIER (IMX9_LPI2C2_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */
#define IMX9_LPI2C2_SDER (IMX9_LPI2C2_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */
#define IMX9_LPI2C2_SCFGR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */
#define IMX9_LPI2C2_SCFGR2 (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */
#define IMX9_LPI2C2_SAMR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */
#define IMX9_LPI2C2_SASR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */
#define IMX9_LPI2C2_STAR (IMX9_LPI2C2_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */
#define IMX9_LPI2C2_STDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */
#define IMX9_LPI2C2_SRDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */
/* LPI2C3 Registers */
#define IMX9_LPI2C3_VERID (IMX9_LPI2C3_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */
#define IMX9_LPI2C3_PARAM (IMX9_LPI2C3_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */
#define IMX9_LPI2C3_MCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */
#define IMX9_LPI2C3_MSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */
#define IMX9_LPI2C3_MIER (IMX9_LPI2C3_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */
#define IMX9_LPI2C3_MDER (IMX9_LPI2C3_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */
#define IMX9_LPI2C3_MCFGR0 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */
#define IMX9_LPI2C3_MCFGR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */
#define IMX9_LPI2C3_MCFGR2 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */
#define IMX9_LPI2C3_MCFGR3 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */
#define IMX9_LPI2C3_MDMR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */
#define IMX9_LPI2C3_MCCR0 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */
#define IMX9_LPI2C3_MCCR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */
#define IMX9_LPI2C3_MFCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */
#define IMX9_LPI2C3_MFSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */
#define IMX9_LPI2C3_MTDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */
#define IMX9_LPI2C3_MRDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */
#define IMX9_LPI2C3_SCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */
#define IMX9_LPI2C3_SSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */
#define IMX9_LPI2C3_SIER (IMX9_LPI2C3_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */
#define IMX9_LPI2C3_SDER (IMX9_LPI2C3_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */
#define IMX9_LPI2C3_SCFGR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */
#define IMX9_LPI2C3_SCFGR2 (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */
#define IMX9_LPI2C3_SAMR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */
#define IMX9_LPI2C3_SASR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */
#define IMX9_LPI2C3_STAR (IMX9_LPI2C3_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */
#define IMX9_LPI2C3_STDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */
#define IMX9_LPI2C3_SRDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */
/* LPI2C4 Registers */
#define IMX9_LPI2C4_VERID (IMX9_LPI2C4_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */
#define IMX9_LPI2C4_PARAM (IMX9_LPI2C4_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */
#define IMX9_LPI2C4_MCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */
#define IMX9_LPI2C4_MSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */
#define IMX9_LPI2C4_MIER (IMX9_LPI2C4_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */
#define IMX9_LPI2C4_MDER (IMX9_LPI2C4_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */
#define IMX9_LPI2C4_MCFGR0 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */
#define IMX9_LPI2C4_MCFGR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */
#define IMX9_LPI2C4_MCFGR2 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */
#define IMX9_LPI2C4_MCFGR3 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */
#define IMX9_LPI2C4_MDMR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */
#define IMX9_LPI2C4_MCCR0 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */
#define IMX9_LPI2C4_MCCR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */
#define IMX9_LPI2C4_MFCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */
#define IMX9_LPI2C4_MFSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */
#define IMX9_LPI2C4_MTDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */
#define IMX9_LPI2C4_MRDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */
#define IMX9_LPI2C4_SCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */
#define IMX9_LPI2C4_SSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */
#define IMX9_LPI2C4_SIER (IMX9_LPI2C4_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */
#define IMX9_LPI2C4_SDER (IMX9_LPI2C4_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */
#define IMX9_LPI2C4_SCFGR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */
#define IMX9_LPI2C4_SCFGR2 (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */
#define IMX9_LPI2C4_SAMR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */
#define IMX9_LPI2C4_SASR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */
#define IMX9_LPI2C4_STAR (IMX9_LPI2C4_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */
#define IMX9_LPI2C4_STDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */
#define IMX9_LPI2C4_SRDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */
/* Register bit definitions *************************************************/
/* LPI2C Version ID Register */
#define LPI2C_VERID_FEATURE_SHIFT (0)
#define LPI2C_VERID_FEATURE_MASK (0xffff << LPI2C_VERID_FEATURE_SHIFT)
#define LPI2C_VERID_MINOR_SHIFT (16)
#define LPI2C_VERID_MINOR_MASK (0xff << LPI2C_VERID_MINOR_SHIFT)
#define LPI2C_VERID_MAJOR_SHIFT (24)
#define LPI2C_VERID_MAJOR_MASK (0xff << LPI2C_VERID_MAJOR_SHIFT)
/* LPI2C Parameter Register */
#define LPI2C_PARAM_MTXFIFO_MASK (0x0f) /* Config number of words in master transmit fifo to 2^MTXFIFO (pow(2,MTXFIFO )) */
# define LPI2C_PARAM_MTXFIFO_1_WORDS (0)
# define LPI2C_PARAM_MTXFIFO_2_WORDS (1)
# define LPI2C_PARAM_MTXFIFO_4_WORDS (2)
# define LPI2C_PARAM_MTXFIFO_8_WORDS (3)
# define LPI2C_PARAM_MTXFIFO_16_WORDS (4)
# define LPI2C_PARAM_MTXFIFO_32_WORDS (5)
# define LPI2C_PARAM_MTXFIFO_64_WORDS (6)
# define LPI2C_PARAM_MTXFIFO_128_WORDS (7)
# define LPI2C_PARAM_MTXFIFO_256_WORDS (8)
# define LPI2C_PARAM_MTXFIFO_512_WORDS (9)
# define LPI2C_PARAM_MTXFIFO_1024_WORDS (10)
# define LPI2C_PARAM_MTXFIFO_2048_WORDS (11)
# define LPI2C_PARAM_MTXFIFO_4096_WORDS (12)
# define LPI2C_PARAM_MTXFIFO_8192_WORDS (13)
# define LPI2C_PARAM_MTXFIFO_16384_WORDS (14)
# define LPI2C_PARAM_MTXFIFO_32768_WORDS (15)
#define LPI2C_PARAM_MRXFIFO_SHIFT (8)
#define LPI2C_PARAM_MRXFIFO_MASK (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT) /* Config number of words in master receive fifo 2^MRXFIFO (pow(2,MTRFIFO )) */
# define LPI2C_PARAM_MRXFIFO_1_WORDS (0 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_2_WORDS (1 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_4_WORDS (2 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_8_WORDS (3 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_16_WORDS (4 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_32_WORDS (5 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_64_WORDS (6 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_128_WORDS (7 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_256_WORDS (8 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_512_WORDS (9 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_1024_WORDS (10 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_2048_WORDS (11 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_4096_WORDS (12 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_8192_WORDS (13 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_16384_WORDS (14 << LPI2C_PARAM_MRXFIFO_SHIFT)
# define LPI2C_PARAM_MRXFIFO_32768_WORDS (15 << LPI2C_PARAM_MRXFIFO_SHIFT)
/* LPI2C Master Control Register */
#define LPI2C_MCR_MEN (1 << 0) /* Master Enable Bit */
#define LPI2C_MCR_RST (1 << 1) /* Software Reset Bit */
#define LPI2C_MCR_DOZEN (1 << 2) /* Doze Mode Enable Bit */
#define LPI2C_MCR_DBGEN (1 << 3) /* Debug Enable Bit */
/* Bits 7-4 Reserved */
#define LPI2C_MCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */
#define LPI2C_MCR_RRF (1 << 9) /* Reset Receive FIFO Bit */
/* Bits 31-10 Reserved */
/* LPI2C Master Status Register */
#define LPI2C_MSR_TDF (1 << 0) /* Transmit Data Flag Bit */
#define LPI2C_MSR_RDF (1 << 1) /* Receive Data Flag Bit */
/* Bits 7-2 Reserved */
#define LPI2C_MSR_EPF (1 << 8) /* End Packet Flag Bit */
#define LPI2C_MSR_SDF (1 << 9) /* STOP Detect Flag Bit */
#define LPI2C_MSR_NDF (1 << 10) /* NACK Detect Flag Bit */
#define LPI2C_MSR_ALF (1 << 11) /* Arbitration Lost Flag Bit */
#define LPI2C_MSR_FEF (1 << 12) /* FIFO Error Flag Bit */
#define LPI2C_MSR_PLTF (1 << 13) /* Pin Low Timeout Flag Bit */
#define LPI2C_MSR_DMF (1 << 14) /* Data Match Flag Bit */
/* Bits 23-15 Reserved */
#define LPI2C_MSR_MBF (1 << 24) /* Master Busy Flag Bit */
#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */
/* Bits 31-26 Reserved */
#define LPI2C_MSR_ERROR_MASK (LPI2C_MSR_NDF | LPI2C_MSR_ALF | \
LPI2C_MSR_FEF)
/* LPI2C Master Interrupt Enable Register */
#define LPI2C_MIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */
#define LPI2C_MIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */
/* Bits 7-2 Reserved */
#define LPI2C_MIER_EPIE (1 << 8) /* End Packet Interrupt Enable Bit */
#define LPI2C_MIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */
#define LPI2C_MIER_NDIE (1 << 10) /* NACK Detect Interrupt Enable Bit */
#define LPI2C_MIER_ALIE (1 << 11) /* Arbitration Lost Interrupt Enable Bit */
#define LPI2C_MIER_FEIE (1 << 12) /* FIFO Error Interrupt Enable Bit */
#define LPI2C_MIER_PLTIE (1 << 13) /* Pin Low Timeout Interrupt Enable Bit */
#define LPI2C_MIER_DMIE (1 << 14) /* Data Match Interrupt Enable Bit */
/* Bits 31-15 Reserved */
/* LPI2C Master DMA Enable Register */
#define LPI2C_MDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */
#define LPI2C_MDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */
/* Bits 31-2 Reserved */
/* LPI2C Master Config Register 0 */
#define LPI2C_MCFG0_HREN (1 << 0) /* Host Request Enable Bit */
#define LPI2C_MCFG0_HRPOL (1 << 1) /* Host Request Polarity Bit */
#define LPI2C_MCFG0_HRSEL (1 << 2) /* Host Request Select Bit */
/* Bits 7-3 Reserved */
#define LPI2C_MCFG0_CIRFIFO (1 << 8) /* Circular FIFO Enable Bit */
#define LPI2C_MCFG0_RDMO (1 << 9) /* Receive Data Match Only Bit */
/* Bits 15-10 Reserved */
#define LPI2C_MCFG0_RELAX (1 << 16) /* Relaxed Mode */
#define LPI2C_MCFG0_ABORT (1 << 17) /* Abort Transfer */
/* Bits 31-18 Reserved */
/* LPI2C Master Config Register 1 */
#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */
#define LPI2C_MCFGR1_PRESCALE(n) ((n) & LPI2C_MCFGR1_PRESCALE_MASK)
# define LPI2C_MCFGR1_PRESCALE_1 (0)
# define LPI2C_MCFGR1_PRESCALE_2 (1)
# define LPI2C_MCFGR1_PRESCALE_4 (2)
# define LPI2C_MCFGR1_PRESCALE_8 (3)
# define LPI2C_MCFGR1_PRESCALE_16 (4)
# define LPI2C_MCFGR1_PRESCALE_32 (5)
# define LPI2C_MCFGR1_PRESCALE_64 (6)
# define LPI2C_MCFGR1_PRESCALE_128 (7)
#define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */
#define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */
#define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */
/* Bits 15-11 Reserved */
#define LPI2C_MCFGR1_MATCFG_SHIFT (16)
#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */
#define LPI2C_MCFGR1_MATCFG(n) (((n) << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT)
/* LPI2C_MCFG1_MATCFG = 001b Reserved */
# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT)
# define LPI2C_MCFGR1_MATCFG3 (3 << LPI2C_MCFGR1_MATCFG_SHIFT)
# define LPI2C_MCFGR1_MATCFG4 (4 << LPI2C_MCFGR1_MATCFG_SHIFT)
# define LPI2C_MCFGR1_MATCFG5 (5 << LPI2C_MCFGR1_MATCFG_SHIFT)
# define LPI2C_MCFGR1_MATCFG6 (6 << LPI2C_MCFGR1_MATCFG_SHIFT)
# define LPI2C_MCFGR1_MATCFG7 (7 << LPI2C_MCFGR1_MATCFG_SHIFT)
/* Bits 23-19 Reserved */
#define LPI2C_MCFGR1_PINCFG_SHIFT (24)
#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */
#define LPI2C_MCFGR1_PINCFG(n) (((n) << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG3 (3 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG4 (4 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG5 (5 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG6 (6 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG7 (7 << LPI2C_MCFGR1_PINCFG_SHIFT)
/* Bits 31-27 Reserved */
/* LPI2C Master Config Register 2 */
#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */
#define LPI2C_MCFG2_BUSIDLE_DISABLE (0)
#define LPI2C_MCFG2_BUSIDLE(n) ((n) & LPI2C_MCFG2_BUSIDLE_MASK)
/* Bits 15-12 Reserved */
#define LPI2C_MCFG2_FILTSCL_SHIFT (16)
#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT)
#define LPI2C_MCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK)
/* Bits 23-20 Reserved */
#define LPI2C_MCFG2_FILTSDA_SHIFT (24)
#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT)
#define LPI2C_MCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK)
/* Bits 31-28 Reserved */
/* LPI2C Master Config Register 3 */
/* Bits 7-0 Reserved */
#define LPI2C_MCFG3_PINLOW_SHIFT (8)
#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */
#define LPI2C_MCFG3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK)
/* Bits 31-20 Reserved */
/* LPI2C Master Data Match Register */
#define LPI2C_MDMR_MATCH0_SHIFT (0)
#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */
#define LPI2C_MDMR_MATCH0(n) (((n) << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
/* Bits 15-8 Reserved */
#define LPI2C_MDMR_MATCH1_SHIFT (16)
#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */
#define LPI2C_MDMR_MATCH1(n) (((n) << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
/* Bits 31-24 Reserved */
/* LPI2C Master Clock Configuration Register 0 */
#define LPI2C_MCCR0_CLKLO_SHIFT (0)
#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */
#define LPI2C_MCCR0_CLKLO(n) (((n) << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
/* Bits 7-6 Reserved */
#define LPI2C_MCCR0_CLKHI_SHIFT (8)
#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */
#define LPI2C_MCCR0_CLKHI(n) (((n) << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_MCCR0_SETHOLD_SHIFT (16)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR0_SETHOLD(n) (((n) << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
/* Bits 23-22 Reserved */
#define LPI2C_MCCR0_DATAVD_SHIFT (24)
#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR0_DATAVD(n) (((n) << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
/* Bits 31-30 Reserved */
/* LPI2C Master Clock Configuration Register 1 */
#define LPI2C_MCCR1_CLKLO_SHIFT (0)
#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */
#define LPI2C_MCCR1_CLKLO(n) (((n) << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
/* Bits 7-6 Reserved */
#define LPI2C_MCCR1_CLKHI_SHIFT (8)
#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */
#define LPI2C_MCCR1_CLKHI(n) (((n) << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_MCCR1_SETHOLD_SHIFT (16)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR1_SETHOLD(n) (((n) << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
/* Bits 23-22 Reserved */
#define LPI2C_MCCR1_DATAVD_SHIFT (24)
#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR1_DATAVD(n) (((n) << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
/* Bits 31-30 Reserved */
/* LPI2C Master FIFO Control Register */
#define LPI2C_MFCR_TXWATER_SHIFT (0)
#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/
#define LPI2C_MFCR_TXWATER(n) (((n) << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark */
/* Bits 15-2 Reserved */
#define LPI2C_MFCR_RXWATER_SHIFT (16)
#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */
#define LPI2C_MFCR_RXWATER(n) (((n) << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark */
/* Bits 31-18 Reserved */
/* LPI2C Master FIFO Status Register */
#define LPI2C_MFSR_TXCOUNT_SHIFT (0)
#define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */
/* Bits 15-2 Reserved */
#define LPI2C_MFSR_RXCOUNT_SHIFT (16)
#define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */
/* Bits 31-18 Reserved */
/* LPI2C Master Transmit Data Register */
#define LPI2C_MTDR_DATA_SHIFT (0)
#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */
#define LPI2C_MTDR_DATA(n) ((n) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_SHIFT (8)
#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */
#define LPI2C_MTDR_CMD(n) (((n) << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_RXD_DISC (3 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_START (4 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_START_NACK (5 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_START_HI (6 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_START_HI_NACK (7 << LPI2C_MTDR_CMD_SHIFT)
/* Bits 31-11 Reserved */
/* LPI2C Master Receive Data Register */
#define LPI2C_MRDR_DATA_SHIFT (0)
#define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */
/* Bits 13-8 Reserved */
#define LPI2C_MRDR_RXEMPTY_SHIFT (14)
#define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */
/* Bits 31-15 Reserved */
/* LPI2C Slave Control Register */
#define LPI2C_SCR_SEN (1 << 0) /* Slave Enable Bit */
#define LPI2C_SCR_RST (1 << 1) /* Software Reset Bit */
/* Bits 3-2 Reserved */
#define LPI2C_SCR_FILTEN (1 << 4) /* Filter Enable Bit */
#define LPI2C_SCR_FILTDZ (1 << 5) /* Filter Doze Enable Bit */
/* Bits 7-4 Reserved */
#define LPI2C_SCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */
#define LPI2C_SCR_RRF (1 << 9) /* Reset Receive FIFO Bit */
/* Bits 31-10 Reserved */
/* LPI2C Slave Status Register */
#define LPI2C_SSR_TDF (1 << 0) /* Transmit Data Flag Bit */
#define LPI2C_SSR_RDF (1 << 1) /* Receive Data Flag Bit */
#define LPI2C_SSR_AVF (1 << 2) /* Address Valid Flag Bit */
#define LPI2C_SSR_TAF (1 << 3) /* Transmit ACK Flag Bit */
/* Bits 7-4 Reserved */
#define LPI2C_SSR_RSF (1 << 8) /* Repeated Start Flag Bit */
#define LPI2C_SSR_SDF (1 << 9) /* STOP Detect Flag Bit */
#define LPI2C_SSR_BEF (1 << 10) /* Bit Error Flag Bit */
#define LPI2C_SSR_FEF (1 << 11) /* FIFO Error Flag Bit */
#define LPI2C_SSR_AM0F (1 << 12) /* Address Match 0 Flag Bit */
#define LPI2C_SSR_AM1F (1 << 13) /* Address Match 1 Flag Bit */
#define LPI2C_SSR_GCF (1 << 14) /* General Call Flag Bit */
#define LPI2C_SSR_SARF (1 << 15) /* SMBus Alert Response Flag Bit */
/* Bits 23-16 Reserved */
#define LPI2C_MSR_SBF (1 << 24) /* Slave Busy Flag Bit */
#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */
/* Bits 31-26 Reserved */
/* LPI2C Slave Interrupt Enable Register */
#define LPI2C_SIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */
#define LPI2C_SIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */
#define LPI2C_SIER_AVIE (1 << 2) /* Address Valid Interrupt Enable Bit */
#define LPI2C_SIER_TAIE (1 << 3) /* Transmit ACK Interrupt Enable Bit */
/* Bits 7-4 Reserved */
#define LPI2C_SIER_RSIE (1 << 8) /* Repeated Start Interrupt Enable Bit */
#define LPI2C_SIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */
#define LPI2C_SIER_BEIE (1 << 10) /* Bit Error Interrupt Enable Bit */
#define LPI2C_SIER_FEIE (1 << 11) /* FIFO Error Interrupt Enable Bit */
#define LPI2C_SIER_AM0IE (1 << 12) /* Address Match 0 Interrupt Enable Bit */
#define LPI2C_SIER_AM1IE (1 << 13) /* Address Match 1 Interrupt Enable Bit */
#define LPI2C_SIER_GCIE (1 << 14) /* General Call Interrupt Enable Bit */
#define LPI2C_SIER_SARIE (1 << 15) /* SMBus Alert Response Interrupt Enable Bit */
/* Bits 31-16 Reserved */
/* LPI2C Slave DMA Enable Register */
#define LPI2C_SDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */
#define LPI2C_SDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */
#define LPI2C_SDER_AVDE (1 << 2) /* Address Valid DMA Enable Bit */
/* Bits 31-3 Reserved */
/* LPI2C Slave Configuration Register 1 */
#define LPI2C_SCFGR1_ADRSTALL (1 << 0) /* Address SCL Stall */
#define LPI2C_SCFGR1_RXSTALL (1 << 1) /* RX SCL Stall */
#define LPI2C_SCFGR1_TXSTALL (1 << 2) /* TX Data SCL Stall */
#define LPI2C_SCFGR1_ACKSTALL (1 << 3) /* ACK SCL Stall */
/* Bits 7-4 Reserved */
#define LPI2C_SCFGR1_GCEN (1 << 8) /* General Call Enable */
#define LPI2C_SCFGR1_SAEN (1 << 9) /* SMBus Alert Enable */
#define LPI2C_SCFGR1_TXCFG (1 << 10) /* Transmit Flag Configuration */
#define LPI2C_SCFGR1_RXCFG (1 << 11) /* Receive Data Configuration */
#define LPI2C_SCFGR1_IFNACK (1 << 12) /* Ignore NACK */
#define LPI2C_SCFGR1_HSMEN (1 << 13) /* High Speed Mode Enable */
/* Bits 15-14 Reserved */
#define LPI2C_SCFG1_ADDRCFG_SHIFT (16)
#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */
#define LPI2C_SCFG1_ADDRCFG(n) (((n) << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG3 (3 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG4 (4 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG5 (5 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG6 (6 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG7 (7 << LPI2C_SCFG1_ADDRCFG_SHIFT)
/* Bits 31-19 Reserved */
/* LPI2C Slave Configuration Register 2 */
#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */
#define LPI2C_SCFG2_CLKHOLD(n) ((n) & LPI2C_SCFG2_CLKHOLD_MASK)
/* Bits 7-4 Reserved */
#define LPI2C_SCFG2_DATAVD_SHIFT (8)
#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */
#define LPI2C_SCFG2_DATAVD(n) (((n) << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_SCFG2_FILTSCL_SHIFT (16)
#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT)
#define LPI2C_SCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK)
/* Bits 23-20 Reserved */
#define LPI2C_SCFG2_FILTSDA_SHIFT (24)
#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT)
#define LPI2C_SCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK)
/* Bits 31-28 Reserved */
/* LPI2C Slave Address Match Register */
/* Bit 0 Reserved */
#define LPI2C_SAMR_ADDR0_SHIFT (1)
#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */
#define LPI2C_SAMR_ADDR0(n) (((n) << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
/* Bits 16-11 Reserved */
#define LPI2C_SAMR_ADDR1_SHIFT (17)
#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */
#define LPI2C_SAMR_ADDR1(n) (((n) << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
/* Bits 31-27 Reserved */
/* LPI2C Slave Address Status Register */
#define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */
/* Bits 16-11
* Reserved
*/
#define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */
/* Bits 31-15 Reserved */
/* LPI2C Slave Transmit ACK Register */
#define LPI2C_STAR_TXNACK (1 << 0) /* Transmit NACK */
/* Bits 31-1 Reserved */
/* LPI2C Slave Transmit Data Register */
#define LPI2C_STDR_DATA_SHIFT (0)
#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */
#define LPI2C_STDR_DATA(n) (((n) << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
/* Bits 31-8 Reserved */
/* LPI2C Slave Receive Data Register */
#define LPI2C_SRDR_DATA_SHIFT (0)
#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */
#define LPI2C_SRDR_DATA(n) (((n) << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
/* Bits 13-8 Reserved */
#define LPI2C_STAR_SOF (1 << 14) /* RX Empty */
#define LPI2C_STAR_RXEMPTY (1 << 15) /* Start Of Frame */
/* Bits 31-16 Reserved */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ */

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arch/arm/src/imx9/hardware/imx9_lpit.h Normal file
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpit.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_LPIT_VERID_OFFSET 0x0000 /* Version ID */
#define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */
#define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */
#define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */
#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */
#define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */
#define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */
#define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */
#define IMX9_LPIT_CVAL0_OFFSET 0x0024 /* Current Timer Channel 0 Value */
#define IMX9_LPIT_TCTRL0_OFFSET 0x0028 /* Timer Channel 0 Control */
#define IMX9_LPIT_TVAL1_OFFSET 0x0030 /* Timer Channel 1 Value */
#define IMX9_LPIT_CVAL1_OFFSET 0x0034 /* Current Timer Channel 1 Value */
#define IMX9_LPIT_TCTRL1_OFFSET 0x0048 /* Timer Channel 1 Control */
#define IMX9_LPIT_TVAL2_OFFSET 0x0040 /* Timer Channel 2 Value */
#define IMX9_LPIT_CVAL2_OFFSET 0x0044 /* Current Timer Channel 2 Value */
#define IMX9_LPIT_TCTRL2_OFFSET 0x0048 /* Timer Channel 2 Control */
#define IMX9_LPIT_TVAL3_OFFSET 0x0050 /* Timer Channel 3 Value */
#define IMX9_LPIT_CVAL3_OFFSET 0x0054 /* Current Timer Channel 3 Value */
#define IMX9_LPIT_TCTRL3_OFFSET 0x0058 /* Timer Channel 3 Control */
/* Register access */
#define LPIT_VERID(n) ((n) + IMX9_LPIT_VERID_OFFSET)
#define LPIT_PARAM(n) ((n) + IMX9_LPIT_PARAM_OFFSET)
#define LPIT_MCR(n) ((n) + IMX9_LPIT_MCR_OFFSET)
#define LPIT_MSR(n) ((n) + IMX9_LPIT_MSR_OFFSET)
#define LPIT_MIER(n) ((n) + IMX9_LPIT_MIER_OFFSET)
#define LPIT_SETTEN(n) ((n) + IMX9_LPIT_SETTEN_OFFSET)
#define LPIT_CLRTEN(n) ((n) + IMX9_LPIT_CLRTEN_OFFSET)
#define LPIT_TVAL0(n) ((n) + IMX9_LPIT_TVAL0_OFFSET)
#define LPIT_CVAL0(n) ((n) + IMX9_LPIT_CVAL0_OFFSET)
#define LPIT_TCTRL0(n) ((n) + IMX9_LPIT_TCTRL0_OFFSET)
#define LPIT_TVAL1(n) ((n) + IMX9_LPIT_TVAL1_OFFSET)
#define LPIT_CVAL1(n) ((n) + IMX9_LPIT_CVAL1_OFFSET)
#define LPIT_TCTRL1(n) ((n) + IMX9_LPIT_TCTRL1_OFFSET)
#define LPIT_TVAL2(n) ((n) + IMX9_LPIT_TVAL2_OFFSET)
#define LPIT_CVAL2(n) ((n) + IMX9_LPIT_CVAL2_OFFSET)
#define LPIT_TCTRL2(n) ((n) + IMX9_LPIT_TCTRL2_OFFSET)
#define LPIT_TVAL3(n) ((n) + IMX9_LPIT_TVAL3_OFFSET)
#define LPIT_CVAL3(n) ((n) + IMX9_LPIT_CVAL3_OFFSET)
#define LPIT_TCTRL3(n) ((n) + IMX9_LPIT_TCTRL3_OFFSET)
/* Register Bitfield Definitions ********************************************/
#define LPIT_PARAM_EXT_TRIG_SHIFT (8) /* Bit[15:8]: Number of External Trigger Inputs */
#define LPIT_PARAM_EXT_TRIG_MASK (0xff << LPIT_PARAM_EXT_TRIG_SHIFT)
#define LPIT_PARAM_CHANNEL_SHIFT (0) /* Bit[7:0]: Number of Timer Channels */
#define LPIT_PARAM_CHANNEL_MASK (0xff << LPIT_PARAM_CHANNEL_SHIFT)
#define LPIT_MCR_DBG_EN (1 << 3) /* Stop Timer when in Debug Mode */
#define LPIT_MCR_DOZE_EN (1 << 2) /* DOZE Mode Enable */
#define LPIT_MCR_SW_RST (1 << 1) /* Software Reset Bit */
#define LPIT_MCR_M_CEN (1 << 0) /* Module Clock Enable */
#define LPIT_MSR_TIF3 (1 << 3) /* Channel 3 Timer Interrupt Flag */
#define LPIT_MSR_TIF2 (1 << 2) /* Channel 2 Timer Interrupt Flag */
#define LPIT_MSR_TIF1 (1 << 1) /* Channel 1 Timer Interrupt Flag */
#define LPIT_MSR_TIF0 (1 << 0) /* Channel 0 Timer Interrupt Flag */
#define LPIT_MIER_TIE3 (1 << 3) /* Channel 3 Timer Interrupt Enable */
#define LPIT_MIER_TIE2 (1 << 2) /* Channel 2 Timer Interrupt Enable */
#define LPIT_MIER_TIE1 (1 << 1) /* Channel 1 Timer Interrupt Enable */
#define LPIT_MIER_TIE0 (1 << 0) /* Channel 0 Timer Interrupt Enable */
#define LPIT_TCTRL_TRG_SEL_SHIFT (27) /* Bit[27:24]: Trigger Select */
#define LPIT_TCTRL_TRG_SEL_MASK (0xf << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN0 (0 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN1 (1 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN2 (2 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN3 (3 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SRC_SHIFT (23) /* Bit23: Trigger Source */
#define LPIT_TCTRL_TRG_SRC_MASK (1 << LPIT_TCTRL_TRG_SRC_SHIFT)
#define LPIT_TCTRL_TRG_SRC_EXTER (0 << LPIT_TCTRL_TRG_SRC_SHIFT) /* external */
#define LPIT_TCTRL_TRG_SRC_INTER (1 << LPIT_TCTRL_TRG_SRC_SHIFT) /* internal */
#define LPIT_TCTRL_TROT (1 << 18) /* Timer Reload On Trigger */
#define LPIT_TCTRL_TSOI (1 << 17) /* Timer Stop On Interrupt */
#define LPIT_TCTRL_TSOT (1 << 16) /* Timer Start On Trigger */
#define LPIT_TCTRL_MODE_SHIFT (2)
#define LPIT_TCTRL_MODE_MASK (3 << LPIT_TCTRL_MODE_SHIFT)
#define LPIT_TCTRL_MODE_32PC (0 << LPIT_TCTRL_MODE_SHIFT) /* 32 Bit periodic Counter */
#define LPIT_TCTRL_MODE_D16PC (1 << LPIT_TCTRL_MODE_SHIFT) /* Dual 16-bit periodic Counter */
#define LPIT_TCTRL_MODE_32TA (2 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Accumulator */
#define LPIT_TCTRL_MODE_32TIC (3 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Input Capture */
#define LPIT_TCTRL_CHAIN (1 << 1) /* Chain Channel */
#define LPIT_TCTRL_T_EN (1 << 0) /* Timer Enable */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpspi.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define IMX9_LPSPI_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */
#define IMX9_LPSPI_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */
#define IMX9_LPSPI_CR_OFFSET (0x0010) /* Control Register (CR) */
#define IMX9_LPSPI_SR_OFFSET (0x0014) /* Status Register (SR) */
#define IMX9_LPSPI_IER_OFFSET (0x0018) /* Interrupt Enable Register (IER) */
#define IMX9_LPSPI_DER_OFFSET (0x001c) /* DMA Enable Register (DER) */
#define IMX9_LPSPI_CFGR0_OFFSET (0x0020) /* Configuration Register 0 (CFGR0) */
#define IMX9_LPSPI_CFGR1_OFFSET (0x0024) /* Configuration Register 1 (CFGR1) */
#define IMX9_LPSPI_DMR0_OFFSET (0x0030) /* Data Match Register 0 (DMR0) */
#define IMX9_LPSPI_DMR1_OFFSET (0x0034) /* Data Match Register 1 (DMR1) */
#define IMX9_LPSPI_CCR_OFFSET (0x0040) /* Clock Configuration Register (CCR) */
#define IMX9_LPSPI_CCR1_OFFSET (0x0044) /* Clock Configuration Register 1 (CCR1) */
#define IMX9_LPSPI_FCR_OFFSET (0x0058) /* FIFO Control Register (FCR) */
#define IMX9_LPSPI_FSR_OFFSET (0x005c) /* FIFO Status Register (FSR) */
#define IMX9_LPSPI_TCR_OFFSET (0x0060) /* Transmit Command Register (TCR) */
#define IMX9_LPSPI_TDR_OFFSET (0x0064) /* Transmit Data Register (TDR) */
#define IMX9_LPSPI_RSR_OFFSET (0x0070) /* Receive Status Register (RSR) */
#define IMX9_LPSPI_RDR_OFFSET (0x0074) /* Receive Data Register (RDR) */
#define IMX9_LPSPI_RDROR_OFFSET (0x0078) /* Receive Data Read Only Register (RDROR) */
#define IMX9_LPSPI_TCBR_OFFSET (0x03fc) /* Transmit Command Burst Register (TCBR) */
#define IMX9_LPSPI_TDBR_OFFSET(n) (0x0400 + ((n) << 2)) /* Transmit Data Burst Register n=0..127 (TDBRn) */
#define IMX9_LPSPI_RDBR_OFFSET(n) (0x0600 + ((n) << 2)) /* Receive Data Burst Register n=0..127 (RDBRn) */
/* Register addresses *******************************************************/
#define IMX9_LPSPI0_VERID(n) ((n) + IMX9_LPSPI_VERID_OFFSET)
#define IMX9_LPSPI0_PARAM(n) ((n) + IMX9_LPSPI_PARAM_OFFSET)
#define IMX9_LPSPI0_CR(n) ((n) + IMX9_LPSPI_CR_OFFSET)
#define IMX9_LPSPI0_SR(n) ((n) + IMX9_LPSPI_SR_OFFSET)
#define IMX9_LPSPI0_IER(n) ((n) + IMX9_LPSPI_IER_OFFSET)
#define IMX9_LPSPI0_DER(n) ((n) + IMX9_LPSPI_DER_OFFSET)
#define IMX9_LPSPI0_CFGR0(n) ((n) + IMX9_LPSPI_CFGR0_OFFSET)
#define IMX9_LPSPI0_CFGR1(n) ((n) + IMX9_LPSPI_CFGR1_OFFSET)
#define IMX9_LPSPI0_DMR0(n) ((n) + IMX9_LPSPI_DMR0_OFFSET)
#define IMX9_LPSPI0_DMR1(n) ((n) + IMX9_LPSPI_DMR1_OFFSET)
#define IMX9_LPSPI0_CCR(n) ((n) + IMX9_LPSPI_CCR_OFFSET)
#define IMX9_LPSPI0_CCR1(n) ((n) + IMX9_LPSPI_CCR1_OFFSET)
#define IMX9_LPSPI0_FCR(n) ((n) + IMX9_LPSPI_FCR_OFFSET)
#define IMX9_LPSPI0_FSR(n) ((n) + IMX9_LPSPI_FSR_OFFSET)
#define IMX9_LPSPI0_TCR(n) ((n) + IMX9_LPSPI_TCR_OFFSET)
#define IMX9_LPSPI0_TDR(n) ((n) + IMX9_LPSPI_TDR_OFFSET)
#define IMX9_LPSPI0_RSR(n) ((n) + IMX9_LPSPI_RSR_OFFSET)
#define IMX9_LPSPI0_RDR(n) ((n) + IMX9_LPSPI_RDR_OFFSET)
#define IMX9_LPSPI0_RDROR(n) ((n) + IMX9_LPSPI_RDROR_OFFSET)
#define IMX9_LPSPI0_TCBR(n) ((n) + IMX9_LPSPI_TCBR_OFFSET)
#define IMX9_LPSPI0_TDBR(n,v) ((n) + IMX9_LPSPI_TDBR_OFFSET(v))
#define IMX9_LPSPI0_RDBR(n,v) ((n) + IMX9_LPSPI_RDBR_OFFSET(v))
/* Register bit definitions *************************************************/
/* Version ID Register (VERID) */
#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number (FEATURE) */
#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT)
#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT)
#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT)
#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT)
#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number (PCSNUM) */
#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT)
/* Bits 24-31: Reserved */
/* Control Register (CR) */
#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable (MEN) */
#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bit 2: Reserved */
#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable (DBGEN) */
/* Bits 4-7: Reserved */
#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */
#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */
/* Bits 10-31: Reserved */
/* Status Register (SR) */
#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */
#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */
/* Bits 2-7: Reserved */
#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag (WCF) */
#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag (FCF) */
#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag (TCF) */
#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag (TEF) */
#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag (REF) */
#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag (DMF) */
/* Bits 14-23: Reserved */
#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag (MBF) */
/* Bits 25-31: Reserved */
/* Interrupt Enable Register (IER) */
#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */
#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */
/* Bits 2-7: Reserved */
#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable (WCIE) */
#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable (FCIE) */
#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable (TCIE) */
#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable (TEIE) */
#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable (REIE) */
#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable (DMIE) */
/* Bits 14-31: Reserved */
/* DMA Enable Register (DER) */
#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */
#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */
/* Bits 2-31: Reserved */
/* Configuration Register 0 (CFGR0) */
#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable (HREN) */
#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity (HRPOL) */
# define LPSPI_CFGR0_HRPOL_HIGH (0 << 1) /* HREQ pin or input trigger is active high */
# define LPSPI_CFGR0_HRPOL_LOW (1 << 1) /* HREQ pin or input trigger is active low */
#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select (HRSEL) */
# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */
# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */
#define LPSPI_CFGR0_HRDIR (1 << 3) /* Bit 3: Host Request Direction (HRDIR) */
# define LPSPI_CFGR0_HRDIR_INPUT (0 << 3) /* HREQ pin is configured as input */
# define LPSPI_CFGR0_HRDIR_OUTPUT (1 << 3) /* HREQ pin is configured as output */
/* Bits 4-7: Reserved */
#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bit 8: Circular FIFO Enable (CIRCFIFO) */
#define LPSPI_CFGR0_RDMO (1 << 9) /* Bit 9: Receive Data Match Only (RDMO) */
# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* Received data is stored in the receive FIFO as in normal operations */
# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* Received data is discarded unless the Data Match Flag (DMF) is set */
/* Bits 10-31: Reserved */
/* Configuration Register 1 (CFGR1) */
#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode (MASTER) */
#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point (SAMPLE) */
# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */
# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */
#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS (AUTOPCS) */
#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall (NOSTALL) */
#define LPSPI_CFGR1_PARTIAL (1 << 4) /* Bit 4: Partial Enable (PARTIAL) */
/* Bits 5-7: Reserved */
#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-15: Peripheral Chip Select Polarity (PCSPOL) */
#define LPSPI_CFGR1_PCSPOL_MASK (0xff << LPSPI_CFGR1_PCSPOL_SHIFT)
# define LPSPI_CFGR1_PCSPOL_LOW(n) (0 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active low */
# define LPSPI_CFGR1_PCSPOL_HIGH(n) (1 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active high */
#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration (MATCFG) */
#define LPSPI_CFGR1_MATCFG_MASK (0x07 << LPSPI_CFGR1_MATCFG_SHIFT)
#define LPSPI_CFGR1_MATCFG_DIS (0x00 << LPSPI_CFGR1_MATCFG_SHIFT) /* Match is disabled */
/* Bits 19-23: Reserved */
#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration (PINCFG) */
#define LPSPI_CFGR1_PINCFG_MASK (0x03 << LPSPI_CFGR1_PINCFG_SHIFT)
# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0x00 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */
# define LPSPI_CFGR1_PINCFG_SIN_SIN (0x01 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (0x02 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SIN (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */
# define LPSPI_CFGR1_PINCFG(n) ((n) << LPSPI_CFGR1_PINCFG_SHIFT)
#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config (OUTCFG) */
# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */
# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */
#define LPSPI_CFGR1_PCSCFG_SHIFT (27) /* Bits 27-28: Peripheral Chip Select Configuration (PCSCFG) */
#define LPSPI_CFGR1_PCSCFG_MASK (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT)
# define LPSPI_CFGR1_PCSCFG_PCS (0x00 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for chip select function */
# define LPSPI_CFGR1_PCSCFG_4BIT (0x01 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:3] are configured for half-duplex 4-bit transfers */
# define LPSPI_CFGR1_PCSCFG_8BIT (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for half-duplex 4-bit and 8-bit transfers */
/* Bits 29-31: Reserved */
/* Data Match Register 0 (DMR0) */
#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value (MATCH0) */
#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT)
/* Data Match Register 0 (DMR1) */
#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value (MATCH1) */
#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT)
/* Clock Configuration Register (CCR) */
#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider (SCKDIV) */
#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT)
# define LPSPI_CCR_SCKDIV(n) (((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers (DBT) */
#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT)
# define LPSPI_CCR_DBT(n) (((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay (PCSSCK) */
#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT)
# define LPSPI_CCR_PCSSCK(n) (((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay (SCKPCS) */
#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT)
# define LPSPI_CCR_SCKPCS(n) (((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT) & LPSPI_CCR_SCKPCS_MASK)
/* Clock Configuration Register 1 (CCR1) */
#define LPSPI_CCR1_SCKSET_SHIFT (0) /* Bits 0-7: SCK Setup (SCKSET) */
#define LPSPI_CCR1_SCKSET_MASK (0xff << LPSPI_CCR1_SCKSET_SHIFT)
#define LPSPI_CCR1_SCKHLD_SHIFT (8) /* Bits 8-15: SCK Hold (SCKHLD) */
#define LPSPI_CCR1_SCKHLD_MASK (0xff << LPSPI_CCR1_SCKHLD_SHIFT)
#define LPSPI_CCR1_PCSPCS_SHIFT (16) /* Bits 16-23: PCS to PCS Delay (PCSPCS) */
#define LPSPI_CCR1_PCSPCS_MASK (0xff << LPSPI_CCR1_PCSPCS_SHIFT)
#define LPSPI_CCR1_SCKSCK_SHIFT (24) /* Bits 24-31: SCK Inter-Frame Delay (SCKSCK) */
#define LPSPI_CCR1_SCKSCK_MASK (0xff << LPSPI_CCR1_SCKSCK_SHIFT)
/* FIFO Control Register (FCR) */
#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-1: Transmit FIFO Watermark (TXWATER) */
#define LPSPI_FCR_TXWATER_MASK (0x03 << LPSPI_FCR_TXWATER_SHIFT)
# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT)
/* Bits 2-15: Reserved */
#define LPSPI_FCR_RXWATER_SHIFT (16) /* Bits 16-17: Receive FIFO Watermark (RXWATER) */
#define LPSPI_FCR_RXWATER_MASK (0x03 << LPSPI_FCR_RXWATER_SHIFT)
# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT)
/* Bits 18-31: Reserved */
/* FIFO Status Register (FSR) */
#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-2: Transmit FIFO Count (TXCOUNT) */
#define LPSPI_FSR_TXCOUNT_MASK (0x07 << LPSPI_FSR_TXCOUNT_SHIFT)
/* Bits 3-15: Reserved */
#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-18: Receive FIFO Count (RXCOUNT) */
#define LPSPI_FSR_RXCOUNT_MASK (0x07 << LPSPI_FSR_RXCOUNT_SHIFT)
/* Bits 19-31: Reserved */
/* Transmit Command Register (TCR) */
#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size (FRAMESZ) */
#define LPSPI_TCR_FRAMESZ_MASK (0x0fff << LPSPI_TCR_FRAMESZ_SHIFT)
# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT)
/* Bits 12-15: Reserved */
#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width (WIDTH) */
#define LPSPI_TCR_WIDTH_MASK (0x03 << LPSPI_TCR_WIDTH_SHIFT)
# define LPSPI_TCR_WIDTH_1BIT (0x00 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */
# define LPSPI_TCR_WIDTH_2BIT (0x01 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */
# define LPSPI_TCR_WIDTH_4BIT (0x02 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */
# define LPSPI_TCR_WIDTH_8BIT (0x03 << LPSPI_TCR_WIDTH_SHIFT) /* 8 bit transfer */
#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask (TXMSK) */
#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask (RXMSK) */
#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command (CONTC) */
#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer (CONT) */
#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap (BYSW) */
#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First (LSBF) */
# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-26: Peripheral Chip Select (PCS) */
#define LPSPI_TCR_PCS_MASK (0x07 << LPSPI_TCR_PCS_SHIFT)
# define LPSPI_TCR_PCS_0 (0x00 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[0] */
# define LPSPI_TCR_PCS_1 (0x01 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[1] */
# define LPSPI_TCR_PCS_2 (0x02 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[2] */
# define LPSPI_TCR_PCS_3 (0x03 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[3] */
# define LPSPI_TCR_PCS_4 (0x04 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[4] */
# define LPSPI_TCR_PCS_5 (0x05 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[5] */
# define LPSPI_TCR_PCS_6 (0x06 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[6] */
# define LPSPI_TCR_PCS_7 (0x07 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[7] */
# define LPSPI_TCR_PCS(n) (((n) << LPSPI_TCR_PCS_SHIFT) & LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value (PRESCALE) */
#define LPSPI_TCR_PRESCALE_MASK (0x07 << LPSPI_TCR_PRESCALE_SHIFT)
# define LPSPI_TCR_PRESCALE_DIV1 (0x00 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */
# define LPSPI_TCR_PRESCALE_DIV2 (0x01 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */
# define LPSPI_TCR_PRESCALE_DIV4 (0x02 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */
# define LPSPI_TCR_PRESCALE_DIV8 (0x03 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */
# define LPSPI_TCR_PRESCALE_DIV16 (0x04 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */
# define LPSPI_TCR_PRESCALE_DIV32 (0x05 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */
# define LPSPI_TCR_PRESCALE_DIV64 (0x06 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */
# define LPSPI_TCR_PRESCALE_DIV128 (0x07 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */
# define LPSPI_TCR_PRESCALE(n) ((n) << LPSPI_TCR_PRESCALE_SHIFT)
#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase (CPHA) */
# define LPSPI_TCR_CPHA_CAPTURED (0 << 30) /* Data is captured on the leading edge of SCK and changed on the following edge of SCK */
# define LPSPI_TCR_CPHA_CHANGED (1 << 30) /* Data is changed on the leading edge of SCK and captured on the following edge of SCK */
#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity (CPOL) */
# define LPSPI_TCR_CPOL_LOW (0 << 31) /* The inactive state value of SCK is low */
# define LPSPI_TCR_CPOL_HIGH (1 << 31) /* The inactive state value of SCK is high */
/* Transmit Data Register (TDR) */
#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data (DATA) */
#define LPSPI_TDR_DATA_MASK (0xffffffff << LPSPI_TDR_DATA_SHIFT)
/* Receive Status Register (RSR) */
#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame (SOF) */
#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty (RXEMPTY) */
/* Bits 2-31: Reserved */
/* Receive Data Register (RDR) */
#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */
#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT)
/* Receive Data Read Only Register (RDROR) */
#define LPSPI_RDROR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */
#define LPSPI_RDROR_DATA_MASK (0xffffffff << LPSPI_RDROR_DATA_SHIFT)
/* Transmit Command Burst Register (TCBR) */
#define LPSPI_TCBR_DATA_SHIFT (0) /* Bits 0-31: Command Data (DATA) */
#define LPSPI_TCBR_DATA_MASK (0xffffffff << LPSPI_TCBR_DATA_SHIFT)
/* Transmit Data Burst Register (TDBR) */
#define LPSPI_TDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */
#define LPSPI_TDBR_DATA_MASK (0xffffffff << LPSPI_TDBR_DATA_SHIFT)
/* Receive Data Burst Register (RDBR) */
#define LPSPI_RDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */
#define LPSPI_RDBR_DATA_MASK (0xffffffff << LPSPI_RDBR_DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lptmr.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_LPTMR_CSR_OFFSET 0x0000 /* Control Status */
#define IMX9_LPTMR_PSR_OFFSET 0x0004 /* Prescale */
#define IMX9_LPTMR_CMR_OFFSET 0x0008 /* Compare */
#define IMX9_LPTMR_CNR_OFFSET 0x000c /* Counter */
/* Register Address *********************************************************/
#define LPTMR_CSR(n) ((n) + IMX9_LPTMR_CSR_OFFSET)
#define LPTMR_PSR(n) ((n) + IMX9_LPTMR_PSR_OFFSET)
#define LPTMR_CMR(n) ((n) + IMX9_LPTMR_CMR_OFFSET)
#define LPTMR_CNR(n) ((n) + IMX9_LPTMR_CNR_OFFSET)
/* Register Bitfield Definitions ********************************************/
#define LPTMR_CSR_TDRE (1 << 8) /* Timer DMA Request Enable */
#define LPTMR_CSR_TCF (1 << 7) /* Timer Compare Flag */
#define LPTMR_CSR_TIE (1 << 6) /* Timer Interrupt Enable */
#define LPTMR_CSR_TPS_SHIFT (4) /* Bit[5:4]: Timer Pin Select */
#define LPTMR_CSR_TPS_MASK (3 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS0 (0 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS1 (1 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS2 (2 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS3 (3 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPP (1 << 3) /* Timer Pin Polarity */
#define LPTMR_CSR_TFC (1 << 2) /* Timer Free-Running Counter */
#define LPTMR_CSR_TMS (1 << 1) /* Timer Mode Select */
#define LPTMR_CSR_TEN (1 << 0) /* Timer Enable */
#define LPTMR_PSR_PRESCALE_SHIFT (3) /* Bit[6:3]: Prescale Value */
#define LPTMR_PSR_PRESCALE_MASK (0xf << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV8 (2 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV16 (3 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV32 (4 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV64 (5 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV128 (6 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV256 (7 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV512 (8 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV1024 (9 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV2048 (10 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV4096 (11 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV8192 (12 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV16384 (13 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV32768 (14 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV65536 (15 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PBYP (1 << 2) /* Prescaler Bypass */
/* Clock sources (module clock / root clock)
* ipg_clk_irclk -> lptmrx_clk_root
* ipg_clk_1khz -> 32k_clk_root
* ipg_clk_32khz -> 32k_clk_root
* ipg_clk_ercl -> 32k_clk_root
*/
#define LPTMR_PSR_PCS_SHIFT (0) /* Bit[1:0]: Prescaler Clock Select */
#define LPTMR_PSR_PCS_MASK (3 << LPTMR_PSR_PCS_SHIFT)
#define LPTMR_PSR_PCS_REF_INT (0 << LPTMR_PSR_PCS_SHIFT) /* Internal reference clock */
#define LPTMR_PSR_PCS_LPO (1 << LPTMR_PSR_PCS_SHIFT) /* LPO 1K Hz */
#define LPTMR_PSR_PCS_RTC (2 << LPTMR_PSR_PCS_SHIFT) /* RTC 32768 Hz */
#define LPTMR_PSR_PCS_REF_EXT (3 << LPTMR_PSR_PCS_SHIFT) /* External reference clock */
# define LPTMR_PSR_PCS_SOSC LPTMR_PSR_PCS_RFOSC
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpuart.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/imx9_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPUART Register Offsets **************************************************/
#define IMX9_LPUART_VERID_OFFSET (0x00) /* Version ID Register (VERID) */
#define IMX9_LPUART_PARAM_OFFSET (0x04) /* Parameter Register (PARAM) */
#define IMX9_LPUART_GLOBAL_OFFSET (0x08) /* LPUART Global Register (GLOBAL) */
#define IMX9_LPUART_PINCFG_OFFSET (0x0c) /* LPUART Pin Configuration Register (PINCFG) */
#define IMX9_LPUART_BAUD_OFFSET (0x10) /* LPUART Baud Rate Register (BAUD) */
#define IMX9_LPUART_STAT_OFFSET (0x14) /* LPUART Status Register (STAT) */
#define IMX9_LPUART_CTRL_OFFSET (0x18) /* LPUART Control Register (CTRL) */
#define IMX9_LPUART_DATA_OFFSET (0x1c) /* LPUART Data Register (DATA) */
#define IMX9_LPUART_MATCH_OFFSET (0x20) /* LPUART Match Address Register (MATCH) */
#define IMX9_LPUART_MODIR_OFFSET (0x24) /* LPUART Modem IrDA Register (MODIR) */
#define IMX9_LPUART_FIFO_OFFSET (0x28) /* LPUART FIFO Register (FIFO) */
#define IMX9_LPUART_WATER_OFFSET (0x2c) /* LPUART Watermark Register (WATER) */
#define IMX9_LPUART_DATARO_OFFSET (0x30) /* Data read-only Register (DATARO) */
/* Register bit definitions *************************************************/
/* Version ID Register (VERID) */
#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number (FEATURE) */
#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT)
# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */
# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */
#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT)
#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT)
#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT)
/* Bits 16-31: Reserved */
/* LPUART Global Register (GLOBAL) */
/* Bit 0: Reserved */
#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bits 2-31: Reserved */
/* LPUART Pin Configuration Register (PINCFG) */
#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select (TRGSEL) */
#define LPUART_PINCFG_TRGSEL_MASK (0x03 << LPUART_PINCFG_TRGSEL_SHIFT)
# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */
# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */
# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */
# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */
/* Bits 2-31: Reserved */
/* LPUART Baud Rate Register (BAUD) */
#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor (SBR) */
#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
# define LPUART_BAUD_SBR(n) ((n) << LPUART_BAUD_SBR_SHIFT)
#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select (SBNS) */
#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable (RXEDGIE) */
#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable (LBKDIE) */
#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable (RESYNCDIS) */
#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling (BOTHEDGE) */
#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration (MATCFG) */
#define LPUART_BAUD_MATCFG_MASK (0x03 << LPUART_BAUD_MATCFG_SHIFT)
# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */
/* Bit 20: Reserved */
#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable (RDMAE) */
/* Bit 22: Reserved */
#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable (TDMAE) */
#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-29: Oversampling Ratio (OSR) */
#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT)
# define LPUART_BAUD_OSR(n) (((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */
#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode Select (M10) */
#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 (MAEN2) */
#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 (MAEN1) */
/* LPUART Status Register (STAT) */
#define LPUART_STAT_LBKFE (1 << 0) /* Bit 0: LIN Break Flag Enable (LBKFE) */
#define LPUART_STAT_AME (1 << 1) /* Bit 1: Address Mark Enable (AME) */
/* Bits 2-13: Reserved */
#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag (MA2F) */
#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag (MA1F) */
#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag (PF) */
#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag (FE) */
#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag (NF) */
#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag (OR) */
#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag (IDLE) */
#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag (RDRF) */
#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag (TC) */
#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag (TDRE) */
#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag (RAF) */
#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable (LBKDE) */
#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length (BRK13) */
#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect (RWUID) */
#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion (RXINV) */
#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First (MSBF) */
#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag (RXEDGIF) */
#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag (LBKDIF) */
/* LPUART Control Register (CTRL) */
#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */
# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */
# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */
#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */
#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */
#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */
#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */
#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */
#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */
#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */
#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */
#define LPUART_CTRL_IDLECFG_MASK (0x07 << LPUART_CTRL_IDLECFG_SHIFT)
# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select (M7) */
/* Bits 12-13: Reserved */
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable (MA2IE) */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable (MA1IE) */
#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break (SBK) */
#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control (RWU) */
#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable (RE) */
#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable (TE) */
#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable (ILIE) */
#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable (RIE) */
#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable (TCIE) */
#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable (TIE) */
#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable (PEIE) */
#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable (FEIE) */
#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable (NEIE) */
#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable (ORIE) */
#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion (TXINV) */
#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode (TXDIR) */
#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 (R9T8) */
#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 (R8T9) */
#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \
LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \
LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \
LPUART_CTRL_MA2IE)
/* LPUART Data Register (DATA) */
#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 (DATA)*/
#define LPUART_DATA_MASK (0x03ff << LPUART_DATA_SHIFT)
#define LPUART_DATA_LINBRK (1 << 10) /* Bit 10: LIN Break (LINBRK) */
#define LPUART_DATA_STATUS_SHIFT (11) /* Bits 11-15: Status */
#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line (IDLINE) */
#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty (RXEMPT) */
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character (FRETSC) */
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error (PARITYE) */
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy Data Received (NOISY) */
/* Bits 16-31: Reserved */
/* LPUART Match Address Register (MATCH) */
#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 (MA1) */
#define LPUART_MATCH_MA1_MASK (0x03ff << LPUART_MATCH_MA1_SHIFT)
# define LPUART_MATCH_MA1(n) ((n) << LPUART_MATCH_MA1_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 (MA2) */
#define LPUART_MATCH_MA2_MASK (0x03ff << LPUART_MATCH_MA2_SHIFT)
# define LPUART_MATCH_MA2(n) ((n) << LPUART_MATCH_MA2_SHIFT)
/* Bits 26-31: Reserved */
/* LPUART Modem IrDA Register (MODIR) */
#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable (TXCTSE) */
#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable (TXRTSE) */
#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity (TXRTSPOL) */
#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable (RXRTSE) */
#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration (TXCTSC) */
# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */
# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */
#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source (TXCTSSRC) */
# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* CTS input is CTS_B pin */
# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* CTS input is receiver address match result */
/* Bits 6-7: Reserved */
#define LPUART_MODIR_RTSWATER_SHIFT (8) /* Bits 8-9: Receive RTS Configuration (RTSWATER) */
#define LPUART_MODIR_RTSWATER_MASK (0x03 << LPUART_MODIR_RTSWATER_SHIFT)
# define LPUART_MODIR_RTSWATER(n) ((n) << LPUART_MODIR_RTSWATER_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse (TNP) */
#define LPUART_MODIR_TNP_MASK (0x03 << LPUART_MODIR_TNP_SHIFT)
# define LPUART_MODIR_TNP(n) (((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */
#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable (IREN) */
/* Bits 19-31: Reserved */
/* LPUART FIFO Register (FIFO) */
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO Buffer Depth (RXFIFOSIZE) */
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x07 << LPUART_FIFO_RXFIFOSIZE_SHIFT)
# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 dataword */
# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable (RXFE) */
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO Buffer Depth (TXFIFOSIZE) */
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x07 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 dataword */
# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable (TXFE) */
#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable (RXUFE) */
#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable (TXOFE) */
#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable (RXIDEN) */
#define LPUART_FIFO_RXIDEN_MASK (0x07 << LPUART_FIFO_RXIDEN_SHIFT)
# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */
# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 character */
# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 characters */
# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 characters */
# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 characters */
# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 characters */
# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 characters */
# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 characters */
/* Bit 13: Reserved */
#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO Flush (RXFLUSH) */
#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO Flush (TXFLUSH) */
#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver FIFO Underflow Flag (RXUF) */
#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter FIFO Overflow Flag (TXOF) */
/* Bits 18-21: Reserved */
#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty (RXEMPT) */
#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty (TXEMPT) */
/* Bits 24-31: Reserved */
/* LPUART Watermark Register (WATER) */
#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-3: Transmit Watermark (TXWATER) */
#define LPUART_WATER_TXWATER_MASK (0x0f << LPUART_WATER_TXWATER_SHIFT)
# define LPUART_WATER_TXWATER(n) ((n) << LPUART_WATER_TXWATER_SHIFT)
/* Bits 4-7: Reserved */
#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-12: Transmit Counter (TXCOUNT) */
#define LPUART_WATER_TXCOUNT_MASK (0x1f << LPUART_WATER_TXCOUNT_SHIFT)
# define LPUART_WATER_TXCOUNT(n) ((n) << LPUART_WATER_TXCOUNT_SHIFT)
/* Bits 13-15: Reserved */
#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-19: Receive Watermark (RXWATER) */
#define LPUART_WATER_RXWATER_MASK (0x0f << LPUART_WATER_RXWATER_SHIFT)
# define LPUART_WATER_RXWATER(n) ((n) << LPUART_WATER_RXWATER_SHIFT)
/* Bits 20-23: Reserved */
#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-28: Receive Counter (RXCOUNT) */
#define LPUART_WATER_RXCOUNT_MASK (0x1f << LPUART_WATER_RXCOUNT_SHIFT)
# define LPUART_WATER_RXCOUNT(n) ((n) << LPUART_WATER_RXCOUNT_SHIFT)
/* Bits 29-31: Reserved */
/* Data read-only Register (DATARO) */
#define LPUART_DATARO_DATA_SHIFT (0) /* Bits 0-15: Receive Data (DATA) */
#define LPUART_DATARO_DATA_MASK (0xffff << LPUART_DATARO_DATA_SHIFT)
/* Bits 16-31: Reserved */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_memorymap.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_mu.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets */
#define IMX9_MU_VER_OFFSET 0x0000 /* Version ID */
#define IMX9_MU_PAR_OFFSET 0x0004 /* Parameter */
#define IMX9_MU_CR_OFFSET 0x0008 /* Control */
#define IMX9_MU_SR_OFFSET 0x000c /* Status */
#define IMX9_MU_FCR_OFFSET 0x0100 /* Flag Control */
#define IMX9_MU_FSR_OFFSET 0x0104 /* Flag Status */
#define IMX9_MU_GIER_OFFSET 0x0110 /* General-Purpose Interrupt Enable */
#define IMX9_MU_GCR_OFFSET 0x0114 /* General-Purpose Control */
#define IMX9_MU_GSR_OFFSET 0x0118 /* General-purpose Status */
#define IMX9_MU_TCR_OFFSET 0x0120 /* Transmit Control */
#define IMX9_MU_TSR_OFFSET 0x0124 /* Transmit Status */
#define IMX9_MU_RCR_OFFSET 0x0128 /* Receive Control */
#define IMX9_MU_RSR_OFFSET 0x012c /* Receive Status */
#define IMX9_MU_TR1_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_TR2_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_TR3_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_TR4_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_RR1_OFFSET 0x0280 /* Receive */
#define IMX9_MU_RR2_OFFSET 0x0280 /* Receive */
#define IMX9_MU_RR3_OFFSET 0x0280 /* Receive */
#define IMX9_MU_RR4_OFFSET 0x0280 /* Receive */
/* Register macros */
#define IMX9_MU_VER(n) ((n) + IMX9_MU_VER_OFFSET) /* Version ID */
#define IMX9_MU_PAR(n) ((n) + IMX9_MU_PAR_OFFSET) /* Parameter */
#define IMX9_MU_CR(n) ((n) + IMX9_MU_CR_OFFSET) /* Control */
#define IMX9_MU_SR(n) ((n) + IMX9_MU_SR_OFFSET) /* Status */
#define IMX9_MU_FCR(n) ((n) + IMX9_MU_FCR_OFFSET) /* Flag Control */
#define IMX9_MU_FSR(n) ((n) + IMX9_MU_FSR_OFFSET) /* Flag Status */
#define IMX9_MU_GIER(n) ((n) + IMX9_MU_GIER_OFFSET) /* General-Purpose Interrupt Enable */
#define IMX9_MU_GCR(n) ((n) + IMX9_MU_GCR_OFFSET) /* General-Purpose Control */
#define IMX9_MU_GSR(n) ((n) + IMX9_MU_GSR_OFFSET) /* General-purpose Status */
#define IMX9_MU_TCR(n) ((n) + IMX9_MU_TCR_OFFSET) /* Transmit Control */
#define IMX9_MU_TSR(n) ((n) + IMX9_MU_TSR_OFFSET) /* Transmit Status */
#define IMX9_MU_RCR(n) ((n) + IMX9_MU_RCR_OFFSET) /* Receive Control */
#define IMX9_MU_RSR(n) ((n) + IMX9_MU_RSR_OFFSET) /* Receive Status */
#define IMX9_MU_TR1(n) ((n) + IMX9_MU_TR1_OFFSET) /* Transmit */
#define IMX9_MU_TR2(n) ((n) + IMX9_MU_TR2_OFFSET) /* Transmit */
#define IMX9_MU_TR3(n) ((n) + IMX9_MU_TR3_OFFSET) /* Transmit */
#define IMX9_MU_TR4(n) ((n) + IMX9_MU_TR4_OFFSET) /* Transmit */
#define IMX9_MU_RR1(n) ((n) + IMX9_MU_RR1_OFFSET) /* Receive */
#define IMX9_MU_RR2(n) ((n) + IMX9_MU_RR2_OFFSET) /* Receive */
#define IMX9_MU_RR3(n) ((n) + IMX9_MU_RR3_OFFSET) /* Receive */
#define IMX9_MU_RR4(n) ((n) + IMX9_MU_RR4_OFFSET) /* Receive */
/* Field definitions */
/* VER register */
#define IMX9_MU_VER_FEATURE_SHIFT 0 /* Feature Set Number */
#define IMX9_MU_VER_FEATURE_MASK 0xffff /* Feature Set Number */
#define IMX9_MU_VER_MINOR_SHIFT 16 /* Minor Version Number */
#define IMX9_MU_VER_MINOR_MASK 0xff /* Minor Version Number */
#define IMX9_MU_VER_MAJOR_SHIFT 24 /* Major Version Number */
#define IMX9_MU_VER_MAJOR_MASK 0xff /* Major Version Number */
/* PAR register */
#define IMX9_MU_PAR_TR_NUM_SHIFT 0 /* Transmit Register Number */
#define IMX9_MU_PAR_TR_NUM_MASK 0xff /* Transmit Register Number */
#define IMX9_MU_PAR_RR_NUM_SHIFT 8 /* Receive Register Number */
#define IMX9_MU_PAR_RR_NUM_MASK 0xff /* Receive Register Number */
#define IMX9_MU_PAR_GIR_NUM_SHIFT 16 /* General-Purpose Interrupt Request Number */
#define IMX9_MU_PAR_GIR_NUM_MASK 0xff /* General-Purpose Interrupt Request Number */
#define IMX9_MU_PAR_FLAG_WIDTH_SHIFT 24 /* Flag Width */
#define IMX9_MU_PAR_FLAG_WIDTH_MASK 0xff /* Flag Width */
/* CR register */
#define IMX9_MU_CR_MUR_SHIFT 0 /* MU Reset */
#define IMX9_MU_CR_MUR_FLAG (1 << IMX9_MU_CR_MUR_SHIFT) /* MU Reset */
#define IMX9_MU_CR_MURIE_SHIFT 1 /* MUA Reset Interrupt Enable */
#define IMX9_MU_CR_MURIE_FLAG (1 << IMX9_MU_CR_MURIE_SHIFT) /* MUA Reset Interrupt Enable */
/* SR register */
#define IMX9_MU_SR_MURS_SHIFT 0 /* MUA and MUB Reset State */
#define IMX9_MU_SR_MURS_FLAG (1 << IMX9_MU_SR_MURS_SHIFT) /* MUA and MUB Reset State */
#define IMX9_MU_SR_MURIP_SHIFT 1 /* MU Reset Interrupt Pending Flag */
#define IMX9_MU_SR_MURIP_FLAG (1 << IMX9_MU_SR_MURIP_SHIFT) /* MU Reset Interrupt Pending Flag */
#define IMX9_MU_SR_EP_SHIFT 2 /* MUA Side Event Pending */
#define IMX9_MU_SR_EP_FLAG (1 << IMX9_MU_SR_EP_SHIFT) /* MUA Side Event Pending */
#define IMX9_MU_SR_FUP_SHIFT 3 /* MUA Flag Update Pending */
#define IMX9_MU_SR_FUP_FLAG (1 << IMX9_MU_SR_FUP_SHIFT) /* MUA Flag Update Pending */
#define IMX9_MU_SR_GIRP_SHIFT 4 /* MUA General-Purpose Interrupt Pending */
#define IMX9_MU_SR_GIRP_FLAG (1 << IMX9_MU_SR_GIRP_SHIFT) /* MUA General-Purpose Interrupt Pending */
#define IMX9_MU_SR_TEP_SHIFT 5 /* MUA Transmit Empty Pending */
#define IMX9_MU_SR_TEP_FLAG (1 << IMX9_MU_SR_TEP_SHIFT) /* MUA Transmit Empty Pending */
#define IMX9_MU_SR_RFP_SHIFT 6 /* MUA Receive Full Pending */
#define IMX9_MU_SR_RFP_FLAG (1 << IMX9_MU_SR_RFP_SHIFT) /* MUA Receive Full Pending */
/* FCR register */
#define IMX9_MU_FCR_F0_SHIFT 0 /* MUA to MUB Flag */
#define IMX9_MU_FCR_F0_FLAG (1 << IMX9_MU_FCR_F0_SHIFT) /* MUA to MUB Flag */
#define IMX9_MU_FCR_F1_SHIFT 1 /* MUA to MUB Flag */
#define IMX9_MU_FCR_F1_FLAG (1 << IMX9_MU_FCR_F1_SHIFT) /* MUA to MUB Flag */
#define IMX9_MU_FCR_F2_SHIFT 2 /* MUA to MUB Flag */
#define IMX9_MU_FCR_F2_FLAG (1 << IMX9_MU_FCR_F2_SHIFT) /* MUA to MUB Flag */
/* FSR register */
#define IMX9_MU_FSR_F0_SHIFT 0 /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F0_FLAG (1 << IMX9_MU_FSR_F0_SHIFT) /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F1_SHIFT 1 /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F1_FLAG (1 << IMX9_MU_FSR_F1_SHIFT) /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F2_SHIFT 2 /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F2_FLAG (1 << IMX9_MU_FSR_F2_SHIFT) /* MUB to MUA-Side Flag */
/* GIER register */
#define IMX9_MU_GIER_GIE0_SHIFT 0 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE0_FLAG (1 << IMX9_MU_GIER_GIE0_SHIFT) /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE1_SHIFT 1 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE1_FLAG (1 << IMX9_MU_GIER_GIE1_SHIFT) /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE2_SHIFT 2 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE2_FLAG (1 << IMX9_MU_GIER_GIE2_SHIFT) /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE3_SHIFT 3 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE3_FLAG (1 << IMX9_MU_GIER_GIE3_SHIFT) /* MUA General-purpose Interrupt Enable */
/* GCR register */
#define IMX9_MU_GCR_GIR0_SHIFT 0 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR0_FLAG (1 << IMX9_MU_GCR_GIR0_SHIFT) /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR1_SHIFT 1 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR1_FLAG (1 << IMX9_MU_GCR_GIR1_SHIFT) /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR2_SHIFT 2 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR2_FLAG (1 << IMX9_MU_GCR_GIR2_SHIFT) /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR3_SHIFT 3 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR3_FLAG (1 << IMX9_MU_GCR_GIR3_SHIFT) /* MUA General-Purpose Interrupt Request */
/* GSR register */
#define IMX9_MU_GSR_GIP0_SHIFT 0 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP0_FLAG (1 << IMX9_MU_GSR_GIP0_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP1_SHIFT 1 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP1_FLAG (1 << IMX9_MU_GSR_GIP1_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP2_SHIFT 2 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP2_FLAG (1 << IMX9_MU_GSR_GIP2_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP3_SHIFT 3 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP3_FLAG (1 << IMX9_MU_GSR_GIP3_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
/* TCR register */
#define IMX9_MU_TCR_TIE0_SHIFT 0 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE0_FLAG (1 << IMX9_MU_TCR_TIE0_SHIFT) /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE1_SHIFT 1 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE1_FLAG (1 << IMX9_MU_TCR_TIE1_SHIFT) /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE2_SHIFT 2 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE2_FLAG (1 << IMX9_MU_TCR_TIE2_SHIFT) /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE3_SHIFT 3 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE3_FLAG (1 << IMX9_MU_TCR_TIE3_SHIFT) /* MUA Transmit Interrupt Enable */
/* TSR register */
#define IMX9_MU_TSR_TE0_SHIFT 0 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE0_FLAG (1 << IMX9_MU_TSR_TE0_SHIFT) /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE1_SHIFT 1 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE1_FLAG (1 << IMX9_MU_TSR_TE1_SHIFT) /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE2_SHIFT 2 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE2_FLAG (1 << IMX9_MU_TSR_TE2_SHIFT) /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE3_SHIFT 3 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE3_FLAG (1 << IMX9_MU_TSR_TE3_SHIFT) /* MUA Transmit Empty */
/* RCR register */
#define IMX9_MU_RCR_RIE0_SHIFT 0 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE0_FLAG (1 << IMX9_MU_RCR_RIE0_SHIFT) /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE1_SHIFT 1 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE1_FLAG (1 << IMX9_MU_RCR_RIE1_SHIFT) /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE2_SHIFT 2 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE2_FLAG (1 << IMX9_MU_RCR_RIE2_SHIFT) /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE3_SHIFT 3 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE3_FLAG (1 << IMX9_MU_RCR_RIE3_SHIFT) /* MUA Receive Interrupt Enable */
/* RSR register */
#define IMX9_MU_RSR_RF0_SHIFT 0 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF0_FLAG (1 << IMX9_MU_RSR_RF0_SHIFT) /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF1_SHIFT 1 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF1_FLAG (1 << IMX9_MU_RSR_RF1_SHIFT) /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF2_SHIFT 2 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF2_FLAG (1 << IMX9_MU_RSR_RF2_SHIFT) /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF3_SHIFT 3 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF3_FLAG (1 << IMX9_MU_RSR_RF3_SHIFT) /* MUA Receive Register Full */
/* Register array dimensions */
#define IMX9_MU_TR_REGARRAY_SIZE 4
#define IMX9_MU_RR_REGARRAY_SIZE 4

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_pinmux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_pinmux.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_tpm.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_TPM_VERID_OFFSET 0x0000 /* Version ID */
#define IMX9_TPM_PARAM_OFFSET 0x0004 /* Parameter */
#define IMX9_TPM_GLOBAL_OFFSET 0x0008 /* TPM Global */
#define IMX9_TPM_SC_OFFSET 0x0010 /* Status and Control */
#define IMX9_TPM_CNT_OFFSET 0x0014 /* Counter */
#define IMX9_TPM_MOD_OFFSET 0x0018 /* Modulo */
#define IMX9_TPM_STATUS_OFFSET 0x001c /* Capture and Compare Status */
#define IMX9_TPM_CXSC_OFFSET(ch) (0x0020 + (ch) * 8) /* Channel Status and Control */
#define IMX9_TPM_CXV_OFFSET(ch) (0x0024 + (ch) * 8) /* Channel Value */
#define IMX9_TPM_C1SC_OFFSET 0x0028 /* Channel n Status and Control */
#define IMX9_TPM_C1V_OFFSET 0x002c /* Channel n Value */
#define IMX9_TPM_C2SC_OFFSET 0x0030 /* Channel n Status and Control */
#define IMX9_TPM_C2V_OFFSET 0x0034 /* Channel n Value */
#define IMX9_TPM_C3SC_OFFSET 0x0038 /* Channel n Status and Control */
#define IMX9_TPM_C3V_OFFSET 0x003c /* Channel n Value */
#define IMX9_TPM_COMBINE_OFFSET 0x0064 /* Combine Channel */
#define IMX9_TPM_TRIG_OFFSET 0x006c /* Channel Trigger */
#define IMX9_TPM_POL_OFFSET 0x0070 /* Channel Polarity */
#define IMX9_TPM_FILTER_OFFSET 0x0078 /* Filter Control */
#define IMX9_TPM_QDCTRL_OFFSET 0x0080 /* Quadrature Decoder Control and Status */
#define IMX9_TPM_CONF_OFFSET 0x0084 /* Configuration */
/* Register Bitfield Definitions ********************************************/
/* PARAM */
#define TPM_PARAM_WIDTH_SHIFT (16) /* Bit[23:16]: Width of the counter and timer channels */
#define TPM_PARAM_WIDTH_MASK (0xff << TPM_PARAM_WIDTH_SHIFT)
#define TPM_PARAM_TRIG_SHIFT (8) /* Bit[15:8]: Number of triggers that TPM implements */
#define TPM_PARAM_TRIG_MASK (0xff << LPIT_PARAM_TRIG_SHIFT)
#define TPM_PARAM_CHAN_SHIFT (0) /* Bit[7:0]: Number of timer channels */
#define TPM_PARAM_CHAN_MASK (0xff << TPM_PARAM_CHAN_SHIFT)
/* GLOBAL */
#define TPM_GLOBAL_RST_SHIFT (1) /* Bit[1]: Software Reset */
#define TPM_GLOBAL_RST_MASK (0x1 << TPM_GLOBAL_RST_SHIFT)
#define TPM_GLOBAL_NOUPDATE_SHIFT (0) /* Bit[0]: Block updates to internal registers */
#define TPM_GLOBAL_NOUPDATE_MASK (0x1 << TPM_GLOBAL_NOUPDATE_SHIFT)
/* SC */
#define TPM_SC_DMA_SHIFT (8) /* Bit[8]: DMA Enable */
#define TPM_SC_DMA_MASK (0x1 << TPM_SC_DMA_SHIFT)
#define TPM_SC_TOF_SHIFT (7) /* Bit[7]: Timer Overflow Flag */
#define TPM_SC_TOF_MASK (0x1 << TPM_SC_TOF_SHIFT)
#define TPM_SC_TOIE_SHIFT (6) /* Bit[6]: Timer Overflow Interrupt Enable */
#define TPM_SC_TOIE_MASK (0x1 << TPM_SC_TOIE_SHIFT)
#define TPM_SC_CPWMS_SHIFT (5) /* Bit[5]: Center-Aligned PWM Select */
#define TPM_SC_CPWMS_MASK (0x1 << TPM_SC_CPWMS_SHIFT)
#define TPM_SC_CMOD_SHIFT (3) /* Bit[4:3]: Clock Mode Selection */
#define TPM_SC_CMOD_MASK (0x3 << TPM_SC_CMOD_SHIFT)
#define TPM_SC_CMOD_VALUE_DISABLE 0
#define TPM_SC_CMOD_VALUE_COUNTER 1
#define TPM_SC_CMOD_VALUE_EXTCLK 2
#define TPM_SC_CMOD_VALUE_TRIG 3
#define TPM_SC_CMOD(n) ((n << TPM_SC_CMOD_SHIFT) & TPM_SC_CMOD_MASK)
#define TPM_SC_PS_SHIFT (0) /* Bit[2:0]: Prescale Factor Selection */
#define TPM_SC_PS_MASK (0x7 << TPM_SC_PS_SHIFT)
/* STATUS */
#define TPM_STATUS_TOF_SHIFT (8) /* Bit[8]: Timer Overflow Flag */
#define TPM_STATUS_TOF_MASK (0x1 << TPM_STATUS_TOF_SHIFT)
#define TPM_STATUS_CH3F_SHIFT (3) /* Bit[3]: Channel 3 Flag */
#define TPM_STATUS_CH3F_MASK (0x1 << TPM_STATUS_CH3F_SHIFT)
#define TPM_STATUS_CH2F_SHIFT (2) /* Bit[2]: Channel 2 Flag */
#define TPM_STATUS_CH2F_MASK (0x1 << TPM_STATUS_CH2F_SHIFT)
#define TPM_STATUS_CH1F_SHIFT (1) /* Bit[1]: Channel 1 Flag */
#define TPM_STATUS_CH1F_MASK (0x1 << TPM_STATUS_CH1F_SHIFT)
#define TPM_STATUS_CH0F_SHIFT (0) /* Bit[0]: Channel 0 Flag */
#define TPM_STATUS_CH0F_MASK (0x1 << TPM_STATUS_CH0F_SHIFT)
/* C0SC - C3SC */
#define TPM_CXSC_CHF_SHIFT (7) /* Bit[7]: Channel Flag */
#define TPM_CXSC_CHF_MASK (0x1 << TPM_CXSC_CHF_SHIFT)
#define TPM_CXSC_CHIE_SHIFT (6) /* Bit[6]: Channel Interrupt Enable */
#define TPM_CXSC_CHIE_MASK (0x1 << TPM_CXSC_CHIE_SHIFT)
#define TPM_CXSC_MSB_SHIFT (5) /* Bit[5]: Channel Mode Select B */
#define TPM_CXSC_MSB_MASK (0x1 << TPM_CXSC_MSB_SHIFT)
#define TPM_CXSC_MSA_SHIFT (4) /* Bit[4]: Channel Mode Select A */
#define TPM_CXSC_MSA_MASK (0x1 << TPM_CXSC_MSA_SHIFT)
#define TPM_CXSC_ELSB_SHIFT (3) /* Bit[3]: Edge or Level Select B */
#define TPM_CXSC_ELSB_MASK (0x1 << TPM_CXSC_ELSB_SHIFT)
#define TPM_CXSC_ELSA_SHIFT (2) /* Bit[2]: Edge or Level Select A */
#define TPM_CXSC_ELSA_MASK (0x1 << TPM_CXSC_ELSA_SHIFT)
#define TPM_CXSC_DMA_SHIFT (0) /* Bit[0]: DMA Enable */
#define TPM_CXSC_DMA_MASK (0x1 << TPM_CXSC_DMA_SHIFT)
/* COMBINE */
#define TPM_COMBINE_COMSWAP1_SHIFT (9) /* Bit[9]: Combine Channels 2 and 3 Swap */
#define TPM_COMBINE_COMSWAP1_MASK (0x1 << TPM_COMBINE_COMSWAP1_SHIFT)
#define TPM_COMBINE_COMBINE1_SHIFT (8) /* Bit[8]: Combine Channels 2 and 3 */
#define TPM_COMBINE_COMBINE1_MASK (0x1 << TPM_COMBINE_COMBINE1_SHIFT)
#define TPM_COMBINE_COMSWAP0_SHIFT (1) /* Bit[1]: Combine Channel 0 and 1 Swap */
#define TPM_COMBINE_COMSWAP0_MASK (0x1 << TPM_COMBINE_COMSWAP0_SHIFT)
#define TPM_COMBINE_COMBINE0_SHIFT (0) /* Bit[0]: Combine Channels 0 and 1 */
#define TPM_COMBINE_COMBINE0_MASK (0x1 << TPM_COMBINE_COMBINE0_SHIFT)
/* TRIG */
#define TPM_TRIG_TRIGX_MASK(ch) (0x1 << (ch)) /* Channel trigger configure */
/* POL */
#define TPM_POL_POLX_MASK(ch) (0x1 < (ch)) /* Channel polarity active low */
/* FILTER */
#define TPM_FILTER_CHXFVAL_SHIFT(ch) ((ch) * 4) /* Channel filter value */
#define TPM_FILTER_CHXFVAL_MASK(ch) (0xf << TPM_FILTER_CHXFVAL_SHIFT(ch))
/* QDCTRL */
#define TPM_QDCTRL_QUADMODE_SHIFT (3) /* Bit[3]: Quadrature Decoder Mode */
#define TPM_QDCTRL_QUADMODE_MASK (0x1 << TPM_QDCTRL_QUADMODE_SHIFT)
#define TPM_QDCTRL_QUADIR_SHIFT (2) /* Bit[2]: Counter Direction */
#define TPM_QDCTRL_QUADIR_MASK (0x1 << TPM_QDCTRL_QUADIR_SHIFT)
#define TPM_QDCTRL_TOFDIR_SHIFT (1) /* Bit[1]: Timer Overflow Direction */
#define TPM_QDCTRL_TOFDIR_MASK (0x1 << TPM_QDCTRL_TOFDIR_SHIFT)
#define TPM_QDCTRL_QUADEN_SHIFT (0) /* Bit[0]: Quadrature Decoder Enable */
#define TPM_QDCTRL_QUADEN_MASK (0x1 << TPM_QDCTRL_QUADEN_SHIFT)
/* CONF */
#define TPM_CONF_TRGSEL_SHIFT (24) /* Bit[25:24]: Trigger Select */
#define TPM_CONF_TRGSEL_MASK (0x3 << TPM_CONF_TRGSEL_SHIFT)
#define TPM_CONF_TRGSRC_SHIFT (23) /* Bit[23]: Trigger Source select */
#define TPM_CONF_TRGSRC_MASK (0x1 << TPM_CONF_TRGSRC_SHIFT)
#define TPM_CONF_TRGPOL_SHIFT (22) /* Bit[22]: Trigger Polarity */
#define TPM_CONF_TRGPOL_MASK (0x1 << TPM_CONF_TRGPOL_SHIFT)
#define TPM_CONF_CPOT_SHIFT (19) /* Bit[19]: Counter Pause on Trigger */
#define TPM_CONF_CPOT_MASK (0x1 << TPM_CONF_CPOT_SHIFT)
#define TPM_CONF_CROT_SHIFT (18) /* Bit[18]: Counter Reload on Trigger */
#define TPM_CONF_CROT_MASK (0x1 << TPM_CONF_CROT_SHIFT)
#define TPM_CONF_CSOO_SHIFT (17) /* Bit[17]: Counter Stop on Overflow */
#define TPM_CONF_CSOO_MASK (0x1 << TPM_CONF_CSOO_SHIFT)
#define TPM_CONF_CSOT_SHIFT (16) /* Bit[16]: Counter Start on Trigger */
#define TPM_CONF_CSOT_MASK (0x1 << TPM_CONF_CSOT_SHIFT)
#define TPM_CONF_DBGMODE_SHIFT (6) /* Bit[7:6]: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (0x3 << TPM_CONF_DBGMODE_SHIFT)
#define TPM_CONF_DOZEEN_SHIFT (5) /* Bit[5]: Doze Enable */
#define TPM_CONF_DOZEEN_MASK (0x1 << TPM_CONF_DOZEEN_SHIFT)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H */

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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_tstmr.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets */
#define IMX9_TSTMR_LOW_OFFSET 0x0000 /* Timestamp Timer Low */
#define IMX9_TSTMR_HIGH_OFFSET 0x0004 /* Timestamp Timer High */
/* Register macros */
#define IMX9_TSTMR_LOW(n) ((n) + IMX9_TSTMR_LOW_OFFSET) /* Timestamp Timer Low */
#define IMX9_TSTMR_HIGH(n) ((n) + IMX9_TSTMR_HIGH_OFFSET) /* Timestamp Timer High */
/* Field definitions */
/* HIGH register */
#define IMX9_TSTMR_HIGH_VALUE_SHIFT 0 /* Timestamp Timer High */
#define IMX9_TSTMR_HIGH_VALUE_MASK 0xffffff /* Timestamp Timer High */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_allocateheap.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <debug.h>
#include <stdint.h>
#include <sys/types.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/imx9/chip.h>
#include "arm_internal.h"
#include "hardware/imx9_memorymap.h"
#include "imx9_mpuinit.h"
#include "mpu.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Primary RAM: The Linker script positions the system BLOB's .data and
* .bss in some RAM. We refer to that RAM as the primary RAM. It also
* holds the IDLE threads stack and any remaining portion of the primary
* OCRAM is automatically added to the heap. The linker provided address,
* ... .sbss, .ebss, .sdat, etc. ... are expected to lie in the the region
* defined by the OCRAM configuration settings.
*
* Other RAM regions must be selected use configuration options and the
* start and end of those RAM regions must also be provided in the
* configuration. CONFIG_MM_REGIONS must also be set to determined the
* number of regions to be added to the heap.
*
*
* IMX9_ITCM_BASE 0x00000000 256KB M7 ITCM
* IMX9_DTCM_BASE 0x20000000 256KB M7 DTCM
* IMX9_OCRAM_BASE 0x20480000 352KB OCRAM
*/
/* There there then several memory configurations with a one primary memory
* region and up to two additional memory regions which may be OCRAM, DTCM
* external DDR.
*/
#undef IMX9_OCRAM_ASSIGNED
#undef IMX9_DCTM_ASSIGNED
#define _IMX9_OCRAM_BASE IMX9_OCRAM_BASE
/* See linker script */
extern const uint32_t _ram_start[];
extern const uint32_t _ram_size[];
extern const uint32_t _ocram_start[];
extern const uint32_t _ocram_size[];
/* by default DTCM size is 256k
* Can be configured by AON__BLK_CTRL_Secure_AON.M7_CFG (0x444f0124)
*/
#define PRIMARY_RAM_START (uint32_t) _ram_start
#define PRIMARY_RAM_SIZE (uint32_t) _ram_size
#define PRIMARY_RAM_END ((uint32_t)_ram_start + (uint32_t)_ram_size)
#define OCRAM_START (uint32_t) _ocram_start
#define OCRAM_SIZE (uint32_t) _ocram_size
#if CONFIG_MM_REGIONS > 1
/* Pick the first region to add to the heap could be any one of OCRAM, DTCM,
* SDRAM, or SRAM depending upon which are enabled and which has not
* already been assigned as the primary RAM.
*/
#if defined(CONFIG_IMX9_OCRAM_HEAP) && !defined(IMX9_OCRAM_ASSIGNED)
#define REGION1_RAM_START OCRAM_START
#define REGION1_RAM_SIZE OCRAM_SIZE
#define IMX9_OCRAM_ASSIGNED 1
#else
#warning CONFIG_MM_REGIONS > 1 but no available memory region
#endif
#define REGION1_RAM_END (REGION1_RAM_START + REGION1_RAM_SIZE)
#endif
#if CONFIG_MM_REGIONS > 2
#warning CONFIG_MM_REGIONS > 2 but no available memory region
#endif
#if CONFIG_MM_REGIONS > 3
#warning CONFIG_MM_REGIONS > 3 but no available memory region
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* _sbss is the start of the BSS region (see the linker script) _ebss is the
* end of the BSS regions (see the linker script). The idle task stack starts
* at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE
* thread is the thread that the system boots on and, eventually, becomes the
* idle, do nothing task that runs only when there is nothing else to run.
* The heap continues from there until the configured end of memory.
* g_idle_topstack is the beginning of this heap region (not necessarily
* aligned).
*/
const uintptr_t g_idle_topstack
= (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap/up_allocate_kheap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* - For the normal "flat" build, this function returns the size of the
* single heap.
* - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel-
* and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function
* provides the size of the unprotected, user-space heap.
* - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides
* the size of the protected, kernel-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated by an analogous up_allocate_kheap(). A custom version of this
* file is needed if memory protection of the kernel heap is required.
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. (size determined by
* CONFIG_IDLETHREAD_STACKSIZE).
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
#ifdef CONFIG_BUILD_KERNEL
void up_allocate_kheap(void **heap_start, size_t *heap_size)
#else
void up_allocate_heap(void **heap_start, size_t *heap_size)
#endif
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase
= (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = PRIMARY_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the PRIMARY_RAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((PRIMARY_RAM_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = PRIMARY_RAM_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)ubase;
*heap_size = usize;
/* Allow user-mode access to the user heap memory */
imx9_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)g_idle_topstack;
*heap_size = PRIMARY_RAM_END - g_idle_topstack;
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel-
* and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* the kernel-space heap. A custom version of this function is needed if
* memory protection of the kernel heap is required.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase
= (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = PRIMARY_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the CONFIG_RAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((PRIMARY_RAM_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = PRIMARY_RAM_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
/* Add region 1 to the user heap */
kumm_addregion((void *)REGION1_RAM_START, REGION1_RAM_SIZE);
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to region 1 */
imx9_mpu_uheap((uintptr_t)REGION1_RAM_START, REGION1_RAM_SIZE);
#endif
#if CONFIG_MM_REGIONS > 2
/* Add region 2 to the user heap */
kumm_addregion((void *)REGION2_RAM_START, REGION2_RAM_SIZE);
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to region 2 */
imx9_mpu_uheap((uintptr_t)REGION2_RAM_START, REGION2_RAM_SIZE);
#endif
#endif /* CONFIG_MM_REGIONS > 2 */
}
#endif /* CONFIG_MM_REGIONS > 1 */

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/****************************************************************************
* arch/arm/src/imx9/imx9_clockconfig.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include <sys/param.h>
#include <sys/types.h>
#include <arch/board/board.h>
#include "barriers.h"
#include "arm_internal.h"
#include "hardware/imx9_gpc.h"
#include "imx9_clockconfig.h"
#include "imx9_scmi.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The base oscillator frequency is 24MHz */
#define XTAL_FREQ 24000000u
#define ROOT_CLOCK_OFFSET 41
/* Common barrier */
#define mb() \
do \
{ \
ARM_DSB(); \
ARM_ISB(); \
} \
while (0)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_clockconfig
*
* Description:
* Called to initialize the i.IMX9. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imx9_clockconfig(void)
{
/* Keep the system clock running so SYSTICK can wake up the system from
* wfi.
*/
modifyreg32(
IMX9_GPC_CTRL_CMC_MODE_CTRL(IMX9_GPC_CTRL_CM7_BASE),
IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK,
IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET(
IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_STAY_IN_RUN_MODE));
modifyreg32(IMX9_GPC_CTRL_CMC_MISC(IMX9_GPC_CTRL_CM7_BASE),
IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG, 0);
/* Cortex-M33 with SM does PLL initalization */
}
#ifdef CONFIG_IMX9_CLK_OVER_SCMI
int imx9_sm_setrootclock(sm_clock_t *sm_clk)
{
scmi_clock_rate_t rate = /* clang-format off */
{
0, 0
}; /* clang-format on */
uint32_t channel = sm_clk->channel;
uint32_t clock_id = sm_clk->clk_id;
uint32_t pclk_id = sm_clk->pclk_id;
uint32_t div = sm_clk->div;
uint32_t attributes = sm_clk->attributes;
uint32_t oem_config_val = sm_clk->oem_config_val;
uint32_t flags = sm_clk->flags;
uint32_t old_pclk_id = 0; /* parent clock id */
uint64_t src_rate, root_rate;
int32_t status = -1;
if (div == 0)
{
return -EINVAL;
}
status = imx9_scmi_clockparentget(channel, clock_id, &old_pclk_id);
if (status != 0)
{
return status;
}
if (old_pclk_id != pclk_id)
{
status = imx9_scmi_clockparentset(channel, clock_id, pclk_id);
if (status != 0)
{
return status;
}
}
status = imx9_scmi_clockrateget(channel, pclk_id, &rate);
if (status != 0)
{
return status;
}
src_rate = rate.upper;
src_rate = (src_rate << 32);
src_rate |= rate.lower;
root_rate = src_rate / div;
rate.lower = root_rate & SM_CLOCK_RATE_MASK;
rate.upper = (root_rate >> 32) & SM_CLOCK_RATE_MASK;
status = imx9_scmi_clockrateset(channel, clock_id, flags, rate);
if (status != 0)
{
return status;
}
status = imx9_scmi_clockconfigset(channel, clock_id, attributes,
oem_config_val);
if (status != 0)
{
return status;
}
return OK;
}
int imx9_sm_getipfreq(sm_clock_t *sm_clk)
{
scmi_clock_rate_t rate = /* clang-format off */
{
0, 0
}; /* clang-format on */
uint32_t channel = sm_clk->channel;
uint32_t clock_id = sm_clk->clk_id;
uint32_t pclk_id = sm_clk->pclk_id;
int status = 0;
status = imx9_scmi_clockparentget(channel, clock_id, &pclk_id);
if (status < 0)
{
return status;
}
status = imx9_scmi_clockrateget(channel, clock_id, &rate);
if (status < 0)
{
return status;
}
return rate.lower;
}
#endif
int imx9_configure_clock(clock_config_t clk_config, bool enabled)
{
sm_clock_t sm_clk = /* clang-format off */
{
0
}; /* clang-format on */
sm_clk.clk_id = GET_CLOCK_ROOT(clk_config) + ROOT_CLOCK_OFFSET;
sm_clk.pclk_id = GET_CLOCK_ID(clk_config);
sm_clk.channel = SM_PLATFORM_A2P;
sm_clk.div = GET_CLOCK_DIV(clk_config);
if (sm_clk.div == 0)
{
/* Make sure div is always 1 */
sm_clk.div = 1;
}
sm_clk.attributes = SCMI_CLOCK_CONFIG_SET_ENABLE(enabled);
sm_clk.flags = SCMI_CLOCK_RATE_FLAGS_ROUND(SCMI_CLOCK_ROUND_AUTO);
return imx9_sm_setrootclock(&sm_clk);
}
/****************************************************************************
* Name: imx9_get_rootclock
*
* Description:
* This function returns the clock frequency of the specified root
* functional clock.
*
* Input Parameters:
* clkroot - Identifies the peripheral clock of interest
* frequency - The location where the peripheral clock frequency will be
* returned
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure. -ENODEV is returned if the clock is not enabled or is not
* being clocked.
*
****************************************************************************/
int imx9_get_rootclock(int clkroot, uint32_t *frequency)
{
if (clkroot <= CCM_CR_COUNT)
{
uint32_t ret = 0;
sm_clock_t sm_clk = /* clang-format off */
{
0
}; /* clang-format on */
sm_clk.clk_id = (uint32_t)(clkroot + ROOT_CLOCK_OFFSET);
sm_clk.channel = SM_PLATFORM_A2P;
ret = imx9_sm_getipfreq(&sm_clk);
if (ret < 0)
{
return -ENODEV;
}
else
{
*frequency = ret;
return OK;
}
}
return -ENODEV;
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_clockconfig.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "hardware/imx9_clock.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_clockconfig
*
* Description:
* Called to initialize the i.IMX9. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imx9_clockconfig(void);
int imx9_configure_clock(clock_config_t clk_config, bool enabled);
/****************************************************************************
* Name: imx9_get_rootclock
*
* Description:
* This function returns the clock frequency of the specified root
* functional clock.
*
* Input Parameters:
* clkroot - Identifies the peripheral clock of interest
* frequency - The location where the peripheral clock frequency will be
* returned
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure. -ENODEV is returned if the clock is not enabled or is not
* being clocked.
*
****************************************************************************/
int imx9_get_rootclock(int clkroot, uint32_t *frequency);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_edma.h
*
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-FileCopyrightText: 2024 NXP
* SPDX-FileCopyrightText: 2019, 2021, 2023 Gregory Nutt.
* SPDX-FileCopyrightText: 2022 NXP
* SPDX-FileCopyrightText: 2016-2017 NXP
* SPDX-FileCopyrightText: 2015, Freescale Semiconductor, Inc.
* SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
* SPDX-FileContributor: David Sidrane <david.sidrane@nscdg.com>
* SPDX-FileContributor: Peter van der Perk <peter.vanderperk@nxp.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H
#define __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H
/* General Usage:
*
* 1. Allocate a DMA channel
*
* DMACH_HANDLE handle;
* handle = edma_dmach_alloc(dmamux, dchpri);
*
* Where 'dmamux' is the channel DMAMUX configuration register setting and
* 'dchpri' is the channel DCHPRIO priority register setting.
*
* 2. Create the transfer configuration:
*
* struct imx9_edma_xfrconfig_s config;
* config.saddr = ..;
* config.daddr = ..;
* etc.
*
* 3. Setup the transfer in hardware:
*
* int ret;
* ret = imx9_dmach_xfrsetup(handle, &config);
*
* 4. If you are setting up a scatter gather DMA
* (with CONFIG_IMX9_EDMA_NTCD > 0), then repeat steps 2 and 3 for
* each segment of the transfer.
*
* 5. Start the DMA:
*
* ret = imx9_dmach_start(handle, my_callback_func, priv);
*
* Where my_callback_func() is called when the DMA completes or an error
* occurs. 'priv' represents some internal driver state that will be
* provided with the callback.
*
* 6. If you need to stop the DMA and free resources (such as if a timeout
* occurs), then:
*
* i mxrt_dmach_stop(handle);
*
* 7. The callback will be received when the DMA completes (or an error
* occurs). After that, you may free the DMA channel, or re-use it on
* subsequent DMAs.
*
* imx9_dmach_free(handle);
*
* Almost non-invasive debug instrumentation is available. You may call
* imx9_dmasample() to save the current state of the eDMA registers at
* any given point in time. At some later, postmortem analysis, you can
* dump the content of the buffered registers with imx9_dmadump().
* imx9_dmasample() is also available for monitoring DMA progress.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration flags.
*
* REVISIT: Many missing options that should be represented as flags:
* 1. Bandwidth
* 2. Source/Destination modulo
*/
#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */
#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT)
# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */
# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */
# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */
#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */
#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT)
# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */
# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */
# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */
#define EDMA_CONFIG_INTHALF (1 << 4) /* Bits 4: Int on HALF */
#define EDMA_CONFIG_INTMAJOR (1 << 5) /* Bits 5: Int on all Major completion
* Default is only on last completion
* if using scatter gather
*/
/****************************************************************************
* Public Types
****************************************************************************/
typedef void *DMACH_HANDLE;
typedef void (*edma_callback_t)(DMACH_HANDLE handle,
void *arg, bool done, int result);
/* eDMA transfer type */
enum imx9_edma_xfrtype_e
{
EDMA_MEM2MEM = 0, /* Transfer from memory to memory */
EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */
EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */
};
/* eDMA transfer sises */
enum imx9_edma_sizes_e
{
EDMA_8BIT = 0, /* Transfer data size 8 */
EDMA_16BIT = 1, /* Transfer data size 16 */
EDMA_32BIT = 2, /* Transfer data size 32 */
EDMA_64BIT = 3, /* Transfer data size 64 */
EDMA_16BYTE = 4, /* Transfer data size 16-byte */
EDMA_32BYTE = 5, /* Transfer data size 32-byte */
EDMA_64BYTE = 6, /* Transfer data size 64-byte */
};
/* This structure holds the source/destination transfer attribute
* configuration.
*/
struct imx9_edma_xfrconfig_s
{
uintptr_t saddr; /* Source data address. */
uintptr_t daddr; /* Destination data address. */
int16_t soff; /* Sign-extended offset for current source address. */
int16_t doff; /* Sign-extended offset for current destination address. */
uint16_t iter; /* Major loop iteration count. */
uint8_t flags; /* See EDMA_CONFIG_* definitions */
uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */
uint8_t dsize; /* Destination data transfer size. */
#ifdef CONFIG_IMX9_EDMA_EMLIM
uint16_t nbytes; /* Bytes to transfer in a minor loop */
#else
uint32_t nbytes; /* Bytes to transfer in a minor loop */
#endif
#ifdef CONFIG_IMX9_EDMA_MOD
uint8_t smod;
uint8_t dmod;
#endif
#ifdef CONFIG_IMX9_EDMA_BWC
uint8_t bwc;
#endif
#ifdef CONFIG_IMX9_EDMA_ELINK
DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */
#endif
};
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA
* is selected
*/
#ifdef CONFIG_DEBUG_DMA
struct imx9_dmaregs_s
{
uint8_t chan; /* Sampled channel */
/* eDMA Global Registers */
uint32_t cr; /* Control */
uint32_t es; /* Error Status */
uint32_t req; /* Interrupt Request */
uint32_t hrs; /* Hardware Request Status */
/* eDMA Channel registers */
uint8_t dchpri; /* Channel priority */
/* eDMA TCD */
uint32_t saddr; /* TCD Source Address */
uint16_t soff; /* TCD Signed Source Address Offset */
uint16_t attr; /* TCD Transfer Attributes */
uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* TCD Last Source Address Adjustment */
uint32_t daddr; /* TCD Destination Address */
uint16_t doff; /* TCD Signed Destination Address Offset */
uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* TCD Control and Status */
uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */
/* DMAMUX registers */
uint32_t dmamux; /* Channel configuration */
};
#endif /* CONFIG_DEBUG_DMA */
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_dmach_alloc
*
* Allocate a DMA channel. This function sets aside a DMA channel,
* initializes the DMAMUX for the channel, then gives the caller exclusive
* access to the DMA channel.
*
* Input Parameters:
* dmamux - DMAMUX configuration see DMAMUX channel configuration register
* bit-field definitions in hardware/imx9_dmamux.h.
* Settings include:
*
* DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required)
* DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional)
* DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required)
*
* A value of zero will disable the DMAMUX channel.
* dchpri - DCHPRI channel priority configuration. See DCHPRI channel
* configuration register bit-field definitions in
* hardware/imx9_edma.h. Meaningful settings include:
*
* EDMA_DCHPRI_CHPRI Channel Arbitration Priority
* DCHPRI_DPA Disable Preempt Ability
* DCHPRI_ECP Enable Channel Preemption
*
* The power-on default, 0x05, is a reasonable choice.
*
* Returned Value:
* If a DMA channel is available, this function returns a non-NULL, void*
* DMA channel handle. NULL is returned on any failure.
*
****************************************************************************/
DMACH_HANDLE imx9_dmach_alloc(uint16_t dmamux, uint8_t dchpri);
/****************************************************************************
* Name: imx9_dmach_free
*
* Description:
* Release a DMA channel.
* NOTE: The 'handle' used in this argument must NEVER be used again
* until imx9_dmach_alloc() is called again to re-gain a valid handle.
*
* Returned Value:
* None
*
****************************************************************************/
void imx9_dmach_free(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmach_xfrsetup
*
* Description:
* This function adds the eDMA transfer to the DMA sequence. The request
* is setup according to the content of the transfer configuration
* structure. For "normal" DMA, imx9_dmach_xfrsetup is called only
* once.
* Scatter/gather DMA is accomplished by calling this function repeatedly,
* once for each transfer in the sequence. Scatter/gather DMA processing
* is enabled automatically when the second transfer configuration is
* received.
*
* This function may be called multiple times to handle multiple,
* discontinuous transfers (scatter-gather)
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
* config - A DMA transfer configuration instance, populated by the
* The content of 'config' describes the transfer
*
* Returned Value
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
****************************************************************************/
int imx9_dmach_xfrsetup(DMACH_HANDLE handle,
const struct imx9_edma_xfrconfig_s *config);
/****************************************************************************
* Name: imx9_dmach_start
*
* Description:
* Start the DMA transfer by enabling the channel DMA request.
* This function should be called after the final call to
* imx9_dmasetup() in order to avoid race conditions.
*
* At the conclusion of each major DMA loop, a callback to the
* user-provided function is made: |For "normal" DMAs, this will
* correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple
* interrupts will be generated with the final being the DONE interrupt.
*
* At the conclusion of the DMA, the DMA channel is reset, all TCDs are
* freed, and the callback function is called with the the success/fail
* result of the DMA.
*
* NOTE:
* On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary
* to invalidate the destination memory. That is not done automatically
* by the DMA module. Invalidation of the destination memory regions is
* the responsibility of the caller.
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
* callback - The callback to be invoked when the DMA is completes or is
* aborted.
* arg - An argument that accompanies the callback
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
****************************************************************************/
int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback,
void *arg);
/****************************************************************************
* Name: imx9_dmach_stop
*
* Description:
* Cancel the DMA. After imx9_dmach_stop() is called, the DMA channel
* is reset, all TCDs are freed, and imx9_dmarx/txsetup() must be called
* before imx9_dmach_start() can be called again
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
*
* Returned Value:
* None.
*
****************************************************************************/
void imx9_dmach_stop(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmach_getcount
*
* Description:
* This function checks the TCD (Task Control Descriptor) status for a
* specified eDMA channel and returns the the number of major loop counts
* that have not finished.
*
* NOTES:
* 1. This function can only be used to get unfinished major loop count of
* transfer without the next TCD, or it might be inaccuracy.
* 2. The unfinished/remaining transfer bytes cannot be obtained directly
* from registers while the channel is running.
*
* Because to calculate the remaining bytes, the initial NBYTES configured
* in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not
* support getting it while a channel is active. In another words, the
* NBYTES value reading is always the actual (decrementing) NBYTES value
* the dma_engine is working with while a channel is running.
* Consequently, to get the remaining transfer bytes, a software-saved
* initial value of NBYTES (for example copied before enabling the channel)
* is needed. The formula to calculate it is shown below:
*
* RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
*
* Returned Value:
* Major loop count which has not been transferred yet for the current TCD.
*
****************************************************************************/
unsigned int imx9_dmach_getcount(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmach_idle
*
* Description:
* This function checks if the dma is idle
*
* Returned Value:
* 0 - if idle
* !0 - not
*
****************************************************************************/
unsigned int imx9_dmach_idle(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmasample
*
* Description:
* Sample DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs);
#else
# define imx9_dmasample(handle,regs)
#endif
/****************************************************************************
* Name: imx9_dmadump
*
* Description:
* Dump previously sampled DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void imx9_dmadump(const struct imx9_dmaregs_s *regs, const char *msg);
#else
# define imx9_dmadump(handle,regs,msg)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_flexcan.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H
#define __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_flexcan.h"
#ifdef CONFIG_IMX9_FLEXCAN
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: arm_caninitialize
*
* Description:
* Initialize the enabled CAN device interfaces. If there are more
* different network devices in the chip, then board-specific logic will
* have to provide this function to determine which, if any, network
* devices should be initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
* Called very early in the initialization sequence.
*
****************************************************************************/
#ifdef CONFIG_NETDEV_LATEINIT
int imx9_caninitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_IMX9_FLEXCAN */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_gpio.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <imx9_gpiobase.c>
#include "chip.h"
#include "arm_internal.h"
#include "imx9_iomuxc.h"
#include "imx9_gpio.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_gpio_dirout
****************************************************************************/
static inline void imx9_gpio_dirout(uint32_t port, uint32_t pin)
{
uint32_t regval = getreg32(IMX9_GPIO_PDDR(port));
regval |= GPIO_PIN(pin);
putreg32(regval, IMX9_GPIO_PDDR(port));
}
/****************************************************************************
* Name: imx9_gpio_dirin
****************************************************************************/
static inline void imx9_gpio_dirin(uint32_t port, uint32_t pin)
{
uint32_t regval = getreg32(IMX9_GPIO_PDDR(port));
regval &= ~GPIO_PIN(pin);
putreg32(regval, IMX9_GPIO_PDDR(port));
}
/****************************************************************************
* Name: imx9_gpio_setoutput
****************************************************************************/
static void imx9_gpio_setoutput(uint32_t port, uint32_t pin, bool value)
{
uintptr_t regaddr = IMX9_GPIO_PDOR(port);
uint32_t regval;
regval = getreg32(regaddr);
if (value)
{
regval |= GPIO_PIN(pin);
}
else
{
regval &= ~GPIO_PIN(pin);
}
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: imx9_gpio_getpin_status
****************************************************************************/
static inline bool imx9_gpio_get_pinstatus(uint32_t port, uint32_t pin)
{
uintptr_t regaddr = IMX9_GPIO_PSOR(port);
uint32_t regval;
regval = getreg32(regaddr);
return ((regval & GPIO_PIN(pin)) != 0);
}
/****************************************************************************
* Name: imx9_gpio_getinput
****************************************************************************/
static inline bool imx9_gpio_getinput(uint32_t port, uint32_t pin)
{
uintptr_t regaddr = IMX9_GPIO_PDIR(port);
uint32_t regval;
regval = getreg32(regaddr);
return ((regval & GPIO_PIN(pin)) != 0);
}
/****************************************************************************
* Name: imx9_gpio_configinput
****************************************************************************/
static int imx9_gpio_configinput(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
/* Configure pin as in input */
imx9_gpio_dirin(port, pin);
return OK;
}
/****************************************************************************
* Name: imx9_gpio_configoutput
****************************************************************************/
static inline int imx9_gpio_configoutput(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
bool value = ((pinset & GPIO_OUTPUT_ONE) != 0);
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
/* Set the output value */
imx9_gpio_setoutput(port, pin, value);
/* Convert the configured input GPIO to an output */
imx9_gpio_dirout(port, pin);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_config_gpio
*
* Description:
* Configure a GPIO pin based on pin-encoded description of the pin.
*
****************************************************************************/
int imx9_config_gpio(gpio_pinset_t pinset)
{
irqstate_t flags;
int ret;
/* Configure the pin as an input initially to avoid any spurious outputs */
flags = enter_critical_section();
/* Configure based upon the pin mode */
switch (pinset & GPIO_MODE_MASK)
{
case GPIO_INPUT:
{
/* Configure the pin as a GPIO input */
ret = imx9_gpio_configinput(pinset);
}
break;
case GPIO_OUTPUT:
{
/* First configure the pin as a GPIO input to avoid output
* glitches.
*/
ret = imx9_gpio_configinput(pinset);
if (ret >= 0)
{
/* Convert the input to an output */
ret = imx9_gpio_configoutput(pinset);
}
}
break;
#ifdef CONFIG_IMX9_GPIO_IRQ
case GPIO_INTERRUPT:
{
/* Configure the pin as a GPIO input */
ret = imx9_gpio_configinput(pinset);
if (ret == OK)
{
ret = imx9_gpioirq_configure(pinset);
}
}
break;
#endif
default:
ret = -EINVAL;
break;
}
leave_critical_section(flags);
return ret;
}
/****************************************************************************
* Name: imx9_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void imx9_gpio_write(gpio_pinset_t pinset, bool value)
{
irqstate_t flags;
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
flags = enter_critical_section();
imx9_gpio_setoutput(port, pin, value);
leave_critical_section(flags);
}
/****************************************************************************
* Name: imx9_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool imx9_gpio_read(gpio_pinset_t pinset)
{
irqstate_t flags;
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
bool value;
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
flags = enter_critical_section();
if ((pinset & (GPIO_OUTPUT)) == (GPIO_OUTPUT))
{
value = imx9_gpio_get_pinstatus(port, pin);
}
else
{
value = imx9_gpio_getinput(port, pin);
}
leave_critical_section(flags);
return value;
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H
#define __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/imx9_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO pinset is a 16-bit word used to configure the GPIO settings. The
* encoding is as follows...
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* ENCODING MMVX BEEG GGGP PPPP
* GPIO INPUT 00.. BEEG GGGP PPPP
* INT INPUT 11.. BEEG GGGP PPPP
* GPIO OUTPUT 01V. ...G GGGP PPPP
*/
/* Input/Output Selection:
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* ENCODING MM.. .... .... ....
*/
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: Pin mode */
#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */
# define GPIO_INTERRUPT (2 << GPIO_MODE_SHIFT) /* Interrupt input */
/* Initial Output Value:
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* GPIO OUTPUT 01V. .... .... ....
*/
#define GPIO_OUTPUT_SHIFT (13) /* Bit 13: Initial output */
#define GPIO_OUTPUT_MASK (0x1 << GPIO_OUTPUT_SHIFT)
# define GPIO_OUTPUT_ZERO (0 << GPIO_OUTPUT_SHIFT) /* Bit 29: 0=Initial output is low */
# define GPIO_OUTPUT_ONE (1 << GPIO_OUTPUT_SHIFT) /* Bit 29: 1=Initial output is high */
/* Interrupt on both edges configuration
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* INT INPUT 11.. B... .... ....
*/
#define GPIO_INTBOTHCFG_SHIFT (11) /* Bit 11: Interrupt both edges configuration */
#define GPIO_INTBOTHCFG_MASK (1 << GPIO_INTBOTHCFG_SHIFT)
# define GPIO_INTBOTH_EDGES (1 << GPIO_INTBOTHCFG_SHIFT)
/* Interrupt edge/level configuration
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* INT INPUT 11.. .EE. .... ....
*/
#define GPIO_INTCFG_SHIFT (9) /* Bits 9-10: Interrupt edge/level configuration */
#define GPIO_INTCFG_MASK (0x3 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_LOWLEVEL (0 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_HIGHLEVEL (1 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_RISINGEDGE (2 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_FALLINGEDGE (3 << GPIO_INTCFG_SHIFT)
/* GPIO Port Number
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* GPIO IN/OUT .... ...G GGG. ....
*/
#define GPIO_PORT_SHIFT (5) /* Bits 5-8: GPIO port index */
#define GPIO_PORT_MASK (0xf << GPIO_PORT_SHIFT)
# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */
# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */
# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */
# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */
# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */
# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */
# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */
# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */
# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */
# define GPIO_PORT10 (GPIO10 << GPIO_PORT_SHIFT) /* GPIO10 */
# define GPIO_PORT11 (GPIO11 << GPIO_PORT_SHIFT) /* GPIO11 */
# define GPIO_PORT12 (GPIO12 << GPIO_PORT_SHIFT) /* GPIO12 */
# define GPIO_PORT13 (GPIO13 << GPIO_PORT_SHIFT) /* GPIO13 */
/* GPIO Pin Number:
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* GPIO IN/OUT .... .... ...P PPPP
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO pin number */
#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT)
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */
/* Port access via global LUT */
#define IMX9_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */
#define IMX9_GPIO_VERID(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_VERID_OFFSET)
#define IMX9_GPIO_PARAM(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PARAM_OFFSET)
#define IMX9_GPIO_LOCK(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_LOCK_OFFSET)
#define IMX9_GPIO_PCNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNS_OFFSET)
#define IMX9_GPIO_ICNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNS_OFFSET)
#define IMX9_GPIO_PCNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNP_OFFSET)
#define IMX9_GPIO_ICNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNP_OFFSET)
#define IMX9_GPIO_PDOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDOR_OFFSET)
#define IMX9_GPIO_PSOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PSOR_OFFSET)
#define IMX9_GPIO_PCOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCOR_OFFSET)
#define IMX9_GPIO_PTOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PTOR_OFFSET)
#define IMX9_GPIO_PDIR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDIR_OFFSET)
#define IMX9_GPIO_PDDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDDR_OFFSET)
#define IMX9_GPIO_PIDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PIDR_OFFSET)
#define IMX9_GPIO_GICLR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICLR_OFFSET)
#define IMX9_GPIO_GICHR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICHR_OFFSET)
/* Interrupt status flags, these have two channels. Channel is selected by
* setting / clearing ICRN.IRQS bit.
*/
#define IMX9_GPIO_ISFR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR0_OFFSET)
#define IMX9_GPIO_ISFR1(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR1_OFFSET)
/* GPIO PIN[0...31] and ICR[0...31] */
#define IMX9_GPIO_P0DR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_P0DR_OFFSET)
#define IMX9_GPIO_PNDR(n, p) (IMX9_GPIO_P0DR(n) + ((p) * 0x4))
#define IMX9_GPIO_ICR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICR0_OFFSET)
#define IMX9_GPIO_ICRN(n, p) (IMX9_GPIO_ICR0(n) + ((p) * 0x4))
/****************************************************************************
* Public Types
****************************************************************************/
/* The smallest integer type that can hold the GPIO encoding */
typedef uint16_t gpio_pinset_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base
* addresses
*/
EXTERN const uintptr_t g_gpio_base[];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_gpioirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
void imx9_gpioirq_initialize(void);
#else
# define imx9_gpioirq_initialize()
#endif
/****************************************************************************
* Name: imx9_config_gpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int imx9_config_gpio(gpio_pinset_t pinset);
/****************************************************************************
* Name: imx9_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void imx9_gpio_write(gpio_pinset_t pinset, bool value);
/****************************************************************************
* Name: imx9_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool imx9_gpio_read(gpio_pinset_t pinset);
/****************************************************************************
* Name: imx9_gpioirq_attach
*
* Description:
* Attach a pin interrupt handler.
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg);
#else
#define imx9_gpioirq_attach(pinset, isr, arg) 0
#endif
/****************************************************************************
* Name: imx9_gpioirq_configure
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_configure(gpio_pinset_t pinset);
#else
# define imx9_gpioirq_configure(pinset) 0
#endif
/****************************************************************************
* Name: imx9_gpioirq_enable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_enable(gpio_pinset_t pinset);
#else
# define imx9_gpioirq_enable(pinset) 0
#endif
/****************************************************************************
* Name: imx9_gpioirq_disable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_disable(gpio_pinset_t pinset);
#else
# define imx9_gpioirq_disable(pinset) 0
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_gpiobase.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "imx9_gpio.h"
/****************************************************************************
* Public Data
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_IMX93)
/* Base address for the GPIO memory mapped registers */
const uintptr_t g_gpio_base[] =
{
IMX9_GPIO1_BASE,
IMX9_GPIO2_BASE,
IMX9_GPIO3_BASE,
IMX9_GPIO4_BASE,
};
#elif defined(CONFIG_ARCH_CHIP_IMX9_CORTEX_M)
/* Base address for the GPIO memory mapped registers */
const uintptr_t g_gpio_base[] =
{
IMX9_GPIO1_BASE,
IMX9_GPIO2_BASE,
IMX9_GPIO3_BASE,
IMX9_GPIO4_BASE,
};
#else
# error Unrecognized i.MX9 architecture
#endif
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/imx9/imx9_gpioirq.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "imx9_gpio.h"
#ifdef CONFIG_IMX9_GPIO_IRQ
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
struct imx9_portisr_s
{
struct
{
xcpt_t isr; /* The interrupt service routine */
void *arg; /* Argument passed to it */
}
pins[IMX9_GPIO_NPINS];
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct imx9_portisr_s g_isrtab[IMX9_GPIO_NPORTS];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_gpio_interrupt
*
* Description:
* GPIO interrupt handlers. iMX9 has two interrupt sources for each pin,
* the NuttX driver uses source 0.
*
****************************************************************************/
static int imx9_gpio_interrupt(int irq, void *context, void *arg)
{
uint32_t port = (uint32_t)((uintptr_t)arg) >> GPIO_PORT_SHIFT;
uint32_t status;
uint32_t pin;
uint32_t regaddr;
/* Get the pending interrupt indications */
regaddr = IMX9_GPIO_ISFR0(port);
status = getreg32(regaddr);
/* Decode the pending interrupts */
for (pin = 0; pin < 32 && status != 0; pin++)
{
/* Is the IRQ associated with this pin pending? */
uint32_t mask = (1 << pin);
if ((status & mask) != 0)
{
struct imx9_portisr_s *isrtab;
/* Yes, clear the status bit and dispatch the interrupt */
putreg32(mask, regaddr);
status &= ~mask;
/* Get the interrupt table for this port */
isrtab = &g_isrtab[port];
if (isrtab->pins[pin].isr != NULL)
{
/* Run the user handler with the user's argument */
isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg);
}
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_gpioirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
void imx9_gpioirq_initialize(void)
{
/* Do not loop over all GPIOs on IMX95 because some IOs may not be
* accessible depending on the system managers configuration
*/
#ifndef CONFIG_ARCH_CHIP_IMX95_M7
uint32_t port;
uint32_t pin;
/* Disable all GPIO interrupts at the source */
for (port = 0; port < IMX9_GPIO_NPORTS; port++)
{
for (pin = 0; pin < IMX9_GPIO_NPINS; pin++)
{
/* Reset the interrupt configuration, disabling the interrupt */
putreg32(0, IMX9_GPIO_ICRN(port, pin));
}
}
#endif /* CONFIG_ARCH_CHIP_IMX95_M7 */
/* Disable all GPIO interrupts */
up_disable_irq(IMX9_IRQ_GPIO1_0);
up_disable_irq(IMX9_IRQ_GPIO1_1);
up_disable_irq(IMX9_IRQ_GPIO2_0);
up_disable_irq(IMX9_IRQ_GPIO2_1);
up_disable_irq(IMX9_IRQ_GPIO3_0);
up_disable_irq(IMX9_IRQ_GPIO3_1);
up_disable_irq(IMX9_IRQ_GPIO4_0);
up_disable_irq(IMX9_IRQ_GPIO4_1);
/* Attach the common GPIO interrupt handler and enable the interrupt */
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO1_0,
imx9_gpio_interrupt, (void *)GPIO_PORT1));
up_enable_irq(IMX9_IRQ_GPIO1_0);
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO2_0,
imx9_gpio_interrupt, (void *)GPIO_PORT2));
up_enable_irq(IMX9_IRQ_GPIO2_0);
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO3_0,
imx9_gpio_interrupt, (void *)GPIO_PORT3));
up_enable_irq(IMX9_IRQ_GPIO3_0);
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO4_0,
imx9_gpio_interrupt, (void *)GPIO_PORT4));
up_enable_irq(IMX9_IRQ_GPIO4_0);
}
/****************************************************************************
* Name: imx9_gpioirq_attach
*
* Description:
* Attach a pin interrupt handler.
*
****************************************************************************/
int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Atomically change the handler */
irqstate_t flags = enter_critical_section();
g_isrtab[port].pins[pin].isr = isr;
g_isrtab[port].pins[pin].arg = arg;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: imx9_gpioirq_configure
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
****************************************************************************/
int imx9_gpioirq_configure(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Nothing much to do here, just reset the IRQ config */
putreg32(0, IMX9_GPIO_ICRN(port, pin));
return OK;
}
/****************************************************************************
* Name: imx9_gpioirq_enable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
int imx9_gpioirq_enable(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uint32_t both = (pinset & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT;
uint32_t icr = (pinset & GPIO_INTCFG_MASK);
uint32_t regval;
uintptr_t regaddr;
/* Perform RMW to the specific pin */
regaddr = IMX9_GPIO_ICRN(port, pin);
regval = getreg32(regaddr);
regval &= ~IMX9_GPIO_ICRN_MASK;
if (both)
{
regval |= IMX9_GPIO_ICRN_BOTH;
}
else if (icr == GPIO_INT_LOWLEVEL)
{
regval |= IMX9_GPIO_ICRN_ZERO;
}
else if (icr == GPIO_INT_HIGHLEVEL)
{
regval |= IMX9_GPIO_ICRN_ONE;
}
else if (icr == GPIO_INT_RISINGEDGE)
{
regval |= IMX9_GPIO_ICRN_RISING;
}
else /* GPIO_INT_FALLINGEDGE */
{
regval |= IMX9_GPIO_ICRN_FALLING;
}
putreg32(regval, regaddr);
return OK;
}
/****************************************************************************
* Name: imx9_gpioirq_disable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
int imx9_gpioirq_disable(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uint32_t regval;
uintptr_t regaddr;
/* Perform RMW to the specific pin */
regaddr = IMX9_GPIO_ICRN(port, pin);
regval = getreg32(regaddr);
regval &= ~IMX9_GPIO_ICRN_MASK;
putreg32(regval, regaddr);
return OK;
}
#endif /* CONFIG_IMX9_GPIO_IRQ */

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/****************************************************************************
* arch/arm/src/imx9/imx9_idle.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
pwrinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
imx9_pmstop(true);
break;
case PM_SLEEP:
imx9_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}

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arch/arm/src/imx9/imx9_iomuxc.c Normal file
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/****************************************************************************
* arch/arm/src/imx9/imx9_iomuxc.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include "arm_internal.h"
#include "hardware/imx9_memorymap.h"
#include "imx9_iomuxc.h"
#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI
#include "imx9_scmi.h"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This function writes the encoded pad configuration to the Pad Control
* register.
*
* Input Parameters:
* cfg - The IOMUX configuration
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI
/* Sets the IOMUXC pin mux mode.
*/
void imx9_sm_iomucx_configure(sm_pinctrl_t *sm_pinctrl)
{
scmi_pin_config_t configs[4];
uint32_t num_configs = 0;
uint32_t channel = sm_pinctrl->channel;
uint32_t mux_register = sm_pinctrl->mux_register;
uint32_t mux_mode = sm_pinctrl->mux_mode;
uint32_t input_register = sm_pinctrl->input_register;
uint32_t input_daisy = sm_pinctrl->input_daisy;
uint32_t input_on_field = sm_pinctrl->input_on_field;
uint32_t config_register = sm_pinctrl->config_register;
uint32_t config_value = sm_pinctrl->config_value;
if (mux_register)
{
configs[num_configs].type = SCMI_PINCTRL_TYPE_MUX;
configs[num_configs].value = SM_PLATFORM_PINCTRL_MUX_MODE(mux_mode)
| SM_PLATFORM_PINCTRL_SION(
input_on_field);
num_configs++;
}
if (input_register & 0xffff)
{
configs[num_configs].type = SCMI_PINCTRL_TYPE_DAISY_ID;
configs[num_configs].value =
(input_register - SM_PLATFORM_PINCTRL_DAISYREG_OFF) / 4;
num_configs++;
configs[num_configs].type = SCMI_PINCTRL_TYPE_DAISY_CFG;
configs[num_configs].value = input_daisy;
num_configs++;
}
if (config_register)
{
configs[num_configs].type = SCMI_PINCTRL_TYPE_CONFIG;
configs[num_configs].value = config_value;
num_configs++;
}
if (mux_register || input_register)
{
uint32_t attributes = SCMI_PINCTRL_SET_ATTR_SELECTOR(
SCMI_PINCTRL_SEL_PIN)
| SCMI_PINCTRL_SET_ATTR_NUM_CONFIGS(
num_configs);
imx9_scmi_pinctrlconfigset(
channel, (mux_register - SM_PLATFORM_PINCTRL_MUXREG_OFF) / 4,
attributes, configs);
}
}
#endif
int imx9_iomux_configure(iomux_cfg_t cfg)
{
#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI
sm_pinctrl_t sm_pinctrl =
{
0
};
sm_pinctrl.channel = SM_PLATFORM_A2P;
sm_pinctrl.mux_register = IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff;
sm_pinctrl.mux_mode = cfg.padcfg.mode;
sm_pinctrl.input_register = IMX9_IOMUXC_BASE + cfg.padcfg.dsyregoff;
sm_pinctrl.input_daisy = cfg.padcfg.dsy;
sm_pinctrl.config_register = IMX9_IOMUXC_BASE + cfg.padcfg.padregoff;
sm_pinctrl.config_value = cfg.pad;
sm_pinctrl.input_on_field = cfg.sion;
imx9_sm_iomucx_configure(&sm_pinctrl);
#else
if (!cfg.padcfg.ctlregoff)
{
return -EINVAL;
}
putreg32(cfg.padcfg.mode | (cfg.sion << IOMUXC_MUX_SION_SHIFT),
IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff);
if (cfg.padcfg.dsyregoff)
{
putreg32(cfg.padcfg.dsy, IMX9_IOMUXC_BASE + cfg.padcfg.dsyregoff);
}
if (cfg.padcfg.padregoff)
{
putreg32(cfg.pad << IOMUXC_PAD_CONFIG_SHIFT,
IMX9_IOMUXC_BASE + cfg.padcfg.padregoff);
}
return OK;
#endif
}
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This can be used to forcibly set a pad to GPIO mode. This overrides and
* disconnects any peripheral using the pin.
*
* Input Parameters:
* cfg - The IOMUX configuration.
* sion - if true; sets SION, otherwise clears it.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion)
{
uint32_t reg_sion;
if (!cfg.padcfg.ctlregoff)
{
return -EINVAL;
}
/* Set sion if requested to do so */
reg_sion = sion ? IOMUXC_MUX_SION_ON : 0;
/* Based on pad number, either ALT0/ALT5 sets the pad as GPIO */
if ((cfg.padcfg.ctlregoff >= IOMUXC_MUX_CTL_GPIO_IO00_OFFSET)
&& (cfg.padcfg.ctlregoff <= IOMUXC_MUX_CTL_GPIO_IO37_OFFSET))
{
putreg32(IOMUXC_MUX_MODE_ALT0 | reg_sion,
IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff);
}
else
{
putreg32(IOMUXC_MUX_MODE_ALT5 | reg_sion,
IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff);
}
return OK;
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_iomuxc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H
#define __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "hardware/imx9_iomuxc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IOMUXC_PAD_CONFIG_SHIFT 1
#define IOMUX_PADCFG(_ctlregoff, _mode, _dsyregoff, _dsy, _padregoff) \
{ \
.ctlregoff = (_ctlregoff), \
.padregoff = (_padregoff), \
.dsyregoff = (_dsyregoff), \
.mode = (_mode), \
.dsy = (_dsy), \
}
#define IOMUX_CFG(_padcfg, _pad, _sion) \
(iomux_cfg_t) \
{ \
.padcfg = _padcfg, \
.pad = (_pad) >> IOMUXC_PAD_CONFIG_SHIFT, \
.sion = (_sion) >> IOMUXC_MUX_SION_SHIFT, \
}
/****************************************************************************
* Public Types
****************************************************************************/
/* Information for the pad alternate function */
struct iomux_padcfg_s
{
/* Register offsets for PAD
* ALT(mode) configuration for ctlreg
* input daisy(dsy) configuration for dsyreg
*/
uint16_t mode : 3;
uint16_t ctlregoff : 13;
uint16_t padregoff : 16;
uint16_t dsy : 3;
uint16_t dsyregoff : 13;
};
struct iomux_cfg_s
{
struct iomux_padcfg_s padcfg;
/* Register values */
uint32_t pad :31;
uint32_t sion : 1;
};
typedef struct iomux_cfg_s iomux_cfg_t;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This function writes the encoded pad configuration to the Pad Control
* register.
*
* Input Parameters:
* cfg - The IOMUX configuration
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int imx9_iomux_configure(iomux_cfg_t cfg);
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This can be used to forcibly set a pad to GPIO mode. This overrides and
* disconnects any peripheral using the pin.
*
* Input Parameters:
* cfg - The IOMUX configuration.
* sion - if true; sets SION, otherwise clears it.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H */

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arch/arm/src/imx9/imx9_irq.c Normal file
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/****************************************************************************
* arch/arm/src/imx9/imx9_irq.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
#include "nvic.h"
#include "ram_vectors.h"
#include "arm_internal.h"
#ifdef CONFIG_IMX9_GPIO_IRQ
# include "imx9_gpio.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void imx9_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE),
getreg32(NVIC_IRQ96_127_ENABLE));
#if IMX9_IRQ_NEXTINT > 128
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ128_159_ENABLE),
getreg32(NVIC_IRQ160_191_ENABLE),
getreg32(NVIC_IRQ192_223_ENABLE),
getreg32(NVIC_IRQ224_239_ENABLE));
#endif
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
#if IMX9_IRQ_NEXTINT > 16
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 32
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 48
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 64
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY),
getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY),
getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 80
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY),
getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY),
getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 96
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY),
getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY),
getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 112
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY),
getreg32(NVIC_IRQ116_119_PRIORITY),
getreg32(NVIC_IRQ120_123_PRIORITY),
getreg32(NVIC_IRQ124_127_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 128
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ128_131_PRIORITY),
getreg32(NVIC_IRQ132_135_PRIORITY),
getreg32(NVIC_IRQ136_139_PRIORITY),
getreg32(NVIC_IRQ140_143_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 144
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ144_147_PRIORITY),
getreg32(NVIC_IRQ148_151_PRIORITY),
getreg32(NVIC_IRQ152_155_PRIORITY),
getreg32(NVIC_IRQ156_159_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 160
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ160_163_PRIORITY),
getreg32(NVIC_IRQ164_167_PRIORITY),
getreg32(NVIC_IRQ168_171_PRIORITY),
getreg32(NVIC_IRQ172_175_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 176
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ176_179_PRIORITY),
getreg32(NVIC_IRQ180_183_PRIORITY),
getreg32(NVIC_IRQ184_187_PRIORITY),
getreg32(NVIC_IRQ188_191_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 192
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ192_195_PRIORITY),
getreg32(NVIC_IRQ196_199_PRIORITY),
getreg32(NVIC_IRQ200_203_PRIORITY),
getreg32(NVIC_IRQ204_207_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 208
irqinfo(" %08x %08x %08x\n",
getreg32(NVIC_IRQ208_211_PRIORITY),
getreg32(NVIC_IRQ212_215_PRIORITY),
getreg32(NVIC_IRQ216_219_PRIORITY));
#endif
#if IMX9_IRQ_NEXTINT > 218
# warning Missing logic
#endif
leave_critical_section(flags);
}
#else
# define imx9_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: imx9_nmi, imx9_pendsv, imx9_pendsv, imx9_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int imx9_nmi(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int imx9_pendsv(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int imx9_reserved(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: imx9_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
static inline void imx9_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
/****************************************************************************
* Name: imx9_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int imx9_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
unsigned int extint = irq - IMX9_IRQ_EXTINT;
DEBUGASSERT(irq >= IMX9_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= IMX9_IRQ_EXTINT)
{
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#if IMX9_IRQ_NEXTINT > 32
if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 64
if (extint < 96)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 96
if (extint < 128)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 128
if (extint < 160)
{
*regaddr = (NVIC_IRQ128_159_ENABLE + offset);
*bit = 1 << (extint - 128);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 160
if (extint < 192)
{
*regaddr = (NVIC_IRQ160_191_ENABLE + offset);
*bit = 1 << (extint - 160);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 192
if (extint < 219)
{
*regaddr = (NVIC_IRQ192_223_ENABLE + offset);
*bit = 1 << (extint - 192);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 218
# error Missing logic
#endif
{
return ERROR; /* Invalid interrupt */
}
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == IMX9_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == IMX9_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == IMX9_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == IMX9_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uintptr_t regaddr;
int nintlines;
int i;
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
* lines that the NVIC supports, defined in groups of 32. That is,
* the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
*
* 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
* 1 -> 64 " " " ", 2 enable registers, 16 priority registers
* 2 -> 96 " " " ", 3 enable registers, 24 priority registers
* ...
*/
nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
/* Disable all interrupts. There are nintlines interrupt enable
* registers.
*/
for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0;
i--, regaddr += 4)
{
putreg32(0xffffffff, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
arm_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* Now set all of the interrupt lines to the default priority. There are
* nintlines * 8 priority registers.
*/
for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
i > 0;
i--, regaddr += 4)
{
putreg32(DEFPRIORITY32, regaddr);
}
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(IMX9_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(IMX9_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(IMX9_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
imx9_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARM_MPU
irq_attach(IMX9_IRQ_MEMFAULT, arm_memfault, NULL);
up_enable_irq(IMX9_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(IMX9_IRQ_NMI, imx9_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(IMX9_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(IMX9_IRQ_BUSFAULT, arm_busfault, NULL);
irq_attach(IMX9_IRQ_USAGEFAULT, arm_usagefault, NULL);
irq_attach(IMX9_IRQ_PENDSV, imx9_pendsv, NULL);
arm_enable_dbgmonitor();
irq_attach(IMX9_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
irq_attach(IMX9_IRQ_RESERVED, imx9_reserved, NULL);
#endif
imx9_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*/
#ifdef CONFIG_IMX9_GPIO_IRQ
imx9_gpioirq_initialize();
#endif
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (imx9_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= IMX9_IRQ_EXTINT)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
#ifdef CONFIG_IMX9_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
imx9_gpioirq_disable(irq);
}
#endif
#if 0 /* Might be useful in early bring-up */
imx9_dumpnvic("disable", irq);
#endif
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (imx9_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= IMX9_IRQ_EXTINT)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
#ifdef CONFIG_IMX9_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
imx9_gpioirq_enable(irq);
}
#endif
#if 0 /* Might be useful in early bring-up */
imx9_dumpnvic("enable", irq);
#endif
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= IMX9_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < IMX9_IRQ_EXTINT)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= IMX9_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
imx9_dumpnvic("prioritize", irq);
return OK;
}
#endif

592
arch/arm/src/imx9/imx9_lowputc.c Normal file
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@ -0,0 +1,592 @@
/****************************************************************************
* arch/arm/src/imx9/imx9_lowputc.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdlib.h>
#include <assert.h>
#include <errno.h>
#include "hardware/imx9_pinmux.h"
#include "hardware/imx9_lpuart.h"
#include "arm_internal.h"
#include "imx9_lowputc.h"
#include "imx9_clockconfig.h"
#include "imx9_iomuxc.h"
#include "hardware/imx9_clock.h"
#include "hardware/imx9_pinmux.h"
#include <arch/board/board.h> /* Include last: has dependencies */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 0
# define IMX9_CONSOLE_BASE IMX9_LPUART1_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART1_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART1_2STOP
#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 1
# define IMX9_CONSOLE_BASE IMX9_LPUART2_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART2_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART2_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART2_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART2_2STOP
#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 2
# define IMX9_CONSOLE_BASE IMX9_LPUART3_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART3_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART3_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART3_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART3_2STOP
#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 3
# define IMX9_CONSOLE_BASE IMX9_LPUART4_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART4_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART4_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART4_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART4_2STOP
#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 4
# define IMX9_CONSOLE_BASE IMX9_LPUART5_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART5_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART5_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART5_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART5_2STOP
#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 5
# define IMX9_CONSOLE_BASE IMX9_LPUART6_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART6_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART6_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART6_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART6_2STOP
#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 6
# define IMX9_CONSOLE_BASE IMX9_LPUART7_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART7_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART7_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART7_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART7_2STOP
#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE)
# define IMX9_CONSOLE_DEVNUM 7
# define IMX9_CONSOLE_BASE IMX9_LPUART8_BASE
# define IMX9_CONSOLE_BAUD CONFIG_LPUART8_BAUD
# define IMX9_CONSOLE_BITS CONFIG_LPUART8_BITS
# define IMX9_CONSOLE_PARITY CONFIG_LPUART8_PARITY
# define IMX9_CONSOLE_2STOP CONFIG_LPUART8_2STOP
#endif
/* Clocking *****************************************************************/
/* Functional clocking is provided via the PCC. The PCC clocking must
* be configured by board-specific logic prior to using the LPUART.
*/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef IMX9_CONSOLE_BASE
static const struct uart_config_s g_console_config =
{
.baud = IMX9_CONSOLE_BAUD, /* Configured baud */
.parity = IMX9_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */
.bits = IMX9_CONSOLE_BITS, /* Number of bits (5-9) */
.stopbits2 = IMX9_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */
};
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imx9_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
#ifdef CONFIG_IMX9_LPUART1
/* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART1_RX);
imx9_iomux_configure(MUX_LPUART1_TX);
#ifdef CONFIG_LPUART1_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART1_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART1_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART2
/* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART2_RX);
imx9_iomux_configure(MUX_LPUART2_TX);
#ifdef CONFIG_LPUART2_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART2_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART2_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART3
/* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART3_RX);
imx9_iomux_configure(MUX_LPUART3_TX);
#ifdef CONFIG_LPUART3_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART3_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART3_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART4
/* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART4_RX);
imx9_iomux_configure(MUX_LPUART4_TX);
#ifdef CONFIG_LPUART4_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART4_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART4_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART5
/* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART5_RX);
imx9_iomux_configure(MUX_LPUART5_TX);
#ifdef CONFIG_LPUART5_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART5_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART5_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART6
/* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART6_RX);
imx9_iomux_configure(MUX_LPUART6_TX);
#ifdef CONFIG_LPUART6_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART6_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART6_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART7
/* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART7_RX);
imx9_iomux_configure(MUX_LPUART7_TX);
#ifdef CONFIG_LPUART7_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART7_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART7_RTS);
#endif
#endif
#ifdef CONFIG_IMX9_LPUART8
/* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imx9_iomux_configure(MUX_LPUART8_RX);
imx9_iomux_configure(MUX_LPUART8_TX);
#ifdef CONFIG_LPUART0_OFLOWCONTROL
imx9_iomux_configure(MUX_LPUART8_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
imx9_iomux_configure(MUX_LPUART8_RTS);
#endif
#endif
#ifdef IMX9_CONSOLE_BASE
/* Configure the serial console for initial, non-interrupt driver mode */
imx9_lpuart_configure(IMX9_CONSOLE_BASE, IMX9_CONSOLE_DEVNUM,
&g_console_config);
#endif
#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */
}
/****************************************************************************
* Name: imx9_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
int imx9_lpuart_configure(uint32_t base, int uartnum,
const struct uart_config_s *config)
{
uint32_t lpuart_freq;
clock_config_t lpuart_config;
uint16_t sbr;
uint16_t temp_sbr;
uint32_t osr;
uint32_t temp_osr;
int temp_diff;
int configured_baud = config->baud;
int calculated_baud;
int baud_diff;
uint32_t regval;
switch (base)
{
#ifdef LPUART1_CLK
case IMX9_LPUART1_BASE:
lpuart_config = LPUART1_CLK;
break;
#endif
#ifdef LPUART2_CLK
case IMX9_LPUART2_BASE:
lpuart_config = LPUART2_CLK;
break;
#endif
#ifdef LPUART3_CLK
case IMX9_LPUART3_BASE:
lpuart_config = LPUART3_CLK;
break;
#endif
#ifdef LPUART4_CLK
case IMX9_LPUART4_BASE:
lpuart_config = LPUART4_CLK;
break;
#endif
#ifdef LPUART5_CLK
case IMX9_LPUART5_BASE:
lpuart_config = LPUART5_CLK;
break;
#endif
#ifdef LPUART6_CLK
case IMX9_LPUART6_BASE:
lpuart_config = LPUART6_CLK;
break;
#endif
#ifdef LPUART7_CLK
case IMX9_LPUART7_BASE:
lpuart_config = LPUART7_CLK;
break;
#endif
#ifdef LPUART8_CLK
case IMX9_LPUART7_BASE:
lpuart_config = LPUART8_CLK;
break;
#endif
default:
return ERROR;
}
/* Configure root clock */
imx9_configure_clock(lpuart_config, true);
imx9_get_rootclock(GET_CLOCK_ROOT(lpuart_config), &lpuart_freq);
/* This LPUART instantiation uses a slightly different baud rate
* calculation. The idea is to use the best OSR (over-sampling rate)
* possible.
*
* NOTE: OSR is typically hard-set to 16 in other LPUART instantiations
* loop to find the best OSR value possible, one that generates minimum
* baud_diff iterate through the rest of the supported values of OSR
*/
baud_diff = configured_baud;
osr = 0;
sbr = 0;
for (temp_osr = 4; temp_osr <= 32; temp_osr++)
{
/* Calculate the temporary sbr value */
temp_sbr = (lpuart_freq / (configured_baud * temp_osr));
/* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the
* desired baud rate.
*/
if (temp_sbr == 0)
{
temp_sbr = 1;
}
/* Calculate the baud rate based on the temporary OSR and SBR values */
calculated_baud = (lpuart_freq / (temp_osr * temp_sbr));
temp_diff = abs(calculated_baud - configured_baud);
/* Select the better value between srb and (sbr + 1) */
calculated_baud = (lpuart_freq / (temp_osr * (temp_sbr + 1)));
if (temp_diff >
abs(calculated_baud - configured_baud))
{
temp_diff = abs(calculated_baud - configured_baud);
temp_sbr++;
}
if (temp_diff <= baud_diff)
{
baud_diff = temp_diff;
osr = temp_osr;
sbr = temp_sbr;
}
}
if (baud_diff > ((configured_baud * 3) / 100))
{
/* Unacceptable baud rate difference of more than 3% */
return ERROR;
}
/* Reset all internal logic and registers, except the Global Register */
regval = getreg32(base + IMX9_LPUART_GLOBAL_OFFSET);
regval |= LPUART_GLOBAL_RST;
putreg32(regval, base + IMX9_LPUART_GLOBAL_OFFSET);
regval &= ~LPUART_GLOBAL_RST;
putreg32(regval, base + IMX9_LPUART_GLOBAL_OFFSET);
/* Enable RX and TX FIFOs */
putreg32(LPUART_FIFO_RXFE | LPUART_FIFO_TXFE,
base + IMX9_LPUART_FIFO_OFFSET);
/* Construct MODIR register */
regval = 0;
if (config->userts)
{
regval |= LPUART_MODIR_RXRTSE;
}
else if (config->users485)
{
/* Both TX and RX side can't control RTS, so this gives
* the RX side precedence. This should have been filtered
* in layers above anyway, but it's just a precaution.
*/
regval |= LPUART_MODIR_TXRTSE;
}
if (config->usects)
{
regval |= LPUART_MODIR_TXCTSE;
}
if (config->invrts)
{
regval |= LPUART_MODIR_TXRTSPOL;
}
putreg32(regval, base + IMX9_LPUART_MODIR_OFFSET);
regval = 0;
if ((osr > 3) && (osr < 8))
{
regval |= LPUART_BAUD_BOTHEDGE;
}
if (config->stopbits2)
{
regval |= LPUART_BAUD_SBNS;
}
regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr);
putreg32(regval, base + IMX9_LPUART_BAUD_OFFSET);
regval = 0;
if (config->parity == 1)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD;
}
else if (config->parity == 2)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN;
}
if (config->bits == 9 || (config->bits == 8 && config->parity != 0))
{
regval |= LPUART_CTRL_M;
}
else if ((config->bits == 8))
{
regval &= ~LPUART_CTRL_M;
}
else
{
/* REVISIT: Here should be added support of other bit modes. */
return -ENOSYS;
}
regval |= LPUART_CTRL_RE | LPUART_CTRL_TE;
putreg32(regval, base + IMX9_LPUART_CTRL_OFFSET);
return OK;
}
/****************************************************************************
* Name: arm_earlyprintinit
*
* Description:
* Configure LPUART1 for non-interrupt driven operation
*
****************************************************************************/
void arm_earlyprintinit(char ch)
{
/* Assume bootloader has already set up the LPUART1 */
}
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from U-
* Boot (and the same UART is used for the console, of course.)
*
****************************************************************************/
void arm_lowputc(char ch)
{
#ifdef IMX9_CONSOLE_BASE
while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
/* If the character to output is a newline,
* then pre-pend a carriage return
*/
if (ch == '\n')
{
/* Send the carriage return by writing it into the UART_TXD register. */
putreg32((uint32_t)'\r',
IMX9_CONSOLE_BASE + IMX9_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
}
/* Send the character by writing it into the UART_TXD register. */
putreg32((uint32_t)ch, IMX9_CONSOLE_BASE + IMX9_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
#endif
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_lowputc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H
#define __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/****************************************************************************
* Public Types
****************************************************************************/
/* This structure describes the configuration of an UART */
struct uart_config_s
{
uint32_t baud; /* Configured baud */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (5-9) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
bool userts; /* True: Assert RTS when there are data to be sent */
bool invrts; /* True: Invert sense of RTS pin (true=active high) */
bool usects; /* True: Condition transmission on CTS asserted */
bool users485; /* True: Assert RTS while transmission progresses */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
/****************************************************************************
* Name: imx9_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imx9_lowsetup(void);
/****************************************************************************
* Name: imx9_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
int imx9_lpuart_configure(uint32_t base,
int uartnum,
const struct uart_config_s *config);
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_lpi2c.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LPI2C_H
#define __ARCH_ARM_SRC_IMX9_IMX9_LPI2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
struct i2c_master_s *imx9_i2cbus_initialize(int port);
/****************************************************************************
* Name: imx9_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameters:
* Device structure as returned by the imx9_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int imx9_i2cbus_uninitialize(struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LPI2C_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_lpspi.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LPSPI_H
#define __ARCH_ARM_SRC_IMX9_IMX9_LPSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/spi/spi.h>
#include "chip.h"
#include "hardware/imx9_lpspi.h"
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
struct spi_dev_s; /* Forward reference */
/****************************************************************************
* Name: imx9_lpspibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameters:
* bus number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct spi_dev_s *imx9_lpspibus_initialize(int bus);
/****************************************************************************
* Name: imx9_lpspibus_uninitialize
*
* Description:
* Unitialize the selected SPI bus if refcount is 1
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* None
*
****************************************************************************/
void imx9_lpspi_uninitialize(struct spi_dev_s *dev);
/****************************************************************************
* Name: imx9_lpspi1/2/...select and imx9_lpspi1/2/...status
*
* Description:
* The external functions, imx9_lpspi1/2/...select,
* imx9_lpspi1/2/...status, and imx9_lpspi1/2/...cmddata must be
* provided by board-specific logic. These are implementations of the
* select, status, and cmddata methods of the SPI interface defined by
* struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
* (including imx9_lpspibus_initialize()) are provided by common IMX9
* logic. To use this common SPI logic on your board:
*
* 1. Provide logic in imx9_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide imx9_lpspi1/2/...select() and imx9_lpspi1/2/...status()
* functions in your board-specific logic. These functions will perform
* chip selection and status operations using GPIOs in the way your
* board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
* then provide imx9_lpspi1/2/...cmddata() functions in your
* board-specific logic. These functions will perform cmd/data selection
* operations using GPIOs in the way your board is configured.
* 4. Add a calls to imx9_lpspibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by imx9_lpspibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
void imx9_lpspi_select(struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t imx9_lpspi_status(struct spi_dev_s *dev, uint32_t devid);
int imx9_lpspi_cmddata(struct spi_dev_s *dev,
uint32_t devid, bool cmd);
#ifdef CONFIG_IMX9_LPSPI_HWPCS
void imx9_lpspi_hw_select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
#endif
/****************************************************************************
* Name: imx9_lpspi1/2/...register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s)
* must be implemented. These functions implements the registercallback
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
int imx9_lpspi_register(struct spi_dev_s *dev,
spi_mediachange_t callback,
void *arg);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LPSPI_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_mpuinit.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <sys/param.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "barriers.h"
#include "hardware/imx9_memorymap.h"
#include "imx9_mpuinit.h"
#include "arm_internal.h"
#ifdef CONFIG_ARM_MPU
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_ARMV7M_DCACHE
/* With Dcache off:
* Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be off
*/
# undef MPU_RASR_B
# define MPU_RASR_B 0
# define RASR_B_VALUE 0
# define RASR_C_VALUE 0
#else
# ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
/* With Dcache on:
* Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be on
*/
# define RASR_B_VALUE MPU_RASR_B
# define RASR_C_VALUE MPU_RASR_C
# else
/* With Dcache in WRITETHROUGH Bufferable (MPU_RASR_B)
* needs to be off, except for FLASH for alignment leniency
*/
# define RASR_B_VALUE 0
# define RASR_C_VALUE MPU_RASR_C
# endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_mpu_initialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted i.MXRT
* resources.
*
****************************************************************************/
void imx9_mpu_initialize(void)
{
uint32_t regval;
uint32_t region;
#ifdef CONFIG_BUILD_PROTECTED
uintptr_t datastart;
uintptr_t dataend;
#endif
/* Show MPU information */
mpu_showtype();
/* Reset MPU if enabled */
mpu_reset();
#ifdef CONFIG_ARMV7M_DCACHE
/* Memory barrier */
ARM_DMB();
#endif
#ifdef CONFIG_BUILD_PROTECTED
/* Configure user flash and SRAM space */
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(dataend >= datastart);
mpu_user_intsram(datastart, dataend - datastart);
#else
region = mpu_allocregion();
DEBUGASSERT(region == 0);
/* Select the region */
putreg32(region, MPU_RNR);
/* Select the region base address */
putreg32(region | MPU_RBAR_VALID, MPU_RBAR);
/* The configure the region */
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_SIZE_LOG2(32) | /* entire memory */
MPU_RASR_TEX_SO | /* Strongly ordered */
MPU_RASR_AP_NONO | /* P:None U:None */
MPU_RASR_XN; /* Execute-never to prevent instruction fetch */
putreg32(regval, MPU_RASR);
mpu_configure_region(IMX9_FLEXSPI1_ALIAS_BASE, 32 * 1024 * 1024,
MPU_RASR_AP_RORO | /* P:R0 U:R0 */
MPU_RASR_TEX_NOR | /* Normal */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B /* Bufferable */
);
mpu_configure_region(IMX9_ITCM_BASE, 512 * 1024,
MPU_RASR_AP_RORO | /* P:R0 U:R0 */
MPU_RASR_TEX_NOR | /* Normal */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B /* Bufferable */
);
mpu_configure_region(IMX9_DTCM_BASE, 512 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR | /* Normal */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B | /* Bufferable */
MPU_RASR_S | /* Shareable */
MPU_RASR_XN /* Execute-never to prevent instruction fetch */
);
mpu_configure_region(0x20400000, 1 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR | /* Normal */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B /* Bufferable */
);
mpu_configure_region(IMX9_FLEXSPI1_BASE, 128 * 1024 * 1024,
MPU_RASR_AP_RORO | /* P:R0 U:R0 */
MPU_RASR_TEX_NOR | /* Strongly Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B /* Bufferable */
);
/* AIPS1 + AIPS2 */
mpu_configure_region(IMX9_AIPS1_BASE, 16 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
);
mpu_configure_region(IMX9_AIPS3_BASE, 8 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
);
mpu_configure_region(IMX9_AIPS4_BASE, 8 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
);
mpu_configure_region(IMX9_GPIO_MEM_BASE, 320 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
);
mpu_configure_region(IMX9_GPIO1_BASE, 64 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
);
/* For RPMSG VRING and RSC table */
mpu_configure_region(IMX9_RPMSG_BASE, 4096 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR /* Normal */
);
mpu_configure_region(IMX9_DRAM_XIP_BASE, 0x003ff800,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR /* Normal */
);
#endif
mpu_control(true, false, true);
}
/****************************************************************************
* Name: imx9_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void imx9_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif
#endif /* CONFIG_ARM_MPU */

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/****************************************************************************
* arch/arm/src/imx9/imx9_mpuinit.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_MPUINIT_H
#define __ARCH_ARM_SRC_IMX9_IMX9_MPUINIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_mpu_initialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted
* i.MXRT resources.
*
****************************************************************************/
#ifdef CONFIG_ARM_MPU
void imx9_mpu_initialize(void);
#else
# define imx9_mpu_initialize()
#endif
/****************************************************************************
* Name: imx9_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void imx9_mpu_uheap(uintptr_t start, size_t size);
#else
# define imx9_mpu_uheap(start,size)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_MPUINIT_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_mu.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "imx9_mu.h"
#include "arm_internal.h"
#include "hardware/imx95/imx95_memorymap.h"
#include "hardware/imx9_mu.h"
#include <debug.h>
#include <nuttx/config.h>
#include <sys/types.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NR_OF_GPI 4
#define MSG_INT_MASK ((1 << IMX9_MU_RR_REGARRAY_SIZE) - 1)
#define GPI_INT_MASK ((1 << NR_OF_GPI) - 1)
/****************************************************************************
* Private Types
****************************************************************************/
struct imx9_mudev_s
{
uint32_t mubase;
uint32_t irq;
imx9_mu_msg_callback_t msg_callback;
imx9_mu_gpi_callback_t gpi_callback;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_IMX9_MU5
static struct imx9_mudev_s g_mu5_dev = /* clang-format off */
{
.mubase = IMX9_MU5_MUA_BASE,
.irq = IMX9_IRQ_MU5_A
}; /* clang-format on */
#endif
#ifdef CONFIG_IMX9_MU7
static struct imx9_mudev_s g_mu7_dev = /* clang-format off */
{
.mubase = IMX9_MU7_MUB_BASE,
.irq = IMX9_IRQ_MU7_B
}; /* clang-format on */
#endif
#ifdef CONFIG_IMX9_MU8
static struct imx9_mudev_s g_mu8_dev = /* clang-format off */
{
.mubase = IMX9_MU8_MUB_BASE,
.irq = IMX9_IRQ_MU8_B
}; /* clang-format on */
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
static int imx9_mu_interrupt(int irq, void *context, void *args)
{
struct imx9_mudev_s *dev = args;
uint32_t sr = getreg32(IMX9_MU_SR(dev->mubase));
uint32_t rsr = getreg32(IMX9_MU_RSR(dev->mubase));
uint32_t gsr = getreg32(IMX9_MU_GSR(dev->mubase));
ipcinfo("MU irq=%d, SR=0x%04lx, RSR=0x%04lx, GSR=0x%04lx\n", irq, sr, rsr,
gsr);
if (sr & IMX9_MU_SR_RFP_FLAG)
{
for (int i = 0; i < IMX9_MU_RR_REGARRAY_SIZE; i++)
{
if (rsr & (1 << i))
{
uint32_t msg = imx95_mu_receive_msg_non_blocking(dev, i);
if (dev->msg_callback)
{
dev->msg_callback(i, msg, dev);
}
}
}
for (int i = 0; i < NR_OF_GPI; i++)
{
if (gsr & (1 << i))
{
putreg32((1 << i), IMX9_MU_GSR(dev->mubase));
if (dev->gpi_callback)
{
dev->gpi_callback(i, dev);
}
}
}
}
/* Unknown interrupt flag which occurs when A55 shuts down */
if (sr & 0x80)
{
/* TODO how to clear this flag? A W1C doesn't seem to work.. */
putreg32(0x80, IMX9_MU_SR(dev->mubase));
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
struct imx9_mudev_s *imx95_mu_init(int index)
{
struct imx9_mudev_s *priv;
#ifdef CONFIG_IMX9_MU5
if ((index == 5))
{
priv = &g_mu5_dev;
}
else
#endif
#ifdef CONFIG_IMX9_MU7
if ((index == 7))
{
priv = &g_mu7_dev;
}
else
#endif
#ifdef CONFIG_IMX9_MU8
if ((index == 8))
{
priv = &g_mu8_dev;
}
else
#endif
{
return NULL;
}
irq_attach(priv->irq, imx9_mu_interrupt, priv);
up_enable_irq(priv->irq);
priv->gpi_callback = NULL;
priv->msg_callback = NULL;
return priv;
}
void imx95_mu_subscribe_msg(struct imx9_mudev_s *priv,
uint32_t msg_int_bitfield,
imx9_mu_msg_callback_t callback)
{
priv->msg_callback = callback;
putreg32(msg_int_bitfield & MSG_INT_MASK, IMX9_MU_RCR(priv->mubase));
}
void imx95_mu_subscribe_gpi(struct imx9_mudev_s *priv,
uint32_t gpi_int_enable,
imx9_mu_gpi_callback_t callback)
{
priv->gpi_callback = callback;
putreg32(gpi_int_enable & GPI_INT_MASK, IMX9_MU_GIER(priv->mubase));
}
void imx95_mu_deinit(struct imx9_mudev_s *priv)
{
up_disable_irq(priv->irq);
}
int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv,
uint32_t reg_index, uint32_t msg)
{
assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE);
ipcinfo("MU send msg nonblocking idx=%ld, msg=%ld\n", reg_index, msg);
if ((getreg32(IMX9_MU_TSR(priv->mubase)) & (1UL << reg_index)) == 0UL)
{
return -EBUSY;
}
putreg32(msg, IMX9_MU_TR1(priv->mubase) + (reg_index * sizeof(uint32_t)));
return OK;
}
void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index,
uint32_t msg)
{
assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE);
ipcinfo("MU send msg idx=%ld, msg=%ld\n", reg_index, msg);
/* Wait TX register to be empty. */
while ((getreg32(IMX9_MU_TSR(priv->mubase)) & (1UL << reg_index)) == 0UL)
;
putreg32(msg, IMX9_MU_TR1(priv->mubase) + (reg_index * sizeof(uint32_t)));
}
int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index)
{
if ((getreg32(IMX9_MU_RSR(priv->mubase)) & (1UL << reg_index)) == 0UL)
{
return -ENODATA;
}
return 0;
}
uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv,
uint32_t reg_index)
{
assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE);
return getreg32(IMX9_MU_RR1(priv->mubase) +
(reg_index * sizeof(uint32_t)));
}
uint32_t imx95_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index)
{
assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE);
/* Wait RX register to be full. */
while (imx95_mu_has_received_msg(priv, reg_index) == -ENODATA);
return getreg32(IMX9_MU_RR1(priv->mubase) +
(reg_index * sizeof(uint32_t)));
}
int imx95_mu_trigger_interrupts(struct imx9_mudev_s *priv,
uint32_t interrupts)
{
int ret = -ECOMM;
uint32_t gcr = getreg32(IMX9_MU_GCR(priv->mubase));
/* Only if previous interrupts has been accepted. */
if ((gcr & interrupts) == 0)
{
putreg32(gcr | interrupts, IMX9_MU_GCR(priv->mubase));
ret = OK;
}
return ret;
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_mu.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_MU_H
#define __ARCH_ARM_SRC_IMX9_IMX9_MU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdbool.h>
#include <stdint.h>
typedef void (*imx9_mu_msg_callback_t)(int id, uint32_t msg, void *arg);
typedef void (*imx9_mu_gpi_callback_t)(int id, void *arg);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct imx9_mudev_s *imx95_mu_init(int index);
void imx95_mu_subscribe_msg(struct imx9_mudev_s *priv,
uint32_t msg_int_bitfield,
imx9_mu_msg_callback_t callback);
void imx95_mu_subscribe_gpi(struct imx9_mudev_s *priv,
uint32_t gpi_int_enable,
imx9_mu_gpi_callback_t callback);
void imx95_mu_deinit(struct imx9_mudev_s *priv);
int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv,
uint32_t reg_index, uint32_t msg);
void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index,
uint32_t msg);
int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index);
uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv,
uint32_t reg_index);
uint32_t imx95_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index);
int imx95_mu_trigger_interrupts(struct imx9_mudev_s *priv,
uint32_t interrupts);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_MU_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_rptun.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "imx9_rptun.h"
#include "arm_internal.h"
#include "imx9_mu.h"
#include "imx9_rsctable.h"
#include <debug.h>
#include <nuttx/config.h>
#include <nuttx/kthread.h>
#include <nuttx/nuttx.h>
#include <nuttx/rptun/rptun.h>
#include <nuttx/semaphore.h>
#include <nuttx/signal.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define VRING_SHMEM 0x88220000 /* Vring shared memory start */
#define RPMSG_MU_CHANNEL 1
#define MU_INSTANCE 7
#define MU_MSG_VQID_BITOFFSET 16
/****************************************************************************
* Private Types
****************************************************************************/
/* IMX9 rptun shared memory */
struct imx9_rptun_shmem_s
{
struct rptun_rsc_s rsc;
};
/* IMX9 rptun device */
struct imx9_rptun_dev_s
{
struct rptun_dev_s rptun;
rptun_callback_t callback;
void *mu;
void *arg;
struct imx9_rptun_shmem_s *shmem;
char cpuname[RPMSG_NAME_SIZE + 1];
char shmemname[RPMSG_NAME_SIZE + 1];
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static const char *imx9_rptun_get_cpuname(struct rptun_dev_s *dev);
static const char *imx9_rptun_get_firmware(struct rptun_dev_s *dev);
static const struct rptun_addrenv_s *
imx9_rptun_get_addrenv(struct rptun_dev_s *dev);
static struct rptun_rsc_s *imx9_rptun_get_resource(struct rptun_dev_s *dev);
static bool imx9_rptun_is_autostart(struct rptun_dev_s *dev);
static bool imx9_rptun_is_master(struct rptun_dev_s *dev);
static int imx9_rptun_start(struct rptun_dev_s *dev);
static int imx9_rptun_stop(struct rptun_dev_s *dev);
static int imx9_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid);
static int imx9_rptun_register_callback(struct rptun_dev_s *dev,
rptun_callback_t callback,
void *arg);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct rptun_ops_s g_imx9_rptun_ops =
{
.get_cpuname = imx9_rptun_get_cpuname,
.get_firmware = imx9_rptun_get_firmware,
.get_addrenv = imx9_rptun_get_addrenv,
.get_resource = imx9_rptun_get_resource,
.is_autostart = imx9_rptun_is_autostart,
.is_master = imx9_rptun_is_master,
.start = imx9_rptun_start,
.stop = imx9_rptun_stop,
.notify = imx9_rptun_notify,
.register_callback = imx9_rptun_register_callback,
};
struct imx9_rptun_dev_s g_rptun_dev;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_rptun_get_cpuname
****************************************************************************/
static const char *imx9_rptun_get_cpuname(struct rptun_dev_s *dev)
{
struct imx9_rptun_dev_s *priv =
container_of(dev, struct imx9_rptun_dev_s, rptun);
return priv->cpuname;
}
/****************************************************************************
* Name: imx9_rptun_get_firmware
****************************************************************************/
static const char *imx9_rptun_get_firmware(struct rptun_dev_s *dev)
{
return NULL;
}
/****************************************************************************
* Name: imx9_rptun_get_addrenv
****************************************************************************/
static const struct rptun_addrenv_s *
imx9_rptun_get_addrenv(struct rptun_dev_s *dev)
{
return NULL;
}
/****************************************************************************
* Name: imx9_rptun_get_resource
****************************************************************************/
static struct rptun_rsc_s *imx9_rptun_get_resource(struct rptun_dev_s *dev)
{
struct imx9_rptun_dev_s *priv =
container_of(dev, struct imx9_rptun_dev_s, rptun);
if (priv->shmem != NULL)
{
return &priv->shmem->rsc;
}
priv->shmem = (struct imx9_rptun_shmem_s *)VRING_SHMEM;
if (priv->shmem->rsc.rsc_tbl_hdr.offset
!= g_imx9_rsc_table.rsc_tbl_hdr.offset)
{
imx9_rsctable_copy();
}
return &priv->shmem->rsc;
}
/****************************************************************************
* Name: imx9_rptun_is_autostart
****************************************************************************/
static bool imx9_rptun_is_autostart(struct rptun_dev_s *dev)
{
return true;
}
/****************************************************************************
* Name: imx9_rptun_is_master
****************************************************************************/
static bool imx9_rptun_is_master(struct rptun_dev_s *dev)
{
return false;
}
/****************************************************************************
* Name: imx9_rptun_start
****************************************************************************/
static int imx9_rptun_start(struct rptun_dev_s *dev)
{
return 0;
}
/****************************************************************************
* Name: imx9_rptun_stop
****************************************************************************/
static int imx9_rptun_stop(struct rptun_dev_s *dev)
{
return 0;
}
/****************************************************************************
* Name: imx9_rptun_notify
****************************************************************************/
static int imx9_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid)
{
struct imx9_rptun_dev_s *priv =
container_of(dev, struct imx9_rptun_dev_s, rptun);
ipcinfo("Rptun notify vqid=%ld\n", vqid);
imx95_mu_send_msg(priv->mu, RPMSG_MU_CHANNEL,
vqid << MU_MSG_VQID_BITOFFSET);
return 0;
}
/****************************************************************************
* Name: imx9_rptun_register_callback
****************************************************************************/
static int imx9_rptun_register_callback(struct rptun_dev_s *dev,
rptun_callback_t callback, void *arg)
{
struct imx9_rptun_dev_s *priv =
container_of(dev, struct imx9_rptun_dev_s, rptun);
priv->callback = callback;
priv->arg = arg;
return 0;
}
/****************************************************************************
* Name: imx9_mu_callback
****************************************************************************/
static void imx9_mu_callback(int id, uint32_t msg, void *arg)
{
if (id == RPMSG_MU_CHANNEL)
{
struct imx9_rptun_dev_s *dev = &g_rptun_dev;
uint32_t vqid = msg >> MU_MSG_VQID_BITOFFSET;
ipcinfo("Rptun interrupt id=%d, vqid=%ld\n", id, vqid);
if (dev->callback != NULL)
{
dev->callback(dev->arg, vqid);
}
}
else
{
DEBUGASSERT(0);
}
__asm volatile("dsb 0xF" ::: "memory");
}
/****************************************************************************
* Public Functions
****************************************************************************/
int imx9_rptun_init(const char *shmemname, const char *cpuname)
{
struct imx9_rptun_dev_s *dev = &g_rptun_dev;
int ret = OK;
/* Subscribe to MU */
dev->mu = imx95_mu_init(MU_INSTANCE);
if (!dev->mu)
{
ipcerr("ERROR: cannot init mailbox %i!\n", MU_INSTANCE);
return ret;
}
imx95_mu_subscribe_msg(dev->mu, (1 << RPMSG_MU_CHANNEL), imx9_mu_callback);
/* Configure device */
dev->rptun.ops = &g_imx9_rptun_ops;
strncpy(dev->cpuname, cpuname, RPMSG_NAME_SIZE);
strncpy(dev->shmemname, shmemname, RPMSG_NAME_SIZE);
ret = rptun_initialize(&dev->rptun);
if (ret < 0)
{
ipcerr("ERROR: rptun_initialize failed %d!\n", ret);
}
return ret;
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_rptun.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_RPTUN_H
#define __ARCH_ARM_SRC_IMX9_IMX9_RPTUN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_rptun_init
****************************************************************************/
int imx9_rptun_init(const char *shmemname, const char *cpuname);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_RPTUN_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_rsctable.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "imx9_rsctable.h"
#include <string.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NUM_VRINGS 0x02
#define RL_BUFFER_COUNT 0x100
#define VRING_ALIGN 0x1000
#define VRING_SIZE 0x8000
#define VDEV0_VRING_BASE 0x88000000
#define RESOURCE_TABLE_BASE 0x88220000
#define NO_RESOURCE_ENTRIES (1)
#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */
#define IMX9_RSC_TABLE_VERSION (1)
/****************************************************************************
* Private Functions
****************************************************************************/
/* Place resource table in special ELF section */
#if defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__ ((section(".resource_table")))
#elif defined(__ICCARM__)
#pragma location = ".resource_table"
#else
#error Compiler not supported!
#endif
const struct rptun_rsc_s g_imx9_rsc_table =
{
.rsc_tbl_hdr =
{
IMX9_RSC_TABLE_VERSION,
NO_RESOURCE_ENTRIES,
{
0, 0
}
},
.offset =
{
offsetof(struct rptun_rsc_s, rpmsg_vdev)
},
.log_trace =
{
RSC_TRACE, 0, 0
},
.rpmsg_vdev = /* SRTM virtio device entry */
{
RSC_VDEV,
7,
2,
RSC_VDEV_FEATURE_NS,
0,
0,
0,
NUM_VRINGS,
{
0, 0
}
},
.rpmsg_vring0 =
{
VDEV0_VRING_BASE,
VRING_ALIGN,
RL_BUFFER_COUNT,
0,
0
},
.rpmsg_vring1 =
{
VDEV0_VRING_BASE + VRING_SIZE,
VRING_ALIGN,
RL_BUFFER_COUNT,
1,
0
},
.config =
{
0
}
};
/****************************************************************************
* Public Functions
****************************************************************************/
void imx9_rsctable_copy(void)
{
memcpy((void *)RESOURCE_TABLE_BASE, (void *)&g_imx9_rsc_table,
sizeof(g_imx9_rsc_table));
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_rsctable.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_RSCTABLE_H
#define __ARCH_ARM_SRC_IMX9_IMX9_RSCTABLE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/rptun/rptun.h>
/****************************************************************************
* Public Data
****************************************************************************/
extern const struct rptun_rsc_s g_imx9_rsc_table;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void imx9_rsctable_copy(void);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_RSCTABLE_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_scmi.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H
#define __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SM_PLATFORM_A2P 0 /* SCMI Agent -> SCMI Platform */
#define SM_PLATFORM_NOTIFY 1 /* SCMI Platform -> SCMI Agent */
#define SM_PLATFORM_PRIORITY 2
#define SM_CLOCK_RATE_MASK 0xFFFFFFFFU
/* SCMI clock round options */
#define SCMI_CLOCK_ROUND_DOWN 0U /* Round down */
#define SCMI_CLOCK_ROUND_UP 1U /* Round up */
#define SCMI_CLOCK_ROUND_AUTO 2U /* Round to nearest */
/* SCMI clock rate flags */
#define SCMI_CLOCK_RATE_FLAGS_ROUND(x) (((x) & 0x3U) << 2U) /* Round up/down */
#define SCMI_CLOCK_RATE_FLAGS_NO_RESP(x) (((x) & 0x1U) << 1U) /* Ignore delayed response */
#define SCMI_CLOCK_RATE_FLAGS_ASYNC(x) (((x) & 0x1U) << 0U) /* Async flag */
/* SCMI clock config attributes */
#define SCMI_CLOCK_CONFIG_SET_OEM(x) (((x) & 0xFFU) << 16U) /* OEM specified config type */
#define SCMI_CLOCK_CONFIG_SET_ENABLE(x) (((x) & 0x3U) << 0U) /* Enable/Disable */
/* SCMI pin control types */
#define SCMI_PINCTRL_SEL_PIN 0U
#define SCMI_PINCTRL_SEL_GROUP 1U
#define SCMI_PINCTRL_TYPE_MUX 192U /* Mux type */
#define SCMI_PINCTRL_TYPE_CONFIG 193U /* Config type */
#define SCMI_PINCTRL_TYPE_DAISY_ID 194U /* Daisy ID type */
#define SCMI_PINCTRL_TYPE_DAISY_CFG 195U /* Daisy config type */
#define SCMI_PINCTRL_SET_ATTR_NUM_CONFIGS(x) (((x) & 0xFFU) << 2U)
#define SCMI_PINCTRL_SET_ATTR_SELECTOR(x) (((x) & 0x3U) << 0U)
/* Pinctrl */
#define SM_PLATFORM_PINCTRL_MUX_MODE_MASK (0x7U)
#define SM_PLATFORM_PINCTRL_MUX_MODE_SHIFT (0U)
#define SM_PLATFORM_PINCTRL_MUX_MODE(x) \
(((uint32_t)(((uint32_t)(x)) << SM_PLATFORM_PINCTRL_MUX_MODE_SHIFT)) & SM_PLATFORM_PINCTRL_MUX_MODE_MASK)
#define SM_PLATFORM_PINCTRL_SION_MASK (0x10)
#define SM_PLATFORM_PINCTRL_SION_SHIFT (4U)
#define SM_PLATFORM_PINCTRL_SION(x) \
(((uint32_t)(((uint32_t)(x)) << SM_PLATFORM_PINCTRL_SION_SHIFT)) & SM_PLATFORM_PINCTRL_SION_MASK)
#define SM_PLATFORM_PINCTRL_BASE IMX9_IOMUXC_BASE
#define SM_PLATFORM_PINCTRL_MUXREG_OFF (SM_PLATFORM_PINCTRL_BASE)
#define SM_PLATFORM_PINCTRL_CFGREG_OFF (SM_PLATFORM_PINCTRL_BASE + 0x204) /* 0x443c0204 */
#define SM_PLATFORM_PINCTRL_DAISYREG_OFF (SM_PLATFORM_PINCTRL_BASE + 0x408) /* 0x443c0408 */
/****************************************************************************
* Public Types
****************************************************************************/
typedef struct
{
uint32_t channel; /* channel id: SCMI_A2P, SCMI_NOTIRY, SCMI_P2A, */
uint32_t rateu;
uint32_t ratel;
uint32_t clk_id; /* clock device id */
uint32_t pclk_id; /* parent clock device id */
uint32_t div; /* clock divider */
uint32_t attributes; /* clock attributes */
uint32_t oem_config_val;
uint32_t flags;
} sm_clock_t;
typedef struct
{
uint32_t channel;
uint32_t mux_register;
uint32_t mux_mode;
uint32_t input_register;
uint32_t input_daisy;
uint32_t config_register;
uint32_t config_value;
uint32_t input_on_field;
} sm_pinctrl_t;
/* SCMI clock rate */
typedef struct
{
uint32_t lower; /* Lower 32 bits of the physical rate in Hz */
uint32_t upper; /* Upper 32 bits of the physical rate in Hz */
} scmi_clock_rate_t;
/* SCMI pin control config */
typedef struct
{
uint32_t type; /* The type of config */
uint32_t value; /* The configuration value */
} scmi_pin_config_t;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_scmi_initialize
*
* Description:
*
****************************************************************************/
void imx9_scmi_initialize(void);
int32_t imx9_scmi_clockparentget(uint32_t channel, uint32_t clockid,
uint32_t *parentid);
int32_t imx9_scmi_clockparentset(uint32_t channel, uint32_t clockid,
uint32_t parentid);
int32_t imx9_scmi_clockrateget(uint32_t channel, uint32_t clockid,
scmi_clock_rate_t *rate);
int32_t imx9_scmi_clockrateset(uint32_t channel, uint32_t clockid,
uint32_t flags, scmi_clock_rate_t rate);
int32_t imx9_scmi_clockconfigset(uint32_t channel, uint32_t clockid,
uint32_t attributes, uint32_t oem_config_val);
int32_t imx9_scmi_pinctrlconfigset(uint32_t channel, uint32_t identifier,
uint32_t attributes, const scmi_pin_config_t *configs);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_serial.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_SERIAL_H
#define __ARCH_ARM_SRC_IMX9_IMX9_SERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_IMX9_LPUART1) || defined(CONFIG_IMX9_LPUART2) || \
defined(CONFIG_IMX9_LPUART3) || defined(CONFIG_IMX9_LPUART4) || \
defined(CONFIG_IMX9_LPUART5) || defined(CONFIG_IMX9_LPUART6) || \
defined(CONFIG_IMX9_LPUART7) || defined(CONFIG_IMX9_LPUART8)
# define HAVE_UART 1
#endif
/* Assume DMA is not used on the console UART */
#undef SERIAL_HAVE_CONSOLE_RXDMA
#undef SERIAL_HAVE_CONSOLE_TXDMA
#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
# undef CONFIG_LPUART1_RXDMA
# undef CONFIG_LPUART1_TXDMA
# undef CONFIG_LPUART2_RXDMA
# undef CONFIG_LPUART2_TXDMA
# undef CONFIG_LPUART3_RXDMA
# undef CONFIG_LPUART3_TXDMA
# undef CONFIG_LPUART4_RXDMA
# undef CONFIG_LPUART4_TXDMA
# undef CONFIG_LPUART5_RXDMA
# undef CONFIG_LPUART5_TXDMA
# undef CONFIG_LPUART6_RXDMA
# undef CONFIG_LPUART6_TXDMA
# undef CONFIG_LPUART7_RXDMA
# undef CONFIG_LPUART7_TXDMA
# undef CONFIG_LPUART8_RXDMA
# undef CONFIG_LPUART8_TXDMA
#endif
/* Disable the DMA configuration on all unused LPUARTs */
#ifndef CONFIG_IMX9_LPUART1
# undef CONFIG_LPUART1_RXDMA
# undef CONFIG_LPUART1_TXDMA
#endif
#ifndef CONFIG_IMX9_LPUART2
# undef CONFIG_LPUART2_RXDMA
# undef CONFIG_LPUART2_TXDMA
#endif
#ifndef CONFIG_IMX9_LPUART3
# undef CONFIG_LPUART3_RXDMA
# undef CONFIG_LPUART3_TXDMA
#endif
#ifndef CONFIG_IMX9_LPUART4
# undef CONFIG_LPUART4_RXDMA
# undef CONFIG_LPUART4_TXDMA
#endif
#ifndef CONFIG_IMX9_LPUART5
# undef CONFIG_LPUART5_RXDMA
# undef CONFIG_LPUART5_TXDMA
#endif
#ifndef CONFIG_IMX9_LPUART6
# undef CONFIG_LPUART6_RXDMA
# undef CONFIG_LPUART6_TXDMA
#endif
#ifndef CONFIG_IMX9_LPUART8
# undef CONFIG_LPUART7_RXDMA
# undef CONFIG_LPUART7_TXDMA
#endif
/* Is RX DMA available on any (enabled) LPUART? */
#undef SERIAL_HAVE_RXDMA
#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_LPUART2_RXDMA) || \
defined(CONFIG_LPUART3_RXDMA) || defined(CONFIG_LPUART4_RXDMA) || \
defined(CONFIG_LPUART5_RXDMA) || defined(CONFIG_LPUART6_RXDMA) || \
defined(CONFIG_LPUART7_RXDMA) || defined(CONFIG_LPUART8_RXDMA)
# define SERIAL_HAVE_RXDMA 1
#endif
/* Is TX DMA available on any (enabled) LPUART? */
#undef SERIAL_HAVE_TXDMA
#if defined(CONFIG_LPUART1_TXDMA) || defined(CONFIG_LPUART2_TXDMA) || \
defined(CONFIG_LPUART3_TXDMA) || defined(CONFIG_LPUART4_TXDMA) || \
defined(CONFIG_LPUART5_TXDMA) || defined(CONFIG_LPUART6_TXDMA) || \
defined(CONFIG_LPUART7_TXDMA) || defined(CONFIG_LPUART8_TXDMA)
# define SERIAL_HAVE_TXDMA 1
#endif
/* Is RX DMA used on all (enabled) LPUARTs */
#define SERIAL_HAVE_ONLY_RXDMA 1
#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_RXDMA)
# undef SERIAL_HAVE_ONLY_RXDMA
#endif
/* Is TX DMA used on all (enabled) LPUARTs */
#define SERIAL_HAVE_ONLY_TXDMA 1
#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_TXDMA)
# undef SERIAL_HAVE_ONLY_TXDMA
#endif
#undef SERIAL_HAVE_ONLY_DMA
#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA)
#define SERIAL_HAVE_ONLY_DMA
#endif
/* Verify that DMA has been enabled and the DMA channel has been defined.
*/
#if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA)
# ifndef CONFIG_IMX9_EDMA
# error IMXRT LPUART receive or transmit DMA requires CONFIG_IMX9_EDMA
# endif
#endif
#if defined(SERIAL_HAVE_RXDMA)
/* Currently RS-485 support cannot be enabled when RXDMA is in use due to
* lack of testing.
*/
# if (defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_RS485)) || \
(defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_RS485)) || \
(defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_RS485)) || \
(defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_RS485)) || \
(defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_RS485)) || \
(defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_RS485)) || \
(defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_RS485)) || \
(defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_RS485))
# error "RXDMA and RS-485 cannot be enabled at the same time for the same LPUART"
# endif
#endif /* SERIAL_HAVE_RXDMA */
/* Currently RS-485 support cannot be enabled when TXDMA is in use due to
* lack of testing.
*/
# if (defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_LPUART1_RS485)) || \
(defined(CONFIG_LPUART2_TXDMA) && defined(CONFIG_LPUART2_RS485)) || \
(defined(CONFIG_LPUART3_TXDMA) && defined(CONFIG_LPUART3_RS485)) || \
(defined(CONFIG_LPUART4_TXDMA) && defined(CONFIG_LPUART4_RS485)) || \
(defined(CONFIG_LPUART5_TXDMA) && defined(CONFIG_LPUART5_RS485)) || \
(defined(CONFIG_LPUART6_TXDMA) && defined(CONFIG_LPUART6_RS485)) || \
(defined(CONFIG_LPUART7_TXDMA) && defined(CONFIG_LPUART7_RS485)) || \
(defined(CONFIG_LPUART8_TXDMA) && defined(CONFIG_LPUART8_RS485))
# error "TXDMA and RS-485 cannot be enabled at the same time for the same LPUART"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_SERIAL_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_start.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "barriers.h"
#include "nvic.h"
#include "mpu.h"
#include "imx9_clockconfig.h"
#include "imx9_mpuinit.h"
#include "imx9_userspace.h"
#include "imx9_lowputc.h"
#include "imx9_serial.h"
#include "imx9_start.h"
#include "imx9_gpio.h"
#ifdef CONFIG_IMX9_SCMI
#include "imx9_scmi.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IDLE_STACK ((unsigned)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
#ifdef CONFIG_DEBUG_FEATURES
#define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/* Memory Map ***************************************************************/
/* 0x2020:0000 - Start of on-chip RAM (OCRAM) and start of .data (_sdata)
* - End of .data (_edata) and start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
* start of heap. NOTE that the ARM uses a decrement before
* store stack so that the correct initial value is the end of
* the stack + 4;
* 0x2027:ffff - End of OCRAM and end of heap (assuming 512Kb OCRAM)
*
* NOTE: This assumes that all internal RAM is configured for OCRAM (vs.
* ITCM or DTCM). The RAM that holds .data and .bss is called the "Primary
* RAM". Many other configurations are possible, including configurations
* where the primary ram is in external memory. Those are not considered
* here.
*/
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) noinstrument_function;
#endif
extern const void * const _vectors[];
/****************************************************************************
* Name: imx9_tcmenable
*
* Description:
* Enable/disable tightly coupled memories. Size of tightly coupled
* memory regions is controlled by GPNVM Bits 7-8.
*
****************************************************************************/
static inline void imx9_tcmenable(void)
{
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Enabled/disabled ITCM */
#ifdef CONFIG_ARMV7M_ITCM
regval = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN;
#else
regval = getreg32(NVIC_ITCMCR);
regval &= ~NVIC_TCMCR_EN;
#endif
putreg32(regval, NVIC_ITCMCR);
/* Enabled/disabled DTCM */
#ifdef CONFIG_ARMV7M_DTCM
regval = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN;
#else
regval = getreg32(NVIC_DTCMCR);
regval &= ~NVIC_TCMCR_EN;
#endif
putreg32(regval, NVIC_DTCMCR);
ARM_DSB();
ARM_ISB();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
register const uint32_t *src;
register uint32_t *dest;
/* Make sure that interrupts are disabled and set MSP */
__asm__ __volatile__ ("CPSID i\n");
__asm__ __volatile__ ("MSR MSP, %0\n" : : "r" (IDLE_STACK) :);
/* Make sure that we use MSP from now on */
__asm__ __volatile__ ("MSR CONTROL, %0\n" : : "r" (0) :);
__asm__ __volatile__ ("ISB SY\n");
/* Make sure VECTAB is set to NuttX vector table
* and not the one from the boot ROM and have consistency
* with debugger that automatically set the VECTAB
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* If enabled reset the MPU */
mpu_early_reset();
#if defined(CONFIG_IMX9_INIT_ISRAM)
imx9_init_isram_functions();
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
{
*dest++ = 0;
}
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in OCRAM. The correct place in OCRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = (const uint32_t *)_eronly,
dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata;
)
{
*dest++ = *src++;
}
/* Copy any necessary code sections from FLASH to RAM. The correct
* destination in OCRAM is given by _sramfuncs and _eramfuncs. The
* temporary location is in flash after the data initialization code
* at _framfuncs. This should be done before imx9_clockconfig() is
* called (in case it has some dependency on initialized C variables).
*/
#ifdef CONFIG_ARCH_RAMFUNCS
for (src = (const uint32_t *)_framfuncs,
dest = (uint32_t *)_sramfuncs; dest < (uint32_t *)_eramfuncs;
)
{
*dest++ = *src++;
}
#endif
#ifdef CONFIG_ARMV7M_STACKCHECK
arm_stack_check_init();
#endif
#ifdef CONFIG_IMX9_SCMI
imx9_scmi_initialize();
#endif
/* Configure the UART so that we can get debug output as soon as possible */
imx9_clockconfig();
arm_fpuconfig();
imx9_lowsetup();
/* Enable/disable tightly coupled memories */
imx9_tcmenable();
/* Initialize onboard resources */
imx9_boardinitialize();
#ifdef CONFIG_ARM_MPU
#ifdef CONFIG_BUILD_PROTECTED
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
imx9_userspace();
#endif
/* Configure the MPU to permit user-space access to its FLASH and RAM (for
* CONFIG_BUILD_PROTECTED) or to manage cache properties in external
* memory regions.
*/
imx9_mpu_initialize();
#endif
/* Enable I- and D-Caches */
up_enable_icache();
up_enable_dcache();
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
/* Then start NuttX */
nx_start();
/* Shouldn't get here */
for (; ; );
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_start.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_START_H
#define __ARCH_ARM_SRC_IMX9_IMX9_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef CONFIG_ARCH_FAMILY_IMX9117x
/* Each IMX9117X board must provide the following initialized structure.
* This is needed to establish the initial board clocking.
*/
extern const struct clock_configuration_s g_initial_clkconfig;
#endif
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imx9_lowsetup(void);
/****************************************************************************
* Name: imx9_boardinitialize
*
* Description:
* All i.MXRT architectures must provide the following entry point. This
* entry point is called early in the initialization -- after clocking and
* memory have been configured but before caches have been enabled and
* before any devices have been initialized.
*
****************************************************************************/
void imx9_boardinitialize(void);
/****************************************************************************
* Name: imx9_init_isram_functions
*
* Description:
* Called off reset vector to reconfigure the ITCM
* and finish the FLASH to RAM Copy.
*
****************************************************************************/
#ifdef IMX9_INIT_ISRAM
void imx9_init_isram_functions(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_START_H */

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/****************************************************************************
* arch/arm/src/imx9/imx9_timerisr.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/power/pm.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "chip.h"
#include "hardware/imx9_clock.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select MCU-specific settings
*
* The SysTick timer is driven by the output of the Main Clock (main_clk).
*/
#define IMX9_SYSTICK_CLOCK BOARD_CPU_FREQUENCY
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*/
#define SYSTICK_RELOAD ((IMX9_SYSTICK_CLOCK / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int imx9_timerisr(int irq, uint32_t *regs, void *arg);
#ifdef CONFIG_PM
static void up_pm_notify(struct pm_callback_s *cb, int dowmin,
enum pm_state_e pmstate);
static int up_pm_prepare(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_PM
static struct pm_callback_s g_timer_pmcb =
{
.notify = up_pm_notify,
.prepare = up_pm_prepare,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: imx9_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int imx9_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Name: up_pm_notify
*
* Description:
* Notify the driver of new power state. This callback is called after
* all drivers have had the opportunity to prepare for the new power state.
*
* Input Parameters:
*
* cb - Returned to the driver. The driver version of the callback
* structure may include additional, driver-specific state data at
* the end of the structure.
*
* pmstate - Identifies the new PM state
*
* Returned Value:
* None - The driver already agreed to transition to the low power
* consumption state when when it returned OK to the prepare() call.
*
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_pm_notify(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate)
{
switch (pmstate)
{
case(PM_NORMAL):
{
/* Logic for PM_NORMAL goes here */
}
break;
case(PM_IDLE):
{
/* Logic for PM_IDLE goes here */
}
break;
case(PM_STANDBY):
{
/* Logic for PM_STANDBY goes here */
}
break;
case(PM_SLEEP):
{
/* Logic for PM_SLEEP goes here */
}
break;
default:
/* Should not get here */
break;
}
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize the timer
* interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
#ifdef CONFIG_PM
int ret;
#endif
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
putreg32(0, NVIC_SYSTICK_CURRENT);
/* Attach the timer interrupt vector */
irq_attach(IMX9_IRQ_SYSTICK, (xcpt_t)imx9_timerisr, NULL);
/* Enable SysTick interrupts */
regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE);
putreg32(regval, NVIC_SYSTICK_CTRL);
#ifdef CONFIG_PM
/* Register to receive power management callbacks */
ret = pm_register(&g_timer_pmcb);
DEBUGASSERT(ret == OK);
UNUSED(ret);
#endif
/* And enable the timer interrupt */
up_enable_irq(IMX9_IRQ_SYSTICK);
}

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/****************************************************************************
* arch/arm/src/imx9/imx9_userspace.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "imx9_mpuinit.h"
#include "imx9_userspace.h"
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
* Assumptions:
* The D-Cache has not yet been enabled.
*
****************************************************************************/
void imx9_userspace(void)
{
uint8_t *src;
uint8_t *dest;
uint8_t *end;
/* Clear all of user-space .bss */
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
*dest++ = 0;
}
/* Initialize all of user-space .data */
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{
*dest++ = *src++;
}
}
#endif /* CONFIG_BUILD_PROTECTED */

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/****************************************************************************
* arch/arm/src/imx9/imx9_userspace.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_USERSPACE_H
#define __ARCH_ARM_SRC_IMX9_IMX9_USERSPACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void imx9_userspace(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_USERSPACE_H */