nuttx/nuttx-update
1
2
Fork 1
Code Issues 1 Pull requests 1 Projects Releases Packages Wiki Activity Actions

NXStyle and preprocessor fixes

Browse source 
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
This commit is contained in:
Peter van der Perk 2022-07-22 17:10:22 +02:00 committed by Xiang Xiao
parent 7f3fc23dd6
commit b3590f00b3
9 changed files with 546 additions and 560 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

262
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
View file

@ -107,139 +107,139 @@
/** edma_mux0 **/
#define DMA_REQ_DISABLED0 0 ///< Channel disabled (default)
#define DMA_REQ_SIUL_0 1 ///< SIUL DMA request 0
#define DMA_REQ_SIUL_1 2 ///< SIUL DMA request 1
#define DMA_REQ_SIUL_2 3 ///< SIUL DMA request 2
#define DMA_REQ_SIUL_3 4 ///< SIUL DMA request 3
#define DMA_REQ_SIUL_4 5 ///< SIUL DMA request 4
#define DMA_REQ_SIUL_5 6 ///< SIUL DMA request 5
#define DMA_REQ_SIUL_6 7 ///< SIUL DMA request 6
#define DMA_REQ_SIUL_7 8 ///< SIUL DMA request 7
#define DMA_REQ_BCTU_FIFO1 10 ///< BCTU DMA FIFO1 request
#define DMA_REQ_BCTU_0 10 ///< BCTU DMA request 0
#define DMA_REQ_BCTU_1 11 ///< BCTU DMA request 1
#define DMA_REQ_EMIOS0_0 12 ///< eMIOS0 DMA request ch0
#define DMA_REQ_EMIOS0_1 13 ///< eMIOS0 DMA request ch1
#define DMA_REQ_EMIOS0_9 14 ///< eMIOS0 DMA request ch9
#define DMA_REQ_EMIOS0_10 15 ///< eMIOS0 DMA request ch10
#define DMA_REQ_EMIOS1_0 16 ///< eMIOS1 DMA request ch0
#define DMA_REQ_EMIOS1_1 17 ///< eMIOS1 DMA request ch1
#define DMA_REQ_EMIOS1_9 18 ///< eMIOS1 DMA request ch9
#define DMA_REQ_EMIOS1_10 19 ///< eMIOS1 DMA request ch10
#define DMA_REQ_EMIOS2_0 20 ///< eMIOS2 DMA request ch0
#define DMA_REQ_EMIOS2_1 21 ///< eMIOS2 DMA request ch1
#define DMA_REQ_EMIOS2_9 22 ///< eMIOS2 DMA request ch9
#define DMA_REQ_EMIOS2_10 23 ///< eMIOS2 DMA request ch10
#define DMA_REQ_LCU0_0 24 ///< LCU0 DMA request 0
#define DMA_REQ_LCU1_0 25 ///< LCU1 DMA request 0
#define DMA_REQ_RESERVED1 26 ///< RESERVED
#define DMA_REQ_RESERVED2 27 ///< RESERVED
#define DMA_REQ_RESERVED3 28 ///< RESERVED
#define DMA_REQ_FLEXCAN0 29 ///< FLEXCAN0 DMA request
#define DMA_REQ_FLEXCAN1 30 ///< FLEXCAN1 DMA request
#define DMA_REQ_FLEXCAN2 31 ///< FLEXCAN2 DMA request
#define DMA_REQ_FLEXCAN3 32 ///< FLEXCAN3 DMA request
#define DMA_REQ_FLEXIO_0 33 ///< FLEXIO DMA shifter0 | timer0 request
#define DMA_REQ_FLEXIO_1 34 ///< FLEXIO DMA shifter1 | timer1 request
#define DMA_REQ_FLEXIO_2 35 ///< FLEXIO DMA shifter2 | timer2 request
#define DMA_REQ_FLEXIO_3 36 ///< FLEXIO DMA shifter3 | timer3 request
#define DMA_REQ_LPUART08_TX 37 ///< LPUART0 | LPUART8 DMA transmit request
#define DMA_REQ_LPUART08_RX 38 ///< LPUART0 | LPUART8 DMA receive request
#define DMA_REQ_LPUART19_TX 39 ///< LPUART1 | LPUART9 DMA transmit request
#define DMA_REQ_LPUART19_RX 40 ///< LPUART1 | LPUART9 DMA receive request
#define DMA_REQ_LPI2C0_RX 41 ///< LPI2C0 DMA receive | receive slave request
#define DMA_REQ_LPI2C0_TX 42 ///< LPI2C0 DMA transmit | transmit slave request
#define DMA_REQ_LPSPI0_TX 43 ///< LPSPI0 DMA transmit request
#define DMA_REQ_LPSPI0_RX 44 ///< LPSPI0 DMA receive request
#define DMA_REQ_LPSPI1_TX 45 ///< LPSPI1 DMA transmit request
#define DMA_REQ_LPSPI1_RX 46 ///< LPSPI1 DMA receive request
#define DMA_REQ_LPSPI2_TX 47 ///< LPSPI2 DMA transmit request
#define DMA_REQ_LPSPI2_RX 48 ///< LPSPI2 DMA receive request
#define DMA_REQ_LPSPI3_TX 49 ///< LPSPI3 DMA transmit request
#define DMA_REQ_LPSPI3_RX 50 ///< LPSPI3 DMA receive request
#define DMA_REQ_I3C0_RX 51 ///< I3C0 DMA receive request
#define DMA_REQ_I3C0_TX 52 ///< I3C0 DMA transmit request
#define DMA_REQ_QSPI_RX 53 ///< QSPI DMA receive buffer drain request
#define DMA_REQ_QSPI_TX 54 ///< QSPI DMA transmit buffer fill request
#define DMA_REQ_SAI0_RX 55 ///< SAI0 DMA receive request
#define DMA_REQ_SAI0_TX 56 ///< SAI0 DMA transmit request
#define DMA_REQ_RESERVED4 57 ///< RESERVED
#define DMA_REQ_ADC0 58 ///< ADC0 DMA request
#define DMA_REQ_ADC1 59 ///< ADC1 DMA request
#define DMA_REQ_ADC2 60 ///< ADC2 DMA request
#define DMA_REQ_LPCMP0 61 ///< LPCMP0 DMA request
#define DMA_REQ_ENABLED0 62 ///< Always enabled
#define DMA_REQ_ENABLED1 63 ///< Always enabled */
#define DMA_REQ_DISABLED0 (0) ///< Channel disabled (default)
#define DMA_REQ_SIUL_0 (1) ///< SIUL DMA request 0
#define DMA_REQ_SIUL_1 (2) ///< SIUL DMA request 1
#define DMA_REQ_SIUL_2 (3) ///< SIUL DMA request 2
#define DMA_REQ_SIUL_3 (4) ///< SIUL DMA request 3
#define DMA_REQ_SIUL_4 (5) ///< SIUL DMA request 4
#define DMA_REQ_SIUL_5 (6) ///< SIUL DMA request 5
#define DMA_REQ_SIUL_6 (7) ///< SIUL DMA request 6
#define DMA_REQ_SIUL_7 (8) ///< SIUL DMA request 7
#define DMA_REQ_BCTU_FIFO1 (10) ///< BCTU DMA FIFO1 request
#define DMA_REQ_BCTU_0 (10) ///< BCTU DMA request 0
#define DMA_REQ_BCTU_1 (11) ///< BCTU DMA request 1
#define DMA_REQ_EMIOS0_0 (12) ///< eMIOS0 DMA request ch0
#define DMA_REQ_EMIOS0_1 (13) ///< eMIOS0 DMA request ch1
#define DMA_REQ_EMIOS0_9 (14) ///< eMIOS0 DMA request ch9
#define DMA_REQ_EMIOS0_10 (15) ///< eMIOS0 DMA request ch10
#define DMA_REQ_EMIOS1_0 (16) ///< eMIOS1 DMA request ch0
#define DMA_REQ_EMIOS1_1 (17) ///< eMIOS1 DMA request ch1
#define DMA_REQ_EMIOS1_9 (18) ///< eMIOS1 DMA request ch9
#define DMA_REQ_EMIOS1_10 (19) ///< eMIOS1 DMA request ch10
#define DMA_REQ_EMIOS2_0 (20) ///< eMIOS2 DMA request ch0
#define DMA_REQ_EMIOS2_1 (21) ///< eMIOS2 DMA request ch1
#define DMA_REQ_EMIOS2_9 (22) ///< eMIOS2 DMA request ch9
#define DMA_REQ_EMIOS2_10 (23) ///< eMIOS2 DMA request ch10
#define DMA_REQ_LCU0_0 (24) ///< LCU0 DMA request 0
#define DMA_REQ_LCU1_0 (25) ///< LCU1 DMA request 0
#define DMA_REQ_RESERVED1 (26) ///< RESERVED
#define DMA_REQ_RESERVED2 (27) ///< RESERVED
#define DMA_REQ_RESERVED3 (28) ///< RESERVED
#define DMA_REQ_FLEXCAN0 (29) ///< FLEXCAN0 DMA request
#define DMA_REQ_FLEXCAN1 (30) ///< FLEXCAN1 DMA request
#define DMA_REQ_FLEXCAN2 (31) ///< FLEXCAN2 DMA request
#define DMA_REQ_FLEXCAN3 (32) ///< FLEXCAN3 DMA request
#define DMA_REQ_FLEXIO_0 (33) ///< FLEXIO DMA shifter0 | timer0 request
#define DMA_REQ_FLEXIO_1 (34) ///< FLEXIO DMA shifter1 | timer1 request
#define DMA_REQ_FLEXIO_2 (35) ///< FLEXIO DMA shifter2 | timer2 request
#define DMA_REQ_FLEXIO_3 (36) ///< FLEXIO DMA shifter3 | timer3 request
#define DMA_REQ_LPUART08_TX (37) ///< LPUART0 | LPUART8 DMA transmit request
#define DMA_REQ_LPUART08_RX (38) ///< LPUART0 | LPUART8 DMA receive request
#define DMA_REQ_LPUART19_TX (39) ///< LPUART1 | LPUART9 DMA transmit request
#define DMA_REQ_LPUART19_RX (40) ///< LPUART1 | LPUART9 DMA receive request
#define DMA_REQ_LPI2C0_RX (41) ///< LPI2C0 DMA receive | receive slave request
#define DMA_REQ_LPI2C0_TX (42) ///< LPI2C0 DMA transmit | transmit slave request
#define DMA_REQ_LPSPI0_TX (43) ///< LPSPI0 DMA transmit request
#define DMA_REQ_LPSPI0_RX (44) ///< LPSPI0 DMA receive request
#define DMA_REQ_LPSPI1_TX (45) ///< LPSPI1 DMA transmit request
#define DMA_REQ_LPSPI1_RX (46) ///< LPSPI1 DMA receive request
#define DMA_REQ_LPSPI2_TX (47) ///< LPSPI2 DMA transmit request
#define DMA_REQ_LPSPI2_RX (48) ///< LPSPI2 DMA receive request
#define DMA_REQ_LPSPI3_TX (49) ///< LPSPI3 DMA transmit request
#define DMA_REQ_LPSPI3_RX (50) ///< LPSPI3 DMA receive request
#define DMA_REQ_I3C0_RX (51) ///< I3C0 DMA receive request
#define DMA_REQ_I3C0_TX (52) ///< I3C0 DMA transmit request
#define DMA_REQ_QSPI_RX (53) ///< QSPI DMA receive buffer drain request
#define DMA_REQ_QSPI_TX (54) ///< QSPI DMA transmit buffer fill request
#define DMA_REQ_SAI0_RX (55) ///< SAI0 DMA receive request
#define DMA_REQ_SAI0_TX (56) ///< SAI0 DMA transmit request
#define DMA_REQ_RESERVED4 (57) ///< RESERVED
#define DMA_REQ_ADC0 (58) ///< ADC0 DMA request
#define DMA_REQ_ADC1 (59) ///< ADC1 DMA request
#define DMA_REQ_ADC2 (60) ///< ADC2 DMA request
#define DMA_REQ_LPCMP0 (61) ///< LPCMP0 DMA request
#define DMA_REQ_ENABLED0 (62) ///< Always enabled
#define DMA_REQ_ENABLED1 (63) ///< Always enabled */
/** edma_mux1 **/
#define DMA_REQ_DISABLED1 DMAMUX_CHCFG_DMAMUX1 | 0 ///< Channel disabled (default)
#define DMA_REQ_SIUL_8 DMAMUX_CHCFG_DMAMUX1 | 1 ///< SIUL DMA request 8
#define DMA_REQ_SIUL_9 DMAMUX_CHCFG_DMAMUX1 | 2 ///< SIUL DMA request 9
#define DMA_REQ_SIUL_10 DMAMUX_CHCFG_DMAMUX1 | 3 ///< SIUL DMA request 10
#define DMA_REQ_SIUL_11 DMAMUX_CHCFG_DMAMUX1 | 4 ///< SIUL DMA request 11
#define DMA_REQ_SIUL_12 DMAMUX_CHCFG_DMAMUX1 | 5 ///< SIUL DMA request 12
#define DMA_REQ_SIUL_13 DMAMUX_CHCFG_DMAMUX1 | 6 ///< SIUL DMA request 13
#define DMA_REQ_SIUL_14 DMAMUX_CHCFG_DMAMUX1 | 7 ///< SIUL DMA request 14
#define DMA_REQ_SIUL_15 DMAMUX_CHCFG_DMAMUX1 | 8 ///< SIUL DMA request 15
#define DMA_REQ_BCTU_FIFO2 DMAMUX_CHCFG_DMAMUX1 | 9 ///< BCTU DMA FIFO2 request
#define DMA_REQ_BCTU_2 DMAMUX_CHCFG_DMAMUX1 | 10 ///< BCTU DMA request 2
#define DMA_REQ_EMIOS0_16 DMAMUX_CHCFG_DMAMUX1 | 11 ///< eMIOS0 DMA request ch16
#define DMA_REQ_EMIOS0_17 DMAMUX_CHCFG_DMAMUX1 | 12 ///< eMIOS0 DMA request ch17
#define DMA_REQ_EMIOS0_18 DMAMUX_CHCFG_DMAMUX1 | 13 ///< eMIOS0 DMA request ch18
#define DMA_REQ_EMIOS0_19 DMAMUX_CHCFG_DMAMUX1 | 14 ///< eMIOS0 DMA request ch19
#define DMA_REQ_EMIOS1_16 DMAMUX_CHCFG_DMAMUX1 | 15 ///< eMIOS1 DMA request ch16
#define DMA_REQ_EMIOS1_17 DMAMUX_CHCFG_DMAMUX1 | 16 ///< eMIOS1 DMA request ch17
#define DMA_REQ_EMIOS1_18 DMAMUX_CHCFG_DMAMUX1 | 17 ///< eMIOS1 DMA request ch18
#define DMA_REQ_EMIOS1_19 DMAMUX_CHCFG_DMAMUX1 | 18 ///< eMIOS1 DMA request ch19
#define DMA_REQ_EMIOS2_16 DMAMUX_CHCFG_DMAMUX1 | 19 ///< eMIOS2 DMA request ch16
#define DMA_REQ_EMIOS2_17 DMAMUX_CHCFG_DMAMUX1 | 20 ///< eMIOS2 DMA request ch17
#define DMA_REQ_EMIOS2_18 DMAMUX_CHCFG_DMAMUX1 | 21 ///< eMIOS2 DMA request ch18
#define DMA_REQ_EMIOS2_19 DMAMUX_CHCFG_DMAMUX1 | 22 ///< eMIOS2 DMA request ch19
#define DMA_REQ_LCU0_1 DMAMUX_CHCFG_DMAMUX1 | 23 ///< LCU0 DMA request 1
#define DMA_REQ_LCU0_2 DMAMUX_CHCFG_DMAMUX1 | 24 ///< LCU1 DMA request 2
#define DMA_REQ_LCU1_1 DMAMUX_CHCFG_DMAMUX1 | 25 ///< LCU1 DMA request 1
#define DMA_REQ_LCU1_2 DMAMUX_CHCFG_DMAMUX1 | 26 ///< LCU1 DMA request 2
#define DMA_REQ_ENET_0 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[0] DMA request
#define DMA_REQ_ENET_1 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[1] DMA request
#define DMA_REQ_ENET_2 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[2] DMA request
#define DMA_REQ_ENET_3 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[3] DMA request
#define DMA_REQ_RESERVED5 DMAMUX_CHCFG_DMAMUX1 | 28 ///< RESERVED
#define DMA_REQ_RESERVED6 DMAMUX_CHCFG_DMAMUX1 | 29 ///< RESERVED
#define DMA_REQ_FLECAN4 DMAMUX_CHCFG_DMAMUX1 | 30 ///< FLEXCAN4 DMA request
#define DMA_REQ_FLECAN5 DMAMUX_CHCFG_DMAMUX1 | 31 ///< FLEXCAN5 DMA request
#define DMA_REQ_RESERVED7 DMAMUX_CHCFG_DMAMUX1 | 32 ///< RESERVED
#define DMA_REQ_RESERVED8 DMAMUX_CHCFG_DMAMUX1 | 33 ///< RESERVED
#define DMA_REQ_FLEXIO_4 DMAMUX_CHCFG_DMAMUX1 | 34 ///< FLEXIO DMA shifter4 | timer4 request
#define DMA_REQ_FLEXIO_5 DMAMUX_CHCFG_DMAMUX1 | 35 ///< FLEXIO DMA shifter5 | timer5 request
#define DMA_REQ_FLEXIO_6 DMAMUX_CHCFG_DMAMUX1 | 36 ///< FLEXIO DMA shifter6 | timer6 request
#define DMA_REQ_FLEXIO_7 DMAMUX_CHCFG_DMAMUX1 | 37 ///< FLEXIO DMA shifter7 | timer7 request
#define DMA_REQ_LPUART210_TX DMAMUX_CHCFG_DMAMUX1 | 38 ///< LPUART2 | LPUART10 DMA transmit request
#define DMA_REQ_LPUART210_RX DMAMUX_CHCFG_DMAMUX1 | 39 ///< LPUART2 | LPUART10 DMA receive request
#define DMA_REQ_LPUART311_TX DMAMUX_CHCFG_DMAMUX1 | 40 ///< LPUART3 | LPUART11 DMA transmit request
#define DMA_REQ_LPUART311_RX DMAMUX_CHCFG_DMAMUX1 | 41 ///< LPUART3 | LPUART11 DMA receive request
#define DMA_REQ_LPUART412_TX DMAMUX_CHCFG_DMAMUX1 | 42 ///< LPUART4 | LPUART12 DMA transmit request
#define DMA_REQ_LPUART412_RX DMAMUX_CHCFG_DMAMUX1 | 43 ///< LPUART4 | LPUART12 DMA receive request
#define DMA_REQ_LPUART513_TX DMAMUX_CHCFG_DMAMUX1 | 44 ///< LPUART5 | LPUART13 DMA transmit request
#define DMA_REQ_LPUART513_RX DMAMUX_CHCFG_DMAMUX1 | 45 ///< LPUART5 | LPUART13 DMA receive request
#define DMA_REQ_LPUART614_TX DMAMUX_CHCFG_DMAMUX1 | 46 ///< LPUART6 | LPUART14 DMA transmit request
#define DMA_REQ_LPUART614_RX DMAMUX_CHCFG_DMAMUX1 | 47 ///< LPUART6 | LPUART14 DMA receive request
#define DMA_REQ_LPUART715_TX DMAMUX_CHCFG_DMAMUX1 | 48 ///< LPUART7 | LPUART15 DMA transmit request
#define DMA_REQ_LPUART715_RX DMAMUX_CHCFG_DMAMUX1 | 49 ///< LPUART7 | LPUART15 DMA receive request
#define DMA_REQ_LPI2C1_RX DMAMUX_CHCFG_DMAMUX1 | 50 ///< LPI2C1 DMA receive | receive slave request
#define DMA_REQ_LPI2C1_TX DMAMUX_CHCFG_DMAMUX1 | 51 ///< LPI2C1 DMA transmit | transmit slave request
#define DMA_REQ_LPSPI4_TX DMAMUX_CHCFG_DMAMUX1 | 52 ///< LPSPI4 DMA transmit request
#define DMA_REQ_LPSPI4_RX DMAMUX_CHCFG_DMAMUX1 | 53 ///< LPSPI4 DMA receive request
#define DMA_REQ_LPSPI5_TX DMAMUX_CHCFG_DMAMUX1 | 54 ///< LPSPI5 DMA transmit request
#define DMA_REQ_LPSPI5_RX DMAMUX_CHCFG_DMAMUX1 | 55 ///< LPSPI5 DMA receive request
#define DMA_REQ_SAI1_RX DMAMUX_CHCFG_DMAMUX1 | 56 ///< SAI1 DMA RX request
#define DMA_REQ_SAI1_TX DMAMUX_CHCFG_DMAMUX1 | 57 ///< SAI1 DMA TX request
#define DMA_REQ_RESERVED9 DMAMUX_CHCFG_DMAMUX1 | 58 ///< RESERVED
#define DMA_REQ_RESERVED10 DMAMUX_CHCFG_DMAMUX1 | 59 ///< RESERVED
#define DMA_REQ_LPCMP1 DMAMUX_CHCFG_DMAMUX1 | 60 ///< LPCMP1 DMA request
#define DMA_REQ_LPCMP2 DMAMUX_CHCFG_DMAMUX1 | 61 ///< LPCMP2 DMA request
#define DMA_REQ_ENABLED2 DMAMUX_CHCFG_DMAMUX1 | 62 ///< Always enabled
#define DMA_REQ_ENABLED3 DMAMUX_CHCFG_DMAMUX1 | 63 ///< Always enabled
#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) ///< Channel disabled (default)
#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) ///< SIUL DMA request 8
#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) ///< SIUL DMA request 9
#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) ///< SIUL DMA request 10
#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) ///< SIUL DMA request 11
#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) ///< SIUL DMA request 12
#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) ///< SIUL DMA request 13
#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) ///< SIUL DMA request 14
#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) ///< SIUL DMA request 15
#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) ///< BCTU DMA FIFO2 request
#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) ///< BCTU DMA request 2
#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) ///< eMIOS0 DMA request ch16
#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) ///< eMIOS0 DMA request ch17
#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) ///< eMIOS0 DMA request ch18
#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) ///< eMIOS0 DMA request ch19
#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) ///< eMIOS1 DMA request ch16
#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) ///< eMIOS1 DMA request ch17
#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) ///< eMIOS1 DMA request ch18
#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) ///< eMIOS1 DMA request ch19
#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) ///< eMIOS2 DMA request ch16
#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) ///< eMIOS2 DMA request ch17
#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) ///< eMIOS2 DMA request ch18
#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) ///< eMIOS2 DMA request ch19
#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) ///< LCU0 DMA request 1
#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) ///< LCU1 DMA request 2
#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) ///< LCU1 DMA request 1
#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) ///< LCU1 DMA request 2
#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[0] DMA request
#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[1] DMA request
#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[2] DMA request
#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[3] DMA request
#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) ///< RESERVED
#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) ///< RESERVED
#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) ///< FLEXCAN4 DMA request
#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) ///< FLEXCAN5 DMA request
#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) ///< RESERVED
#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) ///< RESERVED
#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) ///< FLEXIO DMA shifter4 | timer4 request
#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) ///< FLEXIO DMA shifter5 | timer5 request
#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) ///< FLEXIO DMA shifter6 | timer6 request
#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) ///< FLEXIO DMA shifter7 | timer7 request
#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) ///< LPUART2 | LPUART10 DMA transmit request
#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) ///< LPUART2 | LPUART10 DMA receive request
#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) ///< LPUART3 | LPUART11 DMA transmit request
#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) ///< LPUART3 | LPUART11 DMA receive request
#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) ///< LPUART4 | LPUART12 DMA transmit request
#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) ///< LPUART4 | LPUART12 DMA receive request
#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) ///< LPUART5 | LPUART13 DMA transmit request
#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) ///< LPUART5 | LPUART13 DMA receive request
#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) ///< LPUART6 | LPUART14 DMA transmit request
#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) ///< LPUART6 | LPUART14 DMA receive request
#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) ///< LPUART7 | LPUART15 DMA transmit request
#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) ///< LPUART7 | LPUART15 DMA receive request
#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) ///< LPI2C1 DMA receive | receive slave request
#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) ///< LPI2C1 DMA transmit | transmit slave request
#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) ///< LPSPI4 DMA transmit request
#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) ///< LPSPI4 DMA receive request
#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) ///< LPSPI5 DMA transmit request
#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) ///< LPSPI5 DMA receive request
#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) ///< SAI1 DMA RX request
#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) ///< SAI1 DMA TX request
#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) ///< RESERVED
#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) ///< RESERVED
#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) ///< LPCMP1 DMA request
#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) ///< LPCMP2 DMA request
#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) ///< Always enabled
#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) ///< Always enabled
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */

14
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
View file

@ -1311,13 +1311,13 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
@ -1328,7 +1328,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
/* TCDn Transfer Size (TCDn_NBYTES) */
@ -1364,7 +1364,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
@ -1386,7 +1386,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
/* Bit 13: Reserved */
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
@ -1402,7 +1402,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
#define EDMA_TCD_BITER_LINKCH(n) ((n << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/****************************************************************************

722
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
View file

File diff suppressed because it is too large Load diff

8
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
View file

@ -31,14 +31,6 @@
#include "mr-canhubk3.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Public Functions
****************************************************************************/

29
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
View file

@ -65,21 +65,22 @@ void board_userled(int led, bool ledon)
{
uint32_t ledcfg;
if (led == BOARD_LED_R)
switch (ledcfg)
{
ledcfg = GPIO_LED_R;
}
else if (led == BOARD_LED_G)
{
ledcfg = GPIO_LED_G;
}
else if (led == BOARD_LED_B)
{
ledcfg = GPIO_LED_B;
}
else
{
return;
case BOARD_LED_R:
ledcfg = GPIO_LED_R;
break;
case BOARD_LED_G:
ledcfg = GPIO_LED_G;
break;
case BOARD_LED_B:
ledcfg = GPIO_LED_B;
break;
default:
return;
}
/* Invert output, an output of '0' illuminates the LED */

8
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
View file

@ -31,14 +31,6 @@
#include "s32k344evb.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Public Functions
****************************************************************************/

53
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
View file

@ -70,33 +70,34 @@ void board_userled(int led, bool ledon)
{
uint32_t ledcfg;
if (led == BOARD_LED0_R)
switch (ledcfg)
{
ledcfg = GPIO_LED0_R;
}
else if (led == BOARD_LED0_G)
{
ledcfg = GPIO_LED0_G;
}
else if (led == BOARD_LED0_B)
{
ledcfg = GPIO_LED0_B;
}
else if (led == BOARD_LED1_R)
{
ledcfg = GPIO_LED1_R;
}
else if (led == BOARD_LED1_G)
{
ledcfg = GPIO_LED1_G;
}
else if (led == BOARD_LED1_B)
{
ledcfg = GPIO_LED1_B;
}
else
{
return;
case BOARD_LED0_R:
ledcfg = GPIO_LED0_R;
break;
case BOARD_LED0_G:
ledcfg = GPIO_LED0_G;
break;
case BOARD_LED0_B:
ledcfg = GPIO_LED0_B;
break;
case BOARD_LED1_R:
ledcfg = GPIO_LED1_R;
break;
case BOARD_LED1_G:
ledcfg = GPIO_LED1_G;
break;
case BOARD_LED1_B:
ledcfg = GPIO_LED1_B;
break;
default:
return;
}
/* An output of '1' illuminates the LED */

8
drivers/mtd/mx25rxx.c
View file

@ -101,9 +101,9 @@
#define MX25R_JEDEC_MANUFACTURER 0xc2 /* Macronix manufacturer ID */
#ifdef CONFIG_MX25RXX_LXX
#define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
# define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
#else
#define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
# define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
#endif
#define MX25R_JEDEC_MX25R6435F_CAPACITY 0x17 /* MX25R6435F memory capacity */
#define MX25R_JEDEC_MX25R8035F_CAPACITY 0x14 /* MX25R8035F memory capacity */
@ -118,9 +118,9 @@
#define MX25R6435F_PAGE_SIZE (256)
#ifdef CONFIG_MX25RXX_PAGE128
#define MX25R6435F_PAGE_SHIFT (7)
# define MX25R6435F_PAGE_SHIFT (7)
#else
#define MX25R6435F_PAGE_SHIFT (8)
# define MX25R6435F_PAGE_SHIFT (8)
#endif
/* Status register bit definitions */

2
net/can/can_input.c
View file

@ -161,7 +161,7 @@ int can_input(struct net_driver_s *dev)
{
conn = can_nextconn(conn);
if (conn && (conn->dev == 0x0 || dev == conn->dev))
if (conn && (conn->dev == NULL || dev == conn->dev))
{
uint16_t flags;