arch/risc-v: Refine riscv_testset.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
2b60468845
commit
c15195b126
8 changed files with 36 additions and 20 deletions
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@ -146,6 +146,7 @@ config ARCH_RV_ISA_M
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config ARCH_RV_ISA_A
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bool
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default n
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select ARCH_HAVE_TESTSET
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config ARCH_RV_ISA_C
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bool
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@ -162,11 +163,6 @@ config ARCH_RV_ISA_D
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depends on ARCH_RV_ISA_F
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select ARCH_HAVE_DPFPU
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config ARCH_RV32I
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bool
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default n
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select ARCH_HAVE_SETJMP
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config ARCH_FAMILY
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string
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default "rv32" if ARCH_RV32
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@ -25,6 +25,8 @@ HEAD_ASRC = bl602_vectors.S
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# Specify our general Assembly files
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CHIP_ASRCS = bl602_head.S riscv_syscall.S bl602_entry.S
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CMN_ASRCS += riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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CMN_CSRCS += riscv_createstack.c riscv_exit.c
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@ -25,6 +25,8 @@ HEAD_ASRC = c906_vectors.S
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# Specify our general Assembly files
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CHIP_ASRCS = c906_head.S
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CMN_ASRCS += riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/rv64gc/riscv_testset.S
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* arch/risc-v/src/common/riscv_testset.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -25,12 +25,20 @@
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#include <nuttx/config.h>
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#include <arch/spinlock.h>
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.file "arm_testset.S"
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.file "riscv_testset.S"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_ARCH_RV32
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#define LR_INST lr.w
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#define SC_INST sc.w
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#else
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#define LR_INST lr.d
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#define SC_INST sc.d
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#endif
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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@ -78,29 +86,29 @@
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up_testset:
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li a1, SP_LOCKED
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li a1, SP_LOCKED
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/* Test if the spinlock is locked or not */
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retry:
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lr.d a2, (a0) /* Test if spinlock is locked or not */
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beq a2, a1, locked /* Already locked? Go to locked: */
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LR_INST a2, (a0) /* Test if spinlock is locked or not */
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beq a2, a1, locked /* Already locked? Go to locked: */
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/* Not locked ... attempt to lock it */
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sc.d a2, a1, (a0) /* Attempt to set the locked state (a1) to (a0) */
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bnez a2, retry /* a2 will not be zero, if sc.b failed, try again */
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SC_INST a2, a1, (a0) /* Attempt to set the locked state (a1) to (a0) */
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bnez a2, retry /* a2 will not be zero, if sc.b failed, try again */
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/* Lock acquired -- return SP_UNLOCKED */
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fence /* Required before accessing protected resource */
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li a0, SP_UNLOCKED
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jr ra
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fence /* Required before accessing protected resource */
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li a0, SP_UNLOCKED
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jr ra
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/* Lock not acquired -- return SP_LOCKED */
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locked:
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li a0, SP_LOCKED
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jr ra
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li a0, SP_LOCKED
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jr ra
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.size up_testset, . - up_testset
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.end
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@ -25,6 +25,8 @@ HEAD_ASRC = fe310_vectors.S
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# Specify our general Assembly files
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CHIP_ASRCS = fe310_head.S riscv_syscall.S
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CMN_ASRCS += riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
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@ -25,6 +25,8 @@ HEAD_ASRC = litex_vectors.S
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# Specify our general Assembly files
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CHIP_ASRCS = litex_head.S riscv_syscall.S
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CMN_ASRCS += riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
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@ -25,6 +25,8 @@ HEAD_ASRC = mpfs_vectors.S
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# Specify our general Assembly files
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CHIP_ASRCS = mpfs_head.S
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CMN_ASRCS += riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c
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@ -25,6 +25,8 @@ HEAD_ASRC = qemu_rv32_head.S
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# Specify our general Assembly files
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CHIP_ASRCS = qemu_rv32_vectors.S riscv_syscall.S
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CMN_ASRCS += riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
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@ -39,15 +41,15 @@ CMN_CSRCS += riscv_checkstack.c
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endif
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ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
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CMN_CSRCS += riscv_vfork.c
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CMN_CSRCS += riscv_vfork.c
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endif
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ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
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CMN_CSRCS += riscv_tls.c
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CMN_CSRCS += riscv_tls.c
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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CMN_ASRCS += riscv_fpu.S
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CMN_ASRCS += riscv_fpu.S
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endif
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# Specify our C code within this directory to be included
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