mpfs: clockconfig: add clock initialiation sequence
Add clock initialization sequence especially for systems containing no bootloader. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit is contained in:
Eero Nurkkala
Xiang Xiao
parent
bc72ccdf6a
commit
c34b9620db
2 changed files with 586 additions and 11 deletions
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@ -30,9 +30,12 @@
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include <arch/board/board_liberodefs.h>
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#include "mpfs_clockconfig.h"
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#include "riscv_arch.h"
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#include "hardware/mpfs_sysreg.h"
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#include "hardware/mpfs_sgmii.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -40,16 +43,595 @@
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#define OSC_FREQ 80000000UL
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/* Read & Write Memory barrier */
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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#define mb() RISCV_FENCE(iorw, iorw)
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/* Module reset / clock enable defines */
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#define MPFS_SYSREG_SOFT_RESET_CR (MPFS_SYSREG_BASE + \
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MPFS_SYSREG_SOFT_RESET_CR_OFFSET)
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#define MPFS_SYSREG_SUBBLK_CLOCK_CR (MPFS_SYSREG_BASE + \
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MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET)
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/* PLL bit defines */
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#define PLL_CTRL_LOCK_BIT (1 << 25)
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#define PLL_INIT_AND_OUT_OF_RESET 0x3
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#define PLL_CTRL_REG_POWERDOWN_B_MASK 0x1
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/* eNVM clock frequency settled poll bit */
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#define ENVM_CR_CLOCK_OKAY_MASK (1 << 6)
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/* Silicon version lookup bitmasks */
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#define ARO_REF_PCODE_MASK 0x3f
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#define ARO_REF_PCODE_REVC_THRESHOLD 0x40
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#define MIN_DLL_90_CODE_VALUE_INDICATING_TT_PART_REVB 13
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#define MPFS_SCB_ACCESS_CONFIG ((160 << 8) | (0x80))
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/* Poll loop default retries */
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#define MPFS_DEFAULT_RETRIES 0xffff
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/* Eye width defines */
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#define EARLY_EYE_WIDTH_PART_PART_NOT_DETERMINED 6
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#define EARLY_EYE_WIDTH_PART_REVC_OR_LATER 6
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#define EARLY_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST 7
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#define EARLY_EYE_WIDTH_SS_PART_REVB 5
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#define EARLY_TT_PART_REVB 6
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#define LATE_EYE_WIDTH_PART_NOT_DETERMINED 7
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#define LATE_EYE_WIDTH_PART_REVC_OR_LATER 7
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#define LATE_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST 6
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#define LATE_EYE_WIDTH_SS_PART_REVB 6
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#define LATE_TT_PART_REVB 7
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#define SHIFT_TO_REG_RX0_EYEWIDTH 21
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#define REG_RX0_EYEWIDTH_P_MASK (~(0x7 << SHIFT_TO_REG_RX0_EYEWIDTH))
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#define SHIFT_TO_REG_RX1_EYEWIDTH 21
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#define REG_RX1_EYEWIDTH_P_MASK (~(0x7 << SHIFT_TO_REG_RX1_EYEWIDTH))
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#define SHIFT_TO_CH0_N_EYE_VALUE 26
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#define SHIFT_TO_CH1_N_EYE_VALUE 29
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#define N_EYE_MASK 0x03ffffff
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#define REG_RX0_EN_FLAG_N (1 << 31)
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#define REG_RX1_EN_FLAG_N (1 << 31)
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#define MSSIO_CONTROL_CR_MSS_IO_EN (1 << 13)
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#define MSSIO_CONTROL_CR_MSS_FLASH_VALID (1 << 12)
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#define MSSIO_CONTROL_CR_MSS_CORE_UP (1 << 11)
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#define MSSIO_CONTROL_CR_MSS_DCE (0x7 << 8)
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#define SGMII_NV_MAP_DDR_PHY (1 << 0)
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#define SGMII_ARO_PLL0_LOCK (1 << 7)
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/* MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL bit defines */
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#define SGMII_REG_LANE1_SOFT_RESET_PERIPH (1 << 14)
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#define SGMII_REG_LANE0_SOFT_RESET_PERIPH (1 << 13)
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#define SGMII_REG_PVT_SOFT_RESET_PERIPH (1 << 10)
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/* MPFS_IOSCB_CALIB_SGMII_IOC_REG0 */
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#define SGMII_IOC_REG0_REG_CALIB_LOCK (1 << 14)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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enum part_type_e
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{
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PART_NOT_DETERMINED = 0x00,
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PART_REVC_OR_LATER = 0x01,
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SS_PART_REVB = 0x02,
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TT_PART_REVB = 0x03,
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PART_TYPE_ARRAY_SIZE = 0x04,
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static uint64_t g_cpu_clock = MPFS_MSS_COREPLEX_CPU_CLK;
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static uint64_t g_cpu_clock = MPFS_MSS_EXT_SGMII_REF_CLK;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: mpfs_wait_cycles
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*
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* Description:
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* Wait n number of cycles. This mimics the vendor wait loops in the
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* reference code.
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*
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* Parameters:
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* n - number of cycles to loop
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*
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****************************************************************************/
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static void mpfs_wait_cycles(uint32_t n)
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{
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volatile uint32_t count = n;
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while (--count);
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}
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/****************************************************************************
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* Name: mpfs_set_rtc_divisor
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*
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* Description:
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* Set the RTC divisor based on MSS Configurator setting.
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* This will always be calculated so that RTC clock is 1MHz.
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*
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****************************************************************************/
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static void mpfs_set_rtc_divisor(void)
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{
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/* Disable RTC clock */
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modifyreg32(MPFS_SYSREG_RTC_CLOCK_CR, SYSREG_RTC_CLOCK_CR_ENABLE, 0);
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putreg32((LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK / \
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LIBERO_SETTING_MSS_RTC_TOGGLE_CLK),
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MPFS_SYSREG_RTC_CLOCK_CR);
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/* Enable RTC Clock */
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modifyreg32(MPFS_SYSREG_RTC_CLOCK_CR, 0, SYSREG_RTC_CLOCK_CR_ENABLE);
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}
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/****************************************************************************
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* Name: mpfs_sgmii_mux_config
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*
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* Description:
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* Soft resets and loads RPC settings.
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*
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****************************************************************************/
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void mpfs_sgmii_mux_config(void)
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{
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/* This will load the APB registers, set via SGMII TIP */
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putreg32(1, MPFS_IOSCB_SGMII_MUX_SOFT_RESET);
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}
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/****************************************************************************
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* Name: mpfs_sgmii_pll_config_scb
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*
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* Description:
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* Soft resets and loads RPC settings
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*
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****************************************************************************/
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static void mpfs_sgmii_pll_config_scb(void)
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{
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/* Set the NV map reset. This will load the APB registers, set
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* via SGMII TIP.
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*/
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putreg32(1, MPFS_IOSCB_SGMII_PLL_SOFT_RESET);
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}
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/****************************************************************************
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* Name: mpfs_set_early_late_thresholds
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*
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* Description:
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* Sets the N and P eye width values.
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*
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* Parameters:
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* n_late_threshold - N eye width
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* p_early_threshold - P eye width
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*
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****************************************************************************/
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static void mpfs_set_early_late_thresholds(uint8_t n_late_threshold,
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uint8_t p_early_threshold)
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{
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uint32_t n_eye_values;
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uint32_t p_eye_value;
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/* Set the N eye width value, bits 31:29 for CH1, bits 28:26
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* for CH0 in spare control (N eye width value)
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*/
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n_eye_values = (n_late_threshold << SHIFT_TO_CH0_N_EYE_VALUE);
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n_eye_values |= (n_late_threshold << SHIFT_TO_CH1_N_EYE_VALUE);
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putreg32((LIBERO_SETTING_SPARE_CNTL & N_EYE_MASK) | n_eye_values,
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MPFS_CFG_DDR_SGMII_PHY_SPARE_STAT);
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/* Set CH0/CH1 P values */
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p_eye_value = (p_early_threshold << SHIFT_TO_REG_RX0_EYEWIDTH);
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putreg32(((LIBERO_SETTING_CH0_CNTL & REG_RX0_EYEWIDTH_P_MASK) |
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p_eye_value) | REG_RX0_EN_FLAG_N,
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MPFS_CFG_DDR_SGMII_PHY_CH0_CNTL);
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putreg32(((LIBERO_SETTING_CH1_CNTL & REG_RX1_EYEWIDTH_P_MASK) |
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p_eye_value) | REG_RX1_EN_FLAG_N,
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MPFS_CFG_DDR_SGMII_PHY_CH1_CNTL);
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}
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/****************************************************************************
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* Name: mss_mux_pre_mss_pll_config
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*
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* Description:
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* Apply required reference clks to PLL, configure PLL and wait for lock.
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*
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****************************************************************************/
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static void mss_mux_pre_mss_pll_config(void)
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{
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putreg32(LIBERO_SETTING_MSS_PLL_CKMUX, MPFS_IOSCB_MSS_MUX_PLL_CKMUX);
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putreg32(LIBERO_SETTING_SGMII_CLK_XCVR, MPFS_IOSCB_SGMII_MUX_CLK_XCVR);
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putreg32(LIBERO_SETTING_MSS_BCLKMUX, MPFS_IOSCB_MSS_MUX_BCLKMUX);
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putreg32(LIBERO_SETTING_MSS_FMETER_ADDR, MPFS_IOSCB_MSS_MUX_FMETER_ADDR);
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putreg32(LIBERO_SETTING_MSS_FMETER_DATAW, MPFS_IOSCB_MSS_MUX_FMETER_DATAW);
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putreg32(LIBERO_SETTING_MSS_FMETER_DATAR, MPFS_IOSCB_MSS_MUX_FMETER_DATAR);
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mpfs_wait_cycles(400);
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}
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/****************************************************************************
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* Name: mss_mux_pre_mss_pll_config
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*
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* Description:
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* We must run this code from RAM, as we need to modify the clock of the
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* eNVM. The first thing we do is change the eNVM clock, to prevent L1
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* cache accessing eNVM as it will do as we approach the return
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* instruction. The mb() makes sure order of processing is not changed by
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* the compiler
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*
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* Assumptions:
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* This should be run outside of eNVM, although apparently it works even
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* from eNVM.
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*
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****************************************************************************/
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__attribute__((section(".ram"))) void mpfs_mux_post_mss_pll_config(void)
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{
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/* Modify the eNVM clock, so it matches the new MSS clock
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*
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* 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz
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* 11 will generate a 40ns period 25MHz clock if the AHB clock is 250MHz
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* 15 will generate a 40ns period 25MHz clock if the AHB clock is 400MHz
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*/
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putreg32(LIBERO_SETTING_MSS_ENVM_CR, MPFS_SYSREG_ENVM_CR);
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/* Make sure we change clock in eNVM first so all is ready by the time we
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* leave.
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*/
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mb();
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/* When changing the eNVM clock frequency, there is a bit
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* (ENVM_CR_clock_okay) in the eNVM_CR which can be polled to check that
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* the frequency change has happened before bumping up the AHB frequency.
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*/
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while ((getreg32(MPFS_SYSREG_ENVM_CR) & ENVM_CR_CLOCK_OKAY_MASK) != \
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ENVM_CR_CLOCK_OKAY_MASK);
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/* Change the MSS clock as required */
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putreg32(LIBERO_SETTING_MSS_CLOCK_CONFIG_CR, MPFS_SYSREG_CLOCK_CONFIG_CR);
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/* Feed clock from MSS PLL to MSS, using glitchless mux */
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putreg32(LIBERO_SETTING_MSS_MSSCLKMUX, MPFS_IOSCB_MSS_MUX_MSSCLKMUX);
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/* Change the RTC clock divisor, so RTC clock is 1MHz */
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mpfs_set_rtc_divisor();
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}
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/****************************************************************************
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* Name: mpfs_pll_config
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*
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* Description:
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* On startup, MSS is supplied with 80MHz SCB clock.
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* Power on procedure for the MSS PLL clock:
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*
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* During POR:
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* Keep PLL in power down mode. Powerdown_int_b = 0
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*
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* After POR, Power-On steps:
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* 1) mssclk_mux_sel_int = 0 & powerdown_int_b = 0 & clk_standby_sel = 0
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* MSS PLL is powered down and selects clk_standby = scb_clk
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* 2) PFC Processor writes powerdown_int_b = 1 & divq0_int_en = 1
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* MSS PLL powers up, then lock asserts when locked.
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* 3) PFC Processor switches mssclk_mux_sel_int = 1
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* MSS PLL clock is now sent to MSS.
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* 4) When BOOT authentication is complete
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* a. PFC processor writes mssclk_mux_sel_int = 0 to select
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* clk_standby.
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* b. PFC Processor writes powerdown_int_b = 0 to power down the PLL
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* c. MSS Processor writes new parameters to the MSS PLL
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* 5) MSS Processor writes powerdown_int_b = 1
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* Start up the PLL with new parameters.
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* Wait for PLL to lock.
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* 6) MSS Processor enables all 4 PLL outputs.
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* 7) MSS Processor writes mssclk_mux_sel_int = 1 to select the MSS PLL
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* clock.
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*
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****************************************************************************/
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static int mpfs_pll_config(void)
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{
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uint32_t retries = MPFS_DEFAULT_RETRIES;
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putreg32(PLL_INIT_AND_OUT_OF_RESET, MPFS_IOSCB_MSS_PLL_SOFT_RESET);
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putreg32(PLL_INIT_AND_OUT_OF_RESET, MPFS_IOSCB_DDR_PLL_SOFT_RESET);
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putreg32(LIBERO_SETTING_MSS_PLL_CTRL & ~(PLL_CTRL_REG_POWERDOWN_B_MASK),
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MPFS_IOSCB_MSS_PLL_CTRL);
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putreg32(LIBERO_SETTING_MSS_PLL_REF_FB, MPFS_IOSCB_MSS_PLL_REF_FB);
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putreg32(LIBERO_SETTING_MSS_PLL_DIV_0_1, MPFS_IOSCB_MSS_PLL_DIV_0_1);
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putreg32(LIBERO_SETTING_MSS_PLL_DIV_2_3, MPFS_IOSCB_MSS_PLL_DIV_2_3);
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putreg32(LIBERO_SETTING_MSS_PLL_CTRL2, MPFS_IOSCB_MSS_PLL_CTRL2);
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putreg32(LIBERO_SETTING_MSS_PLL_FRACN, MPFS_IOSCB_MSS_PLL_FRACN);
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putreg32(LIBERO_SETTING_MSS_SSCG_REG_0, MPFS_IOSCB_MSS_PLL_SSCG_REG_0);
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putreg32(LIBERO_SETTING_MSS_SSCG_REG_1, MPFS_IOSCB_MSS_PLL_SSCG_REG_1);
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putreg32(LIBERO_SETTING_MSS_SSCG_REG_2, MPFS_IOSCB_MSS_PLL_SSCG_REG_2);
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putreg32(LIBERO_SETTING_MSS_SSCG_REG_3, MPFS_IOSCB_MSS_PLL_SSCG_REG_3);
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/* PLL phase register */
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putreg32(LIBERO_SETTING_MSS_PLL_PHADJ, MPFS_IOSCB_MSS_PLL_PHADJ);
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/* Write powerdown_int_b = 1, start up the PLL with new parameters
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* and wait for it to lock.
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*/
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mss_mux_pre_mss_pll_config();
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putreg32(LIBERO_SETTING_MSS_PLL_CTRL | 0x01, MPFS_IOSCB_MSS_PLL_CTRL);
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/* Start up the PLL with new parameters. Wait for it to lock. */
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while (!(getreg32(MPFS_IOSCB_MSS_PLL_CTRL) & PLL_CTRL_LOCK_BIT) &&
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--retries);
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DEBUGASSERT(retries > 0);
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/* Processor enables all 4 PLL outputs. Set mssclk_mux_sel_int = 1 to
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* select the MSS PLL clock.
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*/
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mpfs_mux_post_mss_pll_config();
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return 0;
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}
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/****************************************************************************
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* Name: mpfs_sgmii_setup
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*
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* Description:
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* Setup the Serial Gigabit Media-Independent Interface (SGMII)
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*
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****************************************************************************/
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static void mpfs_sgmii_setup(void)
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{
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putreg32(((0x01 << 8) | 0x1), MPFS_CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY);
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putreg32(0x1, MPFS_CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY);
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putreg32(LIBERO_SETTING_SGMII_MODE & ~(1 << 22),
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MPFS_CFG_DDR_SGMII_PHY_SGMII_MODE);
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putreg32(LIBERO_SETTING_CH0_CNTL, MPFS_CFG_DDR_SGMII_PHY_CH0_CNTL);
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putreg32(LIBERO_SETTING_CH1_CNTL, MPFS_CFG_DDR_SGMII_PHY_CH1_CNTL);
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putreg32(LIBERO_SETTING_RECAL_CNTL, MPFS_CFG_DDR_SGMII_PHY_RECAL_CNTL);
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putreg32(LIBERO_SETTING_CLK_CNTL, MPFS_CFG_DDR_SGMII_PHY_CLK_CNTL);
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putreg32(LIBERO_SETTING_SPARE_CNTL, MPFS_CFG_DDR_SGMII_PHY_SPARE_CNTL);
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putreg32(LIBERO_SETTING_PLL_CNTL, MPFS_CFG_DDR_SGMII_PHY_PLL_CNTL);
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/* Enable the Bank controller:
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* - Set soft reset on IP to load RPC to SCB regs (dynamic mode)
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* - Bring the sgmii bank controller out of reset =- ioscb_bank_ctrl_sgmii
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*/
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putreg32(0x01, MPFS_IOSCB_BANK_CNTL_SGMII_SOFT_RESET);
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/* Check the IO_EN signal here. This is an output from the bank controller
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* power detector, which are turned on using MSS_IO_EN.
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*/
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||||
|
||||
while (!(getreg32(MPFS_CFG_DDR_SGMII_PHY_PVT_STAT) & (1 << 6)));
|
||||
|
||||
/* IO power ramp wait time: after IOEN is received from power detectors
|
||||
* DDR and SGMII, extra time is required for voltage to ramp.
|
||||
*/
|
||||
|
||||
mpfs_wait_cycles(10);
|
||||
|
||||
putreg32(0, MPFS_SYSREGSCB_MSS_RESET_CR);
|
||||
|
||||
/* Reset SGMII DLL */
|
||||
|
||||
putreg32(1 << 0, MPFS_IOSCB_DLL_SGMII_SOFT_RESET);
|
||||
|
||||
/* SGMII Lane 01 and 23 soft-reset */
|
||||
|
||||
putreg32(1, MPFS_IOSCB_SGMII_LANE01_SOFT_RESET);
|
||||
putreg32(1, MPFS_IOSCB_SGMII_LANE23_SOFT_RESET);
|
||||
|
||||
putreg32(SGMII_REG_PVT_SOFT_RESET_PERIPH | 0x7f,
|
||||
MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
putreg32(0x7f, MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
|
||||
putreg32(1, MPFS_IOSCB_CALIB_SGMII_SOFT_RESET);
|
||||
putreg32(0, MPFS_IOSCB_CALIB_SGMII_SOFT_RESET);
|
||||
|
||||
/* Verify calibration */
|
||||
|
||||
while (!(getreg32(MPFS_CFG_DDR_SGMII_PHY_PVT_STAT) & (1 << 14)));
|
||||
|
||||
modifyreg32(MPFS_CFG_DDR_SGMII_PHY_PVT_STAT, 0, 0x40000000);
|
||||
modifyreg32(MPFS_IOSCB_CALIB_SGMII_IOC_REG0, 0,
|
||||
SGMII_IOC_REG0_REG_CALIB_LOCK);
|
||||
|
||||
mpfs_sgmii_mux_config();
|
||||
mpfs_sgmii_pll_config_scb();
|
||||
|
||||
/* SGMII wait for MSS lock */
|
||||
|
||||
while (!((getreg32(MPFS_CFG_DDR_SGMII_PHY_PLL_CNTL) &
|
||||
SGMII_ARO_PLL0_LOCK)));
|
||||
|
||||
/* SGMII wait for DLL lock */
|
||||
|
||||
while (!((getreg32(MPFS_CFG_DDR_SGMII_PHY_RECAL_CNTL) & (1 << 23))));
|
||||
|
||||
modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
|
||||
SYSREG_SUBBLK_CLOCK_CR_MAC0 | SYSREG_SUBBLK_CLOCK_CR_MAC1);
|
||||
|
||||
modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, SYSREG_SOFT_RESET_CR_MAC0 |
|
||||
SYSREG_SOFT_RESET_CR_MAC1, 0);
|
||||
|
||||
/* SGMII gigabit mode enable */
|
||||
|
||||
putreg32((1 << 10) | (1 << 11), MPFS_GEM0_NETWORK_CONFIG);
|
||||
putreg32((1 << 10) | (1 << 11), MPFS_GEM1_NETWORK_CONFIG);
|
||||
|
||||
/* Determine silicon variant from generated sro_dll_90_code */
|
||||
|
||||
uint32_t sro_dll_90_code = ((getreg32(MPFS_CFG_DDR_SGMII_PHY_RECAL_CNTL) \
|
||||
>> 16) & 0x7f);
|
||||
uint32_t silicon_variant;
|
||||
|
||||
/* Post rev B silicon */
|
||||
|
||||
if (getreg32(MPFS_CFG_DDR_SGMII_PHY_SPARE_STAT) & (1 << 31))
|
||||
{
|
||||
silicon_variant = PART_REVC_OR_LATER;
|
||||
mpfs_set_early_late_thresholds(
|
||||
LATE_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST,
|
||||
EARLY_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (sro_dll_90_code < MIN_DLL_90_CODE_VALUE_INDICATING_TT_PART_REVB)
|
||||
{
|
||||
silicon_variant = SS_PART_REVB;
|
||||
mpfs_set_early_late_thresholds(LATE_EYE_WIDTH_SS_PART_REVB,
|
||||
EARLY_EYE_WIDTH_SS_PART_REVB);
|
||||
}
|
||||
else
|
||||
{
|
||||
silicon_variant = TT_PART_REVB;
|
||||
mpfs_set_early_late_thresholds(LATE_TT_PART_REVB,
|
||||
EARLY_TT_PART_REVB);
|
||||
}
|
||||
}
|
||||
|
||||
/* DLL soft reset - Already configured
|
||||
* PVT soft reset - Already configured
|
||||
* Bank controller soft reset - Already configured
|
||||
* CLKMUX soft reset - Already configured
|
||||
* Lane0 soft reset - must be soft reset here
|
||||
* Lane1 soft reset - must be soft reset here
|
||||
*/
|
||||
|
||||
putreg32(SGMII_REG_LANE1_SOFT_RESET_PERIPH |
|
||||
SGMII_REG_LANE0_SOFT_RESET_PERIPH | 0x7f,
|
||||
MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
putreg32(0x7f, MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
|
||||
if (silicon_variant == PART_REVC_OR_LATER)
|
||||
{
|
||||
mpfs_wait_cycles(0xfff);
|
||||
|
||||
if ((getreg32(MPFS_CFG_DDR_SGMII_PHY_SPARE_STAT) & ARO_REF_PCODE_MASK)
|
||||
<= ARO_REF_PCODE_REVC_THRESHOLD)
|
||||
{
|
||||
/* Need to adjust eye values */
|
||||
|
||||
mpfs_set_early_late_thresholds(LATE_EYE_WIDTH_PART_REVC_OR_LATER,
|
||||
EARLY_EYE_WIDTH_PART_REVC_OR_LATER);
|
||||
|
||||
/* Now reset the channels */
|
||||
|
||||
putreg32(SGMII_REG_LANE1_SOFT_RESET_PERIPH |
|
||||
SGMII_REG_LANE0_SOFT_RESET_PERIPH | 0x7f,
|
||||
MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
putreg32(0x7f, MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
}
|
||||
}
|
||||
|
||||
mpfs_pll_config();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_clock_init
|
||||
*
|
||||
* Description:
|
||||
* Setup the system clocks
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void mpfs_clockconfig(void)
|
||||
{
|
||||
mpfs_set_rtc_divisor();
|
||||
|
||||
putreg32(MPFS_SCB_ACCESS_CONFIG, MPFS_IOSCBCFG_TIMER);
|
||||
|
||||
putreg32(0x01, MPFS_SYSREG_DFIAPB_CR);
|
||||
|
||||
putreg32((0x3f << 16) | (0x1f << 8), MPFS_CFG_DDR_SGMII_PHY_STARTUP);
|
||||
putreg32(SGMII_REG_PVT_SOFT_RESET_PERIPH | 0x7f,
|
||||
MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL);
|
||||
|
||||
/* DCE:111, CORE_UP:1, FLASH_VALID:0, mss_io_en:0 */
|
||||
|
||||
putreg32(MSSIO_CONTROL_CR_MSS_DCE | MSSIO_CONTROL_CR_MSS_CORE_UP,
|
||||
MPFS_SYSREGSCB_MSSIO_CONTROL_CR);
|
||||
|
||||
mpfs_wait_cycles(10);
|
||||
|
||||
/* DCE:000, CORE_UP:1, FLASH_VALID:0, mss_io_en:0 */
|
||||
|
||||
putreg32(MSSIO_CONTROL_CR_MSS_CORE_UP, MPFS_SYSREGSCB_MSSIO_CONTROL_CR);
|
||||
|
||||
mpfs_wait_cycles(10);
|
||||
|
||||
/* DCE:000, CORE_UP:1, FLASH_VALID:1, mss_io_en:0 */
|
||||
|
||||
putreg32(MSSIO_CONTROL_CR_MSS_CORE_UP | MSSIO_CONTROL_CR_MSS_FLASH_VALID,
|
||||
MPFS_SYSREGSCB_MSSIO_CONTROL_CR);
|
||||
|
||||
mpfs_wait_cycles(10);
|
||||
|
||||
/* DCE:000, CORE_UP:1, FLASH_VALID:1, mss_io_en:1 */
|
||||
|
||||
putreg32(MSSIO_CONTROL_CR_MSS_CORE_UP | MSSIO_CONTROL_CR_MSS_FLASH_VALID |
|
||||
MSSIO_CONTROL_CR_MSS_IO_EN, MPFS_SYSREGSCB_MSSIO_CONTROL_CR);
|
||||
|
||||
/* Setup SGMII */
|
||||
|
||||
mpfs_sgmii_setup();
|
||||
|
||||
/* Setup the MSS PLL */
|
||||
|
||||
mpfs_pll_config();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_get_cpuclk
|
||||
****************************************************************************/
|
||||
|
|
@ -69,12 +651,3 @@ uint64_t mpfs_get_pll0clk(void)
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mpfs_clockconfig
|
||||
****************************************************************************/
|
||||
|
||||
void mpfs_clockconfig(void)
|
||||
{
|
||||
/* All is currently done in bootloader HSS */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -97,9 +97,11 @@ void __mpfs_start(uint32_t mhartid)
|
|||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Setup PLL */
|
||||
/* Setup PLL if not already provided */
|
||||
|
||||
#ifdef CONFIG_MPFS_BOOTLOADER
|
||||
mpfs_clockconfig();
|
||||
#endif
|
||||
|
||||
/* Configure the UART so we can get debug output */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue