arch/intel64: add cpu specific data and per-cpu interrupt stacks
Use GS base regsiter to store reference to CPU private data. Then we can easily refer to private CPU data using the GS segment. Required for SMP support. Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
Alan Carvalho de Assis
parent
87dfcd1020
commit
c6170286ca
17 changed files with 645 additions and 95 deletions
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@ -134,6 +134,7 @@ config ARCH_X86_64
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_INTERRUPTSTACK
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select ARCH_HAVE_CUSTOMOPT
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select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
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---help---
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@ -79,6 +79,8 @@
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#define X86_GDT_DATA_SEL_NUM 2
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# define X86_GDT_DATA_SEL (X86_GDT_DATA_SEL_NUM * X86_GDT_ENTRY_SIZE)
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/* The first TSS entry */
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#define X86_GDT_ISTL_SEL_NUM 6
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#define X86_GDT_ISTH_SEL_NUM (X86_GDT_ISTL_SEL_NUM + 1)
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@ -263,7 +265,12 @@
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#define X86_PIC_8086 1
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#define X86_PIC_EOI 0x20
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#define BITS_PER_LONG 64
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#define BITS_PER_LONG 64
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/* Interrupt Stack Table size */
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#define X86_IST_SIZE 104
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#define X86_TSS_SIZE (104 + 8)
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/* Reset Control Register (RST_CNT) */
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@ -370,9 +377,13 @@ begin_packed_struct struct ist_s
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uint16_t IOPB_OFFSET; /* IOPB_offset */
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} end_packed_struct;
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* TSS */
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begin_packed_struct struct tss_s
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{
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struct ist_s ist; /* IST */
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void *cpu; /* CPU private data */
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} end_packed_struct;
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/****************************************************************************
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* Public Data
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@ -58,18 +58,27 @@
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This holds a references to the current interrupt level register storage
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* structure. It is non-NULL only during interrupt processing.
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/* CPU private data */
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struct intel64_cpu_s
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{
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int id;
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uint8_t loapic_id;
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bool ready;
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/* current_regs holds a references to the current interrupt level
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* register storage structure. If is non-NULL only during interrupt
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* processing. Access to current_regs must be through
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* up_current_regs() and up_set_current_regs() functions
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*/
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extern volatile uint64_t *g_current_regs;
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#endif
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uint64_t *current_regs;
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};
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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@ -100,6 +109,22 @@ extern "C"
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* Inline functions
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****************************************************************************/
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static inline_function uint64_t *up_current_regs(void)
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{
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uint64_t *regs;
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asm volatile("movq %%gs:(%c1), %0"
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: "=rm" (regs)
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: "i" (offsetof(struct intel64_cpu_s, current_regs)));
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return regs;
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}
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static inline_function void up_set_current_regs(uint64_t *regs)
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{
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asm volatile("movq %0, %%gs:(%c1)"
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:: "r" (regs), "i" (offsetof(struct intel64_cpu_s,
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current_regs)));
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}
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/****************************************************************************
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* Name: up_interrupt_context
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*
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@ -109,7 +134,11 @@ extern "C"
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*
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****************************************************************************/
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#define up_interrupt_context() (g_current_regs != NULL)
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noinstrument_function
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static inline_function bool up_interrupt_context(void)
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{
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return up_current_regs() != NULL;
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}
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#undef EXTERN
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#ifdef __cplusplus
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@ -39,6 +39,6 @@
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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uintptr_t up_get_intstackbase(int cpu)
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{
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return (uintptr_t)g_intstackalloc;
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return (uintptr_t)(g_intstackalloc + (cpu * IRQ_STACK_SIZE));
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}
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#endif
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@ -111,7 +111,15 @@
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* referenced is passed to get the state from the TCB.
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*/
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#define x86_64_restorestate(regs) (g_current_regs = regs)
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#define x86_64_restorestate(regs) (up_set_current_regs(regs))
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/* ISR/IRQ stack size */
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#if CONFIG_ARCH_INTERRUPTSTACK == 0
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# define IRQ_STACK_SIZE 0x2000
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#else
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# define IRQ_STACK_SIZE CONFIG_ARCH_INTERRUPTSTACK
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#endif
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/****************************************************************************
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* Public Types
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@ -138,7 +146,7 @@ extern const uintptr_t g_idle_topstack;
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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extern uint8_t g_intstackalloc[];
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extern uint8_t g_intstacktop[];
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extern uint8_t g_intstackalloc[];
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#endif
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/* These symbols are setup by the linker script. */
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@ -63,7 +63,7 @@ void up_switch_context(struct tcb_s *tcb, struct tcb_s *rtcb)
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/* Are we in an interrupt handler? */
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if (g_current_regs)
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if (up_current_regs())
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{
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/* Yes, then we have to do things differently.
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* Just copy the g_current_regs into the OLD rtcb.
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@ -45,7 +45,8 @@ set(SRCS
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intel64_lowsetup.c
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intel64_serial.c
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intel64_rng.c
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intel64_check_capability.c)
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intel64_check_capability.c
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intel64_cpu.c)
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if(CONFIG_ARCH_HAVE_TESTSET)
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list(APPEND SRCS intel64_testset.S)
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@ -32,6 +32,7 @@ CMN_CSRCS += intel64_systemreset.c intel64_freq.c intel64_cache.c
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CHIP_ASRCS = intel64_saveusercontext.S intel64_fullcontextrestore.S intel64_vectors.S intel64_head.S
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CHIP_CSRCS = intel64_start.c intel64_handlers.c intel64_idle.c intel64_lowsetup.c
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CHIP_CSRCS += intel64_serial.c intel64_rng.c intel64_check_capability.c
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CHIP_CSRCS += intel64_cpu.c
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ifeq ($(CONFIG_ARCH_HAVE_TESTSET), y)
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CHIP_ASRCS += intel64_testset.S
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383
arch/x86_64/src/intel64/intel64_cpu.c
Normal file
383
arch/x86_64/src/intel64/intel64_cpu.c
Normal file
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@ -0,0 +1,383 @@
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/****************************************************************************
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* arch/x86_64/src/intel64/intel64_cpu.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/spinlock.h>
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#include <arch/irq.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <stddef.h>
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#include <assert.h>
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#include <intel64_cpu.h>
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#include "x86_64_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Avoid undefined error when CONFIG_SPINLOCK=n */
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#ifndef spin_lock
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# define spin_lock(s)
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#endif
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#define IRQ_STACK_ALLOC (IRQ_STACK_SIZE * CONFIG_SMP_NCPUS)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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extern volatile uint32_t g_cpu_count;
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volatile static spinlock_t g_ap_boot;
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/* CPU private data */
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struct intel64_cpu_s g_cpu_priv[CONFIG_SMP_NCPUS];
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/* Allocate stack for interrupts and isr */
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uint8_t g_intstackalloc[IRQ_STACK_ALLOC] aligned_data(16);
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uint8_t g_isrstackalloc[IRQ_STACK_ALLOC] aligned_data(16);
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: x86_64_cpu_tss_get
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*
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* Description:
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* Get TSS for a given CPU data.
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*
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****************************************************************************/
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static struct tss_s *x86_64_cpu_tss_get(uint8_t cpu)
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{
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return (struct tss_s *)((uintptr_t)&g_ist64_low + X86_64_LOAD_OFFSET +
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(X86_TSS_SIZE * cpu));
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}
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/****************************************************************************
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* Name: x86_64_cpu_tss_load
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*
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* Description:
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* Load TSS for the current CPU
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*
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****************************************************************************/
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static void x86_64_cpu_tss_load(int cpu)
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{
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uint16_t addr;
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/* Get offset for TSS */
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addr = X86_GDT_ISTL_SEL_NUM * 8 + 16 * cpu;
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asm volatile ("mov %0, %%ax; ltr %%ax":: "m"(addr) : "memory", "rax");
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: x86_64_cpu_tss_init
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*
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* Description:
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* Initialize the TSS
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*
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****************************************************************************/
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void x86_64_cpu_tss_init(int cpu)
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{
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struct tss_s *tss = NULL;
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struct ist_s *ist64 = NULL;
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struct gdt_entry_s tss_l;
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uint64_t tss_h;
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/* Get TSS - one per CPU */
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tss = x86_64_cpu_tss_get(cpu);
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/* Setup IST pointer */
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ist64 = &tss->ist;
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/* Reset local data */
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memset(&tss_l, 0, sizeof(tss_l));
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memset(&tss_h, 0, sizeof(tss_h));
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/* Segment limit = IST size - 1 */
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tss_l.limit_low = ((X86_IST_SIZE - 1) & 0xffff);
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/* Low address 1 */
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tss_l.base_low = ((uintptr_t)ist64 & 0x00ffffff);
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/* Low address 2 */
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tss_l.base_high = (((uintptr_t)ist64 & 0xff000000) >> 24);
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tss_l.P = 1;
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/* Set type as IST */
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tss_l.AC = 1;
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tss_l.EX = 1;
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/* High address */
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tss_h = (((uintptr_t)ist64 >> 32) & 0xffffffff);
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g_gdt64[X86_GDT_ISTL_SEL_NUM + 2 * cpu] = tss_l;
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/* memcpy used to handle type punning compiler warning */
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memcpy((void *)&g_gdt64[X86_GDT_ISTH_SEL_NUM + 2 * cpu],
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&tss_h, sizeof(g_gdt64[0]));
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/* Stack for IRQ0-IRQ15 */
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ist64->IST1 = (uintptr_t)(g_isrstackalloc + ((cpu + 1) * IRQ_STACK_SIZE));
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/* Stack for the rest IRQ */
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ist64->IST2 = (uintptr_t)(g_intstackalloc + ((cpu + 1) * IRQ_STACK_SIZE));
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/* Now load TSS */
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x86_64_cpu_tss_load(cpu);
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}
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/****************************************************************************
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* Name: x86_64_cpu_tss_now_get
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*
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* Description:
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* Get CPU TSS data associated with the current CPU
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*
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****************************************************************************/
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struct tss_s *x86_64_cpu_tss_now_get(void)
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{
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uint64_t *ist = 0;
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uint16_t seg = 0;
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uint16_t ist_offset = 0;
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uintptr_t tss_addr = 0;
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/* Get TSS associated with this CPU */
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asm volatile ("str %%ax; mov %%ax, %0": "=rm"(seg) :: "memory", "rax");
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/* This is BSP if TSS not configured yet */
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if (seg == 0)
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{
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return NULL;
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}
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/* Decode TSS */
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ist_offset = ((seg - X86_GDT_ISTL_SEL_NUM * 8) / 8);
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ist = (uint64_t *)((uintptr_t)&g_gdt64_ist_low + X86_64_LOAD_OFFSET);
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/* Low address */
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tss_addr = (ist[ist_offset] >> 16) & 0x00ffffff;
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tss_addr |= ((ist[ist_offset] >> 56) & 0xff) << 24;
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/* High address */
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tss_addr |= ist[ist_offset + 1] << 32;
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return (struct tss_s *)tss_addr;
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}
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/****************************************************************************
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* Name: x86_64_cpu_init
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*
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* Description:
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* Initialize CPU data.
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*
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****************************************************************************/
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void x86_64_cpu_init(void)
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{
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struct tss_s *tss = NULL;
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struct acpi_lapic_s *lapic = NULL;
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int i = 0;
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int ret = OK;
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/* Map logical CPU to Local APIC IDs */
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for (i = 0; i < CONFIG_SMP_NCPUS; i++)
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{
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ret = acpi_lapic_get(i, &lapic);
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if (ret == OK)
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{
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g_cpu_priv[i].loapic_id = lapic->apic_id;
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g_cpu_priv[i].id = i;
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g_cpu_priv[i].ready = false;
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/* Store private CPU in TSS */
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tss = x86_64_cpu_tss_get(i);
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tss->cpu = &g_cpu_priv[i];
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}
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else
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{
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/* We want to fail early when NCPUS doesn't match the number
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* of availalbe CPUs
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*/
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/* Panic if not found */
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PANIC();
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}
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}
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/* Set BSP ready flag */
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g_cpu_priv[0].ready = true;
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}
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/****************************************************************************
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* Name: x86_64_lopaic_to_cpu
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*
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* Description:
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* Get CPU index for a given Local APIC ID
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*
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****************************************************************************/
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uint8_t x86_64_loapic_to_cpu(uint8_t loapic)
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{
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int i;
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for (i = 0; i < CONFIG_SMP_NCPUS; i++)
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{
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if (g_cpu_priv[i].loapic_id == loapic)
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{
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return i;
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}
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}
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/* Panic if not found */
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PANIC();
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}
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/****************************************************************************
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* Name: x86_64_cpu_to_loapic
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*
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* Description:
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* Get Local APIC ID for a given CPU index
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*
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****************************************************************************/
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uint8_t x86_64_cpu_to_loapic(uint8_t cpu)
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{
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return g_cpu_priv[cpu].loapic_id;
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}
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/****************************************************************************
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* Name: x86_64_cpu_ready_set
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*
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* Description:
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* Set CPU ready flag
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*
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****************************************************************************/
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void x86_64_cpu_ready_set(uint8_t cpu)
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{
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spin_lock(&g_ap_boot);
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if (!g_cpu_priv[cpu].ready)
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{
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||||
g_cpu_priv[cpu].ready = true;
|
||||
g_cpu_count++;
|
||||
}
|
||||
|
||||
spin_unlock(&g_ap_boot);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_ready_get
|
||||
*
|
||||
* Description:
|
||||
* Get CPU ready flag
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool x86_64_cpu_ready_get(uint8_t cpu)
|
||||
{
|
||||
struct intel64_cpu_s *priv = &g_cpu_priv[cpu];
|
||||
bool ready;
|
||||
|
||||
spin_lock(&g_ap_boot);
|
||||
ready = priv->ready;
|
||||
spin_unlock(&g_ap_boot);
|
||||
|
||||
return ready;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_count_get
|
||||
*
|
||||
* Description:
|
||||
* Get CPU counter
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t x86_64_cpu_count_get(void)
|
||||
{
|
||||
uint8_t count;
|
||||
|
||||
spin_lock(&g_ap_boot);
|
||||
count = g_cpu_count;
|
||||
spin_unlock(&g_ap_boot);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_priv_set
|
||||
*
|
||||
* Description:
|
||||
* Save CPU private data
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void x86_64_cpu_priv_set(uint8_t cpu)
|
||||
{
|
||||
/* Store private data pointer to GSBASE */
|
||||
|
||||
write_gsbase((uintptr_t)&g_cpu_priv[cpu]);
|
||||
}
|
||||
154
arch/x86_64/src/intel64/intel64_cpu.h
Normal file
154
arch/x86_64/src/intel64/intel64_cpu.h
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
/****************************************************************************
|
||||
* arch/x86_64/src/intel64/intel64_cpu.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_X86_64_SRC_INTEL64_INTEL64_CPU_H
|
||||
#define __ARCH_X86_64_SRC_INTEL64_INTEL64_CPU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch/arch.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_tss_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize the TSS
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void x86_64_cpu_tss_init(int cpu);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_tss_now_get
|
||||
*
|
||||
* Description:
|
||||
* Get CPU TSS data associated with the current CPU
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct tss_s *x86_64_cpu_tss_now_get(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize CPU data.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void x86_64_cpu_init(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_lopaic_to_cpu
|
||||
*
|
||||
* Description:
|
||||
* Get CPU index for a given Local APIC ID
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t x86_64_loapic_to_cpu(uint8_t loapic);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_to_loapic
|
||||
*
|
||||
* Description:
|
||||
* Get Local APIC ID for a given CPU index
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t x86_64_cpu_to_loapic(uint8_t cpu);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_ready_set
|
||||
*
|
||||
* Description:
|
||||
* Set CPU ready flag
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void x86_64_cpu_ready_set(uint8_t cpu);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_ready_get
|
||||
*
|
||||
* Description:
|
||||
* Get CPU ready flag
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool x86_64_cpu_ready_get(uint8_t cpu);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_count_get
|
||||
*
|
||||
* Description:
|
||||
* Get CPU counter
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t x86_64_cpu_count_get(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: x86_64_cpu_priv_set
|
||||
*
|
||||
* Description:
|
||||
* Save CPU private data
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void x86_64_cpu_priv_set(uint8_t cpu);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_X86_64_SRC_INTEL64_INTEL64_CPU_H */
|
||||
|
|
@ -68,8 +68,8 @@ static uint64_t *common_handler(int irq, uint64_t *regs)
|
|||
* Nested interrupts are not supported.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(g_current_regs == NULL);
|
||||
g_current_regs = regs;
|
||||
DEBUGASSERT(up_current_regs() == NULL);
|
||||
up_set_current_regs(regs);
|
||||
|
||||
/* Deliver the IRQ */
|
||||
|
||||
|
|
@ -82,7 +82,7 @@ static uint64_t *common_handler(int irq, uint64_t *regs)
|
|||
* returning from the interrupt.
|
||||
*/
|
||||
|
||||
if (regs != g_current_regs)
|
||||
if (regs != up_current_regs())
|
||||
{
|
||||
#ifdef CONFIG_ARCH_ADDRENV
|
||||
/* Make sure that the address environment for the previously
|
||||
|
|
@ -108,13 +108,13 @@ static uint64_t *common_handler(int irq, uint64_t *regs)
|
|||
* switch occurred during interrupt processing.
|
||||
*/
|
||||
|
||||
regs = (uint64_t *)g_current_regs;
|
||||
regs = (uint64_t *)up_current_regs();
|
||||
|
||||
/* Set g_current_regs to NULL to indicate that we are no longer in an
|
||||
* interrupt handler.
|
||||
*/
|
||||
|
||||
g_current_regs = NULL;
|
||||
up_set_current_regs(NULL);
|
||||
return regs;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -145,8 +145,8 @@ uint64_t *isr_handler(uint64_t *regs, uint64_t irq)
|
|||
return regs;
|
||||
#else
|
||||
|
||||
DEBUGASSERT(g_current_regs == NULL);
|
||||
g_current_regs = regs;
|
||||
DEBUGASSERT(up_current_regs() == NULL);
|
||||
up_set_current_regs(regs);
|
||||
|
||||
switch (irq)
|
||||
{
|
||||
|
|
@ -174,13 +174,13 @@ uint64_t *isr_handler(uint64_t *regs, uint64_t irq)
|
|||
|
||||
/* Maybe we need a context switch */
|
||||
|
||||
regs = (uint64_t *)g_current_regs;
|
||||
regs = (uint64_t *)up_current_regs();
|
||||
|
||||
/* Set g_current_regs to NULL to indicate that we are no longer in an
|
||||
* interrupt handler.
|
||||
*/
|
||||
|
||||
g_current_regs = NULL;
|
||||
up_set_current_regs(NULL);
|
||||
return regs;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
.global g_idle_topstack /* The end of the idle stack, the start of the heap */
|
||||
.global g_mb_info_struct
|
||||
.global g_mb_magic
|
||||
.global g_cpu_count
|
||||
|
||||
/* These are the page tables */
|
||||
.global g_pdpt_low
|
||||
|
|
@ -283,6 +284,9 @@ start64:
|
|||
jmp *%rbx
|
||||
.size __pmode_entry, . - __pmode_entry
|
||||
|
||||
g_cpu_count:
|
||||
.long 1
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __revoke_low_memory
|
||||
*
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <sched.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
|
@ -39,16 +40,13 @@
|
|||
#include <nuttx/spinlock.h>
|
||||
|
||||
#include "x86_64_internal.h"
|
||||
#include "intel64_cpu.h"
|
||||
#include "intel64.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define UART_BASE 0x3f8
|
||||
|
||||
#define IRQ_STACK_SIZE 0x2000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
|
@ -71,14 +69,6 @@ static inline void up_idtinit(void);
|
|||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
volatile uint64_t *g_current_regs;
|
||||
|
||||
uint8_t g_interrupt_stack[IRQ_STACK_SIZE] aligned_data(16);
|
||||
uint8_t *g_interrupt_stack_end = g_interrupt_stack + IRQ_STACK_SIZE - 16;
|
||||
|
||||
uint8_t g_isr_stack[IRQ_STACK_SIZE] aligned_data(16);
|
||||
uint8_t *g_isr_stack_end = g_isr_stack + IRQ_STACK_SIZE - 16;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
|
@ -171,49 +161,6 @@ void up_ioapic_unmask_pin(unsigned int pin)
|
|||
cur & ~(IOAPIC_PIN_DISABLE));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_init_ist
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Interrupt Stack Table
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void up_ist_init(void)
|
||||
{
|
||||
struct gdt_entry_s tss_l;
|
||||
uint64_t tss_h;
|
||||
|
||||
memset(&tss_l, 0, sizeof(tss_l));
|
||||
memset(&tss_h, 0, sizeof(tss_h));
|
||||
|
||||
tss_l.limit_low = (((104 - 1) & 0xffff)); /* Segment limit = TSS size - 1 */
|
||||
|
||||
tss_l.base_low = ((uintptr_t)g_ist64 & 0x00ffffff); /* Low address 1 */
|
||||
tss_l.base_high = (((uintptr_t)g_ist64 & 0xff000000) >> 24); /* Low address 2 */
|
||||
|
||||
tss_l.P = 1;
|
||||
|
||||
/* Set type as IST */
|
||||
|
||||
tss_l.AC = 1;
|
||||
tss_l.EX = 1;
|
||||
|
||||
tss_h = (((uintptr_t)g_ist64 >> 32) & 0xffffffff); /* High address */
|
||||
|
||||
g_gdt64[X86_GDT_ISTL_SEL_NUM] = tss_l;
|
||||
|
||||
/* memcpy used to handle type punning compiler warning */
|
||||
|
||||
memcpy((void *)&g_gdt64[X86_GDT_ISTH_SEL_NUM],
|
||||
(void *)&tss_h, sizeof(g_gdt64[0]));
|
||||
|
||||
g_ist64->IST1 = (uintptr_t)g_interrupt_stack_end;
|
||||
g_ist64->IST2 = (uintptr_t)g_isr_stack_end;
|
||||
|
||||
asm volatile ("mov $0x30, %%ax; ltr %%ax":::"memory", "rax");
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_deinit_8259
|
||||
*
|
||||
|
|
@ -486,21 +433,19 @@ static inline void up_idtinit(void)
|
|||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
/* Initialize the IST */
|
||||
/* Initialize the TSS */
|
||||
|
||||
up_ist_init();
|
||||
|
||||
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
|
||||
/* Disable 8259 PIC */
|
||||
|
||||
up_deinit_8259();
|
||||
#endif
|
||||
x86_64_cpu_tss_init(0);
|
||||
|
||||
/* Initialize the APIC */
|
||||
|
||||
up_apic_init();
|
||||
|
||||
#ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT
|
||||
/* Disable 8259 PIC */
|
||||
|
||||
up_deinit_8259();
|
||||
|
||||
/* Initialize the IOAPIC */
|
||||
|
||||
up_ioapic_init();
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ void backtrace(uint64_t rbp)
|
|||
|
||||
void up_dump_register(void *dumpregs)
|
||||
{
|
||||
volatile uint64_t *regs = dumpregs ? dumpregs : g_current_regs;
|
||||
volatile uint64_t *regs = dumpregs ? dumpregs : up_current_regs();
|
||||
uint64_t mxcsr;
|
||||
uint64_t cr2;
|
||||
|
||||
|
|
|
|||
|
|
@ -46,5 +46,5 @@
|
|||
|
||||
void x86_64_savestate(uint64_t *regs)
|
||||
{
|
||||
x86_64_copystate(regs, (uint64_t *)g_current_regs);
|
||||
x86_64_copystate(regs, (uint64_t *)up_current_regs());
|
||||
}
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@
|
|||
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
{
|
||||
sinfo("tcb=%p sigdeliver=%p\n", tcb, sigdeliver);
|
||||
sinfo("rtcb=%p g_current_regs=%p\n", this_task(), g_current_regs);
|
||||
sinfo("rtcb=%p g_current_regs=%p\n", this_task(), up_current_regs());
|
||||
|
||||
/* Refuse to handle nested signal actions */
|
||||
|
||||
|
|
@ -91,7 +91,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* signalling itself for some reason.
|
||||
*/
|
||||
|
||||
if (!g_current_regs)
|
||||
if (!up_current_regs())
|
||||
{
|
||||
/* In this case just deliver the signal with a function call
|
||||
* now.
|
||||
|
|
@ -120,16 +120,16 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* have been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.saved_rip = g_current_regs[REG_RIP];
|
||||
tcb->xcp.saved_rip = up_current_regs()[REG_RIP];
|
||||
tcb->xcp.saved_rsp = tcb->xcp.regs[REG_RSP];
|
||||
tcb->xcp.saved_rflags = g_current_regs[REG_RFLAGS];
|
||||
tcb->xcp.saved_rflags = up_current_regs()[REG_RFLAGS];
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
g_current_regs[REG_RIP] = (uint64_t)x86_64_sigdeliver;
|
||||
g_current_regs[REG_RFLAGS] = 0;
|
||||
up_current_regs()[REG_RIP] = (uint64_t)x86_64_sigdeliver;
|
||||
up_current_regs()[REG_RFLAGS] = 0;
|
||||
|
||||
/* And make sure that the saved context in the TCB
|
||||
* is the same as the interrupt return context.
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
#include "x86_64_internal.h"
|
||||
|
||||
#include "intel64_cpu.h"
|
||||
#include "intel64_lowsetup.h"
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -129,6 +130,8 @@ void __nxstart(void)
|
|||
{
|
||||
uint64_t *dest = NULL;
|
||||
|
||||
/* This is only for BSP core. */
|
||||
|
||||
/* Do some checking on CPU compatibilities at the top of this function.
|
||||
* BSS cleanup can be optimized with vector instructions, so we need to
|
||||
* enable SSE at this point.
|
||||
|
|
@ -161,6 +164,10 @@ void __nxstart(void)
|
|||
acpi_init(g_acpi_rsdp);
|
||||
#endif
|
||||
|
||||
/* Initialize CPU data (BSP and APs) */
|
||||
|
||||
x86_64_cpu_init();
|
||||
|
||||
/* perform board-specific initializations */
|
||||
|
||||
x86_64_boardinitialize();
|
||||
|
|
@ -171,12 +178,18 @@ void __nxstart(void)
|
|||
x86_64_earlyserialinit();
|
||||
#endif
|
||||
|
||||
/* Configure timer */
|
||||
|
||||
x86_64_timer_calibrate_freq();
|
||||
|
||||
#ifdef CONFIG_LIB_SYSCALL
|
||||
enable_syscall();
|
||||
#endif
|
||||
|
||||
/* Store CPU IDs */
|
||||
|
||||
x86_64_cpu_priv_set(0);
|
||||
|
||||
/* Start NuttX */
|
||||
|
||||
nx_start();
|
||||
|
|
|
|||
Loading…
Reference in a new issue