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stm32h7:ADC STM32_RCC_D3CCIPR_ADCSEL->STM32_RCC_D3CCIPR_ADCSRC

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This commit is contained in:
David Sidrane 2023-12-05 09:17:16 -08:00 committed by Xiang Xiao
parent 6ad7b82cd6
commit d31214aa25
8 changed files with 10 additions and 10 deletions
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4
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
View file

@ -1009,10 +1009,10 @@ void stm32_stdclockconfig(void)
/* Configure ADC source clock */
#if defined(STM32_RCC_D3CCIPR_ADCSEL)
#if defined(STM32_RCC_D3CCIPR_ADCSRC)
regval = getreg32(STM32_RCC_D3CCIPR);
regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
regval |= STM32_RCC_D3CCIPR_ADCSEL;
regval |= STM32_RCC_D3CCIPR_ADCSRC;
putreg32(regval, STM32_RCC_D3CCIPR);
#endif

4
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
View file

@ -983,10 +983,10 @@ void stm32_stdclockconfig(void)
/* Configure ADC source clock */
#if defined(STM32_RCC_D3CCIPR_ADCSEL)
#if defined(STM32_RCC_D3CCIPR_ADCSRC)
regval = getreg32(STM32_RCC_D3CCIPR);
regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
regval |= STM32_RCC_D3CCIPR_ADCSEL;
regval |= STM32_RCC_D3CCIPR_ADCSRC;
putreg32(regval, STM32_RCC_D3CCIPR);
#endif

2
boards/arm/stm32h7/linum-stm32h753bi/include/board.h
View file

@ -232,7 +232,7 @@
/* ADC 1 2 3 clock source - pll2_pclk */
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* FLASH wait states
*

2
boards/arm/stm32h7/nucleo-h743zi/include/board.h
View file

@ -240,7 +240,7 @@
/* ADC 1 2 3 clock source - pll2_pclk */
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* FLASH wait states
*

2
boards/arm/stm32h7/nucleo-h743zi2/include/board.h
View file

@ -240,7 +240,7 @@
/* ADC 1 2 3 clock source - pll2_pclk */
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* FDCAN 1 2 clock source - HSE (TODO: Not the best choice for this board?) */

2
boards/arm/stm32h7/nucleo-h745zi/include/board.h
View file

@ -240,7 +240,7 @@
/* ADC 1 2 3 clock source - pll2_pclk */
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* FLASH wait states
*

2
boards/arm/stm32h7/stm32h745i-disco/include/board.h
View file

@ -236,7 +236,7 @@
/* ADC 1 2 3 clock source - pll2_pclk */
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* FLASH wait states
*

2
boards/arm/stm32h7/stm32h747i-disco/include/board.h
View file

@ -232,7 +232,7 @@
/* ADC 1 2 3 clock source - pll2_pclk */
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* FLASH wait states
*