From e084c52e1238baaf27fd35e631e575c977b37ad2 Mon Sep 17 00:00:00 2001 From: Philippe Leduc Date: Mon, 24 Jul 2023 18:41:05 +0200 Subject: [PATCH] Add i.MX8MP Cortex-M7 port for NuttX --- arch/arm/Kconfig | 19 + arch/arm/include/mx8mp/chip.h | 61 + arch/arm/include/mx8mp/irq.h | 81 ++ arch/arm/include/mx8mp/mx8mp_irq.h | 208 +++ arch/arm/src/mx8mp/Kconfig | 41 + arch/arm/src/mx8mp/Make.defs | 37 + arch/arm/src/mx8mp/chip.h | 51 + arch/arm/src/mx8mp/hardware/mx8mp_ccm.h | 468 +++++++ arch/arm/src/mx8mp/hardware/mx8mp_gpc.h | 53 + arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h | 117 ++ arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h | 906 +++++++++++++ arch/arm/src/mx8mp/hardware/mx8mp_rdc.h | 52 + arch/arm/src/mx8mp/hardware/mx8mp_uart.h | 263 ++++ arch/arm/src/mx8mp/mx8mp_allocateheap.c | 185 +++ arch/arm/src/mx8mp/mx8mp_ccm.c | 642 +++++++++ arch/arm/src/mx8mp/mx8mp_ccm.h | 116 ++ arch/arm/src/mx8mp/mx8mp_clockconfig.c | 149 +++ arch/arm/src/mx8mp/mx8mp_clockconfig.h | 46 + arch/arm/src/mx8mp/mx8mp_clrpend.c | 80 ++ arch/arm/src/mx8mp/mx8mp_config.h | 73 ++ arch/arm/src/mx8mp/mx8mp_idle.c | 90 ++ arch/arm/src/mx8mp/mx8mp_iomuxc.c | 81 ++ arch/arm/src/mx8mp/mx8mp_iomuxc.h | 53 + arch/arm/src/mx8mp/mx8mp_irq.c | 566 ++++++++ arch/arm/src/mx8mp/mx8mp_lowputc.c | 412 ++++++ arch/arm/src/mx8mp/mx8mp_lowputc.h | 81 ++ arch/arm/src/mx8mp/mx8mp_mpuinit.c | 167 +++ arch/arm/src/mx8mp/mx8mp_mpuinit.h | 88 ++ arch/arm/src/mx8mp/mx8mp_serial.c | 1151 +++++++++++++++++ arch/arm/src/mx8mp/mx8mp_serial.h | 83 ++ arch/arm/src/mx8mp/mx8mp_start.c | 184 +++ arch/arm/src/mx8mp/mx8mp_start.h | 47 + arch/arm/src/mx8mp/mx8mp_timerisr.c | 127 ++ arch/arm/src/mx8mp/mx8mp_userspace.h | 49 + boards/Kconfig | 10 + boards/arm/mx8mp/verdin-mx8mp/Kconfig | 4 + boards/arm/mx8mp/verdin-mx8mp/README.txt | 10 + .../mx8mp/verdin-mx8mp/configs/nsh/defconfig | 44 + boards/arm/mx8mp/verdin-mx8mp/include/board.h | 67 + .../arm/mx8mp/verdin-mx8mp/scripts/Make.defs | 46 + boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld | 110 ++ boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld | 105 ++ boards/arm/mx8mp/verdin-mx8mp/src/Makefile | 29 + .../mx8mp/verdin-mx8mp/src/mx8mp_appinit.c | 71 + .../arm/mx8mp/verdin-mx8mp/src/mx8mp_boot.c | 75 ++ .../mx8mp/verdin-mx8mp/src/mx8mp_bringup.c | 62 + .../arm/mx8mp/verdin-mx8mp/src/verdin-mx8mp.h | 59 + 47 files changed, 7519 insertions(+) create mode 100644 arch/arm/include/mx8mp/chip.h create mode 100644 arch/arm/include/mx8mp/irq.h create mode 100644 arch/arm/include/mx8mp/mx8mp_irq.h create mode 100644 arch/arm/src/mx8mp/Kconfig create mode 100644 arch/arm/src/mx8mp/Make.defs create mode 100644 arch/arm/src/mx8mp/chip.h create mode 100644 arch/arm/src/mx8mp/hardware/mx8mp_ccm.h create mode 100644 arch/arm/src/mx8mp/hardware/mx8mp_gpc.h create mode 100644 arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h create mode 100644 arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h create mode 100644 arch/arm/src/mx8mp/hardware/mx8mp_rdc.h create mode 100644 arch/arm/src/mx8mp/hardware/mx8mp_uart.h create mode 100644 arch/arm/src/mx8mp/mx8mp_allocateheap.c create mode 100644 arch/arm/src/mx8mp/mx8mp_ccm.c create mode 100644 arch/arm/src/mx8mp/mx8mp_ccm.h create mode 100644 arch/arm/src/mx8mp/mx8mp_clockconfig.c create mode 100644 arch/arm/src/mx8mp/mx8mp_clockconfig.h create mode 100644 arch/arm/src/mx8mp/mx8mp_clrpend.c create mode 100644 arch/arm/src/mx8mp/mx8mp_config.h create mode 100644 arch/arm/src/mx8mp/mx8mp_idle.c create mode 100644 arch/arm/src/mx8mp/mx8mp_iomuxc.c create mode 100644 arch/arm/src/mx8mp/mx8mp_iomuxc.h create mode 100644 arch/arm/src/mx8mp/mx8mp_irq.c create mode 100644 arch/arm/src/mx8mp/mx8mp_lowputc.c create mode 100644 arch/arm/src/mx8mp/mx8mp_lowputc.h create mode 100644 arch/arm/src/mx8mp/mx8mp_mpuinit.c create mode 100644 arch/arm/src/mx8mp/mx8mp_mpuinit.h create mode 100644 arch/arm/src/mx8mp/mx8mp_serial.c create mode 100644 arch/arm/src/mx8mp/mx8mp_serial.h create mode 100644 arch/arm/src/mx8mp/mx8mp_start.c create mode 100644 arch/arm/src/mx8mp/mx8mp_start.h create mode 100644 arch/arm/src/mx8mp/mx8mp_timerisr.c create mode 100644 arch/arm/src/mx8mp/mx8mp_userspace.h create mode 100644 boards/arm/mx8mp/verdin-mx8mp/Kconfig create mode 100644 boards/arm/mx8mp/verdin-mx8mp/README.txt create mode 100644 boards/arm/mx8mp/verdin-mx8mp/configs/nsh/defconfig create mode 100644 boards/arm/mx8mp/verdin-mx8mp/include/board.h create mode 100644 boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs create mode 100644 boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld create mode 100644 boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld create mode 100644 boards/arm/mx8mp/verdin-mx8mp/src/Makefile create mode 100644 boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_appinit.c create mode 100644 boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_boot.c create mode 100644 boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c create mode 100644 boards/arm/mx8mp/verdin-mx8mp/src/verdin-mx8mp.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a6ca1cd071..b43121be95 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -602,6 +602,21 @@ config ARCH_CHIP_XMC4 ---help--- Infineon XMC4xxx(ARM Cortex-M4) architectures +config ARCH_CHIP_MX8MP + bool "NXP i.MX8MP" + select ARCH_CORTEXM7 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_RAMFUNCS + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select ARMV7M_HAVE_STACKCHECK + ---help--- + NXP i.MX8MP (ARM Cortex-M7) architectures + config ARCH_CHIP_CXD56XX bool "Sony CXD56xx" select ARCH_CORTEXM4 @@ -1036,6 +1051,7 @@ config ARCH_CHIP default "str71x" if ARCH_CHIP_STR71X default "tms570" if ARCH_CHIP_TMS570 default "xmc4" if ARCH_CHIP_XMC4 + default "mx8mp" if ARCH_CHIP_MX8MP default "cxd56xx" if ARCH_CHIP_CXD56XX default "phy62xx" if ARCH_CHIP_PHY62XX default "tlsr82" if ARCH_CHIP_TLSR82 @@ -1490,6 +1506,9 @@ endif if ARCH_CHIP_XMC4 source "arch/arm/src/xmc4/Kconfig" endif +if ARCH_CHIP_MX8MP +source "arch/arm/src/mx8mp/Kconfig" +endif if ARCH_CHIP_PHY62XX source "arch/arm/src/phy62xx/Kconfig" endif diff --git a/arch/arm/include/mx8mp/chip.h b/arch/arm/include/mx8mp/chip.h new file mode 100644 index 0000000000..30b45ce473 --- /dev/null +++ b/arch/arm/include/mx8mp/chip.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/include/mx8mp/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_MX8MP_CHIP_H +#define __ARCH_ARM_INCLUDE_MX8MP_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value. The lower the value, the + * greater the priority of the corresponding interrupt. + * The mx8mp implements only bits[7:4] of this field, bits[3:0] + * read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_MX8MP_CHIP_H */ diff --git a/arch/arm/include/mx8mp/irq.h b/arch/arm/include/mx8mp/irq.h new file mode 100644 index 0000000000..e762024f95 --- /dev/null +++ b/arch/arm/include/mx8mp/irq.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/include/mx8mp/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_MX8MP_IRQ_H +#define __ARCH_ARM_INCLUDE_MX8MP_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define MX8MP_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) + * Vector 0: Reset stack pointer value + * Vector 1: Reset (not handler as an IRQ) */ +#define MX8MP_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define MX8MP_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define MX8MP_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define MX8MP_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define MX8MP_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault + * Vectors 7-10: Reserved */ +#define MX8MP_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define MX8MP_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor + * Vector 13: Reserved */ +#define MX8MP_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define MX8MP_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define MX8MP_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +#if defined(CONFIG_ARCH_CHIP_MX8MP) +# include +#else +/* The interrupt vectors for other parts are defined in other documents and + * may or may not be the same as above (the family members are all very + * similar). + * This error just means that you have to look at the document and determine + * for yourself if the vectors are the same. + */ + +# error "No IRQ numbers for this MX8Mx part" +#endif + +#endif /* __ARCH_ARM_INCLUDE_MX8MP_IRQ_H */ diff --git a/arch/arm/include/mx8mp/mx8mp_irq.h b/arch/arm/include/mx8mp/mx8mp_irq.h new file mode 100644 index 0000000000..ebf1093c50 --- /dev/null +++ b/arch/arm/include/mx8mp/mx8mp_irq.h @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/arm/include/mx8mp/mx8mp_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef ARCH_ARM_INCLUDE_MX8MP_IRQ_H +#define ARCH_ARM_INCLUDE_MX8MP_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/mx8mp/irq.h which includes this file + * + * External interrupts (vectors >= 16) + */ + +#define MX8MP_IRQ_DAP (MX8MP_IRQ_FIRST + 1) +#define MX8MP_IRQ_SDMA1 (MX8MP_IRQ_FIRST + 2) +#define MX8MP_IRQ_GPU3D (MX8MP_IRQ_FIRST + 3) +#define MX8MP_IRQ_SNVS_ONOFF (MX8MP_IRQ_FIRST + 4) +#define MX8MP_IRQ_LCDIF1 (MX8MP_IRQ_FIRST + 5) +#define MX8MP_IRQ_LCDIF2 (MX8MP_IRQ_FIRST + 6) +#define MX8MP_IRQ_VPU_G1 (MX8MP_IRQ_FIRST + 7) +#define MX8MP_IRQ_VPU_G2 (MX8MP_IRQ_FIRST + 8) +#define MX8MP_IRQ_QOS (MX8MP_IRQ_FIRST + 9) +#define MX8MP_IRQ_WDOG3 (MX8MP_IRQ_FIRST + 10) +#define MX8MP_IRQ_HS_CP1 (MX8MP_IRQ_FIRST + 11) +#define MX8MP_IRQ_APBHDMA (MX8MP_IRQ_FIRST + 12) +#define MX8MP_IRQ_NPU (MX8MP_IRQ_FIRST + 13) +#define MX8MP_IRQ_RAWNAND_BCH (MX8MP_IRQ_FIRST + 14) +#define MX8MP_IRQ_RAWNAND_GPMI (MX8MP_IRQ_FIRST + 15) +#define MX8MP_IRQ_ISI_C0 (MX8MP_IRQ_FIRST + 16) +#define MX8MP_IRQ_MIPI_CSI1 (MX8MP_IRQ_FIRST + 17) +#define MX8MP_IRQ_MIPI_DSI (MX8MP_IRQ_FIRST + 18) +#define MX8MP_IRQ_SNVS_SRTC_NTZ (MX8MP_IRQ_FIRST + 19) +#define MX8MP_IRQ_SNVS_SRTC_TZ (MX8MP_IRQ_FIRST + 20) +#define MX8MP_IRQ_CSU (MX8MP_IRQ_FIRST + 21) +#define MX8MP_IRQ_USDHC1 (MX8MP_IRQ_FIRST + 22) +#define MX8MP_IRQ_USDHC2 (MX8MP_IRQ_FIRST + 23) +#define MX8MP_IRQ_USDHC3 (MX8MP_IRQ_FIRST + 24) +#define MX8MP_IRQ_GPU2D (MX8MP_IRQ_FIRST + 25) +#define MX8MP_IRQ_UART1 (MX8MP_IRQ_FIRST + 26) +#define MX8MP_IRQ_UART2 (MX8MP_IRQ_FIRST + 27) +#define MX8MP_IRQ_UART3 (MX8MP_IRQ_FIRST + 28) +#define MX8MP_IRQ_UART4 (MX8MP_IRQ_FIRST + 29) +#define MX8MP_IRQ_VPU (MX8MP_IRQ_FIRST + 30) +#define MX8MP_IRQ_ECSPI1 (MX8MP_IRQ_FIRST + 31) +#define MX8MP_IRQ_ECSPI2 (MX8MP_IRQ_FIRST + 32) +#define MX8MP_IRQ_ECSPI3 (MX8MP_IRQ_FIRST + 33) +#define MX8MP_IRQ_SDMA3 (MX8MP_IRQ_FIRST + 34) +#define MX8MP_IRQ_I2C1 (MX8MP_IRQ_FIRST + 35) +#define MX8MP_IRQ_I2C2 (MX8MP_IRQ_FIRST + 36) +#define MX8MP_IRQ_I2C3 (MX8MP_IRQ_FIRST + 37) +#define MX8MP_IRQ_I2C4 (MX8MP_IRQ_FIRST + 38) +#define MX8MP_IRQ_RDC (MX8MP_IRQ_FIRST + 39) +#define MX8MP_IRQ_USB1 (MX8MP_IRQ_FIRST + 40) +#define MX8MP_IRQ_USB2 (MX8MP_IRQ_FIRST + 41) +#define MX8MP_IRQ_ISI_C1 (MX8MP_IRQ_FIRST + 42) +#define MX8MP_IRQ_HDMI_TX (MX8MP_IRQ_FIRST + 43) +#define MX8MP_IRQ_MICFIL0 (MX8MP_IRQ_FIRST + 44) +#define MX8MP_IRQ_MICFIL1 (MX8MP_IRQ_FIRST + 45) +#define MX8MP_IRQ_GPT6 (MX8MP_IRQ_FIRST + 46) +#define MX8MP_IRQ_SCTR0 (MX8MP_IRQ_FIRST + 47) +#define MX8MP_IRQ_SCTR1 (MX8MP_IRQ_FIRST + 48) +#define MX8MP_IRQ_ANAMIX (MX8MP_IRQ_FIRST + 49) +#define MX8MP_IRQ_SAI3 (MX8MP_IRQ_FIRST + 50) +#define MX8MP_IRQ_GPT5 (MX8MP_IRQ_FIRST + 51) +#define MX8MP_IRQ_GPT4 (MX8MP_IRQ_FIRST + 52) +#define MX8MP_IRQ_GPT3 (MX8MP_IRQ_FIRST + 53) +#define MX8MP_IRQ_GPT2 (MX8MP_IRQ_FIRST + 54) +#define MX8MP_IRQ_GPT1 (MX8MP_IRQ_FIRST + 55) +#define MX8MP_IRQ_GPIO1_7 (MX8MP_IRQ_FIRST + 56) +#define MX8MP_IRQ_GPIO1_6 (MX8MP_IRQ_FIRST + 57) +#define MX8MP_IRQ_GPIO1_5 (MX8MP_IRQ_FIRST + 58) +#define MX8MP_IRQ_GPIO1_4 (MX8MP_IRQ_FIRST + 59) +#define MX8MP_IRQ_GPIO1_3 (MX8MP_IRQ_FIRST + 60) +#define MX8MP_IRQ_GPIO1_2 (MX8MP_IRQ_FIRST + 61) +#define MX8MP_IRQ_GPIO1_1 (MX8MP_IRQ_FIRST + 62) +#define MX8MP_IRQ_GPIO1_0 (MX8MP_IRQ_FIRST + 63) +#define MX8MP_IRQ_GPIO1_0_15 (MX8MP_IRQ_FIRST + 64) +#define MX8MP_IRQ_GPIO1_16_31 (MX8MP_IRQ_FIRST + 65) +#define MX8MP_IRQ_GPIO2_0_15 (MX8MP_IRQ_FIRST + 66) +#define MX8MP_IRQ_GPIO2_16_31 (MX8MP_IRQ_FIRST + 67) +#define MX8MP_IRQ_GPIO3_0_15 (MX8MP_IRQ_FIRST + 68) +#define MX8MP_IRQ_GPIO3_16_31 (MX8MP_IRQ_FIRST + 69) +#define MX8MP_IRQ_GPIO4_0_15 (MX8MP_IRQ_FIRST + 70) +#define MX8MP_IRQ_GPIO4_16_31 (MX8MP_IRQ_FIRST + 71) +#define MX8MP_IRQ_GPIO5_0_15 (MX8MP_IRQ_FIRST + 72) +#define MX8MP_IRQ_GPIO5_16_31 (MX8MP_IRQ_FIRST + 73) +#define MX8MP_IRQ_ISP1 (MX8MP_IRQ_FIRST + 74) +#define MX8MP_IRQ_ISP2 (MX8MP_IRQ_FIRST + 75) +#define MX8MP_IRQ_I2C5 (MX8MP_IRQ_FIRST + 76) +#define MX8MP_IRQ_I2C6 (MX8MP_IRQ_FIRST + 77) +#define MX8MP_IRQ_WDOG1 (MX8MP_IRQ_FIRST + 78) +#define MX8MP_IRQ_WDOG2 (MX8MP_IRQ_FIRST + 79) +#define MX8MP_IRQ_MIPI_CSI2 (MX8MP_IRQ_FIRST + 80) +#define MX8MP_IRQ_PWM1 (MX8MP_IRQ_FIRST + 81) +#define MX8MP_IRQ_PWM2 (MX8MP_IRQ_FIRST + 82) +#define MX8MP_IRQ_PWM3 (MX8MP_IRQ_FIRST + 83) +#define MX8MP_IRQ_PWM4 (MX8MP_IRQ_FIRST + 84) +#define MX8MP_IRQ_CCM1 (MX8MP_IRQ_FIRST + 85) +#define MX8MP_IRQ_CCM2 (MX8MP_IRQ_FIRST + 86) +#define MX8MP_IRQ_GPC1 (MX8MP_IRQ_FIRST + 87) +#define MX8MP_IRQ_MU1_A53 (MX8MP_IRQ_FIRST + 88) +#define MX8MP_IRQ_SRC1 (MX8MP_IRQ_FIRST + 89) +#define MX8MP_IRQ_SAI5 (MX8MP_IRQ_FIRST + 90) +#define MX8MP_IRQ_CAAM (MX8MP_IRQ_FIRST + 91) +#define MX8MP_IRQ_CPU_PERF (MX8MP_IRQ_FIRST + 92) +#define MX8MP_IRQ_CPU_CTI (MX8MP_IRQ_FIRST + 93) +#define MX8MP_IRQ_WDOG_ALL (MX8MP_IRQ_FIRST + 94) +#define MX8MP_IRQ_SAI1 (MX8MP_IRQ_FIRST + 95) +#define MX8MP_IRQ_SAI2 (MX8MP_IRQ_FIRST + 96) +#define MX8MP_IRQ_MU1_M7 (MX8MP_IRQ_FIRST + 97) +#define MX8MP_IRQ_DDR (MX8MP_IRQ_FIRST + 98) +#define MX8MP_IRQ_DDR_DFI (MX8MP_IRQ_FIRST + 99) +#define MX8MP_IRQ_DEWARP (MX8MP_IRQ_FIRST + 100) +#define MX8MP_IRQ_ERROR_AXI (MX8MP_IRQ_FIRST + 101) +#define MX8MP_IRQ_ERROR_ECC (MX8MP_IRQ_FIRST + 102) +#define MX8MP_IRQ_SDMA2 (MX8MP_IRQ_FIRST + 103) +#define MX8MP_IRQ_SJC (MX8MP_IRQ_FIRST + 104) +#define MX8MP_IRQ_CAAM_JQ0 (MX8MP_IRQ_FIRST + 105) +#define MX8MP_IRQ_CAAM_JQ1 (MX8MP_IRQ_FIRST + 106) +#define MX8MP_IRQ_FLEXSPI (MX8MP_IRQ_FIRST + 107) +#define MX8MP_IRQ_TSASC (MX8MP_IRQ_FIRST + 108) +#define MX8MP_IRQ_MICFIL0 (MX8MP_IRQ_FIRST + 109) +#define MX8MP_IRQ_MIFIL1 (MX8MP_IRQ_FIRST + 110) +#define MX8MP_IRQ_SAI7 (MX8MP_IRQ_FIRST + 111) +#define MX8MP_IRQ_PERFMON1 (MX8MP_IRQ_FIRST + 112) +#define MX8MP_IRQ_PERFMON2 (MX8MP_IRQ_FIRST + 113) +#define MX8MP_IRQ_CAAM_JQ2 (MX8MP_IRQ_FIRST + 114) +#define MX8MP_IRQ_CAAM_ERROR (MX8MP_IRQ_FIRST + 115) +#define MX8MP_IRQ_HS_CP0 (MX8MP_IRQ_FIRST + 116) +#define MX8MP_IRQ_CM7 (MX8MP_IRQ_FIRST + 117) +#define MX8MP_IRQ_ENET1_0 (MX8MP_IRQ_FIRST + 118) +#define MX8MP_IRQ_ENET1_1 (MX8MP_IRQ_FIRST + 119) +#define MX8MP_IRQ_ENET1_2 (MX8MP_IRQ_FIRST + 120) +#define MX8MP_IRQ_ENET1_3 (MX8MP_IRQ_FIRST + 121) +#define MX8MP_IRQ_ASRC (MX8MP_IRQ_FIRST + 122) +#define MX8MP_IRQ_PCIE_0 (MX8MP_IRQ_FIRST + 123) +#define MX8MP_IRQ_PCIE_1 (MX8MP_IRQ_FIRST + 124) +#define MX8MP_IRQ_PCIE_2 (MX8MP_IRQ_FIRST + 125) +#define MX8MP_IRQ_PCIE_3 (MX8MP_IRQ_FIRST + 126) +#define MX8MP_IRQ_PCIE_4 (MX8MP_IRQ_FIRST + 127) +#define MX8MP_IRQ_AUDIO_XCVR_0 (MX8MP_IRQ_FIRST + 128) +#define MX8MP_IRQ_AUDIO_XCVR_1 (MX8MP_IRQ_FIRST + 129) +#define MX8MP_IRQ_AUD2HTX (MX8MP_IRQ_FIRST + 130) +#define MX8MP_IRQ_EDMA1_0 (MX8MP_IRQ_FIRST + 131) +#define MX8MP_IRQ_EDMA1_1 (MX8MP_IRQ_FIRST + 132) +#define MX8MP_IRQ_EDMA1_2 (MX8MP_IRQ_FIRST + 133) +#define MX8MP_IRQ_ENET_QOS_0 (MX8MP_IRQ_FIRST + 134) +#define MX8MP_IRQ_ENET_QOS_1 (MX8MP_IRQ_FIRST + 135) +#define MX8MP_IRQ_MU2_A53 (MX8MP_IRQ_FIRST + 136) +#define MX8MP_IRQ_MU2_DSP (MX8MP_IRQ_FIRST + 137) +#define MX8MP_IRQ_MU3_M7 (MX8MP_IRQ_FIRST + 138) +#define MX8MP_IRQ_MU3_DSP (MX8MP_IRQ_FIRST + 139) +#define MX8MP_IRQ_PCIE_5 (MX8MP_IRQ_FIRST + 140) +#define MX8MP_IRQ_PCIE_6 (MX8MP_IRQ_FIRST + 141) +#define MX8MP_IRQ_CAN_FD1_0 (MX8MP_IRQ_FIRST + 142) +#define MX8MP_IRQ_CAN_FD1_1 (MX8MP_IRQ_FIRST + 143) +#define MX8MP_IRQ_CAN_FD2_0 (MX8MP_IRQ_FIRST + 144) +#define MX8MP_IRQ_CAN_FD2_1 (MX8MP_IRQ_FIRST + 145) +#define MX8MP_IRQ_AUDIO_XCVR (MX8MP_IRQ_FIRST + 146) +#define MX8MP_IRQ_DDR_ECC (MX8MP_IRQ_FIRST + 147) +#define MX8MP_IRQ_USB1 (MX8MP_IRQ_FIRST + 148) +#define MX8MP_IRQ_USB2 (MX8MP_IRQ_FIRST + 149) + +#define MX8MP_IRQ_NEXTINTS 160 /* 112 Non core IRQs */ + +/* 160 vectors */ + +#define MX8MP_IRQ_NVECTORS (MX8MP_IRQ_FIRST + MX8MP_IRQ_NEXTINTS) + +/* GPIO IRQ interrupts -- To be provided */ + +#define NR_IRQS MX8MP_IRQ_NVECTORS + +#endif /* ARCH_ARM_INCLUDE_MX8MP_IRQ_H */ diff --git a/arch/arm/src/mx8mp/Kconfig b/arch/arm/src/mx8mp/Kconfig new file mode 100644 index 0000000000..496057ea94 --- /dev/null +++ b/arch/arm/src/mx8mp/Kconfig @@ -0,0 +1,41 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "i.MX8MP Configuration Options" + +menu "i.MX8MP Peripheral Selection" + +config MX8MP_UART1 + bool "UART1" + default n + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MX8MP_UART2 + bool "UART2" + default n + select UART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MX8MP_UART3 + bool "UART3" + default n + select UART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config MX8MP_UART4 + bool "UART4" + default n + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +endmenu + +# These "hidden" settings determine whether a peripheral option is available +# for the selected MCU + +# When there are multiple instances of a device, these "hidden" settings +# will automatically be selected and will represent the 'OR' of the +# instances selected. diff --git a/arch/arm/src/mx8mp/Make.defs b/arch/arm/src/mx8mp/Make.defs new file mode 100644 index 0000000000..53a891086a --- /dev/null +++ b/arch/arm/src/mx8mp/Make.defs @@ -0,0 +1,37 @@ +############################################################################ +# arch/arm/src/mx8mp/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +# Required mx8mp files + +CHIP_CSRCS = mx8mp_start.c mx8mp_allocateheap.c mx8mp_iomuxc.c mx8mp_lowputc.c +CHIP_CSRCS += mx8mp_clrpend.c mx8mp_irq.c mx8mp_mpuinit.c mx8mp_ccm.c +CHIP_CSRCS += mx8mp_serial.c mx8mp_clockconfig.c + +# Configuration-dependent files + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += mx8mp_idle.c +endif + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += mx8mp_timerisr.c +endif diff --git a/arch/arm/src/mx8mp/chip.h b/arch/arm/src/mx8mp/chip.h new file mode 100644 index 0000000000..2bfa7a5423 --- /dev/null +++ b/arch/arm/src/mx8mp/chip.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_CHIP_H +#define __ARCH_ARM_SRC_MX8MP_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include +#include +#include "hardware/mx8mp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported + * external interrupts which, for this architecture, is provided in the + * arch/mx8m/chip.h header file. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS MX8MP_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_MX8MP_CHIP_H */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h b/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h new file mode 100644 index 0000000000..bc3a0edb50 --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h @@ -0,0 +1,468 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_ccm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reference: + * "i.MX 8M Plus Applications Processor Reference Manual", + * Document Number: IMX8MPRM Rev. 1, 06/2021. NXP + */ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_CCM_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mx8mp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CCM Register Addresses ***************************************************/ + +#define CCM_GPR0 (MX8M_CCM + 0) +#define CCM_PLL_BASE (MX8M_CCM + 0x800) +#define CCM_CCGR_BASE (MX8M_CCM + 0x4000) +#define CCM_CLK_ROOT_BASE (MX8M_CCM + 0x8000) + +/* CCM Common Register Offsets **********************************************/ + +#define CCM_SET 0x4 +#define CCM_CLR 0x8 +#define CCM_TOG 0xC + +/* CCM Clock Gating definitions *********************************************/ + +/* Chapter 5.1.2 Clock Root Selects */ + +#define CCM_DVFS_CLK_GATE 0 +#define CCM_ANAMIX_CLK_GATE 1 +#define CCM_CPU_CLK_GATE 2 +#define CCM_CSU_CLK_GATE 3 +#define CCM_DEBUG_CLK_GATE 4 +#define CCM_DDRAM1_CLK_GATE 5 +#define CCM_ECSPI1_CLK_GATE 7 +#define CCM_ECSPI2_CLK_GATE 8 +#define CCM_ECSPI3_CLK_GATE 9 +#define CCM_ENET1_CLK_GATE 10 +#define CCM_GPIO1_CLK_GATE 11 +#define CCM_GPIO2_CLK_GATE 12 +#define CCM_GPIO3_CLK_GATE 13 +#define CCM_GPIO4_CLK_GATE 14 +#define CCM_GPIO5_CLK_GATE 15 +#define CCM_GPT1_CLK_GATE 16 +#define CCM_GPT2_CLK_GATE 17 +#define CCM_GPT3_CLK_GATE 18 +#define CCM_GPT4_CLK_GATE 19 +#define CCM_GPT5_CLK_GATE 20 +#define CCM_GPT6_CLK_GATE 21 +#define CCM_HS_CLK_GATE 22 +#define CCM_I2C1_CLK_GATE 23 +#define CCM_I2C2_CLK_GATE 24 +#define CCM_I2C3_CLK_GATE 25 +#define CCM_I2C4_CLK_GATE 26 +#define CCM_IOMUX_CLK_GATE 27 +#define CCM_IPMUX1_CLK_GATE 28 +#define CCM_IPMUX2_CLK_GATE 29 +#define CCM_IPMUX3_CLK_GATE 30 +#define CCM_MU_CLK_GATE 33 +#define CCM_OCOTP_CLK_GATE 34 +#define CCM_OCRAM_CLK_GATE 35 +#define CCM_OCRAM_S_CLK_GATE 36 +#define CCM_PCIE_CLK_GATE 37 +#define CCM_PERFMON1_CLK_GATE 38 +#define CCM_PERFMON2_CLK_GATE 39 +#define CCM_PWM1_CLK_GATE 40 +#define CCM_PWM2_CLK_GATE 41 +#define CCM_PWM3_CLK_GATE 42 +#define CCM_PWM4_CLK_GATE 43 +#define CCM_QOS_CLK_GATE 44 +#define CCM_QOS_ETHENET_CLK_GATE 46 +#define CCM_FLEXSPI_CLK_GATE 47 +#define CCM_RAWNAND_CLK_GATE 48 +#define CCM_RDC_CLK_GATE 49 +#define CCM_ROM_CLK_GATE 50 +#define CCM_I2C5_CLK_GATE 51 +#define CCM_I2C6_CLK_GATE 52 +#define CCM_CAN1_CLK_GATE 53 +#define CCM_CAN2_CLK_GATE 54 +#define CCM_SCTR_CLK_GATE 57 +#define CCM_SDMA1_CLK_GATE 58 +#define CCM_ENET_QOS_CLK_GATE 59 +#define CCM_SEC_DEBUG_CLK_GATE 60 +#define CCM_SEMA1_CLK_GATE 61 +#define CCM_SEMA2_CLK_GATE 62 +#define CCM_IRQ_STEER_CLK_GATE 63 +#define CCM_SIM_ENET_CLK_GATE 64 +#define CCM_SIM_M_CLK_GATE 65 +#define CCM_SIM_MAIN_CLK_GATE 66 +#define CCM_SIM_S_CLK_GATE 67 +#define CCM_SIM_WAKEUP_CLK_GATE 68 +#define CCM_GPU2D_CLK_GATE 69 +#define CCM_GPU3D_CLK_GATE 70 +#define CCM_SNVS_CLK_GATE 71 +#define CCM_TRACE_CLK_GATE 72 +#define CCM_UART1_CLK_GATE 73 +#define CCM_UART2_CLK_GATE 74 +#define CCM_UART3_CLK_GATE 75 +#define CCM_UART4_CLK_GATE 76 +#define CCM_USB_CLK_GATE 77 +#define CCM_USB_PHY_CLK_GATE 79 +#define CCM_USDHC1_CLK_GATE 81 +#define CCM_USDHC2_CLK_GATE 82 +#define CCM_WDOG1_CLK_GATE 83 +#define CCM_WDOG2_CLK_GATE 84 +#define CCM_WDOG3_CLK_GATE 85 +#define CCM_VPU_G1_CLK_GATE 86 +#define CCM_GPU_CLK_GATE 87 +#define CCM_NOC_WRAPPER_CLK_GATE 88 +#define CCM_VPU_VC8KE_CLK_GATE 89 +#define CCM_VPUG2_CLK_GATE 90 +#define CCM_NPU_CLK_GATE 91 +#define CCM_HSIO_CLK_GATE 92 +#define CCM_MEDIA_CLK_GATE 93 +#define CCM_USDHC3_CLK_GATE 94 +#define CCM_HDMI_CLK_GATE 95 +#define CCM_XTAL_CLK_GATE 96 +#define CCM_PLL_CLK_GATE 97 +#define CCM_TSENSOR_CLK_GATE 98 +#define CCM_VPU_CLK_GATE 99 +#define CCM_MRPR_CLK_GATE 100 +#define CCM_AUDIO_CLK_GATE 101 + +/* CCM Clock Gating Bit Definitions *****************************************/ + +/* Note: only bits of our domain will be applied - cf. 5.1.6.3 */ +#define CLK_NOT_NEEDED 0x0000 +#define CLK_RUN_NEEDED 0x1111 +#define CLK_RUN_WAIT_NEEDED 0x2222 +#define CLK_ALWAYS_NEEDED 0x3333 + +/* Clock root select definitions ********************************************/ + +/* Chapter 5.1.2 Clock Root Selects */ +#define ARM_A53_CLK_ROOT 0 +#define ARM_M7_CLK_ROOT 1 +#define ML_CLK_ROOT 2 +#define GPU3D_CORE_CLK_ROOT 3 +#define GPU3D_SHADER_CLK_ROOT 4 +#define GPU2D_CLK_ROOT 5 +#define AUDIO_AXI_CLK_ROOT 6 +#define HSIO_AXI_CLK_ROOT 7 +#define MEDIA_ISP_CLK_ROOT 8 +#define MAIN_AXI_CLK_ROOT 16 +#define ENET_AXI_CLK_ROOT 17 +#define NAND_USDHC_BUS_CLK_ROOT 18 +#define VPU_BUS_CLK_ROOT 19 +#define MEDIA_AXI_CLK_ROOT 20 +#define MEDIA_APB_CLK_ROOT 21 +#define HDMI_APB_CLK_ROOT 22 +#define HDMI_AXI_CLK_ROOT 23 +#define GPU_AXI_CLK_ROOT 24 +#define GPU_AHB_CLK_ROOT 25 +#define NOC_CLK_ROOT 26 +#define NOC_IO_CLK_ROOT 27 +#define ML_AXI_CLK_ROOT 28 +#define ML_AHB_CLK_ROOT 29 +#define AHB_CLK_ROOT 32 +#define IPG_CLK_ROOT 33 +#define AUDIO_AHB_CLK_ROOT 34 +#define MEDIA_DISP2_CLK_ROOT 38 +#define DRAM_SEL_CFG 48 +#define ARM_A53_CLK_ROOT_SEL 49 +#define DRAM_ALT_CLK_ROOT 64 +#define DRAM_APB_CLK_ROOT 65 +#define VPU_G1_CLK_ROOT 66 +#define VPU_G2_CLK_ROOT 67 +#define CAN1_CLK_ROOT 68 +#define CAN2_CLK_ROOT 69 +#define MEMREPAIR_CLK_ROOT 70 +#define PCIE_PHY_CLK_ROOT 71 +#define PCIE_AUX_CLK_ROOT 72 +#define I2C5_CLK_ROOT 73 +#define I2C6_CLK_ROOT 74 +#define SAI1_CLK_ROOT 75 +#define SAI2_CLK_ROOT 76 +#define SAI3_CLK_ROOT 77 +#define SAI5_CLK_ROOT 79 +#define SAI6_CLK_ROOT 80 +#define ENET_QOS_CLK_ROOT 81 +#define ENET_QOS_TIMER_CLK_ROOT 82 +#define ENET_REF_CLK_ROOT 83 +#define ENET_TIMER_CLK_ROOT 84 +#define ENET_PHY_REF_CLK_ROOT 85 +#define NAND_CLK_ROOT 86 +#define QSPI_CLK_ROOT 87 +#define USDHC1_CLK_ROOT 88 +#define USDHC2_CLK_ROOT 89 +#define I2C1_CLK_ROOT 90 +#define I2C2_CLK_ROOT 91 +#define I2C3_CLK_ROOT 92 +#define I2C4_CLK_ROOT 93 +#define UART1_CLK_ROOT 94 +#define UART2_CLK_ROOT 95 +#define UART3_CLK_ROOT 96 +#define UART4_CLK_ROOT 97 +#define GIC_CLK_ROOT 100 +#define ECSPI1_CLK_ROOT 101 +#define ECSPI2_CLK_ROOT 102 +#define PWM1_CLK_ROOT 103 +#define PWM2_CLK_ROOT 104 +#define PWM3_CLK_ROOT 105 +#define PWM4_CLK_ROOT 106 +#define GPT1_CLK_ROOT 107 +#define GPT2_CLK_ROOT 108 +#define GPT3_CLK_ROOT 109 +#define GPT4_CLK_ROOT 110 +#define GPT5_CLK_ROOT 111 +#define GPT6_CLK_ROOT 112 +#define TRACE_CLK_ROOT 113 +#define WDOG_CLK_ROOT 114 +#define WRCLK_CLK_ROOT 115 +#define IPP_DO_CLKO1 116 +#define IPP_DO_CLKO2 117 +#define HDMI_FDCC_TST_CLK_ROOT 118 +#define HDMI_27M_CLK_ROOT 119 +#define HDMI_REF_266M_CLK_ROOT 120 +#define USDHC3_CLK_ROOT 121 +#define MEDIA_CAM1_PIX_CLK_ROOT 122 +#define MEDIA_MIPI_PHY1_REF_CLK_ROOT 123 +#define MEDIA_DISP1_PIX_CLK_ROOT 124 +#define MEDIA_CAM2_PIX_CLK_ROOT 125 +#define MEDIA_LDB_CLK_ROOT 126 +#define MEDIA_MIPI_TEST_BYTE_CLK 130 +#define ECSPI3_CLK_ROOT 131 +#define PDM_CLK_ROOT 132 +#define VPU_VC8000E_CLK_ROOT 133 +#define SAI7_CLK_ROOT 134 +#define CLOCK_ROOT_MAP_SIZE (SAI7_CLK_ROOT + 1) + +/* CLK_ROOT Register Bit Definitions ****************************************/ + +#define CCM_CLK_ROOT_ENABLE (1 << 28) +#define CCM_CLK_ROOT_MUX_SHIFT 24 +#define CCM_CLK_ROOT_MUX_MASK (7 << CCM_CLK_ROOT_MUX_SHIFT) +#define CCM_CLK_ROOT_PRE_PODF_SHIFT 16 +#define CCM_CLK_ROOT_PRE_PODF_MASK (7 << CCM_CLK_ROOT_PRE_PODF_SHIFT) +#define CCM_CLK_ROOT_POST_PODF_SHIFT 0 +#define CCM_CLK_ROOT_POST_PODF_MASK (0x3f << CCM_CLK_ROOT_POST_PODF_SHIFT) + +/* Analog PLL Register Addresses ********************************************/ + +#define CCM_ANALOG (MX8M_CCM_ANALOG + 0) + +#define CCM_ANALOG_AUDIO_PLL1 (MX8M_CCM_ANALOG + 0x000) +#define CCM_ANALOG_AUDIO_PLL2 (MX8M_CCM_ANALOG + 0x014) +#define CCM_ANALOG_VIDEO_PLL1 (MX8M_CCM_ANALOG + 0x028) +#define CCM_ANALOG_DRAM_PLL (MX8M_CCM_ANALOG + 0x050) +#define CCM_ANALOG_GPU_PLL (MX8M_CCM_ANALOG + 0x064) +#define CCM_ANALOG_VPU_PLL (MX8M_CCM_ANALOG + 0x074) +#define CCM_ANALOG_ARM_PLL (MX8M_CCM_ANALOG + 0x084) +#define CCM_ANALOG_SYSTEM_PLL1 (MX8M_CCM_ANALOG + 0x094) +#define CCM_ANALOG_SYSTEM_PLL2 (MX8M_CCM_ANALOG + 0x104) +#define CCM_ANALOG_SYSTEM_PLL3 (MX8M_CCM_ANALOG + 0x114) + +/* Analog PLL Register Offsets **********************************************/ + +#define CCM_ANALOG_GEN 0 +#define CCM_ANALOG_FDIV0 4 +#define CCM_ANALOG_FDIV1 8 + +/* CLK_ROOT Register Bit Definitions ****************************************/ + +/* General Function Control Register */ + +#define CCM_PLL_LOCK (1 << 31) +#define CCM_PLL_EXT_BYPASS (1 << 16) +#define CCM_PLL_CLKE (1 << 13) +#define CCM_PLL_CLKE_OVERRIDE (1 << 12) +#define CCM_PLL_RST (1 << 9) +#define CCM_PLL_RST_OVERRIDE (1 << 8) +#define CCM_PLL_BYPASS (1 << 4) +#define CCM_PAD_CLK_SEL_SHIFT 2 +#define CCM_PAD_CLK_SEL_MASK (3 << CCM_PAD_CLK_SEL_SHIFT) +#define CCM_PLL_REF_CLK_SEL_SHIFT 0 +#define CCM_PLL_REF_CLK_SEL_MASK (3 << CCM_PLL_REF_CLK_SEL_SHIFT) + +/* Divide and Fraction Data Control 0 Register */ + +#define CCM_FDIV0_MAIN_DIV_SHIFT 12 +#define CCM_FDIV0_MAIN_DIV_MASK (0x3ff << CCM_FDIV0_MAIN_DIV_SHIFT) +#define CCM_FDIV0_PRE_DIV_SHIFT 4 +#define CCM_FDIV0_PRE_DIV_MASK (0x3f << CCM_FDIV0_PRE_DIV_SHIFT) +#define CCM_FDIV0_POST_DIV_SHIFT 0 +#define CCM_FDIV0_POST_DIV_MASK (7 << CCM_FDIV0_POST_DIV_SHIFT) + +/* Divide and Fraction Data Control 1 Register */ + +#define CCM_FDIV1_DSM_SHIFT 0 +#define CCM_FDIV1_DSM_MASK (0xffff << CCM_FDIV1_DSM_SHIFT) + +/* Input clocks definitions *************************************************/ + +#define ARM_PLL_CLK 12 +#define GPU_PLL_CLK 13 +#define VPU_PLL_CLK 14 +#define DRAM_PLL1_CLK 15 +#define SYSTEM_PLL1_CLK 16 +#define SYSTEM_PLL1_DIV2_CLK 17 +#define SYSTEM_PLL1_DIV3_CLK 18 +#define SYSTEM_PLL1_DIV4_CLK 19 +#define SYSTEM_PLL1_DIV5_CLK 20 +#define SYSTEM_PLL1_DIV6_CLK 21 +#define SYSTEM_PLL1_DIV8_CLK 22 +#define SYSTEM_PLL1_DIV10_CLK 23 +#define SYSTEM_PLL1_DIV20_CLK 24 +#define SYSTEM_PLL2_CLK 25 +#define SYSTEM_PLL2_DIV2_CLK 26 +#define SYSTEM_PLL2_DIV3_CLK 27 +#define SYSTEM_PLL2_DIV4_CLK 28 +#define SYSTEM_PLL2_DIV5_CLK 29 +#define SYSTEM_PLL2_DIV6_CLK 30 +#define SYSTEM_PLL2_DIV8_CLK 31 +#define SYSTEM_PLL2_DIV10_CLK 32 +#define SYSTEM_PLL2_DIV20_CLK 33 +#define SYSTEM_PLL3_CLK 34 +#define AUDIO_PLL1_CLK 35 +#define AUDIO_PLL2_CLK 36 +#define VIDEO_PLL_CLK 37 + +/* Theses definitions values are arbitrary: previous definitions + * are used in both PLL_CTRL and clock tree mapping while + * theses definitions have no meaning for PLL_CTR (since they are + * external clock source) but are still use in clock tree mapping. + */ + +#define OSC_32K_REF_CLK 40 +#define OSC_24M_REF_CLK 41 +#define EXT_CLK_1 42 +#define EXT_CLK_2 43 +#define EXT_CLK_3 44 +#define EXT_CLK_4 45 +#define CLK_ROOT_SRC_UNDEFINED 46 + +/* Clock muxing definitions *************************************************/ + +#define ARM_A53_CLK_MUX { OSC_24M_REF_CLK, ARM_PLL_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL1_DIV2_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK } +#define ARM_M7_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV4_CLK, VPU_PLL_CLK, SYSTEM_PLL1_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK } +#define ML_CLK_MUX { OSC_24M_REF_CLK, GPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define GPU3D_CORE_CLK_MUX { OSC_24M_REF_CLK, GPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define GPU3D_SHADER_CLK_MUX { OSC_24M_REF_CLK, GPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define GPU2D_CLK_MUX { OSC_24M_REF_CLK, GPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define AUDIO_AXI_CLK_MUX { OSC_24M_REF_CLK, GPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define HSIO_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL2_DIV5_CLK, EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK } +#define MEDIA_ISP_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV20_CLK, AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_DIV2_CLK } + +#define MAIN_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV3_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV4_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV8_CLK } +#define ENET_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV3_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV4_CLK, SYSTEM_PLL2_DIV5_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK } +#define NAND_USDHC_BUS_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV3_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV6_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL1_CLK } +#define VPU_BUS_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, VPU_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV8_CLK } +#define MEDIA_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV20_CLK, AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_DIV2_CLK } +#define MEDIA_APB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV20_CLK, AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_DIV6_CLK } +#define HDMI_APB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV20_CLK, AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_DIV6_CLK } +#define HDMI_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV20_CLK, AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_DIV2_CLK } +#define GPU_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, GPU_PLL_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define GPU_AHB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, GPU_PLL_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define NOC_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL2_DIV2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define NOC_IO_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL2_DIV2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define ML_AXI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, GPU_PLL_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define ML_AHB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, GPU_PLL_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } + +#define AHB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV6_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK } +#define IPG_CLK_MUX { OSC_24M_REF_CLK, } +#define AUDIO_AHB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL2_DIV6_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK } + +#define MEDIA_DISP2_CLK_MUX { OSC_24M_REF_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4 } + +#define DRAM_SEL_CFG_MUX { DRAM_PLL1_CLK, } +#define ARM_A53_CLK_ROOT_SEL_MUX { ARM_PLL_CLK, } + +#define DRAM_ALT_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL1_DIV8_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_DIV3_CLK } +#define DRAM_APB_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL2_CLK } +#define VPU_G1_CLK_MUX { OSC_24M_REF_CLK, VPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL1_DIV8_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK } +#define VPU_G2_CLK_MUX { OSC_24M_REF_CLK, VPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL1_DIV8_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK } +#define CAN1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL2_CLK } +#define CAN2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL2_CLK } +#define MEMREPAIR_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK } +#define PCIE_PHY_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL2_DIV2_CLK, EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, SYSTEM_PLL1_DIV2_CLK } +#define PCIE_AUX_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_DIV4_CLK } +#define I2C5_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK} +#define I2C6_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK} +#define SAI1_CLK_MUX { OSC_24M_REF_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV6_CLK, CLK_ROOT_SRC_UNDEFINED, EXT_CLK_1, EXT_CLK_2} +#define SAI2_CLK_MUX { OSC_24M_REF_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV6_CLK, CLK_ROOT_SRC_UNDEFINED, EXT_CLK_2, EXT_CLK_3} +#define SAI3_CLK_MUX { OSC_24M_REF_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV6_CLK, CLK_ROOT_SRC_UNDEFINED, EXT_CLK_3, EXT_CLK_4} + +#define SAI5_CLK_MUX { OSC_24M_REF_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV6_CLK, CLK_ROOT_SRC_UNDEFINED, EXT_CLK_2, EXT_CLK_3} +#define SAI6_CLK_MUX { OSC_24M_REF_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV6_CLK, CLK_ROOT_SRC_UNDEFINED, EXT_CLK_3, EXT_CLK_4} +#define ENET_QOS_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4 } +#define ENET_QOS_TIMER_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK } +#define ENET_REF_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4 } +#define ENET_TIMER_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK } +#define ENET_PHY_REF_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV2_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK } +#define NAND_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV2_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_DIV2_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, VIDEO_PLL_CLK } +#define QSPI_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL2_DIV3_CLK, SYSTEM_PLL2_DIV2_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV3_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV8_CLK } +#define USDHC1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV3_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV8_CLK } +#define USDHC2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV3_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV8_CLK } +#define I2C1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK } +#define I2C2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK } +#define I2C3_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK } +#define I2C4_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV6_CLK } +#define UART1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK } +#define UART2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK } +#define UART3_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK } +#define UART4_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK } + +#define GIC_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV2_CLK, EXT_CLK_4, AUDIO_PLL2_CLK } +#define ECSPI1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL2_CLK } +#define ECSPI2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL2_CLK } +#define PWM1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, SYSTEM_PLL1_DIV10_CLK, VIDEO_PLL_CLK } +#define PWM2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, SYSTEM_PLL1_DIV10_CLK, VIDEO_PLL_CLK } +#define PWM3_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, SYSTEM_PLL1_DIV10_CLK, VIDEO_PLL_CLK } +#define PWM4_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, SYSTEM_PLL1_DIV10_CLK, VIDEO_PLL_CLK } +#define GPT1_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_DIV20_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_1 } +#define GPT2_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_DIV20_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_2 } +#define GPT3_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_DIV20_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_3 } +#define GPT4_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_DIV20_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_1 } +#define GPT5_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_DIV20_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_2 } +#define GPT6_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_DIV20_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV10_CLK, AUDIO_PLL1_CLK, EXT_CLK_3 } +#define TRACE_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV6_CLK, SYSTEM_PLL1_DIV5_CLK, VPU_PLL_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3 } +#define WDOG_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV6_CLK, SYSTEM_PLL1_DIV5_CLK, VPU_PLL_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL2_DIV6_CLK } +#define WRCLK_CLK_MUX { OSC_24M_REF_CLK, } +#define IPP_DO_CLKO1_MUX { OSC_24M_REF_CLK, } +#define IPP_DO_CLKO2_MUX { OSC_24M_REF_CLK, } +#define HDMI_FDCC_TST_CLK_MUX { OSC_24M_REF_CLK, } +#define HDMI_27M_CLK_MUX { OSC_24M_REF_CLK, } +#define HDMI_REF_266M_CLK_MUX { OSC_24M_REF_CLK, } +#define USDHC3_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL1_DIV2_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_DIV2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_DIV3_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_DIV8_CLK } +#define MEDIA_CAM1_PIX_CLK_MUX { OSC_24M_REF_CLK, } +#define MEDIA_MIPI_PHY1_REF_CLK_MUX { OSC_24M_REF_CLK, } +#define MEDIA_DISP1_PIX_CLK_MUX { OSC_24M_REF_CLK, } +#define MEDIA_CAM2_PIX_CLK_MUX { OSC_24M_REF_CLK, } +#define MEDIA_LDB_CLK_MUX { OSC_24M_REF_CLK, } + +#define MEDIA_MIPI_TEST_BYTE_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL2_DIV20_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV10_CLK, SYSTEM_PLL1_DIV10_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_DIV4_CLK } +#define ECSPI3_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV5_CLK, SYSTEM_PLL1_DIV20_CLK, SYSTEM_PLL1_DIV5_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_DIV4_CLK, AUDIO_PLL2_CLK } +#define PDM_CLK_MUX { OSC_24M_REF_CLK, SYSTEM_PLL2_DIV10_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_CLK, SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK } +#define VPU_VC8000E_CLK_MUX { OSC_24M_REF_CLK, VPU_PLL_CLK, SYSTEM_PLL1_CLK, SYSTEM_PLL2_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL2_DIV8_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK } +#define SAI7_CLK_MUX { OSC_24M_REF_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_DIV6_CLK, CLK_ROOT_SRC_UNDEFINED, EXT_CLK_3, EXT_CLK_4 } + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_CCM_H */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_gpc.h b/arch/arm/src/mx8mp/hardware/mx8mp_gpc.h new file mode 100644 index 0000000000..035d2277f5 --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_gpc.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_gpc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reference: + * "i.MX 8M Plus Applications Processor Reference Manual", + * Document Number: IMX8MPRM Rev. 1, 06/2021. NXP + */ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_GPC_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_GPC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mx8mp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPC Register Addresses ***************************************************/ + +#define GPC_PU_PGC_SW_PUP_REQ (MX8M_GPC + 0x0D8) +#define GPC_PGC_CPU_M7_MAPPING (MX8M_GPC + 0x1D0) +#define GPC_PU_PWRHSK (MX8M_GPC + 0x190) + +/* GPC PU Register Offsets **************************************************/ + +#define AUDIOMIX_DOMAIN (1 << 7) +#define AUDIOMIX_SW_PUP_REQ (1 << 5) +#define GPC_AUDIOMIX_NOC_PWRDNREQN (1 << 15) +#define GPC_AUDIOMIX_PWRDNACKN (1 << 31) + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_GPC_H */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h b/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h new file mode 100644 index 0000000000..ac500591db --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use + * with Infineon's microcontrollers. This file can be freely distributed + * within development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS + * SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, + * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ****************************************************************************/ + +/* Reference: + * "i.MX 8M Plus Applications Processor Reference Manual", + * Document Number: IMX8MPRM Rev. 1, 06/2021. NXP + */ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_MEMORYMAP_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Peripheral Memory Map ****************************************************/ + +#define MX8M_IOMUXC 0x30330000u +#define MX8M_CCM_ANALOG 0x30360000u +#define MX8M_CCM 0x30380000u +#define MX8M_SRC 0x30390000u +#define MX8M_GPC 0x303A0000u +#define MX8M_RDC 0x303D0000u +#define MX8M_CSU 0x303E0000u + +#define MX8M_AUDIOMIX 0x30E20000u + +#define MX8M_GPT1 0x302D0000u +#define MX8M_GPT2 0x302E0000u +#define MX8M_GPT3 0x302F0000u +#define MX8M_GPT4 0x30700000u +#define MX8M_GPT5 0x306F0000u +#define MX8M_GPT6 0x306E0000u + +#define MX8M_PWM1 0x30660000u +#define MX8M_PWM2 0x30670000u +#define MX8M_PWM3 0x30680000u +#define MX8M_PWM4 0x30690000u + +#define MX8M_I2C1 0x30A20000u +#define MX8M_I2C2 0x30A30000u +#define MX8M_I2C3 0x30A40000u +#define MX8M_I2C4 0x30A50000u +#define MX8M_I2C5 0x30AD0000u +#define MX8M_I2C6 0x30AE0000u + +#define MX8M_UART1 0x30860000u +#define MX8M_UART2 0x30890000u +#define MX8M_UART3 0x30880000u +#define MX8M_UART4 0x30A60000u + +#define MX8M_ECSPI1 0x30820000u +#define MX8M_ECSPI2 0x30830000u +#define MX8M_ECSPI3 0x30840000u + +#define MX8M_GPIO1 0x30200000u +#define MX8M_GPIO2 0x30210000u +#define MX8M_GPIO3 0x30220000u +#define MX8M_GPIO4 0x30230000u +#define MX8M_GPIO5 0x30240000u + +#define MX8M_DDR 0x40000000u +#define MX8M_OCRAM 0x00900000u + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_MEMORYMAP_H */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h b/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h new file mode 100644 index 0000000000..0c8ceb6589 --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h @@ -0,0 +1,906 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reference: + * "i.MX 8M Plus Applications Processor Reference Manual", + * Document Number: IMX8MPRM Rev. 1, 06/2021. NXP + */ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_PINMUX_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IOMUXC Register Offsets **************************************************/ + +/* General Purpose Registers */ + +#define IMX_IOMUXC_GPR0_OFFSET 0x0000 +#define IMX_IOMUXC_GPR1_OFFSET 0x0004 +#define IMX_IOMUXC_GPR2_OFFSET 0x0008 +#define IMX_IOMUXC_GPR3_OFFSET 0x000c +#define IMX_IOMUXC_GPR4_OFFSET 0x0010 +#define IMX_IOMUXC_GPR5_OFFSET 0x0014 +#define IMX_IOMUXC_GPR6_OFFSET 0x0018 +#define IMX_IOMUXC_GPR7_OFFSET 0x001c +#define IMX_IOMUXC_GPR8_OFFSET 0x0020 +#define IMX_IOMUXC_GPR9_OFFSET 0x0024 +#define IMX_IOMUXC_GPR10_OFFSET 0x0028 +#define IMX_IOMUXC_GPR11_OFFSET 0x002c +#define IMX_IOMUXC_GPR12_OFFSET 0x0030 +#define IMX_IOMUXC_GPR13_OFFSET 0x0034 +#define IMX_IOMUXC_GPR14_OFFSET 0x0038 +#define IMX_IOMUXC_GPR15_OFFSET 0x003c +#define IMX_IOMUXC_GPR16_OFFSET 0x0040 +#define IMX_IOMUXC_GPR17_OFFSET 0x0044 +#define IMX_IOMUXC_GPR18_OFFSET 0x0048 +#define IMX_IOMUXC_GPR19_OFFSET 0x004c +#define IMX_IOMUXC_GPR20_OFFSET 0x0050 +#define IMX_IOMUXC_GPR21_OFFSET 0x0054 +#define IMX_IOMUXC_GPR22_OFFSET 0x0058 +#define IMX_IOMUXC_GPR23_OFFSET 0x005c +#define IMX_IOMUXC_GPR24_OFFSET 0x0060 + +/* The pin function ID is a tuple that contains in order: + * mux_register + * mux_mode + * input_register + * input_daisy + * config_register) + */ + +#define IOMUXC_BOOT_MODE0_SRC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330250 +#define IOMUXC_BOOT_MODE1_SRC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254 +#define IOMUXC_BOOT_MODE2_SRC_BOOT_MODE2 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258 +#define IOMUXC_BOOT_MODE3_SRC_BOOT_MODE3 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C + +#define IOMUXC_JTAG_MOD_JTAG_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260 +#define IOMUXC_JTAG_TDI_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264 +#define IOMUXC_JTAG_TMS_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268 +#define IOMUXC_JTAG_TCK_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C +#define IOMUXC_JTAG_TDO_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270 + +#define IOMUXC_RTC_XTALI_SNVS_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000 +#define IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000 +#define IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000 +#define IOMUXC_ONOFF_SNVS_ONOFF 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000 +#define IOMUXC_POR_B_SNVS_POR_B 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000 + +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330014, 0x0, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330014, 0x1, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_GPIO1_IO00_ISP_FL_TRIG_0 0x30330014, 0x3, 0x303305D4, 0x0, 0x30330274 +#define IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x30330014, 0x5, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330014, 0x6, 0x00000000, 0x0, 0x30330274 +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x30330018, 0x0, 0x00000000, 0x0, 0x30330278 +#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x30330018, 0x1, 0x00000000, 0x0, 0x30330278 +#define IOMUXC_GPIO1_IO01_ISP_SHUTTER_TRIG_0 0x30330018, 0x3, 0x303305DC, 0x0, 0x30330278 +#define IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x30330018, 0x5, 0x00000000, 0x0, 0x30330278 +#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x30330018, 0x6, 0x00000000, 0x0, 0x30330278 +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x3033001C, 0x0, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x3033001C, 0x1, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_GPIO1_IO02_ISP_FLASH_TRIG_0 0x3033001C, 0x3, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x3033001C, 0x5, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_GPIO1_IO02_SJC_DE_B 0x3033001C, 0x7, 0x00000000, 0x0, 0x3033027C +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330020, 0x0, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330020, 0x1, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_GPIO1_IO03_ISP_PRELIGHT_TRIG_0 0x30330020, 0x3, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330020, 0x5, 0x00000000, 0x0, 0x30330280 +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330024, 0x0, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330024, 0x1, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_GPIO1_IO04_ISP_SHUTTER_OPEN_0 0x30330024, 0x3, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330024, 0x5, 0x00000000, 0x0, 0x30330284 +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x30330028, 0x0, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_GPIO1_IO05_M7_NMI 0x30330028, 0x1, 0x00000000, 0x0, 0x30330288 +#define IOMUXC_GPIO1_IO05_ISP_FL_TRIG_1 0x30330028, 0x3, 0x303305D8, 0x0, 0x30330288 +#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x30330028, 0x5, 0x30330554, 0x0, 0x30330288 +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x3033002C, 0x0, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO06_ENET_QOS_MDC 0x3033002C, 0x1, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO06_ISP_SHUTTER_TRIG_1 0x3033002C, 0x3, 0x303305E0, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x3033002C, 0x5, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x3033002C, 0x6, 0x00000000, 0x0, 0x3033028C +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330030, 0x0, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO07_ENET_QOS_MDIO 0x30330030, 0x1, 0x30330590, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO07_ISP_FLASH_TRIG_1 0x30330030, 0x3, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330030, 0x5, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330030, 0x6, 0x00000000, 0x0, 0x30330290 +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330034, 0x0, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_IN 0x30330034, 0x1, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO08_PWM1_OUT 0x30330034, 0x2, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO08_ISP_PRELIGHT_TRIG_1 0x30330034, 0x3, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_AUX_IN 0x30330034, 0x4, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330034, 0x5, 0x00000000, 0x0, 0x30330294 +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x30330038, 0x0, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO09_ENET_QOS_1588_EVENT0_OUT 0x30330038, 0x1, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO09_PWM2_OUT 0x30330038, 0x2, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO09_ISP_SHUTTER_OPEN_1 0x30330038, 0x3, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x30330038, 0x4, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x30330038, 0x5, 0x00000000, 0x0, 0x30330298 +#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3033003C, 0x0, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO10_USB1_ID 0x3033003C, 0x1, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO10_PWM3_OUT 0x3033003C, 0x2, 0x00000000, 0x0, 0x3033029C +#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO11_USB2_ID 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO11_PWM2_OUT 0x30330040, 0x2, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330040, 0x4, 0x00000000, 0x0, 0x303302A0 +#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330040, 0x5, 0x30330554, 0x1, 0x303302A0 +#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330044, 0x0, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO12_USB1_PWR 0x30330044, 0x1, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330044, 0x5, 0x00000000, 0x0, 0x303302A4 +#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x30330048, 0x0, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO13_USB1_OC 0x30330048, 0x1, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x30330048, 0x5, 0x00000000, 0x0, 0x303302A8 +#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO14_USB2_PWR 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x3033004C, 0x4, 0x30330608, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x3033004C, 0x6, 0x00000000, 0x0, 0x303302AC +#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO15_USB2_OC 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330050, 0x4, 0x30330634, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330050, 0x5, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330050, 0x6, 0x00000000, 0x0, 0x303302B0 +#define IOMUXC_ENET_MDC_ENET_QOS_MDC 0x30330054, 0x0, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_ENET_MDC_AUDIOMIX_SAI6_TX_DATA0 0x30330054, 0x2, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330054, 0x5, 0x00000000, 0x0, 0x303302B4 +#define IOMUXC_ENET_MDC_USDHC3_STROBE 0x30330054, 0x6, 0x30330630, 0x0, 0x303302B4 +#define IOMUXC_ENET_MDIO_ENET_QOS_MDIO 0x30330058, 0x0, 0x30330590, 0x1, 0x303302B8 +#define IOMUXC_ENET_MDIO_AUDIOMIX_SAI6_TX_SYNC 0x30330058, 0x2, 0x30330528, 0x0, 0x303302B8 +#define IOMUXC_ENET_MDIO_AUDIOMIX_PDM_BIT_STREAM3 0x30330058, 0x3, 0x303304CC, 0x0, 0x303302B8 +#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x30330058, 0x5, 0x00000000, 0x0, 0x303302B8 +#define IOMUXC_ENET_MDIO_USDHC3_DATA5 0x30330058, 0x6, 0x30330624, 0x0, 0x303302B8 +#define IOMUXC_ENET_TD3_ENET_QOS_RGMII_TD3 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_ENET_TD3_AUDIOMIX_SAI6_TX_BCLK 0x3033005C, 0x2, 0x30330524, 0x0, 0x303302BC +#define IOMUXC_ENET_TD3_AUDIOMIX_PDM_BIT_STREAM2 0x3033005C, 0x3, 0x303304C8, 0x0, 0x303302BC +#define IOMUXC_ENET_TD3_GPIO1_IO18 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302BC +#define IOMUXC_ENET_TD3_USDHC3_DATA6 0x3033005C, 0x6, 0x30330628, 0x0, 0x303302BC +#define IOMUXC_ENET_TD2_ENET_QOS_RGMII_TD2 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_ENET_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_ENET_TD2_AUDIOMIX_SAI6_RX_DATA0 0x30330060, 0x2, 0x3033051C, 0x0, 0x303302C0 +#define IOMUXC_ENET_TD2_AUDIOMIX_PDM_BIT_STREAM1 0x30330060, 0x3, 0x303304C4, 0x0, 0x303302C0 +#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C0 +#define IOMUXC_ENET_TD2_USDHC3_DATA7 0x30330060, 0x6, 0x3033062C, 0x0, 0x303302C0 +#define IOMUXC_ENET_TD1_ENET_QOS_RGMII_TD1 0x30330064, 0x0, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_ENET_TD1_AUDIOMIX_SAI6_RX_SYNC 0x30330064, 0x2, 0x30330520, 0x0, 0x303302C4 +#define IOMUXC_ENET_TD1_AUDIOMIX_PDM_BIT_STREAM0 0x30330064, 0x3, 0x303304C0, 0x0, 0x303302C4 +#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330064, 0x5, 0x00000000, 0x0, 0x303302C4 +#define IOMUXC_ENET_TD1_USDHC3_CD_B 0x30330064, 0x6, 0x30330608, 0x1, 0x303302C4 +#define IOMUXC_ENET_TD0_ENET_QOS_RGMII_TD0 0x30330068, 0x0, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_ENET_TD0_AUDIOMIX_SAI6_RX_BCLK 0x30330068, 0x2, 0x30330518, 0x0, 0x303302C8 +#define IOMUXC_ENET_TD0_AUDIOMIX_PDM_CLK 0x30330068, 0x3, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_ENET_TD0_GPIO1_IO21 0x30330068, 0x5, 0x00000000, 0x0, 0x303302C8 +#define IOMUXC_ENET_TD0_USDHC3_WP 0x30330068, 0x6, 0x30330634, 0x1, 0x303302C8 +#define IOMUXC_ENET_TX_CTL_ENET_QOS_RGMII_TX_CTL 0x3033006C, 0x0, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_TX_CTL_AUDIOMIX_SAI6_MCLK 0x3033006C, 0x2, 0x30330514, 0x0, 0x303302CC +#define IOMUXC_ENET_TX_CTL_AUDIOMIX_SPDIF1_OUT 0x3033006C, 0x3, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302CC +#define IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x3033006C, 0x6, 0x30330610, 0x0, 0x303302CC +#define IOMUXC_ENET_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_TXC_ENET_QOS_TX_ER 0x30330070, 0x1, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_TXC_AUDIOMIX_SAI7_TX_DATA0 0x30330070, 0x2, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D0 +#define IOMUXC_ENET_TXC_USDHC3_DATA1 0x30330070, 0x6, 0x30330614, 0x0, 0x303302D0 +#define IOMUXC_ENET_RX_CTL_ENET_QOS_RGMII_RX_CTL 0x30330074, 0x0, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_RX_CTL_AUDIOMIX_SAI7_TX_SYNC 0x30330074, 0x2, 0x30330540, 0x0, 0x303302D4 +#define IOMUXC_ENET_RX_CTL_AUDIOMIX_PDM_BIT_STREAM3 0x30330074, 0x3, 0x303304CC, 0x1, 0x303302D4 +#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330074, 0x5, 0x00000000, 0x0, 0x303302D4 +#define IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x30330074, 0x6, 0x30330618, 0x0, 0x303302D4 +#define IOMUXC_ENET_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x30330078, 0x0, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_RXC_ENET_QOS_RX_ER 0x30330078, 0x1, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_RXC_AUDIOMIX_SAI7_TX_BCLK 0x30330078, 0x2, 0x3033053C, 0x0, 0x303302D8 +#define IOMUXC_ENET_RXC_AUDIOMIX_PDM_BIT_STREAM2 0x30330078, 0x3, 0x303304C8, 0x1, 0x303302D8 +#define IOMUXC_ENET_RXC_GPIO1_IO25 0x30330078, 0x5, 0x00000000, 0x0, 0x303302D8 +#define IOMUXC_ENET_RXC_USDHC3_DATA3 0x30330078, 0x6, 0x3033061C, 0x0, 0x303302D8 +#define IOMUXC_ENET_RD0_ENET_QOS_RGMII_RD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_RD0_AUDIOMIX_SAI7_RX_DATA0 0x3033007C, 0x2, 0x30330534, 0x0, 0x303302DC +#define IOMUXC_ENET_RD0_AUDIOMIX_PDM_BIT_STREAM1 0x3033007C, 0x3, 0x303304C4, 0x1, 0x303302DC +#define IOMUXC_ENET_RD0_GPIO1_IO26 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302DC +#define IOMUXC_ENET_RD0_USDHC3_DATA4 0x3033007C, 0x6, 0x30330620, 0x0, 0x303302DC +#define IOMUXC_ENET_RD1_ENET_QOS_RGMII_RD1 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_RD1_AUDIOMIX_SAI7_RX_SYNC 0x30330080, 0x2, 0x30330538, 0x0, 0x303302E0 +#define IOMUXC_ENET_RD1_AUDIOMIX_PDM_BIT_STREAM0 0x30330080, 0x3, 0x303304C0, 0x1, 0x303302E0 +#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_RD1_USDHC3_RESET_B 0x30330080, 0x6, 0x00000000, 0x0, 0x303302E0 +#define IOMUXC_ENET_RD2_ENET_QOS_RGMII_RD2 0x30330084, 0x0, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_RD2_AUDIOMIX_SAI7_RX_BCLK 0x30330084, 0x2, 0x30330530, 0x0, 0x303302E4 +#define IOMUXC_ENET_RD2_AUDIOMIX_PDM_CLK 0x30330084, 0x3, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330084, 0x5, 0x00000000, 0x0, 0x303302E4 +#define IOMUXC_ENET_RD2_USDHC3_CLK 0x30330084, 0x6, 0x30330604, 0x0, 0x303302E4 +#define IOMUXC_ENET_RD3_ENET_QOS_RGMII_RD3 0x30330088, 0x0, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_RD3_AUDIOMIX_SAI7_MCLK 0x30330088, 0x2, 0x3033052C, 0x0, 0x303302E8 +#define IOMUXC_ENET_RD3_AUDIOMIX_SPDIF1_IN 0x30330088, 0x3, 0x30330544, 0x0, 0x303302E8 +#define IOMUXC_ENET_RD3_GPIO1_IO29 0x30330088, 0x5, 0x00000000, 0x0, 0x303302E8 +#define IOMUXC_ENET_RD3_USDHC3_CMD 0x30330088, 0x6, 0x3033060C, 0x0, 0x303302E8 +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_SD1_CLK_ENET1_MDC 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_SD1_CLK_I2C5_SCL 0x3033008C, 0x3, 0x303305C4, 0x0, 0x303302EC +#define IOMUXC_SD1_CLK_UART1_TX 0x3033008C, 0x4, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_SD1_CLK_UART1_RX 0x3033008C, 0x4, 0x303305E8, 0x0, 0x303302EC +#define IOMUXC_SD1_CLK_GPIO2_IO00 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302EC +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_SD1_CMD_ENET1_MDIO 0x30330090, 0x1, 0x3033057C, 0x0, 0x303302F0 +#define IOMUXC_SD1_CMD_I2C5_SDA 0x30330090, 0x3, 0x303305C8, 0x0, 0x303302F0 +#define IOMUXC_SD1_CMD_UART1_RX 0x30330090, 0x4, 0x303305E8, 0x1, 0x303302F0 +#define IOMUXC_SD1_CMD_UART1_TX 0x30330090, 0x4, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_SD1_CMD_GPIO2_IO01 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F0 +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x30330094, 0x0, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x30330094, 0x1, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_SD1_DATA0_I2C6_SCL 0x30330094, 0x3, 0x303305CC, 0x0, 0x303302F4 +#define IOMUXC_SD1_DATA0_UART1_RTS_B 0x30330094, 0x4, 0x303305E4, 0x0, 0x303302F4 +#define IOMUXC_SD1_DATA0_UART1_CTS_B 0x30330094, 0x4, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x30330094, 0x5, 0x00000000, 0x0, 0x303302F4 +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x30330098, 0x0, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x30330098, 0x1, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_SD1_DATA1_I2C6_SDA 0x30330098, 0x3, 0x303305D0, 0x0, 0x303302F8 +#define IOMUXC_SD1_DATA1_UART1_CTS_B 0x30330098, 0x4, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_SD1_DATA1_UART1_RTS_B 0x30330098, 0x4, 0x303305E4, 0x1, 0x303302F8 +#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x30330098, 0x5, 0x00000000, 0x0, 0x303302F8 +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x3033009C, 0x0, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x3033009C, 0x1, 0x30330580, 0x0, 0x303302FC +#define IOMUXC_SD1_DATA2_I2C4_SCL 0x3033009C, 0x3, 0x303305BC, 0x0, 0x303302FC +#define IOMUXC_SD1_DATA2_UART2_TX 0x3033009C, 0x4, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_SD1_DATA2_UART2_RX 0x3033009C, 0x4, 0x303305F0, 0x0, 0x303302FC +#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x3033009C, 0x5, 0x00000000, 0x0, 0x303302FC +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x303300A0, 0x1, 0x30330584, 0x0, 0x30330300 +#define IOMUXC_SD1_DATA3_I2C4_SDA 0x303300A0, 0x3, 0x303305C0, 0x0, 0x30330300 +#define IOMUXC_SD1_DATA3_UART2_RX 0x303300A0, 0x4, 0x303305F0, 0x1, 0x30330300 +#define IOMUXC_SD1_DATA3_UART2_TX 0x303300A0, 0x4, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330300 +#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300A4, 0x0, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x303300A4, 0x1, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_DATA4_I2C1_SCL 0x303300A4, 0x3, 0x303305A4, 0x0, 0x30330304 +#define IOMUXC_SD1_DATA4_UART2_RTS_B 0x303300A4, 0x4, 0x303305EC, 0x0, 0x30330304 +#define IOMUXC_SD1_DATA4_UART2_CTS_B 0x303300A4, 0x4, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300A4, 0x5, 0x00000000, 0x0, 0x30330304 +#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_DATA5_ENET1_TX_ER 0x303300A8, 0x1, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_DATA5_I2C1_SDA 0x303300A8, 0x3, 0x303305A8, 0x0, 0x30330308 +#define IOMUXC_SD1_DATA5_UART2_CTS_B 0x303300A8, 0x4, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_DATA5_UART2_RTS_B 0x303300A8, 0x4, 0x303305EC, 0x1, 0x30330308 +#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330308 +#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300AC, 0x0, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x303300AC, 0x1, 0x30330588, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA6_I2C2_SCL 0x303300AC, 0x3, 0x303305AC, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA6_UART3_TX 0x303300AC, 0x4, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA6_UART3_RX 0x303300AC, 0x4, 0x303305F8, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300AC, 0x5, 0x00000000, 0x0, 0x3033030C +#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA7_ENET1_RX_ER 0x303300B0, 0x1, 0x3033058C, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA7_I2C2_SDA 0x303300B0, 0x3, 0x303305B0, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA7_UART3_RX 0x303300B0, 0x4, 0x303305F8, 0x1, 0x30330310 +#define IOMUXC_SD1_DATA7_UART3_TX 0x303300B0, 0x4, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330310 +#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300B4, 0x0, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x303300B4, 0x1, 0x30330578, 0x0, 0x30330314 +#define IOMUXC_SD1_RESET_B_I2C3_SCL 0x303300B4, 0x3, 0x303305B4, 0x0, 0x30330314 +#define IOMUXC_SD1_RESET_B_UART3_RTS_B 0x303300B4, 0x4, 0x303305F4, 0x0, 0x30330314 +#define IOMUXC_SD1_RESET_B_UART3_CTS_B 0x303300B4, 0x4, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300B4, 0x5, 0x00000000, 0x0, 0x30330314 +#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_STROBE_I2C3_SDA 0x303300B8, 0x3, 0x303305B8, 0x0, 0x30330318 +#define IOMUXC_SD1_STROBE_UART3_CTS_B 0x303300B8, 0x4, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD1_STROBE_UART3_RTS_B 0x303300B8, 0x4, 0x303305F4, 0x1, 0x30330318 +#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330318 +#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300BC, 0x0, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300BC, 0x5, 0x00000000, 0x0, 0x3033031C +#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD2_CLK_ECSPI2_SCLK 0x303300C0, 0x2, 0x30330568, 0x0, 0x30330320 +#define IOMUXC_SD2_CLK_UART4_RX 0x303300C0, 0x3, 0x30330600, 0x0, 0x30330320 +#define IOMUXC_SD2_CLK_UART4_TX 0x303300C0, 0x3, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330320 +#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300C4, 0x0, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD2_CMD_ECSPI2_MOSI 0x303300C4, 0x2, 0x30330570, 0x0, 0x30330324 +#define IOMUXC_SD2_CMD_UART4_TX 0x303300C4, 0x3, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD2_CMD_UART4_RX 0x303300C4, 0x3, 0x30330600, 0x1, 0x30330324 +#define IOMUXC_SD2_CMD_AUDIOMIX_PDM_CLK 0x303300C4, 0x4, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300C4, 0x5, 0x00000000, 0x0, 0x30330324 +#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD2_DATA0_I2C4_SDA 0x303300C8, 0x2, 0x303305C0, 0x1, 0x30330328 +#define IOMUXC_SD2_DATA0_UART2_RX 0x303300C8, 0x3, 0x303305F0, 0x2, 0x30330328 +#define IOMUXC_SD2_DATA0_UART2_TX 0x303300C8, 0x3, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD2_DATA0_AUDIOMIX_PDM_BIT_STREAM0 0x303300C8, 0x4, 0x303304C0, 0x2, 0x30330328 +#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330328 +#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300CC, 0x0, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD2_DATA1_I2C4_SCL 0x303300CC, 0x2, 0x303305BC, 0x1, 0x3033032C +#define IOMUXC_SD2_DATA1_UART2_TX 0x303300CC, 0x3, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD2_DATA1_UART2_RX 0x303300CC, 0x3, 0x303305F0, 0x3, 0x3033032C +#define IOMUXC_SD2_DATA1_AUDIOMIX_PDM_BIT_STREAM1 0x303300CC, 0x4, 0x303304C4, 0x2, 0x3033032C +#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300CC, 0x5, 0x00000000, 0x0, 0x3033032C +#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD2_DATA2_ECSPI2_SS0 0x303300D0, 0x2, 0x30330574, 0x0, 0x30330330 +#define IOMUXC_SD2_DATA2_AUDIOMIX_SPDIF1_OUT 0x303300D0, 0x3, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD2_DATA2_AUDIOMIX_PDM_BIT_STREAM2 0x303300D0, 0x4, 0x303304C8, 0x2, 0x30330330 +#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330330 +#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300D4, 0x0, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_DATA3_ECSPI2_MISO 0x303300D4, 0x2, 0x3033056C, 0x0, 0x30330334 +#define IOMUXC_SD2_DATA3_AUDIOMIX_SPDIF1_IN 0x303300D4, 0x3, 0x30330544, 0x1, 0x30330334 +#define IOMUXC_SD2_DATA3_AUDIOMIX_PDM_BIT_STREAM3 0x303300D4, 0x4, 0x303304CC, 0x2, 0x30330334 +#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300D4, 0x5, 0x00000000, 0x0, 0x30330334 +#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330338 +#define IOMUXC_SD2_WP_USDHC2_WP 0x303300DC, 0x0, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300DC, 0x5, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x303300DC, 0x6, 0x00000000, 0x0, 0x3033033C +#define IOMUXC_NAND_ALE_NAND_ALE 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_NAND_ALE_FLEXSPI_A_SCLK 0x303300E0, 0x1, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_NAND_ALE_AUDIOMIX_SAI3_TX_BCLK 0x303300E0, 0x2, 0x303304E8, 0x0, 0x30330340 +#define IOMUXC_NAND_ALE_ISP_FL_TRIG_0 0x303300E0, 0x3, 0x303305D4, 0x1, 0x30330340 +#define IOMUXC_NAND_ALE_UART3_RX 0x303300E0, 0x4, 0x303305F8, 0x2, 0x30330340 +#define IOMUXC_NAND_ALE_UART3_TX 0x303300E0, 0x4, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x303300E0, 0x6, 0x00000000, 0x0, 0x30330340 +#define IOMUXC_NAND_CE0_B_NAND_CE0_B 0x303300E4, 0x0, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_NAND_CE0_B_FLEXSPI_A_SS0_B 0x303300E4, 0x1, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_NAND_CE0_B_AUDIOMIX_SAI3_TX_DATA0 0x303300E4, 0x2, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_NAND_CE0_B_ISP_SHUTTER_TRIG_0 0x303300E4, 0x3, 0x303305DC, 0x1, 0x30330344 +#define IOMUXC_NAND_CE0_B_UART3_TX 0x303300E4, 0x4, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_NAND_CE0_B_UART3_RX 0x303300E4, 0x4, 0x303305F8, 0x3, 0x30330344 +#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300E4, 0x5, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x303300E4, 0x6, 0x00000000, 0x0, 0x30330344 +#define IOMUXC_NAND_CE1_B_NAND_CE1_B 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_NAND_CE1_B_FLEXSPI_A_SS1_B 0x303300E8, 0x1, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300E8, 0x2, 0x30330630, 0x1, 0x30330348 +#define IOMUXC_NAND_CE1_B_I2C4_SCL 0x303300E8, 0x4, 0x303305BC, 0x2, 0x30330348 +#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_NAND_CE1_B_CORESIGHT_TRACE00 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330348 +#define IOMUXC_NAND_CE2_B_NAND_CE2_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_NAND_CE2_B_FLEXSPI_B_SS0_B 0x303300EC, 0x1, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x303300EC, 0x2, 0x30330624, 0x1, 0x3033034C +#define IOMUXC_NAND_CE2_B_I2C4_SDA 0x303300EC, 0x4, 0x303305C0, 0x2, 0x3033034C +#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x303300EC, 0x5, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_NAND_CE2_B_CORESIGHT_TRACE01 0x303300EC, 0x6, 0x00000000, 0x0, 0x3033034C +#define IOMUXC_NAND_CE3_B_NAND_CE3_B 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_NAND_CE3_B_FLEXSPI_B_SS1_B 0x303300F0, 0x1, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x303300F0, 0x2, 0x30330628, 0x1, 0x30330350 +#define IOMUXC_NAND_CE3_B_I2C3_SDA 0x303300F0, 0x4, 0x303305B8, 0x1, 0x30330350 +#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_NAND_CE3_B_CORESIGHT_TRACE02 0x303300F0, 0x6, 0x00000000, 0x0, 0x30330350 +#define IOMUXC_NAND_CLE_NAND_CLE 0x303300F4, 0x0, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_NAND_CLE_FLEXSPI_B_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x303300F4, 0x2, 0x3033062C, 0x1, 0x30330354 +#define IOMUXC_NAND_CLE_UART4_RX 0x303300F4, 0x4, 0x30330600, 0x2, 0x30330354 +#define IOMUXC_NAND_CLE_UART4_TX 0x303300F4, 0x4, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_NAND_CLE_GPIO3_IO05 0x303300F4, 0x5, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_NAND_CLE_CORESIGHT_TRACE03 0x303300F4, 0x6, 0x00000000, 0x0, 0x30330354 +#define IOMUXC_NAND_DATA00_NAND_DATA00 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA00_FLEXSPI_A_DATA0 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA00_AUDIOMIX_SAI3_RX_DATA0 0x303300F8, 0x2, 0x303304E4, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA00_ISP_FLASH_TRIG_0 0x303300F8, 0x3, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA00_UART4_RX 0x303300F8, 0x4, 0x30330600, 0x3, 0x30330358 +#define IOMUXC_NAND_DATA00_UART4_TX 0x303300F8, 0x4, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA00_CORESIGHT_TRACE04 0x303300F8, 0x6, 0x00000000, 0x0, 0x30330358 +#define IOMUXC_NAND_DATA01_NAND_DATA01 0x303300FC, 0x0, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA01_FLEXSPI_A_DATA1 0x303300FC, 0x1, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA01_AUDIOMIX_SAI3_TX_SYNC 0x303300FC, 0x2, 0x303304EC, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA01_ISP_PRELIGHT_TRIG_0 0x303300FC, 0x3, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA01_UART4_TX 0x303300FC, 0x4, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA01_UART4_RX 0x303300FC, 0x4, 0x30330600, 0x4, 0x3033035C +#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x303300FC, 0x5, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA01_CORESIGHT_TRACE05 0x303300FC, 0x6, 0x00000000, 0x0, 0x3033035C +#define IOMUXC_NAND_DATA02_NAND_DATA02 0x30330100, 0x0, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_DATA02_FLEXSPI_A_DATA2 0x30330100, 0x1, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330100, 0x2, 0x30330608, 0x2, 0x30330360 +#define IOMUXC_NAND_DATA02_UART4_CTS_B 0x30330100, 0x3, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_DATA02_UART4_RTS_B 0x30330100, 0x3, 0x303305FC, 0x0, 0x30330360 +#define IOMUXC_NAND_DATA02_I2C4_SDA 0x30330100, 0x4, 0x303305C0, 0x3, 0x30330360 +#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330100, 0x5, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_DATA02_CORESIGHT_TRACE06 0x30330100, 0x6, 0x00000000, 0x0, 0x30330360 +#define IOMUXC_NAND_DATA03_NAND_DATA03 0x30330104, 0x0, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_DATA03_FLEXSPI_A_DATA3 0x30330104, 0x1, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330104, 0x2, 0x30330634, 0x2, 0x30330364 +#define IOMUXC_NAND_DATA03_UART4_RTS_B 0x30330104, 0x3, 0x303305FC, 0x1, 0x30330364 +#define IOMUXC_NAND_DATA03_UART4_CTS_B 0x30330104, 0x3, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_DATA03_ISP_FL_TRIG_1 0x30330104, 0x4, 0x303305D8, 0x1, 0x30330364 +#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330104, 0x5, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_DATA03_CORESIGHT_TRACE07 0x30330104, 0x6, 0x00000000, 0x0, 0x30330364 +#define IOMUXC_NAND_DATA04_NAND_DATA04 0x30330108, 0x0, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_DATA04_FLEXSPI_B_DATA0 0x30330108, 0x1, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x30330108, 0x2, 0x30330610, 0x1, 0x30330368 +#define IOMUXC_NAND_DATA04_FLEXSPI_A_DATA4 0x30330108, 0x3, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_DATA04_ISP_SHUTTER_TRIG_1 0x30330108, 0x4, 0x303305E0, 0x1, 0x30330368 +#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x30330108, 0x5, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_DATA04_CORESIGHT_TRACE08 0x30330108, 0x6, 0x00000000, 0x0, 0x30330368 +#define IOMUXC_NAND_DATA05_NAND_DATA05 0x3033010C, 0x0, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_DATA05_FLEXSPI_B_DATA1 0x3033010C, 0x1, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x3033010C, 0x2, 0x30330614, 0x1, 0x3033036C +#define IOMUXC_NAND_DATA05_FLEXSPI_A_DATA5 0x3033010C, 0x3, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_DATA05_ISP_FLASH_TRIG_1 0x3033010C, 0x4, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x3033010C, 0x5, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_DATA05_CORESIGHT_TRACE09 0x3033010C, 0x6, 0x00000000, 0x0, 0x3033036C +#define IOMUXC_NAND_DATA06_NAND_DATA06 0x30330110, 0x0, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA06_FLEXSPI_B_DATA2 0x30330110, 0x1, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330110, 0x2, 0x30330618, 0x1, 0x30330370 +#define IOMUXC_NAND_DATA06_FLEXSPI_A_DATA6 0x30330110, 0x3, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA06_ISP_PRELIGHT_TRIG_1 0x30330110, 0x4, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330110, 0x5, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x30330110, 0x6, 0x00000000, 0x0, 0x30330370 +#define IOMUXC_NAND_DATA07_NAND_DATA07 0x30330114, 0x0, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA07_FLEXSPI_B_DATA3 0x30330114, 0x1, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330114, 0x2, 0x3033061C, 0x1, 0x30330374 +#define IOMUXC_NAND_DATA07_FLEXSPI_A_DATA7 0x30330114, 0x3, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA07_ISP_SHUTTER_OPEN_1 0x30330114, 0x4, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330114, 0x5, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x30330114, 0x6, 0x00000000, 0x0, 0x30330374 +#define IOMUXC_NAND_DQS_NAND_DQS 0x30330118, 0x0, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DQS_FLEXSPI_A_DQS 0x30330118, 0x1, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DQS_AUDIOMIX_SAI3_MCLK 0x30330118, 0x2, 0x303304E0, 0x0, 0x30330378 +#define IOMUXC_NAND_DQS_ISP_SHUTTER_OPEN_0 0x30330118, 0x3, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DQS_I2C3_SCL 0x30330118, 0x4, 0x303305B4, 0x1, 0x30330378 +#define IOMUXC_NAND_DQS_GPIO3_IO14 0x30330118, 0x5, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x30330118, 0x6, 0x00000000, 0x0, 0x30330378 +#define IOMUXC_NAND_RE_B_NAND_RE_B 0x3033011C, 0x0, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_RE_B_FLEXSPI_B_DQS 0x3033011C, 0x1, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x3033011C, 0x2, 0x30330620, 0x1, 0x3033037C +#define IOMUXC_NAND_RE_B_UART4_TX 0x3033011C, 0x4, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_RE_B_UART4_RX 0x3033011C, 0x4, 0x30330600, 0x5, 0x3033037C +#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x3033011C, 0x5, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x3033011C, 0x6, 0x00000000, 0x0, 0x3033037C +#define IOMUXC_NAND_READY_B_NAND_READY_B 0x30330120, 0x0, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330120, 0x2, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_READY_B_I2C3_SCL 0x30330120, 0x4, 0x303305B4, 0x2, 0x30330380 +#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330120, 0x5, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x30330120, 0x6, 0x00000000, 0x0, 0x30330380 +#define IOMUXC_NAND_WE_B_NAND_WE_B 0x30330124, 0x0, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330124, 0x2, 0x30330604, 0x1, 0x30330384 +#define IOMUXC_NAND_WE_B_I2C3_SDA 0x30330124, 0x4, 0x303305B8, 0x2, 0x30330384 +#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330124, 0x5, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x30330124, 0x6, 0x00000000, 0x0, 0x30330384 +#define IOMUXC_NAND_WP_B_NAND_WP_B 0x30330128, 0x0, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x30330128, 0x2, 0x3033060C, 0x1, 0x30330388 +#define IOMUXC_NAND_WP_B_I2C4_SCL 0x30330128, 0x4, 0x303305BC, 0x3, 0x30330388 +#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x30330128, 0x5, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x30330128, 0x6, 0x00000000, 0x0, 0x30330388 +#define IOMUXC_SAI5_RXFS_AUDIOMIX_SAI5_RX_SYNC 0x3033012C, 0x0, 0x30330508, 0x0, 0x3033038C +#define IOMUXC_SAI5_RXFS_AUDIOMIX_SAI1_TX_DATA0 0x3033012C, 0x1, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_SAI5_RXFS_PWM4_OUT 0x3033012C, 0x2, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_SAI5_RXFS_I2C6_SCL 0x3033012C, 0x3, 0x303305CC, 0x1, 0x3033038C +#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x3033012C, 0x5, 0x00000000, 0x0, 0x3033038C +#define IOMUXC_SAI5_RXC_AUDIOMIX_SAI5_RX_BCLK 0x30330130, 0x0, 0x303304F4, 0x0, 0x30330390 +#define IOMUXC_SAI5_RXC_AUDIOMIX_SAI1_TX_DATA1 0x30330130, 0x1, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_SAI5_RXC_PWM3_OUT 0x30330130, 0x2, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_SAI5_RXC_I2C6_SDA 0x30330130, 0x3, 0x303305D0, 0x1, 0x30330390 +#define IOMUXC_SAI5_RXC_AUDIOMIX_PDM_CLK 0x30330130, 0x4, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330130, 0x5, 0x00000000, 0x0, 0x30330390 +#define IOMUXC_SAI5_RXD0_AUDIOMIX_SAI5_RX_DATA0 0x30330134, 0x0, 0x303304F8, 0x0, 0x30330394 +#define IOMUXC_SAI5_RXD0_AUDIOMIX_SAI1_TX_DATA2 0x30330134, 0x1, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_SAI5_RXD0_PWM2_OUT 0x30330134, 0x2, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_SAI5_RXD0_I2C5_SCL 0x30330134, 0x3, 0x303305C4, 0x1, 0x30330394 +#define IOMUXC_SAI5_RXD0_AUDIOMIX_PDM_BIT_STREAM0 0x30330134, 0x4, 0x303304C0, 0x3, 0x30330394 +#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330134, 0x5, 0x00000000, 0x0, 0x30330394 +#define IOMUXC_SAI5_RXD1_AUDIOMIX_SAI5_RX_DATA1 0x30330138, 0x0, 0x303304FC, 0x0, 0x30330398 +#define IOMUXC_SAI5_RXD1_AUDIOMIX_SAI1_TX_DATA3 0x30330138, 0x1, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_SAI5_RXD1_AUDIOMIX_SAI1_TX_SYNC 0x30330138, 0x2, 0x303304D8, 0x0, 0x30330398 +#define IOMUXC_SAI5_RXD1_AUDIOMIX_SAI5_TX_SYNC 0x30330138, 0x3, 0x30330510, 0x0, 0x30330398 +#define IOMUXC_SAI5_RXD1_AUDIOMIX_PDM_BIT_STREAM1 0x30330138, 0x4, 0x303304C4, 0x3, 0x30330398 +#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x30330138, 0x5, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_SAI5_RXD1_CAN1_TX 0x30330138, 0x6, 0x00000000, 0x0, 0x30330398 +#define IOMUXC_SAI5_RXD2_AUDIOMIX_SAI5_RX_DATA2 0x3033013C, 0x0, 0x30330500, 0x0, 0x3033039C +#define IOMUXC_SAI5_RXD2_AUDIOMIX_SAI1_TX_DATA4 0x3033013C, 0x1, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_SAI5_RXD2_AUDIOMIX_SAI1_TX_SYNC 0x3033013C, 0x2, 0x303304D8, 0x1, 0x3033039C +#define IOMUXC_SAI5_RXD2_AUDIOMIX_SAI5_TX_BCLK 0x3033013C, 0x3, 0x3033050C, 0x0, 0x3033039C +#define IOMUXC_SAI5_RXD2_AUDIOMIX_PDM_BIT_STREAM2 0x3033013C, 0x4, 0x303304C8, 0x3, 0x3033039C +#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x3033013C, 0x5, 0x00000000, 0x0, 0x3033039C +#define IOMUXC_SAI5_RXD2_CAN1_RX 0x3033013C, 0x6, 0x3033054C, 0x0, 0x3033039C +#define IOMUXC_SAI5_RXD3_AUDIOMIX_SAI5_RX_DATA3 0x30330140, 0x0, 0x30330504, 0x0, 0x303303A0 +#define IOMUXC_SAI5_RXD3_AUDIOMIX_SAI1_TX_DATA5 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_SAI5_RXD3_AUDIOMIX_SAI1_TX_SYNC 0x30330140, 0x2, 0x303304D8, 0x2, 0x303303A0 +#define IOMUXC_SAI5_RXD3_AUDIOMIX_SAI5_TX_DATA0 0x30330140, 0x3, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_SAI5_RXD3_AUDIOMIX_PDM_BIT_STREAM3 0x30330140, 0x4, 0x303304CC, 0x3, 0x303303A0 +#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_SAI5_RXD3_CAN2_TX 0x30330140, 0x6, 0x00000000, 0x0, 0x303303A0 +#define IOMUXC_SAI5_MCLK_AUDIOMIX_SAI5_MCLK 0x30330144, 0x0, 0x303304F0, 0x0, 0x303303A4 +#define IOMUXC_SAI5_MCLK_AUDIOMIX_SAI1_TX_BCLK 0x30330144, 0x1, 0x303304D4, 0x0, 0x303303A4 +#define IOMUXC_SAI5_MCLK_PWM1_OUT 0x30330144, 0x2, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_MCLK_I2C5_SDA 0x30330144, 0x3, 0x303305C8, 0x1, 0x303303A4 +#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330144, 0x5, 0x00000000, 0x0, 0x303303A4 +#define IOMUXC_SAI5_MCLK_CAN2_RX 0x30330144, 0x6, 0x30330550, 0x0, 0x303303A4 +#define IOMUXC_SAI1_RXFS_AUDIOMIX_SAI1_RX_SYNC 0x30330148, 0x0, 0x303304D0, 0x0, 0x303303A8 +#define IOMUXC_SAI1_RXFS_ENET1_1588_EVENT0_IN 0x30330148, 0x4, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x30330148, 0x5, 0x00000000, 0x0, 0x303303A8 +#define IOMUXC_SAI1_RXC_AUDIOMIX_SAI1_RX_BCLK 0x3033014C, 0x0, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI1_RXC_AUDIOMIX_PDM_CLK 0x3033014C, 0x3, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI1_RXC_ENET1_1588_EVENT0_OUT 0x3033014C, 0x4, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303AC +#define IOMUXC_SAI1_RXD0_AUDIOMIX_SAI1_RX_DATA0 0x30330150, 0x0, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI1_RXD0_AUDIOMIX_SAI1_TX_DATA1 0x30330150, 0x2, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI1_RXD0_AUDIOMIX_PDM_BIT_STREAM0 0x30330150, 0x3, 0x303304C0, 0x4, 0x303303B0 +#define IOMUXC_SAI1_RXD0_ENET1_1588_EVENT1_IN 0x30330150, 0x4, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B0 +#define IOMUXC_SAI1_RXD1_AUDIOMIX_SAI1_RX_DATA1 0x30330154, 0x0, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI1_RXD1_AUDIOMIX_PDM_BIT_STREAM1 0x30330154, 0x3, 0x303304C4, 0x4, 0x303303B4 +#define IOMUXC_SAI1_RXD1_ENET1_1588_EVENT1_OUT 0x30330154, 0x4, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330154, 0x5, 0x00000000, 0x0, 0x303303B4 +#define IOMUXC_SAI1_RXD2_AUDIOMIX_SAI1_RX_DATA2 0x30330158, 0x0, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI1_RXD2_AUDIOMIX_PDM_BIT_STREAM2 0x30330158, 0x3, 0x303304C8, 0x4, 0x303303B8 +#define IOMUXC_SAI1_RXD2_ENET1_MDC 0x30330158, 0x4, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x30330158, 0x5, 0x00000000, 0x0, 0x303303B8 +#define IOMUXC_SAI1_RXD3_AUDIOMIX_SAI1_RX_DATA3 0x3033015C, 0x0, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI1_RXD3_AUDIOMIX_PDM_BIT_STREAM3 0x3033015C, 0x3, 0x303304CC, 0x4, 0x303303BC +#define IOMUXC_SAI1_RXD3_ENET1_MDIO 0x3033015C, 0x4, 0x3033057C, 0x1, 0x303303BC +#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303BC +#define IOMUXC_SAI1_RXD4_AUDIOMIX_SAI1_RX_DATA4 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXD4_AUDIOMIX_SAI6_TX_BCLK 0x30330160, 0x1, 0x30330524, 0x1, 0x303303C0 +#define IOMUXC_SAI1_RXD4_AUDIOMIX_SAI6_RX_BCLK 0x30330160, 0x2, 0x30330518, 0x1, 0x303303C0 +#define IOMUXC_SAI1_RXD4_ENET1_RGMII_RD0 0x30330160, 0x4, 0x30330580, 0x1, 0x303303C0 +#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C0 +#define IOMUXC_SAI1_RXD5_AUDIOMIX_SAI1_RX_DATA5 0x30330164, 0x0, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXD5_AUDIOMIX_SAI6_TX_DATA0 0x30330164, 0x1, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXD5_AUDIOMIX_SAI6_RX_DATA0 0x30330164, 0x2, 0x3033051C, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXD5_AUDIOMIX_SAI1_RX_SYNC 0x30330164, 0x3, 0x303304D0, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXD5_ENET1_RGMII_RD1 0x30330164, 0x4, 0x30330584, 0x1, 0x303303C4 +#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330164, 0x5, 0x00000000, 0x0, 0x303303C4 +#define IOMUXC_SAI1_RXD6_AUDIOMIX_SAI1_RX_DATA6 0x30330168, 0x0, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD6_AUDIOMIX_SAI6_TX_SYNC 0x30330168, 0x1, 0x30330528, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXD6_AUDIOMIX_SAI6_RX_SYNC 0x30330168, 0x2, 0x30330520, 0x1, 0x303303C8 +#define IOMUXC_SAI1_RXD6_ENET1_RGMII_RD2 0x30330168, 0x4, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x30330168, 0x5, 0x00000000, 0x0, 0x303303C8 +#define IOMUXC_SAI1_RXD7_AUDIOMIX_SAI1_RX_DATA7 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD7_AUDIOMIX_SAI6_MCLK 0x3033016C, 0x1, 0x30330514, 0x1, 0x303303CC +#define IOMUXC_SAI1_RXD7_AUDIOMIX_SAI1_TX_SYNC 0x3033016C, 0x2, 0x303304D8, 0x3, 0x303303CC +#define IOMUXC_SAI1_RXD7_AUDIOMIX_SAI1_TX_DATA4 0x3033016C, 0x3, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD7_ENET1_RGMII_RD3 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303CC +#define IOMUXC_SAI1_TXFS_AUDIOMIX_SAI1_TX_SYNC 0x30330170, 0x0, 0x303304D8, 0x4, 0x303303D0 +#define IOMUXC_SAI1_TXFS_ENET1_RGMII_RX_CTL 0x30330170, 0x4, 0x30330588, 0x1, 0x303303D0 +#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D0 +#define IOMUXC_SAI1_TXC_AUDIOMIX_SAI1_TX_BCLK 0x30330174, 0x0, 0x303304D4, 0x1, 0x303303D4 +#define IOMUXC_SAI1_TXC_ENET1_RGMII_RXC 0x30330174, 0x4, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330174, 0x5, 0x00000000, 0x0, 0x303303D4 +#define IOMUXC_SAI1_TXD0_AUDIOMIX_SAI1_TX_DATA0 0x30330178, 0x0, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_TXD0_ENET1_RGMII_TD0 0x30330178, 0x4, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x30330178, 0x5, 0x00000000, 0x0, 0x303303D8 +#define IOMUXC_SAI1_TXD1_AUDIOMIX_SAI1_TX_DATA1 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_TXD1_ENET1_RGMII_TD1 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303DC +#define IOMUXC_SAI1_TXD2_AUDIOMIX_SAI1_TX_DATA2 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_TXD2_ENET1_RGMII_TD2 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E0 +#define IOMUXC_SAI1_TXD3_AUDIOMIX_SAI1_TX_DATA3 0x30330184, 0x0, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_TXD3_ENET1_RGMII_TD3 0x30330184, 0x4, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330184, 0x5, 0x00000000, 0x0, 0x303303E4 +#define IOMUXC_SAI1_TXD4_AUDIOMIX_SAI1_TX_DATA4 0x30330188, 0x0, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXD4_AUDIOMIX_SAI6_RX_BCLK 0x30330188, 0x1, 0x30330518, 0x2, 0x303303E8 +#define IOMUXC_SAI1_TXD4_AUDIOMIX_SAI6_TX_BCLK 0x30330188, 0x2, 0x30330524, 0x2, 0x303303E8 +#define IOMUXC_SAI1_TXD4_ENET1_RGMII_TX_CTL 0x30330188, 0x4, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x30330188, 0x5, 0x00000000, 0x0, 0x303303E8 +#define IOMUXC_SAI1_TXD5_AUDIOMIX_SAI1_TX_DATA5 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXD5_AUDIOMIX_SAI6_RX_DATA0 0x3033018C, 0x1, 0x3033051C, 0x2, 0x303303EC +#define IOMUXC_SAI1_TXD5_AUDIOMIX_SAI6_TX_DATA0 0x3033018C, 0x2, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXD5_ENET1_RGMII_TXC 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303EC +#define IOMUXC_SAI1_TXD6_AUDIOMIX_SAI1_TX_DATA6 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD6_AUDIOMIX_SAI6_RX_SYNC 0x30330190, 0x1, 0x30330520, 0x2, 0x303303F0 +#define IOMUXC_SAI1_TXD6_AUDIOMIX_SAI6_TX_SYNC 0x30330190, 0x2, 0x30330528, 0x2, 0x303303F0 +#define IOMUXC_SAI1_TXD6_ENET1_RX_ER 0x30330190, 0x4, 0x3033058C, 0x1, 0x303303F0 +#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F0 +#define IOMUXC_SAI1_TXD7_AUDIOMIX_SAI1_TX_DATA7 0x30330194, 0x0, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD7_AUDIOMIX_SAI6_MCLK 0x30330194, 0x1, 0x30330514, 0x2, 0x303303F4 +#define IOMUXC_SAI1_TXD7_AUDIOMIX_PDM_CLK 0x30330194, 0x3, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD7_ENET1_TX_ER 0x30330194, 0x4, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x30330194, 0x5, 0x00000000, 0x0, 0x303303F4 +#define IOMUXC_SAI1_MCLK_AUDIOMIX_SAI1_MCLK 0x30330198, 0x0, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI1_MCLK_AUDIOMIX_SAI1_TX_BCLK 0x30330198, 0x2, 0x303304D4, 0x2, 0x303303F8 +#define IOMUXC_SAI1_MCLK_ENET1_TX_CLK 0x30330198, 0x4, 0x30330578, 0x1, 0x303303F8 +#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x30330198, 0x5, 0x00000000, 0x0, 0x303303F8 +#define IOMUXC_SAI2_RXFS_AUDIOMIX_SAI2_RX_SYNC 0x3033019C, 0x0, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI2_RXFS_AUDIOMIX_SAI5_TX_SYNC 0x3033019C, 0x1, 0x30330510, 0x2, 0x303303FC +#define IOMUXC_SAI2_RXFS_AUDIOMIX_SAI5_TX_DATA1 0x3033019C, 0x2, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI2_RXFS_AUDIOMIX_SAI2_RX_DATA1 0x3033019C, 0x3, 0x303304DC, 0x0, 0x303303FC +#define IOMUXC_SAI2_RXFS_UART1_TX 0x3033019C, 0x4, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI2_RXFS_UART1_RX 0x3033019C, 0x4, 0x303305E8, 0x2, 0x303303FC +#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x3033019C, 0x5, 0x00000000, 0x0, 0x303303FC +#define IOMUXC_SAI2_RXFS_AUDIOMIX_PDM_BIT_STREAM2 0x3033019C, 0x6, 0x303304C8, 0x5, 0x303303FC +#define IOMUXC_SAI2_RXC_AUDIOMIX_SAI2_RX_BCLK 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI2_RXC_AUDIOMIX_SAI5_TX_BCLK 0x303301A0, 0x1, 0x3033050C, 0x2, 0x30330400 +#define IOMUXC_SAI2_RXC_CAN1_TX 0x303301A0, 0x3, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI2_RXC_UART1_RX 0x303301A0, 0x4, 0x303305E8, 0x3, 0x30330400 +#define IOMUXC_SAI2_RXC_UART1_TX 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330400 +#define IOMUXC_SAI2_RXC_AUDIOMIX_PDM_BIT_STREAM1 0x303301A0, 0x6, 0x303304C4, 0x5, 0x30330400 +#define IOMUXC_SAI2_RXD0_AUDIOMIX_SAI2_RX_DATA0 0x303301A4, 0x0, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI2_RXD0_AUDIOMIX_SAI5_TX_DATA0 0x303301A4, 0x1, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI2_RXD0_ENET_QOS_1588_EVENT2_OUT 0x303301A4, 0x2, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI2_RXD0_AUDIOMIX_SAI2_TX_DATA1 0x303301A4, 0x3, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301A4, 0x4, 0x303305E4, 0x2, 0x30330404 +#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301A4, 0x4, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301A4, 0x5, 0x00000000, 0x0, 0x30330404 +#define IOMUXC_SAI2_RXD0_AUDIOMIX_PDM_BIT_STREAM3 0x303301A4, 0x6, 0x303304CC, 0x5, 0x30330404 +#define IOMUXC_SAI2_TXFS_AUDIOMIX_SAI2_TX_SYNC 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI2_TXFS_AUDIOMIX_SAI5_TX_DATA1 0x303301A8, 0x1, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI2_TXFS_ENET_QOS_1588_EVENT3_OUT 0x303301A8, 0x2, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI2_TXFS_AUDIOMIX_SAI2_TX_DATA1 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301A8, 0x4, 0x303305E4, 0x3, 0x30330408 +#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330408 +#define IOMUXC_SAI2_TXFS_AUDIOMIX_PDM_BIT_STREAM2 0x303301A8, 0x6, 0x303304C8, 0x6, 0x30330408 +#define IOMUXC_SAI2_TXC_AUDIOMIX_SAI2_TX_BCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI2_TXC_AUDIOMIX_SAI5_TX_DATA2 0x303301AC, 0x1, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI2_TXC_CAN1_RX 0x303301AC, 0x3, 0x3033054C, 0x1, 0x3033040C +#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301AC, 0x5, 0x00000000, 0x0, 0x3033040C +#define IOMUXC_SAI2_TXC_AUDIOMIX_PDM_BIT_STREAM1 0x303301AC, 0x6, 0x303304C4, 0x6, 0x3033040C +#define IOMUXC_SAI2_TXD0_AUDIOMIX_SAI2_TX_DATA0 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI2_TXD0_AUDIOMIX_SAI5_TX_DATA3 0x303301B0, 0x1, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_IN 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI2_TXD0_CAN2_TX 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_AUX_IN 0x303301B0, 0x4, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330410 +#define IOMUXC_SAI2_MCLK_AUDIOMIX_SAI2_MCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_MCLK_AUDIOMIX_SAI5_MCLK 0x303301B4, 0x1, 0x303304F0, 0x2, 0x30330414 +#define IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_IN 0x303301B4, 0x2, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_MCLK_CAN2_RX 0x303301B4, 0x3, 0x30330550, 0x1, 0x30330414 +#define IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_AUX_IN 0x303301B4, 0x4, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301B4, 0x5, 0x00000000, 0x0, 0x30330414 +#define IOMUXC_SAI2_MCLK_AUDIOMIX_SAI3_MCLK 0x303301B4, 0x6, 0x303304E0, 0x1, 0x30330414 +#define IOMUXC_SAI3_RXFS_AUDIOMIX_SAI3_RX_SYNC 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI3_RXFS_AUDIOMIX_SAI2_RX_DATA1 0x303301B8, 0x1, 0x303304DC, 0x1, 0x30330418 +#define IOMUXC_SAI3_RXFS_AUDIOMIX_SAI5_RX_SYNC 0x303301B8, 0x2, 0x30330508, 0x2, 0x30330418 +#define IOMUXC_SAI3_RXFS_AUDIOMIX_SAI3_RX_DATA1 0x303301B8, 0x3, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI3_RXFS_AUDIOMIX_SPDIF1_IN 0x303301B8, 0x4, 0x30330544, 0x2, 0x30330418 +#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330418 +#define IOMUXC_SAI3_RXFS_AUDIOMIX_PDM_BIT_STREAM0 0x303301B8, 0x6, 0x303304C0, 0x5, 0x30330418 +#define IOMUXC_SAI3_RXC_AUDIOMIX_SAI3_RX_BCLK 0x303301BC, 0x0, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI3_RXC_AUDIOMIX_SAI2_RX_DATA2 0x303301BC, 0x1, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI3_RXC_AUDIOMIX_SAI5_RX_BCLK 0x303301BC, 0x2, 0x303304F4, 0x2, 0x3033041C +#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301BC, 0x3, 0x3033059C, 0x0, 0x3033041C +#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301BC, 0x4, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301BC, 0x4, 0x303305EC, 0x2, 0x3033041C +#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301BC, 0x5, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI3_RXC_AUDIOMIX_PDM_CLK 0x303301BC, 0x6, 0x00000000, 0x0, 0x3033041C +#define IOMUXC_SAI3_RXD_AUDIOMIX_SAI3_RX_DATA0 0x303301C0, 0x0, 0x303304E4, 0x1, 0x30330420 +#define IOMUXC_SAI3_RXD_AUDIOMIX_SAI2_RX_DATA3 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI3_RXD_AUDIOMIX_SAI5_RX_DATA0 0x303301C0, 0x2, 0x303304F8, 0x2, 0x30330420 +#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301C0, 0x4, 0x303305EC, 0x3, 0x30330420 +#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301C0, 0x4, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330420 +#define IOMUXC_SAI3_RXD_AUDIOMIX_PDM_BIT_STREAM1 0x303301C0, 0x6, 0x303304C4, 0x7, 0x30330420 +#define IOMUXC_SAI3_TXFS_AUDIOMIX_SAI3_TX_SYNC 0x303301C4, 0x0, 0x303304EC, 0x1, 0x30330424 +#define IOMUXC_SAI3_TXFS_AUDIOMIX_SAI2_TX_DATA1 0x303301C4, 0x1, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI3_TXFS_AUDIOMIX_SAI5_RX_DATA1 0x303301C4, 0x2, 0x303304FC, 0x2, 0x30330424 +#define IOMUXC_SAI3_TXFS_AUDIOMIX_SAI3_TX_DATA1 0x303301C4, 0x3, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301C4, 0x4, 0x303305F0, 0x4, 0x30330424 +#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301C4, 0x4, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301C4, 0x5, 0x00000000, 0x0, 0x30330424 +#define IOMUXC_SAI3_TXFS_AUDIOMIX_PDM_BIT_STREAM3 0x303301C4, 0x6, 0x303304CC, 0x6, 0x30330424 +#define IOMUXC_SAI3_TXC_AUDIOMIX_SAI3_TX_BCLK 0x303301C8, 0x0, 0x303304E8, 0x1, 0x30330428 +#define IOMUXC_SAI3_TXC_AUDIOMIX_SAI2_TX_DATA2 0x303301C8, 0x1, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI3_TXC_AUDIOMIX_SAI5_RX_DATA2 0x303301C8, 0x2, 0x30330500, 0x2, 0x30330428 +#define IOMUXC_SAI3_TXC_GPT1_CAPTURE1 0x303301C8, 0x3, 0x30330594, 0x0, 0x30330428 +#define IOMUXC_SAI3_TXC_UART2_TX 0x303301C8, 0x4, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI3_TXC_UART2_RX 0x303301C8, 0x4, 0x303305F0, 0x5, 0x30330428 +#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330428 +#define IOMUXC_SAI3_TXC_AUDIOMIX_PDM_BIT_STREAM2 0x303301C8, 0x6, 0x303304C8, 0x7, 0x30330428 +#define IOMUXC_SAI3_TXD_AUDIOMIX_SAI3_TX_DATA0 0x303301CC, 0x0, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI3_TXD_AUDIOMIX_SAI2_TX_DATA3 0x303301CC, 0x1, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI3_TXD_AUDIOMIX_SAI5_RX_DATA3 0x303301CC, 0x2, 0x30330504, 0x2, 0x3033042C +#define IOMUXC_SAI3_TXD_GPT1_CAPTURE2 0x303301CC, 0x3, 0x30330598, 0x0, 0x3033042C +#define IOMUXC_SAI3_TXD_AUDIOMIX_SPDIF1_EXT_CLK 0x303301CC, 0x4, 0x30330548, 0x0, 0x3033042C +#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301CC, 0x5, 0x00000000, 0x0, 0x3033042C +#define IOMUXC_SAI3_MCLK_AUDIOMIX_SAI3_MCLK 0x303301D0, 0x0, 0x303304E0, 0x2, 0x30330430 +#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_MCLK_AUDIOMIX_SAI5_MCLK 0x303301D0, 0x2, 0x303304F0, 0x3, 0x30330430 +#define IOMUXC_SAI3_MCLK_AUDIOMIX_SPDIF1_OUT 0x303301D0, 0x4, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330430 +#define IOMUXC_SAI3_MCLK_AUDIOMIX_SPDIF1_IN 0x303301D0, 0x6, 0x30330544, 0x3, 0x30330430 +#define IOMUXC_SPDIF_TX_AUDIOMIX_SPDIF1_OUT 0x303301D4, 0x0, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301D4, 0x1, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SPDIF_TX_I2C5_SCL 0x303301D4, 0x2, 0x303305C4, 0x2, 0x30330434 +#define IOMUXC_SPDIF_TX_GPT1_COMPARE1 0x303301D4, 0x3, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SPDIF_TX_CAN1_TX 0x303301D4, 0x4, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301D4, 0x5, 0x00000000, 0x0, 0x30330434 +#define IOMUXC_SPDIF_RX_AUDIOMIX_SPDIF1_IN 0x303301D8, 0x0, 0x30330544, 0x4, 0x30330438 +#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SPDIF_RX_I2C5_SDA 0x303301D8, 0x2, 0x303305C8, 0x2, 0x30330438 +#define IOMUXC_SPDIF_RX_GPT1_COMPARE2 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SPDIF_RX_CAN1_RX 0x303301D8, 0x4, 0x3033054C, 0x2, 0x30330438 +#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330438 +#define IOMUXC_SPDIF_EXT_CLK_AUDIOMIX_SPDIF1_EXT_CLK 0x303301DC, 0x0, 0x30330548, 0x1, 0x3033043C +#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301DC, 0x1, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SPDIF_EXT_CLK_GPT1_COMPARE3 0x303301DC, 0x3, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301DC, 0x5, 0x00000000, 0x0, 0x3033043C +#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301E0, 0x0, 0x30330558, 0x0, 0x30330440 +#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301E0, 0x1, 0x303305F8, 0x4, 0x30330440 +#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x303301E0, 0x2, 0x303305A4, 0x1, 0x30330440 +#define IOMUXC_ECSPI1_SCLK_AUDIOMIX_SAI7_RX_SYNC 0x303301E0, 0x3, 0x30330538, 0x1, 0x30330440 +#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330440 +#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301E4, 0x0, 0x30330560, 0x0, 0x30330444 +#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301E4, 0x1, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301E4, 0x1, 0x303305F8, 0x5, 0x30330444 +#define IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x303301E4, 0x2, 0x303305A8, 0x1, 0x30330444 +#define IOMUXC_ECSPI1_MOSI_AUDIOMIX_SAI7_RX_BCLK 0x303301E4, 0x3, 0x30330530, 0x1, 0x30330444 +#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301E4, 0x5, 0x00000000, 0x0, 0x30330444 +#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301E8, 0x0, 0x3033055C, 0x0, 0x30330448 +#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301E8, 0x1, 0x303305F4, 0x2, 0x30330448 +#define IOMUXC_ECSPI1_MISO_I2C2_SCL 0x303301E8, 0x2, 0x303305AC, 0x1, 0x30330448 +#define IOMUXC_ECSPI1_MISO_AUDIOMIX_SAI7_RX_DATA0 0x303301E8, 0x3, 0x30330534, 0x1, 0x30330448 +#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330448 +#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x303301EC, 0x0, 0x30330564, 0x0, 0x3033044C +#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x303301EC, 0x1, 0x303305F4, 0x3, 0x3033044C +#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x303301EC, 0x1, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_ECSPI1_SS0_I2C2_SDA 0x303301EC, 0x2, 0x303305B0, 0x1, 0x3033044C +#define IOMUXC_ECSPI1_SS0_AUDIOMIX_SAI7_TX_SYNC 0x303301EC, 0x3, 0x30330540, 0x1, 0x3033044C +#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x303301EC, 0x5, 0x00000000, 0x0, 0x3033044C +#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x303301F0, 0x0, 0x30330568, 0x1, 0x30330450 +#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x303301F0, 0x1, 0x30330600, 0x6, 0x30330450 +#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x303301F0, 0x2, 0x303305B4, 0x3, 0x30330450 +#define IOMUXC_ECSPI2_SCLK_AUDIOMIX_SAI7_TX_BCLK 0x303301F0, 0x3, 0x3033053C, 0x1, 0x30330450 +#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330450 +#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x303301F4, 0x0, 0x30330570, 0x1, 0x30330454 +#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x303301F4, 0x1, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x303301F4, 0x1, 0x30330600, 0x7, 0x30330454 +#define IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x303301F4, 0x2, 0x303305B8, 0x3, 0x30330454 +#define IOMUXC_ECSPI2_MOSI_AUDIOMIX_SAI7_TX_DATA0 0x303301F4, 0x3, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x303301F4, 0x5, 0x00000000, 0x0, 0x30330454 +#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x303301F8, 0x0, 0x3033056C, 0x1, 0x30330458 +#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x303301F8, 0x1, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x303301F8, 0x1, 0x303305FC, 0x2, 0x30330458 +#define IOMUXC_ECSPI2_MISO_I2C4_SCL 0x303301F8, 0x2, 0x303305BC, 0x4, 0x30330458 +#define IOMUXC_ECSPI2_MISO_AUDIOMIX_SAI7_MCLK 0x303301F8, 0x3, 0x3033052C, 0x1, 0x30330458 +#define IOMUXC_ECSPI2_MISO_CCM_CLKO1 0x303301F8, 0x4, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330458 +#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x303301FC, 0x0, 0x30330574, 0x1, 0x3033045C +#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x303301FC, 0x1, 0x303305FC, 0x3, 0x3033045C +#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x303301FC, 0x1, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI2_SS0_I2C4_SDA 0x303301FC, 0x2, 0x303305C0, 0x4, 0x3033045C +#define IOMUXC_ECSPI2_SS0_CCM_CLKO2 0x303301FC, 0x4, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x303301FC, 0x5, 0x00000000, 0x0, 0x3033045C +#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330200, 0x0, 0x303305A4, 0x2, 0x30330460 +#define IOMUXC_I2C1_SCL_ENET_QOS_MDC 0x30330200, 0x1, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x30330200, 0x3, 0x30330558, 0x1, 0x30330460 +#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330200, 0x5, 0x00000000, 0x0, 0x30330460 +#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330204, 0x0, 0x303305A8, 0x2, 0x30330464 +#define IOMUXC_I2C1_SDA_ENET_QOS_MDIO 0x30330204, 0x1, 0x30330590, 0x2, 0x30330464 +#define IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x30330204, 0x3, 0x30330560, 0x1, 0x30330464 +#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330204, 0x5, 0x00000000, 0x0, 0x30330464 +#define IOMUXC_I2C2_SCL_I2C2_SCL 0x30330208, 0x0, 0x303305AC, 0x2, 0x30330468 +#define IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_IN 0x30330208, 0x1, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x30330208, 0x2, 0x30330608, 0x3, 0x30330468 +#define IOMUXC_I2C2_SCL_ECSPI1_MISO 0x30330208, 0x3, 0x3033055C, 0x1, 0x30330468 +#define IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_AUX_IN 0x30330208, 0x4, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x30330208, 0x5, 0x00000000, 0x0, 0x30330468 +#define IOMUXC_I2C2_SDA_I2C2_SDA 0x3033020C, 0x0, 0x303305B0, 0x2, 0x3033046C +#define IOMUXC_I2C2_SDA_ENET_QOS_1588_EVENT1_OUT 0x3033020C, 0x1, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_I2C2_SDA_USDHC3_WP 0x3033020C, 0x2, 0x30330634, 0x3, 0x3033046C +#define IOMUXC_I2C2_SDA_ECSPI1_SS0 0x3033020C, 0x3, 0x30330564, 0x1, 0x3033046C +#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x3033020C, 0x5, 0x00000000, 0x0, 0x3033046C +#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330210, 0x0, 0x303305B4, 0x4, 0x30330470 +#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330210, 0x1, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330210, 0x2, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x30330210, 0x3, 0x30330568, 0x2, 0x30330470 +#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330210, 0x5, 0x00000000, 0x0, 0x30330470 +#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330214, 0x0, 0x303305B8, 0x4, 0x30330474 +#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330214, 0x1, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330214, 0x2, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x30330214, 0x3, 0x30330570, 0x2, 0x30330474 +#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330214, 0x5, 0x00000000, 0x0, 0x30330474 +#define IOMUXC_I2C4_SCL_I2C4_SCL 0x30330218, 0x0, 0x303305BC, 0x5, 0x30330478 +#define IOMUXC_I2C4_SCL_PWM2_OUT 0x30330218, 0x1, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C4_SCL_PCIE_CLKREQ_B 0x30330218, 0x2, 0x303305A0, 0x0, 0x30330478 +#define IOMUXC_I2C4_SCL_ECSPI2_MISO 0x30330218, 0x3, 0x3033056C, 0x2, 0x30330478 +#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x30330218, 0x5, 0x00000000, 0x0, 0x30330478 +#define IOMUXC_I2C4_SDA_I2C4_SDA 0x3033021C, 0x0, 0x303305C0, 0x5, 0x3033047C +#define IOMUXC_I2C4_SDA_PWM1_OUT 0x3033021C, 0x1, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_I2C4_SDA_ECSPI2_SS0 0x3033021C, 0x3, 0x30330574, 0x2, 0x3033047C +#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x3033021C, 0x5, 0x00000000, 0x0, 0x3033047C +#define IOMUXC_UART1_RXD_UART1_RX 0x30330220, 0x0, 0x303305E8, 0x4, 0x30330480 +#define IOMUXC_UART1_RXD_UART1_TX 0x30330220, 0x0, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330220, 0x1, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330220, 0x5, 0x00000000, 0x0, 0x30330480 +#define IOMUXC_UART1_TXD_UART1_TX 0x30330224, 0x0, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_UART1_TXD_UART1_RX 0x30330224, 0x0, 0x303305E8, 0x5, 0x30330484 +#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330224, 0x1, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330224, 0x5, 0x00000000, 0x0, 0x30330484 +#define IOMUXC_UART2_RXD_UART2_RX 0x30330228, 0x0, 0x303305F0, 0x6, 0x30330488 +#define IOMUXC_UART2_RXD_UART2_TX 0x30330228, 0x0, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x30330228, 0x1, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_UART2_RXD_GPT1_COMPARE3 0x30330228, 0x3, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_UART2_RXD_GPIO5_IO24 0x30330228, 0x5, 0x00000000, 0x0, 0x30330488 +#define IOMUXC_UART2_TXD_UART2_TX 0x3033022C, 0x0, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_UART2_TXD_UART2_RX 0x3033022C, 0x0, 0x303305F0, 0x7, 0x3033048C +#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x3033022C, 0x1, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_UART2_TXD_GPT1_COMPARE2 0x3033022C, 0x3, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_UART2_TXD_GPIO5_IO25 0x3033022C, 0x5, 0x00000000, 0x0, 0x3033048C +#define IOMUXC_UART3_RXD_UART3_RX 0x30330230, 0x0, 0x303305F8, 0x6, 0x30330490 +#define IOMUXC_UART3_RXD_UART3_TX 0x30330230, 0x0, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330230, 0x1, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330230, 0x1, 0x303305E4, 0x4, 0x30330490 +#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330230, 0x2, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x30330230, 0x3, 0x30330598, 0x1, 0x30330490 +#define IOMUXC_UART3_RXD_CAN2_TX 0x30330230, 0x4, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330230, 0x5, 0x00000000, 0x0, 0x30330490 +#define IOMUXC_UART3_TXD_UART3_TX 0x30330234, 0x0, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_UART3_TXD_UART3_RX 0x30330234, 0x0, 0x303305F8, 0x7, 0x30330494 +#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330234, 0x1, 0x303305E4, 0x5, 0x30330494 +#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330234, 0x1, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330234, 0x2, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_UART3_TXD_GPT1_CLK 0x30330234, 0x3, 0x3033059C, 0x1, 0x30330494 +#define IOMUXC_UART3_TXD_CAN2_RX 0x30330234, 0x4, 0x30330550, 0x2, 0x30330494 +#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330234, 0x5, 0x00000000, 0x0, 0x30330494 +#define IOMUXC_UART4_RXD_UART4_RX 0x30330238, 0x0, 0x30330600, 0x8, 0x30330498 +#define IOMUXC_UART4_RXD_UART4_TX 0x30330238, 0x0, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART4_RXD_UART2_CTS_B 0x30330238, 0x1, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART4_RXD_UART2_RTS_B 0x30330238, 0x1, 0x303305EC, 0x4, 0x30330498 +#define IOMUXC_UART4_RXD_PCIE_CLKREQ_B 0x30330238, 0x2, 0x303305A0, 0x1, 0x30330498 +#define IOMUXC_UART4_RXD_GPT1_COMPARE1 0x30330238, 0x3, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART4_RXD_I2C6_SCL 0x30330238, 0x4, 0x303305CC, 0x2, 0x30330498 +#define IOMUXC_UART4_RXD_GPIO5_IO28 0x30330238, 0x5, 0x00000000, 0x0, 0x30330498 +#define IOMUXC_UART4_TXD_UART4_TX 0x3033023C, 0x0, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART4_TXD_UART4_RX 0x3033023C, 0x0, 0x30330600, 0x9, 0x3033049C +#define IOMUXC_UART4_TXD_UART2_RTS_B 0x3033023C, 0x1, 0x303305EC, 0x5, 0x3033049C +#define IOMUXC_UART4_TXD_UART2_CTS_B 0x3033023C, 0x1, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x3033023C, 0x3, 0x30330594, 0x1, 0x3033049C +#define IOMUXC_UART4_TXD_I2C6_SDA 0x3033023C, 0x4, 0x303305D0, 0x2, 0x3033049C +#define IOMUXC_UART4_TXD_GPIO5_IO29 0x3033023C, 0x5, 0x00000000, 0x0, 0x3033049C +#define IOMUXC_HDMI_DDC_SCL_HDMIMIX_HDMI_SCL 0x30330240, 0x0, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_HDMI_DDC_SCL_I2C5_SCL 0x30330240, 0x3, 0x303305C4, 0x3, 0x303304A0 +#define IOMUXC_HDMI_DDC_SCL_CAN1_TX 0x30330240, 0x4, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_HDMI_DDC_SCL_GPIO3_IO26 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_HDMI_DDC_SCL_EARC_TEST_OUT0 0x30330240, 0x6, 0x00000000, 0x0, 0x303304A0 +#define IOMUXC_HDMI_DDC_SDA_HDMIMIX_HDMI_SDA 0x30330244, 0x0, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_HDMI_DDC_SDA_I2C5_SDA 0x30330244, 0x3, 0x303305C8, 0x3, 0x303304A4 +#define IOMUXC_HDMI_DDC_SDA_CAN1_RX 0x30330244, 0x4, 0x3033054C, 0x3, 0x303304A4 +#define IOMUXC_HDMI_DDC_SDA_GPIO3_IO27 0x30330244, 0x5, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_HDMI_DDC_SDA_EARC_TEST_OUT1 0x30330244, 0x6, 0x00000000, 0x0, 0x303304A4 +#define IOMUXC_HDMI_CEC_HDMIMIX_HDMI_CEC 0x30330248, 0x0, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_HDMI_CEC_I2C6_SCL 0x30330248, 0x3, 0x303305CC, 0x3, 0x303304A8 +#define IOMUXC_HDMI_CEC_CAN2_TX 0x30330248, 0x4, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_HDMI_CEC_GPIO3_IO28 0x30330248, 0x5, 0x00000000, 0x0, 0x303304A8 +#define IOMUXC_HDMI_HPD_HDMIMIX_HDMI_HPD 0x3033024C, 0x0, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_HDMI_HPD_AUDIOMIX_HDMI_HPD_O 0x3033024C, 0x1, 0x00000000, 0x0, 0x303304AC +#define IOMUXC_HDMI_HPD_I2C6_SDA 0x3033024C, 0x3, 0x303305D0, 0x3, 0x303304AC +#define IOMUXC_HDMI_HPD_CAN2_RX 0x3033024C, 0x4, 0x30330550, 0x3, 0x303304AC +#define IOMUXC_HDMI_HPD_GPIO3_IO29 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304AC + +/* FSEL - Slew Rate Field + * 0b0..Slow Slew Rate (SR=1) + * 0b1..Fast Slew Rate (SR=0) + */ +#define IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK (0x10U) +#define IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT (4U) +#define IOMUXC_SW_PAD_CTL_PAD_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK) + +/* PUE - Pull Up / Down Config. Field + * 0b0..Weak pull down + * 0b1..Weak pull up + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) + +/* PE - Pull Select Field + * 0b0..Pull Disable + * 0b1..Pull Enable + */ +#define IOMUXC_SW_PAD_CTL_PAD_PE_MASK (0x100U) +#define IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT (8U) +#define IOMUXC_SW_PAD_CTL_PAD_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PE_MASK) + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_PINMUX_H */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_rdc.h b/arch/arm/src/mx8mp/hardware/mx8mp_rdc.h new file mode 100644 index 0000000000..0dd673cb4a --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_rdc.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_rdc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reference: + * "i.MX 8M Plus Applications Processor Reference Manual", + * Document Number: IMX8MPRM Rev. 1, 06/2021. NXP + */ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_RDC_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_RDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mx8mp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RDC Register Addresses ***************************************************/ + +#define RDC_VIR (MX8M_RDC + 0) +#define RDC_STAT (MX8M_RDC + 0x024) +#define RDC_INTCTRL (MX8M_RDC + 0x024) +#define RDC_INTSTAT (MX8M_RDC + 0x02C) + +/* RDC Common Register Offsets **********************************************/ + +#define RDC_DID_MASK 0xf +#define RDC_DID (getreg32(RDC_STAT) & RDC_DID_MASK) + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_RDC_H */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_uart.h b/arch/arm/src/mx8mp/hardware/mx8mp_uart.h new file mode 100644 index 0000000000..098cf1df5b --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_uart.h @@ -0,0 +1,263 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reference: + * "i.MX 8M Plus Applications Processor Reference Manual", + * Document Number: IMX8MPRM Rev. 1, 06/2021. NXP + */ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_UART_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/mx8mp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UART Register Offsets ****************************************************/ +#define UART_RXD_OFFSET 0x0000 /* UART receiver register */ +#define UART_TXD_OFFSET 0x0040 /* UART receiver register */ +#define UART_UCR1_OFFSET 0x0080 /* UART control register 1 */ +#define UART_UCR2_OFFSET 0x0084 /* UART control register 2 */ +#define UART_UCR3_OFFSET 0x0088 /* UART control register 3 */ +#define UART_UCR4_OFFSET 0x008c /* UART control register 4 */ +#define UART_UFCR_OFFSET 0x0090 /* UART FIFO control register */ +#define UART_USR1_OFFSET 0x0094 /* UART status register 1 */ +#define UART_USR2_OFFSET 0x0098 /* UART status register 2 */ +#define UART_UESC_OFFSET 0x009c /* UART escape character register */ +#define UART_UTIM_OFFSET 0x00a0 /* UART escape timer register */ +#define UART_UBIR_OFFSET 0x00a4 /* UART BRM incremental register */ +#define UART_UBMR_OFFSET 0x00a8 /* UART BRM modulator register */ +#define UART_UBRC_OFFSET 0x00ac /* UART baud rate counter register */ +#define UART_ONEMS_OFFSET 0x00b0 /* UART One Millisecond Register */ +#define UART_UTS_OFFSET 0x00b4 /* UART test register */ +#define UART_UMCR_OFFSET 0x00b8 /* UART RS-485 Mode Control Register */ + +/* UART Register Bit Definitions ********************************************/ + +/* UART Receiver Register */ + +#define UART_RXD_DATA_SHIFT 0 /* Bits 0-7: Received Data */ +#define UART_RXD_DATA_MASK (0xff << UART_RXD_DATA_SHIFT) +#define UART_RXD_PRERR (1 << 10) /* Bit 10: Parity Error */ +#define UART_RXD_BRK (1 << 11) /* Bit 11: Break Detect */ +#define UART_RXD_FRMERR (1 << 12) /* Bit 12: Frame Error */ +#define UART_RXD_OVRRUN (1 << 13) /* Bit 13: Receiver Overrun */ +#define UART_RXD_ERR (1 << 14) /* Bit 14: Error Detect */ +#define UART_RXD_CHARRDY (1 << 15) /* Bit 15: Character Ready */ + +/* UART Transmitter Register */ + +#define UART_TXDATA_SHIFT 0 /* Bits 0-7: Transmit Data */ +#define UART_TXDATA_MASK (0xff << UART_UCR4_TXDATA_SHIFT) + +/* UART Control Register 1 */ + +#define UART_UCR1_UARTEN (1 << 0) /* Bit 0: Enable/disable UART */ +#define UART_UCR1_DOZE (1 << 1) /* Bit 1: UART Doze enable */ +#define UART_UCR1_ATDMAEN (1 << 2) /* Bit 2: Aging DMA Timer Enable */ +#define UART_UCR1_TXDMAEN (1 << 3) /* Bit 3: Transmitter Ready DMA Enable */ +#define UART_UCR1_SNDBRK (1 << 4) /* Bit 4: Send BREAK */ +#define UART_UCR1_RTSDEN (1 << 5) /* Bit 5: RTS Delta interrupt enable */ +#define UART_UCR1_TXEMPTYEN (1 << 6) /* Bit 6: Transmitter empty interrupt enable */ +#define UART_UCR1_IREN (1 << 7) /* Bit 7: Infrared Interface enable */ +#define UART_UCR1_RDMAEN (1 << 8) /* Bit 8: Receive ready DMA enable */ +#define UART_UCR1_RRDYEN (1 << 9) /* Bit 9: Receiver ready interrupt enable */ +#define UART_UCR1_ICD_SHIFT 10 /* Bit 10-11: Idle condition detect */ +#define UART_UCR1_ICD_MASK (3 << UART_UCR1_ICD_SHIFT) +# define UART_UCR1_ICD_4FRMS (0 << UART_UCR1_ICD_SHIFT) /* Idle for more than 4 frames */ +# define UART_UCR1_ICD_8FRMS (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */ +# define UART_UCR1_ICD_16FRMS (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */ +# define UART_UCR1_ICD_32FRMS (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */ + +#define UART_UCR1_IDEN (1 << 12) /* Bit 12: Idle condition detected interrupt enable */ +#define UART_UCR1_TRDYEN (1 << 13) /* Bit 13: Transmitter ready interrupt enable */ +#define UART_UCR1_ADBR (1 << 14) /* Bit 14: Automatic detection of baud rate */ +#define UART_UCR1_ADEN (1 << 15) /* Bit 15: Automatic baud rate detection interrupt enable */ + +/* UART Control Register 2 */ + +#define UART_UCR2_SRST (1 << 0) /* Bit 0: Software reset */ +#define UART_UCR2_RXEN (1 << 1) /* Bit 1: Receiver enable */ +#define UART_UCR2_TXEN (1 << 2) /* Bit 2: Transmitter enable */ +#define UART_UCR2_ATEN (1 << 3) /* Bit 2: Aging Timer Enable */ +#define UART_UCR2_RTSEN (1 << 4) /* Bit 4: RTS interrupt enable/disable */ +#define UART_UCR2_WS (1 << 5) /* Bit 5: Word size */ +#define UART_UCR2_STPB (1 << 6) /* Bit 6: Controls number of stop bits */ +#define UART_UCR2_PROE (1 << 7) /* Bit 7: Parity Odd/Even */ +#define UART_UCR2_PREN (1 << 8) /* Bit 8: Parity enable */ +#define UART_UCR2_RTEC_SHIFT 9 /* Bit 9-10: Request to send edge control */ +#define UART_UCR2_RTEC_MASK (3 << UART_UCR2_RTEC_SHIFT) +# define UART_UCR2_RTEC_RISE (0 << UART_UCR2_RTEC_SHIFT) /* Interrupt on rising edge */ +# define UART_UCR2_RTEC_FALL (1 << UART_UCR2_RTEC_SHIFT) /* Interrupt on falling edge */ +# define UART_UCR2_RTEC_BOTH (2 << UART_UCR2_RTEC_SHIFT) /* Interrupt on any edge */ + +#define UART_UCR2_ESCEN (1 << 11) /* Bit 11: Escape enable */ +#define UART_UCR2_CTS (1 << 12) /* Bit 12: Clear To Send pin */ +#define UART_UCR2_CTSC (1 << 13) /* Bit 13: CTS Pin control */ +#define UART_UCR2_IRTS (1 << 14) /* Bit 14: Ignore RTS Pin */ +#define UART_UCR2_ESCI (1 << 15) /* Bit 15: Escape Sequence Interrupt Enable */ + +/* UART Control Register 3 */ + +#define UART_UCR3_ACIEN (1 << 0) /* Bit 0: Autobaud Counter Interrupt Enable */ +#define UART_UCR3_INVT (1 << 1) /* Bit 1: Inverted output */ +#define UART_UCR3_RXDMUXSEL (1 << 2) /* Bit 2: RXD muxed input selected */ +#define UART_UCR3_DTRDEN (1 << 3) /* Bit 3: Data Terminal Ready delta enable */ +#define UART_UCR3_AWAKEN (1 << 4) /* Bit 4: Asynchronous wake interrupt enable */ +#define UART_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asynchronous IR Wake interrupt enable */ +#define UART_UCR3_RXDSEN (1 << 6) /* Bit 6: Receive status interrupt enable */ +#define UART_UCR3_ADNIMP (1 << 7) /* Bit 7: Autobaud Detection Not Improved */ +#define UART_UCR3_RI (1 << 8) /* Bit 8: Ring Indicator */ +#define UART_UCR3_DCD (1 << 9) /* Bit 9: Data Carrier Detect */ +#define UART_UCR3_DSR (1 << 10) /* Bit 10: Data Set Ready */ +#define UART_UCR3_FRAERREN (1 << 11) /* Bit 11: Frame error interrupt enable */ +#define UART_UCR3_PARERREN (1 << 12) /* Bit 12: Parity error interrupt enable */ +#define UART_UCR3_DTREN (1 << 13) /* Bit 13: Data Terminal Ready interrupt enable */ +#define UART_UCR3_DPEC_SHIFT (14) /* Bits 14-15: DTR/DSR interrupt edge control */ +#define UART_UCR3_DPEC_MASK (3 << UART_UCR3_DPEC_SHIFT) +# define UART1_DPEC_RISING (0 << UART_UCR3_DPEC_SHIFT) /* Interrupt on rising edge */ +# define UART1_DPEC_FALLING (1 << UART_UCR3_DPEC_SHIFT) /* Interrupt on falling edge */ +# define UART1_DPEC_BOTH (2 << UART_UCR3_DPEC_SHIFT) /* Interrupt on either edge */ + +/* UART Control Register 4 */ + +#define UART_UCR4_DREN (1 << 0) /* Bit 0: Receive data ready interrupt enable */ +#define UART_UCR4_OREN (1 << 1) /* Bit 1: Receiver overrun interrupt enable */ +#define UART_UCR4_BKEN (1 << 2) /* Bit 2: Break condition detected interrupt enable */ +#define UART_UCR4_TCEN (1 << 3) /* Bit 3: Transmit complete interrupt enable */ +#define UART_UCR4_LPBYP (1 << 4) /* Bit 4: Low Power B */ +#define UART_UCR4_IRSC (1 << 5) /* Bit 5: IR special case */ +#define UART_UCR4_IDDMAEN (1 << 6) /* Bit 6: DMA IDLE Condition Detected interrupt enable */ +#define UART_UCR4_WKEN (1 << 7) /* Bit 7: Wake interrupt enable */ +#define UART_UCR4_ENIRI (1 << 8) /* Bit 8: Serial infrared interrupt enable */ +#define UART_UCR4_INVR (1 << 9) /* Bit 9: Inverted reception */ +#define UART_UCR4_CTSTL_SHIFT 10 /* Bits 10-15: CTS trigger level */ +#define UART_UCR4_CTSTL_MASK (0x3f << UART_UCR4_CTSTL_SHIFT) +# define UART_UCR4_CTSTL(n) ((uint32_t)(n) << UART_UCR4_CTSTL_SHIFT) + +/* UART FIFO Control Register */ + +#define UART_UFCR_RXTL_SHIFT 0 /* Bits 0-6: Receiver Trigger Level */ +#define UART_UFCR_RXTL_MASK (0x3f << UART_UFCR_RXTL_SHIFT) +# define UART_UFCR_RXTL(n) ((uint32_t)(n) << UART_UFCR_RXTL_SHIFT) +#define UART_UFCR_RFDIV_SHIFT 7 /* Bits 7-9: Reference Frequency Divider */ +#define UART_UFCR_RFDIV_MASK (7 << UART_UFCR_RFDIV_SHIFT) +# define UART_UFCR_RFDIV6 (0 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 6 */ +# define UART_UFCR_RFDIV5 (1 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 5 */ +# define UART_UFCR_RFDIV4 (2 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 4 */ +# define UART_UFCR_RFDIV3 (3 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 3 */ +# define UART_UFCR_RFDIV2 (4 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 2 */ +# define UART_UFCR_RFDIV1 (5 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 1 */ +# define UART_UFCR_RFDIV7 (6 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 7 */ + +#define UART_UFCR_TXTL_SHIFT 10 /* Bits 10-15: Transmitter Trigger Level */ +#define UART_UFCR_TXTL_MASK (0x3f << UART_UFCR_TXTL_SHIFT) +# define UART_UFCR_TXTL(n) ((uint32_t)(n) << UART_UFCR_TXTL_SHIFT) + +/* UART Status 1 Register */ + +#define UART_USR1_SAD (1 << 3) /* Bit 3: RS-485 Slave Address Detected Interrupt Flag */ +#define UART_USR1_AWAKE (1 << 4) /* Bit 4: Asynchronous WAKE Interrupt Flag */ +#define UART_USR1_AIRINT (1 << 5) /* Bit 5: Asynchronous IR WAKE Interrupt Flag */ +#define UART_USR1_RXDS (1 << 6) /* Bit 6: Receiver IDLE Interrupt Flag */ +#define UART_USR1_DTRD (1 << 7) /* Bit 7: DTR Delta */ +#define UART_USR1_AGTIM (1 << 8) /* Bit 8: Aging Timer Interrupt Flag */ +#define UART_USR1_RRDY (1 << 9) /* Bit 9: RX Ready Interrupt/DMA Flag */ +#define UART_USR1_FRAMERR (1 << 10) /* Bit 10: Frame Error Interrupt Flag */ +#define UART_USR1_ESCF (1 << 11) /* Bit 11: Escape Sequence Interrupt Flag */ +#define UART_USR1_RTSD (1 << 12) /* Bit 12: RTS Delta */ +#define UART_USR1_TRDY (1 << 13) /* Bit 13: TX Ready Interrupt/DMA Flag */ +#define UART_USR1_RTSS (1 << 14) /* Bit 14: RTS_B Pin Status */ +#define UART_USR1_PARITYERR (1 << 15) /* Bit 15: Parity Error Interrupt Flag */ + +/* UART Status 2 Register */ + +#define UART_USR2_RDR (1 << 0) /* Bit 0: Receive data ready */ +#define UART_USR2_ORE (1 << 1) /* Bit 1: Overrun error */ +#define UART_USR2_BRCD (1 << 2) /* Bit 2: Break condition detected */ +#define UART_USR2_TXDC (1 << 3) /* Bit 3: Transmitter complete */ +#define UART_USR2_RTSF (1 << 4) /* Bit 4: RTS Edge Triggered Interrupt flag */ +#define UART_USR2_DCDIN (1 << 5) /* Bit 5: Data Carrier Detect Input */ +#define UART_USR2_DCDDELT (1 << 6) /* Bit 6: Data Carrier Detect Delta */ +#define UART_USR2_WAKE (1 << 7) /* Bit 7: Wake */ +#define UART_USR2_IRINT (1 << 8) /* Bit 8: Serial infrared interrupt flag */ +#define UART_USR2_RIIN (1 << 9) /* Bit 9: Ring Indicator Input */ +#define UART_USR2_RIDELT (1 << 10) /* Bit 10: Ring Indicator */ +#define UART_USR2_ACST (1 << 11) /* Bit 11: Autobaud Counter Stopped */ +#define UART_USR2_IDLE (1 << 12) /* Bit 12: Idle condition */ +#define UART_USR2_DTRF (1 << 13) /* Bit 13: DTR edge triggered interrupt flag */ +#define UART_USR2_TXFE (1 << 14) /* Bit 14: Transmit Buffer FIFO empty */ +#define UART_USR2_ADET (1 << 15) /* Bit 15: Automatic baud rate detection complete */ + +/* UART Escape Character Register */ + +#define UART_UESC_MASK 0xff /* Bits 0-7: UART Escape Character */ + +/* UART Escape Timer Register */ + +#define UART_UTIM_MASK 0xfff /* Bits 0-11: UART Escape Timer */ + +/* UART BRM Incremental Register */ + +#define UART_UBIR_MASK 0xffff /* Bits 0-15: Incremental Numerator */ + +/* UART BRM Modulator Register */ + +#define UART_UBMR_MASK 0xffff /* Bits 0-15: Modulator Denominator */ + +/* UART Baud Rate Count Register */ + +#define UART_UBRC_MASK 0xffff /* Bits 0-15: Baud Rate Count Register */ + +/* UART One Millisecond Register */ + +#define UART_ONEMS_MASK 0xffffff /* Bits 0-23: One Millisecond Register */ + +/* UART Test Register */ + +#define UART_UTS_SOFTRST (1 << 0) /* Bit 0: Software Reset */ +#define UART_UTS_RXFULL (1 << 3) /* Bit 3: RxFIFO FULL */ +#define UART_UTS_TXFULL (1 << 4) /* Bit 4: TxFIFO FULL */ +#define UART_UTS_RXEMPTY (1 << 5) /* Bit 5: RxFIFO Empty */ +#define UART_UTS_TXEMPTY (1 << 6) /* Bit 6: TxFIFO Empty */ +#define UART_UTS_RXDBG (1 << 9) /* Bit 9: RX FIFO debug mode */ +#define UART_UTS_LOOPIR (1 << 10) /* Bit 10: Loop TX and RX for IR Test (LOOPIR)*/ +#define UART_UTS_DBGEN (1 << 11) /* Bit 11: Debug enable B */ +#define UART_UTS_LOOP (1 << 12) /* Bit 12: Loop TX and RX for Test */ +#define UART_UTS_FRCPERR (1 << 13) /* Bit 13: Force Parity Error */ + +/* UART RS-485 Mode Control Register */ + +#define UART_UMCR_MDEN (1 << 0) /* Bit 0: 9-bit data or Multidrop Mode (RS-485) Enable */ +#define UART_UMCR_SLAM (1 << 1) /* Bit 1: RS-485 Slave Address Detect Mode Selection */ +#define UART_UMCR_TXB8 (1 << 2) /* Bit 2: Transmit RS-485 bit 8 */ +#define UART_UMCR_SADEN (1 << 3) /* Bit 3: RS-485 Slave Address Detected Interrupt Enable */ +#define UART_UMCR_SLADDR_SHIFT (8) /* Bits 8-15: RS-485 Slave Address Character */ +#define UART_UMCR_SLADDR_MASK (0xff << UART_UMCR_SLADDR_SHIFT) +# define UART_UMCR_SLADDR(n) ((uint32_t)(n) << UART_UMCR_SLADDR_SHIFT) + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_UART_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_allocateheap.c b/arch/arm/src/mx8mp/mx8mp_allocateheap.c new file mode 100644 index 0000000000..be9103ff5f --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_allocateheap.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "mpu.h" +#include "arm_internal.h" +#include "mx8mp_mpuinit.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS regions (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uintptr_t g_idle_topstack = (uintptr_t)_ebss + + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +void up_allocate_heap(void **heap_start, size_t *heap_size) +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = CONFIG_RAM_END - usize; + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)ubase; + *heap_size = usize; + + /* Allow user-mode access to the user heap memory */ + + mx8mp_mpu_uheap((uintptr_t)ubase, usize); +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * (and protects) the kernel-space heap. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = CONFIG_RAM_END - usize; + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif diff --git a/arch/arm/src/mx8mp/mx8mp_ccm.c b/arch/arm/src/mx8mp/mx8mp_ccm.c new file mode 100644 index 0000000000..851e70d2f4 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_ccm.c @@ -0,0 +1,642 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_ccm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mx8mp_ccm.h" +#include "hardware/mx8mp_rdc.h" + +#include +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t CLK_ROOT_MAP[CLOCK_ROOT_MAP_SIZE][8] = +{ + ARM_A53_CLK_MUX, + ARM_M7_CLK_MUX, + ML_CLK_MUX, + GPU3D_CORE_CLK_MUX, + GPU3D_SHADER_CLK_MUX, + GPU2D_CLK_MUX, + AUDIO_AXI_CLK_MUX, + HSIO_AXI_CLK_MUX, + MEDIA_ISP_CLK_MUX, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + MAIN_AXI_CLK_MUX, + ENET_AXI_CLK_MUX, + NAND_USDHC_BUS_CLK_MUX, + VPU_BUS_CLK_MUX, + MEDIA_AXI_CLK_MUX, + MEDIA_APB_CLK_MUX, + HDMI_APB_CLK_MUX, + HDMI_AXI_CLK_MUX, + GPU_AXI_CLK_MUX, + GPU_AHB_CLK_MUX, + NOC_CLK_MUX, + NOC_IO_CLK_MUX, + ML_AXI_CLK_MUX, + ML_AHB_CLK_MUX, + {}, + {}, + AHB_CLK_MUX, + IPG_CLK_MUX, + AUDIO_AHB_CLK_MUX, + {}, + {}, + {}, + MEDIA_DISP2_CLK_MUX, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + DRAM_SEL_CFG_MUX, + ARM_A53_CLK_ROOT_SEL_MUX, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + {}, + DRAM_ALT_CLK_MUX, + DRAM_APB_CLK_MUX, + VPU_G1_CLK_MUX, + VPU_G2_CLK_MUX, + CAN1_CLK_MUX, + CAN2_CLK_MUX, + MEMREPAIR_CLK_MUX, + PCIE_PHY_CLK_MUX, + PCIE_AUX_CLK_MUX, + I2C5_CLK_MUX, + I2C6_CLK_MUX, + SAI1_CLK_MUX, + SAI2_CLK_MUX, + SAI3_CLK_MUX, + {}, + SAI5_CLK_MUX, + SAI6_CLK_MUX, + ENET_QOS_CLK_MUX, + ENET_QOS_TIMER_CLK_MUX, + ENET_REF_CLK_MUX, + ENET_TIMER_CLK_MUX, + ENET_PHY_REF_CLK_MUX, + NAND_CLK_MUX, + QSPI_CLK_MUX, + USDHC1_CLK_MUX, + USDHC2_CLK_MUX, + I2C1_CLK_MUX, + I2C2_CLK_MUX, + I2C3_CLK_MUX, + I2C4_CLK_MUX, + UART1_CLK_MUX, + UART2_CLK_MUX, + UART3_CLK_MUX, + UART4_CLK_MUX, + {}, + {}, + GIC_CLK_MUX, + ECSPI1_CLK_MUX, + ECSPI2_CLK_MUX, + PWM1_CLK_MUX, + PWM2_CLK_MUX, + PWM3_CLK_MUX, + PWM4_CLK_MUX, + GPT1_CLK_MUX, + GPT2_CLK_MUX, + GPT3_CLK_MUX, + GPT4_CLK_MUX, + GPT5_CLK_MUX, + GPT6_CLK_MUX, + TRACE_CLK_MUX, + WDOG_CLK_MUX, + WRCLK_CLK_MUX, + IPP_DO_CLKO1_MUX, + IPP_DO_CLKO2_MUX, + HDMI_FDCC_TST_CLK_MUX, + HDMI_27M_CLK_MUX, + HDMI_REF_266M_CLK_MUX, + USDHC3_CLK_MUX, + MEDIA_CAM1_PIX_CLK_MUX, + MEDIA_MIPI_PHY1_REF_CLK_MUX, + MEDIA_DISP1_PIX_CLK_MUX, + MEDIA_CAM2_PIX_CLK_MUX, + MEDIA_LDB_CLK_MUX, + {}, + {}, + {}, + MEDIA_MIPI_TEST_BYTE_CLK_MUX, + ECSPI3_CLK_MUX, + PDM_CLK_MUX, + VPU_VC8000E_CLK_MUX, + SAI7_CLK_MUX, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint32_t root_frequency(uint32_t freq_in, + uint32_t main_div, + uint32_t pre_div, + uint32_t scaler, + uint32_t dsm) +{ + /* Reference manual chapter 5.1.5.4.4 SSCG and Fractional PLLs + * Fout = ((m + k /65536) * Fin) / (p * 2^s) + * with m -> main divider, p -> pre-divider, s -> post-scaler and k -> DSM + * => ((m * 65536 + k) * Fin) / (65536 * p * (1 << s)) + */ + + return (uint32_t)(((main_div * 65536llu + dsm) * freq_in) / + (65536llu * pre_div * (1 << scaler))); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t mx8mp_ccm_get_root_clock(int clk_root_src) +{ + uint32_t pll; + uint32_t dsm; + uint32_t final_div; + uint32_t fdiv0; + uint32_t main_div; + uint32_t pre_div; + uint32_t post_div; + uint32_t root_freq; + + dsm = 0; + final_div = 1; + + switch (clk_root_src) + { + case OSC_24M_REF_CLK: + return 24000000; + + case OSC_32K_REF_CLK: + return 32000; + + case ARM_PLL_CLK: + { + pll = CCM_ANALOG_ARM_PLL; + } + break; + + case DRAM_PLL1_CLK: + { + pll = CCM_ANALOG_DRAM_PLL; + dsm = (getreg32(pll + CCM_ANALOG_FDIV1) & CCM_FDIV1_DSM_MASK) + >> CCM_FDIV1_DSM_SHIFT; + } + break; + + case VPU_PLL_CLK: + { + pll = CCM_ANALOG_VPU_PLL; + } + break; + + case GPU_PLL_CLK: + { + pll = CCM_ANALOG_GPU_PLL; + } + break; + + case SYSTEM_PLL1_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + } + break; + + case SYSTEM_PLL1_DIV2_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 2; + } + break; + + case SYSTEM_PLL1_DIV3_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 3; + } + break; + + case SYSTEM_PLL1_DIV4_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 4; + } + break; + + case SYSTEM_PLL1_DIV5_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 5; + } + break; + + case SYSTEM_PLL1_DIV6_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 6; + } + break; + + case SYSTEM_PLL1_DIV8_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 8; + } + break; + + case SYSTEM_PLL1_DIV10_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 10; + } + break; + + case SYSTEM_PLL1_DIV20_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL1; + final_div = 20; + } + break; + + case SYSTEM_PLL2_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + } + break; + + case SYSTEM_PLL2_DIV2_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 2; + } + break; + + case SYSTEM_PLL2_DIV3_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 3; + } + break; + + case SYSTEM_PLL2_DIV4_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 4; + } + break; + + case SYSTEM_PLL2_DIV5_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 5; + } + break; + + case SYSTEM_PLL2_DIV6_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 6; + } + break; + + case SYSTEM_PLL2_DIV8_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 8; + } + break; + + case SYSTEM_PLL2_DIV10_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 10; + } + break; + + case SYSTEM_PLL2_DIV20_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL2; + final_div = 20; + break; + } + + case SYSTEM_PLL3_CLK: + { + pll = CCM_ANALOG_SYSTEM_PLL3; + } + break; + + case AUDIO_PLL1_CLK: + { + pll = CCM_ANALOG_AUDIO_PLL1; + dsm = (getreg32(pll + CCM_ANALOG_FDIV1) & CCM_FDIV1_DSM_MASK) + >> CCM_FDIV1_DSM_SHIFT; + } + break; + + case AUDIO_PLL2_CLK: + { + pll = CCM_ANALOG_AUDIO_PLL2; + dsm = (getreg32(pll + CCM_ANALOG_FDIV1) & CCM_FDIV1_DSM_MASK) + >> CCM_FDIV1_DSM_SHIFT; + } + break; + + case VIDEO_PLL_CLK: + { + pll = CCM_ANALOG_VIDEO_PLL1; + dsm = (getreg32(pll + CCM_ANALOG_FDIV1) & CCM_FDIV1_DSM_MASK) + >> CCM_FDIV1_DSM_SHIFT; + } + break; + + default: + return 0; + } + + fdiv0 = getreg32(pll + CCM_ANALOG_FDIV0); + main_div = (fdiv0 & CCM_FDIV0_MAIN_DIV_MASK) >> CCM_FDIV0_MAIN_DIV_SHIFT; + pre_div = (fdiv0 & CCM_FDIV0_PRE_DIV_MASK) >> CCM_FDIV0_PRE_DIV_SHIFT; + post_div = (fdiv0 & CCM_FDIV0_POST_DIV_MASK) >> CCM_FDIV0_POST_DIV_SHIFT; + root_freq = root_frequency(24000000, + main_div, + pre_div, + post_div, + dsm); + return root_freq / final_div; +} + +uint32_t mx8mp_ccm_get_clock(int clk_index) +{ + uint32_t reg; + uint32_t is_enable; + uint32_t pre_podf; + uint32_t post_podf; + uint32_t mux; + uint32_t src_clk; + + reg = getreg32(CCM_CLK_ROOT_BASE + 128 * clk_index); + is_enable = reg & CCM_CLK_ROOT_ENABLE; + pre_podf = (reg & CCM_CLK_ROOT_PRE_PODF_MASK) + >> CCM_CLK_ROOT_PRE_PODF_SHIFT; + post_podf = (reg & CCM_CLK_ROOT_POST_PODF_MASK) + >> CCM_CLK_ROOT_POST_PODF_SHIFT; + mux = (reg & CCM_CLK_ROOT_MUX_MASK) + >> CCM_CLK_ROOT_MUX_SHIFT; + + if (!is_enable) + { + return 0; + } + + src_clk = mx8mp_ccm_get_root_clock(CLK_ROOT_MAP[clk_index][mux]); + return src_clk / (pre_podf + 1) / (post_podf + 1); +} + +int mx8mp_ccm_configure_clock(int clk_index, + int clk_root_src, + uint32_t pre_div, + uint32_t post_div) +{ + uint32_t reg; + uint32_t value; + int mux = 8; + int i; + + for (i = 0; i < 8; ++i) + { + if (CLK_ROOT_MAP[clk_index][i] == clk_root_src) + { + mux = i; + break; + } + } + + if (mux == 8) + { + /* cannot find a mux for the desired clock root: + * skip the configuration + */ + + return -1; + } + + reg = CCM_CLK_ROOT_BASE + 128 * clk_index; + value = getreg32(reg) & CCM_CLK_ROOT_ENABLE; + value |= (((pre_div - 1) << CCM_CLK_ROOT_PRE_PODF_SHIFT) + & CCM_CLK_ROOT_PRE_PODF_MASK); + value |= (((post_div - 1) << CCM_CLK_ROOT_POST_PODF_SHIFT) + & CCM_CLK_ROOT_POST_PODF_MASK); + value |= ((mux << CCM_CLK_ROOT_MUX_SHIFT) + & CCM_CLK_ROOT_MUX_MASK); + putreg32(value, reg); + + return 0; +} + +void mx8mp_ccm_gate_clock(int gate_index, uint32_t value) +{ + uint32_t reg = (CCM_CCGR_BASE + gate_index * 16); + putreg32(value, reg); +} + +void mx8mp_ccm_enable_clock(int clk_index) +{ + uint32_t reg = CCM_CLK_ROOT_BASE + 128 * clk_index; + modreg32(CCM_CLK_ROOT_ENABLE, CCM_CLK_ROOT_ENABLE, reg); +} + +void mx8mp_ccm_gate_pll(int pll_index, uint32_t value) +{ + uint32_t reg = (CCM_PLL_BASE + pll_index * 16); + putreg32(value, reg); +} + +void mx8mp_ccm_configure_pll(int pll_index, + uint32_t main_div, + uint32_t pre_div, + uint32_t post_div, + uint32_t dsm) +{ + uint32_t reg_genctrl; + uint32_t reg_fdiv0; + uint32_t reg_fdiv1; + uint32_t genctrl; + uint32_t fdiv0; + + /* Associate pll_index (pll gating) to + * pll configuration register in CCM_ANALOG + */ + + switch (pll_index) + { + case ARM_PLL_CLK: + { + reg_genctrl = CCM_ANALOG_ARM_PLL; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case GPU_PLL_CLK: + { + reg_genctrl = CCM_ANALOG_GPU_PLL; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case VPU_PLL_CLK: + { + reg_genctrl = CCM_ANALOG_VPU_PLL; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case DRAM_PLL1_CLK: + { + reg_genctrl = CCM_ANALOG_DRAM_PLL; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case SYSTEM_PLL1_CLK: + { + reg_genctrl = CCM_ANALOG_SYSTEM_PLL1; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case SYSTEM_PLL2_CLK: + { + reg_genctrl = CCM_ANALOG_SYSTEM_PLL2; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case SYSTEM_PLL3_CLK: + { + reg_genctrl = CCM_ANALOG_SYSTEM_PLL3; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = 0; + } + break; + + case AUDIO_PLL1_CLK: + { + reg_genctrl = CCM_ANALOG_AUDIO_PLL1; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = reg_genctrl + CCM_ANALOG_FDIV1; + } + break; + + case AUDIO_PLL2_CLK: + { + reg_genctrl = CCM_ANALOG_ARM_PLL; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = reg_genctrl + CCM_ANALOG_FDIV1; + } + break; + + case VIDEO_PLL_CLK: + { + reg_genctrl = CCM_ANALOG_ARM_PLL; + reg_fdiv0 = reg_genctrl + CCM_ANALOG_FDIV0; + reg_fdiv1 = reg_genctrl + CCM_ANALOG_FDIV1; + } + break; + + default: /* unknown PLL - skip configuration */ + return; + } + + /* Disable PLL, no bypass, clock ref on 24MHz */ + + genctrl = getreg32(reg_genctrl); + genctrl &= ~(CCM_PLL_RST | CCM_PLL_BYPASS | CCM_PLL_REF_CLK_SEL_MASK); + putreg32(genctrl, reg_genctrl); + + /* Apply dividers */ + + fdiv0 = 0; + fdiv0 |= ((main_div << CCM_FDIV0_MAIN_DIV_SHIFT) + & CCM_FDIV0_MAIN_DIV_MASK); + fdiv0 |= ((pre_div << CCM_FDIV0_PRE_DIV_SHIFT) + & CCM_FDIV0_PRE_DIV_MASK); + fdiv0 |= ((post_div << CCM_FDIV0_POST_DIV_SHIFT) + & CCM_FDIV0_POST_DIV_MASK); + putreg32(fdiv0, reg_fdiv0); + + if (reg_fdiv1 != 0) + { + uint32_t fdiv1 = 0; + fdiv1 |= ((dsm << CCM_FDIV1_DSM_SHIFT) + & CCM_FDIV1_DSM_MASK); + putreg32(fdiv1, reg_fdiv1); + } + + /* Enable PLL */ + + genctrl = getreg32(reg_genctrl); + genctrl |= (CCM_PLL_CLKE | CCM_PLL_RST); + putreg32(genctrl, reg_genctrl); + + /* Wait for PLL to stabilize */ + + while (!(getreg32(reg_genctrl) & CCM_PLL_LOCK)); +} diff --git a/arch/arm/src/mx8mp/mx8mp_ccm.h b/arch/arm/src/mx8mp/mx8mp_ccm.h new file mode 100644 index 0000000000..d2e966bbc8 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_ccm.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_ccm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_CCM_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "hardware/mx8mp_ccm.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_ccm_get_root_clock + * + * Description: + * Retrieve the root clock frequency. + * + ****************************************************************************/ + +uint32_t mx8mp_ccm_get_root_clock(int clk_root_index); + +/**************************************************************************** + * Name: mx8mp_ccm_get_clock + * + * Description: + * Retrieve the clock frequency. + * + ****************************************************************************/ + +uint32_t mx8mp_ccm_get_clock(int clk_index); + +/**************************************************************************** + * Name: mx8mp_ccm_configure_clock + * + * Description: + * Configure a clock by setting its root clock source + * and its dividers. + * + ****************************************************************************/ + +int mx8mp_ccm_configure_clock(int clk_index, + int clk_root_src, + uint32_t pre_div, + uint32_t post_div); + +/**************************************************************************** + * Name: mx8mp_ccm_enable_clock + * + * Description: + * Enable a clock. + * + ****************************************************************************/ + +void mx8mp_ccm_enable_clock(int clk_index); + +/**************************************************************************** + * Name: mx8mp_ccm_gate_clock + * + * Description: + * Apply desired gating configuration to the clock. + * + ****************************************************************************/ + +void mx8mp_ccm_gate_clock(int gate_index, uint32_t value); + +/**************************************************************************** + * Name: mx8mp_ccm_gate_pll + * + * Description: + * Apply desired gating configuration to the PLL. + * + ****************************************************************************/ + +void mx8mp_ccm_gate_pll(int pll_index, uint32_t value); + +/**************************************************************************** + * Name: mx8mp_ccm_configure_pll + * + * Description: + * Configure a PLL by settings its divider and DSM (if any). + * + ****************************************************************************/ + +void mx8mp_ccm_configure_pll(int pll_index, + uint32_t main_div, + uint32_t pre_div, + uint32_t post_div, + uint32_t dsm); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_CCM_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_clockconfig.c b/arch/arm/src/mx8mp/mx8mp_clockconfig.c new file mode 100644 index 0000000000..1198bd00c1 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_clockconfig.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "mx8mp_ccm.h" +#include "mx8mp_clockconfig.h" +#include "hardware/mx8mp_gpc.h" +#include + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_clockconfig + * + * Description: + * Called to initialize the i.MXRT. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void mx8mp_clockconfig(void) +{ + /* Ensure the clock of the peripherals used by M core not be affected by + * A core which is running in a different domain. + */ + + mx8mp_ccm_gate_clock(CCM_IOMUX_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_IPMUX1_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_IPMUX2_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_IPMUX3_CLK_GATE, CLK_ALWAYS_NEEDED); + + mx8mp_ccm_gate_pll(SYSTEM_PLL1_CLK, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_pll(SYSTEM_PLL2_CLK, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_pll(SYSTEM_PLL3_CLK, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_pll(AUDIO_PLL1_CLK, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_pll(AUDIO_PLL2_CLK, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_pll(VIDEO_PLL_CLK, CLK_ALWAYS_NEEDED); + + /* Set Cortex-M7 clock source to System PLL1 with no division (800MHz) */ + + mx8mp_ccm_configure_clock(ARM_M7_CLK_ROOT, SYSTEM_PLL1_CLK, 1, 1); + + /* Add dependency on OCRAM and RDC module to the M7 */ + + mx8mp_ccm_gate_clock(CCM_OCRAM_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_RDC_CLK_GATE, CLK_ALWAYS_NEEDED); + + /* Enable Audio clock to power on the audiomix domain */ + + mx8mp_ccm_gate_clock(CCM_AUDIO_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_enable_clock(AUDIO_AXI_CLK_ROOT); + + /* Make sure the M7 core could work normally when A53 core + * enters the low power status. + */ + + mx8mp_ccm_gate_clock(CCM_OCRAM_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_RDC_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_SIM_M_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_SIM_MAIN_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_SIM_S_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_SIM_WAKEUP_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_DEBUG_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_SEC_DEBUG_CLK_GATE, CLK_ALWAYS_NEEDED); + + /* Make sure that main buses are enabled (TODO to be tuned or adjust + * by configuration) + */ + + mx8mp_ccm_enable_clock(IPG_CLK_ROOT); + mx8mp_ccm_enable_clock(AHB_CLK_ROOT); + mx8mp_ccm_enable_clock(MAIN_AXI_CLK_ROOT); + mx8mp_ccm_enable_clock(DRAM_ALT_CLK_ROOT); + + /* Power up the audiomix domain by M7 core. */ + + /* Map the audiomix domain to M7 */ + + modreg32(AUDIOMIX_DOMAIN, + AUDIOMIX_DOMAIN, + GPC_PGC_CPU_M7_MAPPING); + + /* Software request to trigger power up the domain */ + + modreg32(AUDIOMIX_SW_PUP_REQ, + AUDIOMIX_SW_PUP_REQ, + GPC_PU_PGC_SW_PUP_REQ); + + /* Waiting the AUDIOMIX_SW_PUP_REQ bit to self-cleared after power up */ + + while (getreg32(GPC_PU_PGC_SW_PUP_REQ) & AUDIOMIX_SW_PUP_REQ); + + /* Do the handshake to make sure the NOC bus ready after + * power up the AUDIOMIX domain. + */ + + modreg32(GPC_AUDIOMIX_NOC_PWRDNREQN, + GPC_AUDIOMIX_NOC_PWRDNREQN, + GPC_PU_PWRHSK); + while (!(getreg32(GPC_PU_PWRHSK) & GPC_AUDIOMIX_PWRDNACKN)); + + /* Init Audio PLL and buses */ + + /* AUDIO PLL1 to 393.216 MHz (multiple of 48kHz audio sampling rate) */ + + mx8mp_ccm_configure_pll(CCM_ANALOG_AUDIO_PLL1, 262, 2, 3, 9437); + + /* AUDIO PLL2 to 361.2672 MHz (multiple of 44.1kHz audio sampling rate) */ + + mx8mp_ccm_configure_pll(CCM_ANALOG_AUDIO_PLL2, 361, 3, 3, 17511); + + /* Audio AXI on PLL1 @ 800MHz */ + + mx8mp_ccm_configure_clock(AUDIO_AXI_CLK_ROOT, SYSTEM_PLL1_CLK, 1, 1); + + /* Audio AHB on PLL1 @ 400MHz */ + + mx8mp_ccm_configure_clock(AUDIO_AHB_CLK_ROOT, SYSTEM_PLL1_CLK, 1, 2); +} diff --git a/arch/arm/src/mx8mp/mx8mp_clockconfig.h b/arch/arm/src/mx8mp/mx8mp_clockconfig.h new file mode 100644 index 0000000000..d574b05f81 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_clockconfig.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_clockconfig + * + * Description: + * Called to initialize the i.MX8MP. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void mx8mp_clockconfig(void); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_CLOCKCONFIG_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_clrpend.c b/arch/arm/src/mx8mp/mx8mp_clrpend.c new file mode 100644 index 0000000000..51717f920e --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_clrpend.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_clrpend.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "arm_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. Don't know why... + * + * I keep it in a separate file so that it will not increase the footprint + * on mx8mp platforms that do not need this function. + * + ****************************************************************************/ + +void mx8mp_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= MX8MP_IRQ_FIRST) + { + if (irq < (MX8MP_IRQ_FIRST + 32)) + { + putreg32(1 << (irq - MX8MP_IRQ_FIRST), + NVIC_IRQ0_31_CLRPEND); + } + else if (irq < (MX8MP_IRQ_FIRST + 64)) + { + putreg32(1 << (irq - MX8MP_IRQ_FIRST - 32), + NVIC_IRQ32_63_CLRPEND); + } + else if (irq < (MX8MP_IRQ_FIRST +96)) + { + putreg32(1 << (irq - MX8MP_IRQ_FIRST - 64), + NVIC_IRQ64_95_CLRPEND); + } + else if (irq < (MX8MP_IRQ_FIRST +128)) + { + putreg32(1 << (irq - MX8MP_IRQ_FIRST - 96), + NVIC_IRQ96_127_CLRPEND); + } + else if (irq < NR_IRQS) + { + putreg32(1 << (irq - MX8MP_IRQ_FIRST - 128), + NVIC_IRQ128_159_CLRPEND); + } + } +} diff --git a/arch/arm/src/mx8mp/mx8mp_config.h b/arch/arm/src/mx8mp/mx8mp_config.h new file mode 100644 index 0000000000..4844321303 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_config.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_config.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_CONFIG_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Is there a serial console? It could be on UART1-4 */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_MX8MP_UART1) +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_MX8MP_UART2) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_MX8MP_UART3) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_MX8MP_UART4) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_CONSOLE Setting" +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef HAVE_UART_CONSOLE +#endif + +/* Ensure that the MPU is enabled: it is requiered to access devices */ + +#ifndef CONFIG_ARM_MPU +#error "MPU is requiered for proper behavior" +#endif + +#endif /* __ARCH_ARM_SRC_MX8MP_IMX_CONFIG_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_idle.c b/arch/arm/src/mx8mp/mx8mp_idle.c new file mode 100644 index 0000000000..ed045d1f78 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_idle.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} diff --git a/arch/arm/src/mx8mp/mx8mp_iomuxc.c b/arch/arm/src/mx8mp/mx8mp_iomuxc.c new file mode 100644 index 0000000000..2d346593e4 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_iomuxc.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_iomuxc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "mx8mp_iomuxc.h" + +/* MUX_MODE - MUX Mode Select Field. */ + +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) + +/* SION - Software Input On Field. */ + +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) + +/* DAISY - Selecting Pads Involved in Daisy Chain. */ + +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0xFU) +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_iomuxc_config + ****************************************************************************/ + +void mx8mp_iomuxc_config(uint32_t mux_register, + uint32_t mux_mode, + uint32_t input_register, + uint32_t input_daisy, + uint32_t config_register, + uint32_t sion, + uint32_t config) +{ + putreg32(IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | + IOMUXC_SW_MUX_CTL_PAD_SION(sion), + mux_register); + + if (input_register) + { + putreg32(IOMUXC_SELECT_INPUT_DAISY(input_daisy), input_register); + } + + if (config_register) + { + putreg32(config, config_register); + } +} diff --git a/arch/arm/src/mx8mp/mx8mp_iomuxc.h b/arch/arm/src/mx8mp/mx8mp_iomuxc.h new file mode 100644 index 0000000000..b3b6f01de9 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_iomuxc.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_iomuxc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_IOMUXC_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "hardware/mx8mp_pinmux.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_iomuxc_set_pin_config + * + * Description: + * Congigure the IOMUXC pin configuration. + * The first five parameters can be filled with the pin function ID macros. + * + ****************************************************************************/ + +void mx8mp_iomuxc_config(uint32_t mux_register, + uint32_t mux_mode, + uint32_t input_register, + uint32_t input_daisy, + uint32_t config_register, + uint32_t sion, + uint32_t config); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_IOMUXC_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_irq.c b/arch/arm/src/mx8mp/mx8mp_irq.c new file mode 100644 index 0000000000..47fe11d74e --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_irq.c @@ -0,0 +1,566 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_dump_nvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void mx8mp_dump_nvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x " + "SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), + getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), + getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), + getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE), + getreg32(NVIC_IRQ96_127_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), + getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), + getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), + getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), + getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), + getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), + getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), + getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), + getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), + getreg32(NVIC_IRQ60_63_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY), + getreg32(NVIC_IRQ68_71_PRIORITY), + getreg32(NVIC_IRQ72_75_PRIORITY), + getreg32(NVIC_IRQ76_79_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ80_83_PRIORITY), + getreg32(NVIC_IRQ84_87_PRIORITY), + getreg32(NVIC_IRQ88_91_PRIORITY), + getreg32(NVIC_IRQ92_95_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ96_99_PRIORITY), + getreg32(NVIC_IRQ100_103_PRIORITY), + getreg32(NVIC_IRQ104_107_PRIORITY), + getreg32(NVIC_IRQ108_111_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ112_115_PRIORITY), + getreg32(NVIC_IRQ116_129_PRIORITY), + getreg32(NVIC_IRQ120_123_PRIORITY), + getreg32(NVIC_IRQ124_127_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ128_131_PRIORITY), + getreg32(NVIC_IRQ132_135_PRIORITY), + getreg32(NVIC_IRQ136_139_PRIORITY), + getreg32(NVIC_IRQ140_143_PRIORITY)); + irqinfo(" %08x %08x\n", + getreg32(NVIC_IRQ144_147_PRIORITY), + getreg32(NVIC_IRQ148_151_PRIORITY)); + leave_critical_section(flags); +} +#else +# define mx8mp_dump_nvic(msg, irq) +#endif + +/**************************************************************************** + * Name: mx8mp_nmi, mx8mp_pendsv, + * mx8mp_dbgmonitor, mx8mp_pendsv, mx8mp_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int mx8mp_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int mx8mp_pendsv(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int mx8mp_dbgmonitor(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int mx8mp_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: mx8mp_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void mx8mp_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: mx8mp_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int mx8mp_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + DEBUGASSERT(irq >= MX8MP_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= MX8MP_IRQ_FIRST) + { + if (irq < (MX8MP_IRQ_FIRST + 32)) + { + *regaddr = (NVIC_IRQ0_31_ENABLE + offset); + *bit = 1 << (irq - MX8MP_IRQ_FIRST); + } + else if (irq < (MX8MP_IRQ_FIRST + 64)) + { + *regaddr = (NVIC_IRQ32_63_ENABLE + offset); + *bit = 1 << (irq - MX8MP_IRQ_FIRST - 32); + } + else if (irq < (MX8MP_IRQ_FIRST + 96)) + { + *regaddr = (NVIC_IRQ64_95_ENABLE + offset); + *bit = 1 << (irq - MX8MP_IRQ_FIRST - 64); + } + else if (irq < NR_IRQS) + { + *regaddr = (NVIC_IRQ96_127_ENABLE + offset); + *bit = 1 << (irq - MX8MP_IRQ_FIRST - 96); + } + else + { + return ERROR; /* Invalid irq */ + } + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == MX8MP_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == MX8MP_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == MX8MP_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == MX8MP_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uintptr_t regaddr; + int nintlines; + int i; +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + uint32_t regval; +#endif + + /* The NVIC ICTR register (bits 0-4) holds the number of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable registers, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR; + i > 0; + i--, regaddr += 4) + { + putreg32(0xffffffff, regaddr); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + arm_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(MX8MP_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(MX8MP_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(MX8MP_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + mx8mp_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(MX8MP_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(MX8MP_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(MX8MP_IRQ_NMI, mx8mp_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(MX8MP_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(MX8MP_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(MX8MP_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(MX8MP_IRQ_PENDSV, mx8mp_pendsv, NULL); + irq_attach(MX8MP_IRQ_DBGMONITOR, mx8mp_dbgmonitor, NULL); + irq_attach(MX8MP_IRQ_RESERVED, mx8mp_reserved, NULL); +#endif + + mx8mp_dump_nvic("initial", NR_IRQS); + + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + +#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif + + /* And finally, enable interrupts */ + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (mx8mp_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= MX8MP_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + mx8mp_dump_nvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (mx8mp_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= MX8MP_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + mx8mp_dump_nvic("enable", irq); +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +#if 0 /* Does not appear to be necessary in most cases */ + mx8mp_clrpend(irq); +#endif +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= MX8MP_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < MX8MP_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= MX8MP_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + mx8mp_dump_nvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/mx8mp/mx8mp_lowputc.c b/arch/arm/src/mx8mp/mx8mp_lowputc.c new file mode 100644 index 0000000000..19d369c9ee --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_lowputc.c @@ -0,0 +1,412 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" + +#include "mx8mp_config.h" +#include "mx8mp_lowputc.h" +#include "mx8mp_iomuxc.h" +#include "mx8mp_ccm.h" +#include "hardware/mx8mp_pinmux.h" +#include "hardware/mx8mp_uart.h" +#include /* Include last: has dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +#if defined(HAVE_UART_CONSOLE) +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_BASE MX8M_UART1 +# define CONSOLE_FREQ UART1_CLK_ROOT +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_2STOP CONFIG_UART1_2STOP +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_BASE MX8M_UART2 +# define CONSOLE_FREQ UART2_CLK_ROOT +# define CONSOLE_BAUD CONFIG_UART2_BAUD +# define CONSOLE_BITS CONFIG_UART2_BITS +# define CONSOLE_2STOP CONFIG_UART2_2STOP +# define CONSOLE_PARITY CONFIG_UART2_PARITY +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_BASE MX8M_UART3 +# define CONSOLE_FREQ UART3_CLK_ROOT +# define CONSOLE_BAUD CONFIG_UART3_BAUD +# define CONSOLE_BITS CONFIG_UART3_BITS +# define CONSOLE_2STOP CONFIG_UART3_2STOP +# define CONSOLE_PARITY CONFIG_UART3_PARITY +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_BASE MX8M_UART4 +# define CONSOLE_CLK UART4_CLK_ROOT +# define CONSOLE_BAUD CONFIG_UART4_BAUD +# define CONSOLE_BITS CONFIG_UART4_BITS +# define CONSOLE_2STOP CONFIG_UART4_2STOP +# define CONSOLE_PARITY CONFIG_UART4_PARITY +# elif defined(HAVE_UART_CONSOLE) +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_UART_CONSOLE +static const struct uart_config_s g_console_config = +{ + .baud = CONSOLE_BAUD, + .parity = CONSOLE_PARITY, + .bits = CONSOLE_BITS, + .stopbits2 = CONSOLE_2STOP +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int mx8mp_uart_configure(uint32_t base, + uint32_t clk_frequency, + const struct uart_config_s *config) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint64_t tmp; + uint32_t regval; + uint32_t ucr2; + uint32_t refclk; + uint32_t div; + uint32_t num; + uint32_t den; + b16_t ratio; + + /* Disable the UART */ + + putreg32(0, base + UART_UCR1_OFFSET); + putreg32(0, base + UART_UCR2_OFFSET); + putreg32(0, base + UART_UCR3_OFFSET); + putreg32(0, base + UART_UCR4_OFFSET); + + /* Wait for the UART to come out of reset */ + + while ((getreg32(base + UART_UCR2_OFFSET) & UART_UCR2_SRST) == 0); + + /* Set up UCR2, Clearing all bits that will be configured below. */ + + ucr2 = getreg32(base + UART_UCR2_OFFSET); + ucr2 &= ~(UART_UCR2_WS | UART_UCR2_STPB | UART_UCR2_PREN | + UART_UCR2_PROE | UART_UCR2_IRTS | UART_UCR2_CTSC); + + /* Select the number of data bits */ + + DEBUGASSERT(config->bits == 7 || config->bits == 8); + if (config->bits == 8) + { + ucr2 |= UART_UCR2_WS; + } + + /* Select the number of stop bits */ + + if (config->stopbits2) + { + ucr2 |= UART_UCR2_STPB; + } + + /* Select even/odd parity */ + + if (config->parity != 0) + { + DEBUGASSERT(config->parity == 1 || config->parity == 2); + ucr2 |= UART_UCR2_PREN; + if (config->parity == 1) + { + ucr2 |= UART_UCR2_PROE; + } + } + + /* Setup hardware flow control */ + + regval = 0; + +#if 0 + if (config->hwfc) + { + /* CTS controlled by Rx FIFO */ + + ucr2 |= UART_UCR2_CTSC; + + /* Set CTS trigger level */ + + regval |= 30 << UART_UCR4_CTSTL_SHIFT; + + /* REVISIT: There are other relevant bits that must be managed in + * UCR1 and UCR3. + */ + } + else +#endif + { + /* Ignore RTS */ + + ucr2 |= UART_UCR2_IRTS; + } + + putreg32(regval, base + UART_UCR4_OFFSET); + + /* Setup the new UART configuration */ + + putreg32(ucr2, base + UART_UCR2_OFFSET); + + /* Select a reference clock divider. + * REVISIT: For now we just use a divider of 2. That might not be + * optimal for very high or very low baud settings. + */ + + div = 2; + refclk = (clk_frequency >> 1); + + /* Set the baud. + * + * baud = REFFREQ / (16 * NUM/DEN) + * baud = REFFREQ / 16 / RATIO + * RATIO = REFREQ / 16 / baud; + * + * NUM = SCALE * RATIO + * DEN = SCALE + * + * UMBR = NUM-1 + * UBIR = DEN-1; + */ + + tmp = ((uint64_t)refclk << (16 - 4)) / config->baud; + DEBUGASSERT(tmp < 0x0000000100000000ll); + ratio = (b16_t)tmp; + + /* Pick a scale factor that gives us about 14 bits of accuracy. + * REVISIT: Why not go all the way to 16-bits? + */ + + if (ratio < b16HALF) + { + den = (1 << 15); + num = b16toi(ratio << 15); + DEBUGASSERT(num > 0); + } + else if (ratio < b16ONE) + { + den = (1 << 14); + num = b16toi(ratio << 14); + } + else if (ratio < itob16(2)) + { + den = (1 << 13); + num = b16toi(ratio << 13); + } + else if (ratio < itob16(4)) + { + den = (1 << 12); + num = b16toi(ratio << 12); + } + else if (ratio < itob16(8)) + { + den = (1 << 11); + num = b16toi(ratio << 11); + } + else if (ratio < itob16(16)) + { + den = (1 << 10); + num = b16toi(ratio << 10); + } + else if (ratio < itob16(32)) + { + den = (1 << 9); + num = b16toi(ratio << 9); + } + else if (ratio < itob16(64)) + { + den = (1 << 8); + num = b16toi(ratio << 8); + } + else if (ratio < itob16(128)) + { + den = (1 << 7); + num = b16toi(ratio << 7); + } + else if (ratio < itob16(256)) + { + den = (1 << 6); + num = b16toi(ratio << 6); + } + else if (ratio < itob16(512)) + { + den = (1 << 5); + num = b16toi(ratio << 5); + } + else if (ratio < itob16(1024)) + { + den = (1 << 4); + num = b16toi(ratio << 4); + } + else if (ratio < itob16(2048)) + { + den = (1 << 3); + num = b16toi(ratio << 3); + } + else if (ratio < itob16(4096)) + { + den = (1 << 2); + num = b16toi(ratio << 2); + } + else if (ratio < itob16(8192)) + { + den = (1 << 1); + num = b16toi(ratio << 1); + } + else /* if (ratio < itob16(16384)) */ + { + DEBUGASSERT(ratio < itob16(16384)); + den = (1 << 0); + num = b16toi(ratio); + } + + /* Reduce if possible without losing accuracy. */ + + while ((num & 1) == 0 && (den & 1) == 0) + { + num >>= 1; + den >>= 1; + } + + /* The actual values are we write to the registers need to be + * decremented by 1. NOTE that the UBIR must be set before + * the UBMR. + */ + + putreg32(den - 1, base + UART_UBIR_OFFSET); + putreg32(num - 1, base + UART_UBMR_OFFSET); + + /* Fixup the divisor, the value in the UFCR register is + * + * 000 = Divide input clock by 6 + * 001 = Divide input clock by 5 + * 010 = Divide input clock by 4 + * 011 = Divide input clock by 3 + * 100 = Divide input clock by 2 + * 101 = Divide input clock by 1 + * 110 = Divide input clock by 7 + */ + + if (div == 7) + { + div = 6; + } + else + { + div = 6 - div; + } + + regval = div << UART_UFCR_RFDIV_SHIFT; + + /* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer + * characters. Set the RX trigger level to interrupt when the RxFIFO has + * 1 character. + */ + + regval |= ((2 << UART_UFCR_TXTL_SHIFT) | (1 << UART_UFCR_RXTL_SHIFT)); + putreg32(regval, base + UART_UFCR_OFFSET); + + /* Selected. Selects proper input pins for serial and Infrared input + * signal. NOTE: In this chip, UARTs are used in MUXED mode, so that this + * bit should always be set. + */ + + putreg32(UART_UCR3_RXDMUXSEL, base + UART_UCR3_OFFSET); + + /* Enable the TX and RX */ + + ucr2 |= (UART_UCR2_TXEN | UART_UCR2_RXEN); + putreg32(ucr2, base + UART_UCR2_OFFSET); + + /* Enable the UART */ + + regval = getreg32(base + UART_UCR1_OFFSET); + regval |= UART_UCR1_UARTEN; + putreg32(regval, base + UART_UCR1_OFFSET); +#endif + + return OK; +} + +/**************************************************************************** + * Name: mx8mp_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void mx8mp_lowsetup(void) +{ +#ifdef HAVE_UART_CONSOLE + mx8mp_iomuxc_config(IOMUX_CONSOLE_UART_RX); + mx8mp_iomuxc_config(IOMUX_CONSOLE_UART_TX); + + uint32_t clk = mx8mp_ccm_get_clock(CONSOLE_CLK); + mx8mp_uart_configure(CONSOLE_BASE, clk, &g_console_config); +#endif +} + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output a byte with as few system dependencies as possible. This will + * even work BEFORE the console is initialized if we are booting from + * U-Boot (and the same UART is used for the console, of course.) + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Poll the TX fifo trigger level bit of the UART status register. When the + * TXFE bit is non-zero, the TX Buffer FIFO is empty. + */ + + while ((getreg32(CONSOLE_BASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0); + + /* Send the character by writing it into the UART_TXD register. */ + + putreg32((uint32_t)ch, CONSOLE_BASE + UART_TXD_OFFSET); +#endif +} diff --git a/arch/arm/src/mx8mp/mx8mp_lowputc.h b/arch/arm/src/mx8mp/mx8mp_lowputc.h new file mode 100644 index 0000000000..fdaf7e16ca --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_lowputc.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_LOWPUTC_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_uart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +int mx8mp_uart_configure(uint32_t base, + uint32_t clock, + const struct uart_config_s *config); + +/**************************************************************************** + * Name: imx_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void mx8mp_lowsetup(void); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_LOWPUTC_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_mpuinit.c b/arch/arm/src/mx8mp/mx8mp_mpuinit.c new file mode 100644 index 0000000000..54b635b9d0 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_mpuinit.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_mpuinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "mpu.h" +#include "mx8mp_mpuinit.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_mpu_initialize + * + * Description: + * Configure the MPU to permit access to imx8mp SoC complex. + * + ****************************************************************************/ + +void mx8mp_mpu_initialize(void) +{ + /* Show MPU information */ + + mpu_showtype(); + + /* Reset MPU if enabled */ + + mpu_reset(); + + /* Region 0 [0x0000_0000 - 0x3FFF_FFFF] + * Device type, not executable, not shareable, non-cacheable. + */ + + mpu_configure_region(0x00000000, 1 * 1024 * 1024 * 1024, + MPU_RASR_TEX_DEV | /* Device + * Not Cacheable */ + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_XN); /* Not executable */ + + /* Region 1 TCML[0x0000_0000 - 0x0001_FFFF] + * Normal type, not shareable, non-cacheable + */ + + mpu_configure_region(0x00000000, 128 * 1024, + MPU_RASR_TEX_NOR | /* Normal + * Not Cacheable */ + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Executable */ + + /* Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF] + * Normal type, not shareable, cacheable + */ + + mpu_configure_region(0x08000000, 128 * 1024 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Executable */ + + /* Region 3 TCMU[0x2000_0000 - 0x2001_FFFF] + * Normal type, not shareable, non-cacheable + */ + + mpu_configure_region(0x20000000, 128 * 1024, + MPU_RASR_TEX_NOR | /* Normal + * Not Cacheable */ + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Executable */ + + /* Region 4 DDR[0x4000_0000 - 0x7FFF_FFFF] + * Normal type, not shareable, cacheable + */ + + mpu_configure_region(0x40000000, 1 * 1024 * 1024 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Executable */ +#if 0 + +#ifdef CONFIG_BUILD_PROTECTED + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); + + /* Configure user flash and SRAM space */ + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_intsram(datastart, dataend - datastart); +#endif + +#endif + + /* Enable MPU and HFNMIENA feature + * HFNMIENA ensures that M7 core uses MPU configuration when in hard fault, + * NMI, and FAULTMASK handlers, otherwise all memory regions are accessed + * without MPU protection, which has high risks of cacheable, + * especially for AIPS systems. + */ + + mpu_control(true, true, true); +} + +/**************************************************************************** + * Name: mx8mp_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void mx8mp_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/mx8mp/mx8mp_mpuinit.h b/arch/arm/src/mx8mp/mx8mp_mpuinit.h new file mode 100644 index 0000000000..af5629da2a --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_mpuinit.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_mpuinit.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_MPUINIT_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted + * i.MX8MP resources. + * + ****************************************************************************/ + +void mx8mp_mpu_initialize(void); + +/**************************************************************************** + * Name: mx8mp_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +#error not implemented +void mx8mp_mpu_uheap(uintptr_t start, size_t size); +#else +# define mx8mp_mpu_uheap(start,size) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_MPUINIT_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_serial.c b/arch/arm/src/mx8mp/mx8mp_serial.c new file mode 100644 index 0000000000..88cf405e6b --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_serial.c @@ -0,0 +1,1151 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "mx8mp_lowputc.h" +#include "mx8mp_ccm.h" +#include "mx8mp_serial.h" +#include "hardware/mx8mp_uart.h" + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Which UART with be tty0/console and which tty1-3? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART1-4 */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3 is console */ +# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* UART4 is console */ +# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_MX8MP_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_MX8MP_UART2) +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +# elif defined(CONFIG_MX8MP_UART3) +# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +# elif defined(CONFIG_MX8MP_UART4) +# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of UART1-4 excluding the console UART. + * One of UART1-4 could be the console; one of UART1-4 has already been + * assigned to ttys0. + */ + +#if defined(CONFIG_MX8MP_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_MX8MP_UART2) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_MX8MP_UART3) && !defined(UART3_ASSIGNED) +# define TTYS1_DEV g_uart3port /* UART3 is ttyS1 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_MX8MP_UART4) && !defined(UART4_ASSIGNED) +# define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ +# define UART4_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART2-4. It can't be UART1 because that + * was either assigned as ttyS0 or ttys1. One of UART 1-4 could be the + * console. One of UART2-4 has already been assigned to ttys0 or ttyS1. + */ + +#if defined(CONFIG_MX8MP_UART2) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_MX8MP_UART3) && !defined(UART3_ASSIGNED) +# define TTYS2_DEV g_uart3port /* UART3 is ttyS2 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_MX8MP_UART4) && !defined(UART4_ASSIGNED) +# define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ +# define UART4_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of UART3-4. It can't be UART1-2 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * UART3-4 could also be the console. One of UART3-4 has already + * been assigned to ttys0, 1, or 3. + */ + +#if defined(CONFIG_MX8MP_UART3) && !defined(UART3_ASSIGNED) +# define TTYS3_DEV g_uart3port /* UART3 is ttyS3 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_MX8MP_UART4) && !defined(UART4_ASSIGNED) +# define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ +# define UART4_ASSIGNED 1 +#endif + +/* UART, if available, should have been assigned to ttyS0-4. */ + +#if defined(CONFIG_MX8MP_UART4) && !defined(UART4_ASSIGNED) +# errnor UART4 was not assigned to a TTY. +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct mx8mp_uart_s +{ + int clock; /* Peripheral clock as described in hardware/mx8mp_ccm.h */ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t ie; /* Saved enabled interrupts */ + uint32_t ucr1; /* Saved UCR1 value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t iflow:1; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t oflow:1; /* output flow control (CTS) enabled */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t mx8mp_serialin(struct mx8mp_uart_s *priv, + uint32_t offset); +static inline void mx8mp_serialout(struct mx8mp_uart_s *priv, + uint32_t offset, + uint32_t value); +static inline void mx8mp_disableuartint(struct mx8mp_uart_s *priv, + uint32_t *ucr1); +static inline void mx8mp_restoreuartint(struct mx8mp_uart_s *priv, + uint32_t ucr1); +static inline void mx8mp_waittxready(struct mx8mp_uart_s *priv); + +static int mx8mp_setup(struct uart_dev_s *dev); +static void mx8mp_shutdown(struct uart_dev_s *dev); +static int mx8mp_attach(struct uart_dev_s *dev); +static void mx8mp_detach(struct uart_dev_s *dev); +static int mx8mp_interrupt(int irq, void *context, void *arg); +static int mx8mp_ioctl(struct file *filep, int cmd, unsigned long arg); +static int mx8mp_receive(struct uart_dev_s *dev, unsigned int *status); +static void mx8mp_rxint(struct uart_dev_s *dev, bool enable); +static bool mx8mp_rxavailable(struct uart_dev_s *dev); +static void mx8mp_send(struct uart_dev_s *dev, int ch); +static void mx8mp_txint(struct uart_dev_s *dev, bool enable); +static bool mx8mp_txready(struct uart_dev_s *dev); +static bool mx8mp_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Serial driver UART operations */ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = mx8mp_setup, + .shutdown = mx8mp_shutdown, + .attach = mx8mp_attach, + .detach = mx8mp_detach, + .ioctl = mx8mp_ioctl, + .receive = mx8mp_receive, + .rxint = mx8mp_rxint, + .rxavailable = mx8mp_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = mx8mp_send, + .txint = mx8mp_txint, + .txready = mx8mp_txready, + .txempty = mx8mp_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_MX8MP_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MX8MP_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MX8MP_UART3 +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_MX8MP_UART4 +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif + +/* This describes the state of the IMX uart1 port. */ + +#ifdef CONFIG_MX8MP_UART1 +static struct mx8mp_uart_s g_uart1priv = +{ + .clock = UART1_CLK_ROOT, + .uartbase = MX8M_UART1, + .baud = CONFIG_UART1_BAUD, + .irq = MX8MP_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static struct uart_dev_s g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the IMX uart2 port. */ + +#ifdef CONFIG_MX8MP_UART2 +static struct mx8mp_uart_s g_uart2priv = +{ + .clock = UART2_CLK_ROOT, + .uartbase = MX8M_UART2, + .baud = CONFIG_UART2_BAUD, + .irq = MX8MP_IRQ_UART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static struct uart_dev_s g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +#ifdef CONFIG_MX8MP_UART3 +static struct mx8mp_uart_s g_uart3priv = +{ + .clock = UART3_CLK_ROOT, + .uartbase = MX8M_UART3, + .baud = CONFIG_UART3_BAUD, + .irq = MX8MP_IRQ_UART3, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stopbits2 = CONFIG_UART3_2STOP, +}; + +static struct uart_dev_s g_uart3port = +{ + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +#ifdef CONFIG_MX8MP_UART4 +static struct mx8mp_uart_s g_uart4priv = +{ + .clock = UART4_CLK_ROOT, + .uartbase = MX8M_UART4, + .baud = CONFIG_UART4_BAUD, + .irq = MX8MP_IRQ_UART4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, +}; + +static struct uart_dev_s g_uart4port = +{ + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_serialin + ****************************************************************************/ + +static inline uint32_t mx8mp_serialin(struct mx8mp_uart_s *priv, + uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: mx8mp_serialout + ****************************************************************************/ + +static inline void mx8mp_serialout(struct mx8mp_uart_s *priv, + uint32_t offset, + uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: mx8mp_disableuartint + ****************************************************************************/ + +static inline void mx8mp_disableuartint(struct mx8mp_uart_s *priv, + uint32_t *ucr1) +{ + /* Return the current Rx and Tx interrupt state */ + + if (ucr1 != NULL) + { + *ucr1 = priv->ucr1 & (UART_UCR1_RRDYEN | UART_UCR1_TXEMPTYEN); + } + + /* Then disable both Rx and Tx interrupts */ + + priv->ucr1 &= ~(UART_UCR1_RRDYEN | UART_UCR1_TXEMPTYEN); + mx8mp_serialout(priv, UART_UCR1_OFFSET, priv->ucr1); +} + +/**************************************************************************** + * Name: mx8mp_restoreuartint + ****************************************************************************/ + +static inline void mx8mp_restoreuartint(struct mx8mp_uart_s *priv, + uint32_t ucr1) +{ + /* Enable/disable any interrupts that are currently disabled but should be + * enabled/disabled. + */ + + priv->ucr1 &= ~(UART_UCR1_RRDYEN | UART_UCR1_TXEMPTYEN); + priv->ucr1 |= ucr1 & (UART_UCR1_RRDYEN | UART_UCR1_TXEMPTYEN); + mx8mp_serialout(priv, UART_UCR1_OFFSET, priv->ucr1); +} + +/**************************************************************************** + * Name: mx8mp_waittxready + ****************************************************************************/ + +static inline void mx8mp_waittxready(struct mx8mp_uart_s *priv) +{ + int tmp; + + for (tmp = 1000 ; tmp > 0 ; tmp--) + { + if ((mx8mp_serialin(priv, UART_UTS_OFFSET) & UART_UTS_TXFULL) == 0) + { + break; + } + } +} + +/**************************************************************************** + * Name: mx8mp_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int mx8mp_setup(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct uart_config_s config; + int ret; + + /* Configure the UART */ + + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + + uint32_t clk = mx8mp_ccm_get_clock(priv->clock); + ret = mx8mp_uart_configure(priv->uartbase, clk, &config); + + /* Initialize the UCR1 shadow register */ + + priv->ucr1 = mx8mp_serialin(priv, UART_UCR1_OFFSET); + return ret; + +#else + /* Initialize the UCR1 shadow register */ + + priv->ucr1 = mx8mp_serialin(priv, UART_UCR1_OFFSET); + return OK; +#endif +} + +/**************************************************************************** + * Name: mx8mp_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void mx8mp_shutdown(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + /* Disable the UART */ + + mx8mp_serialout(priv, UART_UCR1_OFFSET, 0); + mx8mp_serialout(priv, UART_UCR2_OFFSET, 0); + mx8mp_serialout(priv, UART_UCR3_OFFSET, 0); + mx8mp_serialout(priv, UART_UCR4_OFFSET, 0); +} + +/**************************************************************************** + * Name: mx8mp_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int mx8mp_attach(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, mx8mp_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: mx8mp_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void mx8mp_detach(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: mx8mp_interrupt (and front-ends) + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int mx8mp_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct mx8mp_uart_s *priv; + uint32_t usr1; + int passes = 0; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct mx8mp_uart_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + for (; ; ) + { + /* Get the current UART status and check for loop + * termination conditions + */ + + usr1 = mx8mp_serialin(priv, UART_USR1_OFFSET); + usr1 &= (UART_USR1_RRDY | UART_USR1_TRDY); + + if (usr1 == 0 || passes > 256) + { + return OK; + } + + /* Handle incoming, receive bytes */ + + if (usr1 & UART_USR1_RRDY) + { + uart_recvchars(dev); + } + + /* Handle outgoing, transmit bytes */ + + if (usr1 & UART_USR1_TRDY && + (mx8mp_serialin(priv, UART_UCR1_OFFSET) & UART_UCR1_TXEMPTYEN) != 0) + { + uart_xmitchars(dev); + } + + /* Keep track of how many times we do this in case there + * is some hardware failure condition. + */ + + passes++; + } +} + +/**************************************************************************** + * Name: mx8mp_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int mx8mp_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct mx8mp_uart_s *user = (struct mx8mp_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct mx8mp_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); +#endif + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + +#if defined(CS9) + case 9: + termiosp->c_cflag |= CS9; + break; +#endif + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + +#if defined(CS9) + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flags = spin_lock_irqsave(NULL); + mx8mp_disableuartint(priv, &ie); + ret = mx8mp_setup(dev); + + /* Restore the interrupt state */ + + mx8mp_restoreuartint(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(NULL, flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: mx8mp_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int mx8mp_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + uint32_t rxd0; + + rxd0 = mx8mp_serialin(priv, UART_RXD_OFFSET); + *status = rxd0; + return (rxd0 & UART_RXD_DATA_MASK) >> UART_RXD_DATA_SHIFT; +} + +/**************************************************************************** + * Name: mx8mp_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void mx8mp_rxint(struct uart_dev_s *dev, bool enable) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + /* Enable interrupts for data availab at Rx FIFO */ + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ucr1 |= UART_UCR1_RRDYEN; +#endif + } + else + { + priv->ucr1 &= ~UART_UCR1_RRDYEN; + } + + mx8mp_serialout(priv, UART_UCR1_OFFSET, priv->ucr1); +} + +/**************************************************************************** + * Name: mx8mp_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool mx8mp_rxavailable(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + /* Return true is data is ready in the Rx FIFO */ + + return ((mx8mp_serialin(priv, UART_USR2_OFFSET) & UART_USR2_RDR) != 0); +} + +/**************************************************************************** + * Name: mx8mp_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void mx8mp_send(struct uart_dev_s *dev, int ch) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + mx8mp_serialout(priv, UART_TXD_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: mx8mp_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void mx8mp_txint(struct uart_dev_s *dev, bool enable) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + /* We won't take an interrupt until the FIFO is completely empty (although + * there may still be a transmission in progress). + */ + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ucr1 |= UART_UCR1_TXEMPTYEN; +#endif + } + else + { + priv->ucr1 &= ~UART_UCR1_TXEMPTYEN; + } + + mx8mp_serialout(priv, UART_UCR1_OFFSET, priv->ucr1); +} + +/**************************************************************************** + * Name: mx8mp_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool mx8mp_txready(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + /* When TXFULL is set, there is no space in the Tx FIFO */ + + return ((mx8mp_serialin(priv, UART_UTS_OFFSET) & UART_UTS_TXFULL) == 0); +} + +/**************************************************************************** + * Name: mx8mp_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool mx8mp_txempty(struct uart_dev_s *dev) +{ + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)dev->priv; + + /* When TXDC is set, the FIFO is empty and the transmission is complete */ + + return ((mx8mp_serialin(priv, UART_USR2_OFFSET) & UART_USR2_TXDC) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before arm_serialinit. + * + ****************************************************************************/ + +void arm_earlyserialinit(void) +{ + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was performed by the + * function mx8mp_lowsetup() earlier in the boot sequence. + */ + + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ +#ifdef HAVE_UART_CONSOLE + CONSOLE_DEV.isconsole = true; + mx8mp_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that mx8mp_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef HAVE_UART_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV); +# ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +# ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV); +# ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS2_DEV); +# ifdef TTYS4_DEV + uart_register("/dev/ttyS4", &TTYS2_DEV); +# endif +# endif +# endif +# endif +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug + * writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + struct mx8mp_uart_s *priv = (struct mx8mp_uart_s *)CONSOLE_DEV.priv; + uint32_t ier; + + /* Disable UART interrupts and wait until the hardware is ready to send + * a byte. + */ + + mx8mp_disableuartint(priv, &ier); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm_lowputc('\r'); + } + + arm_lowputc(ch); + mx8mp_restoreuartint(priv, ier); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +# undef MX8MP_CONSOLE_VBASE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define MX8MP_CONSOLE MX8M_UART1 +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define MX8MP_CONSOLE MX8M_UART2 +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define MX8MP_CONSOLE MX8M_UART3 +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define MX8MP_CONSOLE MX8M_UART4 +# endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef MX8MP_CONSOLE +static inline void mx8mp_waittxready(void) +{ + int tmp; + + for (tmp = 1000 ; tmp > 0 ; tmp--) + { + /* Loop until TXFULL is zero -- meaning that there is space available + * in the TX FIFO. + */ + + if ((getreg32(MX8MP_CONSOLE + UART_UTS_OFFSET) & UART_UTS_TXFULL) == 0) + { + break; + } + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef MX8MP_CONSOLE + mx8mp_waittxready(); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + putreg32((uint16_t)'\r', MX8MP_CONSOLE + UART_TXD_OFFSET); + mx8mp_waittxready(); + } + + putreg32((uint16_t)ch, MX8MP_CONSOLE + UART_TXD_OFFSET); +#endif + + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/mx8mp/mx8mp_serial.h b/arch/arm/src/mx8mp/mx8mp_serial.h new file mode 100644 index 0000000000..30cc8b78ce --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_serial.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_serial.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_SERIAL_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "mx8mp_config.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_serialinit + * + * Description: + * Register the UART serial console and serial ports. This assumes that + * mx8mp_earlyserialinit was called previously. + * + ****************************************************************************/ + +#ifdef MX8MP_HAVE_UART +void arm_serialinit(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_SERIAL_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_start.c b/arch/arm/src/mx8mp/mx8mp_start.c new file mode 100644 index 0000000000..09ec8b8e1c --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_start.c @@ -0,0 +1,184 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "mx8mp_mpuinit.h" +#include "mx8mp_lowputc.h" +#include "mx8mp_userspace.h" +#include "mx8mp_clockconfig.h" +#include "mx8mp_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) noinstrument_function; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile ("sub r10, sp, %0" : : "r" + (CONFIG_IDLETHREAD_STACKSIZE - 64) :); +#endif + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in SRAM is given by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initialization code + * at _framfuncs + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = (const uint32_t *)_framfuncs, + dest = (uint32_t *)_sramfuncs; dest < (uint32_t *)_eramfuncs; + ) + { + *dest++ = *src++; + } +#endif + + /* Initialize the FPU (if configured) */ + + arm_fpuconfig(); + + /* Initialize the MPU to handle caching accesses */ + + mx8mp_mpu_initialize(); + + /* Enable I cache and D cache now that MPU is initialized */ + + up_enable_icache(); + up_enable_dcache(); + + /* Perform clock initialization */ + + mx8mp_clockconfig(); + + /* Configure the uart and perform early serial initialization so that we + * can get debug output as soon as possible (This depends on clock + * configuration). + */ + + mx8mp_lowsetup(); + showprogress('A'); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + arm_earlyserialinit(); + showprogress('B'); +#endif + +#ifdef CONFIG_BUILD_PROTECTED + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + + mx8mp_userspace(); + showprogress('C'); +#endif + + /* Initialize other on-board resources */ + + mx8mp_board_initialize(); + showprogress('D'); + + /* Then start NuttX */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/mx8mp/mx8mp_start.h b/arch/arm/src/mx8mp/mx8mp_start.h new file mode 100644 index 0000000000..6178b95a22 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_start.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_start.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_START_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_board_initialize + * + * Description: + * All MX8MP architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void mx8mp_board_initialize(void); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_START_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_timerisr.c b/arch/arm/src/mx8mp/mx8mp_timerisr.c new file mode 100644 index 0000000000..debe37c93a --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_timerisr.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "arm_internal.h" +#include "chip.h" +#include "mx8mp_ccm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + */ + +#define SYSTICK_RELOAD(coreclk) (((coreclk) / CLK_TCK) - 1) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int mx8mp_timerisr(int irq, uint32_t *regs, void *arg); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imxrt_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int mx8mp_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + uint32_t coreclk; + uint32_t reload; + + /* Get the reload value */ + + coreclk = mx8mp_ccm_get_clock(ARM_M7_CLK_ROOT); + reload = SYSTICK_RELOAD(coreclk); + + /* The size of the reload field is 24 bits. */ + + DEBUGASSERT(reload <= 0x00ffffff); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(reload, NVIC_SYSTICK_RELOAD); + putreg32(0, NVIC_SYSTICK_CURRENT); + + /* Attach the timer interrupt vector */ + + irq_attach(MX8MP_IRQ_SYSTICK, (xcpt_t)mx8mp_timerisr, NULL); + + /* Enable SysTick interrupts */ + + regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE); + putreg32(regval, NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(MX8MP_IRQ_SYSTICK); +} diff --git a/arch/arm/src/mx8mp/mx8mp_userspace.h b/arch/arm/src/mx8mp/mx8mp_userspace.h new file mode 100644 index 0000000000..9ec09c9d19 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_userspace.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_userspace.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_USERSPACE_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_USERSPACE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void mx8mp_userspace(void); +#endif + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_USERSPACE_H */ diff --git a/boards/Kconfig b/boards/Kconfig index 65a8b19ea9..e15971b9ec 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2745,6 +2745,12 @@ config ARCH_BOARD_XMC4700RELAX select ARCH_HAVE_IRQBUTTONS ---help--- Infineon XMC4700 Relax + +config ARCH_BOARD_VERDIN_MX8MP + bool "Toradex Verdin i.MX8MP" + depends on ARCH_CHIP_MX8MP + ---help--- + Toradex Verdin i.MX8MP config ARCH_BOARD_Z16F2800100ZCOG bool "Zilog Z16F2800100ZCOG Development Kit" @@ -3211,6 +3217,7 @@ config ARCH_BOARD default "viewtool-stm32f107" if ARCH_BOARD_VIEWTOOL_STM32F107 default "xmc4500-relax" if ARCH_BOARD_XMC4500RELAX default "xmc4700-relax" if ARCH_BOARD_XMC4700RELAX + default "verdin-mx8mp" if ARCH_BOARD_VERDIN_MX8MP default "z16f2800100zcog" if ARCH_BOARD_Z16F2800100ZCOG default "z20x" if ARCH_BOARD_Z20X default "z80sim" if ARCH_BOARD_Z80SIM @@ -3894,6 +3901,9 @@ endif if ARCH_BOARD_XMC4700RELAX source "boards/arm/xmc4/xmc4700-relax/Kconfig" endif +if ARCH_BOARD_VERDIN_MX8MP +source "boards/arm/mx8mp/verdin-mx8mp/Kconfig" +endif if ARCH_BOARD_AVR32DEV1 source "boards/avr/at32uc3/avr32dev1/Kconfig" endif diff --git a/boards/arm/mx8mp/verdin-mx8mp/Kconfig b/boards/arm/mx8mp/verdin-mx8mp/Kconfig new file mode 100644 index 0000000000..f72f3c094c --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/boards/arm/mx8mp/verdin-mx8mp/README.txt b/boards/arm/mx8mp/verdin-mx8mp/README.txt new file mode 100644 index 0000000000..b536017ac8 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/README.txt @@ -0,0 +1,10 @@ +README for the verdin-mx8mp Relax +============================ + + The directory provides board support for the Toradex Verdin mx8mp. + Note: this port works on the internal Cortex-M7 auxiliary core, NOT the main Cortex-53 complex! + +Status +====== + + 2023-08-23: The Verdin mx8mp boots into NSH, provides the NSH prompt. diff --git a/boards/arm/mx8mp/verdin-mx8mp/configs/nsh/defconfig b/boards/arm/mx8mp/verdin-mx8mp/configs/nsh/defconfig new file mode 100644 index 0000000000..a5e0437712 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/configs/nsh/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_RAMFUNCS is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="verdin-mx8mp" +CONFIG_ARCH_BOARD_VERDIN_MX8MP=y +CONFIG_ARCH_CHIP="mx8mp" +CONFIG_ARCH_CHIP_MX8MP=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARM_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=159972 +CONFIG_BUILTIN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MX8MP_UART4=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=10 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2014 +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_RAMTEST=y +CONFIG_UART4_SERIAL_CONSOLE=y diff --git a/boards/arm/mx8mp/verdin-mx8mp/include/board.h b/boards/arm/mx8mp/verdin-mx8mp/include/board.h new file mode 100644 index 0000000000..11472f2893 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/include/board.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_MX8MP_MX8MP_VERDIN_INCLUDE_BOARD_H +#define __BOARDS_ARM_MX8MP_MX8MP_VERDIN_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOMUX_CONSOLE_UART_RX IOMUXC_UART4_RXD_UART4_RX, 0, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PE_MASK +#define IOMUX_CONSOLE_UART_TX IOMUXC_UART4_TXD_UART4_TX, 0, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PE_MASK + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_MX8MP_MX8MP_VERDIN_INCLUDE_BOARD_H */ diff --git a/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs b/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs new file mode 100644 index 0000000000..a4da6f694d --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ddr.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) diff --git a/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld b/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld new file mode 100644 index 0000000000..0b54256c50 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* +* The on-chip SRAM is split in two parts: +* 1) 128Kb of program memory located at 0x0000:0000 +* 2) 128Kb of data memory beginning at the address 0x2000:0000 +* +* The cortex-m7 can also use the main memory (DDR, shared with the Cortex-A53) and we choose to use it here for the program memory to overcome the size limitation. +*/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x80000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x80100000, LENGTH = 1024K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + __CACHE_REGION_START = ORIGIN(flash); + __CACHE_REGION_SIZE = LENGTH(flash) + LENGTH(sram); +} diff --git a/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld b/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld new file mode 100644 index 0000000000..f3a417f88e --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* +* The on-chip SRAM is split in two parts: +* 1) 128Kb of program memory located at 0x0000:0000 +* 2) 128Kb of data memory beginning at the address 0x2000:0000 +*/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/mx8mp/verdin-mx8mp/src/Makefile b/boards/arm/mx8mp/verdin-mx8mp/src/Makefile new file mode 100644 index 0000000000..9d4ba8179a --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/src/Makefile @@ -0,0 +1,29 @@ +############################################################################ +# boards/arm/mx8mp/verdin-mx8mp/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = mx8mp_boot.c mx8mp_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += mx8mp_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_appinit.c b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_appinit.c new file mode 100644 index 0000000000..fe0faaa1d3 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "verdin-mx8mp.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return mx8mp_bringup(); +#else + return OK; +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ +} diff --git a/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_boot.c b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_boot.c new file mode 100644 index 0000000000..8cd8bc3c62 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_boot.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "verdin-mx8mp.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_board_initialize + * + * Description: + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void mx8mp_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + mx8mp_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c new file mode 100644 index 0000000000..2d42980dbe --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_USERLED +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int mx8mp_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/mx8mp/verdin-mx8mp/src/verdin-mx8mp.h b/boards/arm/mx8mp/verdin-mx8mp/src/verdin-mx8mp.h new file mode 100644 index 0000000000..cb6308f164 --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/src/verdin-mx8mp.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/mx8mp/verdin-mx8mp/src/verdin-mx8mp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_MX8MP_MX8MP_VERDIN_SRC_VERDIN_MX8MP_H +#define __BOARDS_ARM_MX8MP_MX8MP_VERDIN_SRC_VERDIN_MX8MP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int mx8mp_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_MX8MP_MX8MP_VERDIN_SRC_VERDIN_MX8MP_H */