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esp32[c6|h2]: Add pulse counter support

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This commit is contained in:
Eren Terzioglu 2024-11-01 15:19:10 +01:00 committed by Alan C. Assis
parent 3894dc12b0
commit e48d092778
19 changed files with 2435 additions and 285 deletions
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2
Documentation/platforms/risc-v/esp32c6/index.rst
View file

@ -287,7 +287,7 @@ Int. Temp. No
LED No
LED_PWM Yes
MCPWM Yes
Pulse Counter No
Pulse Counter Yes
RMT No
RNG No
RSA No

2
Documentation/platforms/risc-v/esp32h2/index.rst
View file

@ -287,7 +287,7 @@ Int. Temp. No
LED No
LED_PWM Yes
MCPWM No
Pulse Counter No
Pulse Counter Yes
RMT No
RNG No
RSA No

31
arch/risc-v/src/common/espressif/Kconfig
View file

@ -554,14 +554,20 @@ config ESP_MCPWM
config ESP_PCNT
bool "Pulse Counter (PCNT / QE) Module"
default n
select CAPTURE
depends on ESPRESSIF_ESP32H2 || ESPRESSIF_ESP32C6
---help---
Pulse Counter is currently used to implement Quadrature
Encoder.
menu "Pulse Counter (PCNT) Configuration"
depends on ESP_PCNT
config ESP_PCNT_TEST_MODE
bool "Pulse Counter character driver loopback test mode (for testing only)"
default n
---help---
This enables a loopback test mode that attaches the transmitter
to the receiver internally, being able to test the PCNT
peripheral without any external connection.
config ESP_PCNT_AS_QE
bool
default n
@ -574,7 +580,7 @@ if ESP_PCNT_U0
config ESP_PCNT_U0_QE
bool "Use this PCNT Unit as Quadrature Encoder"
default y
default n
select ESP_PCNT_AS_QE
config ESP_PCNT_U0_CH0_EDGE_PIN
@ -584,15 +590,15 @@ config ESP_PCNT_U0_CH0_EDGE_PIN
config ESP_PCNT_U0_CH0_LEVEL_PIN
int "PCNT_U0 CH0 Level/Control Pin Number"
default 4
default 4 if !ESP_PCNT_U0_QE
default -1 if ESP_PCNT_U0_QE
range -1 39
depends on !ESP_PCNT_U0_QE
config ESP_PCNT_U0_CH1_EDGE_PIN
int "PCNT_U0 CH1 Edge/Pulse Pin Number"
default 0
default 0 if !ESP_PCNT_U0_QE
default -1 if ESP_PCNT_U0_QE
range -1 39
depends on !ESP_PCNT_U0_QE
config ESP_PCNT_U0_CH1_LEVEL_PIN
int "PCNT_U0 CH1 Level/Control Pin Number"
@ -618,13 +624,14 @@ endif # ESP_PCNT_U0
config ESP_PCNT_U1
bool "Enable PCNT Unit 1"
depends on ESP_PCNT_U0
default n
if ESP_PCNT_U1
config ESP_PCNT_U1_QE
bool "Use this PCNT Unit as Quadrature Encoder"
default y
default n
select ESP_PCNT_AS_QE
config ESP_PCNT_U1_CH0_EDGE_PIN
@ -668,13 +675,14 @@ endif # ESP_PCNT_U1
config ESP_PCNT_U2
bool "Enable PCNT Unit 2"
depends on ESP_PCNT_U1
default n
if ESP_PCNT_U2
config ESP_PCNT_U2_QE
bool "Use this PCNT Unit as Quadrature Encoder"
default y
default n
select ESP_PCNT_AS_QE
config ESP_PCNT_U2_CH0_EDGE_PIN
@ -718,13 +726,14 @@ endif # ESP_PCNT_U2
config ESP_PCNT_U3
bool "Enable PCNT Unit 3"
depends on ESP_PCNT_U2
default n
if ESP_PCNT_U3
config ESP_PCNT_U3_QE
bool "Use this PCNT Unit as Quadrature Encoder"
default y
default n
select ESP_PCNT_AS_QE
config ESP_PCNT_U3_CH0_EDGE_PIN

7
arch/risc-v/src/common/espressif/Make.defs
View file

@ -85,8 +85,11 @@ ifeq ($(CONFIG_ESPRESSIF_LEDC),y)
CHIP_CSRCS += esp_ledc.c
endif
ifeq ($(CONFIG_ESP_PCNT_AS_QE),y)
CHIP_CSRCS += esp_qencoder.c
ifeq ($(CONFIG_ESP_PCNT),y)
CHIP_CSRCS += esp_pcnt.c
ifeq ($(CONFIG_ESP_PCNT_AS_QE),y)
CHIP_CSRCS += esp_qencoder.c
endif
endif
ifeq ($(CONFIG_ESPRESSIF_USBSERIAL),y)

1380
arch/risc-v/src/common/espressif/esp_pcnt.c Normal file
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File diff suppressed because it is too large Load diff

238
arch/risc-v/src/common/espressif/esp_pcnt.h Normal file
View file

@ -0,0 +1,238 @@
/****************************************************************************
* arch/risc-v/src/common/espressif/esp_pcnt.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_PCNT_H
#define __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_PCNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ESP_PCNT_CHAN_INVERT_EDGE_IN (1 << 0)
#define ESP_PCNT_CHAN_INVERT_LVL_IN (1 << 1)
#define ESP_PCNT_CHAN_VIRT_EDGE_IO_LVL (1 << 2)
#define ESP_PCNT_CHAN_VIRT_LVL_IO_LVL (1 << 3)
#define ESP_PCNT_CHAN_IO_LOOPBACK (1 << 4)
/****************************************************************************
* Public Types
****************************************************************************/
enum esp_pcnt_chan_level_action_e
{
ESP_PCNT_CHAN_LEVEL_ACTION_KEEP, /* Keep current count mode */
ESP_PCNT_CHAN_LEVEL_ACTION_INVERSE, /* Invert current count mode */
ESP_PCNT_CHAN_LEVEL_ACTION_HOLD, /* Hold current count value */
};
enum esp_pcnt_chan_edge_action_e
{
ESP_PCNT_CHAN_EDGE_ACTION_HOLD, /* Hold current count value */
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE, /* Increase count value */
ESP_PCNT_CHAN_EDGE_ACTION_DECREASE, /* Decrease count value */
};
enum esp_pcnt_unit_zero_cross_mode_e
{
ESP_PCNT_UNIT_ZERO_CROSS_POS_ZERO, /* From positive value to zero */
ESP_PCNT_UNIT_ZERO_CROSS_NEG_ZERO, /* From negative value, to zero */
ESP_PCNT_UNIT_ZERO_CROSS_NEG_POS, /* From negative value, to positive value */
ESP_PCNT_UNIT_ZERO_CROSS_POS_NEG, /* From positive value, to negative value */
};
struct esp_pcnt_unit_config_s
{
int low_limit; /* Low limitation of the count unit */
int high_limit; /* High limitation of the count unit */
bool accum_count; /* Accumulate the count value when overflow flag */
};
struct esp_pcnt_chan_config_s
{
int edge_gpio_num; /* Edge signal GPIO number,-1 if unused */
int level_gpio_num; /* Level signal GPIO number ,-1 if unused */
int flags; /* Channel config flags */
};
struct esp_pcnt_watch_event_data_s
{
int unit_id; /* PCNT Unit id */
int watch_point_value; /* Watch point value that triggered the event */
enum esp_pcnt_unit_zero_cross_mode_e zero_cross_mode; /* Zero cross mode */
};
/****************************************************************************
* Public functions
****************************************************************************/
/****************************************************************************
* Name: esp_pcnt_new_unit
*
* Description:
* Request PCNT unit and config it with given parameters.
*
* Input Parameters:
* config - PCNT unit configuration
*
* Returned Value:
* PCNT unit number (>=0) if success or -1 if fail.
*
****************************************************************************/
struct cap_lowerhalf_s *esp_pcnt_new_unit(
struct esp_pcnt_unit_config_s *config);
/****************************************************************************
* Name: esp_pcnt_del_unit
*
* Description:
* Delete PCNT unit.
*
* Input Parameters:
* dev - Pointer to the pcnt driver struct
*
* Returned Value:
* OK on success; ERROR on failure
*
****************************************************************************/
int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev);
/****************************************************************************
* Name: esp_pcnt_unit_add_watch_point
*
* Description:
* Add watch point to given PCNT unit.
*
* Input Parameters:
* dev - Pointer to the pcnt driver struct
* ret - Value to watch
*
* Returned Value:
* OK on success; ERROR on failure
*
****************************************************************************/
int esp_pcnt_unit_add_watch_point(struct cap_lowerhalf_s *dev,
int watch_point);
/****************************************************************************
* Name: esp_pcnt_unit_remove_watch_point
*
* Description:
* Remove watch point from given PCNT unit.
*
* Input Parameters:
* dev - Pointer to the pcnt driver struct
* ret - Watch point value to remove
*
* Returned Value:
* OK on success; ERROR on failure
*
****************************************************************************/
int esp_pcnt_unit_remove_watch_point(struct cap_lowerhalf_s *dev,
int watch_point);
/****************************************************************************
* Name: esp_pcnt_new_channel
*
* Description:
* Request channel on given PCNT unit and config it with given parameters.
*
* Input Parameters:
* dev - Pointer to the pcnt driver struct
* config - PCNT unit channel configuration
*
* Returned Value:
* PCNT unit channel number (>=0) if success or -1 if fail.
*
****************************************************************************/
int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
struct esp_pcnt_chan_config_s *config);
/****************************************************************************
* Name: esp_pcnt_del_channel
*
* Description:
* Delete PCNT unit channel.
*
* Input Parameters:
* channel - Channel number to delete
*
* Returned Value:
* OK on success; ERROR on failure
*
****************************************************************************/
int esp_pcnt_del_channel(int channel);
/****************************************************************************
* Name: esp_pcnt_channel_set_edge_action
*
* Description:
* Set channel actions when edge signal changes.
*
* Input Parameters:
* channel - Channel number to set actions
* post act - Action on posedge signal
* neg_act - Action on negedge signal
*
* Returned Value:
* OK on success; ERROR on failure
*
****************************************************************************/
void esp_pcnt_channel_set_edge_action(int channel,
enum esp_pcnt_chan_edge_action_e pos_act,
enum esp_pcnt_chan_edge_action_e neg_act);
/****************************************************************************
* Name: esp_pcnt_channel_set_level_action
*
* Description:
* Set channel actions when level signal changes.
*
* Input Parameters:
* channel - Channel number to set actions
* post act - Action on posedge signal
* neg_act - Action on negedge signal
*
* Returned Value:
* OK on success; ERROR on failure
*
****************************************************************************/
void esp_pcnt_channel_set_level_action(int channel,
enum esp_pcnt_chan_level_action_e pos_act,
enum esp_pcnt_chan_level_action_e neg_act);
#endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_PCNT_H */

219
arch/risc-v/src/common/espressif/esp_qencoder.c
View file

@ -36,6 +36,8 @@
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/sensors/qencoder.h>
#include <nuttx/sensors/sensor.h>
#include <nuttx/timers/capture.h>
#include <arch/board/board.h>
@ -80,24 +82,10 @@
* Private Types
****************************************************************************/
/* Constant configuration structure that is retained in FLASH */
struct esp_qeconfig_s
{
uint8_t pcntid; /* PCNT ID {0,1,2,3} */
uint8_t ch0_gpio; /* Channel 0 gpio pin (Edge/Pulse) */
uint8_t ch1_gpio; /* Channel 1 gpio pin (Level/Ctrl) */
uint32_t ch0_pulse_sig; /* ch0 pulse signal index */
uint32_t ch0_ctrl_sig; /* ch0 ctrl signal index */
uint32_t ch1_pulse_sig; /* ch1 pulse signal index */
uint32_t ch1_ctrl_sig; /* ch1 ctrl signal index */
uint16_t filter_thres; /* Filter threshold for this PCNT Unit */
};
/* NOTE: we are using Quadrature Encoder in X4 mode on ESP PCNT, then
* instead of using 'pulse_gpio' and 'ctrl_gpio' names, we only use ch0_gpio
* and ch1_gpio names. It avoid confusion, since the same signal that is used
* on pin 'pulse' of CH0 is also connected to 'ctrl' pin of the CH1 and
* and ch1_gpio names. It avoids confusion, since the same signal that is
* used on pin 'pulse' of CH0 is also connected to 'ctrl' pin of the CH1 and
* 'ctrl' pin of CH0 is also connected on 'pulse' pin of CH1.
*/
@ -113,10 +101,9 @@ struct qe_dev_lowerhalf_s
/* ESP driver-specific fields: */
const struct esp_qeconfig_s *config; /* static configuration */
bool inuse; /* True: The lower-half driver is
* in-use */
struct pcnt_dev_t *dev; /* Device handle */
struct cap_lowerhalf_s *pcnt; /* Device handle */
int pcnt_num; /* Pulse Counter (PCNT) unit number */
bool inuse; /* True: The lower-half driver is in-use */
volatile int32_t position; /* The current position offset */
spinlock_t lock; /* Device specific lock. */
};
@ -125,12 +112,6 @@ struct qe_dev_lowerhalf_s
* Private Function Prototypes
****************************************************************************/
/* Interrupt handling */
#if 0 /* FIXME: To be implemented */
static int esp_interrupt(int irq, void *context, void *arg);
#endif
/* Lower-half Quadrature Encoder Driver Methods */
static int esp_setup(struct qe_lowerhalf_s *lower);
@ -163,90 +144,34 @@ static const struct qe_ops_s g_qecallbacks =
/* Per-pcnt state structures */
#ifdef CONFIG_ESP_PCNT_U0_QE
static const struct esp_qeconfig_s g_pcnt0config =
{
.pcntid = 0,
.ch0_gpio = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN,
.ch1_gpio = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN,
.ch0_pulse_sig = PCNT_SIG_CH0_IN0_IDX,
.ch1_pulse_sig = PCNT_SIG_CH1_IN0_IDX,
.ch0_ctrl_sig = PCNT_CTRL_CH0_IN0_IDX,
.ch1_ctrl_sig = PCNT_CTRL_CH1_IN0_IDX,
.filter_thres = CONFIG_ESP_PCNT_U0_FILTER_THRES,
};
static struct qe_dev_lowerhalf_s g_pcnt0lower =
{
.ops = &g_qecallbacks,
.config = &g_pcnt0config,
.inuse = false,
.dev = PCNT_LL_GET_HW(0),
};
#endif
#ifdef CONFIG_ESP_PCNT_U1_QE
static const struct esp_qeconfig_s g_pcnt1config =
{
.pcntid = 1,
.ch0_gpio = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN,
.ch1_gpio = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN,
.ch0_pulse_sig = PCNT_SIG_CH0_IN1_IDX,
.ch1_pulse_sig = PCNT_SIG_CH1_IN1_IDX,
.ch0_ctrl_sig = PCNT_CTRL_CH0_IN1_IDX,
.ch1_ctrl_sig = PCNT_CTRL_CH1_IN1_IDX,
.filter_thres = CONFIG_ESP_PCNT_U1_FILTER_THRES,
};
static struct qe_dev_lowerhalf_s g_pcnt1lower =
{
.ops = &g_qecallbacks,
.config = &g_pcnt1config,
.inuse = false,
.dev = PCNT_LL_GET_HW(0),
};
#endif
#ifdef CONFIG_ESP_PCNT_U2_QE
static const struct esp_qeconfig_s g_pcnt2config =
{
.pcntid = 2,
.ch0_gpio = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN,
.ch1_gpio = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN,
.ch0_pulse_sig = PCNT_SIG_CH0_IN2_IDX,
.ch1_pulse_sig = PCNT_SIG_CH1_IN2_IDX,
.ch0_ctrl_sig = PCNT_CTRL_CH0_IN2_IDX,
.ch1_ctrl_sig = PCNT_CTRL_CH1_IN2_IDX,
.filter_thres = CONFIG_ESP_PCNT_U2_FILTER_THRES,
};
static struct qe_dev_lowerhalf_s g_pcnt2lower =
{
.ops = &g_qecallbacks,
.config = &g_pcnt2config,
.inuse = false,
.dev = PCNT_LL_GET_HW(0),
};
#endif
#ifdef CONFIG_ESP_PCNT_U3_QE
static const struct esp_qeconfig_s g_pcnt3config =
{
.pcntid = 3,
.ch0_gpio = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN,
.ch1_gpio = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN,
.ch0_pulse_sig = PCNT_SIG_CH0_IN3_IDX,
.ch1_pulse_sig = PCNT_SIG_CH1_IN3_IDX,
.ch0_ctrl_sig = PCNT_CTRL_CH0_IN3_IDX,
.ch1_ctrl_sig = PCNT_CTRL_CH1_IN3_IDX,
.filter_thres = CONFIG_ESP_PCNT_U3_FILTER_THRES,
};
static struct qe_dev_lowerhalf_s g_pcnt3lower =
{
.ops = &g_qecallbacks,
.config = &g_pcnt3config,
.inuse = false,
.dev = PCNT_LL_GET_HW(0),
};
#endif
@ -254,27 +179,6 @@ static struct qe_dev_lowerhalf_s g_pcnt3lower =
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp_interrupt
*
* Description:
* Common timer interrupt handling. NOTE: Only 16-bit timers require timer
* interrupts.
*
****************************************************************************/
#if 0 /* FIXME: To be implemented */
static int esp_interrupt(int irq, void *context, void *arg)
{
struct qe_dev_lowerhalf_s *priv = (struct qe_dev_lowerhalf_s *)arg;
uint16_t regval;
DEBUGASSERT(priv != NULL);
return OK;
}
#endif
/****************************************************************************
* Name: esp_setup
*
@ -306,59 +210,15 @@ static int esp_setup(struct qe_lowerhalf_s *lower)
if (priv->inuse)
{
snerr("ERROR: PCNT%d is in-use\n", priv->config->pcntid);
snerr("ERROR: PCNT%d is in-use\n", priv->pcnt_num);
spin_unlock_irqrestore(&priv->lock, flags);
return -EBUSY;
}
/* Disable interrupts */
pcnt_ll_enable_intr(priv->dev, priv->config->pcntid, false);
/* Disable all events */
pcnt_ll_disable_all_events(priv->dev, priv->config->pcntid);
/* Configure the limits range PCNT_CNT_L_LIM | PCNT_CNT_H_LIM */
pcnt_ll_set_high_limit_value(priv->dev, priv->config->pcntid, INT16_MAX);
pcnt_ll_set_low_limit_value(priv->dev, priv->config->pcntid, INT16_MIN);
/* Setup POS/NEG/LCTRL/HCTRL/FILTER modes */
pcnt_ll_set_glitch_filter_thres(priv->dev,
priv->config->pcntid,
priv->config->filter_thres);
pcnt_ll_enable_glitch_filter(priv->dev,
priv->config->pcntid,
true);
pcnt_ll_set_edge_action(priv->dev,
priv->config->pcntid,
0,
PCNT_CHANNEL_EDGE_ACTION_DECREASE,
PCNT_CHANNEL_EDGE_ACTION_INCREASE);
pcnt_ll_set_level_action(priv->dev,
priv->config->pcntid,
0,
PCNT_CHANNEL_LEVEL_ACTION_KEEP,
PCNT_CHANNEL_LEVEL_ACTION_INVERSE);
pcnt_ll_set_edge_action(priv->dev,
priv->config->pcntid,
1,
PCNT_CHANNEL_EDGE_ACTION_INCREASE,
PCNT_CHANNEL_EDGE_ACTION_DECREASE);
pcnt_ll_set_level_action(priv->dev,
priv->config->pcntid,
1,
PCNT_CHANNEL_LEVEL_ACTION_KEEP,
PCNT_CHANNEL_LEVEL_ACTION_INVERSE);
/* Clear the Reset bit to enable the Pulse Counter */
pcnt_ll_clear_count(priv->dev, priv->config->pcntid);
pcnt_ll_start_count(priv->dev, priv->config->pcntid);
priv->pcnt->ops->ioctl(priv->pcnt, CAPIOC_CLR_CNT, 0);
priv->pcnt->ops->start(priv->pcnt);
/* Mark as being used to prevent double opening of the same unit which
* would reset position
@ -400,11 +260,7 @@ static int esp_shutdown(struct qe_lowerhalf_s *lower)
/* Disable interrupts */
pcnt_ll_enable_intr(priv->dev, priv->config->pcntid, false);
/* Disable all events */
pcnt_ll_disable_all_events(priv->dev, priv->config->pcntid);
priv->pcnt->ops->ioctl(priv->pcnt, SNIOC_DISABLE, 0);
/* Make sure initial position is 0 */
@ -439,13 +295,20 @@ static int esp_position(struct qe_lowerhalf_s *lower, int32_t *pos)
struct qe_dev_lowerhalf_s *priv = (struct qe_dev_lowerhalf_s *)lower;
irqstate_t flags;
int32_t position;
int16_t count;
int count = 0;
int ret = OK;
flags = spin_lock_irqsave(&priv->lock);
position = priv->position;
count = (int16_t)(pcnt_ll_get_count(priv->dev,
priv->config->pcntid) & 0xffff);
ret = (priv->pcnt->ops->ioctl(priv->pcnt,
CAPIOC_PULSES,
(unsigned long)&count) & 0xffff);
if (ret < 0)
{
snerr("ERROR: Failed to get PCNT%d count value \n", priv->pcnt_num);
}
/* Update the position measurement */
@ -496,7 +359,6 @@ static int esp_reset(struct qe_lowerhalf_s *lower)
struct qe_dev_lowerhalf_s *priv = (struct qe_dev_lowerhalf_s *)lower;
irqstate_t flags;
uint32_t regval;
sninfo("Resetting position to zero\n");
@ -506,7 +368,7 @@ static int esp_reset(struct qe_lowerhalf_s *lower)
/* Reset RST bit and clear RST bit to enable counting again */
pcnt_ll_clear_count(priv->dev, priv->config->pcntid);
priv->pcnt->ops->ioctl(priv->pcnt, CAPIOC_CLR_CNT, 0);
priv->position = 0;
@ -572,16 +434,18 @@ static int esp_ioctl(struct qe_lowerhalf_s *lower, int cmd,
* called from board-specific logic.
*
* Input Parameters:
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* pcnt - The PCNT number to used. 'pcnt' must be an element of
* {0,1,2,3}
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* pcnt - Pointer to the pcnt driver struct
* pcnt_num - The PCNT number to used. 'pcnt' must be an element of
* {0,1,2,3}
*
* Returned Value:
* Zero on success; A negated errno value is returned on failure.
*
****************************************************************************/
int esp_qeinitialize(const char *devpath, int pcnt)
int esp_qeinitialize(const char *devpath, struct cap_lowerhalf_s *pcnt,
int pcnt_num)
{
struct qe_dev_lowerhalf_s *priv;
int ret;
@ -590,7 +454,7 @@ int esp_qeinitialize(const char *devpath, int pcnt)
* timer
*/
switch (pcnt)
switch (pcnt_num)
{
#ifdef CONFIG_ESP_PCNT_U0_QE
case 0:
@ -618,12 +482,13 @@ int esp_qeinitialize(const char *devpath, int pcnt)
if (priv == NULL)
{
snerr("ERROR: PCNT%d support not configured\n", pcnt);
snerr("ERROR: PCNT%d support not configured\n", pcnt_num);
return -ENXIO;
}
/* Register the upper-half driver */
priv->pcnt = pcnt;
ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv);
if (ret < 0)
{
@ -631,27 +496,7 @@ int esp_qeinitialize(const char *devpath, int pcnt)
return ret;
}
/* Configure GPIO pins as Input with Pull-Up enabled */
esp_configgpio(priv->config->ch0_gpio, INPUT_FUNCTION | PULLUP);
esp_configgpio(priv->config->ch1_gpio, INPUT_FUNCTION | PULLUP);
/* Connect Channel A (ch0_gpio) and Channel B (ch1_gpio) crossed for X4 */
esp_gpio_matrix_in(priv->config->ch0_gpio,
priv->config->ch0_pulse_sig, 0);
esp_gpio_matrix_in(priv->config->ch1_gpio,
priv->config->ch0_ctrl_sig, 0);
esp_gpio_matrix_in(priv->config->ch1_gpio,
priv->config->ch1_pulse_sig, 0);
esp_gpio_matrix_in(priv->config->ch0_gpio,
priv->config->ch1_ctrl_sig, 0);
/* Enable the PCNT Clock and Reset the peripheral */
periph_module_enable(PERIPH_PCNT_MODULE);
periph_module_reset(PERIPH_PCNT_MODULE);
priv->pcnt_num = pcnt_num;
return OK;
}

15
arch/risc-v/src/common/espressif/esp_qencoder.h
View file

@ -64,21 +64,22 @@
* Name: esp_qeinitialize
*
* Description:
* Initialize a quadrature encoder interface. This function must be called
* from board-specific logic..
* Initialize a quadrature encoder interface. This function must be
* called from board-specific logic.
*
* Input Parameters:
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* pcnt - The PCNT number to used. 'tim' must be an element of
* {0,1,2,3}
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* pcnt - Pointer to the pcnt driver struct
* pcnt_num - The PCNT number to used. 'pcnt' must be an element of
* {0,1,2,3}
*
* Returned Value:
* Zero on success; A negated errno value is returned on failure.
*
****************************************************************************/
int esp_qeinitialize(const char *devpath, int pcnt);
int esp_qeinitialize(const char *devpath, struct cap_lowerhalf_s *pcnt,
int pcnt_num);
#endif /* CONFIG_SENSORS_QENCODER */
#endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_QENCODER_H */

2
arch/risc-v/src/esp32c6/hal_esp32c6.mk
View file

@ -131,6 +131,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)lp_timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c
@ -156,6 +157,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)risc
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)lldesc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c

2
arch/risc-v/src/esp32h2/hal_esp32h2.mk
View file

@ -117,6 +117,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)lp_timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c
@ -139,6 +140,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)risc
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)lldesc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c

104
boards/risc-v/esp32c6/common/src/esp_board_qencoder.c → boards/risc-v/esp32c6/common/include/esp_board_pcnt.h
View file

@ -1,7 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c6/common/src/esp_board_qencoder.c
*
* SPDX-License-Identifier: Apache-2.0
* boards/risc-v/esp32c6/common/include/esp_board_pcnt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -20,80 +18,62 @@
*
****************************************************************************/
#ifndef __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_PCNT_H
#define __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_PCNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <stdio.h>
#include <nuttx/sensors/qencoder.h>
#include <arch/board/board.h>
#include "espressif/esp_qencoder.h"
/****************************************************************************
* Public Functions
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: board_qencoder_initialize
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: board_pcnt_initialize
*
* Description:
* Initialize the quadrature encoder driver
* Initialize the pulse counter/quadrature encoder driver
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; errno on failure.
*
****************************************************************************/
int board_qencoder_initialize(void)
{
int ret;
char devpath[12];
int devno = 0;
int board_pcnt_initialize(void);
/* Initialize a quadrature encoder interface. */
#ifdef CONFIG_ESP_PCNT_U0_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, 0);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_ESP_PCNT_U1_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, 1);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_ESP_PCNT_U2_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, 2);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_ESP_PCNT_U3_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, 3);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
#endif
return ret;
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_PCNT_H */

2
boards/risc-v/esp32c6/common/src/Make.defs
View file

@ -71,7 +71,7 @@ ifeq ($(CONFIG_CL_MFRC522),y)
endif
ifeq ($(CONFIG_ESP_PCNT),y)
CSRCS += esp_board_qencoder.c
CSRCS += esp_board_pcnt.c
endif
DEPPATH += --dep-path src

333
boards/risc-v/esp32c6/common/src/esp_board_pcnt.c Normal file
View file

@ -0,0 +1,333 @@
/****************************************************************************
* boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <stdio.h>
#include <arch/board/board.h>
#include <nuttx/timers/capture.h>
#include <nuttx/sensors/sensor.h>
#include "espressif/esp_pcnt.h"
#include "espressif/esp_gpio.h"
#ifdef CONFIG_ESP_PCNT_AS_QE
#include "espressif/esp_qencoder.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define PCNT_HIGH_LIMIT 1000
#define PCNT_LOW_LIMIT -1000
#define PCNT_GLITCH_FILTER(pcnt, thres) pcnt->ops->ioctl(pcnt, \
CAPIOC_FILTER, \
thres) \
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: board_pcnt_init
*
* Description:
* Initialize and register the pulse counter driver
*
* Input Parameters:
* devpath - The full path to the driver to register.
* unit_cfg - PCNT unit configuration
* chan0_cfg - PCNT unit channel 0 configuration
* chan1_cfg - PCNT unit channel 1 configuration
* glitch_threshold - Threshold value for glitch filter in ns
*
* Returned Value:
* Valid PCNT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
static struct cap_lowerhalf_s *board_pcnt_init(
const char *devpath,
struct esp_pcnt_unit_config_s *unit_cfg,
struct esp_pcnt_chan_config_s *chan0_cfg,
struct esp_pcnt_chan_config_s *chan1_cfg,
uint32_t glitch_threshold)
{
struct cap_lowerhalf_s *pcnt;
int chan0;
int chan1;
int ret;
pcnt = esp_pcnt_new_unit(unit_cfg);
if (!pcnt)
{
syslog(LOG_ERR, "Failed to create unit!\n");
return NULL;
}
chan0 = esp_pcnt_new_channel(pcnt, chan0_cfg);
if (chan0 == ERROR)
{
syslog(LOG_ERR, "Failed to create channel!\n");
esp_pcnt_del_unit(pcnt);
return NULL;
}
#ifdef CONFIG_ESP_PCNT_TEST_MODE
esp_pcnt_channel_set_edge_action(chan0, ESP_PCNT_CHAN_EDGE_ACTION_HOLD,
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE);
esp_pcnt_channel_set_level_action(chan0, ESP_PCNT_CHAN_LEVEL_ACTION_KEEP,
ESP_PCNT_CHAN_LEVEL_ACTION_KEEP);
#else
esp_pcnt_channel_set_edge_action(chan0, ESP_PCNT_CHAN_EDGE_ACTION_DECREASE,
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE);
esp_pcnt_channel_set_level_action(chan0, ESP_PCNT_CHAN_LEVEL_ACTION_KEEP,
ESP_PCNT_CHAN_LEVEL_ACTION_INVERSE);
#endif
if (chan1_cfg)
{
chan1 = esp_pcnt_new_channel(pcnt, chan1_cfg);
if (chan1 == ERROR)
{
syslog(LOG_ERR, "Failed to create channel!\n");
esp_pcnt_del_channel(chan0);
esp_pcnt_del_unit(pcnt);
return NULL;
}
esp_pcnt_channel_set_edge_action(chan1,
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE,
ESP_PCNT_CHAN_EDGE_ACTION_DECREASE);
esp_pcnt_channel_set_level_action(chan1,
ESP_PCNT_CHAN_LEVEL_ACTION_KEEP,
ESP_PCNT_CHAN_LEVEL_ACTION_INVERSE);
}
PCNT_GLITCH_FILTER(pcnt, glitch_threshold);
ret = cap_register(devpath, pcnt);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Error registering PCNT!\n");
esp_pcnt_del_channel(chan0);
if (chan1_cfg)
{
esp_pcnt_del_channel(chan1);
}
esp_pcnt_del_unit(pcnt);
return NULL;
}
return pcnt;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_pcnt_initialize
*
* Description:
* Initialize the pulse counter/quadrature encoder driver
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; errno on failure.
*
****************************************************************************/
int board_pcnt_initialize(void)
{
struct cap_lowerhalf_s *pcnt;
int ret = OK;
int glitch_threshold = 0;
#ifdef CONFIG_ESP_PCNT_AS_QE
char devpath[12];
int devno = 0;
#endif
struct esp_pcnt_unit_config_s unit_cfg =
{
.high_limit = PCNT_HIGH_LIMIT,
.low_limit = PCNT_LOW_LIMIT,
.accum_count = false,
};
struct esp_pcnt_chan_config_s chan0_cfg =
{
0
};
struct esp_pcnt_chan_config_s chan1_cfg =
{
0
};
#ifdef CONFIG_ESP_PCNT_U0
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
#ifdef CONFIG_ESP_PCNT_TEST_MODE
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U0_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt0", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U0_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 0);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
#ifdef CONFIG_ESP_PCNT_U1
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U1_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt1", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U1_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 1);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
#ifdef CONFIG_ESP_PCNT_U2
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U2_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt2", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U2_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 2);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
#ifdef CONFIG_ESP_PCNT_U3
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U3_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt3", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U3_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 3);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
return ret;
}

1
boards/risc-v/esp32c6/esp32c6-devkitc/configs/qencoder/defconfig
View file

@ -27,6 +27,7 @@ CONFIG_ESP_PCNT_U0=y
CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN=10
CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN=11
CONFIG_ESP_PCNT_U0_FILTER_EN=y
CONFIG_ESP_PCNT_U0_QE=y
CONFIG_EXAMPLES_QENCODER=y
CONFIG_EXAMPLES_QENCODER_DELAY=1000
CONFIG_EXAMPLES_QENCODER_NSAMPLES=20

12
boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c
View file

@ -102,8 +102,8 @@
# include "esp_board_mcpwm.h"
#endif
#ifdef CONFIG_ESP_PCNT_AS_QE
# include "esp_board_qencoder.h"
#ifdef CONFIG_ESP_PCNT
# include "esp_board_pcnt.h"
#endif
#ifdef CONFIG_SYSTEM_NXDIAG_ESPRESSIF_CHIP_WO_TOOL
@ -391,13 +391,13 @@ int esp_bringup(void)
}
#endif
#ifdef CONFIG_SENSORS_QENCODER
/* Initialize and register the qencoder driver */
#ifdef CONFIG_ESP_PCNT
/* Initialize and register the pcnt/qencoder driver */
ret = board_qencoder_initialize();
ret = board_pcnt_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: board_qencoder_initialize failed: %d\n", ret);
syslog(LOG_ERR, "ERROR: board_pcnt_initialize failed: %d\n", ret);
}
#endif

20
boards/risc-v/esp32c6/common/include/esp_board_qencoder.h → boards/risc-v/esp32h2/common/include/esp_board_pcnt.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c6/common/include/esp_board_qencoder.h
* boards/risc-v/esp32h2/common/include/esp_board_pcnt.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_QENCODER_H
#define __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_QENCODER_H
#ifndef __BOARDS_RISC_V_ESP32H2_COMMON_INCLUDE_ESP_BOARD_PCNT_H
#define __BOARDS_RISC_V_ESP32H2_COMMON_INCLUDE_ESP_BOARD_PCNT_H
/****************************************************************************
* Included Files
@ -58,19 +58,25 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: board_qencoder_initialize
* Name: board_pcnt_initialize
*
* Description:
* Initialize the quadrature encoder driver for the given timer
* Initialize the pulse counter/quadrature encoder driver
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; errno on failure.
*
****************************************************************************/
int board_qencoder_initialize(void);
int board_pcnt_initialize(void);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_QENCODER_H */
#endif /* __BOARDS_RISC_V_ESP32H2_COMMON_INCLUDE_ESP_BOARD_PCNT_H */

4
boards/risc-v/esp32h2/common/src/Make.defs
View file

@ -62,6 +62,10 @@ ifeq ($(CONFIG_ESP_MCPWM),y)
CSRCS += esp_board_mcpwm.c
endif
ifeq ($(CONFIG_ESP_PCNT),y)
CSRCS += esp_board_pcnt.c
endif
DEPPATH += --dep-path src
VPATH += :src
CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src

333
boards/risc-v/esp32h2/common/src/esp_board_pcnt.c Normal file
View file

@ -0,0 +1,333 @@
/****************************************************************************
* boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <stdio.h>
#include <arch/board/board.h>
#include <nuttx/timers/capture.h>
#include <nuttx/sensors/sensor.h>
#include "espressif/esp_pcnt.h"
#include "espressif/esp_gpio.h"
#ifdef CONFIG_ESP_PCNT_AS_QE
#include "espressif/esp_qencoder.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define PCNT_HIGH_LIMIT 1000
#define PCNT_LOW_LIMIT -1000
#define PCNT_GLITCH_FILTER(pcnt, thres) pcnt->ops->ioctl(pcnt, \
CAPIOC_FILTER, \
thres) \
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: board_pcnt_init
*
* Description:
* Initialize and register the pulse counter driver
*
* Input Parameters:
* devpath - The full path to the driver to register.
* unit_cfg - PCNT unit configuration
* chan0_cfg - PCNT unit channel 0 configuration
* chan1_cfg - PCNT unit channel 1 configuration
* glitch_threshold - Threshold value for glitch filter in ns
*
* Returned Value:
* Valid PCNT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
static struct cap_lowerhalf_s *board_pcnt_init(
const char *devpath,
struct esp_pcnt_unit_config_s *unit_cfg,
struct esp_pcnt_chan_config_s *chan0_cfg,
struct esp_pcnt_chan_config_s *chan1_cfg,
uint32_t glitch_threshold)
{
struct cap_lowerhalf_s *pcnt;
int chan0;
int chan1;
int ret;
pcnt = esp_pcnt_new_unit(unit_cfg);
if (!pcnt)
{
syslog(LOG_ERR, "Failed to create unit!\n");
return NULL;
}
chan0 = esp_pcnt_new_channel(pcnt, chan0_cfg);
if (chan0 == ERROR)
{
syslog(LOG_ERR, "Failed to create channel!\n");
esp_pcnt_del_unit(pcnt);
return NULL;
}
#ifdef CONFIG_ESP_PCNT_TEST_MODE
esp_pcnt_channel_set_edge_action(chan0, ESP_PCNT_CHAN_EDGE_ACTION_HOLD,
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE);
esp_pcnt_channel_set_level_action(chan0, ESP_PCNT_CHAN_LEVEL_ACTION_KEEP,
ESP_PCNT_CHAN_LEVEL_ACTION_KEEP);
#else
esp_pcnt_channel_set_edge_action(chan0, ESP_PCNT_CHAN_EDGE_ACTION_DECREASE,
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE);
esp_pcnt_channel_set_level_action(chan0, ESP_PCNT_CHAN_LEVEL_ACTION_KEEP,
ESP_PCNT_CHAN_LEVEL_ACTION_INVERSE);
#endif
if (chan1_cfg)
{
chan1 = esp_pcnt_new_channel(pcnt, chan1_cfg);
if (chan1 == ERROR)
{
syslog(LOG_ERR, "Failed to create channel!\n");
esp_pcnt_del_channel(chan0);
esp_pcnt_del_unit(pcnt);
return NULL;
}
esp_pcnt_channel_set_edge_action(chan1,
ESP_PCNT_CHAN_EDGE_ACTION_INCREASE,
ESP_PCNT_CHAN_EDGE_ACTION_DECREASE);
esp_pcnt_channel_set_level_action(chan1,
ESP_PCNT_CHAN_LEVEL_ACTION_KEEP,
ESP_PCNT_CHAN_LEVEL_ACTION_INVERSE);
}
PCNT_GLITCH_FILTER(pcnt, glitch_threshold);
ret = cap_register(devpath, pcnt);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Error registering PCNT!\n");
esp_pcnt_del_channel(chan0);
if (chan1_cfg)
{
esp_pcnt_del_channel(chan1);
}
esp_pcnt_del_unit(pcnt);
return NULL;
}
return pcnt;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_pcnt_initialize
*
* Description:
* Initialize the pulse counter/quadrature encoder driver
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; errno on failure.
*
****************************************************************************/
int board_pcnt_initialize(void)
{
struct cap_lowerhalf_s *pcnt;
int ret = OK;
int glitch_threshold = 0;
#ifdef CONFIG_ESP_PCNT_AS_QE
char devpath[12];
int devno = 0;
#endif
struct esp_pcnt_unit_config_s unit_cfg =
{
.high_limit = PCNT_HIGH_LIMIT,
.low_limit = PCNT_LOW_LIMIT,
.accum_count = false,
};
struct esp_pcnt_chan_config_s chan0_cfg =
{
0
};
struct esp_pcnt_chan_config_s chan1_cfg =
{
0
};
#ifdef CONFIG_ESP_PCNT_U0
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
#ifdef CONFIG_ESP_PCNT_TEST_MODE
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U0_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt0", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U0_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 0);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
#ifdef CONFIG_ESP_PCNT_U1
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U1_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt1", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U1_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 1);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
#ifdef CONFIG_ESP_PCNT_U2
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U2_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt2", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U2_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 2);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
#ifdef CONFIG_ESP_PCNT_U3
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
glitch_threshold = 0;
#else
glitch_threshold = CONFIG_ESP_PCNT_U3_FILTER_THRES;
#endif
pcnt = board_pcnt_init("/dev/pcnt3", &unit_cfg, &chan0_cfg,
&chan1_cfg, glitch_threshold);
if (!pcnt)
{
syslog(LOG_ERR, "ERROR: pcnt initialize failed: %d\n", ret);
return ERROR;
}
#ifdef CONFIG_ESP_PCNT_U3_QE
snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno++);
ret = esp_qeinitialize(devpath, pcnt, 3);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: esp_qeinitialize failed: %d\n", ret);
return ret;
}
pcnt = NULL;
#endif
#endif
return ret;
}

13
boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c
View file

@ -94,6 +94,11 @@
# include "esp_board_mcpwm.h"
#endif
#ifdef CONFIG_ESP_PCNT
# include "espressif/esp_pcnt.h"
# include "esp_board_pcnt.h"
#endif
#ifdef CONFIG_SYSTEM_NXDIAG_ESPRESSIF_CHIP_WO_TOOL
# include "espressif/esp_nxdiag.h"
#endif
@ -354,6 +359,14 @@ int esp_bringup(void)
}
#endif
#ifdef CONFIG_ESP_PCNT
ret = board_pcnt_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: board_pcnt_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_SYSTEM_NXDIAG_ESPRESSIF_CHIP_WO_TOOL
ret = esp_nxdiag_initialize();
if (ret < 0)