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at32uc3a0: Initial work for SimpleMachines' Mizar32-A

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This commit is contained in:
Raman Gopalan 2024-02-17 22:10:32 +05:30 committed by Xiang Xiao
parent e0b99216b0
commit ef271b8fe2
23 changed files with 1696 additions and 312 deletions
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5
arch/avr/src/at32uc3/Kconfig
View file

@ -10,6 +10,11 @@ choice
prompt "AT32U3 Processor Selection"
default ARCH_CHIP_AT32UC3B0256
config ARCH_CHIP_AT32UC3A0512
bool "AT32UC3A0512"
select ARCH_CHIP_AT32UC3A
select ARCH_CHIP_AT32UC3A0
config ARCH_CHIP_AT32UC3B064
bool "AT32UC3B064"
select ARCH_CHIP_AT32UC3B

32
arch/avr/src/at32uc3/at32uc3_clkinit.c
View file

@ -212,11 +212,13 @@ static inline void up_enableosc1(void)
#ifdef AVR32_CLOCK_PLL0
static inline void up_enablepll0(void)
{
uint32_t regval;
/* Setup PLL0 */
regval = (AVR32_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) |
(AVR32_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) |
(16 << PM_PLL_PLLCOUNT_SHIFT)
(16 << PM_PLL_PLLCOUNT_SHIFT);
/* Select PLL0/1 oscillator */
@ -229,7 +231,7 @@ static inline void up_enablepll0(void)
/* Set PLL0 options */
regval = getreg32(AVR32_PM_PLL0);
regval &= ~PM_PLL_PLLOPT_MASK
regval &= ~PM_PLL_PLLOPT_MASK;
#if AVR32_PLL0_FREQ < 160000000
regval |= PM_PLL_PLLOPT_VCO;
#endif
@ -239,13 +241,13 @@ static inline void up_enablepll0(void)
#if AVR32_PLL0_WBWM != 0
regval |= PM_PLL_PLLOPT_WBWDIS;
#endif
putreg32(regval, AVR32_PM_PLL0)
putreg32(regval, AVR32_PM_PLL0);
/* Enable PLL0 */
regval = getreg32(AVR32_PM_PLL0);
regval |= PM_PLL_PLLEN;
putreg32(regval, AVR32_PM_PLL0)
putreg32(regval, AVR32_PM_PLL0);
/* Wait for PLL0 locked. */
@ -268,7 +270,7 @@ static inline void up_enablepll1(void)
regval = (AVR32_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) |
(AVR32_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) |
(16 << PM_PLL_PLLCOUNT_SHIFT)
(16 << PM_PLL_PLLCOUNT_SHIFT);
/* Select PLL0/1 oscillator */
@ -281,7 +283,7 @@ static inline void up_enablepll1(void)
/* Set PLL1 options */
regval = getreg32(AVR32_PM_PLL1);
regval &= ~PM_PLL_PLLOPT_MASK
regval &= ~PM_PLL_PLLOPT_MASK;
#if AVR32_PLL1_FREQ < 160000000
regval |= PM_PLL_PLLOPT_VCO;
#endif
@ -291,13 +293,13 @@ static inline void up_enablepll1(void)
#if AVR32_PLL1_WBWM != 0
regval |= PM_PLL_PLLOPT_WBWDIS;
#endif
putreg32(regval, AVR32_PM_PLL1)
putreg32(regval, AVR32_PM_PLL1);
/* Enable PLL1 */
regval = getreg32(AVR32_PM_PLL1);
regval |= PM_PLL_PLLEN;
putreg32(regval, AVR32_PM_PLL1)
putreg32(regval, AVR32_PM_PLL1);
/* Wait for PLL1 locked. */
@ -319,22 +321,22 @@ static inline void up_clksel(void)
#if AVR32_CKSEL_CPUDIV != 0
regval |= PM_CKSEL_CPUDIV;
regval |= (AVR32_CKSEL_CPUDIV << PM_CKSEL_CPUSEL_SHIFT)
regval |= (AVR32_CKSEL_CPUDIV << PM_CKSEL_CPUSEL_SHIFT);
#endif
#if AVR32_CKSEL_HSBDIV != 0
regval |= PM_CKSEL_HSBDIV;
regval |= (AVR32_CKSEL_HSBDIV << PM_CKSEL_HSBSEL_SHIFT)
regval |= (AVR32_CKSEL_HSBDIV << PM_CKSEL_HSBSEL_SHIFT);
#endif
#if AVR32_CKSEL_PBADIV != 0
regval |= PM_CKSEL_PBADIV;
regval |= (AVR32_CKSEL_PBADIV << PM_CKSEL_PBASEL_SHIFT)
regval |= (AVR32_CKSEL_PBADIV << PM_CKSEL_PBASEL_SHIFT);
#endif
#if AVR32_CKSEL_PBBDIV != 0
regval |= PM_CKSEL_PBBDIV;
regval |= (AVR32_CKSEL_PBBDIV << PM_CKSEL_PBBSEL_SHIFT)
regval |= (AVR32_CKSEL_PBBDIV << PM_CKSEL_PBBSEL_SHIFT);
#endif
putreg32(regval, AVR32_PM_CKSEL);
@ -411,13 +413,13 @@ static inline void up_usbclock(void)
u_avr32_pm_gcctrl.GCCTRL.diven = diven;
u_avr32_pm_gcctrl.GCCTRL.div = div;
#endif
putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB));
/* Enable USB GCLK */
regval = getreg32(AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
regval = getreg32(AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB));
regval |= PM_GCCTRL_CEN;
putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB));
}
#endif

6
arch/avr/src/at32uc3/at32uc3_gpio.c
View file

@ -66,13 +66,13 @@ static uint32_t g_portmap[AVR32_NGPIO_PORTS] =
AVR32_GPIO0_BASE
#endif
#if AVR32_NGPIO > 32
, AVR32_GPIO1_BASE,
, AVR32_GPIO1_BASE
#endif
#if AVR32_NGPIO > 64
, AVR32_GPIO2_BASE,
, AVR32_GPIO2_BASE
#endif
#if AVR32_NGPIO > 96
, AVR32_GPIO3_BASE,
, AVR32_GPIO3_BASE
#endif
#if AVR32_NGPIO > 128
, AVR32_GPIO4_BASE,

2
arch/avr/src/at32uc3/at32uc3_lowconsole.c
View file

@ -348,7 +348,7 @@ void up_consoleinit(void)
#endif
/* Enable selected clocks (and disabled unselected clocks) */
/* Enable selected clocks (and disable unselected clocks) */
regval = getreg32(AVR32_PM_PBAMASK);
regval &= ~(PM_PBAMASK_USART0 | PM_PBAMASK_USART1 | PM_PBAMASK_USART2);

292
arch/avr/src/at32uc3/at32uc3_pm.h
View file

@ -27,294 +27,18 @@
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_AT32UC3B)
# include "at32uc3b_pm.h"
#elif defined(CONFIG_ARCH_CHIP_AT32UC3A)
# include "at32uc3a_pm.h"
#else
# error "Unknown AVR32 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define AVR32_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */
#define AVR32_PM_CKSEL_OFFSET 0x0004 /* Clock Select Register */
#define AVR32_PM_CPUMASK_OFFSET 0x0008 /* CPU Mask Register */
#define AVR32_PM_HSBMASK_OFFSET 0x000c /* HSB Mask Register */
#define AVR32_PM_PBAMASK_OFFSET 0x0010 /* PBA Mask Register */
#define AVR32_PM_PBBMASK_OFFSET 0x0014 /* PBB Mask Register */
#define AVR32_PM_PLL0_OFFSET 0x0020 /* PLL0 Control Register */
#define AVR32_PM_PLL1_OFFSET 0x0024 /* PLL1 Control Register */
#define AVR32_PM_OSCCTRL0_OFFSET 0x0028 /* Oscillator 0 Control Register */
#define AVR32_PM_OSCCTRL1_OFFSET 0x002c /* Oscillator 1 Control Register */
#define AVR32_PM_OSCCTRL32_OFFSET 0x0030 /* Oscillator 32 Control Register */
#define AVR32_PM_IER_OFFSET 0x0040 /* Interrupt Enable Register */
#define AVR32_PM_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
#define AVR32_PM_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
#define AVR32_PM_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define AVR32_PM_ICR_OFFSET 0x0050 /* Interrupt Clear Register */
#define AVR32_PM_POSCSR_OFFSET 0x0054 /* Power and Oscillators Status Register */
#define AVR32_PM_GCCTRL_OFFSET(n) (0x0060+((n)<<2)) /* 0x0060-0x070 Generic Clock Control Register */
#define AVR32_PM_RCCR_OFFSET 0x00c0 /* RC Oscillator Calibration Register */
#define AVR32_PM_BGCR_OFFSET 0x00c4 /* Bandgap Calibration Register */
#define AVR32_PM_VREGCR_OFFSET 0x00c8 /* Linear Regulator Calibration Register */
#define AVR32_PM_BOD_OFFSET 0x00d0 /* BOD Level Register BOD Read/Write */
#define AVR32_PM_RCAUSE_OFFSET 0x0140 /* Reset Cause Register */
#define AVR32_PM_AWEN_OFFSET 0x0144 /* Asynchronous Wake Up Enable Register */
#define AVR32_PM_GPLP0_OFFSET 0x0200 /* General Purpose Low-Power Register 0 */
#define AVR32_PM_GPLP1_OFFSET 0x0204 /* General Purpose Low-Power Register 1 */
/* Register Addresses *******************************************************/
#define AVR32_PM_MCCTRL (AVR32_PM_BASE+AVR32_PM_MCCTRL_OFFSET)
#define AVR32_PM_CKSEL (AVR32_PM_BASE+AVR32_PM_CKSEL_OFFSET)
#define AVR32_PM_CPUMASK (AVR32_PM_BASE+AVR32_PM_CPUMASK_OFFSET)
#define AVR32_PM_HSBMASK (AVR32_PM_BASE+AVR32_PM_HSBMASK_OFFSET)
#define AVR32_PM_PBAMASK (AVR32_PM_BASE+AVR32_PM_PBAMASK_OFFSET)
#define AVR32_PM_PBBMASK (AVR32_PM_BASE+AVR32_PM_PBBMASK_OFFSET)
#define AVR32_PM_PLL0 (AVR32_PM_BASE+AVR32_PM_PLL0_OFFSET)
#define AVR32_PM_PLL1 (AVR32_PM_BASE+AVR32_PM_PLL1_OFFSET)
#define AVR32_PM_OSCCTRL0 (AVR32_PM_BASE+AVR32_PM_OSCCTRL0_OFFSET)
#define AVR32_PM_OSCCTRL1 (AVR32_PM_BASE+AVR32_PM_OSCCTRL1_OFFSET)
#define AVR32_PM_OSCCTRL32 (AVR32_PM_BASE+AVR32_PM_OSCCTRL32_OFFSET)
#define AVR32_PM_IER (AVR32_PM_BASE+AVR32_PM_IER_OFFSET)
#define AVR32_PM_IDR (AVR32_PM_BASE+AVR32_PM_IDR_OFFSET)
#define AVR32_PM_IMR (AVR32_PM_BASE+AVR32_PM_IMR_OFFSET)
#define AVR32_PM_ISR (AVR32_PM_BASE+AVR32_PM_ISR_OFFSET)
#define AVR32_PM_ICR (AVR32_PM_BASE+AVR32_PM_ICR_OFFSET)
#define AVR32_PM_POSCSR (AVR32_PM_BASE+AVR32_PM_POSCSR_OFFSET)
#define AVR32_PM_GCCTRL(n) (AVR32_PM_BASE+AVR32_PM_GCCTRL_OFFSET(n))
#define AVR32_PM_RCCR (AVR32_PM_BASE+AVR32_PM_RCCR_OFFSET)
#define AVR32_PM_BGCR (AVR32_PM_BASE+AVR32_PM_BGCR_OFFSET)
#define AVR32_PM_VREGCR (AVR32_PM_BASE+AVR32_PM_VREGCR_OFFSET)
#define AVR32_PM_BOD (AVR32_PM_BASE+AVR32_PM_BOD_OFFSET)
#define AVR32_PM_RCAUSE (AVR32_PM_BASE+AVR32_PM_RCAUSE_OFFSET)
#define AVR32_PM_AWEN (AVR32_PM_BASE+AVR32_PM_AWEN_OFFSET)
#define AVR32_PM_GPLP0 (AVR32_PM_BASE+AVR32_PM_GPLP0_OFFSET)
#define AVR32_PM_GPLP1 (AVR32_PM_BASE+AVR32_PM_GPLP1_OFFSET)
/* Register Bit-field Definitions *******************************************/
/* Main Clock Control Register Bit-field Definitions */
#define PM_MCCTRL_MCSEL_SHIFT (0) /* Bits 0-1: Main Clock Select */
#define PM_MCCTRL_MCSEL_MASK (3 << PM_MCCTRL_MCSEL_SHIFT)
# define PM_MCCTRL_MCSEL_SLOW (0 << PM_MCCTRL_MCSEL_SHIFT) /* slow clock is source */
# define PM_MCCTRL_MCSEL_OSC0 (1 << PM_MCCTRL_MCSEL_SHIFT) /* Oscillator 0 is source */
# define PM_MCCTRL_MCSEL_PLL0 (2 << PM_MCCTRL_MCSEL_SHIFT) /* PLL0 is source */
#define PM_MCCTRL_OSC0EN (1 << 2) /* Bit 2: Oscillator 0 Enable */
#define PM_MCCTRL_OSC1EN (1 << 3) /* Bit 3: Oscillator 1 Enable */
/* Clock Select Register Bit-field Definitions */
#define PM_CKSEL_CPUSEL_SHIFT (0) /* Bits 0-2: CPU Clock Select */
#define PM_CKSEL_CPUSEL_MASK (7 << PM_CKSEL_CPUSEL_SHIFT)
#define PM_CKSEL_CPUDIV (1 << 7) /* Bit 7: CPU Division */
#define PM_CKSEL_HSBSEL_SHIFT (8) /* Bits 8-10: HSB Clock Select */
#define PM_CKSEL_HSBSEL_MASK (7 << PM_CKSEL_HSBSEL_SHIFT)
#define PM_CKSEL_HSBDIV (1 << 15) /* Bit 15: HSB Division */
#define PM_CKSEL_PBASEL_SHIFT (16) /* Bits 16-28: BA Clock Select */
#define PM_CKSEL_PBASEL_MASK (7 << PM_CKSEL_PBASEL_SHIFT)
#define PM_CKSEL_PBADIV (1 << 23) /* Bit 23: PBA Division */
#define PM_CKSEL_PBBSEL_SHIFT (24) /* Bits 24-26: PBB Clock Select */
#define PM_CKSEL_PBBSEL_MASK (7 << PM_CKSEL_PBBSEL_SHIFT)
#define PM_CKSEL_PBBDIV (1 << 31) /* Bit 31: PBB Division */
/* CPU Mask Register Bit-field Definitions */
#define PM_CPUMASK_OCD (1 << 1) /* Bit 1: OCD */
/* HSB Mask Register Bit-field Definitions */
#define PM_HSBMASK_FLASHC (1 << 0) /* Bit 0: FLASHC */
#define PM_HSBMASK_PBA (1 << 1) /* Bit 1: PBA bridge */
#define PM_HSBMASK_PBB (1 << 2) /* Bit 2: PBB bridge */
#define PM_HSBMASK_USBB (1 << 3) /* Bit 3: USBB */
#define PM_HSBMASK_PDCA (1 << 4) /* Bit 4: PDCA */
/* PBA Mask Register Bit-field Definitions */
#define PM_PBAMASK_INTC (1 << 0) /* Bit 0: INTC */
#define PM_PBAMASK_GPIO (1 << 1) /* Bit 1: GPIO */
#define PM_PBAMASK_PDCA (1 << 2) /* Bit 2: PDCA */
#define PM_PBAMASK_PMRTCEIC (1 << 3) /* Bit 3: PM/RTC/EIC */
#define PM_PBAMASK_ADC (1 << 4) /* Bit 4: ADC */
#define PM_PBAMASK_SPI (1 << 5) /* Bit 5: SPI */
#define PM_PBAMASK_TWI (1 << 6) /* Bit 6: TWI */
#define PM_PBAMASK_USART0 (1 << 7) /* Bit 7: USART0 */
#define PM_PBAMASK_USART1 (1 << 8) /* Bit 8: USART1 */
#define PM_PBAMASK_USART2 (1 << 9) /* Bit 9: USART2 */
#define PM_PBAMASK_PWM (1 << 10) /* Bit 10: PWM */
#define PM_PBAMASK_SSC (1 << 11) /* Bit 11: SSC */
#define PM_PBAMASK_TC (1 << 12) /* Bit 12: TC */
#define PM_PBAMASK_ABDAC (1 << 13) /* Bit 13: ABDAC */
/* PBB Mask Register Bit-field Definitions */
#define PM_PBBMASK_HMATRIX (1 << 0) /* Bit 0: HMATRIX */
#define PM_PBBMASK_USBB (1 << 2) /* Bit 2: USBB */
#define PM_PBBMASK_FLASHC (1 << 3) /* Bit 3: FLASHC */
/* PLL0/1 Control Register Bit-field Definitions */
#define PM_PLL_PLLEN (1 << 0) /* Bit 0: PLL Enable */
#define PM_PLL_PLLOSC (1 << 1) /* Bit 1: PLL Oscillator Select */
#define PM_PLL_PLLOPT_SHIFT (2) /* Bits 2-3: PLL Option */
#define PM_PLL_PLLOPT_MASK (7 << PM_PLL_PLLOPT_SHIFT)
# define PM_PLL_PLLOPT_VCO (1 << PM_PLL_PLLOPT_SHIFT) /* Select the VCO frequency range */
# define PM_PLL_PLLOPT_XTRADIV (2 << PM_PLL_PLLOPT_SHIFT) /* Enable the extra output divider */
# define PM_PLL_PLLOPT_WBWDIS (4 << PM_PLL_PLLOPT_SHIFT) /* Disable the Wide-Bandwidth mode */
#define PM_PLL_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */
#define PM_PLL_PLLDIV_MASK (15 << PM_PLL_PLLDIV_SHIFT)
#define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */
#define PM_PLL_PLLMUL_MASK (15 << PM_PLL_PLLMUL_SHIFT)
#define PM_PLL_PLLCOUNT_SHIFT (24) /* Bits 24-29: PLL Count */
#define PM_PLL_PLLCOUNT_MASK (0x3f << PM_PLL_PLLCOUNT_SHIFT)
/* Oscillator 0/1 Control Register Bit-field Definitions */
#define PM_OSCCTRL_MODE_SHIFT (0) /* Bits 0-2: Oscillator Mode */
#define PM_OSCCTRL_MODE_MASK (7 << PM_OSCCTRL_MODE_SHIFT)
# define PM_OSCCTRL_MODE_EXT (0 << PM_OSCCTRL_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL_MODE_XTALP9 (4 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.4-0.9MHz */
# define PM_OSCCTRL_MODE_XTAL3 (5 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.9-3.0MHz */
# define PM_OSCCTRL_MODE_XTAL8 (6 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 3.0-8.0MHz */
# define PM_OSCCTRL_MODE_XTALHI (7 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN above 8.0MHz */
#define PM_OSCCTRL_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator Startup Time */
#define PM_OSCCTRL_STARTUP_MASK (7 << PM_OSCCTRL_STARTUP_SHIFT)
# define PM_OSCCTRL_STARTUP_0 (0 << PM_OSCCTRL_STARTUP_SHIFT) /* Num RCOsc cycles */
# define PM_OSCCTRL_STARTUP_64 (1 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_128 (2 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_2K (3 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_4K (4 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_8K (5 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_16K (6 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
/* Oscillator 32 Control Register Bit-field Definitions */
#define PM_OSCCTRL32_EN (1 << 0) /* Bit 0: Enable the 32KHz oscillator */
#define PM_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */
#define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT)
# define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */
#define PM_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Startup Time */
#define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT)
# define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */
# define PM_OSCCTRL32_STARTUP_128 (1 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_8K (2 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_16K (3 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_64K (4 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_128K (5 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_512K (6 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
/* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */
#define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
#define PM_INT_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
#define PM_INT_CKRDY (1 << 5) /* Bit 5: Clock Ready */
#define PM_INT_MSKRDY (1 << 6) /* Bit 6: Mask Ready */
#define PM_INT_OSC0RDY (1 << 7) /* Bit 7: Oscillator 0 Ready */
#define PM_INT_OSC1RDY (1 << 8) /* Bit 8: Oscillator 1 Ready */
#define PM_INT_OSC32RDY (1 << 9) /* Bit 9: 32 KHz oscillator Ready */
#define PM_INT_BODDET (1 << 16) /* Bit 16: Brown out detection */
/* Power and Oscillators Status Register Bit-field Definitions */
#define PM_POSCSR_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
#define PM_POSCSR_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
#define PM_POSCSR_WAKE (1 << 2) /* Bit 1: PLL1 locked */
#define PM_POSCSR_CKRDY (1 << 5) /* Bit 5: Clock Ready */
#define PM_POSCSR_MSKRDY (1 << 6) /* Bit 6: Mask Ready */
#define PM_POSCSR_OSC0RDY (1 << 7) /* Bit 7: Oscillator 0 Ready */
#define PM_POSCSR_OSC1RDY (1 << 8) /* Bit 8: Oscillator 1 Ready */
#define PM_POSCSR_OSC32RDY (1 << 9) /* Bit 9: 32 KHz oscillator Ready */
#define PM_POSCSR_BODDET (1 << 16) /* Bit 16: Brown out detection */
/* 0x0060-0x070 Generic Clock Control Register Bit-field Definitions */
#define PM_GCCTRL_OSCSEL (1 << 0) /* Bit 0: Oscillator Select */
#define PM_GCCTRL_PLLSEL (1 << 1) /* Bit 1: PLL Select */
#define PM_GCCTRL_CEN (1 << 2) /* Bit 2: Clock Enable */
#define PM_GCCTRL_DIVEN (1 << 4) /* Bit 4: Divide Enable */
#define PM_GCCTRL_DIV_SHIFT (8) /* Bits 8-15: Division Factor */
#define PM_GCCTRL_DIV_MASK (0xff << PM_GCCTRL_DIV_SHIFT)
/* RC Oscillator Calibration Register Bit-field Definitions */
#define PM_RCCR_CALIB_SHIFT (0) /* Bits 0-9: Calibration Value */
#define PM_RCCR_CALIB_MASK (0x3ff << PM_RCCR_CALIB_SHIFT)
#define PM_RCCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_RCCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_RCCR_KEY_MASK (0xff << PM_RCCR_KEY_SHIFT)
/* Bandgap Calibration Register Bit-field Definitions */
#define PM_BGCR_CALIB_SHIFT (0) /* Bits 0-3: Calibration Value */
#define PM_BGCR_CALIB_MASK (7 << PM_BGCR_CALIB_SHIFT)
#define PM_BGCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_BGCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BGCR_KEY_MASK (0xff << PM_BGCR_KEY_SHIFT)
/* Linear Regulator Calibration Register Bit-field Definitions */
#define PM_VREGCR_CALIB_SHIFT (0) /* Bits 0-3: Calibration Value */
#define PM_VREGCR_CALIB_MASK (7 << PM_VREGCR_CALIB_SHIFT)
#define PM_VREGCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_VREGCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_VREGCR_KEY_MASK (0xff << PM_VREGCR_KEY_SHIFT)
/* BOD Level Register BOD Read/Write Bit-field Definitions */
#define PM_BOD_LEVEL_SHIFT (0) /* Bits 0-5: BOD Level */
#define PM_BOD_LEVEL_MASK (0x3f << PM_BOD_LEVEL_SHIFT)
#define PM_BOD_HYST (1 << 6) /* Bit 6: BOD Hysteresis */
#define PM_BOD_CTRL_SHIFT (8) /* Bits 8-9: BOD Control */
#define PM_BOD_CTRL_MASK (3 << PM_BOD_CTRL_SHIFT)
# define PM_BOD_CTRL_OFF (xxx << PM_BOD_CTRL_SHIFT) /* BOD is off */
# define PM_BOD_CTRL_RESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/can reset */
# define PM_BOD_CTRL_NORESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/cannot reset */
#define PM_BOD_FCD (1 << 16) /* Bit 16: BOD Fuse calibration done */
#define PM_BOD_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BOD_KEY_MASK (0xff << PM_BOD_KEY_SHIFT)
/* Reset Cause Register */
#define PM_RCAUSE_POR (1 << 0) /* Bit 0: Power-on Reset */
#define PM_RCAUSE_BOD (1 << 1) /* Bit 1: Brown-out Reset */
#define PM_RCAUSE_EXT (1 << 2) /* Bit 2: External Reset Pin */
#define PM_RCAUSE_WDT (1 << 3) /* Bit 3: Watchdog Reset */
#define PM_RCAUSE_JTAG (1 << 4) /* Bit 4: JTAG reset */
#define PM_RCAUSE_SLEEP (1 << 6) /* Bit 6: Sleep */
#define PM_RCAUSE_CPUERR (1 << 7) /* Bit 7: CPU Error */
#define PM_RCAUSE_OCDRST (1 << 8) /* Bit 8: OCD Reset */
/* Asynchronous Wake Up Enable Register Bit-field Definitions */
#define PM_AWEN_USBWAKEN (1 << 0) /* Bit 0: USB Wake Up Enable */
/* General Purpose Low-Power Register 0/1 Bit-field Definitions */
/* These registers contain a 32-bit value with no smaller bit-field */
/* GCLK Allocation **********************************************************/
#define AVR32_PM_GCLK0 (0) /* GCLK0 pin */
#define AVR32_PM_GCLK1 (1) /* GCLK2 pin */
#define AVR32_PM_GCLK2 (2) /* GCLK2 pin */
#define AVR32_PM_GCLK_USBB (3) /* USBB */
#define AVR32_PM_GCLK_ABDAC (4) /* ABDAC */
/****************************************************************************
* Public Types
****************************************************************************/

5
arch/avr/src/at32uc3/at32uc3a_pinmux.h
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@ -31,7 +31,8 @@
* Pre-processor Definitions
****************************************************************************/
#warning "Not Implemented"
#define PINMUX_USART1_RXD_0 (GPIO_PERIPH | GPIO_FUNCA | GPIO_PORTA | 5)
#define PINMUX_USART1_TXD_0 (GPIO_PERIPH | GPIO_FUNCA | GPIO_PORTA | 6)
/****************************************************************************
* Public Types
@ -45,4 +46,4 @@
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PINMUX_H */
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3A_PINMUX_H */

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@ -0,0 +1,337 @@
/****************************************************************************
* arch/avr/src/at32uc3/at32uc3a_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3A_PM_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3A_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define AVR32_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */
#define AVR32_PM_CKSEL_OFFSET 0x0004 /* Clock Select Register */
#define AVR32_PM_CPUMASK_OFFSET 0x0008 /* CPU Mask Register */
#define AVR32_PM_HSBMASK_OFFSET 0x000c /* HSB Mask Register */
#define AVR32_PM_PBAMASK_OFFSET 0x0010 /* PBA Mask Register */
#define AVR32_PM_PBBMASK_OFFSET 0x0014 /* PBB Mask Register */
#define AVR32_PM_PLL0_OFFSET 0x0020 /* PLL0 Control Register */
#define AVR32_PM_PLL1_OFFSET 0x0024 /* PLL1 Control Register */
#define AVR32_PM_OSCCTRL0_OFFSET 0x0028 /* Oscillator 0 Control Register */
#define AVR32_PM_OSCCTRL1_OFFSET 0x002c /* Oscillator 1 Control Register */
#define AVR32_PM_OSCCTRL32_OFFSET 0x0030 /* Oscillator 32 Control Register */
#define AVR32_PM_IER_OFFSET 0x0040 /* Interrupt Enable Register */
#define AVR32_PM_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
#define AVR32_PM_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
#define AVR32_PM_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define AVR32_PM_ICR_OFFSET 0x0050 /* Interrupt Clear Register */
#define AVR32_PM_POSCSR_OFFSET 0x0054 /* Power and Oscillators Status Register */
#define AVR32_PM_GCCTRL_OFFSET(n) (0x0060+((n)<<2)) /* 0x0060-0x070 Generic Clock Control Register */
#define AVR32_PM_RCCR_OFFSET 0x00c0 /* RC Oscillator Calibration Register */
#define AVR32_PM_BGCR_OFFSET 0x00c4 /* Bandgap Calibration Register */
#define AVR32_PM_VREGCR_OFFSET 0x00c8 /* Linear Regulator Calibration Register */
#define AVR32_PM_BOD_OFFSET 0x00d0 /* BOD Level Register BOD Read/Write */
#define AVR32_PM_RCAUSE_OFFSET 0x0140 /* Reset Cause Register */
#define AVR32_PM_AWEN_OFFSET 0x0144 /* Asynchronous Wake Up Enable Register */
#define AVR32_PM_GPLP0_OFFSET 0x0200 /* General Purpose Low-Power Register 0 */
#define AVR32_PM_GPLP1_OFFSET 0x0204 /* General Purpose Low-Power Register 1 */
/* Register Addresses *******************************************************/
#define AVR32_PM_MCCTRL (AVR32_PM_BASE+AVR32_PM_MCCTRL_OFFSET)
#define AVR32_PM_CKSEL (AVR32_PM_BASE+AVR32_PM_CKSEL_OFFSET)
#define AVR32_PM_CPUMASK (AVR32_PM_BASE+AVR32_PM_CPUMASK_OFFSET)
#define AVR32_PM_HSBMASK (AVR32_PM_BASE+AVR32_PM_HSBMASK_OFFSET)
#define AVR32_PM_PBAMASK (AVR32_PM_BASE+AVR32_PM_PBAMASK_OFFSET)
#define AVR32_PM_PBBMASK (AVR32_PM_BASE+AVR32_PM_PBBMASK_OFFSET)
#define AVR32_PM_PLL0 (AVR32_PM_BASE+AVR32_PM_PLL0_OFFSET)
#define AVR32_PM_PLL1 (AVR32_PM_BASE+AVR32_PM_PLL1_OFFSET)
#define AVR32_PM_OSCCTRL0 (AVR32_PM_BASE+AVR32_PM_OSCCTRL0_OFFSET)
#define AVR32_PM_OSCCTRL1 (AVR32_PM_BASE+AVR32_PM_OSCCTRL1_OFFSET)
#define AVR32_PM_OSCCTRL32 (AVR32_PM_BASE+AVR32_PM_OSCCTRL32_OFFSET)
#define AVR32_PM_IER (AVR32_PM_BASE+AVR32_PM_IER_OFFSET)
#define AVR32_PM_IDR (AVR32_PM_BASE+AVR32_PM_IDR_OFFSET)
#define AVR32_PM_IMR (AVR32_PM_BASE+AVR32_PM_IMR_OFFSET)
#define AVR32_PM_ISR (AVR32_PM_BASE+AVR32_PM_ISR_OFFSET)
#define AVR32_PM_ICR (AVR32_PM_BASE+AVR32_PM_ICR_OFFSET)
#define AVR32_PM_POSCSR (AVR32_PM_BASE+AVR32_PM_POSCSR_OFFSET)
#define AVR32_PM_GCCTRL(n) (AVR32_PM_BASE+AVR32_PM_GCCTRL_OFFSET(n))
#define AVR32_PM_RCCR (AVR32_PM_BASE+AVR32_PM_RCCR_OFFSET)
#define AVR32_PM_BGCR (AVR32_PM_BASE+AVR32_PM_BGCR_OFFSET)
#define AVR32_PM_VREGCR (AVR32_PM_BASE+AVR32_PM_VREGCR_OFFSET)
#define AVR32_PM_BOD (AVR32_PM_BASE+AVR32_PM_BOD_OFFSET)
#define AVR32_PM_RCAUSE (AVR32_PM_BASE+AVR32_PM_RCAUSE_OFFSET)
#define AVR32_PM_AWEN (AVR32_PM_BASE+AVR32_PM_AWEN_OFFSET)
#define AVR32_PM_GPLP0 (AVR32_PM_BASE+AVR32_PM_GPLP0_OFFSET)
#define AVR32_PM_GPLP1 (AVR32_PM_BASE+AVR32_PM_GPLP1_OFFSET)
/* Register Bit-field Definitions *******************************************/
/* Main Clock Control Register Bit-field Definitions */
#define PM_MCCTRL_MCSEL_SHIFT (0) /* Bits 0-1: Main Clock Select */
#define PM_MCCTRL_MCSEL_MASK (3 << PM_MCCTRL_MCSEL_SHIFT)
# define PM_MCCTRL_MCSEL_SLOW (0 << PM_MCCTRL_MCSEL_SHIFT) /* slow clock is source */
# define PM_MCCTRL_MCSEL_OSC0 (1 << PM_MCCTRL_MCSEL_SHIFT) /* Oscillator 0 is source */
# define PM_MCCTRL_MCSEL_PLL0 (2 << PM_MCCTRL_MCSEL_SHIFT) /* PLL0 is source */
#define PM_MCCTRL_OSC0EN (1 << 2) /* Bit 2: Oscillator 0 Enable */
#define PM_MCCTRL_OSC1EN (1 << 3) /* Bit 3: Oscillator 1 Enable */
/* Clock Select Register Bit-field Definitions */
#define PM_CKSEL_CPUSEL_SHIFT (0) /* Bits 0-2: CPU Clock Select */
#define PM_CKSEL_CPUSEL_MASK (7 << PM_CKSEL_CPUSEL_SHIFT)
#define PM_CKSEL_CPUDIV (1 << 7) /* Bit 7: CPU Division */
#define PM_CKSEL_HSBSEL_SHIFT (8) /* Bits 8-10: HSB Clock Select */
#define PM_CKSEL_HSBSEL_MASK (7 << PM_CKSEL_HSBSEL_SHIFT)
#define PM_CKSEL_HSBDIV (1 << 15) /* Bit 15: HSB Division */
#define PM_CKSEL_PBASEL_SHIFT (16) /* Bits 16-28: BA Clock Select */
#define PM_CKSEL_PBASEL_MASK (7 << PM_CKSEL_PBASEL_SHIFT)
#define PM_CKSEL_PBADIV (1 << 23) /* Bit 23: PBA Division */
#define PM_CKSEL_PBBSEL_SHIFT (24) /* Bits 24-26: PBB Clock Select */
#define PM_CKSEL_PBBSEL_MASK (7 << PM_CKSEL_PBBSEL_SHIFT)
#define PM_CKSEL_PBBDIV (1 << 31) /* Bit 31: PBB Division */
/* CPU Mask Register Bit-field Definitions */
#define PM_CPUMASK_OCD (1 << 1) /* Bit 1: OCD */
/* HSB Mask Register Bit-field Definitions */
#define PM_HSBMASK_FLASHC (1 << 0) /* Bit 0: FLASHC */
#define PM_HSBMASK_PBA (1 << 1) /* Bit 1: PBA bridge */
#define PM_HSBMASK_PBB (1 << 2) /* Bit 2: PBB bridge */
#define PM_HSBMASK_USBB (1 << 3) /* Bit 3: USBB */
#define PM_HSBMASK_MACB (1 << 4) /* Bit 4: MACB */
#define PM_HSBMASK_PDCA (1 << 5) /* Bit 5: PDCA */
#define PM_HSBMASK_EBI (1 << 6) /* Bit 6: EBI */
/* PBA Mask Register Bit-field Definitions */
#define PM_PBAMASK_INTC (1 << 0) /* Bit 0: INTC */
#define PM_PBAMASK_GPIO (1 << 1) /* Bit 1: GPIO */
#define PM_PBAMASK_PDCA (1 << 2) /* Bit 2: PDCA */
#define PM_PBAMASK_PMRTCEIC (1 << 3) /* Bit 3: PM/RTC/EIC */
#define PM_PBAMASK_ADC (1 << 4) /* Bit 4: ADC */
#define PM_PBAMASK_SPI0 (1 << 5) /* Bit 5: SPI0 */
#define PM_PBAMASK_SPI1 (1 << 6) /* Bit 6: SPI1 */
#define PM_PBAMASK_TWI (1 << 7) /* Bit 7: TWI */
#define PM_PBAMASK_USART0 (1 << 8) /* Bit 8: USART0 */
#define PM_PBAMASK_USART1 (1 << 9) /* Bit 9: USART1 */
#define PM_PBAMASK_USART2 (1 << 10) /* Bit 10: USART2 */
#define PM_PBAMASK_USART3 (1 << 11) /* Bit 11: USART3 */
#define PM_PBAMASK_PWM (1 << 12) /* Bit 12: PWM */
#define PM_PBAMASK_SSC (1 << 13) /* Bit 13: SSC */
#define PM_PBAMASK_TC (1 << 14) /* Bit 14: TC */
#define PM_PBAMASK_ABDAC (1 << 15) /* Bit 15: ABDAC */
/* PBB Mask Register Bit-field Definitions */
#define PM_PBBMASK_HMATRIX (1 << 0) /* Bit 0: HMATRIX */
#define PM_PBBMASK_USBB (1 << 1) /* Bit 1: USBB */
#define PM_PBBMASK_FLASHC (1 << 2) /* Bit 2: FLASHC */
#define PM_PBBMASK_MACB (1 << 3) /* Bit 3: MACB */
#define PM_PBBMASK_SMC (1 << 4) /* Bit 4: SMC */
#define PM_PBBMASK_SDRAMC (1 << 5) /* Bit 5: SDRAMC */
/* PLL0/1 Control Register Bit-field Definitions */
#define PM_PLL_PLLEN (1 << 0) /* Bit 0: PLL Enable */
#define PM_PLL_PLLOSC (1 << 1) /* Bit 1: PLL Oscillator Select */
#define PM_PLL_PLLOPT_SHIFT (2) /* Bits 2-3: PLL Option */
#define PM_PLL_PLLOPT_MASK (7 << PM_PLL_PLLOPT_SHIFT)
# define PM_PLL_PLLOPT_VCO (1 << PM_PLL_PLLOPT_SHIFT) /* Select the VCO frequency range */
# define PM_PLL_PLLOPT_XTRADIV (2 << PM_PLL_PLLOPT_SHIFT) /* Enable the extra output divider */
# define PM_PLL_PLLOPT_WBWDIS (4 << PM_PLL_PLLOPT_SHIFT) /* Disable the Wide-Bandwidth mode */
#define PM_PLL_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */
#define PM_PLL_PLLDIV_MASK (15 << PM_PLL_PLLDIV_SHIFT)
#define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */
#define PM_PLL_PLLMUL_MASK (15 << PM_PLL_PLLMUL_SHIFT)
#define PM_PLL_PLLCOUNT_SHIFT (24) /* Bits 24-29: PLL Count */
#define PM_PLL_PLLCOUNT_MASK (0x3f << PM_PLL_PLLCOUNT_SHIFT)
/* Oscillator 0/1 Control Register Bit-field Definitions */
#define PM_OSCCTRL_MODE_SHIFT (0) /* Bits 0-2: Oscillator Mode */
#define PM_OSCCTRL_MODE_MASK (7 << PM_OSCCTRL_MODE_SHIFT)
# define PM_OSCCTRL_MODE_EXT (0 << PM_OSCCTRL_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL_MODE_XTALP9 (4 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.4-0.9MHz */
# define PM_OSCCTRL_MODE_XTAL3 (5 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.9-3.0MHz */
# define PM_OSCCTRL_MODE_XTAL8 (6 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 3.0-8.0MHz */
# define PM_OSCCTRL_MODE_XTALHI (7 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN above 8.0MHz */
#define PM_OSCCTRL_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator Startup Time */
#define PM_OSCCTRL_STARTUP_MASK (7 << PM_OSCCTRL_STARTUP_SHIFT)
# define PM_OSCCTRL_STARTUP_0 (0 << PM_OSCCTRL_STARTUP_SHIFT) /* Num RCOsc cycles */
# define PM_OSCCTRL_STARTUP_64 (1 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_128 (2 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_2K (3 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_4K (4 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_8K (5 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_16K (6 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
/* Oscillator 32 Control Register Bit-field Definitions */
#define PM_OSCCTRL32_EN (1 << 0) /* Bit 0: Enable the 32KHz oscillator */
#define PM_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */
#define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT)
# define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */
#define PM_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Startup Time */
#define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT)
# define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */
# define PM_OSCCTRL32_STARTUP_128 (1 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_8K (2 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_16K (3 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_64K (4 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_128K (5 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_512K (6 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
/* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */
#define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
#define PM_INT_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
#define PM_INT_CKRDY (1 << 5) /* Bit 5: Clock Ready */
#define PM_INT_MSKRDY (1 << 6) /* Bit 6: Mask Ready */
#define PM_INT_OSC0RDY (1 << 7) /* Bit 7: Oscillator 0 Ready */
#define PM_INT_OSC1RDY (1 << 8) /* Bit 8: Oscillator 1 Ready */
#define PM_INT_OSC32RDY (1 << 9) /* Bit 9: 32 KHz oscillator Ready */
#define PM_INT_BODDET (1 << 16) /* Bit 16: Brown out detection */
/* Power and Oscillators Status Register Bit-field Definitions */
#define PM_POSCSR_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
#define PM_POSCSR_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
#define PM_POSCSR_WAKE (1 << 2) /* Bit 1: PLL1 locked */
#define PM_POSCSR_CKRDY (1 << 5) /* Bit 5: Clock Ready */
#define PM_POSCSR_MSKRDY (1 << 6) /* Bit 6: Mask Ready */
#define PM_POSCSR_OSC0RDY (1 << 7) /* Bit 7: Oscillator 0 Ready */
#define PM_POSCSR_OSC1RDY (1 << 8) /* Bit 8: Oscillator 1 Ready */
#define PM_POSCSR_OSC32RDY (1 << 9) /* Bit 9: 32 KHz oscillator Ready */
#define PM_POSCSR_BODDET (1 << 16) /* Bit 16: Brown out detection */
/* 0x0060-0x070 Generic Clock Control Register Bit-field Definitions */
#define PM_GCCTRL_OSCSEL (1 << 0) /* Bit 0: Oscillator Select */
#define PM_GCCTRL_PLLSEL (1 << 1) /* Bit 1: PLL Select */
#define PM_GCCTRL_CEN (1 << 2) /* Bit 2: Clock Enable */
#define PM_GCCTRL_DIVEN (1 << 4) /* Bit 4: Divide Enable */
#define PM_GCCTRL_DIV_SHIFT (8) /* Bits 8-15: Division Factor */
#define PM_GCCTRL_DIV_MASK (0xff << PM_GCCTRL_DIV_SHIFT)
/* RC Oscillator Calibration Register Bit-field Definitions */
#define PM_RCCR_CALIB_SHIFT (0) /* Bits 0-9: Calibration Value */
#define PM_RCCR_CALIB_MASK (0x3ff << PM_RCCR_CALIB_SHIFT)
#define PM_RCCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_RCCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_RCCR_KEY_MASK (0xff << PM_RCCR_KEY_SHIFT)
/* Bandgap Calibration Register Bit-field Definitions */
#define PM_BGCR_CALIB_SHIFT (0) /* Bits 0-3: Calibration Value */
#define PM_BGCR_CALIB_MASK (7 << PM_BGCR_CALIB_SHIFT)
#define PM_BGCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_BGCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BGCR_KEY_MASK (0xff << PM_BGCR_KEY_SHIFT)
/* Linear Regulator Calibration Register Bit-field Definitions */
#define PM_VREGCR_CALIB_SHIFT (0) /* Bits 0-3: Calibration Value */
#define PM_VREGCR_CALIB_MASK (7 << PM_VREGCR_CALIB_SHIFT)
#define PM_VREGCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_VREGCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_VREGCR_KEY_MASK (0xff << PM_VREGCR_KEY_SHIFT)
/* BOD Level Register BOD Read/Write Bit-field Definitions */
#define PM_BOD_LEVEL_SHIFT (0) /* Bits 0-5: BOD Level */
#define PM_BOD_LEVEL_MASK (0x3f << PM_BOD_LEVEL_SHIFT)
#define PM_BOD_HYST (1 << 6) /* Bit 6: BOD Hysteresis */
#define PM_BOD_CTRL_SHIFT (8) /* Bits 8-9: BOD Control */
#define PM_BOD_CTRL_MASK (3 << PM_BOD_CTRL_SHIFT)
# define PM_BOD_CTRL_OFF (xxx << PM_BOD_CTRL_SHIFT) /* BOD is off */
# define PM_BOD_CTRL_RESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/can reset */
# define PM_BOD_CTRL_NORESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/cannot reset */
#define PM_BOD_FCD (1 << 16) /* Bit 16: BOD Fuse calibration done */
#define PM_BOD_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BOD_KEY_MASK (0xff << PM_BOD_KEY_SHIFT)
/* Reset Cause Register */
#define PM_RCAUSE_POR (1 << 0) /* Bit 0: Power-on Reset */
#define PM_RCAUSE_BOD (1 << 1) /* Bit 1: Brown-out Reset */
#define PM_RCAUSE_EXT (1 << 2) /* Bit 2: External Reset Pin */
#define PM_RCAUSE_WDT (1 << 3) /* Bit 3: Watchdog Reset */
#define PM_RCAUSE_JTAG (1 << 4) /* Bit 4: JTAG reset */
#define PM_RCAUSE_SLEEP (1 << 6) /* Bit 6: Sleep */
#define PM_RCAUSE_CPUERR (1 << 7) /* Bit 7: CPU Error */
#define PM_RCAUSE_OCDRST (1 << 8) /* Bit 8: OCD Reset */
/* Asynchronous Wake Up Enable Register Bit-field Definitions */
#define PM_AWEN_USBWAKEN (1 << 0) /* Bit 0: USB Wake Up Enable */
/* General Purpose Low-Power Register 0/1 Bit-field Definitions */
/* These registers contain a 32-bit value with no smaller bit-field */
/* GCLK Allocation **********************************************************/
#define AVR32_PM_GCLK0 (0) /* GCLK0 pin */
#define AVR32_PM_GCLK1 (1) /* GCLK2 pin */
#define AVR32_PM_GCLK2 (2) /* GCLK2 pin */
#define AVR32_PM_GCLK_USBB (3) /* USBB */
#define AVR32_PM_GCLK_ABDAC (4) /* ABDAC */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3A_PM_H */

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/****************************************************************************
* arch/avr/src/at32uc3/at32uc3b_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PM_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define AVR32_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */
#define AVR32_PM_CKSEL_OFFSET 0x0004 /* Clock Select Register */
#define AVR32_PM_CPUMASK_OFFSET 0x0008 /* CPU Mask Register */
#define AVR32_PM_HSBMASK_OFFSET 0x000c /* HSB Mask Register */
#define AVR32_PM_PBAMASK_OFFSET 0x0010 /* PBA Mask Register */
#define AVR32_PM_PBBMASK_OFFSET 0x0014 /* PBB Mask Register */
#define AVR32_PM_PLL0_OFFSET 0x0020 /* PLL0 Control Register */
#define AVR32_PM_PLL1_OFFSET 0x0024 /* PLL1 Control Register */
#define AVR32_PM_OSCCTRL0_OFFSET 0x0028 /* Oscillator 0 Control Register */
#define AVR32_PM_OSCCTRL1_OFFSET 0x002c /* Oscillator 1 Control Register */
#define AVR32_PM_OSCCTRL32_OFFSET 0x0030 /* Oscillator 32 Control Register */
#define AVR32_PM_IER_OFFSET 0x0040 /* Interrupt Enable Register */
#define AVR32_PM_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
#define AVR32_PM_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
#define AVR32_PM_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define AVR32_PM_ICR_OFFSET 0x0050 /* Interrupt Clear Register */
#define AVR32_PM_POSCSR_OFFSET 0x0054 /* Power and Oscillators Status Register */
#define AVR32_PM_GCCTRL_OFFSET(n) (0x0060+((n)<<2)) /* 0x0060-0x070 Generic Clock Control Register */
#define AVR32_PM_RCCR_OFFSET 0x00c0 /* RC Oscillator Calibration Register */
#define AVR32_PM_BGCR_OFFSET 0x00c4 /* Bandgap Calibration Register */
#define AVR32_PM_VREGCR_OFFSET 0x00c8 /* Linear Regulator Calibration Register */
#define AVR32_PM_BOD_OFFSET 0x00d0 /* BOD Level Register BOD Read/Write */
#define AVR32_PM_RCAUSE_OFFSET 0x0140 /* Reset Cause Register */
#define AVR32_PM_AWEN_OFFSET 0x0144 /* Asynchronous Wake Up Enable Register */
#define AVR32_PM_GPLP0_OFFSET 0x0200 /* General Purpose Low-Power Register 0 */
#define AVR32_PM_GPLP1_OFFSET 0x0204 /* General Purpose Low-Power Register 1 */
/* Register Addresses *******************************************************/
#define AVR32_PM_MCCTRL (AVR32_PM_BASE+AVR32_PM_MCCTRL_OFFSET)
#define AVR32_PM_CKSEL (AVR32_PM_BASE+AVR32_PM_CKSEL_OFFSET)
#define AVR32_PM_CPUMASK (AVR32_PM_BASE+AVR32_PM_CPUMASK_OFFSET)
#define AVR32_PM_HSBMASK (AVR32_PM_BASE+AVR32_PM_HSBMASK_OFFSET)
#define AVR32_PM_PBAMASK (AVR32_PM_BASE+AVR32_PM_PBAMASK_OFFSET)
#define AVR32_PM_PBBMASK (AVR32_PM_BASE+AVR32_PM_PBBMASK_OFFSET)
#define AVR32_PM_PLL0 (AVR32_PM_BASE+AVR32_PM_PLL0_OFFSET)
#define AVR32_PM_PLL1 (AVR32_PM_BASE+AVR32_PM_PLL1_OFFSET)
#define AVR32_PM_OSCCTRL0 (AVR32_PM_BASE+AVR32_PM_OSCCTRL0_OFFSET)
#define AVR32_PM_OSCCTRL1 (AVR32_PM_BASE+AVR32_PM_OSCCTRL1_OFFSET)
#define AVR32_PM_OSCCTRL32 (AVR32_PM_BASE+AVR32_PM_OSCCTRL32_OFFSET)
#define AVR32_PM_IER (AVR32_PM_BASE+AVR32_PM_IER_OFFSET)
#define AVR32_PM_IDR (AVR32_PM_BASE+AVR32_PM_IDR_OFFSET)
#define AVR32_PM_IMR (AVR32_PM_BASE+AVR32_PM_IMR_OFFSET)
#define AVR32_PM_ISR (AVR32_PM_BASE+AVR32_PM_ISR_OFFSET)
#define AVR32_PM_ICR (AVR32_PM_BASE+AVR32_PM_ICR_OFFSET)
#define AVR32_PM_POSCSR (AVR32_PM_BASE+AVR32_PM_POSCSR_OFFSET)
#define AVR32_PM_GCCTRL(n) (AVR32_PM_BASE+AVR32_PM_GCCTRL_OFFSET(n))
#define AVR32_PM_RCCR (AVR32_PM_BASE+AVR32_PM_RCCR_OFFSET)
#define AVR32_PM_BGCR (AVR32_PM_BASE+AVR32_PM_BGCR_OFFSET)
#define AVR32_PM_VREGCR (AVR32_PM_BASE+AVR32_PM_VREGCR_OFFSET)
#define AVR32_PM_BOD (AVR32_PM_BASE+AVR32_PM_BOD_OFFSET)
#define AVR32_PM_RCAUSE (AVR32_PM_BASE+AVR32_PM_RCAUSE_OFFSET)
#define AVR32_PM_AWEN (AVR32_PM_BASE+AVR32_PM_AWEN_OFFSET)
#define AVR32_PM_GPLP0 (AVR32_PM_BASE+AVR32_PM_GPLP0_OFFSET)
#define AVR32_PM_GPLP1 (AVR32_PM_BASE+AVR32_PM_GPLP1_OFFSET)
/* Register Bit-field Definitions *******************************************/
/* Main Clock Control Register Bit-field Definitions */
#define PM_MCCTRL_MCSEL_SHIFT (0) /* Bits 0-1: Main Clock Select */
#define PM_MCCTRL_MCSEL_MASK (3 << PM_MCCTRL_MCSEL_SHIFT)
# define PM_MCCTRL_MCSEL_SLOW (0 << PM_MCCTRL_MCSEL_SHIFT) /* slow clock is source */
# define PM_MCCTRL_MCSEL_OSC0 (1 << PM_MCCTRL_MCSEL_SHIFT) /* Oscillator 0 is source */
# define PM_MCCTRL_MCSEL_PLL0 (2 << PM_MCCTRL_MCSEL_SHIFT) /* PLL0 is source */
#define PM_MCCTRL_OSC0EN (1 << 2) /* Bit 2: Oscillator 0 Enable */
#define PM_MCCTRL_OSC1EN (1 << 3) /* Bit 3: Oscillator 1 Enable */
/* Clock Select Register Bit-field Definitions */
#define PM_CKSEL_CPUSEL_SHIFT (0) /* Bits 0-2: CPU Clock Select */
#define PM_CKSEL_CPUSEL_MASK (7 << PM_CKSEL_CPUSEL_SHIFT)
#define PM_CKSEL_CPUDIV (1 << 7) /* Bit 7: CPU Division */
#define PM_CKSEL_HSBSEL_SHIFT (8) /* Bits 8-10: HSB Clock Select */
#define PM_CKSEL_HSBSEL_MASK (7 << PM_CKSEL_HSBSEL_SHIFT)
#define PM_CKSEL_HSBDIV (1 << 15) /* Bit 15: HSB Division */
#define PM_CKSEL_PBASEL_SHIFT (16) /* Bits 16-28: BA Clock Select */
#define PM_CKSEL_PBASEL_MASK (7 << PM_CKSEL_PBASEL_SHIFT)
#define PM_CKSEL_PBADIV (1 << 23) /* Bit 23: PBA Division */
#define PM_CKSEL_PBBSEL_SHIFT (24) /* Bits 24-26: PBB Clock Select */
#define PM_CKSEL_PBBSEL_MASK (7 << PM_CKSEL_PBBSEL_SHIFT)
#define PM_CKSEL_PBBDIV (1 << 31) /* Bit 31: PBB Division */
/* CPU Mask Register Bit-field Definitions */
#define PM_CPUMASK_OCD (1 << 1) /* Bit 1: OCD */
/* HSB Mask Register Bit-field Definitions */
#define PM_HSBMASK_FLASHC (1 << 0) /* Bit 0: FLASHC */
#define PM_HSBMASK_PBA (1 << 1) /* Bit 1: PBA bridge */
#define PM_HSBMASK_PBB (1 << 2) /* Bit 2: PBB bridge */
#define PM_HSBMASK_USBB (1 << 3) /* Bit 3: USBB */
#define PM_HSBMASK_PDCA (1 << 4) /* Bit 4: PDCA */
/* PBA Mask Register Bit-field Definitions */
#define PM_PBAMASK_INTC (1 << 0) /* Bit 0: INTC */
#define PM_PBAMASK_GPIO (1 << 1) /* Bit 1: GPIO */
#define PM_PBAMASK_PDCA (1 << 2) /* Bit 2: PDCA */
#define PM_PBAMASK_PMRTCEIC (1 << 3) /* Bit 3: PM/RTC/EIC */
#define PM_PBAMASK_ADC (1 << 4) /* Bit 4: ADC */
#define PM_PBAMASK_SPI (1 << 5) /* Bit 5: SPI */
#define PM_PBAMASK_TWI (1 << 6) /* Bit 6: TWI */
#define PM_PBAMASK_USART0 (1 << 7) /* Bit 7: USART0 */
#define PM_PBAMASK_USART1 (1 << 8) /* Bit 8: USART1 */
#define PM_PBAMASK_USART2 (1 << 9) /* Bit 9: USART2 */
#define PM_PBAMASK_PWM (1 << 10) /* Bit 10: PWM */
#define PM_PBAMASK_SSC (1 << 11) /* Bit 11: SSC */
#define PM_PBAMASK_TC (1 << 12) /* Bit 12: TC */
#define PM_PBAMASK_ABDAC (1 << 13) /* Bit 13: ABDAC */
/* PBB Mask Register Bit-field Definitions */
#define PM_PBBMASK_HMATRIX (1 << 0) /* Bit 0: HMATRIX */
#define PM_PBBMASK_USBB (1 << 2) /* Bit 2: USBB */
#define PM_PBBMASK_FLASHC (1 << 3) /* Bit 3: FLASHC */
/* PLL0/1 Control Register Bit-field Definitions */
#define PM_PLL_PLLEN (1 << 0) /* Bit 0: PLL Enable */
#define PM_PLL_PLLOSC (1 << 1) /* Bit 1: PLL Oscillator Select */
#define PM_PLL_PLLOPT_SHIFT (2) /* Bits 2-3: PLL Option */
#define PM_PLL_PLLOPT_MASK (7 << PM_PLL_PLLOPT_SHIFT)
# define PM_PLL_PLLOPT_VCO (1 << PM_PLL_PLLOPT_SHIFT) /* Select the VCO frequency range */
# define PM_PLL_PLLOPT_XTRADIV (2 << PM_PLL_PLLOPT_SHIFT) /* Enable the extra output divider */
# define PM_PLL_PLLOPT_WBWDIS (4 << PM_PLL_PLLOPT_SHIFT) /* Disable the Wide-Bandwidth mode */
#define PM_PLL_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */
#define PM_PLL_PLLDIV_MASK (15 << PM_PLL_PLLDIV_SHIFT)
#define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */
#define PM_PLL_PLLMUL_MASK (15 << PM_PLL_PLLMUL_SHIFT)
#define PM_PLL_PLLCOUNT_SHIFT (24) /* Bits 24-29: PLL Count */
#define PM_PLL_PLLCOUNT_MASK (0x3f << PM_PLL_PLLCOUNT_SHIFT)
/* Oscillator 0/1 Control Register Bit-field Definitions */
#define PM_OSCCTRL_MODE_SHIFT (0) /* Bits 0-2: Oscillator Mode */
#define PM_OSCCTRL_MODE_MASK (7 << PM_OSCCTRL_MODE_SHIFT)
# define PM_OSCCTRL_MODE_EXT (0 << PM_OSCCTRL_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL_MODE_XTALP9 (4 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.4-0.9MHz */
# define PM_OSCCTRL_MODE_XTAL3 (5 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.9-3.0MHz */
# define PM_OSCCTRL_MODE_XTAL8 (6 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 3.0-8.0MHz */
# define PM_OSCCTRL_MODE_XTALHI (7 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN above 8.0MHz */
#define PM_OSCCTRL_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator Startup Time */
#define PM_OSCCTRL_STARTUP_MASK (7 << PM_OSCCTRL_STARTUP_SHIFT)
# define PM_OSCCTRL_STARTUP_0 (0 << PM_OSCCTRL_STARTUP_SHIFT) /* Num RCOsc cycles */
# define PM_OSCCTRL_STARTUP_64 (1 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_128 (2 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_2K (3 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_4K (4 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_8K (5 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL_STARTUP_16K (6 << PM_OSCCTRL_STARTUP_SHIFT) /* " " " " " " */
/* Oscillator 32 Control Register Bit-field Definitions */
#define PM_OSCCTRL32_EN (1 << 0) /* Bit 0: Enable the 32KHz oscillator */
#define PM_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */
#define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT)
# define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */
#define PM_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Startup Time */
#define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT)
# define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */
# define PM_OSCCTRL32_STARTUP_128 (1 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_8K (2 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_16K (3 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_64K (4 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_128K (5 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
# define PM_OSCCTRL32_STARTUP_512K (6 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
/* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */
#define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
#define PM_INT_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
#define PM_INT_CKRDY (1 << 5) /* Bit 5: Clock Ready */
#define PM_INT_MSKRDY (1 << 6) /* Bit 6: Mask Ready */
#define PM_INT_OSC0RDY (1 << 7) /* Bit 7: Oscillator 0 Ready */
#define PM_INT_OSC1RDY (1 << 8) /* Bit 8: Oscillator 1 Ready */
#define PM_INT_OSC32RDY (1 << 9) /* Bit 9: 32 KHz oscillator Ready */
#define PM_INT_BODDET (1 << 16) /* Bit 16: Brown out detection */
/* Power and Oscillators Status Register Bit-field Definitions */
#define PM_POSCSR_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
#define PM_POSCSR_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
#define PM_POSCSR_WAKE (1 << 2) /* Bit 1: PLL1 locked */
#define PM_POSCSR_CKRDY (1 << 5) /* Bit 5: Clock Ready */
#define PM_POSCSR_MSKRDY (1 << 6) /* Bit 6: Mask Ready */
#define PM_POSCSR_OSC0RDY (1 << 7) /* Bit 7: Oscillator 0 Ready */
#define PM_POSCSR_OSC1RDY (1 << 8) /* Bit 8: Oscillator 1 Ready */
#define PM_POSCSR_OSC32RDY (1 << 9) /* Bit 9: 32 KHz oscillator Ready */
#define PM_POSCSR_BODDET (1 << 16) /* Bit 16: Brown out detection */
/* 0x0060-0x070 Generic Clock Control Register Bit-field Definitions */
#define PM_GCCTRL_OSCSEL (1 << 0) /* Bit 0: Oscillator Select */
#define PM_GCCTRL_PLLSEL (1 << 1) /* Bit 1: PLL Select */
#define PM_GCCTRL_CEN (1 << 2) /* Bit 2: Clock Enable */
#define PM_GCCTRL_DIVEN (1 << 4) /* Bit 4: Divide Enable */
#define PM_GCCTRL_DIV_SHIFT (8) /* Bits 8-15: Division Factor */
#define PM_GCCTRL_DIV_MASK (0xff << PM_GCCTRL_DIV_SHIFT)
/* RC Oscillator Calibration Register Bit-field Definitions */
#define PM_RCCR_CALIB_SHIFT (0) /* Bits 0-9: Calibration Value */
#define PM_RCCR_CALIB_MASK (0x3ff << PM_RCCR_CALIB_SHIFT)
#define PM_RCCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_RCCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_RCCR_KEY_MASK (0xff << PM_RCCR_KEY_SHIFT)
/* Bandgap Calibration Register Bit-field Definitions */
#define PM_BGCR_CALIB_SHIFT (0) /* Bits 0-3: Calibration Value */
#define PM_BGCR_CALIB_MASK (7 << PM_BGCR_CALIB_SHIFT)
#define PM_BGCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_BGCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BGCR_KEY_MASK (0xff << PM_BGCR_KEY_SHIFT)
/* Linear Regulator Calibration Register Bit-field Definitions */
#define PM_VREGCR_CALIB_SHIFT (0) /* Bits 0-3: Calibration Value */
#define PM_VREGCR_CALIB_MASK (7 << PM_VREGCR_CALIB_SHIFT)
#define PM_VREGCR_FCD (1 << 16) /* Bit 16: Flash Calibration Done */
#define PM_VREGCR_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_VREGCR_KEY_MASK (0xff << PM_VREGCR_KEY_SHIFT)
/* BOD Level Register BOD Read/Write Bit-field Definitions */
#define PM_BOD_LEVEL_SHIFT (0) /* Bits 0-5: BOD Level */
#define PM_BOD_LEVEL_MASK (0x3f << PM_BOD_LEVEL_SHIFT)
#define PM_BOD_HYST (1 << 6) /* Bit 6: BOD Hysteresis */
#define PM_BOD_CTRL_SHIFT (8) /* Bits 8-9: BOD Control */
#define PM_BOD_CTRL_MASK (3 << PM_BOD_CTRL_SHIFT)
# define PM_BOD_CTRL_OFF (xxx << PM_BOD_CTRL_SHIFT) /* BOD is off */
# define PM_BOD_CTRL_RESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/can reset */
# define PM_BOD_CTRL_NORESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/cannot reset */
#define PM_BOD_FCD (1 << 16) /* Bit 16: BOD Fuse calibration done */
#define PM_BOD_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BOD_KEY_MASK (0xff << PM_BOD_KEY_SHIFT)
/* Reset Cause Register */
#define PM_RCAUSE_POR (1 << 0) /* Bit 0: Power-on Reset */
#define PM_RCAUSE_BOD (1 << 1) /* Bit 1: Brown-out Reset */
#define PM_RCAUSE_EXT (1 << 2) /* Bit 2: External Reset Pin */
#define PM_RCAUSE_WDT (1 << 3) /* Bit 3: Watchdog Reset */
#define PM_RCAUSE_JTAG (1 << 4) /* Bit 4: JTAG reset */
#define PM_RCAUSE_SLEEP (1 << 6) /* Bit 6: Sleep */
#define PM_RCAUSE_CPUERR (1 << 7) /* Bit 7: CPU Error */
#define PM_RCAUSE_OCDRST (1 << 8) /* Bit 8: OCD Reset */
/* Asynchronous Wake Up Enable Register Bit-field Definitions */
#define PM_AWEN_USBWAKEN (1 << 0) /* Bit 0: USB Wake Up Enable */
/* General Purpose Low-Power Register 0/1 Bit-field Definitions */
/* These registers contain a 32-bit value with no smaller bit-field */
/* GCLK Allocation **********************************************************/
#define AVR32_PM_GCLK0 (0) /* GCLK0 pin */
#define AVR32_PM_GCLK1 (1) /* GCLK2 pin */
#define AVR32_PM_GCLK2 (2) /* GCLK2 pin */
#define AVR32_PM_GCLK_USBB (3) /* USBB */
#define AVR32_PM_GCLK_ABDAC (4) /* ABDAC */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PM_H */

33
arch/avr/src/at32uc3/chip.h
View file

@ -27,6 +27,12 @@
#include <nuttx/config.h>
/* Include only the memory map. Other chip hardware files should then
* include this file for the proper setup
*/
#include "at32uc3_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -35,11 +41,30 @@
/* UC3 A0/A1 Series */
#if defined (CONFIG_ARCH_CHIP_AT32UC3A0512)
# define CONFIG_ARCH_CHIP_AT32UC3A 1 /* UC3 A series */
# define CONFIG_ARCH_CHIP_AT32UC3A0 1 /* UC3 A0 (144-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (512*1024) /* Size of on-chip FLASH (bytes) */
# define AVR32_ONCHIP_SRAM_SIZE (64*1024) /* Size of on-chip SRAM (bytes) */
# define AVR32_USB_FULLSPEED 1 /* USB full-speed support */
# define AVR32_USB_HOST 1 /* USB host support (OTG) */
# define AVR32_USB_DEVICE 1 /* USB device support */
# define AVR32_NUSART 4 /* Number of USARTs */
# define AVR32_NSPI 2 /* Number of SPI */
# define AVR32_NTWI 1 /* Number of TWI (I2C) */
# define AVR32_NSSC 1 /* Number of SSC (I2S audio) */
# define AVR32_NGPIO 66 /* Number of GPIO pins */
# define AVR32_NTIMER 1 /* Number of Timers */
# define AVR32_NPWM 7 /* Number of PWM channels */
# define AVR32_NOSC 1 /* Number of crystal oscillators */
# define AVR32_NADC10 8 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 1 /* Number of DMA channels */
/* UC3 A2/A3 Series */
/* UC3 B0 (64-pin) / B1 (48-pin, no USB host) Series */
#ifdef CONFIG_ARCH_CHIP_AT32UC3B064
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B064)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B0 1 /* UC3 B0 (64-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (64*1024) /* Size of on-chip FLASH (bytes) */
@ -187,12 +212,6 @@
# error "Unsupported AVR32 chip"
#endif
/* Include only the memory map. Other chip hardware files should then
* include this file for the proper setup
*/
#include "at32uc3_memorymap.h"
/****************************************************************************
* Public Types
****************************************************************************/

13
boards/Kconfig
View file

@ -1084,6 +1084,15 @@ config ARCH_BOARD_MISOC_VERILATOR
---help---
This configuration is port to NuttX running on Verilator.
config ARCH_BOARD_MIZAR32A
bool "Mizar32-A"
depends on ARCH_CHIP_AT32UC3A0512
select ARCH_HAVE_LEDS
---help---
This is a port of NuttX for the Mizar32-A board designed by SimpleMachines,
Italy. The board is based on the AT32UC3A0512 MCU and uses avr32-gcc
version 4.4.7 for its build on GNU/Linux.
config ARCH_BOARD_MOTEINO_MEGA
bool "LowPowerLab MoteinoMEGA"
depends on ARCH_CHIP_ATMEGA1284P
@ -3281,6 +3290,7 @@ config ARCH_BOARD
default "micropendous3" if ARCH_BOARD_MICROPENDOUS3
default "mirtoo" if ARCH_BOARD_MIRTOO
default "misoc" if ARCH_BOARD_MISOC_QEMU || ARCH_BOARD_MISOC_VERILATOR
default "mizar32a" if ARCH_BOARD_MIZAR32A
default "moteino-mega" if ARCH_BOARD_MOTEINO_MEGA
default "ne64badge" if ARCH_BOARD_NE64BADGE
default "nrf52-feather" if ARCH_BOARD_NRF52_FEATHER
@ -4229,6 +4239,9 @@ endif
if ARCH_BOARD_AVR32DEV1
source "boards/avr/at32uc3/avr32dev1/Kconfig"
endif
if ARCH_BOARD_MIZAR32A
source "boards/avr/at32uc3/mizar32a/Kconfig"
endif
if ARCH_BOARD_MEGA1284P_XPLAINED
source "boards/avr/atmega/mega1284p-xplained/Kconfig"
endif

7
boards/avr/at32uc3/mizar32a/Kconfig Normal file
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@ -0,0 +1,7 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_MIZAR32A
endif

39
boards/avr/at32uc3/mizar32a/configs/nsh/defconfig Normal file
View file

@ -0,0 +1,39 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH="avr"
CONFIG_ARCH_AVR=y
CONFIG_ARCH_BOARD="mizar32a"
CONFIG_ARCH_BOARD_MIZAR32A=y
CONFIG_ARCH_CHIP="at32uc3"
CONFIG_ARCH_CHIP_AT32UC3=y
CONFIG_ARCH_CHIP_AT32UC3A0512=y
CONFIG_ARCH_CHIP_AT32UC3A=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_AVR32_GPIOIRQ=y
CONFIG_AVR32_GPIOIRQSETA=0
CONFIG_AVR32_GPIOIRQSETB=0x0000000c
CONFIG_AVR32_USART1=y
CONFIG_BOARD_LOOPSPERMSEC=1140
CONFIG_ENDIAN_BIG=y
CONFIG_FS_FAT=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=65536
CONFIG_RAM_START=0x00000004
CONFIG_START_DAY=2
CONFIG_START_MONTH=11
CONFIG_START_YEAR=2010
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y

149
boards/avr/at32uc3/mizar32a/include/board.h Normal file
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@ -0,0 +1,149 @@
/****************************************************************************
* boards/avr/at32uc3/mizar32a/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_AVR_AT32UC3_MIZAR32A_INCLUDE_BOARD_H
#define __BOARDS_AVR_AT32UC3_MIZAR32A_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* Oscillator setup: RCOSC, OSC32, OSC0, OSC1. Only RCOSC, OSC0, or PLL0
* can drive the main clock.
*/
/* The RCOSC frequency needs to be calibrated! */
#define AVR32_FRCOSC 115000 /* RCOSC frequency in Hz. 115KHz nominal */
#define AVR32_FOSC32 32768 /* OSC32 frequency in Hz */
#define AVR32_OSC32STARTUP 3 /* OSC32 startup time in RCOSC periods */
#define AVR32_FOSC0 12000000 /* OSC0 frequency in Hz */
#define AVR32_OSC0STARTUP 3 /* OSC0 startup time in RCOSC periods. */
/* #define AVR32_FOSC1 12000000 OSC1 frequency: Hz.
* #define AVR32_OSC1STARTUP 3 OSC1 startup time in RCOSC periods.
*/
/* PLL setup
*
* FOSC0 MUL DIV PLL DIV2_EN CPU_CLOCK PBA_CLOCK COMMENT
* (MHz) (MHz) (MHz) (MHz)
* 12 15 1 192 1 12 12
* 12 9 3 40 1 20 20 PLL out of spec
* 12 15 1 192 1 24 12
* 12 9 1 120 1 30 15
* 12 9 3 40 0 40 20 PLL out of spec
* 12 15 1 192 1 48 12
* 12 15 1 192 1 48 24
* 12 8 1 108 1 54 27
* 12 9 1 120 1 60 15
* 12 9 1 120 1 60 30
* 12 10 1 132 1 66 16.5 This applies for Mizar32-A.
*/
#define AVR32_CLOCK_PLL0_OSC0 1
#undef AVR32_CLOCK_PLL0_OSC1
#define AVR32_PLL0_MUL 10
#define AVR32_PLL0_DIV 1
#define AVR32_PLL0_DIV2 1
#define AVR32_PLL0_WBWM 0
#define AVR32_PLL0_FREQ 132000000
/* Set PLL1 @ 96 MHz from OSC0: 12MHz*(7+1)/1 = 96MHz */
#define AVR32_CLOCK_PLL1_OSC0 1
#undef AVR32_CLOCK_PLL1_OSC1
#define AVR32_PLL1_MUL 7
#define AVR32_PLL1_DIV 1
#define AVR32_PLL1_DIV2 1
#define AVR32_PLL1_WBWM 0
#define AVR32_PLL1_FREQ 96000000
/* Clock divider setup */
#define AVR32_CKSEL_CPUDIV 0
#define AVR32_CKSEL_HSBDIV 0
#define AVR32_CKSEL_PBADIV 1
#define AVR32_CKSEL_PBBDIV 0
/* GCLK_USBB */
#undef AVR32_CLOCK_USB_PLL0
#define AVR32_CLOCK_USB_PLL1 1
#undef AVR32_CLOCK_USB_OSC0
#undef AVR32_CLOCK_USB_OSC1
#define AVR32_CLOCK_USB_DIV 0
/* Main Clock setup: Select OSC0 as the main clock.
*
* - A 12MHz crystal is provided on he board for OSC0.
* - The Mizar32-A board has no support for OSC1.
* - There are pads for the 32KHz OSC32, but it is not populated on the
* board.
*/
#define AVR32_CLOCK_OSC0 1
#undef AVR32_CLOCK_OSC1 /* Not supported */
#undef AVR32_CLOCK_OSC32 /* Not populated */
#define AVR32_CLOCK_PLL0 /* Enable PLL0 */
#undef AVR32_CLOCK_PLL1
#define AVR32_CPU_CLOCK 66000000
#define AVR32_PBA_CLOCK 16500000
/* Pin muliplexing selecion *************************************************/
#define PINMUX_USART1_RXD PINMUX_USART1_RXD_0
#define PINMUX_USART1_TXD PINMUX_USART1_TXD_0
/* LED definitions **********************************************************/
/* The Mizar32-A board has only one controllable LED */
#define LED_STARTED 0 /* No LEDs */
#define LED_HEAPALLOCATE 1 /* LED1 on */
#define LED_IRQSENABLED 2 /* LED2 on */
#define LED_STACKCREATED 3 /* LED1 on */
#define LED_INIRQ 4 /* LED1 off */
#define LED_SIGNAL 5 /* LED2 on */
#define LED_ASSERTION 6 /* LED1 + LED2 */
#define LED_PANIC 7 /* LED1 / LED2 blinking */
/* Button definitions *******************************************************/
/* The Mizar32 board has 2 BUTTONs,
* one of which can be sensed through GPIO pins.
*/
#define BUTTON1 1 /* Bit 0: Button 1 */
#endif /* __BOARDS_AVR_AT32UC3_MIZAR32A_INCLUDE_BOARD_H */

38
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############################################################################
# boards/avr/at32uc3/mizar32a/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/avr/src/avr32/Toolchain.defs
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)mizar32a.ld
ARCHCFLAGS = -muse-rodata-section
ARCHNOPICFLAGS = -fno-pic
ARCHPICFLAGS = -fpic
ARCHALLCFLAGS = $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
ARCHALLCXXFLAGS = $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CFLAGS := $(ARCHNOPICFLAGS) $(ARCHALLCFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(ARCHALLCFLAGS)
CXXFLAGS := $(ARCHNOPICFLAGS) $(ARCHALLCXXFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(ARCHALLCXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(ARCHALLCFLAGS) -D__ASSEMBLY__

90
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/****************************************************************************
* boards/avr/at32uc3/mizar32a/scripts/mizar32a.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
ENTRY(_stext)
/* The following assumes that the bootloader resides at 0x8000:0000 and so
* links the application to execute after the bootloader at 0x8000:2000.
* To link so that NuttX boots directly without using the bootloader,
* change the flash definition to:
*
* flash (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
*/
MEMORY
{
flash (rxai!w) : ORIGIN = 0x80002000, LENGTH = 0x00080000 - 0x2000
intram (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
}
SECTIONS
{
.text : {
. = ALIGN(4);
_stext = .;
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_etext = .;
} > flash
_eronly = .; /* See below */
.data : AT(_etext) {
. = ALIGN(4);
_sdata = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = .;
} > intram
.bss : { /* BSS */
_sbss = .;
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} > intram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

33
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############################################################################
# boards/avr/at32uc3/mizar32a/src/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = avr32_boot.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += avr32_leds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += avr32_buttons.c
endif
CSRCS += avr32_appinit.c
CSRCS += avr32_bringup.c
include $(TOPDIR)/boards/Board.mk

71
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/****************************************************************************
* boards/avr/at32uc3/mizar32a/src/avr32_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "mizar32a.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifndef CONFIG_BOARD_LATE_INITIALIZE
/* Perform board initialization */
return avr32_bringup();
#else
return OK;
#endif /* CONFIG_BOARD_LATE_INITIALIZE */
}

68
boards/avr/at32uc3/mizar32a/src/avr32_boot.c Normal file
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/****************************************************************************
* boards/avr/at32uc3/mizar32a/src/avr32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "avr_internal.h"
#include "at32uc3.h"
#include "mizar32a.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: at32uc3_boardinitialize
*
* Description:
* All AVR32 AT32UC3 architectures must provide the following entry point.
* This entry point is called early in the initialization - after all
* memory has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void at32uc3_boardinitialize(void)
{
/* Configure SPI chip selects */
/* Configure on-board LEDs if LED support has been selected. */
#ifdef CONFIG_ARCH_LEDS
board_autoled_initializeialize();
#endif
}

57
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/****************************************************************************
* boards/avr/at32uc3/mizar32a/src/avr32_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: avr32_bringup
*
* Description:
* Bring up board features
*
****************************************************************************/
int avr32_bringup(void)
{
int ret = OK;
/* #warning "Not Implemented" */
return ret;
}

159
boards/avr/at32uc3/mizar32a/src/avr32_buttons.c Normal file
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/****************************************************************************
* boards/avr/at32uc3/mizar32a/src/avr32_buttons.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "at32uc3_config.h"
#include <sys/types.h>
#include <stdint.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/irq.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "at32uc3.h"
#include "mizar32a.h"
#ifdef CONFIG_ARCH_BUTTONS
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_irqx
*
* Description:
* This function implements the core of the board_button_irq() logic.
*
****************************************************************************/
#if defined(CONFIG_AVR32_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS) && \
defined(CONFIG_MIAR32A_BUTTON1_IRQ)
static int board_button_irqx(int irq, xcpt_t irqhandler, void *arg)
{
/* Attach the handler */
int ret = gpio_irqattach(irq, irqhandler, &oldhandler, arg);
if (ret >= 0)
{
/* Enable/disable the interrupt */
if (irqhandler != NULL)
{
gpio_irqenable(irq);
}
else
{
gpio_irqdisable(irq);
}
}
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_initialize
*
* Description:
* board_button_initialize() must be called to initialize button resources.
* After that, board_buttons() may be called to collect the current state
* of all buttons or board_button_irq() may be called to register button
* interrupt handlers.
*
****************************************************************************/
uint32_t board_button_initialize(void)
{
at32uc3_configgpio(PINMUX_GPIO_BUTTON1);
return 2;
}
/****************************************************************************
* Name: board_buttons
*
* Description:
* After board_button_initialize() has been called, board_buttons() may be
* called to collect the state of all buttons. board_buttons() returns an
* 32-bit bit set with each bit associated with a button. See the BUTTON*
* definitions in the board.h header file for the meaning of each bit in
* the returned value.
*
****************************************************************************/
uint32_t board_buttons(void)
{
uint32_t retval;
retval = at32uc3_gpioread(PINMUX_GPIO_BUTTON1) ? 0 : BUTTON1;
return retval;
}
/****************************************************************************
* Name: board_button_irq
*
* Description:
* This function may be called to register an interrupt handler that will
* be called when a button is depressed or released. The ID value is one
* of the BUTTON* definitions provided above.
*
* Configuration Notes:
* Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the
* overall GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or
* CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support
* interrupts on. For button support, bits 2 and 3 must be set in
* CONFIG_AVR32_GPIOIRQSETB (PB2 and PB3).
*
****************************************************************************/
#if defined(CONFIG_AVR32_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS)
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
{
int ret;
#ifdef CONFIG_MIZAR32A_BUTTON1_IRQ
if (id == BUTTON1)
{
ret = board_button_irqx(GPIO_BUTTON1_IRQ, irqhandler, arg);
}
else
#endif
{
ret = -EINVAL;
}
return ret;
}
#endif
#endif /* CONFIG_ARCH_BUTTONS */

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/****************************************************************************
* boards/avr/at32uc3/mizar32a/src/avr32_leds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "at32uc3.h"
#include "mizar32a.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
static inline void set_led(bool v)
{
at32uc3_gpiowrite(PINMUX_GPIO_LED1, v);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled_initializeialize
****************************************************************************/
void board_autoled_initializeialize(void)
{
at32uc3_configgpio(PINMUX_GPIO_LED1);
}
/****************************************************************************
* Name: board_autoled_on
****************************************************************************/
void board_autoled_on(int led)
{
switch (led)
{
case LED_STARTED:
case LED_HEAPALLOCATE:
/* As the board provides only one soft controllable LED,
* we simply turn it on when the board boots
*/
set_led(false);
break;
case LED_PANIC:
/* For panic state, the LED is blinking */
set_led(false);
break;
}
}
/****************************************************************************
* Name: board_autoled_off
****************************************************************************/
void board_autoled_off(int led)
{
switch (led)
{
case LED_PANIC:
/* For panic state, the LED is blinking */
set_led(true);
break;
}
}
#endif /* CONFIG_ARCH_LEDS */

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/****************************************************************************
* boards/avr/at32uc3/mizar32a/src/mizar32a.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_AVR_AT32UC3_MIZAR32A_SRC_MIZAR32A_H
#define __BOARDS_AVR_AT32UC3_MIZAR32A_SRC_MIZAR32A_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include "at32uc3_config.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if (CONFIG_AVR32_GPIOIRQSETB & 4) == 1
# define CONFIG_MIZAR32A_BUTTON1_IRQ 1
#endif
#if (CONFIG_AVR32_GPIOIRQSETB & 8) == 1
# define CONFIG_MIZAR32A_BUTTON2_IRQ 1
#endif
/* AVRDEV1 GPIO Pin Definitions *********************************************/
/* LEDs
*
* The Mizar32-A board has 2 LEDs,
* one of which can be controlled through GPIO pins.
*
* PIN 20 PB29 LED1
*/
#define PINMUX_GPIO_LED1 (GPIO_ENABLE | GPIO_OUTPUT | GPIO_LOW | GPIO_PORTB | 29)
/* BUTTONs
*
* The Mizar32-A board has 2 BUTTONs,
* one of which can be sensed through GPIO pins.
*
* PIN 61 PX16 KEY1
*/
#if CONFIG_MIZAR32A_BUTTON1_IRQ
# define PINMUX_GPIO_BUTTON1 (GPIO_ENABLE | GPIO_INPUT | GPIO_INTR | \
GPIO_INTMODE_BOTH | GPIO_GLITCH | GPIO_PORTB | 2)
# define GPIO_BUTTON1_IRQ AVR32_IRQ_GPIO_PB2
#else
# define PINMUX_GPIO_BUTTON1 (GPIO_ENABLE | GPIO_INPUT | GPIO_GLITCH | \
GPIO_PORTB | 2)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions Definitions
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_AVR_AT32UC3_MIZAR32A_SRC_MIZAR32A_H */

45
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#!/usr/bin/env bash
#set -x
# This script must be executed in the NuttX top-level directory. We'll check..
# the .config file should be located there.
# Note: dfu-programmer needs 'sudo' for its operation. Execute
# this script by prefixing 'sudo' during its invocation.
TOPDIR=`pwd`
if [ ! -f .config ]; then
echo "There is no configured version of NuttX in this directory."
echo " Is '$TOPDIR' the NuttX top level directory?"
echo " Has NuttX been configured?"
exit 1
fi
# The NuttX build system creates a nuttx ELF file, but the batchisp tools
# expects the file to have a .elf extension
if [ ! -f nuttx.elf ]; then
if [ ! -f nuttx ]; then
echo "The NuttX ELF file (nuttx or nuttx.elf) does not exist in this directory."
echo " Has the NuttX binary been built?"
exit 1
fi
echo "Re-naming nuttx to nuttx.elf"
mv nuttx nuttx.elf || { echo "mv failed"; exit 1; }
else
if [ -f nuttx ]; then
echo "Replacing the old nuttx.elf with the new nuttx file."
mv nuttx nuttx.elf || { echo "mv failed"; exit 1; }
fi
fi
DEVICE=at32uc3a0512
ERASE="erase"
FLASH="flash nuttx.hex"
START="start"
# Invoke dfu-programmer
dfu-programmer $DEVICE $ERASE
dfu-programmer $DEVICE $FLASH
dfu-programmer $DEVICE $START