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cxd: use small lock

Browse source 
reason:
We would like to replace the big lock with a small lock.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5 2024-12-18 16:22:36 +08:00 committed by Xiang Xiao
parent c19e8c7861
commit f367ba2842
5 changed files with 48 additions and 30 deletions
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18
arch/arm/src/cxd32xx/cxd32_irq.c
View file

@ -53,6 +53,12 @@
#define INTC_EN(n) (CXD32_INTC_BASE + 0x10 + (((n) >> 5) << 2))
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_cxd32_lock = SP_UNLOCKED;
/****************************************************************************
* Public Data
****************************************************************************/
@ -74,7 +80,7 @@ static void cxd32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_cxd32_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
getreg32(NVIC_VECTAB));
@ -103,7 +109,7 @@ static void cxd32_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_cxd32_lock, flags);
}
#else
# define cxd32_dumpnvic(msg, irq)
@ -331,14 +337,14 @@ void up_disable_irq(int irq)
if (irq >= CXD32_IRQ_EXTINT)
{
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_cxd32_lock);
irq -= CXD32_IRQ_EXTINT;
bit = 1 << (irq & 0x1f);
regval = getreg32(INTC_EN(irq));
regval &= ~bit;
putreg32(regval, INTC_EN(irq));
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd32_lock, flags);
putreg32(bit, NVIC_IRQ_CLEAR(irq));
}
else
@ -370,14 +376,14 @@ void up_enable_irq(int irq)
if (irq >= CXD32_IRQ_EXTINT)
{
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_cxd32_lock);
irq -= CXD32_IRQ_EXTINT;
bit = 1 << (irq & 0x1f);
regval = getreg32(INTC_EN(irq));
regval |= bit;
putreg32(regval, INTC_EN(irq));
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd32_lock, flags);
putreg32(bit, NVIC_IRQ_ENABLE(irq));
}
else

6
arch/arm/src/cxd32xx/cxd32_uart.c
View file

@ -112,6 +112,8 @@ struct uartdev
* Private Data
****************************************************************************/
static spinlock_t g_cxd32xx_lock = SP_UNLOCKED;
static const struct uartdev g_uartdevs[] =
{
{
@ -270,7 +272,7 @@ void cxd32_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
uint32_t fbrd;
uint32_t lcr_h;
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);
div = (uint64_t)(basefreq);
div *= (uint64_t)(256);
@ -287,5 +289,5 @@ void cxd32_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
lcr_h = getreg32(uartbase + CXD32_UART_LCR_H);
putreg32(lcr_h, uartbase + CXD32_UART_LCR_H);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
}

20
arch/arm/src/cxd56xx/cxd56_gpioint.c
View file

@ -95,6 +95,8 @@
* Private Data
****************************************************************************/
static spinlock_t g_cxd56_lock = SP_UNLOCKED;
static xcpt_t g_isr[MAX_SLOT];
static uint32_t g_bothedge = 0;
@ -114,7 +116,7 @@ static int alloc_slot(int pin, bool isalloc)
: CXD56_TOPREG_IOCAPP_INTSEL0;
int offset = (pin < PIN_IS_CLK) ? 1 : 56;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&g_cxd56_lock);
for (slot = 0; slot < MAX_SYS_SLOT; slot++)
{
@ -144,12 +146,12 @@ static int alloc_slot(int pin, bool isalloc)
}
else
{
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
return -ENXIO; /* no space */
}
}
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
if (PIN_IS_CLK <= pin)
{
@ -309,13 +311,13 @@ static void invert_irq(int irq)
irqstate_t flags;
uint32_t val;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&g_cxd56_lock);
val = getreg32(CXD56_INTC_INVERT);
val ^= (1 << (irq - CXD56_IRQ_EXTINT));
putreg32(val, CXD56_INTC_INVERT);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
}
static bool inverted_irq(int irq)
@ -431,9 +433,9 @@ int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr,
irq_attach(irq, NULL, NULL);
g_isr[slot] = NULL;
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&g_cxd56_lock);
g_bothedge &= ~(1 << slot);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
return irq;
}
@ -447,9 +449,9 @@ int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr,
{
/* set GPIO pseudo both edge interrupt */
flags = spin_lock_irqsave(NULL);
flags = spin_lock_irqsave(&g_cxd56_lock);
g_bothedge |= (1 << slot);
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
/* detect the change from the current signal */

18
arch/arm/src/cxd56xx/cxd56_irq.c
View file

@ -100,6 +100,12 @@ const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
};
#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 */
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_cxd56_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -117,7 +123,7 @@ static void cxd56_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_cxd56_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
getreg32(NVIC_VECTAB));
@ -146,7 +152,7 @@ static void cxd56_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
}
#else
# define cxd56_dumpnvic(msg, irq)
@ -405,14 +411,14 @@ void up_disable_irq(int irq)
g_cpu_for_irq[irq] = -1;
#endif
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_cxd56_lock);
irq -= CXD56_IRQ_EXTINT;
bit = 1 << (irq & 0x1f);
regval = getreg32(INTC_EN(irq));
regval &= ~bit;
putreg32(regval, INTC_EN(irq));
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
putreg32(bit, NVIC_IRQ_CLEAR(irq));
}
else
@ -460,14 +466,14 @@ void up_enable_irq(int irq)
}
#endif
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_cxd56_lock);
irq -= CXD56_IRQ_EXTINT;
bit = 1 << (irq & 0x1f);
regval = getreg32(INTC_EN(irq));
regval |= bit;
putreg32(regval, INTC_EN(irq));
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd56_lock, flags);
putreg32(bit, NVIC_IRQ_ENABLE(irq));
}
else

16
arch/arm/src/cxd56xx/cxd56_uart.c
View file

@ -129,6 +129,8 @@ struct uartdev
* Private Data
****************************************************************************/
static spinlock_t g_cxd32xx_lock = SP_UNLOCKED;
static struct uartdev g_uartdevs[] =
{
{
@ -206,7 +208,7 @@ static void cxd56_uart_pincontrol(int ch, bool on)
static void cxd56_uart_start(int ch)
{
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);
cxd56_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
@ -214,7 +216,7 @@ static void cxd56_uart_start(int ch)
putreg32(g_cr, g_uartdevs[ch].uartbase + CXD56_UART_CR);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
}
/****************************************************************************
@ -230,7 +232,7 @@ static void cxd56_uart_stop(int ch)
{
uint32_t cr;
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);
while (UART_FR_BUSY & getreg32(g_uartdevs[ch].uartbase + CXD56_UART_FR));
@ -242,7 +244,7 @@ static void cxd56_uart_stop(int ch)
g_lcr = getreg32(g_uartdevs[ch].uartbase + CXD56_UART_LCR_H);
putreg32(0, g_uartdevs[ch].uartbase + CXD56_UART_LCR_H);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
}
/****************************************************************************
@ -463,7 +465,7 @@ void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
uint32_t div;
uint32_t lcr_h;
irqstate_t flags = spin_lock_irqsave(NULL);
irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);
if (uartbase == CXD56_UART2_BASE)
{
@ -475,7 +477,7 @@ void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
}
else
{
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
return;
}
@ -502,7 +504,7 @@ void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
putreg32(lcr_h, uartbase + CXD56_UART_LCR_H);
finish:
spin_unlock_irqrestore(NULL, flags);
spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
}
/****************************************************************************