nuttx/nuttx-update
1
2
Fork 1
Code Issues 1 Pull requests 1 Projects Releases Packages Wiki Activity Actions

Replace all occurrences of vdbg with vinfo

Browse source
This commit is contained in:
Gregory Nutt 2016-06-11 11:59:51 -06:00
parent 3a74a438d9
commit fc3540cffe
845 changed files with 5817 additions and 5817 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/src/a1x/a1x_serial.c
View file

@ -1156,7 +1156,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, A1X_UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
info("MSR: %02x\n", status);
break;
}
@ -1167,7 +1167,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, A1X_UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
info("LSR: %02x\n", status);
break;
}

2
arch/arm/src/arm/up_dataabort.c
View file

@ -142,7 +142,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* (It has not yet been saved in the register context save area).
*/
pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
{
goto segfault;

10
arch/arm/src/arm/up_elf.c
View file

@ -172,7 +172,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -201,7 +201,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@ -210,7 +210,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@ -225,7 +225,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@ -236,7 +236,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);

22
arch/arm/src/armv6-m/up_elf.c
View file

@ -168,7 +168,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -197,7 +197,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@ -245,7 +245,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
binfo("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@ -279,7 +279,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
bvdbg(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
binfo(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
S, J1, J2, (long)offset, offset + sym->st_value - addr);
offset += sym->st_value - addr;
@ -320,14 +320,14 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
binfo(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
S, J1, J2, (int)upper_insn, (int)lower_insn);
}
break;
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@ -342,7 +342,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@ -353,7 +353,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -408,7 +408,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
binfo("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@ -425,7 +425,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
bvdbg(" offset=%08lx branch target=%08lx\n",
binfo(" offset=%08lx branch target=%08lx\n",
(long)offset, offset + sym->st_value);
offset += sym->st_value;
@ -445,7 +445,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" insn [%04x %04x]\n",
binfo(" insn [%04x %04x]\n",
(int)upper_insn, (int)lower_insn);
}
break;

16
arch/arm/src/armv7-a/arm_addrenv.c
View file

@ -257,7 +257,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
{
int ret;
bvdbg("addrenv=%p textsize=%lu datasize=%lu\n",
binfo("addrenv=%p textsize=%lu datasize=%lu\n",
addrenv, (unsigned long)textsize, (unsigned long)datasize);
DEBUGASSERT(addrenv);
@ -353,7 +353,7 @@ errout:
int up_addrenv_destroy(FAR group_addrenv_t *addrenv)
{
bvdbg("addrenv=%p\n", addrenv);
binfo("addrenv=%p\n", addrenv);
DEBUGASSERT(addrenv);
/* Destroy the .text region */
@ -405,7 +405,7 @@ int up_addrenv_destroy(FAR group_addrenv_t *addrenv)
int up_addrenv_vtext(FAR group_addrenv_t *addrenv, FAR void **vtext)
{
bvdbg("return=%p\n", (FAR void *)CONFIG_ARCH_TEXT_VBASE);
binfo("return=%p\n", (FAR void *)CONFIG_ARCH_TEXT_VBASE);
/* Not much to do in this case */
@ -439,7 +439,7 @@ int up_addrenv_vtext(FAR group_addrenv_t *addrenv, FAR void **vtext)
int up_addrenv_vdata(FAR group_addrenv_t *addrenv, uintptr_t textsize,
FAR void **vdata)
{
bvdbg("return=%p\n",
binfo("return=%p\n",
(FAR void *)(CONFIG_ARCH_DATA_VBASE + ARCH_DATA_RESERVE_SIZE));
/* Not much to do in this case */
@ -636,7 +636,7 @@ int up_addrenv_restore(FAR const save_addrenv_t *oldenv)
uintptr_t vaddr;
int i;
bvdbg("oldenv=%p\n", oldenv);
binfo("oldenv=%p\n", oldenv);
DEBUGASSERT(oldenv);
for (vaddr = CONFIG_ARCH_TEXT_VBASE, i = 0;
@ -752,7 +752,7 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
int up_addrenv_clone(FAR const group_addrenv_t *src,
FAR group_addrenv_t *dest)
{
bvdbg("src=%p dest=%p\n", src, dest);
binfo("src=%p dest=%p\n", src, dest);
DEBUGASSERT(src && dest);
/* Just copy the address environment from the source to the destination */
@ -784,7 +784,7 @@ int up_addrenv_clone(FAR const group_addrenv_t *src,
int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
{
bvdbg("group=%p tcb=%p\n", group, tcb);
binfo("group=%p tcb=%p\n", group, tcb);
/* Nothing needs to be done in this implementation */
@ -817,7 +817,7 @@ int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
int up_addrenv_detach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
{
bvdbg("group=%p tcb=%p\n", group, tcb);
binfo("group=%p tcb=%p\n", group, tcb);
/* Nothing needs to be done in this implementation */

4
arch/arm/src/armv7-a/arm_addrenv_kstack.c
View file

@ -144,7 +144,7 @@
int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
{
bvdbg("tcb=%p stacksize=%u\n", tcb, ARCH_KERNEL_STACKSIZE);
binfo("tcb=%p stacksize=%u\n", tcb, ARCH_KERNEL_STACKSIZE);
DEBUGASSERT(tcb && tcb->xcp.kstack == 0);
@ -177,7 +177,7 @@ int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
int up_addrenv_kstackfree(FAR struct tcb_s *tcb)
{
bvdbg("tcb=%p\n", tcb);
binfo("tcb=%p\n", tcb);
DEBUGASSERT(tcb);
/* Does the exiting thread have a kernel stack? */

4
arch/arm/src/armv7-a/arm_addrenv_shm.c
View file

@ -92,7 +92,7 @@ int up_shmat(FAR uintptr_t *pages, unsigned int npages, uintptr_t vaddr)
unsigned int nmapped;
unsigned int shmndx;
shmvdbg("pages=%p npages=%d vaddr=%08lx\n",
shminfo("pages=%p npages=%d vaddr=%08lx\n",
pages, npages, (unsigned long)vaddr);
/* Sanity checks */
@ -241,7 +241,7 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages)
unsigned int nunmapped;
unsigned int shmndx;
shmvdbg("npages=%d vaddr=%08lx\n", npages, (unsigned long)vaddr);
shminfo("npages=%d vaddr=%08lx\n", npages, (unsigned long)vaddr);
/* Sanity checks */

6
arch/arm/src/armv7-a/arm_addrenv_ustack.c
View file

@ -143,7 +143,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
{
int ret;
bvdbg("tcb=%p stacksize=%lu\n", tcb, (unsigned long)stacksize);
binfo("tcb=%p stacksize=%lu\n", tcb, (unsigned long)stacksize);
DEBUGASSERT(tcb);
@ -190,7 +190,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
int up_addrenv_ustackfree(FAR struct tcb_s *tcb)
{
bvdbg("tcb=%p\n", tcb);
binfo("tcb=%p\n", tcb);
DEBUGASSERT(tcb);
/* Destroy the stack region */
@ -221,7 +221,7 @@ int up_addrenv_ustackfree(FAR struct tcb_s *tcb)
int up_addrenv_vustack(FAR const struct tcb_s *tcb, FAR void **vstack)
{
bvdbg("Return=%p\n", (FAR void *)CONFIG_ARCH_STACK_VBASE);
binfo("Return=%p\n", (FAR void *)CONFIG_ARCH_STACK_VBASE);
/* Not much to do in this case */

4
arch/arm/src/armv7-a/arm_addrenv_utils.c
View file

@ -84,7 +84,7 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
unsigned int i;
unsigned int j;
bvdbg("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
binfo("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
listlen, (unsigned long)vaddr, (unsigned long)regionsize,
(unsigned int)mmuflags);
@ -201,7 +201,7 @@ void arm_addrenv_destroy_region(FAR uintptr_t **list, unsigned int listlen,
int i;
int j;
bvdbg("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
binfo("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
for (i = 0; i < listlen; vaddr += SECTION_SIZE, list++, i++)
{

4
arch/arm/src/armv7-a/arm_cpustart.c
View file

@ -106,7 +106,7 @@ int arm_start_handler(int irq, FAR void *context)
{
FAR struct tcb_s *tcb;
sllvdbg("CPU%d Started\n", up_cpu_index());
sllinfo("CPU%d Started\n", up_cpu_index());
/* Reset scheduler parameters */
@ -155,7 +155,7 @@ int arm_start_handler(int irq, FAR void *context)
int up_cpu_start(int cpu)
{
sllvdbg("Starting CPU%d\n", cpu);
sllinfo("Starting CPU%d\n", cpu);
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());

2
arch/arm/src/armv7-a/arm_dataabort.c
View file

@ -126,7 +126,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* (It has not yet been saved in the register context save area).
*/
pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
{
goto segfault;

10
arch/arm/src/armv7-a/arm_elf.c
View file

@ -162,7 +162,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -191,7 +191,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@ -200,7 +200,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@ -215,7 +215,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@ -226,7 +226,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);

2
arch/arm/src/armv7-a/arm_gicv2.c
View file

@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
gicllvdbg("irq=%d\n", irq);
gicllinfo("irq=%d\n", irq);
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.

8
arch/arm/src/armv7-a/gic.h
View file

@ -596,13 +596,13 @@
#ifdef CONFIG_DEBUG_IRQ
# define gicdbg(format, ...) dbg(format, ##__VA_ARGS__)
# define giclldbg(format, ...) lldbg(format, ##__VA_ARGS__)
# define gicvdbg(format, ...) vdbg(format, ##__VA_ARGS__)
# define gicllvdbg(format, ...) llvdbg(format, ##__VA_ARGS__)
# define gicinfo(format, ...) info(format, ##__VA_ARGS__)
# define gicllinfo(format, ...) llinfo(format, ##__VA_ARGS__)
#else
# define gicdbg(x...)
# define giclldbg(x...)
# define gicvdbg(x...)
# define gicllvdbg(x...)
# define gicinfo(x...)
# define gicllinfo(x...)
#endif
/****************************************************************************

24
arch/arm/src/armv7-m/up_elf.c
View file

@ -164,7 +164,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -193,7 +193,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@ -204,7 +204,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_TARGET2: /* TARGET2 is a platform-specific relocation: gcc-arm-none-eabi
* performs a self relocation */
{
bvdbg("Performing TARGET2 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing TARGET2 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value - addr;
@ -253,7 +253,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
binfo("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@ -287,7 +287,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
bvdbg(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
binfo(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
S, J1, J2, (long)offset, offset + sym->st_value - addr);
offset += sym->st_value - addr;
@ -328,14 +328,14 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
binfo(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
S, J1, J2, (int)upper_insn, (int)lower_insn);
}
break;
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@ -350,7 +350,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@ -361,7 +361,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -416,7 +416,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
binfo("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@ -433,7 +433,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
bvdbg(" offset=%08lx branch target=%08lx\n",
binfo(" offset=%08lx branch target=%08lx\n",
(long)offset, offset + sym->st_value);
offset += sym->st_value;
@ -455,7 +455,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
(offset & 0x00ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" insn [%04x %04x]\n",
binfo(" insn [%04x %04x]\n",
(int)upper_insn, (int)lower_insn);
}
break;

6
arch/arm/src/armv7-m/up_ramvec_attach.c
View file

@ -60,10 +60,10 @@
#ifdef CONFIG_DEBUG_IRQ
# define intdbg lldbg
# define intvdbg llvdbg
# define intinfo llinfo
#else
# define intdbg(x...)
# define intvdbg(x...)
# define intinfo(x...)
#endif
/****************************************************************************
@ -103,7 +103,7 @@ int up_ramvec_attach(int irq, up_vector_t vector)
{
int ret = -EINVAL;
intvdbg("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
intinfo("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
if ((unsigned)irq < NR_VECTORS)
{

8
arch/arm/src/armv7-m/up_ramvec_initialize.c
View file

@ -79,10 +79,10 @@
#ifdef CONFIG_DEBUG_IRQ
# define intdbg lldbg
# define intvdbg llvdbg
# define intinfo llinfo
#else
# define intdbg(x...)
# define intvdbg(x...)
# define intinfo(x...)
#endif
/****************************************************************************
@ -147,7 +147,7 @@ void up_ramvec_initialize(void)
src = (const CODE up_vector_t *)getreg32(NVIC_VECTAB);
dest = g_ram_vectors;
intvdbg("src=%p dest=%p\n", src, dest);
intinfo("src=%p dest=%p\n", src, dest);
for (i = 0; i < ARMV7M_VECTAB_SIZE; i++)
{
@ -163,7 +163,7 @@ void up_ramvec_initialize(void)
* the table alignment is insufficient.
*/
intvdbg("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
intinfo("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
DEBUGASSERT(getreg32(NVIC_VECTAB) == (uint32_t)g_ram_vectors);
}

10
arch/arm/src/armv7-r/arm_elf.c
View file

@ -174,7 +174,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@ -203,7 +203,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@ -212,7 +212,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@ -227,7 +227,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@ -238,7 +238,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);

52
arch/arm/src/c5471/c5471_ethernet.c
View file

@ -417,7 +417,7 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, unsi
* defined or the following does nothing.
*/
nvdbgdumpbuffer(msg, buffer, nbytes);
ninfodumpbuffer(msg, buffer, nbytes);
}
#else
# define c5471_dumpbuffer(msg, buffer,nbytes)
@ -802,7 +802,7 @@ static inline void c5471_inctxcpu(struct c5471_driver_s *c5471)
c5471->c_txcpudesc += 2*sizeof(uint32_t);
}
nvdbg("TX CPU desc: %08x\n", c5471->c_txcpudesc);
ninfo("TX CPU desc: %08x\n", c5471->c_txcpudesc);
}
/****************************************************************************
@ -825,7 +825,7 @@ static inline void c5471_incrxcpu(struct c5471_driver_s *c5471)
c5471->c_rxcpudesc += 2*sizeof(uint32_t);
}
nvdbg("RX CPU desc: %08x\n", c5471->c_rxcpudesc);
ninfo("RX CPU desc: %08x\n", c5471->c_rxcpudesc);
}
/****************************************************************************
@ -861,7 +861,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
bfirstframe = true;
c5471->c_lastdescstart = c5471->c_rxcpudesc;
nvdbg("Packet size: %d RX CPU desc: %08x\n", nbytes, c5471->c_rxcpudesc);
ninfo("Packet size: %d RX CPU desc: %08x\n", nbytes, c5471->c_rxcpudesc);
c5471_dumpbuffer("Transmit packet", dev->d_buf, dev->d_len);
while (nbytes)
@ -918,7 +918,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
putreg32(((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen), c5471->c_rxcpudesc);
nbytes -= framelen;
nvdbg("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
ninfo("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
if (0 == nbytes)
{
@ -1092,43 +1092,43 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471)
if ((rxstatus & EIM_TXDESC_RETRYERROR) != 0)
{
c5471->c_rxretries++;
nvdbg("c_rxretries: %d\n", c5471->c_rxretries);
ninfo("c_rxretries: %d\n", c5471->c_rxretries);
}
if ((rxstatus & EIM_TXDESC_HEARTBEAT) != 0)
{
c5471->c_rxheartbeat++;
nvdbg("c_rxheartbeat: %d\n", c5471->c_rxheartbeat);
ninfo("c_rxheartbeat: %d\n", c5471->c_rxheartbeat);
}
if ((rxstatus & EIM_TXDESC_LCOLLISON) != 0)
{
c5471->c_rxlcollision++;
nvdbg("c_rxlcollision: %d\n", c5471->c_rxlcollision);
ninfo("c_rxlcollision: %d\n", c5471->c_rxlcollision);
}
if ((rxstatus & EIM_TXDESC_COLLISION) != 0)
{
c5471->c_rxcollision++;
nvdbg("c_rxcollision: %d\n", c5471->c_rxcollision);
ninfo("c_rxcollision: %d\n", c5471->c_rxcollision);
}
if ((rxstatus & EIM_TXDESC_CRCERROR) != 0)
{
c5471->c_rxcrc++;
nvdbg("c_rxcrc: %d\n", c5471->c_rxcrc);
ninfo("c_rxcrc: %d\n", c5471->c_rxcrc);
}
if ((rxstatus & EIM_TXDESC_UNDERRUN) != 0)
{
c5471->c_rxunderrun++;
nvdbg("c_rxunderrun: %d\n", c5471->c_rxunderrun);
ninfo("c_rxunderrun: %d\n", c5471->c_rxunderrun);
}
if ((rxstatus & EIM_TXDESC_LOC) != 0)
{
c5471->c_rxloc++;
nvdbg("c_rxloc: %d\n", c5471->c_rxloc);
ninfo("c_rxloc: %d\n", c5471->c_rxloc);
}
}
}
@ -1166,7 +1166,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
* the EIM for additional packets that might be received later from the network.
*/
nvdbg("Reading TX CPU desc: %08x\n", c5471->c_txcpudesc);
ninfo("Reading TX CPU desc: %08x\n", c5471->c_txcpudesc);
while (bmore)
{
/* Words #0 and #1 of descriptor */
@ -1196,7 +1196,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
/* Divide by 2 with round up to get the number of 16-bit words. */
nshorts = (framelen + 1) >> 1;
nvdbg("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
ninfo("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
framelen, packetlen, nshorts, packetmem);
for (i = 0 ; i < nshorts; i++, j++)
@ -1210,7 +1210,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
}
else
{
nvdbg("Discarding framelen: %d packetlen\n", framelen, packetlen);
ninfo("Discarding framelen: %d packetlen\n", framelen, packetlen);
}
if (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_LIF)
@ -1253,7 +1253,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
/* Set amount of data in c5471->c_dev.d_len. */
dev->d_len = packetlen;
nvdbg("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
ninfo("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
c5471_dumpbuffer("Received packet", dev->d_buf, dev->d_len);
#ifdef CONFIG_NET_PKT
@ -1267,7 +1267,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1310,7 +1310,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1432,43 +1432,43 @@ static void c5471_txstatus(struct c5471_driver_s *c5471)
if ((txstatus & EIM_RXDESC_MISS) != 0)
{
c5471->c_txmiss++;
nvdbg("c_txmiss: %d\n", c5471->c_txmiss);
ninfo("c_txmiss: %d\n", c5471->c_txmiss);
}
if ((txstatus & EIM_RXDESC_VLAN) != 0)
{
c5471->c_txvlan++;
nvdbg("c_txvlan: %d\n", c5471->c_txvlan);
ninfo("c_txvlan: %d\n", c5471->c_txvlan);
}
if ((txstatus & EIM_RXDESC_LFRAME) != 0)
{
c5471->c_txlframe++;
nvdbg("c_txlframe: %d\n", c5471->c_txlframe);
ninfo("c_txlframe: %d\n", c5471->c_txlframe);
}
if ((txstatus & EIM_RXDESC_SFRAME) != 0)
{
c5471->c_txsframe++;
nvdbg("c_txsframe: %d\n", c5471->c_txsframe);
ninfo("c_txsframe: %d\n", c5471->c_txsframe);
}
if ((txstatus & EIM_RXDESC_CRCERROR) != 0)
{
c5471->c_txcrc++;
nvdbg("c_txcrc: %d\n", c5471->c_txcrc);
ninfo("c_txcrc: %d\n", c5471->c_txcrc);
}
if ((txstatus & EIM_RXDESC_OVERRUN) != 0)
{
c5471->c_txoverrun++;
nvdbg("c_txoverrun: %d\n", c5471->c_txoverrun);
ninfo("c_txoverrun: %d\n", c5471->c_txoverrun);
}
if ((txstatus & EIM_RXDESC_OVERRUN) != 0)
{
c5471->c_txalign++;
nvdbg("c_txalign: %d\n", c5471->c_txalign);
ninfo("c_txalign: %d\n", c5471->c_txalign);
}
}
}
@ -1607,7 +1607,7 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...)
#ifdef CONFIG_C5471_NET_STATS
c5471->c_txtimeouts++;
nvdbg("c_txtimeouts: %d\n", c5471->c_txtimeouts);
ninfo("c_txtimeouts: %d\n", c5471->c_txtimeouts);
#endif
/* Then try to restart the hardware */

16
arch/arm/src/common/up_vfork.c
View file

@ -130,12 +130,12 @@ pid_t up_vfork(const struct vfork_s *context)
uint32_t stackutil;
int ret;
svdbg("vfork context [%p]:\n", context);
svdbg(" r4:%08x r5:%08x r6:%08x r7:%08x\n",
sinfo("vfork context [%p]:\n", context);
sinfo(" r4:%08x r5:%08x r6:%08x r7:%08x\n",
context->r4, context->r5, context->r6, context->r7);
svdbg(" r8:%08x r9:%08x r10:%08x\n",
sinfo(" r8:%08x r9:%08x r10:%08x\n",
context->r8, context->r9, context->r10);
svdbg(" fp:%08x sp:%08x lr:%08x\n",
sinfo(" fp:%08x sp:%08x lr:%08x\n",
context->fp, context->sp, context->lr);
/* Allocate and initialize a TCB for the child task. */
@ -147,7 +147,7 @@ pid_t up_vfork(const struct vfork_s *context)
return (pid_t)ERROR;
}
svdbg("TCBs: Parent=%p Child=%p\n", parent, child);
sinfo("TCBs: Parent=%p Child=%p\n", parent, child);
/* Get the size of the parent task's stack. Due to alignment operations,
* the adjusted stack size may be smaller than the stack size originally
@ -176,7 +176,7 @@ pid_t up_vfork(const struct vfork_s *context)
DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp);
stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
svdbg("Parent: stacksize:%d stackutil:%d\n", stacksize, stackutil);
sinfo("Parent: stacksize:%d stackutil:%d\n", stacksize, stackutil);
/* Make some feeble effort to preserve the stack contents. This is
* feeble because the stack surely contains invalid pointers and other
@ -201,9 +201,9 @@ pid_t up_vfork(const struct vfork_s *context)
newfp = context->fp;
}
svdbg("Parent: stack base:%08x SP:%08x FP:%08x\n",
sinfo("Parent: stack base:%08x SP:%08x FP:%08x\n",
parent->adj_stack_ptr, context->sp, context->fp);
svdbg("Child: stack base:%08x SP:%08x FP:%08x\n",
sinfo("Child: stack base:%08x SP:%08x FP:%08x\n",
child->cmn.adj_stack_ptr, newsp, newfp);
/* Update the stack pointer, frame pointer, and volatile registers. When

132
arch/arm/src/dm320/dm320_framebuffer.c
View file

@ -768,15 +768,15 @@ static void dm320_disable(void)
{
/* Disable all planes */
gvdbg("Inactivate OSD:\n");
ginfo("Inactivate OSD:\n");
putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */
putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */
putreg16(0, DM320_OSD_RECTCUR); /* Rectangular cursor mode = 0 (1:active) */
gvdbg("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
gvdbg("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
ginfo("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
ginfo("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
/****************************************************************************
@ -791,17 +791,17 @@ static void dm320_hwinitialize(void)
/* Initialize the main video to correct the origin */
gvdbg("Setup main video origin:\n");
ginfo("Setup main video origin:\n");
putreg16(CONFIG_DM320_BASEX, DM320_OSD_BASEPX);
putreg16(CONFIG_DM320_BASEY, DM320_OSD_BASEPY);
gvdbg("DM320_OSD_BASEPX: %04x\n", getreg16(DM320_OSD_BASEPX));
gvdbg("DM320_OSD_BASEPY: %04x\n", getreg16(DM320_OSD_BASEPY));
ginfo("DM320_OSD_BASEPX: %04x\n", getreg16(DM320_OSD_BASEPX));
ginfo("DM320_OSD_BASEPY: %04x\n", getreg16(DM320_OSD_BASEPY));
/* Set up the frame buffer address registers */
gvdbg("Setup framebuffer addresses:\n");
ginfo("Setup framebuffer addresses:\n");
putreg16(((dm320_osd1upperoffset() << 8) |
@ -809,9 +809,9 @@ static void dm320_hwinitialize(void)
putreg16(dm320_osd0loweroffset(), DM320_OSD_OSDWIN0ADL);
putreg16(dm320_osd1loweroffset(), DM320_OSD_OSDWIN1ADL);
gvdbg("DM320_OSD_OSDWINADH: %04x\n", getreg16(DM320_OSD_OSDWINADH));
gvdbg("DM320_OSD_OSDWIN0ADL: %04x\n", getreg16(DM320_OSD_OSDWIN0ADL));
gvdbg("DM320_OSD_OSDWIN1ADL: %04x\n", getreg16(DM320_OSD_OSDWIN1ADL));
ginfo("DM320_OSD_OSDWINADH: %04x\n", getreg16(DM320_OSD_OSDWINADH));
ginfo("DM320_OSD_OSDWIN0ADL: %04x\n", getreg16(DM320_OSD_OSDWIN0ADL));
ginfo("DM320_OSD_OSDWIN1ADL: %04x\n", getreg16(DM320_OSD_OSDWIN1ADL));
/* Set up VID WIN0 */
@ -820,19 +820,19 @@ static void dm320_hwinitialize(void)
#endif
#ifndef CONFIG_DM320_VID0_DISABLE
gvdbg("Initialize video win0:\n");
ginfo("Initialize video win0:\n");
putreg16(dm320_vid0loweroffset(), DM320_OSD_VIDWIN0ADL);
gvdbg("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
gvdbg("DM320_OSD_VIDWIN0ADL: %04x\n", getreg16(DM320_OSD_VIDWIN0ADL));
ginfo("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
ginfo("DM320_OSD_VIDWIN0ADL: %04x\n", getreg16(DM320_OSD_VIDWIN0ADL));
dm320_blankscreen((uint8_t *)g_vid0base, DM320_VID0_FBLEN);
#ifndef CONFIG_DM320_DISABLE_PINGPONG
putreg16(dm320_vid0ppupperoffset(), DM320_OSD_PPVWIN0ADH);
putreg16(dm320_vid0pploweroffset(), DM320_OSD_PPVWIN0ADL);
gvdbg("DM320_OSD_PPVWIN0ADH: %04x\n", getreg16(DM320_OSD_PPVWIN0ADH));
gvdbg("DM320_OSD_PPVWIN0ADL: %04x\n", getreg16(DM320_OSD_PPVWIN0ADL));
ginfo("DM320_OSD_PPVWIN0ADH: %04x\n", getreg16(DM320_OSD_PPVWIN0ADH));
ginfo("DM320_OSD_PPVWIN0ADL: %04x\n", getreg16(DM320_OSD_PPVWIN0ADL));
dm320_blankscreen((uint8_t *)g_vid0ppbase, DM320_VID0_FBLEN);
#endif
@ -842,21 +842,21 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_VID0_XRES, DM320_OSD_VIDWIN0XL);
putreg16(CONFIG_DM320_VID0_YRES, DM320_OSD_VIDWIN0YL);
gvdbg("DM320_OSD_VIDWIN0XP: %04x\n", getreg16(DM320_OSD_VIDWIN0XP));
gvdbg("DM320_OSD_VIDWIN0YP: %04x\n", getreg16(DM320_OSD_VIDWIN0YP));
gvdbg("DM320_OSD_VIDWIN0OFST: %04x\n", getreg16(DM320_OSD_VIDWIN0OFST));
gvdbg("DM320_OSD_VIDWIN0XL: %04x\n", getreg16(DM320_OSD_VIDWIN0XL));
gvdbg("DM320_OSD_VIDWIN0YL: %04x\n", getreg16(DM320_OSD_VIDWIN0YL));
ginfo("DM320_OSD_VIDWIN0XP: %04x\n", getreg16(DM320_OSD_VIDWIN0XP));
ginfo("DM320_OSD_VIDWIN0YP: %04x\n", getreg16(DM320_OSD_VIDWIN0YP));
ginfo("DM320_OSD_VIDWIN0OFST: %04x\n", getreg16(DM320_OSD_VIDWIN0OFST));
ginfo("DM320_OSD_VIDWIN0XL: %04x\n", getreg16(DM320_OSD_VIDWIN0XL));
ginfo("DM320_OSD_VIDWIN0YL: %04x\n", getreg16(DM320_OSD_VIDWIN0YL));
#endif
/* Set up VID WIN1 */
#ifndef CONFIG_DM320_VID1_DISABLE
gvdbg("Initialize video win1:\n");
ginfo("Initialize video win1:\n");
putreg16(dm320_vid1loweroffset(), DM320_OSD_VIDWIN1ADL);
gvdbg("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
gvdbg("DM320_OSD_VIDWIN1ADL: %04x\n", getreg16(DM320_OSD_VIDWIN1ADL));
ginfo("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
ginfo("DM320_OSD_VIDWIN1ADL: %04x\n", getreg16(DM320_OSD_VIDWIN1ADL));
dm320_blankscreen((uint8_t *)g_vid1base, DM320_VID1_FBLEN);
putreg16(CONFIG_DM320_VID1_XPOS, DM320_OSD_VIDWIN1XP);
@ -865,20 +865,20 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_VID1_XRES, DM320_OSD_VIDWIN1XL);
putreg16(CONFIG_DM320_VID1_YRES, DM320_OSD_VIDWIN1YL);
gvdbg("DM320_OSD_VIDWIN1XP: %04x\n", getreg16(DM320_OSD_VIDWIN1XP));
gvdbg("DM320_OSD_VIDWIN1YP: %04x\n", getreg16(DM320_OSD_VIDWIN1YP));
gvdbg("DM320_OSD_VIDWIN1OFST: %04x\n", getreg16(DM320_OSD_VIDWIN1OFST));
gvdbg("DM320_OSD_VIDWIN1XL: %04x\n", getreg16(DM320_OSD_VIDWIN1XL));
gvdbg("DM320_OSD_VIDWIN1YL: %04x\n", getreg16(DM320_OSD_VIDWIN1YL));
ginfo("DM320_OSD_VIDWIN1XP: %04x\n", getreg16(DM320_OSD_VIDWIN1XP));
ginfo("DM320_OSD_VIDWIN1YP: %04x\n", getreg16(DM320_OSD_VIDWIN1YP));
ginfo("DM320_OSD_VIDWIN1OFST: %04x\n", getreg16(DM320_OSD_VIDWIN1OFST));
ginfo("DM320_OSD_VIDWIN1XL: %04x\n", getreg16(DM320_OSD_VIDWIN1XL));
ginfo("DM320_OSD_VIDWIN1YL: %04x\n", getreg16(DM320_OSD_VIDWIN1YL));
#endif
putreg16(DM320_VIDMODE, DM320_OSD_VIDWINMD);
gvdbg("DM320_OSD_VIDWINMD: %04x\n", getreg16(DM320_OSD_VIDWINMD));
ginfo("DM320_OSD_VIDWINMD: %04x\n", getreg16(DM320_OSD_VIDWINMD));
/* Set up OSD WIN0 */
#ifndef CONFIG_DM320_OSD0_DISABLE
gvdbg("Initialize OSD win0:\n");
ginfo("Initialize OSD win0:\n");
dm320_blankscreen((uint8_t *)g_osd0base, DM320_OSD0_FBLEN);
putreg16(CONFIG_DM320_OSD0_XPOS, DM320_OSD_OSDWIN0XP);
@ -892,18 +892,18 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_OSD0_YRES, DM320_OSD_OSDWIN0YL);
putreg16(INITIAL_OSD0MODE, DM320_OSD_OSDWIN0MD);
gvdbg("DM320_OSD_OSDWIN0XP: %04x\n", getreg16(DM320_OSD_OSDWIN0XP));
gvdbg("DM320_OSD_OSDWIN0YP: %04x\n", getreg16(DM320_OSD_OSDWIN0YP));
gvdbg("DM320_OSD_OSDWIN0OFST: %04x\n", getreg16(DM320_OSD_OSDWIN0OFST));
gvdbg("DM320_OSD_OSDWIN0XL: %04x\n", getreg16(DM320_OSD_OSDWIN0XL));
gvdbg("DM320_OSD_OSDWIN0YL: %04x\n", getreg16(DM320_OSD_OSDWIN0YL));
gvdbg("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
ginfo("DM320_OSD_OSDWIN0XP: %04x\n", getreg16(DM320_OSD_OSDWIN0XP));
ginfo("DM320_OSD_OSDWIN0YP: %04x\n", getreg16(DM320_OSD_OSDWIN0YP));
ginfo("DM320_OSD_OSDWIN0OFST: %04x\n", getreg16(DM320_OSD_OSDWIN0OFST));
ginfo("DM320_OSD_OSDWIN0XL: %04x\n", getreg16(DM320_OSD_OSDWIN0XL));
ginfo("DM320_OSD_OSDWIN0YL: %04x\n", getreg16(DM320_OSD_OSDWIN0YL));
ginfo("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
#endif
/* Set up OSD WIN1 */
#ifndef CONFIG_DM320_OSD1_DISABLE
gvdbg("Initialize OSD win1\n");
ginfo("Initialize OSD win1\n");
dm320_blankscreen((uint8_t *)g_osd1base, DM320_OSD1_FBLEN);
putreg16(CONFIG_DM320_OSD1_XPOS, DM320_OSD_OSDWIN1XP);
@ -917,12 +917,12 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_OSD1_YRES, DM320_OSD_OSDWIN1YL);
putreg16(INITIAL_OSD1MODE, DM320_OSD_OSDWIN1MD);
gvdbg("DM320_OSD_OSDWIN1XP: %04x\n", getreg16(DM320_OSD_OSDWIN1XP));
gvdbg("DM320_OSD_OSDWIN1YP: %04x\n", getreg16(DM320_OSD_OSDWIN1YP));
gvdbg("DM320_OSD_OSDWIN1OFST: %04x\n", getreg16(DM320_OSD_OSDWIN1OFST));
gvdbg("DM320_OSD_OSDWIN1XL: %04x\n", getreg16(DM320_OSD_OSDWIN1XL));
gvdbg("DM320_OSD_OSDWIN1YL: %04x\n", getreg16(DM320_OSD_OSDWIN1YL));
gvdbg("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
ginfo("DM320_OSD_OSDWIN1XP: %04x\n", getreg16(DM320_OSD_OSDWIN1XP));
ginfo("DM320_OSD_OSDWIN1YP: %04x\n", getreg16(DM320_OSD_OSDWIN1YP));
ginfo("DM320_OSD_OSDWIN1OFST: %04x\n", getreg16(DM320_OSD_OSDWIN1OFST));
ginfo("DM320_OSD_OSDWIN1XL: %04x\n", getreg16(DM320_OSD_OSDWIN1XL));
ginfo("DM320_OSD_OSDWIN1YL: %04x\n", getreg16(DM320_OSD_OSDWIN1YL));
ginfo("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
#endif
/* Set up the rectangular cursor with defaults */
@ -946,11 +946,11 @@ static void dm320_hwinitialize(void)
putreg16(DM320_RECTCURSOR_SETUP, DM320_OSD_RECTCUR);
gvdbg("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
gvdbg("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
ginfo("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
ginfo("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
ginfo("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
ginfo("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
#endif
/* Set main window to the hardware default state. That initial
@ -969,7 +969,7 @@ static void dm320_hwinitialize(void)
*/
putreg16(CONFIG_DM320_BKGDCLUT, DM320_OSD_OSDMODE);
gvdbg("DM320_OSD_OSDMODE: %04x\n", getreg16(DM320_OSD_OSDMODE));
ginfo("DM320_OSD_OSDMODE: %04x\n", getreg16(DM320_OSD_OSDMODE));
}
/****************************************************************************
@ -1265,16 +1265,16 @@ static int dm320_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursora
attrib->mxsize.w = MAX_XRES;
attrib->mxsize.h = MAX_YRES;
gvdbg("DM320_OSD_CURXP: %04x\n", attrib->pos.x);
gvdbg("DM320_OSD_CURYP: %04x\n", attrib->pos.y);
ginfo("DM320_OSD_CURXP: %04x\n", attrib->pos.x);
ginfo("DM320_OSD_CURYP: %04x\n", attrib->pos.y);
#ifdef CONFIG_FB_HWCURSORSIZE
gvdbg("DM320_OSD_CURXL: %04x\n", attrib->size.w);
gvdbg("DM320_OSD_CURYL: %04x\n", attrib->size.h);
ginfo("DM320_OSD_CURXL: %04x\n", attrib->size.w);
ginfo("DM320_OSD_CURYL: %04x\n", attrib->size.h);
#else
gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
ginfo("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
ginfo("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
#endif
gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
#endif
@ -1300,7 +1300,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
flags = enter_critical_section();
if ((settings->flags & FB_CUR_SETPOSITION) != 0)
{
gvdbg("x=%d y=%d\n", settings->pos.x, settings->pos.y);
ginfo("x=%d y=%d\n", settings->pos.x, settings->pos.y);
if (settings->pos.x > MAX_YRES)
{
@ -1319,7 +1319,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
#ifdef CONFIG_FB_HWCURSORSIZE
if ((settings->flags & FB_CUR_SETSIZE) != 0)
{
gvdbg("h=%d w=%d\n", settings->size.h, settings->size.w);
ginfo("h=%d w=%d\n", settings->size.h, settings->size.w);
if (settings->size.w > MAX_YRES)
{
@ -1349,11 +1349,11 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
putreg16(regval, DM320_OSD_RECTCUR);
leave_critical_section(flags);
gvdbg("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
gvdbg("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
ginfo("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
ginfo("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
ginfo("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
ginfo("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
#endif
@ -1381,7 +1381,7 @@ int up_fbinitialize(int display)
{
int ret;
gvdbg("Allocating framebuffers\n");
ginfo("Allocating framebuffers\n");
ret = dm320_allocvideomemory();
if (ret != 0)
{
@ -1391,7 +1391,7 @@ int up_fbinitialize(int display)
/* Initialize the hardware */
gvdbg("Initializing hardware\n");
ginfo("Initializing hardware\n");
dm320_hwinitialize();
return 0;
}

4
arch/arm/src/dm320/dm320_usbdev.c
View file

@ -1216,7 +1216,7 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
value = GETUINT16(ctrl.value);
len = GETUINT16(ctrl.len);
ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1618,7 +1618,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context)
}
else
{
ullvdbg("Pending data on OUT endpoint\n");
ullinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}

36
arch/arm/src/efm32/efm32_adc.c
View file

@ -717,22 +717,22 @@ endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
static void adc_tim_dumpregs(struct efm32_dev_s *priv, FAR const char *msg)
{
#if defined(CONFIG_DEBUG_ANALOG) && defined(CONFIG_DEBUG_INFO)
avdbg("%s:\n", msg);
avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
ainfo("%s:\n", msg);
ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
tim_getreg(priv, EFM32_GTIM_CR1_OFFSET),
tim_getreg(priv, EFM32_GTIM_CR2_OFFSET),
tim_getreg(priv, EFM32_GTIM_SMCR_OFFSET),
tim_getreg(priv, EFM32_GTIM_DIER_OFFSET));
avdbg(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
tim_getreg(priv, EFM32_GTIM_SR_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCMR1_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCMR2_OFFSET));
avdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
tim_getreg(priv, EFM32_GTIM_CCER_OFFSET),
tim_getreg(priv, EFM32_GTIM_CNT_OFFSET),
tim_getreg(priv, EFM32_GTIM_PSC_OFFSET),
tim_getreg(priv, EFM32_GTIM_ARR_OFFSET));
avdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
tim_getreg(priv, EFM32_GTIM_CCR1_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCR2_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCR3_OFFSET),
@ -740,7 +740,7 @@ static void adc_tim_dumpregs(struct efm32_dev_s *priv, FAR const char *msg)
if (priv->tbase == EFM32_TIM1_BASE || priv->tbase == EFM32_TIM8_BASE)
{
avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
tim_getreg(priv, EFM32_ATIM_RCR_OFFSET),
tim_getreg(priv, EFM32_ATIM_BDTR_OFFSET),
tim_getreg(priv, EFM32_ATIM_DCR_OFFSET),
@ -748,7 +748,7 @@ static void adc_tim_dumpregs(struct efm32_dev_s *priv, FAR const char *msg)
}
else
{
avdbg(" DCR: %04x DMAR: %04x\n",
ainfo(" DCR: %04x DMAR: %04x\n",
tim_getreg(priv, EFM32_GTIM_DCR_OFFSET),
tim_getreg(priv, EFM32_GTIM_DMAR_OFFSET));
}
@ -775,7 +775,7 @@ static void adc_startconv(struct efm32_dev_s *priv, bool enable)
{
uint32_t regval;
avdbg("enable: %d\n", enable);
ainfo("enable: %d\n", enable);
regval = adc_getreg(priv, EFM32_ADC_CR2_OFFSET);
if (enable)
@ -864,7 +864,7 @@ static void adc_enable(FAR struct efm32_dev_s *priv, bool enable)
{
uint32_t regval;
avdbg("enable: %d\n", enable);
ainfo("enable: %d\n", enable);
regval = adc_getreg(priv, EFM32_ADC_CR2_OFFSET);
if (enable)
@ -922,7 +922,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
int ret;
#endif
avdbg("intf: ADC%d\n", priv->intf);
ainfo("intf: ADC%d\n", priv->intf);
flags = enter_critical_section();
/* Enable ADC reset state */
@ -1040,11 +1040,11 @@ static void adc_reset(FAR struct adc_dev_s *dev)
leave_critical_section(flags);
avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
adc_getreg(priv, EFM32_ADC_SR_OFFSET),
adc_getreg(priv, EFM32_ADC_CR1_OFFSET),
adc_getreg(priv, EFM32_ADC_CR2_OFFSET));
avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
adc_getreg(priv, EFM32_ADC_SQR1_OFFSET),
adc_getreg(priv, EFM32_ADC_SQR2_OFFSET),
adc_getreg(priv, EFM32_ADC_SQR3_OFFSET));
@ -1081,7 +1081,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
/* Enable the ADC interrupt */
avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
up_enable_irq(priv->irq);
}
@ -1132,7 +1132,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv;
uint32_t regval;
avdbg("intf: %d enable: %d\n", priv->intf, enable);
ainfo("intf: %d enable: %d\n", priv->intf, enable);
regval = adc_getreg(priv, EFM32_ADC_CR1_OFFSET);
if (enable)
@ -1271,12 +1271,12 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
FAR struct adc_dev_s *dev;
FAR struct efm32_dev_s *priv;
avdbg("intf: %d nchannels: %d\n", intf, nchannels);
ainfo("intf: %d nchannels: %d\n", intf, nchannels);
#ifdef CONFIG_EFM32_ADC1
if (intf == 1)
{
avdbg("ADC1 Selected\n");
ainfo("ADC1 Selected\n");
dev = &g_adcdev1;
}
else
@ -1284,7 +1284,7 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
#ifdef CONFIG_EFM32_ADC2
if (intf == 2)
{
avdbg("ADC2 Selected\n");
ainfo("ADC2 Selected\n");
dev = &g_adcdev2;
}
else
@ -1292,7 +1292,7 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
#ifdef CONFIG_EFM32_ADC3
if (intf == 3)
{
avdbg("ADC3 Selected\n");
ainfo("ADC3 Selected\n");
dev = &g_adcdev3;
}
else

4
arch/arm/src/efm32/efm32_dma.c
View file

@ -270,7 +270,7 @@ void weak_function up_dmainitialize(void)
uint32_t regval;
int i;
dmallvdbg("Initialize XDMAC0\n");
dmallinfo("Initialize XDMAC0\n");
/* Initialize the channel list */
@ -416,7 +416,7 @@ void efm32_dmafree(DMA_HANDLE handle)
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
DEBUGASSERT(dmach != NULL && dmach->inuse);
dmavdbg("DMA channel %d\n", dmach->chan);
dmainfo("DMA channel %d\n", dmach->chan);
/* Disable the channel */

8
arch/arm/src/efm32/efm32_i2c.c
View file

@ -138,10 +138,10 @@
#ifdef CONFIG_DEBUG_I2C
# define i2cdbg dbg
# define i2cvdbg vdbg
# define i2cinfo info
#else
# define i2cdbg(x...)
# define i2cvdbg(x...)
# define i2cinfo(x...)
#endif
/* I2C event trace logic. NOTE: trace uses the internal, non-standard,
@ -605,7 +605,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
while (priv->result == I2CRESULT_INPROGRESS);
i2cvdbg("result: %s elapsed: %d threshold: %d i2c_state %s "
i2cinfo("result: %s elapsed: %d threshold: %d i2c_state %s "
"I2Cx_STATES: %08x I2Cx_IF: %08x\n",
efm32_i2c_result_str(priv->result), elapsed, timeout,
efm32_i2c_state_str(priv->i2c_state), priv->i2c_reg_state,
@ -652,7 +652,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
while ((priv->result == I2CRESULT_INPROGRESS) && elapsed < timeout);
i2cvdbg("result: %s elapsed: %d threshold: %d i2c_state %s "
i2cinfo("result: %s elapsed: %d threshold: %d i2c_state %s "
"I2Cx_STATES: %08x I2Cx_IF: %08x\n",
efm32_i2c_result_str(priv->result), elapsed, timeout,
efm32_i2c_state_str(priv->i2c_state), priv->i2c_reg_state,

2
arch/arm/src/efm32/efm32_idle.c
View file

@ -110,7 +110,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

42
arch/arm/src/efm32/efm32_pwm.c
View file

@ -85,19 +85,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) efm32_dumpgpio(p,m)
# else
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif
@ -329,23 +329,23 @@ static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
/* TODO debug pwm_dumpregs */
#if 0
pwmvdbg("%s:\n", msg);
pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwminfo("%s:\n", msg);
pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
pwmvdbg(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
pwmvdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
pwm_getreg(priv, STM32_GTIM_PSC_OFFSET),
pwm_getreg(priv, STM32_GTIM_ARR_OFFSET));
pwmvdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
@ -353,7 +353,7 @@ static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, STM32_ATIM_RCR_OFFSET),
pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET),
pwm_getreg(priv, STM32_ATIM_DCR_OFFSET),
@ -362,7 +362,7 @@ static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
else
#endif
{
pwmvdbg(" DCR: %04x DMAR: %04x\n",
pwminfo(" DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
@ -396,11 +396,11 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
#ifdef CONFIG_PWM_PULSECOUNT
pwmvdbg("TIMER%d channel: %d frequency: %d duty: %08x count: %d\n",
pwminfo("TIMER%d channel: %d frequency: %d duty: %08x count: %d\n",
priv->timid, priv->channel, info->frequency,
info->duty, info->count);
#else
pwmvdbg("TIMER%d channel: %d frequency: %d duty: %08x\n",
pwminfo("TIMER%d channel: %d frequency: %d duty: %08x\n",
priv->timid, priv->channel, info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0 && info->duty >= 0 &&
@ -541,7 +541,7 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
/* Now all of the time critical stuff is done so we can do some debug output */
pwmllvdbg("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
pwmllinfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
regval, priv->prev, priv->curr, priv->count);
return OK;
@ -669,7 +669,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
{
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
pwmvdbg("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwminfo("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwm_dumpregs(priv, "Initially");
/* Configure the PWM output pin, but do not start the timer yet */
@ -726,7 +726,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
uint32_t pincfg;
pwmvdbg("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwminfo("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@ -805,7 +805,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
irqstate_t flags;
pwmvdbg("TIMER%d\n", priv->timid);
pwminfo("TIMER%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@ -848,7 +848,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
/* There are no platform-specific ioctl commands */
pwmvdbg("TIMER%d\n", priv->timid);
pwminfo("TIMER%d\n", priv->timid);
#endif
return -ENOTTY;
}
@ -878,7 +878,7 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
{
FAR struct efm32_pwmtimer_s *lower;
pwmvdbg("TIMER%d\n", timer);
pwminfo("TIMER%d\n", timer);
switch (timer)
{

6
arch/arm/src/efm32/efm32_rmu.h
View file

@ -58,13 +58,13 @@
#ifdef CONFIG_EFM32_RMU_DEBUG
# define rmudbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define rmuvdbg lldbg
# define rmuinfo lldbg
# else
# define rmuvdbg(x...)
# define rmuinfo(x...)
# endif
#else
# define rmudbg(x...)
# define rmuvdbg(x...)
# define rmuinfo(x...)
#endif
/****************************************************************************

22
arch/arm/src/efm32/efm32_spi.c
View file

@ -102,13 +102,13 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/****************************************************************************
@ -897,7 +897,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
*/
actual = (BOARD_HFPERCLK_FREQUENCY << 7) / (256 + clkdiv);
spivdbg("frequency=%u actual=%u\n", frequency, actual);
spiinfo("frequency=%u actual=%u\n", frequency, actual);
/* Save the frequency selection so that subsequent reconfigurations
* will be faster.
@ -932,7 +932,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t setting;
uint32_t regval;
spivdbg("mode=%d\n", mode);
spiinfo("mode=%d\n", mode);
DEBUGASSERT(priv && priv->config);
config = priv->config;
@ -998,7 +998,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
uint32_t setting;
bool lsbfirst;
spivdbg("nbits=%d\n", nbits);
spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && priv->config);
config = priv->config;
@ -1222,7 +1222,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
spi_wait_status(config, _USART_STATUS_RXDATAV_MASK, USART_STATUS_RXDATAV);
ret = (uint16_t)spi_getreg(config, EFM32_USART_RXDATA_OFFSET);
spivdbg("Sent: %04x Return: %04x \n", wd, ret);
spiinfo("Sent: %04x Return: %04x \n", wd, ret);
return ret;
}
@ -1263,7 +1263,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
DEBUGASSERT(priv && priv->config);
config = priv->config;
spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Flush any unread data */
@ -1427,7 +1427,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
else
#endif
{
spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n",
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
txbuffer, rxbuffer, nwords);
/* Pre-calculate the timeout value */
@ -1492,7 +1492,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer,
size_t nwords)
{
spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords);
return spi_exchange(dev, txbuffer, NULL, nwords);
}
#endif
@ -1521,7 +1521,7 @@ static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer,
static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer,
size_t nwords)
{
spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
return spi_exchange(dev, NULL, rxbuffer, nwords);
}
#endif

22
arch/arm/src/efm32/efm32_timer.c
View file

@ -71,19 +71,19 @@
# define efm32_timerdbg dbg
# define efm32_timerlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define efm32_timervdbg vdbg
# define efm32_timerllvdbg llvdbg
# define efm32_timerinfo info
# define efm32_timerllinfo llinfo
# define efm32_timer_dumpgpio(p,m) efm32_dumpgpio(p,m)
# else
# define efm32_timerlldbg(x...)
# define efm32_timerllvdbg(x...)
# define efm32_timerllinfo(x...)
# define efm32_timer_dumpgpio(p,m)
# endif
#else
# define efm32_timerdbg(x...)
# define efm32_timerlldbg(x...)
# define efm32_timervdbg(x...)
# define efm32_timerllvdbg(x...)
# define efm32_timerinfo(x...)
# define efm32_timerllinfo(x...)
# define efm32_timer_dumpgpio(p,m)
#endif
@ -121,14 +121,14 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
{
int i;
efm32_timervdbg("%s:\n", msg);
efm32_timervdbg(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n",
efm32_timerinfo("%s:\n", msg);
efm32_timerinfo(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n",
getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
getreg32(base + EFM32_TIMER_IEN_OFFSET ),
getreg32(base + EFM32_TIMER_IF_OFFSET )
);
efm32_timervdbg(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n",
efm32_timerinfo(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n",
getreg32(base + EFM32_TIMER_TOP_OFFSET ),
getreg32(base + EFM32_TIMER_TOPB_OFFSET ),
getreg32(base + EFM32_TIMER_CNT_OFFSET ),
@ -140,7 +140,7 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
#if defined(CONFIG_DEBUG_TIMER) && defined(CONFIG_DEBUG_INFO)
uintptr_t base_cc = base + EFM32_TIMER_CC_OFFSET(i);
#endif
efm32_timervdbg("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n",
efm32_timerinfo("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n",
i
getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET ),
getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET ),
@ -149,13 +149,13 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
);
}
efm32_timervdbg("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n",
efm32_timerinfo("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n",
getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
getreg32(base + EFM32_TIMER_IEN_OFFSET ),
getreg32(base + EFM32_TIMER_IF_OFFSET )
);
efm32_timervdbg("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n",
efm32_timerinfo("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n",
getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
getreg32(base + EFM32_TIMER_IEN_OFFSET ),

14
arch/arm/src/efm32/efm32_usbdev.c
View file

@ -1220,7 +1220,7 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv,
return;
}
ullvdbg("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
privep->epphy, privreq, privreq->req.len,
privreq->req.xfrd, privep->zlp);
@ -1486,7 +1486,7 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv,
return;
}
ullvdbg("EP%d: len=%d xfrd=%d\n",
ullinfo("EP%d: len=%d xfrd=%d\n",
privep->epphy, privreq->req.len, privreq->req.xfrd);
/* Return the completed read request to the class driver and mark the state
@ -1521,7 +1521,7 @@ static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt)
DEBUGASSERT(privep && privep->ep.priv);
priv = (FAR struct efm32_usbdev_s *)privep->ep.priv;
ullvdbg("EP0: bcnt=%d\n", bcnt);
ullinfo("EP0: bcnt=%d\n", bcnt);
usbtrace(TRACE_READ(EP0), bcnt);
/* Verify that an OUT SETUP request as received before this data was
@ -1614,7 +1614,7 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt)
return;
}
ullvdbg("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
usbtrace(TRACE_READ(privep->epphy), bcnt);
/* Get the number of bytes to transfer from the RxFIFO */
@ -1698,7 +1698,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv,
return;
}
ullvdbg("EP%d: len=%d\n", privep->epphy, privreq->req.len);
ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
/* Ignore any attempt to receive a zero length packet (this really
* should not happen.
@ -2494,7 +2494,7 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
ctrlreq.index = GETUINT16(priv->ctrlreq.index);
ctrlreq.len = GETUINT16(priv->ctrlreq.len);
ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
/* Check for a standard request */
@ -4333,7 +4333,7 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

32
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -2016,7 +2016,7 @@ static void efm32_in_next(FAR struct efm32_usbhost_s *priv,
/* The transfer is complete, with or without an error */
uvdbg("Transfer complete: %d\n", result);
uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@ -2302,7 +2302,7 @@ static void efm32_out_next(FAR struct efm32_usbhost_s *priv,
/* The transfer is complete, with or without an error */
uvdbg("Transfer complete: %d\n", result);
uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@ -2448,7 +2448,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@ -2709,7 +2709,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@ -3012,7 +3012,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Read and pop the next status from the Rx FIFO */
grxsts = efm32_getreg(EFM32_USB_GRXSTSP);
ullvdbg("GRXSTS: %08x\n", grxsts);
ullinfo("GRXSTS: %08x\n", grxsts);
/* Isolate the channel number/index in the status word */
@ -3166,7 +3166,7 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
ullvdbg("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
@ -3254,7 +3254,7 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
ullvdbg("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
@ -3827,7 +3827,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
uvdbg("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
uinfo("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
@ -3844,7 +3844,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
uvdbg("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
#endif
@ -3964,7 +3964,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn,
/* Then let the common usbhost_enumerate do the real enumeration. */
uvdbg("Enumerate the device\n");
uinfo("Enumerate the device\n");
priv->smstate = SMSTATE_ENUM;
ret = usbhost_enumerate(hport, &hport->devclass);
@ -4380,7 +4380,7 @@ static int efm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(USBHOST_VTRACE2_CTRLIN, req->type, req->req);
uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@ -4465,7 +4465,7 @@ static int efm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(USBHOST_VTRACE2_CTRLOUT, req->type, req->req);
uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@ -4583,7 +4583,7 @@ static ssize_t efm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
unsigned int chidx = (unsigned int)ep;
ssize_t nbytes;
uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < EFM32_MAX_TX_FIFOS && buflen > 0);
@ -4650,7 +4650,7 @@ static int efm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
unsigned int chidx = (unsigned int)ep;
int ret;
uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < EFM32_MAX_TX_FIFOS && buflen > 0);
@ -4700,7 +4700,7 @@ static int efm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
unsigned int chidx = (unsigned int)ep;
irqstate_t flags;
uvdbg("chidx: %u: %d\n", chidx);
uinfo("chidx: %u: %d\n", chidx);
DEBUGASSERT(priv && chidx < EFM32_MAX_TX_FIFOS);
chan = &priv->chan[chidx];
@ -4795,7 +4795,7 @@ static int efm32_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

4
arch/arm/src/kinetis/kinetis_enet.c
View file

@ -557,7 +557,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->dev);
/* Handle ARP on input then give the IPv4 packet to the network
@ -598,7 +598,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->dev);
/* Give the IPv6 packet to the network layer */

46
arch/arm/src/kinetis/kinetis_pwm.c
View file

@ -86,19 +86,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) kinetis_pindump(p,m)
# else
# define pwmlldbg(x...)
# define pwmllvdbg(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif
@ -265,25 +265,25 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
{
int nchannels = (priv->tpmid == 0) ? 8 : 2;
pwmvdbg("%s:\n", msg);
pwmvdbg(" FTM%d_SC: %04x FTM%d_CNT: %04x FTM%d_MOD: %04x\n",
pwminfo("%s:\n", msg);
pwminfo(" FTM%d_SC: %04x FTM%d_CNT: %04x FTM%d_MOD: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_SC_OFFSET),
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_CNT_OFFSET),
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_MOD_OFFSET));
pwmvdbg(" FTM%d_STATUS: %04x FTM%d_CONF: %04x\n",
pwminfo(" FTM%d_STATUS: %04x FTM%d_CONF: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_STATUS_OFFSET),
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_CONF_OFFSET));
pwmvdbg(" FTM%d_C0SC: %04x FTM%d_C0V: %04x\n",
pwminfo(" FTM%d_C0SC: %04x FTM%d_C0V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C0SC_OFFSET),
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C0V_OFFSET));
pwmvdbg(" FTM%d_C1SC: %04x FTM%d_C1V: %04x\n",
pwminfo(" FTM%d_C1SC: %04x FTM%d_C1V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C1SC_OFFSET),
priv->tpmid,
@ -291,7 +291,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 3)
{
pwmvdbg(" FTM%d_C2SC: %04x FTM%d_C2V: %04x\n",
pwminfo(" FTM%d_C2SC: %04x FTM%d_C2V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C2SC_OFFSET),
priv->tpmid,
@ -300,7 +300,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 4)
{
pwmvdbg(" FTM%d_C3SC: %04x FTM%d_C3V: %04x\n",
pwminfo(" FTM%d_C3SC: %04x FTM%d_C3V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C3SC_OFFSET),
priv->tpmid,
@ -309,7 +309,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 5)
{
pwmvdbg(" FTM%d_C4SC: %04x FTM%d_C4V: %04x\n",
pwminfo(" FTM%d_C4SC: %04x FTM%d_C4V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C4SC_OFFSET),
priv->tpmid,
@ -318,7 +318,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 6)
{
pwmvdbg(" FTM%d_C5SC: %04x FTM%d_C5V: %04x\n",
pwminfo(" FTM%d_C5SC: %04x FTM%d_C5V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C5SC_OFFSET),
priv->tpmid,
@ -326,7 +326,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
}
if (nchannels >= 7)
{
pwmvdbg(" FTM%d_C6SC: %04x FTM%d_C6V: %04x\n",
pwminfo(" FTM%d_C6SC: %04x FTM%d_C6V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C6SC_OFFSET),
priv->tpmid,
@ -334,7 +334,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
}
if (nchannels >= 8)
{
pwmvdbg(" FTM%d_C7SC: %04x FTM%d_C7V: %04x\n",
pwminfo(" FTM%d_C7SC: %04x FTM%d_C7V: %04x\n",
priv->tpmid,
pwm_getreg(priv, KINETIS_FTM_C7SC_OFFSET),
priv->tpmid,
@ -376,7 +376,7 @@ static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
pwmvdbg("FTM%d channel: %d frequency: %d duty: %08x\n",
pwminfo("FTM%d channel: %d frequency: %d duty: %08x\n",
priv->tpmid, priv->channel, info->frequency, info->duty);
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
@ -446,7 +446,7 @@ static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv,
cv = b16toi(info->duty * modulo + b16HALF);
pwmvdbg("FTM%d PCLK: %d frequency: %d FTMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
pwminfo("FTM%d PCLK: %d frequency: %d FTMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
priv->tpmid, priv->pclk, info->frequency, tpmclk,
presc_values[prescaler], modulo, cv);
@ -570,7 +570,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
regval |= SIM_SCGC3_FTM2;
putreg32(regval, KINETIS_SIM_SCGC3);
pwmvdbg("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwm_dumpregs(priv, "Initially");
/* Configure the PWM output pin, but do not start the timer yet */
@ -601,7 +601,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
uint32_t pincfg;
pwmvdbg("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
/* Make sure that the output has been stopped */
@ -661,7 +661,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
irqstate_t flags;
pwmvdbg("FTM%d\n", priv->tpmid);
pwminfo("FTM%d\n", priv->tpmid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@ -744,7 +744,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
/* There are no platform-specific ioctl commands */
pwmvdbg("FTM%d\n", priv->tpmid);
pwminfo("FTM%d\n", priv->tpmid);
#endif
return -ENOTTY;
}
@ -772,7 +772,7 @@ FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer)
{
FAR struct kinetis_pwmtimer_s *lower;
pwmvdbg("FTM%d\n", timer);
pwminfo("FTM%d\n", timer);
switch (timer)
{

44
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -791,7 +791,7 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
* ready (BWR)
*/
fllvdbg("Entry: remaining: %d IRQSTAT: %08x\n",
fllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
@ -837,7 +837,7 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
putreg32(data.w, KINETIS_SDHC_DATPORT);
}
fllvdbg("Exit: remaining: %d IRQSTAT: %08x\n",
fllinfo("Exit: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
}
@ -877,7 +877,7 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
* ready (BRR)
*/
fllvdbg("Entry: remaining: %d IRQSTAT: %08x\n",
fllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
@ -929,7 +929,7 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
fllvdbg("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
fllinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
getreg32(KINETIS_SDHC_WML));
@ -1105,7 +1105,7 @@ static int kinetis_interrupt(int irq, void *context)
regval = getreg32(KINETIS_SDHC_IRQSIGEN);
enabled = getreg32(KINETIS_SDHC_IRQSTAT) & regval;
fllvdbg("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
fllinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
/* Disable card interrupts to clear the card interrupt to the host system. */
@ -1289,7 +1289,7 @@ static void kinetis_reset(FAR struct sdio_dev_s *dev)
putreg32(SDHC_INT_ALL, KINETIS_SDHC_IRQSTATEN);
fvdbg("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
finfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT),
getreg32(KINETIS_SDHC_IRQSTATEN));
@ -1504,7 +1504,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
regval |= (SDHC_SYSCTL_SDCLKEN | SDHC_SYSCTL_PEREN | SDHC_SYSCTL_HCKEN |
SDHC_SYSCTL_IPGEN);
putreg32(regval, KINETIS_SDHC_SYSCTL);
fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
}
#endif
@ -1538,7 +1538,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval = getreg32(KINETIS_SDHC_SYSCTL);
regval &= ~SDHC_SYSCTL_SDCLKEN;
putreg32(regval, KINETIS_SDHC_SYSCTL);
fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
switch (rate)
{
@ -1552,7 +1552,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN |
SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DVS_MASK);
putreg32(regval, KINETIS_SDHC_SYSCTL);
fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
return;
}
@ -1593,7 +1593,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval = getreg32(KINETIS_SDHC_SYSCTL);
regval &= ~SDHC_SYSCTL_SDCLKEN;
putreg32(regval, KINETIS_SDHC_SYSCTL);
fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
/* Clear the old prescaler and divisor values so that new ones can be ORed
* in.
@ -1619,7 +1619,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN);
putreg32(regval, KINETIS_SDHC_SYSCTL);
fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
return;
}
@ -1653,7 +1653,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
}
putreg32(regval, KINETIS_SDHC_SYSCTL);
fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
}
#endif
@ -1824,7 +1824,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
/* Other bits? What about CMDTYP? */
fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
/* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately
* after the transfer type register is written. This bit is cleared when
@ -2486,7 +2486,7 @@ static void kinetis_callbackenable(FAR struct sdio_dev_s *dev,
{
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev;
fvdbg("eventset: %02x\n", eventset);
finfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@ -2522,7 +2522,7 @@ static int kinetis_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
fvdbg("Register %p(%p)\n", callback, arg);
finfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@ -2694,7 +2694,7 @@ static void kinetis_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
@ -2739,14 +2739,14 @@ static void kinetis_callback(void *arg)
{
/* Yes.. queue it */
fvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@ -2792,7 +2792,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
regval = getreg32(KINETIS_SIM_SCGC3);
regval |= SIM_SCGC3_SDHC;
putreg32(regval, KINETIS_SIM_SCGC3);
fvdbg("SIM_SCGC3: %08x\n", regval);
finfo("SIM_SCGC3: %08x\n", regval);
/* In addition to the system clock, the SDHC module needs a clock for the
* base for the external card clock. There are four possible sources for
@ -2808,7 +2808,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
regval &= ~SIM_SOPT2_SDHCSRC_MASK;
regval |= SIM_SOPT2_SDHCSRC_CORE;
putreg32(regval, KINETIS_SIM_SOPT2);
fvdbg("SIM_SOPT2: %08x\n", regval);
finfo("SIM_SOPT2: %08x\n", regval);
/* Configure pins for 1 or 4-bit, wide-bus operation (the chip is capable
* of 8-bit wide bus operation but D4-D7 are not configured).
@ -2892,7 +2892,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
fvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@ -2937,7 +2937,7 @@ void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
fvdbg("cdstatus: %02x\n", priv->cdstatus);
finfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_KINETIS_SDHC */

26
arch/arm/src/kinetis/kinetis_usbdev.c
View file

@ -371,9 +371,9 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
# define regdbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define regvdbg lldbg
# define reginfo lldbg
# else
# define regvdbg(x...)
# define reginfo(x...)
# endif
#else
@ -381,7 +381,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
# define khci_getreg(addr) getreg8(addr)
# define khci_putreg(val,addr) putreg8(val,addr)
# define regdbg(x...)
# define regvdbg(x...)
# define reginfo(x...)
#endif
@ -391,15 +391,15 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
# define bdtdbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define bdtvdbg lldbg
# define bdtinfo lldbg
# else
# define bdtvdbg(x...)
# define bdtinfo(x...)
# endif
#else
# define bdtdbg(x...)
# define bdtvdbg(x...)
# define bdtinfo(x...)
#endif
@ -987,10 +987,10 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv,
epno = USB_EPNO(privep->ep.eplog);
#ifdef CONFIG_USBDEV_NOWRITEAHEAD
ullvdbg("EP%d: len=%d xfrd=%d inflight=%d\n",
ullinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
#else
ullvdbg("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
ullinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
epno, privreq->req.len, privreq->req.xfrd,
privreq->inflight[0], privreq->inflight[1]);
#endif
@ -1303,7 +1303,7 @@ static int khci_wrstart(struct khci_usbdev_s *priv,
bytesleft = privreq->req.len;
}
ullvdbg("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
ullinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
/* Get the number of bytes left to be sent in the packet */
@ -1417,7 +1417,7 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv,
bdtout = privep->bdtout;
epno = USB_EPNO(privep->ep.eplog);
ullvdbg("EP%d: len=%d xfrd=%d\n",
ullinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n",
epno, bdtout, bdtout->status, bdtout->addr);
@ -1705,7 +1705,7 @@ static int khci_rdrequest(struct khci_usbdev_s *priv,
return OK;
}
ullvdbg("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
ullinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
/* Ignore any attempt to receive a zero length packet */
@ -1995,7 +1995,7 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@ -2239,7 +2239,7 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
{
/* Special case recipient=device test mode */
ullvdbg("test mode: %d\n", index.w);
ullinfo("test mode: %d\n", index.w);
}
else
{

2
arch/arm/src/kl/kl_idle.c
View file

@ -103,7 +103,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

44
arch/arm/src/kl/kl_pwm.c
View file

@ -83,19 +83,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) kl_dumpgpio(p,m)
# else
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif
@ -258,25 +258,25 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
{
int nchannels = (priv->tpmid == 0) ? 6 : 2;
pwmvdbg("%s:\n", msg);
pwmvdbg(" TPM%d_SC: %04x TPM%d_CNT: %04x TPM%d_MOD: %04x\n",
pwminfo("%s:\n", msg);
pwminfo(" TPM%d_SC: %04x TPM%d_CNT: %04x TPM%d_MOD: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_SC_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_CNT_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_MOD_OFFSET));
pwmvdbg(" TPM%d_STATUS: %04x TPM%d_CONF: %04x\n",
pwminfo(" TPM%d_STATUS: %04x TPM%d_CONF: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_STATUS_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_CONF_OFFSET));
pwmvdbg(" TPM%d_C0SC: %04x TPM%d_C0V: %04x\n",
pwminfo(" TPM%d_C0SC: %04x TPM%d_C0V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C0SC_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_C0V_OFFSET));
pwmvdbg(" TPM%d_C1SC: %04x TPM%d_C1V: %04x\n",
pwminfo(" TPM%d_C1SC: %04x TPM%d_C1V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C1SC_OFFSET),
priv->tpmid,
@ -284,7 +284,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 3)
{
pwmvdbg(" TPM%d_C2SC: %04x TPM%d_C2V: %04x\n",
pwminfo(" TPM%d_C2SC: %04x TPM%d_C2V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C2SC_OFFSET),
priv->tpmid,
@ -293,7 +293,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 4)
{
pwmvdbg(" TPM%d_C3SC: %04x TPM%d_C3V: %04x\n",
pwminfo(" TPM%d_C3SC: %04x TPM%d_C3V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C3SC_OFFSET),
priv->tpmid,
@ -302,7 +302,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 5)
{
pwmvdbg(" TPM%d_C4SC: %04x TPM%d_C4V: %04x\n",
pwminfo(" TPM%d_C4SC: %04x TPM%d_C4V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C4SC_OFFSET),
priv->tpmid,
@ -311,7 +311,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 6)
{
pwmvdbg(" TPM%d_C5SC: %04x TPM%d_C5V: %04x\n",
pwminfo(" TPM%d_C5SC: %04x TPM%d_C5V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C5SC_OFFSET),
priv->tpmid,
@ -353,7 +353,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
pwmvdbg("TPM%d channel: %d frequency: %d duty: %08x\n",
pwminfo("TPM%d channel: %d frequency: %d duty: %08x\n",
priv->tpmid, priv->channel, info->frequency, info->duty);
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
@ -423,7 +423,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
cv = b16toi(info->duty * modulo + b16HALF);
pwmvdbg("TPM%d PCLK: %d frequency: %d TPMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
pwminfo("TPM%d PCLK: %d frequency: %d TPMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
priv->tpmid, priv->pclk, info->frequency, tpmclk,
presc_values[prescaler], modulo, cv);
@ -530,7 +530,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
regval |= SIM_SCGC6_TPM0 | SIM_SCGC6_TPM1 | SIM_SCGC6_TPM2;
putreg32(regval, KL_SIM_SCGC6);
pwmvdbg("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwminfo("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwm_dumpregs(priv, "Initially");
/* Configure the PWM output pin, but do not start the timer yet */
@ -561,7 +561,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct kl_pwmtimer_s *priv = (FAR struct kl_pwmtimer_s *)dev;
uint32_t pincfg;
pwmvdbg("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwminfo("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
/* Make sure that the output has been stopped */
@ -621,7 +621,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
FAR struct kl_pwmtimer_s *priv = (FAR struct kl_pwmtimer_s *)dev;
irqstate_t flags;
pwmvdbg("TPM%d\n", priv->tpmid);
pwminfo("TPM%d\n", priv->tpmid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@ -696,7 +696,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
/* There are no platform-specific ioctl commands */
pwmvdbg("TPM%d\n", priv->tpmid);
pwminfo("TPM%d\n", priv->tpmid);
#endif
return -ENOTTY;
}
@ -724,7 +724,7 @@ FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer)
{
FAR struct kl_pwmtimer_s *lower;
pwmvdbg("TPM%d\n", timer);
pwminfo("TPM%d\n", timer);
switch (timer)
{

14
arch/arm/src/kl/kl_spi.c
View file

@ -73,13 +73,13 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/****************************************************************************
@ -388,7 +388,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev;
uint8_t regval;
spivdbg("mode=%d\n", mode);
spiinfo("mode=%d\n", mode);
/* Has the mode changed? */
@ -519,7 +519,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR uint8_t *txptr = (FAR uint8_t *)txbuffer;
uint8_t data;
spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Loop, sending each word in the user-provied data buffer. */
@ -585,7 +585,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
size_t nwords)
{
spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords);
return spi_exchange(dev, txbuffer, NULL, nwords);
}
#endif
@ -612,7 +612,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
#ifndef CONFIG_SPI_EXCHANGE
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords)
{
spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
return spi_exchange(dev, NULL, rxbuffer, nwords);
}
#endif

2
arch/arm/src/lpc11xx/lpc11_serial.c
View file

@ -630,7 +630,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC11_UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
info("LSR: %02x\n", status);
break;
}

6
arch/arm/src/lpc11xx/lpc11_spi.c
View file

@ -82,13 +82,13 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/* SSP Clocking *************************************************************/

10
arch/arm/src/lpc11xx/lpc11_ssp.c
View file

@ -83,13 +83,13 @@
#ifdef CONFIG_DEBUG_SPI
# define sspdbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define sspdbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/* SSP Clocking *************************************************************/
@ -754,7 +754,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC11_SSP_FIFOSZ) && nwords)
{
@ -767,7 +767,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* empty.
*/
spivdbg("RX: rxpending: %d\n", rxpending);
spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = (uint8_t)ssp_getreg(priv, LPC11_SSP_DR_OFFSET);

12
arch/arm/src/lpc11xx/lpc11_timer.c
View file

@ -92,19 +92,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
# else
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif

8
arch/arm/src/lpc17xx/lpc176x_rtc.c
View file

@ -82,14 +82,14 @@
#ifdef CONFIG_DEBUG_RTC
# define rtcdbg dbg
# define rtcvdbg vdbg
# define rtcinfo info
# define rtclldbg lldbg
# define rtcllvdbg llvdbg
# define rtcllinfo llinfo
#else
# define rtcdbg(x...)
# define rtcvdbg(x...)
# define rtcinfo(x...)
# define rtclldbg(x...)
# define rtcllvdbg(x...)
# define rtcllinfo(x...)
#endif
/************************************************************************************

34
arch/arm/src/lpc17xx/lpc17_can.c
View file

@ -167,18 +167,18 @@
#ifdef CONFIG_DEBUG_CAN
# ifdef CONFIG_CAN_REGDEBUG
# define candbg lldbg
# define canvdbg llvdbg
# define caninfo llinfo
# else
# define candbg dbg
# define canvdbg vdbg
# define caninfo info
# endif
# define canlldbg lldbg
# define canllvdbg llvdbg
# define canllinfo llinfo
#else
# define candbg(x...)
# define canvdbg(x...)
# define caninfo(x...)
# define canlldbg(x...)
# define canllvdbg(x...)
# define canllinfo(x...)
#endif
/* Timing *******************************************************************/
@ -504,7 +504,7 @@ static void can_reset(FAR struct can_dev_s *dev)
irqstate_t flags;
int ret;
canvdbg("CAN%d\n", priv->port);
caninfo("CAN%d\n", priv->port);
flags = enter_critical_section();
@ -558,7 +558,7 @@ static int can_setup(FAR struct can_dev_s *dev)
#endif
int ret;
canvdbg("CAN%d\n", priv->port);
caninfo("CAN%d\n", priv->port);
ret = irq_attach(LPC17_IRQ_CAN, can12_interrupt);
if (ret == OK)
@ -588,7 +588,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
#ifdef CONFIG_DEBUG_CAN
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv;
canvdbg("CAN%d\n", priv->port);
caninfo("CAN%d\n", priv->port);
#endif
up_disable_irq(LPC17_IRQ_CAN);
@ -615,7 +615,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
uint32_t regval;
irqstate_t flags;
canvdbg("CAN%d enable: %d\n", priv->port, enable);
caninfo("CAN%d enable: %d\n", priv->port, enable);
/* The EIR register is also modifed from the interrupt handler, so we have
* to protect this code section.
@ -656,7 +656,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
uint32_t regval;
irqstate_t flags;
canvdbg("CAN%d enable: %d\n", priv->port, enable);
caninfo("CAN%d enable: %d\n", priv->port, enable);
/* Only disabling of the TX interrupt is supported here. The TX interrupt
* is automatically enabled just before a message is sent in order to avoid
@ -753,7 +753,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
irqstate_t flags;
int ret = OK;
canvdbg("CAN%d ID: %d DLC: %d\n",
caninfo("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
if (msg->cm_hdr.ch_rtr)
@ -958,7 +958,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Read the interrupt and capture register (also clearing most status bits) */
regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET);
canllvdbg("CAN%d ICR: %08x\n", priv->port, regval);
canllinfo("CAN%d ICR: %08x\n", priv->port, regval);
/* Check for a receive interrupt */
@ -1065,7 +1065,7 @@ static int can12_interrupt(int irq, void *context)
{
/* Handle CAN1/2 interrupts */
canllvdbg("irq: %d\n", irq);
canllinfo("irq: %d\n", irq);
#ifdef CONFIG_LPC17_CAN1
can_interrupt(&g_can1dev);
@ -1142,7 +1142,7 @@ static int can_bittiming(struct up_dev_s *priv)
uint32_t ts2;
uint32_t sjw;
canllvdbg("CAN%d PCLK: %d baud: %d\n", priv->port,
canllinfo("CAN%d PCLK: %d baud: %d\n", priv->port,
CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
@ -1195,7 +1195,7 @@ static int can_bittiming(struct up_dev_s *priv)
sjw = 1;
canllvdbg("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
canllinfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
/* Configure bit timing */
@ -1212,7 +1212,7 @@ static int can_bittiming(struct up_dev_s *priv)
btr |= CAN_BTR_SAM;
#endif
canllvdbg("Setting CANxBTR= 0x%08x\n", btr);
canllinfo("Setting CANxBTR= 0x%08x\n", btr);
can_putreg(priv, LPC17_CAN_BTR_OFFSET, btr); /* Set bit timing */
return OK;
}
@ -1240,7 +1240,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
irqstate_t flags;
uint32_t regval;
canllvdbg("CAN%d\n", port);
canllinfo("CAN%d\n", port);
flags = enter_critical_section();

16
arch/arm/src/lpc17xx/lpc17_ethernet.c
View file

@ -906,7 +906,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->lp_dev);
/* Handle ARP on input then give the IPv4 packet to the
@ -948,7 +948,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->lp_dev);
/* Give the IPv6 packet to the network layer */
@ -1671,7 +1671,7 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)lpc17_addmac(dev, mac);
@ -2145,7 +2145,7 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t crc;
unsigned int ndx;
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Hash function:
@ -2221,7 +2221,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t crc;
unsigned int ndx;
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Hash function:
@ -2647,14 +2647,14 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
*/
phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1);
nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
ninfo("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
/* Compare OUI bits 3-18 */
if (phyreg == LPC17_PHYID1)
{
phyreg = lpc17_phyread(phyaddr, MII_PHYID2);
nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg);
ninfo("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg);
/* Compare OUI bits 19-24 and the 6-bit model number (ignoring the
* 4-bit revision number).
@ -2676,7 +2676,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
ndbg("No PHY detected\n");
return -ENODEV;
}
nvdbg("phyaddr: %d\n", phyaddr);
ninfo("phyaddr: %d\n", phyaddr);
/* Save the discovered PHY device address */

38
arch/arm/src/lpc17xx/lpc17_lcd.c
View file

@ -202,7 +202,7 @@ struct fb_vtable_s g_fbobject =
static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable,
FAR struct fb_videoinfo_s *vinfo)
{
gvdbg("vtable=%p vinfo=%p\n", vtable, vinfo);
ginfo("vtable=%p vinfo=%p\n", vtable, vinfo);
if (vtable && vinfo)
{
memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
@ -220,7 +220,7 @@ static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable,
static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno,
FAR struct fb_planeinfo_s *pinfo)
{
gvdbg("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
if (vtable && planeno == 0 && pinfo)
{
memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s));
@ -244,7 +244,7 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable,
int last;
int i;
gvdbg("vtable=%p cmap=%p first=%d len=%d\n",
ginfo("vtable=%p cmap=%p first=%d len=%d\n",
vtable, cmap, cmap->first, cmap->len);
DEBUGASSERT(vtable && cmap &&
@ -319,7 +319,7 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable,
int last;
int i;
gvdbg("vtable=%p cmap=%p first=%d len=%d\n",
ginfo("vtable=%p cmap=%p first=%d len=%d\n",
vtable, cmap, cmap->first, cmap->len);
DEBUGASSERT(vtable && cmap);
@ -383,21 +383,21 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable,
static int lpc17_getcursor(FAR struct fb_vtable_s *vtable,
FAR struct fb_cursorattrib_s *attrib)
{
gvdbg("vtable=%p attrib=%p\n", vtable, attrib);
ginfo("vtable=%p attrib=%p\n", vtable, attrib);
if (vtable && attrib)
{
#ifdef CONFIG_FB_HWCURSORIMAGE
attrib->fmt = LPC17_COLOR_FMT;
#endif
gvdbg("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y);
ginfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y);
attrib->pos = g_cpos;
#ifdef CONFIG_FB_HWCURSORSIZE
attrib->mxsize.h = CONFIG_LPC17_LCD_VHEIGHT;
attrib->mxsize.w = CONFIG_LPC17_LCD_HWIDTH;
gvdbg("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w);
ginfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w);
attrib->size = g_csize;
#endif
return OK;
@ -416,26 +416,26 @@ static int lpc17_getcursor(FAR struct fb_vtable_s *vtable,
static int lpc17_setcursor(FAR struct fb_vtable_s *vtable,
FAR struct fb_setcursor_s *setttings)
{
gvdbg("vtable=%p setttings=%p\n", vtable, setttings);
ginfo("vtable=%p setttings=%p\n", vtable, setttings);
if (vtable && setttings)
{
gvdbg("flags: %02x\n", settings->flags);
ginfo("flags: %02x\n", settings->flags);
if ((flags & FB_CUR_SETPOSITION) != 0)
{
g_cpos = settings->pos;
gvdbg("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
ginfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
}
#ifdef CONFIG_FB_HWCURSORSIZE
if ((flags & FB_CUR_SETSIZE) != 0)
{
g_csize = settings->size;
gvdbg("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
ginfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
}
#endif
#ifdef CONFIG_FB_HWCURSORIMAGE
if ((flags & FB_CUR_SETIMAGE) != 0)
{
gvdbg("image: (h:%d, w:%d) @ %p\n",
ginfo("image: (h:%d, w:%d) @ %p\n",
settings->img.height, settings->img.width,
settings->img.image);
}
@ -473,7 +473,7 @@ int up_fbinitialize(int display)
uint32_t regval;
int i;
gvdbg("Entry\n");
ginfo("Entry\n");
/* Give LCD bus priority */
@ -485,7 +485,7 @@ int up_fbinitialize(int display)
/* Configure pins */
/* Video data */
gvdbg("Configuring pins\n");
ginfo("Configuring pins\n");
lpc17_configgpio(GPIO_LCD_VD0);
lpc17_configgpio(GPIO_LCD_VD1);
@ -528,7 +528,7 @@ int up_fbinitialize(int display)
modifyreg32(LPC17_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD);
gvdbg("Configuring the LCD controller\n");
ginfo("Configuring the LCD controller\n");
/* Disable the cursor */
@ -686,7 +686,7 @@ int up_fbinitialize(int display)
#endif
putreg32(0, LPC17_LCD_INTMSK);
gvdbg("Enabling the display\n");
ginfo("Enabling the display\n");
for (i = LPC17_LCD_PWREN_DELAY; i; i--);
@ -727,7 +727,7 @@ int up_fbinitialize(int display)
FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
{
gvdbg("vplane: %d\n", vplane);
ginfo("vplane: %d\n", vplane);
if (vplane == 0)
{
return &g_fbobject;
@ -801,14 +801,14 @@ void lpc17_lcdclear(nxgl_mxpixel_t color)
#if LPC17_BPP > 16
uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE;
gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n",
ginfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
color, CONFIG_LPC17_LCD_VRAMBASE,
CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t));
#else
uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE;
gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n",
ginfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
color, CONFIG_LPC17_LCD_VRAMBASE,
CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t));
#endif

30
arch/arm/src/lpc17xx/lpc17_mcpwm.c
View file

@ -91,19 +91,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
# else
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif
@ -246,8 +246,8 @@ static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t v
static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
FAR const char *msg)
{
pwmvdbg("%s:\n", msg);
pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwminfo("%s:\n", msg);
pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
mcpwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@ -255,7 +255,7 @@ static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
#if defined(CONFIG_LPC17_MCPWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
mcpwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@ -264,7 +264,7 @@ static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
else
#endif
{
pwmvdbg(" DCR: %04x DMAR: %04x\n",
pwminfo(" DCR: %04x DMAR: %04x\n",
mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR3_OFFSET));
}
@ -520,7 +520,7 @@ static int mcpwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev;
uint32_t pincfg;
pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@ -576,7 +576,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
pwmvdbg("TIM%d\n", priv->timid);
pwminfo("TIM%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@ -602,7 +602,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev)
leave_critical_section(flags);
pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
mcpwm_dumpregs(priv, "After stop");
return OK;
}
@ -630,7 +630,7 @@ static int mcpwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long a
/* There are no platform-specific ioctl commands */
pwmvdbg("TIM%d\n", priv->timid);
pwminfo("TIM%d\n", priv->timid);
#endif
return -ENOTTY;
}
@ -660,7 +660,7 @@ FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer)
{
FAR struct lpc17_mcpwmtimer_s *lower;
pwmvdbg("TIM%d\n", timer);
pwminfo("TIM%d\n", timer);
switch (timer)
{

30
arch/arm/src/lpc17xx/lpc17_pwm.c
View file

@ -109,19 +109,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
# else
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif
@ -261,8 +261,8 @@ static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value
#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_INFO)
static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
{
pwmvdbg("%s:\n", msg);
pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwminfo("%s:\n", msg);
pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@ -270,7 +270,7 @@ static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
#if defined(CONFIG_LPC17_PWM1)
if (priv->timtype == TIMTYPE_ADVANCED)
{
pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@ -279,7 +279,7 @@ static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
else
#endif
{
pwmvdbg(" DCR: %04x DMAR: %04x\n",
pwminfo(" DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR3_OFFSET));
}
@ -491,7 +491,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev;
uint32_t pincfg;
pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@ -547,7 +547,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
pwmvdbg("TIM%d\n", priv->timid);
pwminfo("TIM%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@ -573,7 +573,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
leave_critical_section(flags);
pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
pwm_dumpregs(priv, "After stop");
return OK;
}
@ -601,7 +601,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
/* There are no platform-specific ioctl commands */
pwmvdbg("TIM%d\n", priv->timid);
pwminfo("TIM%d\n", priv->timid);
#endif
return -ENOTTY;
}
@ -631,7 +631,7 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer)
{
FAR struct lpc17_pwmtimer_s *lower;
pwmvdbg("TIM%d\n", timer);
pwminfo("TIM%d\n", timer);
switch (timer)
{

20
arch/arm/src/lpc17xx/lpc17_sdcard.c
View file

@ -529,7 +529,7 @@ static inline void lpc17_setclock(uint32_t clkcr)
regval |= clkcr;
putreg32(regval, LPC17_SDCARD_CLOCK);
fvdbg("CLKCR: %08x PWR: %08x\n",
finfo("CLKCR: %08x PWR: %08x\n",
getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR));
}
@ -1480,7 +1480,7 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev)
lpc17_setpwrctrl(SDCARD_PWR_CTRL_ON);
leave_critical_section(flags);
fvdbg("CLCKR: %08x POWER: %08x\n",
finfo("CLCKR: %08x POWER: %08x\n",
getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR));
}
@ -1689,7 +1689,7 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
regval |= cmdidx | SDCARD_CMD_CPSMEN;
fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
/* Write the SD card CMD */
@ -2341,7 +2341,7 @@ static void lpc17_callbackenable(FAR struct sdio_dev_s *dev,
{
struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev;
fvdbg("eventset: %02x\n", eventset);
finfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@ -2377,7 +2377,7 @@ static int lpc17_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
fvdbg("Register %p(%p)\n", callback, arg);
finfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@ -2590,7 +2590,7 @@ static void lpc17_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
@ -2635,14 +2635,14 @@ static void lpc17_callback(void *arg)
{
/* Yes.. queue it */
fvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@ -2781,7 +2781,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
{
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
fvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@ -2824,7 +2824,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
{
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
fvdbg("cdstatus: %02x\n", priv->cdstatus);
finfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_LPC17_SDCARD */

4
arch/arm/src/lpc17xx/lpc17_serial.c
View file

@ -1134,7 +1134,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, LPC17_UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
info("MSR: %02x\n", status);
break;
}
@ -1145,7 +1145,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC17_UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
info("LSR: %02x\n", status);
break;
}

6
arch/arm/src/lpc17xx/lpc17_spi.c
View file

@ -82,13 +82,13 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/* SSP Clocking *************************************************************/

10
arch/arm/src/lpc17xx/lpc17_ssp.c
View file

@ -83,13 +83,13 @@
#ifdef CONFIG_DEBUG_SPI
# define sspdbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define sspdbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/* SSP Clocking *************************************************************/
@ -745,7 +745,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC17_SSP_FIFOSZ) && nwords)
{
@ -756,7 +756,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
spivdbg("RX: rxpending: %d\n", rxpending);
spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = (uint8_t)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);

12
arch/arm/src/lpc17xx/lpc17_timer.c
View file

@ -92,19 +92,19 @@
# define pwmdbg dbg
# define pwmlldbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define pwmvdbg vdbg
# define pwmllvdbg llvdbg
# define pwminfo info
# define pwmllinfo llinfo
# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
# else
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
# endif
#else
# define pwmdbg(x...)
# define pwmlldbg(x...)
# define pwmvdbg(x...)
# define pwmllvdbg(x...)
# define pwminfo(x...)
# define pwmllinfo(x...)
# define pwm_dumpgpio(p,m)
#endif

12
arch/arm/src/lpc17xx/lpc17_usbdev.c
View file

@ -1076,7 +1076,7 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep)
return OK;
}
ullvdbg("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@ -1185,7 +1185,7 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep)
return OK;
}
ullvdbg("len=%d xfrd=%d nullpkt=%d\n",
ullinfo("len=%d xfrd=%d nullpkt=%d\n",
privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@ -1593,7 +1593,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1739,7 +1739,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullvdbg("test mode: %d\n", index);
ullinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2321,7 +2321,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
}
else
{
ullvdbg("Pending data on OUT endpoint\n");
ullinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@ -2797,7 +2797,7 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

60
arch/arm/src/lpc17xx/lpc17_usbhost.c
View file

@ -1192,7 +1192,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv,
interval = lpc17_getinterval(epdesc->interval);
ed->interval = interval;
uvdbg("interval: %d->%d\n", epdesc->interval, interval);
uinfo("interval: %d->%d\n", epdesc->interval, interval);
/* Get the offset associated with the ED direction. IN EDs get the even
* entries, OUT EDs get the odd entries.
@ -1225,7 +1225,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv,
interval = priv->outinterval;
}
}
uvdbg("min interval: %d offset: %d\n", interval, offset);
uinfo("min interval: %d offset: %d\n", interval, offset);
/* Get the head of the first of the duplicated entries. The first offset
* entry is always guaranteed to contain the common ED list head.
@ -1244,7 +1244,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv,
ed->hw.nexted = head;
lpc17_setinttab((uint32_t)ed, interval, offset);
uvdbg("head: %08x next: %08x\n", ed, head);
uinfo("head: %08x next: %08x\n", ed, head);
/* Re-enabled periodic list processing */
@ -1314,7 +1314,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv,
*/
head = (struct lpc17_ed_s *)HCCA->inttbl[offset];
uvdbg("ed: %08x head: %08x next: %08x offset: %d\n",
uinfo("ed: %08x head: %08x next: %08x offset: %d\n",
ed, head, head ? head->hw.nexted : 0, offset);
/* Find the ED to be removed in the ED list */
@ -1349,7 +1349,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv,
prev->hw.nexted = ed->hw.nexted;
}
uvdbg("ed: %08x head: %08x next: %08x\n",
uinfo("ed: %08x head: %08x next: %08x\n",
ed, head, head ? head->hw.nexted : 0);
/* Calculate the new minimum interval for this list */
@ -1363,7 +1363,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv,
}
}
uvdbg("min interval: %d offset: %d\n", interval, offset);
uinfo("min interval: %d offset: %d\n", interval, offset);
/* Save the new minimum interval */
@ -1642,7 +1642,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
intst = lpc17_getreg(LPC17_USBHOST_INTST);
regval = lpc17_getreg(LPC17_USBHOST_INTEN);
ullvdbg("INST: %08x INTEN: %08x\n", intst, regval);
ullinfo("INST: %08x INTEN: %08x\n", intst, regval);
pending = intst & regval;
if (pending != 0)
@ -1652,18 +1652,18 @@ static int lpc17_usbinterrupt(int irq, void *context)
if ((pending & OHCI_INT_RHSC) != 0)
{
uint32_t rhportst1 = lpc17_getreg(LPC17_USBHOST_RHPORTST1);
ullvdbg("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
ullinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
if ((rhportst1 & OHCI_RHPORTST_CSC) != 0)
{
uint32_t rhstatus = lpc17_getreg(LPC17_USBHOST_RHSTATUS);
ullvdbg("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
ullinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
/* If DRWE is set, Connect Status Change indicates a remote wake-up event */
if (rhstatus & OHCI_RHSTATUS_DRWE)
{
ullvdbg("DRWE: Remote wake-up\n");
ullinfo("DRWE: Remote wake-up\n");
}
/* Otherwise... Not a remote wake-up event */
@ -1680,7 +1680,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. connected. */
ullvdbg("Connected\n");
ullinfo("Connected\n");
priv->connected = true;
priv->change = true;
@ -1710,7 +1710,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
priv->rhport.hport.speed = USB_SPEED_FULL;
}
ullvdbg("Speed:%d\n", priv->rhport.hport.speed);
ullinfo("Speed:%d\n", priv->rhport.hport.speed);
}
/* Check if we are now disconnected */
@ -1719,7 +1719,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. disconnect the device */
ullvdbg("Disconnected\n");
ullinfo("Disconnected\n");
priv->connected = false;
priv->change = true;
@ -2089,7 +2089,7 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn,
/* Then let the common usbhost_enumerate do the real enumeration. */
uvdbg("Enumerate the device\n");
uinfo("Enumerate the device\n");
ret = usbhost_enumerate(hport, &hport->devclass);
if (ret < 0)
{
@ -2155,7 +2155,7 @@ static int lpc17_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
lpc17_givesem(&priv->exclsem);
uvdbg("EP0 CTRL:%08x\n", ed->hw.ctrl);
uinfo("EP0 CTRL:%08x\n", ed->hw.ctrl);
return OK;
}
@ -2255,7 +2255,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr,
ed->hw.ctrl |= ED_CONTROL_F;
}
#endif
uvdbg("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
uinfo("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
/* Initialize the semaphore that is used to wait for the endpoint
* WDH event.
@ -2608,7 +2608,7 @@ static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@ -2646,7 +2646,7 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@ -2712,7 +2712,7 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv,
xfrinfo = ed->xfrinfo;
in = (ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN;
uvdbg("EP%u %s toggle:%u maxpacket:%u buflen:%lu\n",
uinfo("EP%u %s toggle:%u maxpacket:%u buflen:%lu\n",
(ed->hw.ctrl & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT,
in ? "IN" : "OUT",
(ed->hw.headp & ED_HEADP_C) != 0 ? 1 : 0,
@ -2790,7 +2790,7 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv,
if (buflen > CONFIG_USBHOST_IOBUFSIZE)
{
uvdbg("buflen (%d) > IO buffer size (%d)\n",
uinfo("buflen (%d) > IO buffer size (%d)\n",
buflen, CONFIG_USBHOST_IOBUFSIZE);
return -ENOMEM;
}
@ -2800,7 +2800,7 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv,
newbuffer = lpc17_allocio();
if (!newbuffer)
{
uvdbg("IO buffer allocation failed\n");
uinfo("IO buffer allocation failed\n");
return -ENOMEM;
}
@ -3454,7 +3454,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
@ -3700,14 +3700,14 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
/* Show AHB SRAM memory map */
#if 0 /* Useful if you have doubts about the layout */
uvdbg("AHB SRAM:\n");
uvdbg(" HCCA: %08x %d\n", LPC17_HCCA_BASE, LPC17_HCCA_SIZE);
uvdbg(" TDTAIL: %08x %d\n", LPC17_TDTAIL_ADDR, LPC17_TD_SIZE);
uvdbg(" EDCTRL: %08x %d\n", LPC17_EDCTRL_ADDR, LPC17_ED_SIZE);
uvdbg(" EDFREE: %08x %d\n", LPC17_EDFREE_BASE, LPC17_ED_SIZE);
uvdbg(" TDFREE: %08x %d\n", LPC17_TDFREE_BASE, LPC17_EDFREE_SIZE);
uvdbg(" TBFREE: %08x %d\n", LPC17_TBFREE_BASE, LPC17_TBFREE_SIZE);
uvdbg(" IOFREE: %08x %d\n", LPC17_IOFREE_BASE, LPC17_IOBUFFERS * CONFIG_USBHOST_IOBUFSIZE);
uinfo("AHB SRAM:\n");
uinfo(" HCCA: %08x %d\n", LPC17_HCCA_BASE, LPC17_HCCA_SIZE);
uinfo(" TDTAIL: %08x %d\n", LPC17_TDTAIL_ADDR, LPC17_TD_SIZE);
uinfo(" EDCTRL: %08x %d\n", LPC17_EDCTRL_ADDR, LPC17_ED_SIZE);
uinfo(" EDFREE: %08x %d\n", LPC17_EDFREE_BASE, LPC17_ED_SIZE);
uinfo(" TDFREE: %08x %d\n", LPC17_TDFREE_BASE, LPC17_EDFREE_SIZE);
uinfo(" TBFREE: %08x %d\n", LPC17_TBFREE_BASE, LPC17_TBFREE_SIZE);
uinfo(" IOFREE: %08x %d\n", LPC17_IOFREE_BASE, LPC17_IOBUFFERS * CONFIG_USBHOST_IOBUFSIZE);
#endif
/* Initialize all the TDs, EDs and HCCA to 0 */

4
arch/arm/src/lpc214x/lpc214x_serial.c
View file

@ -530,7 +530,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, LPC214X_UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
info("MSR: %02x\n", status);
break;
}
@ -541,7 +541,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC214X_UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
info("LSR: %02x\n", status);
break;
}

12
arch/arm/src/lpc214x/lpc214x_usbdev.c
View file

@ -1021,7 +1021,7 @@ static int lpc214x_wrrequest(struct lpc214x_ep_s *privep)
return OK;
}
ullvdbg("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@ -1130,7 +1130,7 @@ static int lpc214x_rdrequest(struct lpc214x_ep_s *privep)
return OK;
}
ullvdbg("len=%d xfrd=%d nullpkt=%d\n",
ullinfo("len=%d xfrd=%d nullpkt=%d\n",
privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@ -1552,7 +1552,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1697,7 +1697,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullvdbg("test mode: %d\n", index);
ullinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2287,7 +2287,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
}
else
{
ullvdbg("Pending data on OUT endpoint\n");
ullinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@ -2763,7 +2763,7 @@ static int lpc214x_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

4
arch/arm/src/lpc2378/lpc23xx_serial.c
View file

@ -648,7 +648,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
info("MSR: %02x\n", status);
break;
}
@ -659,7 +659,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
info("LSR: %02x\n", status);
break;
}

6
arch/arm/src/lpc2378/lpc23xx_spi.c
View file

@ -81,13 +81,13 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/* SPI Clocking.

12
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -2113,7 +2113,7 @@ static int lpc31_async_setup(struct lpc31_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_ASYNCXFR, epinfo->epno, buflen);
#else
uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
uinfo("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
RHPORT(rhport), epinfo->epno, buffer, buflen, req);
#endif
@ -2391,7 +2391,7 @@ static int lpc31_intr_setup(struct lpc31_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_INTRXFR, epinfo->epno, buflen);
#else
uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
uinfo("RHport%d EP%d: buffer=%p, buflen=%d\n",
RHPORT(rhport), epinfo->epno, buffer, buflen);
#endif
@ -3377,7 +3377,7 @@ static int lpc31_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@ -3909,7 +3909,7 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_EPALLOC, epdesc->addr, epdesc->xfrtype);
#else
uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
uinfo("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
epdesc->addr, epdesc->in ? "IN" : "OUT", hport->funcaddr,
epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
#endif
@ -4199,7 +4199,7 @@ static int lpc31_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_CTRLINOUT, RHPORT(rhport), req->req);
#else
uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
RHPORT(rhport), req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], len);
#endif
@ -4687,7 +4687,7 @@ static int lpc31_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

4
arch/arm/src/lpc31xx/lpc31_serial.c
View file

@ -541,7 +541,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = getreg32(LPC31_UART_MSR);
fvdbg("MSR: %02x\n", status);
finfo("MSR: %02x\n", status);
break;
}
@ -552,7 +552,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = getreg32(LPC31_UART_LSR);
fvdbg("LSR: %02x\n", status);
finfo("LSR: %02x\n", status);
break;
}

6
arch/arm/src/lpc31xx/lpc31_usbdev.c
View file

@ -1183,7 +1183,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1323,7 +1323,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullvdbg("test mode: %d\n", index);
ullinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2083,7 +2083,7 @@ static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

12
arch/arm/src/lpc43xx/lpc43_ehci.c
View file

@ -1989,7 +1989,7 @@ static int lpc43_async_setup(struct lpc43_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_ASYNCXFR, epinfo->epno, buflen);
#else
uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
uinfo("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
RHPORT(rhport), epinfo->epno, buffer, buflen, req);
#endif
@ -2267,7 +2267,7 @@ static int lpc43_intr_setup(struct lpc43_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_INTRXFR, epinfo->epno, buflen);
#else
uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
uinfo("RHport%d EP%d: buffer=%p, buflen=%d\n",
RHPORT(rhport), epinfo->epno, buffer, buflen);
#endif
@ -3207,7 +3207,7 @@ static int lpc43_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@ -3739,7 +3739,7 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_EPALLOC, epdesc->addr, epdesc->xfrtype);
#else
uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
uinfo("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
epdesc->addr, epdesc->in ? "IN" : "OUT", hport->funcaddr,
epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
#endif
@ -4023,7 +4023,7 @@ static int lpc43_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_CTRLINOUT, RHPORT(rhport), req->req);
#else
uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
RHPORT(rhport), req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], len);
#endif
@ -4511,7 +4511,7 @@ static int lpc43_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

50
arch/arm/src/lpc43xx/lpc43_ethernet.c
View file

@ -947,7 +947,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
txdesc = priv->txhead;
txfirst = txdesc;
nllvdbg("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
@ -964,7 +964,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
bufcount = (priv->dev.d_len + (CONFIG_LPC43_ETH_BUFSIZE-1)) / CONFIG_LPC43_ETH_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_LPC43_ETH_BUFSIZE;
nllvdbg("bufcount: %d lastsize: %d\n", bufcount, lastsize);
nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
/* Set the first segment bit in the first TX descriptor */
@ -1074,7 +1074,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
priv->inflight++;
nllvdbg("txhead: %p txtail: %p inflight: %d\n",
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
@ -1373,7 +1373,7 @@ static void lpc43_freesegment(FAR struct lpc43_ethmac_s *priv,
struct eth_rxdesc_s *rxdesc;
int i;
nllvdbg("rxfirst: %p segments: %d\n", rxfirst, segments);
nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
@ -1431,7 +1431,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
uint8_t *buffer;
int i;
nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if there are free buffers. We cannot receive new frames in this
@ -1497,7 +1497,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
rxcurr = priv->rxcurr;
}
nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if any errors are reported in the frame */
@ -1536,7 +1536,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
lpc43_freesegment(priv, rxcurr, priv->segments);
nllvdbg("rxhead: %p d_buf: %p d_len: %d\n",
nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
priv->rxhead, dev->d_buf, dev->d_len);
return OK;
@ -1563,7 +1563,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = rxdesc;
nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
return -EAGAIN;
@ -1632,7 +1632,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1672,7 +1672,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1709,7 +1709,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllvdbg("ARP frame\n");
nllinfo("ARP frame\n");
/* Handle ARP packet */
@ -1768,7 +1768,7 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
int i;
nllvdbg("txhead: %p txtail: %p inflight: %d\n",
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* Scan for "in-flight" descriptors owned by the CPU */
@ -1784,7 +1784,7 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
* TX descriptors.
*/
nllvdbg("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
DEBUGASSERT(txdesc->tdes2 != 0);
@ -1837,7 +1837,7 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
priv->txtail = txdesc;
nllvdbg("txhead: %p txtail: %p inflight: %d\n",
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
}
}
@ -2480,7 +2480,7 @@ static int lpc43_ifdown(struct net_driver_s *dev)
static inline void lpc43_txavail_process(FAR struct lpc43_ethmac_s *priv)
{
nvdbg("ifup: %d\n", priv->ifup);
ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@ -2647,7 +2647,7 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Add the MAC address to the hardware multicast hash table */
@ -2704,7 +2704,7 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Remove the MAC address to the hardware multicast hash table */
@ -3172,7 +3172,7 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv)
up_systemreset();
}
nvdbg("PHY ID1: 0x%04X\n", phyval);
ninfo("PHY ID1: 0x%04X\n", phyval);
/* Now check the "DAVICOM Specified Configuration Register (DSCR)", Register 16 */
@ -3330,7 +3330,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
/* Remember the selected speed and duplex modes */
nvdbg("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval);
ninfo("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval);
#ifdef CONFIG_ETH0_PHY_LAN8720
if ((phyval & (MII_MSR_100BASETXHALF | MII_MSR_100BASETXFULL)) != 0)
@ -3718,7 +3718,7 @@ static void lpc43_macaddress(FAR struct lpc43_ethmac_s *priv)
FAR struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
@ -3786,7 +3786,7 @@ static void lpc43_ipv6multicast(FAR struct lpc43_ethmac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)lpc43_addmac(dev, mac);
@ -3925,12 +3925,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Reset the Ethernet block */
nllvdbg("Reset the Ethernet block\n");
nllinfo("Reset the Ethernet block\n");
lpc43_ethreset(priv);
/* Initialize the PHY */
nllvdbg("Initialize the PHY\n");
nllinfo("Initialize the PHY\n");
ret = lpc43_phyinit(priv);
if (ret < 0)
{
@ -3945,7 +3945,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Initialize the MAC and DMA */
nllvdbg("Initialize the MAC and DMA\n");
nllinfo("Initialize the MAC and DMA\n");
ret = lpc43_macconfig(priv);
if (ret < 0)
{
@ -3966,7 +3966,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Enable normal MAC operation */
nllvdbg("Enable normal operation\n");
nllinfo("Enable normal operation\n");
return lpc43_macenable(priv);
}

6
arch/arm/src/lpc43xx/lpc43_gpdma.c
View file

@ -69,14 +69,14 @@
#ifdef DMA_DEBUG
# define dmadbg lldbg
# ifdef DMA_VERBOSE
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# undef DMA_VERBOSE
# define dmadbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/****************************************************************************

2
arch/arm/src/lpc43xx/lpc43_idle.c
View file

@ -98,7 +98,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

4
arch/arm/src/lpc43xx/lpc43_serial.c
View file

@ -854,7 +854,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, LPC43_UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
info("MSR: %02x\n", status);
break;
}
@ -865,7 +865,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC43_UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
info("LSR: %02x\n", status);
break;
}

6
arch/arm/src/lpc43xx/lpc43_spi.c
View file

@ -69,14 +69,14 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# undef CONFIG_DEBUG_INFO
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
/* SPI Clocking.

96
arch/arm/src/lpc43xx/lpc43_spifi.c
View file

@ -382,7 +382,7 @@ static void lpc43_blockerase(struct lpc43_dev_s *priv, off_t sector)
priv->operands.dest = SPIFI_BASE + (sector << SPIFI_BLKSHIFT);
priv->operands.length = SPIFI_BLKSIZE;
fvdbg("SPIFI_ERASE: dest=%p length=%d\n",
finfo("SPIFI_ERASE: dest=%p length=%d\n",
priv->operands.dest, priv->operands.length);
result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
@ -411,7 +411,7 @@ static inline int lpc43_chiperase(struct lpc43_dev_s *priv)
priv->operands.dest = SPIFI_BASE;
priv->operands.length = SPIFI_BLKSIZE * priv->nblocks;
fvdbg("SPIFI_ERASE: dest=%p length=%d\n",
finfo("SPIFI_ERASE: dest=%p length=%d\n",
priv->operands.dest, priv->operands.length);
result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
@ -457,7 +457,7 @@ static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
priv->operands.dest = dest;
priv->operands.length = nbytes;
fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n",
finfo("SPIFI_PROGRAM: src=%p dest=%p length=%d\n",
src, priv->operands.dest, priv->operands.length);
result = SPIFI_PROGRAM(priv, &priv->rom, src, &priv->operands);
@ -492,7 +492,7 @@ static inline void lpc43_pageread(FAR struct lpc43_dev_s *priv,
FAR uint8_t *dest, FAR const uint8_t *src,
size_t nbytes)
{
fvdbg("src=%p dest=%p length=%d\n", src, dest, nbytes);
finfo("src=%p dest=%p length=%d\n", src, dest, nbytes);
memcpy(dest, src, nbytes);
}
@ -511,7 +511,7 @@ static void lpc43_cacheflush(struct lpc43_dev_s *priv)
* the cached erase block to FLASH.
*/
fvdbg("flags: %02x blkno: %d\n", priv->flags, priv->blkno);
finfo("flags: %02x blkno: %d\n", priv->flags, priv->blkno);
if (IS_DIRTY(priv) || IS_ERASED(priv))
{
/* Get the SPIFI address corresponding to the cached erase block */
@ -551,7 +551,7 @@ static FAR uint8_t *lpc43_cacheread(struct lpc43_dev_s *priv, off_t sector)
*/
blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
fvdbg("sector: %ld blkno: %d\n", sector, blkno);
finfo("sector: %ld blkno: %d\n", sector, blkno);
/* Check if the requested erase block is already in the cache */
@ -612,7 +612,7 @@ static void lpc43_cacheerase(struct lpc43_dev_s *priv, off_t sector)
if (!IS_ERASED(priv))
{
off_t blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
fvdbg("sector: %ld blkno: %d\n", sector, blkno);
finfo("sector: %ld blkno: %d\n", sector, blkno);
lpc43_blockerase(priv, blkno);
SET_ERASED(priv);
@ -646,7 +646,7 @@ static void lpc43_cachewrite(FAR struct lpc43_dev_s *priv, FAR const uint8_t *bu
dest = lpc43_cacheread(priv, sector);
fvdbg("dest=%p src=%p sector: %ld flags: %02x\n",
finfo("dest=%p src=%p sector: %ld flags: %02x\n",
dest, buffer, sector, priv->flags);
/* Erase the block containing this sector if it is not already erased.
@ -657,7 +657,7 @@ static void lpc43_cachewrite(FAR struct lpc43_dev_s *priv, FAR const uint8_t *bu
if (!IS_ERASED(priv))
{
off_t blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
fvdbg("sector: %ld blkno: %d\n", sector, blkno);
finfo("sector: %ld blkno: %d\n", sector, blkno);
lpc43_blockerase(priv, blkno);
SET_ERASED(priv);
@ -692,7 +692,7 @@ static int lpc43_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nbloc
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
size_t blocksleft = nblocks;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
while (blocksleft-- > 0)
{
@ -726,7 +726,7 @@ static ssize_t lpc43_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
#ifdef CONFIG_SPIFI_SECTOR512
ssize_t nbytes;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* On this device, we can handle the block read just like the byte-oriented read */
@ -743,7 +743,7 @@ static ssize_t lpc43_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
ssize_t nbytes;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* On this device, we can handle the block read just like the byte-oriented read */
@ -774,7 +774,7 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
lpc43_cachewrite(priv, buffer, startblock, nblocks);
@ -786,7 +786,7 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
FAR uint8_t *dest;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* Get the SPIFI address corresponding to the erase block */
@ -819,7 +819,7 @@ static ssize_t lpc43_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
FAR const uint8_t *src;
fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Get the SPIFI address corresponding sector */
@ -829,7 +829,7 @@ static ssize_t lpc43_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
lpc43_pageread(priv, buffer, src, nbytes);
fvdbg("return nbytes: %d\n", (int)nbytes);
finfo("return nbytes: %d\n", (int)nbytes);
return nbytes;
}
@ -842,7 +842,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
int ret = -EINVAL; /* Assume good command with bad parameters */
fvdbg("cmd: %d \n", cmd);
finfo("cmd: %d \n", cmd);
switch (cmd)
{
@ -871,7 +871,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
#endif
ret = OK;
fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
finfo("blocksize: %d erasesize: %d neraseblocks: %d\n",
geo->blocksize, geo->erasesize, geo->neraseblocks);
}
}
@ -891,7 +891,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
break;
}
fvdbg("return %d\n", ret);
finfo("return %d\n", ret);
return ret;
}
@ -1038,24 +1038,24 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
}
}
fvdbg("SPFI:\n");
fvdbg(" base: %08x\n", priv->rom.base);
fvdbg(" regbase: %08x\n", priv->rom.regbase);
fvdbg(" devsize: %08x\n", priv->rom.devsize);
fvdbg(" memsize: %08x\n", priv->rom.memsize);
fvdbg(" mfger: %02x\n", priv->rom.mfger);
fvdbg(" devtype: %02x\n", priv->rom.devtype);
fvdbg(" devid: %02x\n", priv->rom.devid);
fvdbg(" busy: %02x\n", priv->rom.busy);
fvdbg(" stat: %04x\n", priv->rom.stat.h);
fvdbg(" setprot: %04x\n", priv->rom.setprot);
fvdbg(" writeprot: %04x\n", priv->rom.writeprot);
fvdbg(" memcmd: %08x\n", priv->rom.memcmd);
fvdbg(" progcmd: %08x\n", priv->rom.progcmd);
fvdbg(" sectors: %04x\n", priv->rom.sectors);
fvdbg(" protbytes: %04x\n", priv->rom.protbytes);
fvdbg(" opts: %08x\n", priv->rom.opts);
fvdbg(" errcheck: %08x\n", priv->rom.errcheck);
finfo("SPFI:\n");
finfo(" base: %08x\n", priv->rom.base);
finfo(" regbase: %08x\n", priv->rom.regbase);
finfo(" devsize: %08x\n", priv->rom.devsize);
finfo(" memsize: %08x\n", priv->rom.memsize);
finfo(" mfger: %02x\n", priv->rom.mfger);
finfo(" devtype: %02x\n", priv->rom.devtype);
finfo(" devid: %02x\n", priv->rom.devid);
finfo(" busy: %02x\n", priv->rom.busy);
finfo(" stat: %04x\n", priv->rom.stat.h);
finfo(" setprot: %04x\n", priv->rom.setprot);
finfo(" writeprot: %04x\n", priv->rom.writeprot);
finfo(" memcmd: %08x\n", priv->rom.memcmd);
finfo(" progcmd: %08x\n", priv->rom.progcmd);
finfo(" sectors: %04x\n", priv->rom.sectors);
finfo(" protbytes: %04x\n", priv->rom.protbytes);
finfo(" opts: %08x\n", priv->rom.opts);
finfo(" errcheck: %08x\n", priv->rom.errcheck);
/* Get the largest erase block size */
@ -1065,11 +1065,11 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
sectors = priv->rom.sectors;
log2 = 0;
fvdbg("FLASH Geometry:\n");
finfo("FLASH Geometry:\n");
while (sectors > 0)
{
fvdbg(" log2: %d rept: %d\n", desc->log2, desc->rept);
finfo(" log2: %d rept: %d\n", desc->log2, desc->rept);
/* Check if this is the largest erase block size seen */
@ -1091,10 +1091,10 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
priv->blksize = (1 << log2);
priv->nblocks = (priv->rom.memsize - CONFIG_SPIFI_OFFSET) / priv->blksize;
fvdbg("Driver FLASH Geometry:\n");
fvdbg(" blkshift: %d\n", priv->blkshift);
fvdbg(" blksize: %08x\n", priv->blksize);
fvdbg(" nblocks: %d\n", priv->nblocks);
finfo("Driver FLASH Geometry:\n");
finfo(" blkshift: %d\n", priv->blkshift);
finfo(" blksize: %08x\n", priv->blksize);
finfo(" nblocks: %d\n", priv->nblocks);
#ifdef CONFIG_SPIFI_SECTOR512
DEBUGASSERT(log2 > 9);
@ -1106,10 +1106,10 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
priv->nblocks = ((priv->rom.memsize - CONFIG_SPIFI_OFFSET) >> SPIFI_BLKSHIFT);
fvdbg("Driver FLASH Geometry:\n");
fvdbg(" blkshift: %d\n", SPIFI_BLKSHIFT);
fvdbg(" blksize: %08x\n", SPIFI_BLKSIZE);
fvdbg(" nblocks: %d\n", priv->nblocks);
finfo("Driver FLASH Geometry:\n");
finfo(" blkshift: %d\n", SPIFI_BLKSHIFT);
finfo(" blksize: %08x\n", SPIFI_BLKSIZE);
finfo(" nblocks: %d\n", priv->nblocks);
#endif
return OK;
@ -1208,7 +1208,7 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void)
/* Return the implementation-specific state structure as the MTD device */
fvdbg("Return %p\n", priv);
finfo("Return %p\n", priv);
return (FAR struct mtd_dev_s *)priv;
}

10
arch/arm/src/lpc43xx/lpc43_ssp.c
View file

@ -78,14 +78,14 @@
#ifdef CONFIG_SSP_DEBUG
# define sspdbg lldbg
# ifdef CONFIG_SSP_VERBOSE
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# undef CONFIG_SSP_VERBOSE
# define sspdbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
@ -576,7 +576,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC43_SSP_FIFOSZ) && nwords)
{
@ -599,7 +599,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
spivdbg("RX: rxpending: %d\n", rxpending);
spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);

6
arch/arm/src/lpc43xx/lpc43_usb0dev.c
View file

@ -1228,7 +1228,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
priv->ep0buf_len = len;
ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl->type, ctrl->req, value, index, len);
/* Starting a control request - update state */
@ -1393,7 +1393,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullvdbg("test mode: %d\n", index);
ullinfo("test mode: %d\n", index);
}
else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2206,7 +2206,7 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

2
arch/arm/src/nuc1xx/nuc_idle.c
View file

@ -99,7 +99,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

8
arch/arm/src/sam34/sam4cm_freerun.c
View file

@ -121,7 +121,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
uint32_t cmr;
int ret;
tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
tcinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(freerun && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@ -137,7 +137,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
return ret;
}
tcvdbg("frequency=%lu, divisor=%u, cmr=%08lx\n",
tcinfo("frequency=%lu, divisor=%u, cmr=%08lx\n",
(unsigned long)frequency, (unsigned long)divisor,
(unsigned long)cmr);
@ -257,7 +257,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
leave_critical_section(flags);
tcvdbg("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
tcinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
(unsigned long)counter, (unsigned long)verify,
(unsigned long)overflow, (unsigned long)sr);
@ -277,7 +277,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
tcvdbg("usec=%llu ts=(%lu, %lu)\n",
tcinfo("usec=%llu ts=(%lu, %lu)\n",
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
return OK;

18
arch/arm/src/sam34/sam4cm_oneshot.c
View file

@ -91,7 +91,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
tcllvdbg("Expired...\n");
tcllinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
@ -148,7 +148,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint32_t cmr;
int ret;
tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
tcinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(oneshot && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@ -164,7 +164,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
return ret;
}
tcvdbg("frequency=%lu, divisor=%lu, cmr=%08lx\n",
tcinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n",
(unsigned long)frequency, (unsigned long)divisor,
(unsigned long)cmr);
@ -258,7 +258,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
uint64_t regval;
irqstate_t flags;
tcvdbg("handler=%p arg=%p, ts=(%lu, %lu)\n",
tcinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
@ -269,7 +269,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
{
/* Yes.. then cancel it */
tcvdbg("Already running... cancelling\n");
tcinfo("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
@ -291,7 +291,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
tcvdbg("usec=%llu regval=%08llx\n", usec, regval);
tcinfo("usec=%llu regval=%08llx\n", usec, regval);
DEBUGASSERT(regval <= UINT16_MAX);
/* Set up to receive the callback when the interrupt occurs */
@ -400,7 +400,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* REVISIT: This does not appear to be the case.
*/
tcvdbg("Cancelling...\n");
tcinfo("Cancelling...\n");
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
@ -436,7 +436,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* oneshot timer.
*/
tcvdbg("rc=%lu count=%lu usec=%lu\n",
tcinfo("rc=%lu count=%lu usec=%lu\n",
(unsigned long)rc, (unsigned long)count, (unsigned long)usec);
/* REVISIT: I am not certain why the timer counter value sometimes
@ -481,7 +481,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
ts->tv_nsec = (unsigned long)nsec;
}
tcvdbg("remaining (%lu, %lu)\n",
tcinfo("remaining (%lu, %lu)\n",
(unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
}

18
arch/arm/src/sam34/sam4cm_tc.c
View file

@ -876,7 +876,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
* access to the requested channel.
*/
tcvdbg("channel=%d mode=%08x\n", channel, mode);
tcinfo("channel=%d mode=%08x\n", channel, mode);
chan = sam_tc_initialize(channel);
if (chan)
@ -902,7 +902,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
/* Return an opaque reference to the channel */
tcvdbg("Returning %p\n", chan);
tcinfo("Returning %p\n", chan);
return (TC_HANDLE)chan;
}
@ -924,7 +924,7 @@ void sam_tc_free(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
tcvdbg("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
tcinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Make sure that interrupts are detached and disabled and that the channel
@ -957,7 +957,7 @@ void sam_tc_start(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
tcvdbg("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
tcinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Read the SR to clear any pending interrupts on this channel */
@ -989,7 +989,7 @@ void sam_tc_stop(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
tcvdbg("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
tcinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS);
@ -1096,7 +1096,7 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval)
DEBUGASSERT(chan && regid < TC_NREGISTERS);
tcvdbg("Channel %d: Set register RC%d to %08lx\n",
tcinfo("Channel %d: Set register RC%d to %08lx\n",
chan->chan, regid, (unsigned long)regval);
sam_chan_putreg(chan, g_regoffset[regid], regval);
@ -1233,7 +1233,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
uint32_t ftcin = sam_tc_infreq();
int ndx = 0;
tcvdbg("frequency=%d\n", frequency);
tcinfo("frequency=%d\n", frequency);
/* Satisfy lower bound. That is, the value of the divider such that:
*
@ -1270,7 +1270,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
if (div)
{
uint32_t value = sam_tc_freqdiv_lookup(ftcin, ndx);
tcvdbg("return div=%lu\n", (unsigned long)value);
tcinfo("return div=%lu\n", (unsigned long)value);
*div = value;
}
@ -1278,7 +1278,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
if (tcclks)
{
tcvdbg("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx));
tcinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx));
*tcclks = TC_CMR_TCCLKS(ndx);
}

8
arch/arm/src/sam34/sam4cm_tc.h
View file

@ -84,14 +84,14 @@
#ifdef CONFIG_SAM34_TC_DEBUG
# define tcdbg dbg
# define tcvdbg vdbg
# define tcinfo info
# define tclldbg lldbg
# define tcllvdbg llvdbg
# define tcllinfo llinfo
#else
# define tcdbg(x...)
# define tcvdbg(x...)
# define tcinfo(x...)
# define tclldbg(x...)
# define tcllvdbg(x...)
# define tcllinfo(x...)
#endif
/****************************************************************************

2
arch/arm/src/sam34/sam4cm_tickless.c
View file

@ -197,7 +197,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
tcllvdbg("Expired...\n");
tcllinfo("Expired...\n");
sched_timer_expiration();
}

20
arch/arm/src/sam34/sam_dmac.c
View file

@ -1354,7 +1354,7 @@ static int sam_dmainterrupt(int irq, void *context)
void weak_function up_dmainitialize(void)
{
dmallvdbg("Initialize DMAC0\n");
dmallinfo("Initialize DMAC0\n");
/* Enable peripheral clock */
@ -1460,7 +1460,7 @@ DMA_HANDLE sam_dmachannel(uint32_t chflags)
sam_givechsem();
dmavdbg("chflags: %08x returning dmach: %p\n", (int)chflags, dmach);
dmainfo("chflags: %08x returning dmach: %p\n", (int)chflags, dmach);
return (DMA_HANDLE)dmach;
}
@ -1486,7 +1486,7 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
/* Set the new DMA channel flags. */
dmavdbg("chflags: %08x\n", (int)chflags);
dmainfo("chflags: %08x\n", (int)chflags);
dmach->flags = chflags;
}
@ -1507,7 +1507,7 @@ void sam_dmafree(DMA_HANDLE handle)
{
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
dmavdbg("dmach: %p\n", dmach);
dmainfo("dmach: %p\n", dmach);
DEBUGASSERT((dmach != NULL) && (dmach->inuse));
/* Mark the channel no longer in use. Clearing the inuse flag is an atomic
@ -1536,10 +1536,10 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nby
size_t maxtransfer;
int ret = OK;
dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@ -1604,10 +1604,10 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nby
size_t maxtransfer;
int ret = OK;
dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@ -1667,7 +1667,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
int ret = -EINVAL;
dmavdbg("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
dmainfo("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
DEBUGASSERT(dmach != NULL);
/* Verify that the DMA has been setup (i.e., at least one entry in the
@ -1711,7 +1711,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
irqstate_t flags;
dmavdbg("dmach: %p\n", dmach);
dmainfo("dmach: %p\n", dmach);
DEBUGASSERT(dmach != NULL);
flags = enter_critical_section();

76
arch/arm/src/sam34/sam_emac.c
View file

@ -753,7 +753,7 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
nllvdbg("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
@ -830,7 +830,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllvdbg("Disabling RX interrupts\n");
nllinfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@ -1010,7 +1010,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
sam_cmcc_invalidate((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllvdbg("rxndx: %d\n", rxndx);
nllinfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1060,7 +1060,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1107,7 +1107,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1132,7 +1132,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
@ -1167,7 +1167,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllvdbg("rxndx: %d\n", priv->rxndx);
nllinfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1222,7 +1222,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1262,7 +1262,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1299,7 +1299,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllvdbg("ARP frame\n");
nllinfo("ARP frame\n");
/* Handle ARP packet */
@ -1442,7 +1442,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllvdbg("isr: %08x pending: %08x\n", isr, pending);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -1962,7 +1962,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
nllvdbg("Initialize the EMAC\n");
nllinfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -1994,11 +1994,11 @@ static int sam_ifup(struct net_driver_s *dev)
}
while (sam_linkup(priv) == 0);
nllvdbg("Link detected \n");
nllinfo("Link detected \n");
/* Enable normal MAC operation */
nllvdbg("Enable normal operation\n");
nllinfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -2077,7 +2077,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
nllvdbg("ifup: %d\n", priv->ifup);
nllinfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@ -2331,7 +2331,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2405,7 +2405,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2601,21 +2601,21 @@ static void sam_phydump(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAM34_EMAC_RMII
nllvdbg("RMII Registers (Address %02x)\n", priv->phyaddr);
nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else /* defined(CONFIG_SAM34_EMAC_MII) */
nllvdbg("MII Registers (Address %02x)\n", priv->phyaddr);
nllinfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
nllvdbg(" MCR: %04x\n", phyval);
nllinfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
nllvdbg(" MSR: %04x\n", phyval);
nllinfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
nllvdbg(" ADVERTISE: %04x\n", phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
nllvdbg(" LPR: %04x\n", phyval);
nllinfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &phyval);
nllvdbg(" PHYSR: %04x\n", phyval);
nllinfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@ -2738,7 +2738,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
nllvdbg(" sam_phyreset\n");
nllinfo(" sam_phyreset\n");
/* Enable management port */
@ -2805,7 +2805,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllvdbg("Find a valid PHY address\n");
nllinfo("Find a valid PHY address\n");
/* Enable management port */
@ -2850,10 +2850,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAM34_EMAC_PHYSR, &phyval);
nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@ -3030,7 +3030,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
@ -3039,14 +3039,14 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
nllvdbg(" Vendor Model Number: %04x\n",
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllvdbg(" Model Revision Number: %04x\n",
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
@ -3118,7 +3118,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg(" MCR: %04x\n", mcr);
nllinfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@ -3138,7 +3138,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
nllvdbg("AutoNegotiate complete\n");
nllinfo("AutoNegotiate complete\n");
break;
}
@ -3297,7 +3297,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
nllvdbg("Link is up\n");
nllinfo("Link is up\n");
linkup = true;
errout:
@ -3598,7 +3598,7 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
@ -3664,7 +3664,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@ -3710,7 +3710,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
nllvdbg("Entry\n");
nllinfo("Entry\n");
/* Enable clocking to the EMAC peripheral */

18
arch/arm/src/sam34/sam_hsmci.c
View file

@ -1320,7 +1320,7 @@ static int sam_interrupt(int irq, void *context)
{
/* Yes.. Was the error some kind of timeout? */
fllvdbg("ERROR: events: %08x SR: %08x\n",
fllinfo("ERROR: events: %08x SR: %08x\n",
priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@ -1754,7 +1754,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
/* Write the fully decorated command to CMDR */
fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
putreg32(regval, SAM_HSMCI_CMDR);
sam_cmdsample1(SAMPLENDX_AFTER_CMDR);
return OK;
@ -2348,7 +2348,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
fvdbg("eventset: %02x\n", eventset);
finfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@ -2384,7 +2384,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
fvdbg("Register %p(%p)\n", callback, arg);
finfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@ -2581,7 +2581,7 @@ static void sam_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
@ -2626,14 +2626,14 @@ static void sam_callback(void *arg)
{
/* Yes.. queue it */
fllvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@ -2741,7 +2741,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
fllvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@ -2786,7 +2786,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
fvdbg("cdstatus: %02x\n", priv->cdstatus);
finfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_SAM34_HSMCI */

8
arch/arm/src/sam34/sam_rtc.c
View file

@ -90,14 +90,14 @@
#ifdef CONFIG_DEBUG_RTC
# define rtcdbg dbg
# define rtcvdbg vdbg
# define rtcinfo info
# define rtclldbg lldbg
# define rtcllvdbg llvdbg
# define rtcllinfo llinfo
#else
# define rtcdbg(x...)
# define rtcvdbg(x...)
# define rtcinfo(x...)
# define rtclldbg(x...)
# define rtcllvdbg(x...)
# define rtcllinfo(x...)
#endif
/************************************************************************************

28
arch/arm/src/sam34/sam_rtt.c
View file

@ -82,10 +82,10 @@
#ifdef CONFIG_DEBUG_RTT
# define rttdbg lldbg
# define rttvdbg llvdbg
# define rttinfo llinfo
#else
# define rttdbg(x...)
# define rttvdbg(x...)
# define rttinfo(x...)
#endif
/****************************************************************************
@ -287,7 +287,7 @@ static int sam34_interrupt(int irq, FAR void *context)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
rttvdbg("Entry\n");
rttinfo("Entry\n");
DEBUGASSERT(irq == SAM_IRQ_RTT);
/* Check if the interrupt is really pending */
@ -373,7 +373,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
uint32_t mr;
uint32_t vr;
rttvdbg("Entry\n");
rttinfo("Entry\n");
DEBUGASSERT(priv);
if (priv->started)
@ -433,7 +433,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
rttvdbg("Entry\n");
rttinfo("Entry\n");
DEBUGASSERT(priv);
if (!priv->started)
@ -474,7 +474,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
rttvdbg("Entry\n");
rttinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@ -498,9 +498,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
status->timeleft = 1000000ULL*(sam34_getreg(SAM_RTT_AR) - sam34_readvr())/RTT_FCLK;
rttvdbg(" flags : %08x\n", status->flags);
rttvdbg(" timeout : %d\n", status->timeout);
rttvdbg(" timeleft : %d\n", status->timeleft);
rttinfo(" flags : %08x\n", status->flags);
rttinfo(" timeout : %d\n", status->timeout);
rttinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@ -526,7 +526,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
DEBUGASSERT(priv);
rttvdbg("Entry: timeout=%d\n", timeout);
rttinfo("Entry: timeout=%d\n", timeout);
if (priv->started)
{
@ -547,7 +547,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
timeout = (1000000ULL * priv->clkticks) / RTT_FCLK; /* Truncated timeout */
priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */
rttvdbg("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
rttinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
RTT_FCLK, priv->clkticks, priv->timeout, priv->adjustment);
return OK;
@ -582,7 +582,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower,
flags = enter_critical_section();
DEBUGASSERT(priv);
rttvdbg("Entry: handler=%p\n", handler);
rttinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@ -623,7 +623,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
rttvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
rttinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
UNUSED(priv);
return ret;
@ -653,7 +653,7 @@ void sam_rttinitialize(FAR const char *devpath)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
rttvdbg("Entry: devpath=%s\n", devpath);
rttinfo("Entry: devpath=%s\n", devpath);
/* Initialize the driver state structure. Here we assume: (1) the state
* structure lies in .bss and was zeroed at reset time. (2) This function

42
arch/arm/src/sam34/sam_spi.c
View file

@ -150,13 +150,13 @@
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef CONFIG_DEBUG_INFO
# define spivdbg lldbg
# define spiinfo lldbg
# else
# define spivdbg(x...)
# define spiinfo(x...)
# endif
#else
# define spidbg(x...)
# define spivdbg(x...)
# define spiinfo(x...)
#endif
#define DMA_INITIAL 0
@ -523,17 +523,17 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_INFO)
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg)
{
spivdbg("%s:\n", msg);
spivdbg(" MR:%08x SR:%08x IMR:%08x\n",
spiinfo("%s:\n", msg);
spiinfo(" MR:%08x SR:%08x IMR:%08x\n",
getreg32(spi->base + SAM_SPI_MR_OFFSET),
getreg32(spi->base + SAM_SPI_SR_OFFSET),
getreg32(spi->base + SAM_SPI_IMR_OFFSET));
spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
spiinfo(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
getreg32(spi->base + SAM_SPI_CSR0_OFFSET),
getreg32(spi->base + SAM_SPI_CSR1_OFFSET),
getreg32(spi->base + SAM_SPI_CSR2_OFFSET),
getreg32(spi->base + SAM_SPI_CSR3_OFFSET));
spivdbg(" WPCR:%08x WPSR:%08x\n",
spiinfo(" WPCR:%08x WPSR:%08x\n",
getreg32(spi->base + SAM_SPI_WPCR_OFFSET),
getreg32(spi->base + SAM_SPI_WPSR_OFFSET));
}
@ -893,7 +893,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
spivdbg("lock=%d\n", lock);
spiinfo("lock=%d\n", lock);
if (lock)
{
/* Take the semaphore (perhaps waiting) */
@ -941,10 +941,10 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
/* Are we selecting or de-selecting the device? */
spivdbg("selected=%d\n", selected);
spiinfo("selected=%d\n", selected);
if (selected)
{
spivdbg("cs=%d\n", spics->cs);
spiinfo("cs=%d\n", spics->cs);
/* Before writing the TDR, the PCS field in the SPI_MR register must be set
* in order to select a slave.
@ -999,7 +999,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
uint32_t regval;
unsigned int offset;
spivdbg("cs=%d frequency=%d\n", spics->cs, frequency);
spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
/* Check if the requested frequency is the same as the frequency selection */
@ -1069,7 +1069,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
/* Calculate the new actual frequency */
actual = SAM_SPI_CLOCK / scbr;
spivdbg("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
spiinfo("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
/* Save the frequency setting */
@ -1102,7 +1102,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t regval;
unsigned int offset;
spivdbg("cs=%d mode=%d\n", spics->cs, mode);
spiinfo("cs=%d mode=%d\n", spics->cs, mode);
/* Has the mode changed? */
@ -1145,7 +1145,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
}
spi_putreg(spi, regval, offset);
spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the mode so that subsequent re-configurations will be faster */
@ -1175,7 +1175,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
uint32_t regval;
unsigned int offset;
spivdbg("cs=%d nbits=%d\n", spics->cs, nbits);
spiinfo("cs=%d nbits=%d\n", spics->cs, nbits);
DEBUGASSERT(spics && nbits > 7 && nbits < 17);
/* Has the number of bits changed? */
@ -1190,7 +1190,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
regval |= SPI_CSR_BITS(nbits);
spi_putreg(spi, regval, offset);
spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the selection so the subsequence re-configurations will be faster */
@ -1228,7 +1228,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
rxbyte = (uint8_t)0;
spi_exchange(dev, &txbyte, &rxbyte, 1);
spivdbg("Sent %02x received %02x\n", txbyte, rxbyte);
spiinfo("Sent %02x received %02x\n", txbyte, rxbyte);
return (uint16_t)rxbyte;
}
@ -1276,7 +1276,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint8_t *rxptr8;
uint8_t *txptr8;
spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Set up PCS bits */
@ -1422,7 +1422,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spics = (struct sam_spics_s *)dev;
spi = spi_device(spics);
@ -1745,7 +1745,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
/* The support SAM parts have only a single SPI port */
spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino);
spiinfo("port: %d csno: %d spino: %d\n", port, csno, spino);
DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS);
#if defined(CONFIG_SAM34_SPI0) && defined(CONFIG_SAM34_SPI1)
@ -1924,7 +1924,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi_putreg(spi, regval, offset);
spics->nbits = 8;
spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
return &spics->spidev;
}

30
arch/arm/src/sam34/sam_tc.c
View file

@ -80,10 +80,10 @@
#ifdef CONFIG_DEBUG_TIMER
# define tcdbg lldbg
# define tcvdbg llvdbg
# define tcinfo llinfo
#else
# define tcdbg(x...)
# define tcvdbg(x...)
# define tcinfo(x...)
#endif
/****************************************************************************
@ -268,7 +268,7 @@ static int sam34_interrupt(int irq, FAR void *context)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0];
tcvdbg("Entry\n");
tcinfo("Entry\n");
DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5));
/* Check if the interrupt is really pending */
@ -299,7 +299,7 @@ static int sam34_interrupt(int irq, FAR void *context)
/* No handler or the handler returned false.. stop the timer */
sam34_stop((FAR struct timer_lowerhalf_s *)priv);
tcvdbg("Stopped\n");
tcinfo("Stopped\n");
}
/* TC_INT_CPCS is cleared by reading SAM_TCx_SR */
@ -328,7 +328,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t mr_val;
tcvdbg("Entry\n");
tcinfo("Entry\n");
DEBUGASSERT(priv);
if (priv->started)
@ -382,7 +382,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
tcvdbg("Entry\n");
tcinfo("Entry\n");
DEBUGASSERT(priv);
if (!priv->started)
@ -421,7 +421,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t elapsed;
tcvdbg("Entry\n");
tcinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@ -446,9 +446,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
elapsed = sam34_getreg(priv->base + SAM_TC_CV_OFFSET);
status->timeleft = ((uint64_t)priv->timeout * elapsed) / (priv->clkticks + 1); /* TODO - check on this +1 */
tcvdbg(" flags : %08x\n", status->flags);
tcvdbg(" timeout : %d\n", status->timeout);
tcvdbg(" timeleft : %d\n", status->timeleft);
tcinfo(" flags : %08x\n", status->flags);
tcinfo(" timeout : %d\n", status->timeout);
tcinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@ -480,7 +480,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
return -EPERM;
}
tcvdbg("Entry: timeout=%d\n", timeout);
tcinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
@ -496,7 +496,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
timeout = (1000000ULL * priv->clkticks) / TC_FCLK; /* Truncated timeout */
priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */
tcvdbg("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
tcinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
TC_FCLK, priv->clkticks, priv->timeout, priv->adjustment);
return OK;
@ -531,7 +531,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower,
flags = enter_critical_section();
DEBUGASSERT(priv);
tcvdbg("Entry: handler=%p\n", handler);
tcinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@ -572,7 +572,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
tcvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
tcinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
UNUSED(priv);
return ret;
@ -602,7 +602,7 @@ void sam_tcinitialize(FAR const char *devpath, int irq)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0];
tcvdbg("Entry: devpath=%s\n", devpath);
tcinfo("Entry: devpath=%s\n", devpath);
DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5));
/* Initialize the driver state structure. Here we assume: (1) the state

18
arch/arm/src/sam34/sam_twi.c
View file

@ -100,14 +100,14 @@
#ifdef CONFIG_DEBUG_I2C
# define i2cdbg dbg
# define i2cvdbg vdbg
# define i2cinfo info
# define i2clldbg lldbg
# define i2cllvdbg llvdbg
# define i2cllinfo llinfo
#else
# define i2cdbg(x...)
# define i2cvdbg(x...)
# define i2cinfo(x...)
# define i2clldbg(x...)
# define i2cllvdbg(x...)
# define i2cllinfo(x...)
#endif
/****************************************************************************
@ -460,7 +460,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
pending = sr & imr;
i2cllvdbg("TWI%d pending: %08x\n", priv->twi, pending);
i2cllinfo("TWI%d pending: %08x\n", priv->twi, pending);
msg = priv->msg;
@ -708,7 +708,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
int ret;
DEBUGASSERT(dev != NULL);
i2cvdbg("TWI%d count: %d\n", priv->twi, count);
i2cinfo("TWI%d count: %d\n", priv->twi, count);
/* Get exclusive access to the device */
@ -842,7 +842,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
uint32_t mck;
#endif
i2cvdbg("TWI%d Initializing\n", priv->twi);
i2cinfo("TWI%d Initializing\n", priv->twi);
/* SVEN: TWI Slave Mode Enabled */
@ -925,7 +925,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
uint32_t frequency;
unsigned int pid;
i2cvdbg("Initializing TWI%d\n", bus);
i2cinfo("Initializing TWI%d\n", bus);
flags = enter_critical_section();
@ -1029,7 +1029,7 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
i2cvdbg("TWI%d Un-initializing\n", priv->twi);
i2cinfo("TWI%d Un-initializing\n", priv->twi);
/* Disable interrupts */

10
arch/arm/src/sam34/sam_udp.c
View file

@ -968,7 +968,7 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
ullvdbg("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
@ -1139,7 +1139,7 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
ullvdbg("EP%d: len=%d xfrd=%d\n",
ullinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@ -1408,7 +1408,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@ -1572,7 +1572,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
ullvdbg("test mode: %d\n", index.w);
ullinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2749,7 +2749,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
DEBUGASSERT(privep && privep->dev && desc);
uvdbg("len: %02x type: %02x addr: %02x attr: %02x "
uinfo("len: %02x type: %02x addr: %02x attr: %02x "
"maxpacketsize: %02x %02x interval: %02x\n",
desc->len, desc->type, desc->addr, desc->attr,
desc->mxpacketsize[0], desc->mxpacketsize[1],

30
arch/arm/src/sam34/sam_wdt.c
View file

@ -89,10 +89,10 @@
#ifdef CONFIG_DEBUG_WATCHDOG
# define wddbg lldbg
# define wdvdbg llvdbg
# define wdinfo llinfo
#else
# define wddbg(x...)
# define wdvdbg(x...)
# define wdinfo(x...)
#endif
/****************************************************************************
@ -314,7 +314,7 @@ static int sam34_start(FAR struct watchdog_lowerhalf_s *lower)
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t mr_val = 0;
wdvdbg("Entry\n");
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* The watchdog is always disabled after a reset. It is enabled by setting
@ -360,7 +360,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
* except by a reset.
*/
wdvdbg("Entry\n");
wdinfo("Entry\n");
return -ENOSYS;
}
@ -386,7 +386,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
static int sam34_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
wdvdbg("Entry\n");
wdinfo("Entry\n");
sam34_putreg((WDT_CR_KEY | WDT_CR_WDRSTT), SAM_WDT_CR);
return OK;
@ -414,7 +414,7 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t elapsed;
wdvdbg("Entry\n");
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@ -441,10 +441,10 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
wdvdbg("Status : %08x\n", sam34_getreg(SAM_WDT_SR));
wdvdbg(" flags : %08x\n", status->flags);
wdvdbg(" timeout : %d\n", status->timeout);
wdvdbg(" timeleft : %d\n", status->timeleft);
wdinfo("Status : %08x\n", sam34_getreg(SAM_WDT_SR));
wdinfo(" flags : %08x\n", status->flags);
wdinfo(" timeout : %d\n", status->timeout);
wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@ -471,7 +471,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t reload;
DEBUGASSERT(priv);
wdvdbg("Entry: timeout=%d\n", timeout);
wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
@ -503,7 +503,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->reload = reload;
wdvdbg("fwdt=%d reload=%d timout=%d\n",
wdinfo("fwdt=%d reload=%d timout=%d\n",
WDT_FCLK, reload, priv->timeout);
/* Don't commit to MR register until started! */
@ -543,7 +543,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
uint16_t regval;
DEBUGASSERT(priv);
wdvdbg("Entry: handler=%p\n", handler);
wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@ -611,7 +611,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
wdvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
/* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls
* are received within this time, a reset event will be generated.
@ -676,7 +676,7 @@ void sam_wdtinitialize(FAR const char *devpath)
WDT_MR_WDRSTEN);
sam34_putreg(mr_val, SAM_WDT_MR);
wdvdbg("Entry: devpath=%s\n", devpath);
wdinfo("Entry: devpath=%s\n", devpath);
/* NOTE we assume that clocking to the IWDG has already been provided by
* the RCC initialization logic.

54
arch/arm/src/sama5/sam_adc.c
View file

@ -604,7 +604,7 @@ static void sam_adc_dmadone(void *arg)
int chan;
int i;
avdbg("ready=%d enabled=%d\n", priv->enabled, priv->ready);
ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
ASSERT(priv != NULL && !priv->ready);
/* If the DMA transfer is not enabled, just ignore the data (and do not start
@ -725,7 +725,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
struct sam_adc_s *priv = (struct sam_adc_s *)arg;
int ret;
allvdbg("ready=%d enabled=%d\n", priv->enabled, priv->ready);
allinfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
DEBUGASSERT(priv->ready);
/* Check of the bottom half is keeping up with us.
@ -798,7 +798,7 @@ static int sam_adc_dmasetup(FAR struct sam_adc_s *priv, FAR uint8_t *buffer,
uint32_t paddr;
uint32_t maddr;
avdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
ainfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
DEBUGASSERT(((uint32_t)buffer & 3) == 0);
@ -849,7 +849,7 @@ static void sam_adc_endconversion(void *arg)
int chan;
ASSERT(priv != NULL);
avdbg("pending=%08x\n", priv->pending);
ainfo("pending=%08x\n", priv->pending);
/* Get the set of unmasked, pending ADC interrupts */
@ -1011,7 +1011,7 @@ static void sam_adc_reset(struct adc_dev_s *dev)
#endif
uint32_t regval;
avdbg("Resetting..\n");
ainfo("Resetting..\n");
/* NOTE: We can't really reset the ADC hardware without losing the
* touchscreen configuration.
@ -1081,7 +1081,7 @@ static int sam_adc_setup(struct adc_dev_s *dev)
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
uint32_t regval;
avdbg("Setup\n");
ainfo("Setup\n");
/* Enable channel number tag. This bit will force the channel number (CHNB)
* to be included in the LDCR register content.
@ -1152,7 +1152,7 @@ static void sam_adc_shutdown(struct adc_dev_s *dev)
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
#endif
avdbg("Shutdown\n");
ainfo("Shutdown\n");
/* Reset the ADC peripheral */
@ -1181,7 +1181,7 @@ static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
#endif
avdbg("enable=%d\n", enable);
ainfo("enable=%d\n", enable);
#ifdef CONFIG_SAMA5_ADC_DMA
/* Ignore redundant requests */
@ -1232,7 +1232,7 @@ static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
#endif
int ret = OK;
avdbg("cmd=%d arg=%ld\n", cmd, arg);
ainfo("cmd=%d arg=%ld\n", cmd, arg);
switch (cmd)
{
@ -1277,7 +1277,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
uint32_t regval;
int ret;
avdbg("frequency=%ld channel=%d\n", (long)frequency, channel);
ainfo("frequency=%ld channel=%d\n", (long)frequency, channel);
DEBUGASSERT(priv && frequency > 0);
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
@ -1350,7 +1350,7 @@ static void sam_adc_freetimer(struct sam_adc_s *priv)
{
/* Is a timer allocated? */
avdbg("tc=%p\n", priv->tc);
ainfo("tc=%p\n", priv->tc);
if (priv->tc)
{
@ -1377,7 +1377,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
int ret = OK;
#if defined(CONFIG_SAMA5_ADC_SWTRIG)
avdbg("Setup software trigger\n");
ainfo("Setup software trigger\n");
/* Configure the software trigger */
@ -1393,7 +1393,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
sam_adc_putreg(priv, SAM_ADC_TRGR, regval);
#elif defined(CONFIG_SAMA5_ADC_ADTRG)
avdbg("Setup ADTRG trigger\n");
ainfo("Setup ADTRG trigger\n");
/* Configure the trigger via the external ADTRG signal */
@ -1420,7 +1420,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
sam_adc_putreg(priv, SAM_ADC_TRGR, regval);
#elif defined(CONFIG_SAMA5_ADC_TIOATRIG)
avdbg("Setup timer/counter trigger\n");
ainfo("Setup timer/counter trigger\n");
/* Start the timer */
@ -1500,7 +1500,7 @@ static void sam_adc_autocalibrate(struct sam_adc_s *priv)
#ifdef CONFIG_SAMA5_ADC_AUTOCALIB
uint32_t regval;
avdbg("Entry\n");
ainfo("Entry\n");
/* Launch an automatic calibration of the ADC cell on next sequence */
@ -1527,7 +1527,7 @@ static void sam_adc_offset(struct sam_adc_s *priv)
{
uint32_t regval = 0;
avdbg("Entry\n");
ainfo("Entry\n");
#ifdef CONFIG_SAMA5_ADC_ANARCH
/* Set the offset for each enabled channel. This centers the analog signal
@ -1644,7 +1644,7 @@ static void sam_adc_gain(struct sam_adc_s *priv)
#ifdef CONFIG_SAMA5_ADC_ANARCH
uint32_t regval;
avdbg("Entry\n");
ainfo("Entry\n");
/* Set the gain for each enabled channel */
@ -1690,7 +1690,7 @@ static void sam_adc_gain(struct sam_adc_s *priv)
sam_adc_putreg(priv, SAM_ADC_CGR, regval);
#else
avdbg("Gain=%d\n", CONFIG_SAMA5_ADC_GAIN);
ainfo("Gain=%d\n", CONFIG_SAMA5_ADC_GAIN);
/* Set GAIN0 only. GAIN0 will be used for all channels. */
@ -1711,7 +1711,7 @@ static void sam_adc_analogchange(struct sam_adc_s *priv)
{
uint32_t regval;
avdbg("Entry\n");
ainfo("Entry\n");
/* Enable/disable the analog change feature */
@ -1754,7 +1754,7 @@ static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq)
*seqr1 |= ADC_SEQR1_USCH(seq, chan);
}
avdbg("chan=%d seqr1=%08x seqr2=%08x seq=%d\n", chan, *seqr1, *seqr2, seq);
ainfo("chan=%d seqr1=%08x seqr2=%08x seq=%d\n", chan, *seqr1, *seqr2, seq);
}
#endif
@ -1766,7 +1766,7 @@ static void sam_adc_sequencer(struct sam_adc_s *priv)
uint32_t seqr2;
int seq;
avdbg("Setup sequencer\n");
ainfo("Setup sequencer\n");
/* Set user configured channel sequence */
@ -1855,7 +1855,7 @@ static void sam_adc_sequencer(struct sam_adc_s *priv)
#else
uint32_t regval;
avdbg("Disable sequencer\n");
ainfo("Disable sequencer\n");
/* Disable the sequencer */
@ -1878,7 +1878,7 @@ static void sam_adc_channels(struct sam_adc_s *priv)
{
uint32_t regval;
avdbg("Entry\n");
ainfo("Entry\n");
/* Enable channels. */
@ -1964,7 +1964,7 @@ struct adc_dev_s *sam_adc_initialize(void)
if (!priv->initialized)
{
avdbg("Initializing...\n");
ainfo("Initializing...\n");
/* Disable ADC peripheral clock */
@ -2127,7 +2127,7 @@ struct adc_dev_s *sam_adc_initialize(void)
/* Return a pointer to the device structure */
avdbg("Returning %p\n", &g_adcdev);
ainfo("Returning %p\n", &g_adcdev);
return &g_adcdev;
}
@ -2143,7 +2143,7 @@ void sam_adc_lock(FAR struct sam_adc_s *priv)
{
int ret;
avdbg("Locking\n");
ainfo("Locking\n");
do
{
@ -2168,7 +2168,7 @@ void sam_adc_lock(FAR struct sam_adc_s *priv)
void sam_adc_unlock(FAR struct sam_adc_s *priv)
{
avdbg("Unlocking\n");
ainfo("Unlocking\n");
sem_post(&priv->exclsem);
}

32
arch/arm/src/sama5/sam_can.c
View file

@ -128,14 +128,14 @@
#ifdef CONFIG_DEBUG_CAN
# define candbg dbg
# define canvdbg vdbg
# define caninfo info
# define canlldbg lldbg
# define canllvdbg llvdbg
# define canllinfo llinfo
#else
# define candbg(x...)
# define canvdbg(x...)
# define caninfo(x...)
# define canlldbg(x...)
# define canllvdbg(x...)
# define canllinfo(x...)
#endif
#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_CAN)
@ -730,7 +730,7 @@ static int can_recvsetup(FAR struct sam_can_s *priv)
priv->rxmbset |= (1 << mbndx);
canvdbg("CAN%d Mailbox %d: Index=%d rxmbset=%02x\n",
caninfo("CAN%d Mailbox %d: Index=%d rxmbset=%02x\n",
config->port, mbno, mbndx, priv->rxmbset);
/* Set up the message ID and filter mask
@ -798,7 +798,7 @@ static void can_reset(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllvdbg("CAN%d\n", config->port);
canllinfo("CAN%d\n", config->port);
UNUSED(config);
/* Get exclusive access to the CAN peripheral */
@ -855,7 +855,7 @@ static int can_setup(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllvdbg("CAN%d pid: %d\n", config->port, config->pid);
canllinfo("CAN%d pid: %d\n", config->port, config->pid);
/* Get exclusive access to the CAN peripheral */
@ -933,7 +933,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllvdbg("CAN%d\n", config->port);
canllinfo("CAN%d\n", config->port);
/* Get exclusive access to the CAN peripheral */
@ -972,7 +972,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
canllvdbg("CAN%d enable: %d\n", priv->config->port, enable);
canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the mailbox interrupts from all receive mailboxes */
@ -1005,7 +1005,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
canllvdbg("CAN%d enable: %d\n", priv->config->port, enable);
canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Get exclusive access to the CAN peripheral */
@ -1106,8 +1106,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
canllvdbg("CAN%d\n", priv->config->port);
canllvdbg("CAN%d ID: %d DLC: %d\n",
canllinfo("CAN%d\n", priv->config->port);
canllinfo("CAN%d ID: %d DLC: %d\n",
priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Get exclusive access to the CAN peripheral */
@ -1126,7 +1126,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
priv->txmbset |= (1 << mbndx);
canvdbg("Mailbox Index=%d txmbset=%02x\n", mbndx, priv->txmbset);
caninfo("Mailbox Index=%d txmbset=%02x\n", mbndx, priv->txmbset);
/* Set up the ID and mask, standard 11-bit or extended 29-bit.
* REVISIT: This logic should be capable of sending standard messages
@ -1788,7 +1788,7 @@ static int can_autobaud(struct sam_can_s *priv)
uint32_t regval;
int ret;
canllvdbg("CAN%d\n", config->port);
canllinfo("CAN%d\n", config->port);
/* The CAN controller can start listening to the network in Autobaud Mode.
* In this case, the error counters are locked and a mailbox may be
@ -1858,7 +1858,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
uint32_t mck;
int ret;
canllvdbg("CAN%d\n", config->port);
canllinfo("CAN%d\n", config->port);
/* Configure CAN pins */
@ -1970,7 +1970,7 @@ FAR struct can_dev_s *sam_caninitialize(int port)
FAR struct sam_can_s *priv;
FAR const struct sam_config_s *config;
canvdbg("CAN%d\n", port);
caninfo("CAN%d\n", port);
/* NOTE: Peripherical clocking for CAN0 and/or CAN1 was already provided
* by sam_clockconfig() early in the reset sequence.

26
arch/arm/src/sama5/sam_dmac.c
View file

@ -1920,7 +1920,7 @@ void sam_dmainitialize(struct sam_dmac_s *dmac)
void weak_function up_dmainitialize(void)
{
#ifdef CONFIG_SAMA5_DMAC0
dmallvdbg("Initialize DMAC0\n");
dmallinfo("Initialize DMAC0\n");
/* Enable peripheral clock */
@ -1940,7 +1940,7 @@ void weak_function up_dmainitialize(void)
#endif
#ifdef CONFIG_SAMA5_DMAC1
dmallvdbg("Initialize DMAC1\n");
dmallinfo("Initialize DMAC1\n");
/* Enable peripheral clock */
@ -2046,7 +2046,7 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
if (dmach)
{
dmavdbg("DMAC%d CH%d: chflags: %08x returning dmach: %p\n",
dmainfo("DMAC%d CH%d: chflags: %08x returning dmach: %p\n",
(int)dmacno, dmach->chan, (int)chflags, dmach);
}
else
@ -2082,13 +2082,13 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
dmach->flags = chflags;
#if defined(CONFIG_SAMA5_DMAC0) && defined(CONFIG_SAMA5_DMAC1)
dmavdbg("DMAC%d CH%d: chflags: %08x\n",
dmainfo("DMAC%d CH%d: chflags: %08x\n",
dmach->dmac, dmach->chan, (int)chflags);
#elif defined(CONFIG_SAMA5_DMAC0)
dmavdbg("DMAC0 CH%d: chflags: %08x\n",
dmainfo("DMAC0 CH%d: chflags: %08x\n",
dmach->chan, (int)chflags);
#else
dmavdbg("DMAC1 CH%d: chflags: %08x\n",
dmainfo("DMAC1 CH%d: chflags: %08x\n",
dmach->chan, (int)chflags);
#endif
}
@ -2110,7 +2110,7 @@ void sam_dmafree(DMA_HANDLE handle)
{
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
dmavdbg("dmach: %p\n", dmach);
dmainfo("dmach: %p\n", dmach);
DEBUGASSERT((dmach != NULL) && (dmach->inuse));
/* Mark the channel no longer in use. Clearing the inuse flag is an atomic
@ -2140,10 +2140,10 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@ -2219,10 +2219,10 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@ -2294,7 +2294,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
int ret = -EINVAL;
dmavdbg("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
dmainfo("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
DEBUGASSERT(dmach != NULL);
/* Verify that the DMA has been setup (i.e., at least one entry in the
@ -2338,7 +2338,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
irqstate_t flags;
dmavdbg("dmach: %p\n", dmach);
dmainfo("dmach: %p\n", dmach);
DEBUGASSERT(dmach != NULL);
flags = enter_critical_section();

12
arch/arm/src/sama5/sam_ehci.c
View file

@ -1928,7 +1928,7 @@ static int sam_async_setup(struct sam_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_ASYNCXFR, epinfo->epno, buflen);
#else
uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
uinfo("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
RHPORT(rhport), epinfo->epno, buffer, buflen, req);
#endif
@ -2206,7 +2206,7 @@ static int sam_intr_setup(struct sam_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_INTRXFR, epinfo->epno, buflen);
#else
uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
uinfo("RHport%d EP%d: buffer=%p, buflen=%d\n",
RHPORT(rhport), epinfo->epno, buffer, buflen);
#endif
@ -3187,7 +3187,7 @@ static int sam_ehci_tophalf(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@ -3730,7 +3730,7 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_EPALLOC, epdesc->addr, epdesc->xfrtype);
#else
uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
uinfo("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
epdesc->addr, epdesc->in ? "IN" : "OUT", hport->funcaddr,
epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
#endif
@ -4019,7 +4019,7 @@ static int sam_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_CTRLINOUT, RHPORT(rhport), req->req);
#else
uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
RHPORT(rhport), req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], len);
#endif
@ -4500,7 +4500,7 @@ static int sam_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

76
arch/arm/src/sama5/sam_emaca.c
View file

@ -725,7 +725,7 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
nllvdbg("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
@ -806,7 +806,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllvdbg("Disabling RX interrupts\n");
nllinfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@ -986,7 +986,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllvdbg("rxndx: %d\n", rxndx);
nllinfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1042,7 +1042,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1097,7 +1097,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1128,7 +1128,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
@ -1172,7 +1172,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllvdbg("rxndx: %d\n", priv->rxndx);
nllinfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1227,7 +1227,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1267,7 +1267,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1304,7 +1304,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllvdbg("ARP frame\n");
nllinfo("ARP frame\n");
/* Handle ARP packet */
@ -1449,7 +1449,7 @@ static int sam_emac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllvdbg("isr: %08x pending: %08x\n", isr, pending);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -1705,7 +1705,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
nllvdbg("Initialize the EMAC\n");
nllinfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -1737,11 +1737,11 @@ static int sam_ifup(struct net_driver_s *dev)
}
while (sam_linkup(priv) == 0);
nllvdbg("Link detected \n");
nllinfo("Link detected \n");
/* Enable normal MAC operation */
nllvdbg("Enable normal operation\n");
nllinfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -1825,7 +1825,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
nllvdbg("ifup: %d\n", priv->ifup);
nllinfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@ -2003,7 +2003,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2077,7 +2077,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2273,21 +2273,21 @@ static void sam_phydump(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAMA5_EMAC_RMII
nllvdbg("RMII Registers (Address %02x)\n", priv->phyaddr);
nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else /* defined(CONFIG_SAMA5_EMAC_MII) */
nllvdbg("MII Registers (Address %02x)\n", priv->phyaddr);
nllinfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
nllvdbg(" MCR: %04x\n", phyval);
nllinfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
nllvdbg(" MSR: %04x\n", phyval);
nllinfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
nllvdbg(" ADVERTISE: %04x\n", phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
nllvdbg(" LPR: %04x\n", phyval);
nllinfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
nllvdbg(" PHYSR: %04x\n", phyval);
nllinfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@ -2410,7 +2410,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
nllvdbg(" sam_phyreset\n");
nllinfo(" sam_phyreset\n");
/* Enable management port */
@ -2477,7 +2477,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllvdbg("Find a valid PHY address\n");
nllinfo("Find a valid PHY address\n");
/* Enable management port */
@ -2522,10 +2522,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@ -2684,7 +2684,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
@ -2693,14 +2693,14 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
nllvdbg(" Vendor Model Number: %04x\n",
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllvdbg(" Model Revision Number: %04x\n",
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
@ -2772,7 +2772,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg(" MCR: %04x\n", mcr);
nllinfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@ -2792,7 +2792,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
nllvdbg("AutoNegotiate complete\n");
nllinfo("AutoNegotiate complete\n");
break;
}
@ -2955,7 +2955,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
nllvdbg("Link is up\n");
nllinfo("Link is up\n");
linkup = true;
errout:
@ -3276,7 +3276,7 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
@ -3342,7 +3342,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@ -3388,7 +3388,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
nllvdbg("Entry\n");
nllinfo("Entry\n");
/* Enable clocking to the EMAC peripheral */

76
arch/arm/src/sama5/sam_emacb.c
View file

@ -1088,7 +1088,7 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
nllvdbg("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
@ -1169,7 +1169,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllvdbg("Disabling RX interrupts\n");
nllinfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
}
@ -1349,7 +1349,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllvdbg("rxndx: %d\n", rxndx);
nllinfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1405,7 +1405,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1460,7 +1460,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1491,7 +1491,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
nlldbg("ERROR: Buffer size %d; frame size %d\n",
@ -1535,7 +1535,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllvdbg("rxndx: %d\n", priv->rxndx);
nllinfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1590,7 +1590,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1630,7 +1630,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1667,7 +1667,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllvdbg("ARP frame\n");
nllinfo("ARP frame\n");
/* Handle ARP packet */
@ -1836,7 +1836,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllvdbg("isr: %08x pending: %08x\n", isr, pending);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -2390,7 +2390,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
nllvdbg("Initialize the EMAC\n");
nllinfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -2422,11 +2422,11 @@ static int sam_ifup(struct net_driver_s *dev)
}
while (sam_linkup(priv) == 0);
nllvdbg("Link detected \n");
nllinfo("Link detected \n");
/* Enable normal MAC operation */
nllvdbg("Enable normal operation\n");
nllinfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -2505,7 +2505,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
nllvdbg("ifup: %d\n", priv->ifup);
nllinfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@ -2758,7 +2758,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2831,7 +2831,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -3026,19 +3026,19 @@ static void sam_phydump(struct sam_emac_s *priv)
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
nllvdbg("%s Registers (Address %02x)\n",
nllinfo("%s Registers (Address %02x)\n",
priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
nllvdbg(" MCR: %04x\n", phyval);
nllinfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
nllvdbg(" MSR: %04x\n", phyval);
nllinfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
nllvdbg(" ADVERTISE: %04x\n", phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
nllvdbg(" LPR: %04x\n", phyval);
nllinfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
nllvdbg(" PHYSR: %04x\n", phyval);
nllinfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@ -3262,7 +3262,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
nllvdbg(" sam_phyreset\n");
nllinfo(" sam_phyreset\n");
/* Enable management port */
@ -3329,7 +3329,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllvdbg("Find a valid PHY address\n");
nllinfo("Find a valid PHY address\n");
/* Enable management port */
@ -3374,10 +3374,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, priv->attr->physr, &phyval);
nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@ -3556,7 +3556,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
@ -3565,15 +3565,15 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == priv->attr->msoui &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
(uint16_t)priv->attr->lsoui)
{
nllvdbg(" Vendor Model Number: %04x\n",
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllvdbg(" Model Revision Number: %04x\n",
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
@ -3645,7 +3645,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
goto errout;
}
nllvdbg(" MCR: %04x\n", mcr);
nllinfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@ -3665,7 +3665,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
nllvdbg("AutoNegotiate complete\n");
nllinfo("AutoNegotiate complete\n");
break;
}
@ -3828,7 +3828,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
nllvdbg("Link is up\n");
nllinfo("Link is up\n");
linkup = true;
errout:
@ -4012,7 +4012,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
else
#endif
{
nvdbg("ERROR: emac=%d\n", priv->attr->emac);
ninfo("ERROR: emac=%d\n", priv->attr->emac);
}
}
@ -4311,7 +4311,7 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
@ -4377,7 +4377,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@ -4423,7 +4423,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
nllvdbg("Entry\n");
nllinfo("Entry\n");
/* Enable clocking to the EMAC peripheral */

8
arch/arm/src/sama5/sam_freerun.c
View file

@ -138,7 +138,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
uint32_t cmr;
int ret;
tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
tcinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(freerun && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@ -154,7 +154,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
return ret;
}
tcvdbg("frequency=%lu, divisor=%u, cmr=%08lx\n",
tcinfo("frequency=%lu, divisor=%u, cmr=%08lx\n",
(unsigned long)frequency, (unsigned long)divisor,
(unsigned long)cmr);
@ -274,7 +274,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
leave_critical_section(flags);
tcvdbg("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
tcinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
(unsigned long)counter, (unsigned long)verify,
(unsigned long)overflow, (unsigned long)sr);
@ -294,7 +294,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
tcvdbg("usec=%llu ts=(%lu, %lu)\n",
tcinfo("usec=%llu ts=(%lu, %lu)\n",
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
return OK;

72
arch/arm/src/sama5/sam_gmac.c
View file

@ -656,7 +656,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
uint32_t regval;
uint32_t status;
nllvdbg("d_len: %d txhead: %d txtail: %d\n",
nllinfo("d_len: %d txhead: %d txtail: %d\n",
dev->d_len, priv->txhead, priv->txtail);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
@ -738,7 +738,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
nllvdbg("Disabling RX interrupts\n");
nllinfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_RCOMP);
}
@ -918,7 +918,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
nllvdbg("rxndx: %d\n", rxndx);
nllinfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & GMACRXD_ADDR_OWNER) != 0)
{
@ -974,7 +974,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the GMAC */
@ -1029,7 +1029,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Frame size from the GMAC */
dev->d_len = (rxdesc->status & GMACRXD_STA_FRLEN_MASK);
nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1060,7 +1060,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
* all of the data.
*/
nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
@ -1102,7 +1102,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllvdbg("rxndx: %d\n", priv->rxndx);
nllinfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1157,7 +1157,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllvdbg("IPv4 frame\n");
nllinfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1197,7 +1197,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllvdbg("Iv6 frame\n");
nllinfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1234,7 +1234,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllvdbg("ARP frame\n");
nllinfo("ARP frame\n");
/* Handle ARP packet */
@ -1377,7 +1377,7 @@ static int sam_gmac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_GMAC_IMR);
pending = isr & ~(imr | GMAC_INT_UNUSED);
nllvdbg("isr: %08x pending: %08x\n", isr, pending);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -1657,7 +1657,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the GMAC interface for normal operation. */
nllvdbg("Initialize the GMAC\n");
nllinfo("Initialize the GMAC\n");
sam_gmac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -1696,7 +1696,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Enable normal MAC operation */
nllvdbg("Enable normal operation\n");
nllinfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -1780,7 +1780,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
irqstate_t flags;
nllvdbg("ifup: %d\n", priv->ifup);
nllinfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@ -1958,7 +1958,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2032,7 +2032,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2220,21 +2220,21 @@ static void sam_phydump(struct sam_gmac_s *priv)
sam_enablemdio(priv);
nllvdbg("GMII Registers (Address %02x)\n", priv->phyaddr);
nllinfo("GMII Registers (Address %02x)\n", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
nllvdbg(" MCR: %04x\n", phyval);
nllinfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
nllvdbg(" MSR: %04x\n", phyval);
nllinfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ADVERTISE, &phyval);
nllvdbg(" ADVERTISE: %04x\n", phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_LPA, &phyval);
nllvdbg(" LPR: %04x\n", phyval);
nllinfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &phyval);
nllvdbg(" 1000BTCR: %04x\n", phyval);
nllinfo(" 1000BTCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &phyval);
nllvdbg(" 1000BTSR: %04x\n", phyval);
nllinfo(" 1000BTSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ESTATUS, &phyval);
nllvdbg(" ESTATUS: %04x\n", phyval);
nllinfo(" ESTATUS: %04x\n", phyval);
/* Disable management port */
@ -2418,7 +2418,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int timeout;
int ret;
nllvdbg(" sam_phyreset\n");
nllinfo(" sam_phyreset\n");
/* Enable management port */
@ -2480,7 +2480,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllvdbg("Find a valid PHY address\n");
nllinfo("Find a valid PHY address\n");
/* Enable management port */
@ -2523,7 +2523,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
}
@ -2683,7 +2683,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
goto errout;
}
nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
/* Read the LS bits of the OUI from Pthe PHYID2 register */
@ -2694,14 +2694,14 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
goto errout;
}
nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == GMII_OUI_MSB &&
(phyid2 & GMII_PHYID2_OUI_MASK) == GMII_OUI_LSB)
{
nllvdbg(" Vendor Model Number: %04x\n",
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
nllvdbg(" Model Revision Number: %04x\n",
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
}
else
@ -2777,7 +2777,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
goto errout;
}
nllvdbg(" MCR: 0x%X\n", phyval);
nllinfo(" MCR: 0x%X\n", phyval);
/* Wait for autonegotion to complete */
@ -2797,7 +2797,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
{
/* Yes.. break out of the loop */
nllvdbg("AutoNegotiate complete\n");
nllinfo("AutoNegotiate complete\n");
break;
}
@ -3324,7 +3324,7 @@ static void sam_macaddress(struct sam_gmac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
@ -3390,7 +3390,7 @@ static void sam_ipv6multicast(struct sam_gmac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@ -3436,7 +3436,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
{
uint32_t regval;
nllvdbg("Entry\n");
nllinfo("Entry\n");
/* Enable clocking to the GMAC peripheral */

18
arch/arm/src/sama5/sam_hsmci.c
View file

@ -1609,7 +1609,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was the error some kind of timeout? */
fllvdbg("ERROR: events: %08x SR: %08x\n",
fllinfo("ERROR: events: %08x SR: %08x\n",
priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@ -2090,7 +2090,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
/* Write the fully decorated command to CMDR */
fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET);
sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR);
return OK;
@ -2812,7 +2812,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
fvdbg("eventset: %02x\n", eventset);
finfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@ -2848,7 +2848,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
fvdbg("Register %p(%p)\n", callback, arg);
finfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@ -3095,7 +3095,7 @@ static void sam_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
flags = enter_critical_section();
@ -3153,7 +3153,7 @@ static void sam_callback(void *arg)
fdbg("ERROR: Failed to cancel work: %d\n", ret);
}
fllvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, 0);
if (ret < 0)
@ -3323,7 +3323,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
return NULL;
}
fvdbg("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
finfo("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
priv, priv->base, priv->hsmci, dmac, pid);
/* Initialize the HSMCI slot structure */
@ -3393,7 +3393,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
fllvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@ -3438,7 +3438,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
fvdbg("cdstatus: %02x\n", priv->cdstatus);
finfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}

2
arch/arm/src/sama5/sam_isi.c
View file

@ -160,7 +160,7 @@ int sam_isi_initialize(void)
*/
g_isi.actual = sam_pck_configure(ISI_PCKID, PCKSRC_MCK, CONFIG_ISI_MCKFREQ);
gvdbg("PCK%d frequency=%d actual=%d\n",
ginfo("PCK%d frequency=%d actual=%d\n",
ISI_PCKID, CONFIG_ISI_MCKFREQ, g_isi.actual);
/* Enable the MCK (output) */

44
arch/arm/src/sama5/sam_lcd.c
View file

@ -1101,7 +1101,7 @@ static void sam_wait_lcdstatus(uint32_t mask, uint32_t value)
static int sam_base_getvideoinfo(struct fb_vtable_s *vtable,
struct fb_videoinfo_s *vinfo)
{
gvdbg("vtable=%p vinfo=%p\n", vtable, vinfo);
ginfo("vtable=%p vinfo=%p\n", vtable, vinfo);
if (vtable && vinfo)
{
memcpy(vinfo, &g_base_videoinfo, sizeof(struct fb_videoinfo_s));
@ -1119,7 +1119,7 @@ static int sam_base_getvideoinfo(struct fb_vtable_s *vtable,
static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
struct fb_planeinfo_s *pinfo)
{
gvdbg("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
if (vtable && planeno == 0 && pinfo)
{
pinfo->fbmem = (void *)LAYER_BASE.framebuffer;
@ -1166,21 +1166,21 @@ static int sam_base_putcmap(struct fb_vtable_s *vtable,
static int sam_hcr_getcursor(struct fb_vtable_s *vtable,
struct fb_cursorattrib_s *attrib)
{
gvdbg("vtable=%p attrib=%p\n", vtable, attrib);
ginfo("vtable=%p attrib=%p\n", vtable, attrib);
if (vtable && attrib)
{
#ifdef CONFIG_FB_HWCURSORIMAGE
attrib->fmt = SAMA5_HCR_COLOR_FMT;
#endif
gvdbg("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
ginfo("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
attrib->pos = g_lcdc.cpos;
#ifdef CONFIG_FB_HWCURSORSIZE
attrib->mxsize.h = CONFIG_SAMA5_LCDC_HCR_HEIGHT;
attrib->mxsize.w = CONFIG_SAMA5_LCDC_HCR_WIDTH;
gvdbg("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
ginfo("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
attrib->size = g_lcdc.csize;
#endif
return OK;
@ -1199,26 +1199,26 @@ static int sam_hcr_getcursor(struct fb_vtable_s *vtable,
static int sam_hcr_setcursor(struct fb_vtable_s *vtable,
struct fb_setcursor_s *setttings)
{
gvdbg("vtable=%p setttings=%p\n", vtable, setttings);
ginfo("vtable=%p setttings=%p\n", vtable, setttings);
if (vtable && setttings)
{
gvdbg("flags: %02x\n", settings->flags);
ginfo("flags: %02x\n", settings->flags);
if ((flags & FB_CUR_SETPOSITION) != 0)
{
g_lcdc.cpos = settings->pos;
gvdbg("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
ginfo("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
}
#ifdef CONFIG_FB_HWCURSORSIZE
if ((flags & FB_CUR_SETSIZE) != 0)
{
g_lcdc.csize = settings->size;
gvdbg("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
ginfo("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
}
#endif
#ifdef CONFIG_FB_HWCURSORIMAGE
if ((flags & FB_CUR_SETIMAGE) != 0)
{
gvdbg("image: (h:%d, w:%d) @ %p\n",
ginfo("image: (h:%d, w:%d) @ %p\n",
settings->img.height, settings->img.width,
settings->img.image);
}
@ -1294,9 +1294,9 @@ static void sam_dmasetup(int lid, struct sam_dscr_s *dscr, uint8_t *buffer)
#if defined(CONFIG_DEBUG_GRAPHICS) && defined(CONFIG_DEBUG_INFO)
/* Dump the DMA setup */
gvdbg("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n",
ginfo("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n",
dscr->addr, dscr->ctrl, dscr->next);
gvdbg("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n",
ginfo("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n",
lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]),
sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid]));
#endif
@ -1379,7 +1379,7 @@ static int sam_setclut(struct sam_layer_s *layer,
unsigned int end;
int i;
gvdbg("layer=%d cmap=%p first=%d len=%d\n",
ginfo("layer=%d cmap=%p first=%d len=%d\n",
layer->lid, cmap, cmap->first, cmap->len);
DEBUGASSERT(layer && cmap);
@ -1460,7 +1460,7 @@ static int sam_getclut(struct sam_layer_s *layer,
uintptr_t regval;
int i;
gvdbg("layer=%d cmap=%p first=%d len=%d\n",
ginfo("layer=%d cmap=%p first=%d len=%d\n",
layer->lid, cmap, layer->offset, layer->nclut);
DEBUGASSERT(layer && cmap);
@ -1514,7 +1514,7 @@ static void sam_pio_config(void)
{
int i;
gvdbg("Configuring pins\n");
ginfo("Configuring pins\n");
/* Configure each pin */
@ -2915,7 +2915,7 @@ int up_fbinitialize(int display)
uint32_t regval;
#endif
gvdbg("Entry\n");
ginfo("Entry\n");
/* Configure layer layer structures, DMA descriptor memory, and
* framebuffers
@ -2931,7 +2931,7 @@ int up_fbinitialize(int display)
sam_pio_config();
gvdbg("Configuring the LCD controller\n");
ginfo("Configuring the LCD controller\n");
/* Enable the LCD peripheral clock */
@ -2959,7 +2959,7 @@ int up_fbinitialize(int display)
/* And turn the LCD on */
gvdbg("Enabling the display\n");
ginfo("Enabling the display\n");
sam_lcd_enable();
/* Display base layer */
@ -3012,7 +3012,7 @@ int up_fbinitialize(int display)
FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
{
gvdbg("vplane: %d\n", vplane);
ginfo("vplane: %d\n", vplane);
if (vplane == 0)
{
return (struct fb_vtable_s *)&g_base_vtable;
@ -3062,7 +3062,7 @@ void sam_lcdclear(nxgl_mxpixel_t color)
uint16_t *dest = (uint16_t *)LAYER_BASE.framebuffer;
int i;
gvdbg("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n",
ginfo("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n",
color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint16_t))
@ -3076,7 +3076,7 @@ void sam_lcdclear(nxgl_mxpixel_t color)
uint8_t b;
int i;
gvdbg("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n",
ginfo("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n",
color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
b = color & 0xff;
@ -3093,7 +3093,7 @@ void sam_lcdclear(nxgl_mxpixel_t color)
uint32_t *dest = (uint32_t *)LAYER_BASE.framebuffer;
int i;
gvdbg("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n",
ginfo("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n",
color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint32_t))

36
arch/arm/src/sama5/sam_nand.c
View file

@ -999,7 +999,7 @@ static uint32_t nand_nfc_poll(void)
sr = nand_getreg(SAM_HSMC_SR);
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
// fllvdbg("sr=%08x\n", sr);
// fllinfo("sr=%08x\n", sr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@ -1065,7 +1065,7 @@ static int hsmc_interrupt(int irq, void *context)
uint32_t pending = sr & imr;
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
fllvdbg("sr=%08x imr=%08x\n", sr, imr);
fllinfo("sr=%08x imr=%08x\n", sr, imr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@ -1233,7 +1233,7 @@ static int nand_wait_dma(struct sam_nandcs_s *priv)
}
}
fvdbg("Awakened: result=%d\n", priv->result);
finfo("Awakened: result=%d\n", priv->result);
priv->dmadone = false;
return priv->result;
}
@ -1293,7 +1293,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv,
DEBUGASSERT(priv->dma);
fvdbg("vsrc=%08x vdest=%08x nbytes=%d\n",
finfo("vsrc=%08x vdest=%08x nbytes=%d\n",
(int)vsrc, (int)vdest, (int)nbytes);
/* Initialize sampling */
@ -1463,7 +1463,7 @@ static int nand_nfcsram_read(struct sam_nandcs_s *priv, uint8_t *buffer,
int remaining;
int ret;
fvdbg("buffer=%p buflen=%d\n", buffer, buflen);
finfo("buffer=%p buflen=%d\n", buffer, buflen);
/* Get the offset data source address */
@ -1530,7 +1530,7 @@ static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
int buswidth;
int ret;
fvdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
/* Get the buswidth */
@ -1622,7 +1622,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
uint16_t sparesize;
int ret;
fvdbg("block=%d page=%d data=%p\n", (int)block, page, data);
finfo("block=%d page=%d data=%p\n", (int)block, page, data);
DEBUGASSERT(priv && data);
/* Get page and spare sizes */
@ -1765,7 +1765,7 @@ static int nand_nfcsram_write(struct sam_nandcs_s *priv, uint8_t *buffer,
uintptr_t dest;
int ret;
fvdbg("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
finfo("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
nand_dump("NFC SRAM Write", buffer, buflen);
/* Apply the offset to the destination address */
@ -1829,7 +1829,7 @@ static int nand_write(struct sam_nandcs_s *priv, uint8_t *buffer,
int buswidth;
int ret;
fvdbg("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
finfo("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
nand_dump("NAND Write", buffer, buflen);
/* Apply the offset to the destination address */
@ -1924,7 +1924,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
off_t coladdr;
int ret;
fvdbg("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
finfo("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
DEBUGASSERT(priv && (data || spare));
/* Get page and spare sizes */
@ -2038,7 +2038,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
int ret;
int i;
fvdbg("block=%d page=%d data=%p\n", (int)block, page, data);
finfo("block=%d page=%d data=%p\n", (int)block, page, data);
DEBUGASSERT(priv && data);
/* Make sure that we have exclusive access to the PMECC and that the PMECC
@ -2159,7 +2159,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
off_t rowaddr;
int ret = OK;
fvdbg("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
finfo("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
/* Get page and spare sizes */
@ -2320,7 +2320,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
unsigned int i;
int ret = 0;
fvdbg("block=%d page=%d data=%p\n", (int)block, page, data);
finfo("block=%d page=%d data=%p\n", (int)block, page, data);
DEBUGASSERT(priv && data);
/* Make sure that we have exclusive access to the PMECC and that the PMECC
@ -2344,7 +2344,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
/* Calculate physical address of the page */
rowaddr = block * nandmodel_pagesperblock(&priv->raw.model) + page;
fvdbg("pagesize=%d eccsaddr=%d rowaddr=%d\n", pagesize, eccsaddr, rowaddr);
finfo("pagesize=%d eccsaddr=%d rowaddr=%d\n", pagesize, eccsaddr, rowaddr);
#if 1 /* Use NFC SRAM */
/* Write the data area to NFC SRAM */
@ -2437,7 +2437,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
eccpersector = (pmecc_get_eccsize()) / sectersperpage;
eccsize = sectersperpage * eccpersector;
fvdbg("sectersperpage=%d eccpersector=%d eccsize=%d\n",
finfo("sectersperpage=%d eccpersector=%d eccsize=%d\n",
sectersperpage, eccpersector, eccsize);
#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
@ -2550,7 +2550,7 @@ static int nand_eraseblock(struct nand_raw_s *raw, off_t block)
DEBUGASSERT(priv);
fvdbg("block=%d\n", (int)block);
finfo("block=%d\n", (int)block);
/* Get exclusvie access to the HSMC hardware.
* REVISIT: The scope of this exclusivity is just NAND.
@ -2796,7 +2796,7 @@ static int nand_writepage(struct nand_raw_s *raw, off_t block,
static void nand_reset(struct sam_nandcs_s *priv)
{
fvdbg("Resetting\n");
finfo("Resetting\n");
nand_nfc_cleale(priv, 0, COMMAND_RESET, 0, 0, 0);
nand_wait_ready(priv);
}
@ -2834,7 +2834,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
uint8_t ecctype;
int ret;
fvdbg("CS%d\n", cs);
finfo("CS%d\n", cs);
/* Select the device structure (In SAMA5D3, NAND is only supported on CS3). */

Some files were not shown because too many files have changed in this diff Show more