Modify the kernel to use only atomic_xx and atomic64_xx interfaces,
avoiding the use of sizeof or typeof to determine the type of
atomic operations, thereby simplifying the kernel's atomic
interface operations.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.
To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.
However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.
About libcxx with CONFIG_LIBC_ARCH_ATOMIC, it still
does not work. It is also needed to call nx_atomic_ ver
instead of __atomic ver in
libcxx/include/__atomic/cxx_atomic_lmpl.h.
Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.
To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.
However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.
Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
kasan does not instrument the assembly function,
so it is checked in advance before calling.
If Kasan is not turned on, the speed and space will
be almost unchanged under compiler optimization.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Use address addition and subtraction, no longer as the return value of the address. Tags must be removed before calculation
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
gprof can analyze code hot spots based on scheduled sampling.
After adding the "-pg" parameter when compiling, you can view the code call graph.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
GOTPCRELX reloc available only for CONFIG_ARCH_ADDRENV=y
when CONFIG_ARCH_ADDRENV is not set, CONFIG_ARCH_TEXT_VBASE is not specified
so we can't relocate
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
we add ghs header file support using to fix the following link error:
[elxr] (error #412) unresolved symbols: 1
__sync_synchronize from libopenamp.a(io.o)
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Summary:
1.Modify the conditions for entering different include header files
2.Added pre-definition for _Atomic _Bool when it is missing
3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
The ELF loader needs to load the app into the memory before
executing it from the same location. As expected, this memory space
should be able to execute code. For architectures containing data
and instruction buses, the instruction bus may not be able to be
accessed in a non-aligned way, which is usually required when
copying data to that location. Eventually, this same memory space
can be accessed through the data bus, using different address
ranges. This commit enables accessing the memory through the data
bus to copy the app's data before executing it when
`CONFIG_ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ` is enabled.
This applies uintreg_t in risc-v commons and fixes araised ci issues
for multiple devices. The FLAT build runs on qemu-rv64ilp32 target.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
As pointed out in #11322 there is a hardware design issue in RISC-V that
affects RV64 relocations. The problem is with how address bits are loaded
into registers via lui / auipc and sign extension.
If the hi20 relocation value happens to have its 32-bit sign bit set, i.e.
value is 0x80000000 (but not negative! i.e. negative in 64-bit format) the
relocation will fail, as the address is erroneously sign extended:
0x00000000_80000000 becomes 0xffffffff_80000000 which is not correct.
Also, make sure the correct opcode is used with PCREL_HI20, it expects
AUIPC (not LUI). The C compiler will never emit such code but when hand-
writing assembly code this can happen.
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
